Pixel circuit and driving method thereof, display panel, and display device

Abstract

A pixel circuit (10), a driving method thereof, a display panel, and a display device, are provided. In the pixel circuit (10), a control terminal (113) of a driving circuit (110) and a memory circuit (140) are connected to a first node (P1), and a first light-emitting control circuit (150) and a first terminal (111) of the driving circuit (110) are connected to a second node (P2). The driving method for the pixel circuit 10 includes the steps of: before a data writing stage, turning on the first reset circuit 160 to apply a first reset voltage to the control end 113 of the driving circuit 110 to reset the first node P1; turning on the first light-emitting control circuit 150 to apply a first voltage to the first end 111 of the driving circuit 110 to reset the second node P2; during a data writing stage, turning on the data writing circuit 120 to write a data signal to the first end 111 of the driving circuit 110; and during a light-emitting stage, turning on the first light-emitting control circuit 150 to cause the light-emitting element 170 to emit light according to the driving current. This method can reduce or eliminate the influence of residual charge on the data writing accuracy and the anode potential of the light-emitting device during the light-emitting stage, thereby optimizing the display effect.

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application filed on August 23, 2022, bearing application number 202211012901.3, the entire contents of which are incorporated herein by reference. The embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, a display panel, and a display device. [Background technology]

[0002] Organic light-emitting diode (OLED) display devices have been gaining attention due to their advantages of wide viewing angles, high contrast, fast response speed, higher luminance, and lower driving voltage compared to inorganic light-emitting display devices. Due to these characteristics, OLEDs can be applied to devices with display functions such as mobile phones, displays, laptops, digital cameras, instruments, and meters.

[0003] Pixel circuits in OLED displays generally employ a matrix drive system. Depending on whether switching elements are incorporated into each pixel, they can be divided into active matrix (AM) and passive matrix (PM) drive systems. PMOLEDs are simple to process and low cost, but suffer from drawbacks such as crosstalk, high power consumption, and short lifespan, making them inadequate for high-resolution and large-screen displays. In contrast, AMOLEDs integrate a thin-film transistor (TFT) and storage capacitor into each pixel's pixel circuit, driving and controlling the TFT and storage capacitor to control the current flowing through the OLED, causing it to emit light as needed. Compared to PMOLEDs, AMOLEDs have lower drive current, lower power consumption, and longer lifespan, making them more suitable for high-resolution, multi-grayscale, large-screen displays. At the same time, AMOLEDs offer distinct advantages in viewing angle, color reproduction, power consumption, and response time, making them suitable for high-information-content, high-resolution displays. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a method for driving a pixel circuit, the pixel circuit including a driving circuit, a data writing circuit, a threshold compensation circuit, a memory circuit, a first light-emitting control circuit, and a first reset circuit. the driving circuit includes a control end, a first end, and a second end and is configured to control a driving current flowing through the light-emitting element; the data writing circuit is connected to the first end of the driving circuit and configured to write a data signal to the first end of the driving circuit in response to a first scanning signal; the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit and configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal; the memory circuit is connected to the control end of the driving circuit and a first voltage line and configured to store the compensation signal and hold the compensation signal at the control end of the driving circuit; the first light-emitting control circuit is connected to the first voltage line and the first end of the driving circuit and configured to apply a first voltage provided by the first voltage line to the first end of the driving circuit in response to a first light-emitting control signal; and the first reset circuit is connected to the threshold compensation circuit and configured to apply a first reset voltage to the control end of the driving circuit in response to a first reset signal. The control end of the driving circuit and the memory circuit are connected to a first node, and the first light-emitting control circuit and the first end of the driving circuit are connected to a second node. The method includes, before a data writing step, the steps of making the first reset circuit conductive in response to the first reset signal and applying the first reset voltage to the control end of the driving circuit to reset the first node, making the first light-emitting control circuit conductive in response to the first light-emitting control signal and applying the first voltage to the first end of the driving circuit to reset the second node, making the data writing circuit conductive in response to the first scan signal and writing the data signal to the first end of the driving circuit in the data writing step, and making the first light-emitting control circuit conductive in response to the first light-emitting control signal and causing the light-emitting element to emit light in accordance with the driving current in the light-emitting step.

[0005] For example, in a method provided by one embodiment of the present disclosure, the step of making the first reset circuit conductive in response to the first reset signal and applying the first reset voltage to the control end of the driving circuit to reset the first node includes the step of making the first reset circuit conductive in response to the first reset signal, making the threshold compensation circuit conductive in response to the second scanning signal, and applying the first reset voltage to the control end of the driving circuit through a path formed by the first reset circuit and the threshold compensation circuit to reset the first node.

[0006] For example, in a method provided by an embodiment of the present disclosure, the pixel circuit further includes a second light-emitting control circuit and a second reset circuit, the second light-emitting control circuit is connected to the second end of the driving circuit and the light-emitting element and configured to apply a voltage at the second end of the driving circuit to the light-emitting element in response to a second light-emitting control signal, the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element and configured to apply a second reset voltage to the light-emitting element in response to a second reset signal, the second light-emitting control circuit and the second end of the driving circuit are connected to a third node, and the second reset circuit, the second light-emitting control circuit and the light-emitting element are connected to a fourth node. The method further includes, before the data writing step, the first reset circuit resets the first node and simultaneously applies the first reset voltage to the second end of the driving circuit to reset the third node, and / or, before the data writing step, the second reset circuit is turned on in response to the second reset signal to apply the second reset voltage to the light-emitting element to reset the fourth node.

[0007] For example, in a method provided by an embodiment of the present disclosure, before the data writing step, the first node and the second node are reset simultaneously or at different time periods, respectively.

[0008] For example, in a method provided by an embodiment of the present disclosure, if the third node and the fourth node are both reset before the data writing step, the third node and the fourth node may be reset simultaneously or at different periods.

[0009] For example, in a method provided by one embodiment of the present disclosure, before the data writing step, a reset period of at least one of the third node and the fourth node overlaps with a reset period of at least one of the first node and the second node.

[0010] For example, in a method provided by an embodiment of the present disclosure, before the data writing step, the reset period of the first node, the reset period of the second node, the reset period of the third node, and the reset period of the fourth node do not overlap.

[0011] For example, in a method provided by one embodiment of the present disclosure, after the data writing step and before the light emitting step, the first light emitting control circuit may be made conductive in response to the first light emitting control signal, applying the first voltage to the first end of the driving circuit to reset the second node; and / or after the data writing step and before the light emitting step, the first reset circuit may be made conductive in response to the first reset signal, applying a first reset voltage to the second end of the driving circuit to reset the third node; and / or after the data writing step and before the light emitting step, the second reset circuit may be made conductive in response to the second reset signal, applying the second reset voltage to the light emitting element to reset the fourth node.

[0012] For example, in a method provided by one embodiment of the present disclosure, after the data writing step and before the light emitting step, at least two nodes among the second node, the third node, and the fourth node are reset simultaneously or at different periods.

[0013] For example, in a method provided by one embodiment of the present disclosure, the driving circuit includes a driving transistor, the data writing circuit includes a data writing transistor, the threshold compensation circuit includes a threshold compensation transistor, the first light-emitting control circuit includes a first light-emitting control transistor, and the first reset circuit includes a first reset transistor, wherein the driving transistor, the data writing transistor, the first light-emitting control transistor, and the first reset transistor are transistors of a first type, and the threshold compensation transistor is a transistor of a second type different from the first type.

[0014] For example, in a method provided by one embodiment of the present disclosure, the first type transistor includes a P-type thin film transistor, and the second type transistor includes an N-type thin film transistor.

[0015] For example, in a method provided by one embodiment of the present disclosure, the pixel circuit further includes a leakage prevention circuit connected to the control end of the driving circuit, the threshold compensation circuit, and the memory circuit, and the leakage prevention circuit is configured to suppress leakage of the control end of the driving circuit.

[0016] For example, in a method provided by an embodiment of the present disclosure, the leakage protection circuit includes a leakage protection transistor, which is the second type of transistor.

[0017] At least one embodiment of the present disclosure further provides a pixel circuit including a driving circuit, a data writing circuit, a threshold compensation circuit, a memory circuit, and a first reset circuit, wherein the driving circuit includes a control end, a first end, and a second end and is configured to control a driving current flowing through a light-emitting element, the data writing circuit is connected to the first end of the driving circuit and configured to write a data signal to the first end of the driving circuit in response to a first scanning signal, the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit and configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal, the memory circuit is connected to the control end of the driving circuit and a first voltage line and configured to store the compensation signal and hold the compensation signal at the control end of the driving circuit, the control end of the driving circuit and the memory circuit are connected to a first node, and the first reset circuit is connected to the threshold compensation circuit and the second end of the driving circuit and configured to apply a first reset voltage to the second end of the driving circuit in response to a first reset signal.

[0018] For example, in a pixel circuit provided by one embodiment of the present disclosure, the driving circuit includes a driving transistor having a gate electrode used as a control end of the driving circuit, a first pole used as a first end of the driving circuit, and a second pole used as a second end of the driving circuit; the data writing circuit includes a data writing transistor having a gate electrode connected to a first scan line to receive the first scanning signal, a first pole connected to a data line to receive the data signal, and a second pole connected to the first pole of the driving transistor; and the threshold compensation circuit includes a threshold compensation transistor having a gate electrode connected to a second scan line to receive the second scanning signal, a first pole connected to the second pole of the driving transistor, and a second pole connected to the gate electrode of the driving transistor. The memory circuit includes a storage capacitor having a first pole connected to the first voltage line and a second pole connected to a gate electrode of the drive transistor, and the first reset circuit includes a first reset transistor having a gate electrode connected to a first reset line to receive the first reset signal, a first electrode connected to a first reset voltage line to receive the first reset voltage, and a second pole connected to a second pole of the drive transistor.

[0019] For example, a pixel circuit provided by one embodiment of the present disclosure further includes a first light-emitting control circuit and a second light-emitting control circuit, wherein the first light-emitting control circuit is connected to the first voltage line and a first end of the drive circuit and is configured to apply a first voltage provided by the first voltage line to the first end of the drive circuit in response to a first light-emitting control signal, the first light-emitting control circuit and the first end of the drive circuit are connected to a second node, the second light-emitting control circuit is connected to the second end of the drive circuit and the light-emitting element and applies a voltage at the second end of the drive circuit to the light-emitting element in response to a second light-emitting control signal, and the second light-emitting control circuit and the second end of the drive circuit are connected to a third node.

[0020] For example, in a pixel circuit provided by an embodiment of the present disclosure, the first light-emitting control circuit includes a first light-emitting control transistor having a gate electrode connected to a first light-emitting control line to receive the first light-emitting control signal, a first pole connected to the first voltage line, and a second pole connected to a first end of the driving circuit, and the second light-emitting control circuit includes a second light-emitting control transistor having a gate electrode connected to the second light-emitting control line to receive the second light-emitting control signal, a first pole connected to the second end of the driving circuit, and a second pole connected to the light-emitting element.

[0021] For example, a pixel circuit provided by one embodiment of the present disclosure further includes a second reset circuit, the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element, and is configured to apply a second reset voltage to the light-emitting element in response to a second reset signal, the second reset circuit, the second light-emitting control circuit, and the light-emitting element are connected to a fourth node, and the potential of the third node after being reset by the first reset circuit is higher than the potential of the fourth node after being reset by the second reset circuit.

[0022] For example, in a pixel circuit provided by one embodiment of the present disclosure, the second reset circuit includes a second reset transistor having a gate electrode connected to a second reset line to receive the second reset signal, a first pole connected to a second reset voltage line to receive the second reset voltage, and a second pole connected to the second pole of the second light-emitting control transistor and the light-emitting element.

[0023] For example, a pixel circuit provided by one embodiment of the present disclosure further includes a third reset circuit connected to the threshold compensation circuit and the control end of the driving circuit, and configured to apply a third reset voltage to the control end of the driving circuit in response to a third reset signal, wherein the potential of the first node after being reset by the third reset circuit is lower than the potential of the third node after being reset by the first reset circuit and is equal to or lower than the potential of the fourth node after being reset by the second reset circuit.

[0024] For example, in a pixel circuit provided by an embodiment of the present disclosure, the third reset circuit includes a third reset transistor having a gate electrode connected to a third reset line to receive the third reset signal, a first electrode connected to a third reset voltage line to receive the third reset voltage, and a second electrode connected to a control end of the driving circuit.

[0025] For example, a pixel circuit provided by an embodiment of the present disclosure further includes a fourth reset circuit connected to a first end of the driving circuit and configured to apply a fourth reset voltage to the first end of the driving circuit in response to a fourth reset signal, wherein the potential of the second node after being reset by the fourth reset circuit is higher than the potential of the first node after being reset by the third reset circuit, higher than the potential of the third node after being reset by the first reset circuit, and higher than the potential of the fourth node after being reset by the second reset circuit.

[0026] For example, in a pixel circuit provided by an embodiment of the present disclosure, the fourth reset circuit includes a fourth reset transistor having a gate electrode connected to a fourth reset line to receive the fourth reset signal, a first electrode connected to a fourth reset voltage line to receive the fourth reset voltage, and a second electrode connected to a first end of the driving circuit.

[0027] At least one embodiment of the present disclosure further provides a display panel including a plurality of pixel units, each including a pixel circuit provided by any of the embodiments of the present disclosure.

[0028] At least one embodiment of the present disclosure further provides a display device including a display panel provided by any embodiment of the present disclosure. [Brief explanation of the drawings]

[0029] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0030] [Figure 1A] FIG. 1A is a schematic diagram of a 2T1C pixel circuit. [Figure 1B] FIG. 1B is a schematic diagram of another 2T1C pixel circuit. [Figure 2] FIG. 2 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure. [Figure 3] FIG. 3 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. [Figure 4] FIG. 4 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. [Figure 5] FIG. 5 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. [Figure 6] FIG. 6 is a schematic flowchart of a method for driving a pixel circuit provided by some embodiments of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. [Figure 8] FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. [Figure 9] FIG. 9 is a timing diagram of the first voltage provided by some embodiments of the present disclosure. [Figure 10] FIG. 10 is another timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. [Figure 11] FIG. 11 is another timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. [Figure 12] FIG. 12 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. [Figure 13]FIG. 13 is a timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. [Figure 14] FIG. 14 is another timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. [Figure 15] FIG. 15 is another timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. [Figure 16] FIG. 16 is another timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. [Figure 17] FIG. 17 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. [Figure 18] FIG. 18 is a timing diagram of the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure. [Figure 19] FIG. 19 is another timing diagram of the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure. [Figure 20] FIG. 20 is another timing diagram of the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure. [Figure 21] FIG. 21 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. [Figure 22] FIG. 22 is a timing diagram of the pixel circuit shown in FIG. 21 provided by some embodiments of the present disclosure. [Figure 23] FIG. 23 is a schematic diagram of a circuit structure of a pixel circuit provided by some embodiments of the present disclosure. [Figure 24] FIG. 24 is a timing diagram of the pixel circuit shown in FIG. 23 provided by some embodiments of the present disclosure. [Figure 25] FIG. 25 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure. [Figure 26] FIG. 26 is a schematic block diagram of a display device provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0031] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure, the words "first," "second," and similar words do not denote any order, quantity, or importance, but are used only to distinguish between different components. Similarly, similar words such as "one," "an," or "the" do not denote a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "comprise" or "containing" mean that the element or thing preceding the word includes the elements or things listed thereafter and their equivalents, without excluding other elements or things. Words such as "connect" or "coupled" are not limited to physical or mechanical connections, but can include direct or indirect electrical connections. Terms such as "top," "bottom," "left," and "right" are used to express relative positions, and if the absolute position of the described object changes, the relative positions may also change.

[0033] The basic pixel circuit used in AMOLED displays is typically a 2T1C pixel circuit, which uses two thin-film transistors (TFTs) and a storage capacitor Cs to achieve the basic function of driving the OLED to emit light. Figures 1A and 1B show schematic diagrams of two types of 2T1C pixel circuits, respectively.

[0034] As shown in FIG. 1A, the 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs. For example, the gate electrode of the switching transistor T0 is connected to a scan line to receive a scan signal Scan1, for example, the source electrode is connected to a data line to receive a data signal Vdata, and the drain electrode is connected to the gate electrode of the driving transistor N0. The source electrode of the driving transistor N0 is connected to a first voltage terminal to receive a first voltage Vdd (for example, a high voltage), and the drain electrode is connected to the anode of the OLED. One end of the storage capacitor Cs is connected to the drain electrode of the switching transistor T0 and the gate electrode of the driving transistor N0, and the other end is connected to the source electrode of the driving transistor N0 and the first voltage terminal. The cathode of the OLED is connected to a second voltage terminal to receive a second voltage Vss (a low voltage, for example, ground voltage).

[0035] The driving method of this 2T1C pixel circuit is to control the brightness (grayscale) of the pixel using two TFTs and a storage capacitor Cs. When a scan signal Scan1 is applied through a scan line to turn on the switching transistor T0, a data signal Vdata sent from the data driving circuit through the data line charges the storage capacitor Cs through the switching transistor T0, and the data signal Vdata is stored in the storage capacitor Cs. The stored data signal Vdata controls the conductivity of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to cause the OLED to emit light. In other words, this current determines the grayscale of the pixel when it emits light. In the 2T1C pixel circuit shown in Figure 1A, the switching transistor T0 is an N-type transistor, while the driving transistor N0 is a P-type transistor.

[0036] As shown in FIG. 1B, another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection method is slightly modified, with the driving transistor N0 being an N-type transistor. The changes in the pixel circuit of FIG. 1B compared to FIG. 1A include that the anode of the OLED is connected to a first voltage terminal to receive a first voltage Vdd (e.g., a high voltage), the cathode is connected to the drain electrode of the driving transistor N0, and the source electrode of the driving transistor N0 is connected to a second voltage terminal to receive a second voltage Vss (a low voltage, e.g., a ground voltage). One end of the storage capacitor Cs is connected to the drain electrode of the switching transistor T0 and the gate electrode of the driving transistor N0, and the other end is connected to the source electrode of the driving transistor N0 and the second voltage terminal. The operation mode of this 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, so it will not be repeated here.

[0037] Furthermore, in the pixel circuits shown in Figures 1A and 1B, the switching transistor T0 is not limited to an N-type transistor and may be a P-type transistor, and the polarity of the scanning signal Scan1 that controls its conduction or cut-off can be changed accordingly.

[0038] An OLED display device generally includes a plurality of pixel units arranged in an array, each of which may include, for example, the pixel circuit described above. In an OLED display device, the threshold voltage of the drive transistor of each pixel circuit varies depending on the manufacturing process, and the threshold voltage of the drive transistor may drift due to factors such as temperature changes. Therefore, if the threshold voltages of the drive transistors vary, display defects (e.g., display unevenness) may occur, and therefore the threshold voltages must be compensated. At the same time, when the transistors are in the off state, display defects may occur due to the presence of leakage current.

[0039] Therefore, based on the above-mentioned basic 2T1C pixel circuit, the industry also provides other pixel circuits with compensation functions that can be realized by voltage compensation, current compensation, or mixed compensation. Pixel circuits with compensation functions include, for example, 4T1C and 4T2C, which will not be described in detail here.

[0040] In current pixel circuits, especially those used in display screens (e.g., mobile phones, watches, etc.), residual charges exist during the working process before data is written and before light is emitted. These residual charges affect circuit performance, affect the accuracy of data writing, and affect the potential of the anode of the light-emitting device during the light-emitting stage, and this adverse effect is particularly noticeable after changing the frequency.

[0041] At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device, which can reduce or eliminate the influence of residual charges on the data writing accuracy and the anode potential of a light-emitting device during the light-emitting stage, thereby optimizing the display effect.

[0042]

[0023] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which it should be noted that the same reference numerals in different drawings are used to refer to the same illustrated elements.

[0043] At least one embodiment of the present disclosure provides a method for driving a pixel circuit. The pixel circuit includes a drive circuit, a data write circuit, a threshold compensation circuit, a memory circuit, a first light-emitting control circuit, and a first reset circuit. The drive circuit includes a control end, a first end, and a second end and is configured to control a drive current flowing through a light-emitting element. The data write circuit is connected to the first end of the drive circuit and configured to write a data signal to the first end of the drive circuit in response to a first scanning signal. The threshold compensation circuit is connected between the control end of the drive circuit and the second end of the drive circuit and configured to write a compensation signal based on the data signal to the control end of the drive circuit in response to a second scanning signal. The memory circuit is connected to the control end of the drive circuit and a first voltage line and configured to store the compensation signal and hold it at the control end of the drive circuit. The first light-emitting control circuit is connected to the first voltage line and the first end of the drive circuit and configured to apply a first voltage provided by the first voltage line to the first end of the drive circuit in response to a first light-emitting control signal. The first reset circuit is connected to the threshold compensation circuit and configured to apply a first reset voltage to a control end of the driving circuit in response to a first reset signal. The control end of the driving circuit and the memory circuit are connected to a first node, and the first light-emitting control circuit and the first end of the driving circuit are connected to a second node. A driving method for the pixel circuit includes, before a data writing step, making the first reset circuit conductive in response to the first reset signal to apply a first reset voltage to the control end of the driving circuit to reset the first node, making the first light-emitting control circuit conductive in response to a first light-emitting control signal to apply a first voltage to the first end of the driving circuit to reset the second node, making the data writing circuit conductive in response to a first scan signal to write a data signal to the first end of the driving circuit, and making the light-emitting element emit light in response to a driving current in the light-emitting step.

[0044] 2 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure. A driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG.

[0045] As shown in FIG. 2, the pixel circuit 10 includes a drive circuit 110, a data write circuit 120, a threshold compensation circuit 130, a memory circuit 140, a first light-emitting control circuit 150, and a first reset circuit 160.

[0046] For example, the driving circuit 110 includes a first end 111, a second end 112, and a control end 113, and is configured to control a driving current flowing through the light emitting element 170. For example, in a light emitting stage, the driving circuit 110 supplies a driving current to the light emitting element 170 to drive the light emitting element 170 to emit light and to emit light according to a required "grayscale." For example, the light emitting element 170 may employ any type of suitable device, including multiple structures that can be selected and arranged according to actual needs, and the embodiments of the present disclosure are not limited thereto. For example, the light emitting element 170 may be an OLED, a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), etc., and can be determined according to actual needs.

[0047] The data writing circuit 120 is connected to the first end 111 of the driving circuit 110 and is configured to write a data signal to the first end 111 of the driving circuit 110 in response to a first scan signal. For example, the data writing circuit 120 is connected to a first scan line SC1 for providing the first scan signal and a data line Vdata for providing a data signal. In a data writing phase, the data writing circuit 120 is turned on in response to the first scan signal provided by the first scan line SC1, thereby writing the data signal provided by the data line Vdata to the first end 111 of the driving circuit 110. Furthermore, the data signal is written to the control end 113 of the driving circuit 110 via the driving circuit 110 and the threshold compensation circuit 130 and stored in the memory circuit 140. In a light emitting phase, a driving current is generated according to the data signal to drive the light emitting element 170 to emit light.

[0048] The threshold compensation circuit 130 is connected between the control end 113 of the driving circuit 110 and the second end 112 of the driving circuit 110, and is configured to write a compensation signal based on the data signal to the control end 113 of the driving circuit 110 in response to the second scanning signal. For example, the threshold compensation circuit 130 may be directly connected to the control end 113 and the second end 112 of the driving circuit 110, i.e., directly connected between the control end 113 and the second end 112 of the driving circuit 110. Of course, the threshold compensation circuit 130 may also be indirectly connected between the control end 113 and the second end 112 of the driving circuit 110, i.e., between the threshold compensation circuit 130 and the control end 113 of the driving circuit 110. Other circuits (e.g., a leakage prevention circuit 230, which will be described later) may be provided between the threshold compensation circuit 130 and the second end 112 of the driving circuit 110, and the embodiments of the present disclosure are not limited thereto.

[0049] For example, the threshold compensation circuit 130 is connected to the second scan line SC2 for providing the second scan signal. When the first scan signal provided by the first scan line SC1 and the second scan signal provided by the second scan line SC2 are both at an active level, the data write circuit 120 and the threshold compensation circuit 130 are both turned on. At this time, the driving circuit 110 is also turned on, and a data signal is transmitted to the threshold compensation circuit 130 via the data write circuit 120 and the driving circuit 110. The threshold compensation circuit 130 generates a compensation signal based on the data signal and writes the compensation signal to the control end 113 of the driving circuit 110. For example, in the data write phase, the threshold compensation circuit 130 can electrically connect the control end 113 and the second end 112 of the driving circuit 110, so that relevant information about the threshold voltage of the driving circuit 110 is also stored in the memory circuit 140. Therefore, in the light emitting phase, the data signal and the stored voltage including the threshold voltage can be used to control the driving circuit 110, so that the driving circuit 110 can be compensated.

[0050] The memory circuit 140 is connected to the control end 113 of the driving circuit 110 and the first voltage line VDD, and is configured to store the compensation signal and hold the compensation signal at the control end 113 of the driving circuit 110.

[0051] The first light-emitting control circuit 150 is connected to the first voltage line VDD and the first end 111 of the drive circuit 110 and is configured to apply a first voltage provided by the first voltage line VDD to the first end 111 of the drive circuit 110 in response to a first light-emitting control signal. For example, the first light-emitting control circuit 150 is connected to the first light-emitting control line EM1, which is used to provide the first light-emitting control signal. The first light-emitting control circuit 150 is turned on in response to the first light-emitting control signal, and the first end 111 of the drive circuit 110 is electrically connected to the first voltage line VDD, thereby applying the first voltage provided by the first voltage line VDD to the first end 111 of the drive circuit 110.

[0052] The first reset circuit 160 is connected to the threshold compensation circuit 130 and configured to apply a first reset voltage to the control end 113 of the drive circuit 110 in response to a first reset signal. For example, the first reset circuit 160 is connected to a first reset line RST1 for providing the first reset signal and a first reset voltage line VR1 for supplying the first reset voltage. The first reset circuit 160 is turned on in response to the first reset signal and transmits the first reset voltage to the second end 112 of the drive circuit 110, which is then transmitted to the control end 113 of the drive circuit 110 via the threshold compensation circuit 130, thereby resetting the control end 113 of the drive circuit 110.

[0053] The anode of the light emitting element 170 receives the driving current provided by the driving circuit 110, and the cathode of the light emitting element 170 is connected to a second voltage line VSS for providing a second voltage.

[0054] For the purpose of explanation, the first voltage line VDD in each embodiment of the present disclosure continues to receive, for example, a high-level DC signal, and this high-level DC is referred to as the first voltage, and the second voltage line VSS continues to receive, for example, a low-level DC signal, and this low-level DC is referred to as the second voltage (which may be a ground voltage) and is lower than the first voltage. The following embodiments are the same, so they will not be described repeatedly.

[0055] For example, in some examples, the pixel circuit 10 further includes a second light-emitting control circuit 180 and a second reset circuit 190.

[0056] The second light-emitting control circuit 180 is connected to the second end 112 of the drive circuit 110 and the light-emitting element 170, and is configured to apply the voltage at the second end 112 of the drive circuit 110 to the light-emitting element 170 in response to a second light-emitting control signal. For example, the second light-emitting control circuit 180 is connected to a second light-emitting control line EM2 for providing the second light-emitting control signal. The second light-emitting control circuit 180 can be turned on in response to the second light-emitting control signal to electrically connect the second end 112 of the drive circuit 110 to the light-emitting element 170 (e.g., the anode of the light-emitting element 170), thereby applying the voltage at the second end 112 of the drive circuit 110 to the light-emitting element 170.

[0057] The second reset circuit 190 is connected to the second light-emitting control circuit 180 and the light-emitting element 170, and is configured to apply the second reset voltage to the light-emitting element 170 (e.g., the anode of the light-emitting element 170) in response to the second reset voltage. For example, the second reset circuit 190 is connected to a second reset line RST2 for providing a second reset signal and a second reset voltage line VR2 for supplying the second reset signal. The second reset circuit 190 is turned on in response to the second reset signal, and transmits the second reset voltage to the connection between the second light-emitting control circuit 180 and the light-emitting element 170 to reset the light-emitting element 170.

[0058] For example, the control end 113 of the driving circuit 110 and the memory circuit 140 are connected to a first node P1, the first light-emitting control circuit 150 and the first end 111 of the driving circuit 110 are connected to a second node P2, the second light-emitting control circuit 180 and the second end 112 of the driving circuit 110 are connected to a third node P3, and the second reset circuit 190, the second light-emitting control circuit 180, and the light-emitting element 170 are connected to a fourth node P4. For example, the potential of the third node P3 after being reset by the first reset circuit 160 is higher than the potential of the fourth node P4 after being reset by the second reset circuit 190. This provides a better reset effect and can better reduce or eliminate the influence of residual charges on the anode potential of the light-emitting device during the light-emitting stage.

[0059] 3 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. A driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG.

[0060] 3, in some examples, the pixel circuit 10 may further include a third reset circuit 210. The third reset circuit 210 is connected to the threshold compensation circuit 130 and the control end 113 of the drive circuit 110 and is configured to apply a third reset voltage to the control end 113 of the drive circuit 110 in response to a third reset signal. For example, the third reset circuit 210 is connected to a third reset line RST3 for providing the third reset signal and a third reset voltage line VR3 for supplying the third reset signal. The third reset circuit 210 is turned on in response to the third reset signal and transmits the third reset voltage to the control end 113 of the drive circuit 110 to reset the control end 113 of the drive circuit 110. Other parts of the pixel circuit 10 are basically the same as those of the pixel circuit 10 shown in FIG. 2, and therefore will not be described again here.

[0061] For example, in this example, the potential of the third node P3 after being reset by the first reset circuit 160 is higher than the potential of the fourth node P4 after being reset by the second reset circuit 190, and the potential of the first node P1 after being reset by the third reset circuit 210 is lower than the potential of the third node P3 after being reset by the first reset circuit 160 and is equal to or lower than the potential of the fourth node P4 after being reset by the second reset circuit 190. This provides a better reset effect and can better reduce or eliminate the influence of residual charges on the accuracy of data writing and the potential of the anode of the light-emitting device during the light-emitting stage.

[0062] 4 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. A driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG.

[0063] 4, in some examples, the pixel circuit 10 may further include a fourth reset circuit 220. The fourth reset circuit 220 is connected to the first end 111 of the drive circuit 110 and configured to apply a fourth reset voltage to the first end 111 of the drive circuit 110 in response to a fourth reset signal. For example, the fourth reset circuit 220 is connected to a fourth reset line RST4 for providing the fourth reset signal and a fourth reset voltage line VR4 for supplying the fourth reset voltage. The fourth reset circuit 220 is turned on in response to the fourth reset signal and transmits the fourth reset voltage to the first end 111 of the drive circuit 110 to reset the first end 111 of the drive circuit 110. Other parts of the pixel circuit 10 are basically the same as those of the pixel circuit 10 shown in FIG. 3, and therefore will not be described again here.

[0064] For example, in this example, the potential of the third node P3 after being reset by the first reset circuit 160 is higher than the potential of the fourth node P4 after being reset by the second reset circuit 190, and the potential of the first node P1 after being reset by the third reset circuit 210 is lower than the potential of the third node P3 after being reset by the first reset circuit 160 and is equal to or lower than the potential of the fourth node P4 after being reset by the second reset circuit 190. The potential of the second node P2 after being reset by the fourth reset circuit 220 is higher than the potential of the first node P1 after being reset by the third reset circuit 210, the potential of the second node P2 after being reset by the fourth reset circuit 220 is higher than the potential of the third node P3 after being reset by the first reset circuit 160, and the potential of the second node P2 after being reset by the fourth reset circuit 220 is higher than the potential of the fourth node P4 after being reset by the second reset circuit 190. This can provide a better reset effect, and can better reduce or eliminate the influence of residual charges on the accuracy of data writing and the potential of the anode of the light-emitting device during the light-emitting stage.

[0065] 5 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure. A driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG.

[0066] 5, in some examples, the pixel circuit 10 may further include a leakage prevention circuit 230. The leakage prevention circuit 230 is connected to the control end 113 of the driving circuit 110, the threshold compensation circuit 130, and the memory circuit 140, and is configured to suppress leakage of the control end 113 of the driving circuit 110. The leakage prevention circuit 230 is further connected to a third scan line SC3 for providing a third scan signal. The leakage prevention circuit 230 is turned on in response to the third scan signal, thereby transmitting the required electrical signal to the control end 113 of the driving circuit 110. In this example, the first reset circuit 160 is connected to the threshold compensation circuit 130 and the leakage prevention circuit 230, and can apply a first reset voltage to the first node P1 through the conductive leakage prevention circuit 230, and can apply a first reset voltage to the third node P3 through the conductive threshold compensation circuit 130. Other parts of the pixel circuit 10 are basically the same as those of the pixel circuit 10 shown in FIG. 2, and therefore will not be described again here.

[0067] 6 is a schematic flowchart of a pixel circuit driving method provided by some embodiments of the present disclosure, which can be used for the pixel circuit 10 shown in, for example, FIGS. 2, 3, 4, and 5. As shown in FIG. 6, the driving method provided by the embodiments of the present disclosure includes: Before the data writing step, a step S10 is performed in which a first reset circuit is turned on in response to a first reset signal, a first reset voltage is applied to a control end of the driving circuit, and a first node is reset; and a first light-emitting control circuit is turned on in response to a first light-emitting control signal, a first voltage is applied to a first end of the driving circuit, and a second node is reset; In a data writing step, a data writing circuit is turned on in response to a first scanning signal to write a data signal into a first end of the driving circuit (step S20); The light emitting step includes step S30 in which the first light emitting control circuit is turned on in response to the first light emitting control signal, and the light emitting element emits light in response to the driving current.

[0068] 2, 3, and 4, the reset operation of the first node in step S10 may include the steps of: making the first reset circuit 160 conductive in response to a first reset signal, making the threshold compensation circuit 130 conductive in response to a second scan signal, and applying a first reset voltage to the control end 113 of the driving circuit 110 through a path formed by the first reset circuit 160 and the threshold compensation circuit 130 to reset the first node P1. For example, before the data writing stage, the first reset circuit 160 is made conductive in response to the first reset signal, and at this time, the threshold compensation circuit 130 is made conductive in response to the second scan signal to apply the first reset voltage to the control end 113 of the driving circuit 110, i.e., to the first node P1, to reset the first node P1. In addition, in response to the first light-emitting control signal, the first light-emitting control circuit 150 is turned on and applies the first voltage to the first terminal 111 of the driving circuit 110, that is, to the second node P2, thereby resetting the second node P2.

[0069] 5, before the data writing step, the first reset circuit 160 is made conductive in response to the first reset signal, and the leakage prevention circuit 230 is made conductive in response to the third scan signal to apply a first reset voltage to the control end 113 of the driving circuit 110, i.e., to the first node P1, thereby resetting the first node P1. Also, the first light-emitting control circuit 150 is made conductive in response to the first light-emitting control signal to apply a first voltage to the first terminal 111 of the driving circuit 110, i.e., to the second node P2, thereby resetting the second node P2.

[0070] For example, in step S20, in the data writing stage, the data writing circuit 120 is turned on in response to a first scanning signal, and writes a data signal to the first end 111 of the driving circuit 110, i.e., the second node P2. At this time, the driving circuit 110 and the threshold compensation circuit 130 are also turned on. In the pixel circuit 10 shown in FIG. 5, the leakage prevention circuit 230 is also turned on. Therefore, the data signal is written from the second node P2 to the control end 113 of the driving circuit 110, i.e., the first node P1, and can be stored in the memory circuit 140. In this process, relevant information about the threshold voltage of the driving circuit 110 is also stored in the memory circuit 140. Therefore, in the light-emitting stage, the data signal and the stored voltage including the threshold voltage can be used to control the driving circuit 110, and thereby compensate the driving circuit 110.

[0071] For example, in step S30, during the light-emitting stage, the first light-emitting control circuit 150 is turned on in response to the first light-emitting control signal, causing the light-emitting element 170 to emit light according to the driving current. At this time, the second light-emitting control circuit 180 is also turned on, forming a current path in front of the first voltage line VDD and the second voltage line VSS, and the driving circuit 110 controls the magnitude of the driving current to cause the light-emitting element 170 to emit light according to the required "gradation."

[0072] For example, the driving method provided by the embodiment of the present disclosure is as follows: Before the data writing stage, a first reset circuit resets the first node and applies a first reset voltage to the second end of the driving circuit, thereby resetting the third node; and / or The method further includes, before the data writing step, making the second reset circuit conductive in response to the second reset signal to apply the second reset voltage to the light emitting element and reset the fourth node.

[0073] For example, in the case of the pixel circuit 10 shown in Figures 2, 3, and 4, before the data writing stage, the first reset circuit 160 is used to reset the first node P1, and the first reset voltage is first written to the second end 112 of the driving circuit 110 (i.e., the third node P3), thereby resetting the third node P3.

[0074] For example, in the case of the pixel circuit 10 shown in FIG. 5, before the data writing stage, the first reset circuit 160 is used to reset the first node P1, and the threshold compensation circuit 130 is turned on, so that the first reset voltage transmitted by the first reset circuit 160 is transmitted to the third node P3 through the threshold compensation circuit 130, thereby resetting the third node P3.

[0075] For example, before the data writing step, the second reset circuit 190 is turned on in response to the second reset signal to apply a second reset voltage to the light emitting element 170 (eg, the anode of the light emitting element 170) and reset the fourth node P4.

[0076] For example, in some cases, before the data writing step, the first node P1 and the second node P2 are reset simultaneously, or the first node P1 and the second node P2 are reset at different times, i.e., the first node P1 and the second node P2 can be reset simultaneously, the first node P1 and the second node P2 can be reset sequentially, the first node P1 can be reset first and then the second node P2, or the second node P2 can be reset first and then the first node P1.

[0077] For example, in some cases, when both the third node P3 and the fourth node P4 are reset before the data writing step, the third node P3 and the fourth node P4 may be reset simultaneously or at different times, i.e., the third node P3 and the fourth node P4 may be reset simultaneously, the third node P3 and the fourth node P4 may be reset sequentially, the third node P3 may be reset first and then the fourth node P4, or the fourth node P4 may be reset first and then the third node P3.

[0078] For example, in some examples, before the data writing phase, the reset period of at least one of the third node P3 and the fourth node P4 overlaps with the reset period of at least one of the first node P1 and the second node P2, i.e., at least one of the third node P3 and the fourth node P4 is reset simultaneously with at least one of the first node P1 and the second node P2.

[0079] For example, in some examples, before the data writing stage, the reset period of the first node P1, the reset period of the second node P2, the reset period of the third node P3, and the reset period of the fourth node P4 do not overlap. That is, the reset period of each node does not overlap with the reset period of the other nodes, and only one node is reset in each reset period. Note that the reset period refers to the period during which the node is reset, and may be a continuous period or short periods depending on the length of time required for the reset operation, and embodiments of the present disclosure are not limited thereto.

[0080] For example, the driving method provided by the embodiment of the present disclosure is as follows: After the data writing step and before the light emitting step, the first light emitting control circuit is turned on in response to the first light emitting control signal to apply a first voltage to the first end of the driving circuit and reset the second node; and / or After the data writing step and before the light emitting step, the first reset circuit is made conductive in response to the first reset signal to apply a first reset voltage to the second end of the driving circuit to reset the third node; and / or The method further includes, after the data writing step and before the light emitting step, making the second reset circuit conductive in response to the second reset signal to apply the second reset voltage to the light emitting element and reset the fourth node.

[0081] For example, in the pixel circuit 10 shown in Figures 2, 3, 4, and 5, after the data writing stage and before the light emitting stage, the first light emitting control circuit 150 is turned on in response to the first light emitting control signal, applies a first voltage to the first end 111 of the driving circuit 110, i.e., the second node P2, and resets the second node P2.

[0082] For example, in the case of the pixel circuit 10 shown in Figures 2, 3, and 4, after the data writing stage and before the light emitting stage, the first reset circuit 160 is made conductive in response to the first reset signal, and applies a first reset voltage to the second end 112 of the driving circuit 110, i.e., the third node P3, to reset the third node P3.

[0083] For example, in the case of the pixel circuit 10 shown in FIG. 5, after the data writing stage and before the light emitting stage, the first reset circuit 160 is made conductive, and at the same time, the threshold compensation circuit 130 is also made conductive, and the first reset voltage is applied to the third node P3 via the threshold compensation circuit 130, thereby resetting the third node P3.

[0084] For example, after the data writing stage and before the light emitting stage, the second reset circuit 190 is turned on in response to the second reset signal, and applies a second reset voltage to the light emitting element 170 (e.g., the anode of the light emitting element 170), i.e., the fourth node P4, to reset the fourth node P4.

[0085] For example, in some examples, after the data writing stage and before the light-emitting stage, at least two of the second node P2, the third node P3, and the fourth node P4 are reset simultaneously, or at least two of the second node P2, the third node P3, and the fourth node P4 are reset with different periods. That is, the second node P2, the third node P3, and the fourth node P4 can be reset individually with three different reset periods, or any two of the second node P2, the third node P3, and the fourth node P4 can be reset simultaneously and the remaining nodes can be reset with different periods, or the second node P2, the third node P3, and the fourth node P4 can be reset simultaneously with the same period. This can be determined according to actual needs, but the embodiments of the present disclosure are not limited thereto.

[0086] In the driving method provided by the embodiment of the present disclosure, before the data writing stage, any one or more of the first node P1, the second node P2, the third node P3, and the fourth node P4 can be reset. Nodes that need to be reset can be reset simultaneously, or the reset periods of each node can be staggered. Therefore, before writing data, one or more of the anode of the OLED and / or the source electrode, drain electrode, and gate electrode of the driving transistor can be initialized or reset. By resetting the nodes on the data writing path, the adverse effects of residual charges can be reduced or eliminated, optimizing the display effect.

[0087] In the driving method provided by the embodiment of the present disclosure, after the data writing stage and before the light emitting stage, any one or more of the second node P2, the third node P3, and the fourth node P4 can be reset. For nodes that need to be reset, they can be reset simultaneously or the reset periods of each node can be staggered. Therefore, after writing data and before light emitting, one or more of the anode of the OLED and / or the source electrode and drain electrode of the driving transistor can be initialized or reset. By resetting the nodes on the light emitting path, the adverse effects of residual charges can be reduced or eliminated, optimizing the display effect.

[0088] In the driving method provided by the embodiments of the present disclosure, the nodes that need to be reset before the data writing step and the nodes that need to be reset after the data writing step and before the light-emitting step may be the same or different, and the reset operation before the data writing step and the reset operation after the data writing step and before the light-emitting step may be the same or different, and can be determined according to actual needs, but the embodiments of the present disclosure are not limited thereto.

[0089] The driving method provided by the embodiment of the present disclosure will be briefly described below in conjunction with a specific circuit structure.

[0090] FIG. 7 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 2. As shown in FIG. 7, the pixel circuit 10 includes transistors M1 to M7 and a storage capacitor Cst. For example, transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be implemented as a light-emitting element EL, which may be, for example, an OLED, and the embodiments of the present disclosure include, but are not limited to, this. The following embodiments will be described using an OLED as an example, and will not be described repeatedly. The OLED may be of various types, such as a top-emitting type or a bottom-emitting type, and may emit red light, green light, blue light, or white light, and the embodiments of the present disclosure are not limited thereto.

[0091] 7, the driving circuit 110 can be specifically realized as a driving transistor, i.e., transistor M3. The gate electrode of the driving transistor (transistor M3) is used as the control end 113 of the driving circuit 110, the first pole of the driving transistor (transistor M3) is used as the first end 111 of the driving circuit 110, and the second pole of the driving transistor (transistor M3) is used as the second end 112 of the driving circuit 110.

[0092] The data write circuit 120 can be realized as a data write transistor, i.e., transistor M4. A gate electrode of the data write transistor (transistor M4) is connected to the first scan line (scan line S3) to receive a first scan signal, a first pole of the data write transistor (transistor M4) is connected to the data line (data line DL) to receive a data signal, and a second pole of the data write transistor (transistor M4) and a first pole of the drive transistor (transistor M3) are connected to the second node P2.

[0093] The threshold compensation circuit 130 can be realized as a threshold compensation transistor, i.e., transistor M2. The gate electrode of the threshold compensation transistor (transistor M2) is connected to the second scan line (scan line S5) to receive the second scan signal, the first pole of the threshold compensation transistor (transistor M2) and the second pole of the driving transistor (transistor M3) are connected to the third node P3, and the second pole of the threshold compensation transistor (transistor M2) and the gate electrode of the driving transistor (transistor M3) are connected to the first node P1.

[0094] The memory circuit 140 can be realized as a storage capacitor Cst, where a first pole of the storage capacitor Cst is connected to a first voltage line VDD, and a second pole of the storage capacitor Cst and a gate electrode of a driving transistor (transistor M3) are connected to a first node P1.

[0095] The first light-emitting control circuit 150 can be realized as a first light-emitting control transistor, i.e., transistor M5. The gate electrode of the first light-emitting control transistor (transistor M5) is connected to the first light-emitting control line (scan line S1) to receive the first light-emitting control transistor, its first pole is connected to the first voltage line VDD, and its second pole is connected to the first end of the driving circuit, i.e., the driving transistor (transistor M3), and the second node P2.

[0096] The first reset circuit 160 can be realized as a first reset transistor, i.e., transistor M1. The gate electrode of the first reset transistor (transistor M1) is connected to the first reset line (scan line S4) to receive the first reset signal, the first pole of the first reset transistor is connected to the first reset voltage line (voltage line INIT1) to receive the first reset voltage, and the second pole of the first reset transistor (transistor M1) and the second pole of the driving transistor (transistor M3) are connected to the third node P3.

[0097] The second light-emitting control circuit 180 can be realized as a second light-emitting control transistor, i.e., transistor M6. The gate electrode of the second light-emitting control transistor (transistor M6) is connected to the second light-emitting control line (scan line S2) to receive the second light-emitting control signal, and its first electrode is connected to the second end of the driving circuit, i.e., the second electrode of the driving transistor (transistor M3) is connected to the third node P3, and its second electrode and the anode of the light-emitting element EL are connected to the fourth node P4.

[0098] The second reset circuit 190 can be realized as a second reset transistor, i.e., transistor M7. The gate electrode of the second reset transistor (transistor M7) is connected to the second reset line (scan line S6) to receive the second reset signal, the first electrode of the second reset transistor (transistor M7) is connected to the second reset voltage line (voltage line INIT2) to receive the second reset voltage, and the second electrode of the second reset transistor (transistor M6), the second electrode of the second light-emitting control transistor (transistor M6), and the light-emitting element EL are connected to the fourth node P4.

[0099] For example, the driving transistor (transistor M3), the data writing transistor (transistor M4), the first light-emitting control transistor (transistor M5), and the first reset transistor (transistor M1) are all first-type transistors, and the threshold compensation transistor (transistor M2) is a second-type transistor different from the first type. For example, in some examples, the first-type transistors include P-type thin film transistors, and the second-type transistors include N-type thin film transistors. That is, the driving transistor (transistor M3), the data writing transistor (transistor M4), the first light-emitting control transistor (transistor M5), and the first reset transistor (transistor M1) are P-type thin film transistors, and the threshold compensation transistor (transistor M2) is an N-type transistor. Of course, the embodiments of the present disclosure are not limited thereto, and the types of some transistors used in the pixel circuit 10 can be changed according to actual needs, for example, by changing a P-type thin film transistor to an N-type thin film transistor, or by changing an N-type thin film transistor to a P-type thin film transistor.

[0100] 8 is a timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. As shown in FIG. 8, in some examples, as shown in FIG. 9, in the first stage T1, the gate electrode of transistor M5 is connected to the low-potential scan line S1, transistor M5 is turned on, and the high potential of the first voltage line VDD is written to the first pole of transistor M3, i.e., second node P2, and the potential of second node P2 is V1. The potential of V1 may be VDD or may be greater than 0 and less than VDD. When the potential of V1 is equal to VDD, the potential provided by the first voltage line VDD is constant, and when the potential of V1 is greater than 0 and less than VDD, the potential provided by the first voltage line VDD changes. The gate electrode of transistor M1 is connected to the low-potential scan line S4, causing transistor M1 to conduct, and the gate electrode of transistor M2 is connected to the high-potential scan line S5, causing transistor M2 to conduct, and the low potential of the voltage line INIT1 is written to the second electrode of transistor M3 (i.e., the third node P3) and the gate electrode of transistor M3 (i.e., the first node P1). The gate electrode of transistor M7 is connected to the low-potential scan line S6, causing transistor M7 to conduct, and the low potential of the voltage line INIT2 is written to the anode of the light-emitting element EL (i.e., the fourth node P4). Therefore, in the first stage T1, the anode of the light-emitting element EL and the first electrode, second electrode, and gate electrode of transistor M3 are reset, removing any residual charges displayed in the previous frame, thereby contributing to accurate writing of data in the second stage T2.

[0101] In the second phase T2, S3 is low and S5 is high, causing transistors M4 and M2 to conduct. A data signal is written to the gate electrode of transistor M3 through transistors M4, M3, and M2, respectively. At this time, the potential of node P1 becomes Vdata+|Vth|, where Vdata is the data signal and Vth is the threshold voltage of transistor M3. In this phase, to ensure that node P4 maintains a stable low potential before light emission, transistor M7 remains conductive in the second phase T2, causing the low potential of voltage line INIT2 to be written to node P4. That is, node P4 is reset in both phases T1 and T2.

[0102] During the third stage T3, the potentials of S1 and S2 are low, transistors M5 and M6 are conductive, and the light-emitting element EL emits light. The current flowing through transistor M3 is I = 1 / 2μ * W / L * Cox(Vgs - Vth)² = 1 / 2μ * W / L * Cox(VDD - Vdata)², where W / L is the width-to-length ratio of transistor M3, Cox is the dielectric constant of the channel insulating layer of transistor M3, and μ is the channel carrier mobility of transistor M3. Simulations yielded favorable results. The simulation conditions were: VDD = 4.6V, VSS = -3V, Vinit (i.e., INIT1 and INIT2) = -3V, Vdata = 3V, and Vth = -2V. Good simulation results indicate high data writing accuracy and minimal residual charge influence on the anode potential of the light-emitting device during the light-emitting stage.

[0103] 9, in the third stage T3, i.e., the light-emitting stage, the potential of the first voltage line VDD is VDD, and in the non-light-emitting stage, the first stage T1 for resetting and the second stage T2 for writing data are included, and the potential of the first voltage line can be lowered to V1 to save power consumption. The potential of the second node P2 can be greater than V1, i.e., 0, but less than VDD, thereby realizing the reset function.

[0104] In this example, S2 and S5 may be signals output by the same gate drive circuit (e.g., GOA), and S3 and S4 may be signals provided by the same type of GOA, for example, S3 is a signal provided by a shift register unit of a specific stage of the GOA, and S4 is a signal provided by a shift register unit in the previous stage of the GOA. Therefore, a row of pixel circuits needs at least four GOAs, or one stage of the shift register unit of the GOA needs to output four shift signals (if the GOA used can output multiple signals, for example, one GOA can output two signals with different pulse widths or two signals with different potentials).

[0105] 10 is another timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. As shown in FIG. 10, compared with the example shown in FIG. 8, in this example, a period for resetting the drain electrode and gate electrode of the transistor M3 (i.e., the third node P3 and the first node P1) is added between the reset stage and the data write stage in FIG. 8. Of course, in other examples, this stage can also be incorporated into the T1 stage to shorten the reset time.

[0106] In the example shown in FIG. 10, after writing data and before light emission, the source electrode of transistor M3 (i.e., second node P2) and the drain electrode of transistor M7 (i.e., the anode of the light-emitting element EL) are reset again, i.e., a T4 period is added. The purpose of resetting second node P2 again is to remove residual charge at second node P2 after writing data, thereby eliminating its effect on the current flowing through the driving transistor (transistor M3) during the light-emission period. The purpose of resetting fourth node P4 again is to remove residual charge that may be generated at fourth node P4 due to leakage current that may flow through transistor M6 during the data writing period. During the four periods T1 to T4, S6 can be set to maintain a low potential so that the low-potential control transistor M7 of S6 is conductive and the potential of fourth node P4 can maintain the potential of INIT2 for a long period during the non-light-emission period. Simulations have yielded favorable results. The simulation conditions are: VDD is 4.6V, VSS is −3V, Vinit (ie, INIT1 and INIT2) is −3V, and Vdata is 3V.

[0107] In this example, S3 and S4 may be signals provided by the same type of GOA, for example, S3 is a signal provided by a shift register unit of a specific stage of the GOA, and S4 is a signal provided by a shift register unit of a previous stage of the GOA. Therefore, at least four GOAs are required for a row of pixel circuits, or one stage of the shift register unit of the GOA needs to output four shift signals (if the GOA used can output multiple signals, for example, one GOA can output two signals with different pulse widths or two signals with different potentials).

[0108] 11 is another timing diagram of the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure. As shown in FIG. 11, comparing this example with the example shown in FIG. 10, the same point is that in step T2 before the data writing step T3 and step T4 after it, both the second node P2 and the fourth node P4 are reset, thereby ensuring that data can be accurately written and that residual charges on the light-emitting path can be removed before light emission. In this example, the reset operation of the first node P1 and the third node P3 is performed in the first step T1.

[0109] In this example, S1 and S5 may be signals output by the same GOA, and S3 and S4 may be signals provided by the same type of GOA, for example, S3 is a signal provided by a shift register unit of a specific stage of the GOA, and S4 is a signal provided by a shift register unit two stages before the GOA. Therefore, a row of pixel circuits needs at least four GOAs, or one stage of the shift register unit of the GOA needs to output four shift signals.

[0110] FIG. 12 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 5. As shown in FIG. 12, the pixel circuit 10 includes transistors M1 to M8 and a storage capacitor Cst. For example, transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be realized as a light-emitting element EL, which can be, for example, an OLED, and embodiments of the present disclosure include, but are not limited to, this. The following embodiments will be described using an OLED as an example, and will not be described repeatedly. The OLED can be of various types, such as a top-emitting type or a bottom-emitting type, and can emit red light, green light, blue light, or white light, and embodiments of the present disclosure are not limited thereto.

[0111] For example, as shown in FIG. 12, the drive circuit 110 can be implemented as a drive transistor, i.e., transistor M3, and the data write circuit 120 can be implemented as a data write transistor, i.e., transistor M4. The threshold compensation circuit 130 can be implemented as a threshold compensation transistor, i.e., transistor M2. The memory circuit 140 can be implemented as a storage capacitor Cst. The first light-emitting control circuit 150 can be implemented as a first light-emitting control transistor, i.e., transistor M5. The second light-emitting control circuit 180 can be implemented as a second light-emitting control transistor, i.e., transistor M6. The second reset circuit 190 can be implemented as a second reset transistor, i.e., transistor M7. The connection methods of these transistors and storage capacitors are similar to those of the circuit structure shown in FIG. 7, and will not be described again here.

[0112] The difference between this example and the circuit structure shown in FIG. 7 is that the first reset circuit 160 is connected in a different way and further includes a leakage prevention circuit 230. For example, the first reset circuit 160 can be realized as a first reset transistor, i.e., transistor M1. The gate electrode of the first reset transistor (transistor M1) is connected to the first reset line (scan line S4), its first pole is connected to the first reset voltage line (voltage line INIT1), and its second pole is connected to the second pole of transistor M2. The leakage prevention circuit 230 can be realized as a leakage prevention transistor, i.e., transistor M8. The gate electrode of the leakage prevention transistor (transistor M8) is connected to the third scan line (scan line S7), its first pole is connected to the second pole of transistor M2, and its second pole and the gate electrode of transistor M3 are connected to the first node P1. For example, the leakage prevention transistor is a second type transistor, such as an N-type thin film transistor.

[0113] 13 is a timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. As shown in FIG. 13, in some examples, compared with the previous example using the circuit structure shown in FIG. 7, the pixel circuit 10 used in this example includes two N-type thin film transistors (transistor M8 and transistor M2), and can therefore play a better role in preventing leakage at the first node P1, which is prone to leakage. Furthermore, the two N-type thin film transistors M2 and M8 can increase operational flexibility; for example, if only the first node P1 needs to be reset, only transistor M8 needs to be turned on.

[0114] 13, in the first stage T1, the transistor M8 controlled by S7 is turned on, the transistor M1 controlled by S4 is turned on, a reset voltage of INIT1 is written to the first node P1 to reset the gate electrode of the transistor, i.e., reset the first node P1, the transistor M5 controlled by S1 is turned on, the transistor M7 controlled by S6 is turned on, a high potential of VDD is written to the second node P2 to reset the second node P2, and the potential of INIT2 is written to the anode of the light-emitting element EL to reset the fourth node P4.

[0115] In the second phase T2, a data write operation is performed. The transistor M4 controlled by S3 is turned on, and the transistor M2 controlled by S5 is turned on, so that a data signal is written to the gate electrode of the transistor M3 (i.e., the first node P1), and the potential of the first node P1 becomes Vdata+|Vth|. At the same time, the transistor M7 controlled by S6 remains on, so that the potential of the fourth node P4 becomes INIT2.

[0116] In the third stage T3, the potentials of S1 and S2 are low, the transistors M5 and M6 are conductive, and therefore the light-emitting element EL emits light.

[0117] FIG. 14 is another timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. As shown in FIG. 14, compared to the example shown in FIG. 13, the difference in this example is that the reset operation before data writing is divided into two stages: in the first stage T1, the second node P2 and the fourth node P4 are reset, and in the second stage T2, the first node P1 is reset. To save time, in other examples, the T1 and T2 stages in this example can be combined into one stage. After writing the data, the second node P2 and the fourth node P4 are reset again to remove residual charges on the light-emitting path, thereby entering the light-emitting stage.

[0118] In this example, S7 and S1 may be signals output by the same GOA, and S3 and S4 may be signals provided by the same type of GOA, for example, S3 is a signal provided by a shift register unit of a specific stage of the GOA, and S4 is a signal provided by a shift register unit in the previous stage of the GOA. Therefore, a row of pixel circuits needs at least five GOAs, or one stage of the shift register unit of the GOA needs to output five shift signals.

[0119] 15 is another timing diagram of the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure. As shown in FIG. 15, in this example, in stage T2 before the data writing stage (third stage T3) and stage T4 after it, reset operations are performed on both the second node P2 and the fourth node P4. The reset operation on the first node P1 is performed in the first stage T1. For the conduction states of each transistor during the reset operation, please refer to the above content, and a repeated description will not be given here.

[0120] FIG. 16 is another timing diagram of the pixel circuit shown in FIG. 12 , provided by some embodiments of the present disclosure. As shown in FIG. 16 , in this example, a reset operation is performed in two stages before data is written. Specifically, in the first stage T1, the first node P1 and the third node P3 are reset, and in the second stage T2, the second node P2 and the fourth node P4 are reset. After the data is written, the second node P2, the third node P3, and the fourth node P4 are reset, with the potential of the second node P2 being VDD, the potential of the third node P3 being INIT1, and the potential of the fourth node P4 being INIT2. The conduction states of each transistor during the reset operation can be referenced above, and will not be described again here.

[0121] FIG. 17 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 3. As shown in FIG. 17, the pixel circuit 10 includes transistors M1 to M8 and a storage capacitor Cst. For example, transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be realized as a light-emitting element EL, which may be, for example, an OLED, and embodiments of the present disclosure include, but are not limited to, this. The following embodiments will be described using an OLED as an example, and will not be described repeatedly. The OLED may be of various types, such as a top-emitting type or a bottom-emitting type, and may emit red light, green light, blue light, or white light, and embodiments of the present disclosure are not limited thereto.

[0122] For example, as shown in FIG. 17, the drive circuit 110 can be implemented as a drive transistor, i.e., transistor M3, and the data write circuit 120 can be implemented as a data write transistor, i.e., transistor M4. The threshold compensation circuit 130 can be implemented as a threshold compensation transistor, i.e., transistor M2. The memory circuit 140 can be implemented as a storage capacitor Cst. The first light-emitting control circuit 150 can be implemented as a first light-emitting control transistor, i.e., transistor M5. The second light-emitting control circuit 180 can be implemented as a second light-emitting control transistor, i.e., transistor M6. The first reset circuit 160 can be implemented as a first reset transistor, i.e., transistor M1. The second reset circuit 190 can be implemented as a second reset transistor, i.e., transistor M7. The connections between these transistors and the storage capacitors are similar to those in the circuit structure shown in FIG. 7, and will not be described again here.

[0123] The difference between this example and the circuit structure shown in FIG. 7 is that it further includes a third reset circuit 210. For example, the third reset circuit 210 can be realized as a third reset transistor, i.e., transistor M8. The gate electrode of the third reset transistor (transistor M8) is connected to the third reset line (scan line S7) to receive the third reset signal, its first pole is connected to the third reset voltage line (voltage line INIT1) to receive the third reset voltage, and its second pole is connected to the control end 113 of the driving circuit 110, i.e., the gate electrode of transistor M3 and the first node P1. For example, the third reset transistor is a second type transistor, such as an N-type thin film transistor.

[0124] FIG. 18 is a timing diagram of the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure. As shown in FIG. 18, in this example, transistor M1 is used to reset the drain electrode of transistor M3 (i.e., third node P3). In the first stage T1, the first node P1, the third node P2, the second node P3, and the fourth node P4 are reset. Next, in the second stage T2, a data write operation is performed. In the third stage T3, the second node P2 is reset by the conductive transistor M5, the third node P3 is reset by the conductive transistor M1, and the fourth node P4 is reset by the conductive transistor M7. In the fourth stage T4, the light-emitting element EL emits light. The conductive states of each transistor during the reset operation can be referred to above, and will not be described again here.

[0125] FIG. 19 is another timing diagram of the pixel circuit shown in FIG. 17 , provided by some embodiments of the present disclosure. As shown in FIG. 19 , in this example, in the first stage T1, the first node P1, the second node P2, and the fourth node P4 are reset, and in the second stage T2, the first node P1, the third node P3, and the fourth node P4 are reset. For example, the second node P2 can be reset by the conductive transistor M5, the third node P3 can be reset by the conductive transistor M1, the fourth node P4 can be reset by the conductive transistor M7, and the first node P1 can be reset by the conductive transistor M8. In the second stage T3, a data write operation is performed. Next, in the fourth stage T4, the light-emitting element EL emits light. The conductive states of each transistor during the reset operation can be referred to above, and will not be described again here.

[0126] 20 is another timing diagram of the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure. As shown in FIG. 20, in this example, in the first stage T1, the first node P1, the second node P2, and the fourth node P4 are reset, and in the second stage T2, the first node P1, the third node P3, and the fourth node P4 are reset. In the third stage T3, a data write operation is performed. In the fourth stage T4, the third node P3 and the fourth node P4 are reset. In the fifth stage T5, the light-emitting element EL emits light. The conductive states of each transistor during the reset operation can be referred to above, and will not be described again here.

[0127] FIG. 21 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 4. As shown in FIG. 21, the pixel circuit 10 includes transistors M1 to M9 and a storage capacitor Cst. For example, transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be realized as a light-emitting element EL, which may be, for example, an OLED, and embodiments of the present disclosure include, but are not limited to, this. The following embodiments will be described using an OLED as an example, and will not be described repeatedly. The OLED may be of various types, such as a top-emitting type or a bottom-emitting type, and may emit red light, green light, blue light, or white light, and embodiments of the present disclosure are not limited thereto.

[0128] For example, as shown in FIG. 21 , the drive circuit 110 can be implemented as a drive transistor, i.e., transistor M3, and the data write circuit 120 can be implemented as a data write transistor, i.e., transistor M4. The threshold compensation circuit 130 can be implemented as a threshold compensation transistor, i.e., transistor M2. The memory circuit 140 can be implemented as a storage capacitor Cst. The first light-emitting control circuit 150 can be implemented as a first light-emitting control transistor, i.e., transistor M5. The second light-emitting control circuit 180 can be implemented as a second light-emitting control transistor, i.e., transistor M6. The first reset circuit 160 can be implemented as a first reset transistor, i.e., transistor M1. The second reset circuit 190 can be implemented as a second reset transistor, i.e., transistor M7. The third reset circuit 210 can be implemented as a third reset transistor, i.e., transistor M8. The connections between these transistors and the storage capacitors are similar to those in the circuit structure shown in FIG. 17 , and will not be described again here.

[0129] 17 is that it further includes a fourth reset circuit 220. For example, the fourth reset circuit 220 can be realized as a fourth reset transistor, i.e., transistor M9. The gate electrode of the fourth reset transistor (transistor M9) is connected to the fourth reset line (scan line S8) to receive the fourth reset signal, the first electrode of the fourth reset transistor (transistor M9) is connected to the fourth reset voltage line (voltage line INIT4) to receive the fourth reset voltage, and the second electrode of the fourth reset transistor (transistor M9) is connected to the first end 111 of the driving circuit 110, i.e., the gate electrode of transistor M3, and the second node P2.

[0130] FIG. 22 is a timing diagram of the pixel circuit shown in FIG. 21 , provided by some embodiments of the present disclosure. As shown in FIG. 22 , in this example, in a first stage T1, the first node P1 is reset by the conductive transistor M8, and the second node P2 and the fourth node P4 are reset by the conductive transistors M9 and M7, respectively. In a second stage T2, the third node P3 is reset by the conductive transistor M1. In a third stage T3, a data write operation is performed. In a fourth stage T4, the third node P3 and the fourth node P4 are again reset by the conductive transistors M1 and M7, respectively. In a fifth stage T5, the light-emitting element EL emits light. The conductive states of each transistor during the reset operation can be referred to above, and will not be described again here.

[0131] This timing was simulated under the following conditions: VINT4 = 6V, VINT1 = -3V or -4V, VINT2 = -3V, and VINT3 = 0V, 1V, 2V, 3V, or 4V. Different VINT3 voltages can produce better simulation results. For example, the VINT3 voltage can be 0V, 1V, 2V, 3V, or 4V, depending on your needs. If you need a fast reset and it's applicable to a high-frequency scenario, you can choose a lower voltage, such as 0V. If you need a slower reset and it's applicable to a low-frequency scenario, you can choose a voltage closer to the data voltage, such as 3V or 4V.

[0132] For example, in this example, the potential of the third node P3 after being reset by the first reset transistor (transistor M1) is higher than the potential of the fourth node P4 after being reset by the second reset transistor (transistor M7), and the potential of the first node P1 after being reset by the third reset transistor (transistor M8) is lower than the potential of the third node P3 after being reset by the first reset transistor (transistor M1) and equal to or lower than the potential of the fourth node P4 after being reset by the second reset transistor (transistor M7). The potential of the second node P2 after being reset by the fourth reset transistor (transistor M9) is higher than the potential of the first node P1 after being reset by the third reset transistor (transistor M8), higher than the potential of the third node P3 after being reset by the first reset transistor (transistor M1), and higher than the potential of the fourth node P4 after being reset by the second reset transistor (transistor M7). This provides a better reset effect and can better reduce the influence of residual charge.

[0133] For example, in the timing diagram shown in FIG. 22, different operating frequencies may result in different reset conditions within one frame. For example, at low frequencies, such as 30 Hz or less, the first node P1, the second node P2, the third node P3, and the fourth node P4 are all reset. Operating at low frequencies allows sufficient time for the reset to complete. Because transistors in the pixel circuit are more likely to leak current at low frequencies, sufficient resetting helps improve the hysteresis effect and thereby enhance display quality. For example, at medium frequencies, such as 30 Hz to 90 Hz, fewer nodes may be selected to be reset than at low frequencies. For example, the first node P1, the second node P2, and the fourth node P4 may be reset, or the first node P1, the third node P3, and the fourth node P4 may be reset. In a high-frequency operating state, such as 90 Hz to 120 Hz or even higher, fewer nodes can be selected to be reset than in the medium / low-frequency states. For example, the first node P1 and the fourth node P4 can be reset, or only one of the two nodes can be reset. The higher the frequency, the fewer nodes are reset, allowing for quick data writing in a short period of time and achieving a high refresh rate. Furthermore, in a high-frequency operating state, the number of nodes reset is reduced, which is advantageous for further reducing power consumption.

[0134] For example, to reduce the number of transistors in the pixel circuit and reset the second node P2, a separate voltage generation circuit can be used to generate three voltage signals, i.e., VDD1, VDD2, and VSS, used in the pixel circuit. Alternatively, two signal lines can be connected to the first voltage line VDD to transmit VDD1 and VDD2, respectively. The relationship between the three is VDD1 > VDD2 > VSS. In the non-emission phase, the signal connected to the first voltage line VDD is VDD2, and in the emission phase, the signal connected to the first voltage line VDD is VDD1. Therefore, transistor M9 in FIG. 21 can be omitted. Of course, embodiments of the present disclosure are not limited thereto. The first voltage transmitted to the first voltage line VDD may be constant, and embodiments of the present disclosure are not limited thereto.

[0135] FIG. 23 is a schematic diagram of a circuit structure of a pixel circuit provided by some embodiments of the present disclosure. In some examples, as shown in FIG. 23, the pixel circuit 10 includes transistors M1 to M9 and a storage capacitor Cst. For example, transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be implemented as a light-emitting element EL, which can be, for example, an OLED, and embodiments of the present disclosure include, but are not limited to, this. The following embodiments will be described using an OLED as an example, and will not be described again. The OLED can be of various types, such as a top-emitting type or a bottom-emitting type, and can emit red light, green light, blue light, or white light, and embodiments of the present disclosure are not limited thereto.

[0136] 23, the driving circuit 110 can be implemented as a driving transistor, i.e., transistor M3, and the data writing circuit 120 can be implemented as a data writing transistor, i.e., transistor M4. The threshold compensation circuit 130 can be implemented as a threshold compensation transistor, i.e., transistor M2. The storage circuit 140 can be implemented as a storage capacitor Cst. The first light-emitting control circuit 150 can be implemented as a first light-emitting control transistor, i.e., transistor M5. The second light-emitting control circuit 180 can be implemented as a second light-emitting control transistor, i.e., transistor M6. The first reset circuit 160 can be implemented as a first reset transistor, i.e., transistor M1. The second reset circuit 190 can be implemented as a second reset transistor, i.e., transistor M7. The third reset circuit 210 can be implemented as a third reset transistor, i.e., transistor M8. The fourth reset circuit 220 can be implemented as a fourth reset transistor, i.e., transistor M9. The operating principle of the pixel circuit 10 in this example is basically the same as that of the pixel circuit 10 shown in Figure 21. The difference is that all transistors in the pixel circuit 10 in this example are N-type thin film transistors. For the related principles, please refer to the above content and will not be repeated here.

[0137] 24 is a timing diagram of the pixel circuit shown in FIG. 23 provided by some embodiments of the present disclosure. In this example, in the first stage T1, the second node P2 is reset by the conductive transistor M9. In the second stage T2, the third node P3 is reset by the conductive transistor M1, the fourth node P4 is reset by the conductive transistor M7, and the first node P1 is reset by the conductive transistor M8. In the third stage T3, a data write operation is performed. In the fourth stage T4, the fourth node P4 and the second node P2 are reset by the conductive transistors M7 and M9, respectively. In the fifth stage T5, the light-emitting element EL emits light.

[0138] Although several examples have been described above in conjunction with FIGS. 7 to 24, the reset operations for the first node P1, the second node P2, the third node P3, and the fourth node P4 have been described in a specific order in these examples, this does not limit the embodiments of the present disclosure. The order of the reset operations for the first node P1, the second node P2, the third node P3, and the fourth node P4 is not limited to the situations described in the embodiments of the present disclosure and can be adjusted and changed according to actual situations. The embodiments of the present disclosure are not limited thereto. In the embodiments of the present disclosure, one or more of the first node P1, the second node P2, the third node P3, and the fourth node P4 can be selected and reset before the data write phase and / or between the data write phase and the light-emitting phase (i.e., after the data write phase and before the light-emitting phase). The selected nodes can be reset in any applicable order and manner, and the embodiments of the present disclosure are not limited thereto.

[0139] Although the reset operation of each node has been described with respect to a specific circuit structure, this does not limit the embodiments of the present disclosure, and the driving method provided by the embodiments of the present disclosure can be further applied to other circuit structures, and is not limited to the circuit structures shown in Figures 2 to 5, 7, 12, 17, 21, and 23, nor is it limited to pixel circuits including 7 transistors / 8 transistors / 9 transistors, and the driving method can be applied to any applicable pixel circuit.

[0140] In the embodiments of the present disclosure, by resetting the nodes on the data write path before writing data, the influence of residual charges (including residual charges due to leakage current) from the previous stage can be eliminated, and data can be accurately written to the gate electrode of the drive transistor. Because the nodes on the light-emitting path are reset before light emission and the light-emitting stage is performed after data is written, residual charges will occur in the light-emitting path after data is written, and residual charges will also occur in the light-emitting path due to leakage current of some transistors. However, by resetting the positions and nodes where residual charges may exist before light emission, the accuracy of the light-emitting current on the light-emitting path can be significantly improved, and display quality can be improved.

[0141] In each embodiment of the present disclosure, the storage capacitor Cst may be a capacitor element manufactured by a process, for example, a capacitor element may be realized by manufacturing special capacitor electrodes, and each electrode of the capacitor may be realized by a metal layer or a semiconductor layer (e.g., doped polysilicon). The storage capacitor Cst may be a parasitic capacitor between transistors, and may be realized by the transistor itself or other devices and circuits.

[0142] In describing each embodiment of the present disclosure, it should be noted that the first node P1, the second node P2, the third node P3, and the fourth node P4 do not represent actual components, but rather represent the junctions of associated electrical connections in the circuit diagram.

[0143] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are used as examples. The source and drain electrodes of the transistors used here have symmetrical structures, so there is no structural difference between the source and drain electrodes. In the embodiments of the present disclosure, to distinguish between the two poles of the transistor excluding the gate electrode, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0144] Furthermore, in the embodiments of the present disclosure, if the transistor is an N-type transistor, the first electrode of the transistor is a drain electrode and the second electrode is a source electrode; if the transistor is a P-type transistor, the first electrode of the transistor is a source electrode and the second electrode is a drain electrode. To change the type of transistor, simply refer to the corresponding transistor electrodes in the embodiments of the present disclosure and connect the electrodes of the selected type of transistor appropriately so that the corresponding voltage terminals provide corresponding high or low voltages. When using N-type transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current compared to using low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin film transistor.

[0145] At least one embodiment of the present disclosure further provides a pixel circuit, including a driving circuit, a data writing circuit, a threshold compensation circuit, a memory circuit, a first light-emitting control circuit, and a first reset circuit. The driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current flowing through the light-emitting element. The data writing circuit is connected to the first end of the driving circuit and is configured to write a data signal to the first end of the driving circuit in response to a first scanning signal during a data writing phase. The threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit and is configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal. The memory circuit is connected to the control end of the driving circuit and a first voltage line, and the control end of the memory circuit and the driving circuit are connected to a first node, and the memory circuit is configured to store the compensation signal and maintain the compensation signal at the control end of the driving circuit. The first light-emitting control circuit is connected to a first voltage line and a first end of the driving circuit, and the first light-emitting control circuit and the first end of the driving circuit are connected to a second node. The first light-emitting control circuit is configured to apply a first voltage provided by the first voltage line to the first end of the driving circuit in response to a first light-emitting control signal to reset the second node before the data writing stage. The first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to the control end of the driving circuit in response to a first reset signal to reset the first node before the data writing stage. This pixel circuit can reduce or eliminate the influence of residual charge on the data writing accuracy and the potential of the anode of the light-emitting device during the light-emitting stage, thereby optimizing the display effect. For a detailed description of this pixel circuit, please refer to the above description of pixel circuit 10 shown in Figures 2 to 5, and will not be repeated here.

[0146] At least one embodiment of the present disclosure further provides a pixel circuit, the pixel circuit including a driving circuit, a data writing circuit, a threshold compensation circuit, a memory circuit, and a first reset circuit. The driving circuit includes a control end, a first end, and a second end and is configured to control a driving current flowing through a light-emitting element. The data writing circuit is connected to the first end of the driving circuit and configured to write a data signal to the first end of the driving circuit in response to a first scanning signal. The threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit and configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal. The memory circuit is connected to the control end of the driving circuit and a first voltage line and configured to store the compensation signal and hold the compensation signal at the control end of the driving circuit. The first reset circuit is connected to the threshold compensation circuit and the second end of the driving circuit and configured to apply a first reset voltage to the second end of the driving circuit in response to the first reset signal. The pixel circuit is, for example, the pixel circuit 10 shown in Figures 2, 3, and 4, and for detailed explanations of the drive circuit, data write circuit, threshold compensation circuit, memory circuit, and first reset circuit, please refer to the above explanations of the drive circuit 110, data write circuit 120, threshold compensation circuit 130, memory circuit 140, and first reset circuit 160 in the pixel circuit 10 shown in Figures 2, 3, and 4, and they will not be repeated here.

[0147] For example, the driving circuit includes a driving transistor, the gate electrode of the transistor is used as the control end of the driving circuit, the first pole of the transistor is used as the first end of the driving circuit, and the second pole of the transistor is used as the second end of the driving circuit.

[0148] For example, the data writing circuit includes a data writing transistor, the gate electrode of the data writing transistor is connected to the first scanning line to receive the first scanning signal, the first pole of the data writing transistor is connected to the data line to receive the data signal, and the second pole of the data writing transistor is connected to the first pole of the driving transistor.

[0149] For example, the threshold compensation circuit includes a threshold compensation transistor, the gate electrode of the threshold compensation transistor is connected to the second scanning line to receive the second scanning signal, the first pole of the threshold compensation transistor is connected to the second pole of the driving transistor, and the second pole of the threshold compensation transistor is connected to the gate electrode of the driving transistor.

[0150] For example, the memory circuit includes a storage capacitor having a first pole connected to the first voltage line and a second pole connected to the gate electrode of the drive transistor.

[0151] For example, the first reset circuit includes a first reset transistor having a gate electrode connected to a first reset line to receive a first reset signal, a first pole connected to a first reset voltage line to receive a first reset voltage, and a second pole connected to a second pole of the drive transistor.

[0152] For specific methods of connecting the transistors and storage capacitors, refer to the methods of connecting the transistors and storage capacitors in pixel circuit 10 shown in Figures 7, 17, and 21. The drive transistor is, for example, transistor M3, the data write transistor is, for example, transistor M4, the threshold compensation transistor is, for example, transistor M2, the storage capacitor is, for example, storage capacitor Cst, and the first reset transistor is, for example, transistor M2. Detailed description will not be repeated here.

[0153] In some examples, the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit. The first light-emitting control circuit is connected to a first voltage line and a first end of the drive circuit and is configured to apply a first voltage provided by the first voltage line to the first end of the drive circuit in response to a first light-emitting control signal. The second light-emitting control circuit is connected to a second end of the drive circuit and the light-emitting element and is configured to apply a voltage at the second end of the drive circuit to the light-emitting element in response to a second light-emitting control signal. For a detailed description of the first light-emitting control circuit and the second light-emitting control circuit, please refer to the above description of the first light-emitting control circuit 150 and the second light-emitting control circuit 180 in the pixel circuit 10 shown in Figures 2, 3, and 4, and a description thereof will not be repeated here.

[0154] For example, the first light-emitting control circuit includes a first light-emitting control transistor, a gate electrode of the first light-emitting control transistor connected to a first light-emitting control line to receive a first light-emitting control signal, a first electrode of the first light-emitting control transistor connected to a first voltage line, and a second electrode of the second light-emitting control transistor connected to a first end of the drive circuit. For example, the second light-emitting control circuit includes a second light-emitting control transistor, a gate electrode of the second light-emitting control transistor connected to a second light-emitting control line to receive a second light-emitting control signal, a first electrode of the second light-emitting control transistor connected to a second end of the drive circuit, and a second electrode of the second light-emitting element. For specific connections of the transistors, see the connections of the transistors in the pixel circuit 10 shown in FIGS. 7, 17, and 21. The first light-emitting control transistor is, for example, transistor M5, and the second light-emitting control transistor is, for example, transistor M6. Detailed descriptions thereof will not be repeated here.

[0155] In some examples, the pixel circuit may further include a second reset circuit. The second reset circuit is connected to the second light-emitting control circuit and the light-emitting element, and is configured to apply the second reset voltage to the light-emitting element in response to the second reset voltage. For a detailed description of the second reset circuit, please refer to the description of the second reset circuit 190 of the pixel circuit 10 shown in Figures 2, 3, and 4, and will not be described again here.

[0156] For example, the second reset circuit includes a second reset transistor having a gate electrode connected to the second reset line to receive the second reset signal, a first electrode connected to the second reset voltage line to receive the second reset voltage, and a second electrode connected to the second electrode of the second light-emitting control transistor and the light-emitting element. For specific connection methods of the transistors, see the connection methods of the transistors in the pixel circuit 10 shown in Figures 7, 17, and 21. The second light-emitting control transistor is, for example, transistor M7, and detailed description thereof will not be repeated here.

[0157] In some examples, the pixel circuit may further include a third reset circuit. The third reset circuit is connected to the threshold compensation circuit and the control end of the drive circuit, and is configured to apply a third reset voltage to the control end of the drive circuit in response to a third reset signal. For a detailed description of the third reset circuit, please refer to the description of the third reset circuit 210 of the pixel circuit 10 shown in Figures 3 and 4, and will not be described again here.

[0158] For example, the third reset circuit includes a third reset transistor having a gate electrode connected to the third reset line to receive the third reset signal, a first electrode connected to the third reset voltage line to receive the third reset voltage, and a second electrode connected to the control end of the driving circuit. For specific connections of the transistors, see the connections of the transistors in pixel circuit 10 shown in Figures 17 and 21. The third light-emitting control transistor is, for example, transistor M8, and detailed descriptions thereof will not be repeated here.

[0159] For example, in some examples, the pixel circuit may further include a fourth reset circuit. The fourth reset circuit is connected to the first end of the drive circuit and configured to apply a fourth reset voltage to the first end of the drive circuit in response to a fourth reset signal. For a detailed description of the fourth reset circuit, please refer to the description of the fourth reset circuit 220 of the pixel circuit 10 shown in FIG. 4, and a description thereof will not be repeated here.

[0160] For example, the fourth reset circuit includes a fourth reset transistor having a gate electrode connected to the fourth reset line to receive the fourth reset signal, a first electrode connected to the fourth reset voltage line to receive the fourth reset voltage, and a second electrode connected to a first end of the driving circuit. For specific connections of the transistors, see the connections of the transistors in pixel circuit 10 shown in FIG. 21. The fourth reset transistor is, for example, transistor M9, and detailed descriptions thereof will not be repeated here.

[0161] At least one embodiment of the present disclosure further provides a display panel including a plurality of pixel units, each including a pixel circuit provided by any one of the embodiments of the present disclosure, which can reduce or eliminate the influence of residual charges on data writing accuracy and the potential of the anode of the light-emitting device during light-emitting stage, thereby optimizing the display effect.

[0162] 25 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure. As shown in FIG. 25, in some embodiments, the display panel 30 includes a plurality of pixel units 301 arranged, for example, in an array. Each pixel unit 301 includes a pixel circuit 302. The pixel circuit 302 may be a pixel circuit provided by any embodiment of the present disclosure, such as the pixel circuit 10 described above.

[0163] For example, the display panel 30 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or other suitable display panel. Each pixel unit 301 not only includes a pixel circuit 302 but also a light-emitting element (e.g., OLED, QLED).

[0164] For example, the display panel 30 may be a rectangular panel, a circular panel, an oval panel, or a polygonal panel. The display panel 30 may be a flat panel, a curved panel, or a spherical panel. For example, the display panel 30 may have a touch function, i.e., the display panel 30 may be a touch panel. For example, the display panel 30 may be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, or a navigation system. For example, the display panel 30 may be a flexible display panel, which can meet various practical application requirements. For example, the display panel 30 may be applied to a curved screen.

[0165] For clarity and simplicity, the embodiments of the present disclosure do not show all the constituent units of the display panel 30. To achieve the basic functions of the display panel 30, those skilled in the art can provide and arrange other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited thereto.

[0166] Regarding the technical effects of the display panel 30 provided by the above-described embodiments, reference may be made to the technical effects of the pixel circuit 10 provided by the embodiments of the present disclosure, and the description will not be repeated here.

[0167] At least one embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure, which can reduce or eliminate the influence of residual charges on data writing accuracy and the potential of the anode of the light-emitting device during the light-emitting stage, thereby optimizing the display effect.

[0168] FIG. 26 is a schematic block diagram of a display device provided according to some embodiments of the present disclosure. As shown in FIG. 26, the display device 40 includes a display panel 4000, a gate driver 4010, a timing controller 4020, and a data driver 4030. The display panel 4000 includes a plurality of pixel units P defined by a plurality of scan lines GL and a plurality of data lines DL. The display panel 4000 may be, for example, the display panel 30 described above, or any other display panel provided according to any embodiment of the present disclosure. The plurality of scan lines GL include the first scan line SC1, the second scan line SC2, the third scan line SC3, the first light-emitting control line EM1, the second light-emitting control line EM2, etc. described above. The plurality of data lines DL includes the aforementioned data line Vdata. The gate driver 4010 is used to drive a plurality of scanning lines GL, the data driver 4030 is used to drive a plurality of data lines DL, and the timing controller 4020 processes image data RGB input from outside the display device 40, provides the processed image data RGB to the data driver 4030, and outputs a scanning control signal GCS and a data control signal DCS to the gate driver 4010 and the data driver 4030 to control the gate driver 4010 and the data driver 4030.

[0169] For example, the gate driver 4010 can be implemented as a semiconductor chip and integrated into the display panel 4000 to form a GOA circuit.

[0170] For example, the data driver 4030 converts the digital image data RGB input from the timing controller 4020 into data signals using the reference gamma voltage in accordance with a plurality of data control signals DCS from the timing controller 4020. The data driver 4030 provides the converted data signals to a plurality of data lines DL. For example, the data driver 4030 can be realized as a semiconductor chip.

[0171] For example, the timing controller 4020 processes image data RGB input from outside to match the size and resolution of the display panel 4000, and then provides the processed image data to the data driver 4030. The timing controller 4020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from outside the display device 40. The timing controller 4020 provides the generated scan control signals GCS and data control signals DCS to the gate driver 4010 and the data driver 4030, respectively, to control the gate driver 4010 and the data driver 4030.

[0172] The display device 40 may further include other components, such as a signal decoding circuit and a voltage conversion circuit. These components may be, for example, existing conventional components, and will not be described in detail here. The display device 40 may be applied to any product or part with a display function, such as an e-book reader, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. For a detailed description of the display device 40, please refer to the description of the pixel circuit 10 and the display panel 30 in the embodiments of the present disclosure, and a repeated description will not be provided here.

[0173] The following points need to be explained: (1) The drawings of the embodiments of the present disclosure only include structures related to the embodiments of the present disclosure, and common designs may be referenced for other structures. (2) The embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain new embodiments, provided that there is no contradiction.

[0174] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and should be subject to the scope of protection of the claims.

Claims

1. A method for driving a pixel circuit, comprising: the pixel circuit includes a drive circuit, a data write circuit, a threshold compensation circuit, a memory circuit, a first light emission control circuit, and a first reset circuit; The driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current flowing through the light-emitting element; the data writing circuit is connected to a first end of the driving circuit and configured to write a data signal to the first end of the driving circuit in response to a first scanning signal; the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit, and is configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal; the memory circuit is connected to the control end of the drive circuit and a first voltage line, and is configured to store the compensation signal and hold the compensation signal at the control end of the drive circuit; the first light-emitting control circuit is connected to the first voltage line and a first end of the drive circuit, and is configured to apply a first voltage provided by the first voltage line to the first end of the drive circuit in response to a first light-emitting control signal; the first reset circuit is connected to the threshold compensation circuit and configured to apply a first reset voltage to a control end of the drive circuit in response to a first reset signal; a control end of the driving circuit and the memory circuit are connected to a first node, and the first light-emitting control circuit and a first end of the driving circuit are connected to a second node; The method comprises: Before the data writing step, the first reset circuit is turned on in response to the first reset signal, and the first reset voltage is applied to the control end of the driving circuit to reset the first node; the first light-emitting control circuit is turned on in response to the first light-emitting control signal, and the first voltage is applied to the first end of the driving circuit to reset the second node; In the data writing step, the data writing circuit is turned on in response to the first scanning signal, and the data signal is written to the first end of the driving circuit; In a light emitting step, the first light emitting control circuit is turned on in response to the first light emitting control signal, and the light emitting element emits light in response to the driving current.

2. the step of applying the first reset voltage to a control end of the driving circuit by making the first reset circuit conductive in response to the first reset signal, thereby resetting the first node; 2. The method of claim 1, further comprising the steps of: making the first reset circuit conductive in response to the first reset signal; making the threshold compensation circuit conductive in response to the second scan signal; and applying the first reset voltage to a control end of the drive circuit via a path formed by the first reset circuit and the threshold compensation circuit, thereby resetting the first node.

3. the pixel circuit further includes a second light-emitting control circuit and a second reset circuit; the second light-emitting control circuit is connected to the second end of the drive circuit and the light-emitting element, and is configured to apply a voltage at the second end of the drive circuit to the light-emitting element in response to a second light-emitting control signal; the second reset circuit is connected to the second light emission control circuit and the light emitting element, and is configured to apply a second reset voltage to the light emitting element in response to a second reset signal; second ends of the second light-emitting control circuit and the drive circuit are connected to a third node, and the second reset circuit, the second light-emitting control circuit and the light-emitting element are connected to a fourth node; The method comprises: Before the data writing step, the first reset circuit resets the first node, and the first reset circuit applies the first reset voltage to the second end of the driving circuit to reset the third node; and / or 3. The method according to claim 1, further comprising the step of: before the data writing step, the second reset circuit is made conductive in response to the second reset signal, and applying the second reset voltage to the light-emitting element to reset the fourth node.

4. The method according to any one of claims 1 to 3, wherein, before the data writing step, the first node and the second node are reset simultaneously or at different time periods, respectively.

5. 4. The method of claim 3, wherein, when both the third node and the fourth node are reset before the data writing step, the third node and the fourth node are reset simultaneously or at different time periods.

6. 6. The method of claim 5, wherein, prior to the data writing step, a reset period of at least one of the third node and the fourth node overlaps with a reset period of at least one of the first node and the second node.

7. 6. The method of claim 5, wherein, prior to the data writing step, the reset period of the first node, the reset period of the second node, the reset period of the third node, and the reset period of the fourth node do not overlap.

8. After the data writing step and before the light emitting step, the first light emitting control circuit is turned on in response to the first light emitting control signal to apply the first voltage to the first end of the driving circuit and reset the second node; and / or After the data writing step and before the light emitting step, the first reset circuit is made conductive in response to the first reset signal to apply the first reset voltage to the second end of the driving circuit to reset the third node; and / or 4. The method of claim 3, further comprising the step of: after the data writing step and before the light emitting step, the second reset circuit is made conductive in response to the second reset signal, applying the second reset voltage to the light emitting element, and resetting the fourth node.

9. 9. The method of claim 8, wherein after the data writing step and before the light emitting step, at least two of the second node, the third node, and the fourth node are reset simultaneously or at different time periods.

10. the drive circuit includes a drive transistor, the data write circuit includes a data write transistor, the threshold compensation circuit includes a threshold compensation transistor, the first light emission control circuit includes a first light emission control transistor, and the first reset circuit includes a first reset transistor; the driving transistor, the data writing transistor, the first light-emitting control transistor, and the first reset transistor are first type transistors; The method of any one of claims 1 to 9, wherein the threshold compensation transistor is a transistor of a second type different from the first type.

11. The method of claim 10 , wherein the first type of transistor comprises a P-type thin film transistor and the second type of transistor comprises an N-type thin film transistor.

12. 12. The method according to claim 10, wherein the pixel circuit further includes a leakage prevention circuit connected to a control end of the driving circuit, the threshold compensation circuit, and the memory circuit, the leakage prevention circuit being configured to suppress leakage of the control end of the driving circuit.

13. 13. The method of claim 12, wherein the leakage protection circuit includes a leakage protection transistor, the leakage protection transistor being the second type of transistor.

14. A pixel circuit including a drive circuit, a data write circuit, a threshold compensation circuit, a memory circuit, and a first reset circuit, The driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current flowing through the light-emitting element; the data writing circuit is connected to a first end of the driving circuit and configured to write a data signal to the first end of the driving circuit in response to a first scanning signal; the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit, and is configured to write a compensation signal based on the data signal to the control end of the driving circuit in response to a second scanning signal; the storage circuit is connected to the control end of the driving circuit and a first voltage line, and is configured to store the compensation signal and hold the compensation signal at the control end of the driving circuit, the control end of the driving circuit and the storage circuit are connected to a first node; the first reset circuit is connected to the threshold compensation circuit and the second end of the drive circuit, and is configured to apply a first reset voltage to the second end of the drive circuit in response to a first reset signal.

15. the driving circuit includes a driving transistor, a gate electrode of the driving transistor is used as a control end of the driving circuit, a first pole of the driving transistor is used as a first end of the driving circuit, and a second pole of the driving transistor is used as a second end of the driving circuit; the data write circuit includes a data write transistor, a gate electrode of the data write transistor is connected to a first scan line to receive the first scan signal, a first pole of the data write transistor is connected to a data line to receive the data signal, and a second pole of the data write transistor is connected to the first pole of the driving transistor; the threshold compensation circuit includes a threshold compensation transistor, a gate electrode of the threshold compensation transistor is connected to a second scan line to receive the second scan signal, a first pole of the threshold compensation transistor is connected to a second pole of the driving transistor, and the second pole of the threshold compensation transistor is connected to a gate electrode of the driving transistor; the memory circuit includes a storage capacitor, a first pole of the storage capacitor connected to the first voltage line, and a second pole of the storage capacitor connected to a gate electrode of the drive transistor; 15. The pixel circuit of claim 14, wherein the first reset circuit includes a first reset transistor, a gate electrode of the first reset transistor connected to a first reset line to receive the first reset signal, a first pole of the first reset transistor connected to a first reset voltage line to receive the first reset voltage, and a second pole of the first reset transistor connected to a second pole of the drive transistor.

16. further including a first light-emitting control circuit and a second light-emitting control circuit; the first light-emitting control circuit is connected to the first voltage line and a first end of the driving circuit, and is configured to apply a first voltage provided by the first voltage line to the first end of the driving circuit in response to a first light-emitting control signal; the first light-emitting control circuit and the first end of the driving circuit are connected to a second node; 16. The pixel circuit of claim 14, wherein the second light-emitting control circuit is connected to the second end of the drive circuit and the light-emitting element, and is configured to apply a voltage at the second end of the drive circuit to the light-emitting element in response to a second light-emitting control signal, and the second light-emitting control circuit and the second end of the drive circuit are connected to a third node.

17. the first light-emitting control circuit includes a first light-emitting control transistor, a gate electrode of the first light-emitting control transistor is connected to a first light-emitting control line to receive the first light-emitting control signal, a first electrode of the first light-emitting control transistor is connected to the first voltage line, and a second electrode of the first light-emitting control transistor is connected to a first end of the driving circuit; 17. The pixel circuit of claim 16, wherein the second light-emitting control circuit includes a second light-emitting control transistor, a gate electrode of the second light-emitting control transistor is connected to a second light-emitting control line to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is connected to a second end of the drive circuit, and a second electrode of the second light-emitting control transistor is connected to the light-emitting element.

18. a second reset circuit connected to the second light emission control circuit and the light emitting element, the second reset circuit configured to apply a second reset voltage to the light emitting element in response to a second reset voltage; the second reset circuit, the second light-emitting control circuit, and the light-emitting element are connected to a fourth node; 18. The pixel circuit of claim 17, wherein the potential of the third node after being reset by the first reset circuit is higher than the potential of the fourth node after being reset by the second reset circuit.

19. 19. The pixel circuit of claim 18, wherein the second reset circuit includes a second reset transistor, a gate electrode of the second reset transistor connected to a second reset line to receive the second reset signal, a first electrode of the second reset transistor connected to a second reset voltage line to receive the second reset voltage, and a second pole of the second reset transistor connected to the second pole of the second light-emitting control transistor and the light-emitting element.

20. a third reset circuit connected to the threshold compensation circuit and a control end of the driving circuit, configured to apply a third reset voltage to the control end of the driving circuit in response to a third reset signal; the potential of the first node after being reset by the third reset circuit is lower than the potential of the third node after being reset by the first reset circuit; 20. The pixel circuit according to claim 18, wherein the potential of the first node after being reset by the third reset circuit is equal to or lower than the potential of the fourth node after being reset by the second reset circuit.

21. 21. The pixel circuit of claim 20, wherein the third reset circuit includes a third reset transistor, a gate electrode of the third reset transistor connected to a third reset line to receive the third reset signal, a first pole of the third reset transistor connected to a third reset voltage line to receive the third reset voltage, and a second pole of the third reset transistor connected to a control end of the driving circuit.

22. a fourth reset circuit connected to the first end of the drive circuit and configured to apply a fourth reset voltage to the first end of the drive circuit in response to a fourth reset signal; the potential of the second node after being reset by the fourth reset circuit is higher than the potential of the first node after being reset by the third reset circuit; the potential of the second node after being reset by the fourth reset circuit is higher than the potential of the third node after being reset by the first reset circuit; 22. The pixel circuit according to claim 20, wherein the potential of the second node after being reset by the fourth reset circuit is higher than the potential of the fourth node after being reset by the second reset circuit.

23. 23. The pixel circuit of claim 22, wherein the fourth reset circuit includes a fourth reset transistor, a gate electrode of the fourth reset transistor connected to a fourth reset line to receive the fourth reset signal, a first pole of the fourth reset transistor connected to a fourth reset voltage line to receive the fourth reset voltage, and a second pole of the fourth reset transistor connected to a first end of the driving circuit.

24. A display panel comprising a plurality of pixel units, each pixel unit comprising the pixel circuit according to any one of claims 14 to 23.

25. A display device comprising the display panel of claim 24.

Images