Adaptive Low Density Parity Check Decoder

Abstract

This disclosure describes apparatus and methods for implementing an adaptive low-density parity-check (LDPC) decoder. In various aspects, an adaptive LDPC decoder (130) processes a first portion of data using first parameters effective to change the status of the LDPC decoder (704). The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder (706). The LDPC decoder then processes a second portion of the data using the second parameters with the LDPC decoder (708) and provides decoded data for the channel based on at least the processing of the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters (712). By adaptively modifying the decoding parameters based on the status of the decoder, the adaptive LDPC decoder may decode the channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

Description

[Technical Field]

[0001] [Background technology] Many computing and electronic devices transfer data to provide various device functions. Data transfer systems, such as data transmission systems and data storage systems, are typically characterized as data channels. In data transmission systems, data may be transmitted over channels such as printed circuit board (PCB) traces, wire cables, fiber optic cables, and wireless protocols. In data storage systems, the storage media to which data is written and from which data is read may be considered the data channel of the data storage system. Thus, a data storage data channel may include magnetic storage media, optical storage media, holographic storage media, solid-state storage media, or the like.

[0002] The efficiency and reliability of a data channel can be determined by many factors, including the signal-to-noise ratio (SNR) of the channel. For example, a storage medium with a high SNR generally allows for more accurate storage and recovery of data. Conversely, a storage medium with a low SNR may have a higher rate of data errors, such as misreading or being unable to recover data. Similarly, the quality of a digital data communication channel is determined by the SNR of the channel, where a communication channel with a high SNR can communicate data quickly and accurately, while a communication channel with a low SNR may have difficulty communicating data through the channel (e.g., data packets may be dropped).

[0003] Error correcting codes (ECCs) can provide a way to reduce errors in data storage and transmission by introducing data redundancy into a communication channel, usually in the form of additional bits that allow the validity of the original data to be checked. ECCs utilize codewords, which are specific patterns of bits or symbols within a storage medium or transmission signal, to group data into chunks and check for errors. However, most ECCs are implemented using static configurations that may be suboptimal or may not be able to account at all for variations in the data or the channel through which the data is transmitted. This can result in excessive ECC-related processing of the data or an inability to complete data decoding. As a result, communication or storage systems with static ECC configurations may be inefficient, reduce data throughput, suffer data loss, or consume excess power. Summary of the Invention

[0004] This summary is provided to introduce subject matter that is further described in the detailed description and drawings. As such, this summary should not be construed as describing essential features, nor should it be used to limit the scope of the claimed subject matter.

[0005] In some aspects, a method of adaptive low-density parity check (LDPC) decoding includes processing, by an LDPC decoder, a first portion of data of a channel using first parameters effective to alter a status of the LDPC decoder. The method selects second parameters of the LDPC decoder based on the status of the LDPC decoder and processes a second portion of data using the second parameters (e.g., during the same or one iteration). The method then provides decoded data for the channel based on at least the processing of the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. In some aspects, the adaptive decoder may determine multiple data portions or subsets from received data and process each of the multiple portions using adaptively selected or determined decoding parameters. By adaptively altering the decoding parameters based on the decoder status, the adaptive LDPC decoder may decode channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

[0006] In another aspect, an apparatus includes a data interface configured for communicating data over a channel, an LDPC decoder, and an adaptive controller for the LDPC decoder. The adaptive controller is configured to process a first block of data received from the channel using first parameters by the LDPC decoder effective to modify a metric of the LDPC decoder. The controller selects second parameters for the LDPC decoder based on the metric of the LDPC decoder and processes a second block of data by the LDPC decoder using the second parameters. The adaptive controller provides decoded data for the channel from the LDPC decoder based on at least the processing of the first block using the first parameters and the processing of the second block using the second parameters.

[0007] In yet another aspect, a system-on-chip (SoC) is described that includes a media interface for accessing a storage medium of a storage system, a host interface for communicating with a host system, an LDPC decoder, and an adaptive controller for the LDPC decoder. The adaptive controller is configured to process a first block of data received from the channel using first parameters by the LDPC decoder, the first parameters being effective to change a status of the LDPC decoder. The controller selects second parameters for the LDPC decoder based on the status of the LDPC decoder, and processes a second block of data using the second parameters by the LDPC decoder. The adaptive controller then provides decoded data for the channel from the LDPC decoder based on at least the processing of the first block of data using the first parameters and the processing of the second block of data using the second parameters.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0009] The accompanying figures and the detailed description below set forth details of one or more implementations of an adaptive low-density parity-check (LDPC) decoder. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. Use of the same reference number in different instances in the description and figures indicates similar elements. [Figure 1] 1 illustrates an exemplary operating environment having a system in which an adaptive LDPC decoder is implemented in accordance with one or more aspects of the present disclosure. [Figure 2] 1 illustrates an example of a data channel in which a decoder can implement aspects of adaptive LDPC decoding. [Figure 3] 1 illustrates an example configuration of a storage system including an adaptive LDPC decoder implemented in accordance with one or more aspects. [Figure 4] 1 illustrates an exemplary Tanner graph for LDPC data that may be processed by an adaptive LDPC decoder. [Figure 5] 1 illustrates an example algorithm that an adaptive LDPC decoder can implement in accordance with various aspects. [Figure 6] 1 illustrates an exemplary algorithm for adaptive LDPC decoding with thresholds adjusted based on the syndrome of the LDPC decoder. [Figure 7] 1 illustrates an example method for adaptive LDPC decoding in accordance with one or more aspects. [Figure 8] 1 illustrates an exemplary method for implementing adaptive LDPC decoding based on a decoder's syndrome. [Figure 9] 9A and 9B show an exemplary method for selecting decoding parameters of an adaptive LDPC decoder based on the status of the decoder. [Figure 10]1 illustrates an exemplary method for selecting parameters of an adaptive LDPC decoder based on results of processing data using a combination of parameters. [Figure 11] 1 illustrates an exemplary system-on-chip (SoC) environment in which aspects of adaptive LDPC decoding may be implemented. [Figure 12] 1 illustrates an exemplary storage system controller in which an adaptive LDPC decoder is implemented in accordance with one or more aspects. DETAILED DESCRIPTION OF THE INVENTION

[0010] Many computing and electronic devices transfer data to provide various device functions. Data transfer systems, such as data transmission systems and data storage systems, are typically characterized as data channels. Generally, error correction codes (ECCs) can provide a way to reduce errors in data storage and transmission by introducing data redundancy into the communication channel, usually in the form of additional bits that allow for checking the validity of the original data. ECCs utilize codewords, which are specific patterns of bits or symbols within a storage medium or transmission signal, to group data into chunks and check for errors. However, most ECCs are implemented using static configurations (e.g., preset static rules) that may be suboptimal or may not account at all for variations in the data or the channel through which the data is transferred, resulting in excessive ECC-related processing of the data. As a result, communication or storage systems with static ECC configurations may be inefficient, reduce data throughput, suffer data loss, or consume excess power.

[0011] This disclosure describes apparatus and techniques for adaptive low-density parity-check (LDPC) decoding. In contrast to the aforementioned ECC techniques, the described apparatus and techniques may implement an adaptive LDPC decoder that dynamically changes or selects decoding rules (e.g., thresholds) based on the decoder's status, allowing the decoder to adapt on-the-fly during the decoding process. By doing so, the adaptive LDPC decoder may achieve faster convergence in a bit-flipping decoder, improve decoder throughput, reduce decoder latency, or reduce the average number of processing iterations required to decode data. Generally, the described aspects may implement an adaptive decoding process in which a bit-flipping or symbol-flipping decoder can adopt dynamic inversion rules within an iteration of the decoding process. In some implementations of adaptive decoding, instead of the decoder using fixed rule values ​​throughout a given iteration for all bits in the LDPC code of the data being decoded, the decoding rules (e.g., inversion thresholds) adaptively change at each point in the decoding based on the decoder's status (e.g., metrics) (e.g., real-time status within each decoding iteration).

[0012] In various aspects, the decoder status may include one or more of a syndrome weight, a column weight, an LDPC code being decoded, an iteration index, a block index, and whether a bit (or symbol) is inverted or not (e.g., inversion status), etc. Thus, the adaptive controller of the LDPC decoder may set or select a decoding rule (e.g., an inversion threshold) based on the real-time status of the decoder in addition to the iteration number or bit inversion status. In some aspects, the adaptive controller uses the sum of the syndrome values ​​(current syndrome weight) in the LDPC decoder as the decoder status for adaptively selecting or setting a decoding rule. In other words, as the decoder's current syndrome weight changes in real time, the adaptive controller of the LDPC decoder changes the decoding rule (e.g., an inversion threshold) in the decoder in real time or on the fly during a decoding iteration. Alternatively or additionally, the adaptive LDPC decoder may use the status to select or set different decoding rules for decoding different blocks in the LDPC decoder. For example, a block in a decoder may include multiple bits in an LDPC code having bit nodes of the same or different types or degrees. In one implementation, the adaptive controller can divide the data to be decoded, or the entire LDPC code, into a number M of blocks. The adaptive controller can determine any suitable number of blocks of data (e.g., portions or subsets of data), which may range from at least two blocks to several blocks or tens of blocks, depending on the complexity of the LDPC decoder. One block may contain or correspond to one type of bit, while another block may contain or correspond to another type of bit. In general, the number of bit types in the data being decoded may be the same as or different from the number of blocks. Thus, the adaptive LDPC decoder may be configured to divide or form bits of data into two types (T=2), but there are three different blocks (M=3).As an example, multiple blocks may cover the same type, such as two blocks covering a first type, one block covering a second type, etc. These are just a few examples of adaptive LDPC decoders, and are described in detail along with others throughout this disclosure.

[0013] In various aspects of adaptive LDPC decoding, the adaptive LDPC decoder processes a first portion of data using first parameters effective to change the status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of data using the second parameters with the LDPC decoder and provides decoded data for the channel based on at least the processing of the first portion of data using the first parameters and the processing of the second portion of data using the second parameters. In some aspects, the adaptive decoder may determine multiple data portions or subsets from the received data and process each of the multiple portions using adaptively selected or determined decoding parameters. By adaptively modifying the decoding parameters based on the status of the decoder, the adaptive LDPC decoder may decode the channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

[0014] The following discussion describes an operating environment, techniques that may be employed in that operating environment, and a system-on-chip (SoC) that components of that operating environment may be embodied in. In the context of this disclosure, references to the operating environment or various components are made by way of example only.

[0015] (Operating environment) 1 illustrates an exemplary operating environment 100 having a host system 102 capable of storing, accessing, or communicating various forms of data or information. Examples of host systems 102 may include a laptop computer 104, a desktop computer 106, and a server 108, any of which may be configured as a user device, a computing device, or as part of a storage network, a data storage center, cloud storage, or the like. Further examples of host system 102 (not shown) may include tablet computers, set-top boxes, data storage devices, wearable smart devices, televisions, content streaming devices, high-definition multimedia interface (HDMI) media sticks, smart appliances, home automation controllers, smart thermostats, Internet-of-Things (IoT) devices, mobile-internet devices (MIDs), network-attached-storage (NAS) drives, aggregate storage systems, gaming consoles, automotive entertainment devices, automotive computing systems, and automotive control modules (e.g., engine or powertrain control modules), etc. Generally, host system 102 may communicate or store data for any suitable purpose, such as enabling functionality of a particular type of device, providing a user interface, enabling network access, implementing gaming applications, playing media, providing navigation, editing content, or providing data storage.

[0016] The host system 102 includes a processor 110 and a computer-readable medium 112. The processor 110 may be implemented as any suitable type or number of processors, single-core or multi-core, for executing instructions or commands of the host system's 102 operating system or other applications. In aspects, the host system's processor 110 may execute tenants, services, or workloads of a data storage system or data storage center. The computer-readable medium 112 (CRM 112) includes the host system's 102 memory (not shown) and storage system 114. The host system's 102 memory may include any suitable type or combination of volatile or non-volatile memory. For example, the host system's 102 volatile memory may include various types of random-access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), or the like. Non-volatile memory may include read-only memory (ROM), electronically erasable programmable ROM (EEPROM), solid-state storage media, or flash memory.

[0017] The storage system 114 of the host system 102 may be configured as any suitable type of data storage system, such as a data storage center, storage device, storage drive, storage array, storage volume, or the like. Although described in the context of the host system 102, the storage system 114 may be implemented separately as part of a larger storage collective, such as a network-attached storage device, an external storage drive, a data storage center, a server farm, or a virtualized storage system (e.g., cloud-based storage or service), or as a standalone device. Examples of the storage system 114 include magnetic storage media drives 116, non-volatile memory express (NVMe) solid-state drives (not shown), peripheral component interconnect express (PCIe) solid-state drives 118, solid-state drives 120 (SSDs 120), and storage arrays 122, which may be implemented using any combination of storage devices or drives.

[0018] The storage system 114 includes a storage medium 124 and a storage medium controller 126 (storage controller 126) for managing various operations or functionality of the storage system 114. The storage medium 124 may include or be formed from a non-volatile memory device on which data 128 or information for the host system 102 is stored. The storage medium 124 may be implemented using any type or combination of storage media, which may include optical storage media, magnetic storage media, holographic storage media, solid-state storage media, or the like. In aspects, the solid-state memory media may include one of flash memory, NAND flash, RAM, DRAM (e.g., for caching), SRAM, or the like. For example, storage media 124 of storage system 114 may include NAND flash memory, single-level cell (SLC) flash memory, multi-level cell (MLC) flash memory, triple-level cell (TLC) flash, quad-level cell (QLC) flash, NOR cell flash, or any combination thereof, which memories, individually or in combination, may store data associated with users, applications, tenants, workloads, services, and / or operating systems of host system 102.

[0019] Generally, the storage controller 126 manages the operation of the storage system 114 and enables the host system 102 to access the storage medium 124 for storage of data. The storage controller 126 may be implemented through any suitable combination of hardware, firmware, or software to provide various functionality of the storage system 114. The storage controller 126 may manage or perform internal tasks or operations associated with the storage medium 124, which may include data placement, data-to-block mapping, wear leveling, data caching, data migration, garbage collection, thermal management (e.g., throttling), power management, or the like. As such, the storage controller 126 may receive read requests (e.g., host I / O) from the host system 102 for data access and queue (or generate) internal commands (e.g., I / O) associated with the internal operations of the storage medium 124. Generally, storage controller 126 may perform media I / O for accessing storage medium 124, corresponding to scheduled host I / O for data access (e.g., host write or read requests) and / or internal I / O for internal operations or tasks associated with storage medium 124.

[0020] In this example, storage controller 126 also includes adaptive LDPC decoder 130 (LDPC decoder 130), decoding parameters 132, decoding metrics 134, and adaptive decoder controller 136 (adaptive controller 136). Although not shown, LDPC decoder 130 may include one or more processing blocks for implementing decoding of LDPC-encoded data, such as data received over a channel (e.g., a storage channel or a communication channel from a transmitter). In other configurations, LDPC decoder 130 and adaptive controller 136 may be implemented in combination as an adaptive LDPC decoder. Thus, adaptive LDPC decoder 130 may include a controller or control circuitry configured to implement various aspects of adaptive LDPC decoding. In some implementations, decoding parameters 132 may include a set of decoding rules or thresholds stored in a lookup table, which may be implemented in memory or hardware associated with LDPC decoder 130.

[0021] In various aspects, LDPC decoder 130 and / or adaptive controller 136 use parameters 132 and metrics 134, which may be used to dynamically configure parameters 132 for decoding data read from storage medium 124 of storage system 114. Generally, LDPC decoder 130 and adaptive controller 136 may implement adaptive decoding of ECC data read from storage medium 124 of storage system 114. In some cases, LDPC decoder 130 processes a first portion of the data, and adaptive controller 136 obtains status or metrics from LDPC decoder 130 that are changed or updated in response to processing the first portion of the data. Adaptive controller 136 then selects or modifies parameters 132 based on the status or metrics of the LDPC decoder for use when decoding a second portion of the data. The selected decoding parameters provided by the adaptive controller 136 may enable the LDPC decoder 130 to decode data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

[0022] For example, LDPC decoder 130 processes a first portion of data received from a channel using a first parameter effective to modify the status (e.g., syndrome weights) of the LDPC decoder. Adaptive controller 136 selects a second parameter of the LDPC decoder, such as a bit-flip threshold or a symbol-flip threshold, based on the status of the LDPC decoder. LDPC decoder 130 then processes the second portion of data using the second parameter with the LDPC decoder and provides decoded data for the channel based on at least the processing of the first portion of data using the first parameter and the processing of the second portion of data using the second parameter. By adaptively modifying the decoding parameters based on the status of the decoder, the LDPC decoder may decode the channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance. This is just one example of adaptive LDPC decoding; other examples of adaptive LDPC decoding are described throughout this disclosure.

[0023] Returning to FIG. 1 , host system 102 may also include I / O ports 138, graphics processing unit 140 (GPU 140), and data interface 142. Generally, I / O ports 138 allow host system 102 to interact with other devices, peripherals, or a user. For example, I / O ports 138 may include or be coupled to a universal serial bus, a human interface device, audio input, audio output, or the like. GPU 140 processes and renders graphics-related data for host system 102, such as user interface elements for an operating system, application, or the like. In some cases, GPU 140 accesses a portion of local memory to render graphics or includes dedicated memory for rendering graphics (e.g., video RAM) for host system 102.

[0024] The data interface 142 of the host system 102 provides connectivity to one or more networks and other devices connected to these networks. The data interface 142 may include a wired interface, such as an Ethernet or fiber optic interface, for communication over a local network, an intranet, or the Internet. Alternatively or additionally, the data interface 142 may include a wireless interface that facilitates communication over a wireless network, such as a wireless LAN, a wide-area wireless network (e.g., a cellular network), and / or a wireless personal-area network (WPAN). Any data communicated through the I / O port 138 or the data interface 142 may be decoded using aspects described herein. For example, the decoder of the data interface may be configured as an adaptive LDPC decoder and implement one or more of the described techniques for decoding data received over a communication channel. Alternatively or additionally, data read from storage system 114 of host system 102 may be decoded and / or re-encoded for communication via data interface 142 according to one or more aspects of adaptive LDPC decoding.

[0025] FIG. 2 illustrates at 200 an example data channel over which a decoder can implement aspects of adaptive LDPC decoding. Generally, the illustrated data channel may represent a medium for transmitting data to a receiver or a medium where data is stored and read from. In some cases, the data channel in FIG. 2 represents a medium over which encoded data is subject to noise or interference, such as a wired medium, a wireless medium, an optical medium, a storage medium, or the like. Thus, noise or interference in the data channel may corrupt (e.g., cause coding errors in) any encoded and / or modulated data transmitted through or stored in the data channel by an electronic device. As described herein, aspects of adaptive LDPC decoding may improve decoder performance to correct such errors with fewer decoding iterations, reduced decoder latency, or a higher error correction success rate.

[0026] In the context of the data channel of FIG. 2 , user information 202 is encoded by an encoding mechanism, which in this example is shown as an LDPC encoder 204. The user information 202 may include any suitable type of information or data (e.g., message information, message vector) that can be grouped into units of k symbols, where each symbol may be binary, ternary, quaternary, or any other suitable type of data. For brevity, implementations of the present disclosure are described in terms of binary bits or symbols (e.g., LDPC codes over Galois fields). For example, the described aspects may be applied to symbol-reversal decoders for non-binary LDPC codes, such as LDPC codes over a Galois field GF(q) where the field size q is greater than 2. Note that LDPC codes over GF(2) include the binary LDPC codes described throughout this disclosure. In the process of encoding the user information 202, any suitable code may be used by the encoding block to achieve a number of different results. In this example, LDPC encoder 204 encodes user information 202 using an LDPC code to produce one or more codewords (not shown) of encoded information. LDPC encoder 204 may be configured to implement various LDPC encoding schemes or to produce codewords of one or more predetermined lengths. In aspects, LDPC encoder 204 provides or transmits the codewords to modulator 206, which prepares the codewords for transmission over channel 208. By way of example, modulator 206 may modulate the codewords using phase-shift keying, frequency-shift keying, quadrature amplitude modulation, or any suitable modulation technique to convert the codewords into one or more information-bearing signals. The encoded or modulated data may then be written to or stored in channel 208, which represents a medium through which the information-bearing signals pass (e.g., optical or electrical signals) or on which the information-bearing signals are stored.For example, channel 208 may represent a wired or wireless medium of a communication system, an optical communication system (e.g., fiber or free space), a solid-state medium (e.g., RAM, ROM), a magnetic medium (e.g., hard disk, tape drive), or an optical medium (e.g., DVD, holographic) storage medium on which information-bearing signals may be stored.

[0027] Due to interfering signals and other types of noise and phenomena, channel 208 may affect or corrupt the information-bearing signal generated by modulator 206. Thus, the waveform of the information-bearing signal received by demodulator 210 may differ from the original waveform of the information-bearing signal entering channel 208. Demodulator 210 demodulates the information-bearing signal received through or from channel 208 and may implement filtering, multiplication by a periodic function, or any suitable demodulation technique corresponding to the type of modulation implemented by modulator 206. Due to the non-ideal nature (e.g., noise) of channel 208, the result of the demodulation may include demodulated bits or a bit stream (e.g., a received vector) that may contain errors due to channel corruption.

[0028] To recover data from the demodulated signal (e.g., a received vector), the decode block 212 may decode the bit stream or vector to detect and / or remove errors resulting from the channel 208. In this example, the decode block 212 includes an adaptive LDPC decoder 130, a processing block 214, decoding parameters 132 (parameters 132), decoding metrics 134 (metrics 134), and an adaptive controller 136. Generally, the LDPC decoder 130 may detect and / or correct errors in data received from a channel, such as encoded information read from a storage medium. The LDPC decoder 130 may implement an iterative decoding algorithm (e.g., flooding decoding, hierarchical decoding, bit-flipping decoding, symbol-flipping decoding) to detect and / or correct errors in the demodulated data or vector provided by the demodulator 210. In aspects, the LDPC decoder 130 is configured as a bit-flipping decoder that iteratively decodes the noisy data received from the channel 208. The LDPC decoder 130 may provide information such as an LDPC vector or a bit-flipping vector to the processing block 214. In general, the processing block 214 can receive any relevant information from the LDPC decoder 130. In some cases, the processing block 214 receives information from the LDPC decoder 130 for calculations to be performed during the decoder iterations. In some implementations, the LDPC information is received in vector form (e.g., an LDPC vector), which may include or correspond to the number of unsatisfied check vectors (NUC vectors) for each bit node or each group of bit nodes (e.g., bits of a codeword) in the LDPC decoder. In aspects, processing block 214 may convert the LDPC vector 508 (or NUC vector) and bit reversal vector 510 into a decoding metric 134 (e.g., decoder status) of the LDPC decoder 130, which may include a NUC status, where the NUC status may indicate the number of unsatisfied checks for a bit node or block of bit nodes.

[0029] When utilizing such an iterative algorithm, the LDPC decoder 130 may perform multiple iterations of the bit-flip operation until the output of the adaptive LDPC decoder 130 converges to a valid codeword. As described herein, during the decoding process, the adaptive controller 136 may select or modify the decoding parameters 132 based on the decoding metrics 134 (e.g., status, state information) of the LDPC decoder 130 during the decoding iterations. For example, the adaptive controller 136 may obtain the metrics 134 (e.g., LDPC state information, syndrome weights) from the LDPC decoder 130 during the decoding iterations and select one or more different bit-flip thresholds for decoding the remaining bits in the iterations of the decoding process. Once the LDPC decoder 130 converges to a valid codeword or reaches a maximum iteration limit, the adaptive LDPC decoder 130 provides decoded information 216, which may correspond to the original user information 202 transmitted over the channel 208 if the adaptive LDPC decoder successfully corrects errors.

[0030] 3 illustrates at 300 an exemplary configuration of a storage system including an adaptive LDPC decoder implemented in accordance with one or more aspects. In this example, storage controller 126 of storage system 114 includes instances of LDPC decoder 130, processing block 214, and adaptive controller 136, which may be implemented as or part of a decode block of storage controller 126. Storage controller 126 may be configured to manage or enable access to any suitable type of storage medium 124 from host system 102 and may include or implement corresponding functionality, such as a flash transfer layer (not shown) or the like. Adaptive decoder 130 and / or adaptive controller 136 may interact with storage controller 126 or components thereof to implement aspects of the adaptive LDPC decoding.

[0031] In this example, the LDPC decoder 130 and adaptive controller 136 are shown in the context of a storage system 114 implemented as an instance of a solid-state storage drive (SSD) 120. The SSD 120 may be coupled to any suitable host system 102 and implemented using a storage medium 124 including multiple NAND flash dies (not shown). Alternatively, the exemplary storage system may be implemented using magnetic storage media, optical storage media, or the like. While shown as components of the SSD 120, the adaptive LDPC decoder 130, processing block 214, and / or adaptive controller 136 may be implemented separately from or external to the storage system 114. In some cases, the adaptive LDPC decoder 130 or adaptive controller 136 is implemented as part of a storage media accelerator or aggregate storage controller coupled between the host system 102 and one or more storage systems 114.

[0032] Generally, operation of SSD 120 is enabled or managed by an instance of storage controller 126, which in this example includes a host interface 302 that enables communication with host system 102 and a media interface 304 that enables access to storage media 124. The host interface 302 may be configured to implement any suitable type of storage interface or protocol, such as serial advanced technology attachment (SATA), universal serial bus (USB), PCIe, advanced host controller interface (AHCI), NVMe, NVM-over Fabric (NVM-OF), NVM host controller interface specification (NVMHCIS), small computer system interface (SCSI), serial attached SCSI (SAS), secure digital I / O (SDIO), Fibre Channel, any combination of these protocols (e.g., M.2 or next generation form factor (NGFF) unified interface), or the like. Alternatively or additionally, the media interface 304 may implement any suitable type of storage media interface, such as a flash interface, a flash bus channel interface, a NAND channel interface, a physical page addressing (PPA) interface, a read / write channel interface (e.g., for magnetic media), or the like.

[0033] In various aspects, the components of storage controller 126 provide a data path through the controller between a host interface 302 to host system 102 and a media interface 304 to storage medium 124. In this example, storage controller 126 includes a processor core 306 for executing a kernel, firmware, or driver for implementing the functionality of storage controller 126. In some cases, processor core 306 may execute processor-executable instructions for implementing adaptive LDPC decoder 130 or adaptive controller 136 of storage controller 126. Alternatively or additionally, adaptive LDPC decoder 130 or adaptive controller 136 may be executed from or on ML-specific hardware, an AI engine, or processor core.

[0034] 3, fabric 308 of storage controller 126, which may include control and data buses, operatively couples and enables communication between components of storage controller 126. For example, adaptive LDPC decoder 130 or processing block 214 may communicate with host interface 302, processor core 306 (e.g., firmware), or media interface 304 to exchange data, decoding information, commands, or I / O within storage controller 126. In aspects, adaptive LDPC decoder 130 may implement adaptive decoding of information (e.g., codewords) read from storage medium 124, which may be performed in response to a read request by host system 102. Generally, adaptive LDPC decoder 130 and processing block 214 may use adaptive controller 136 to implement aspects of adaptive decoding, in which decoding rules or thresholds of the LDPC decoder are dynamically adjusted or selected during a decoding iteration based on the LDPC decoder's status, state information, or metrics to provide error detection and / or error correction of data read from storage medium 124. Static random-access memory 310 (SRAM 310) of storage controller 126 may store processor-executable instructions or code for storage controller firmware or drivers, which may be executed by processor core 306. Storage controller 126 may also include a dynamic random-access memory (DRAM) controller 312 and associated DRAM 314 for storing or caching various data as storage controller 126 moves data between host system 102, storage medium 124, and other components of the storage controller.

[0035] 4 illustrates at 400 an exemplary Tanner graph for LDPC data that may be processed by an adaptive LDPC decoder. In the context of a storage or communication system, data received from a channel may include encoded data or codewords that LDPC decoder 130 (not shown) attempts to decode to provide or recreate the original data written or transmitted to the channel. In the context of a storage system, when data is read from a storage medium such as a NAND flash memory, the data may contain bit errors (e.g., a 0 flipped to a 1, a 1 flipped to a 0). Generally, an encoder may apply an LDPC code to the data before it is transmitted over a communication channel (e.g., before writing to the storage medium), and adaptive LDPC decoder 130 may decode the LDPC-encoded data after the encoded data is received from the communication channel (e.g., after reading from the storage medium). In aspects, the adaptive LDPC decoder is implemented as a bit-flipping LDPC decoder, whereby bits are inverted when decoding encoded data, and erroneous bits can potentially be flipped back to their original value when transmitted or written to the channel.

[0036] As an example, as shown in FIG. 4, an LDPC code is typically defined by a parity check matrix H 402, such as a codeword of encoded bits or the like. The LDPC code may be represented as a bipartite Tanner graph 404 of the encoded bits 406, where each bit "1" in the parity check matrix H 402 is represented by an edge between a corresponding variable node 408 (column) and a corresponding check node 410 (row). In some cases, the variable nodes 408 may also be referred to as bit nodes. During the decoding process, the adaptive LDPC decoder 130 may calculate a syndrome vector 412 (e.g., "syndrome") as shown in Equation 1. Syndrome = H z (where z represents the received bit vector) Equation 1: LDPC Syndrome

[0037] For example, the received bit vector z may represent a noisy version of the encoded data to be written or stored in a channel such as a solid-state or magnetic storage medium. The weight of the syndrome vector may be referred to as the syndrome weight, which may be calculated as the sum of the entries (0s and 1s) of the syndrome vector. As shown in FIG. 4, each circular node corresponds to an encoded bit or variable node 408. The number of lines between one variable node 408 (or bit node) and one square check node 410 may be referred to as the "type of bit," which may also be referred to as the degree of the bit node (or variable node degree). The degree of this type of bit or bit node is equal to the number of 1s in each column of the parity-check matrix H 402 corresponding to the Tanner graph 404. For example, as shown in FIG. 4, the variable node 408 (leftmost) is connected to each check node 410 by two lines, i.e., this variable node is a type 2 (degree 2) node, and the number of 1s in the first column of the parity-check matrix H is 2. The next variable node connects to each check node 410 with three lines, i.e., it is a type 3 (degree 3) node, and the number of ones in the second column of the parity-check matrix H is three. In general, aspects of adaptive LDPC encoding may relate to or concern LDPC codes that may have one, two, three, or more different bit types, and as a result, the methodologies described herein may be applied to all such LDPC code configurations. Thus, the described aspects of adaptive decoding may be applied to symbol-inversion decoders, such as Galois field-based symbol decoders that can accommodate four states, eight states, and the like. As shown at 414, if the received or read bit is noisy, the syndrome vector for the bit is typically a non-zero vector and the syndrome weight is greater than zero. Alternatively, if the received or read bit is completely noiseless, the syndrome vector is a zero vector (e.g., zero entries) and the syndrome weight is zero.In aspects, the LDPC decoder 130 and adaptive controller 136 may iteratively process bits of the noisy data or codeword (e.g., flip bits) until the syndrome 412 or syndrome weight of the codeword approaches zero, i.e., errors in the received or read bits are corrected.

[0038] In adaptive decoding aspects, LDPC decoder 130 and adaptive controller 136 implement an adaptive decoding process in which the decoder's bit-flip or symbol-flip parameters (e.g., rules, thresholds) are dynamically updated during iterations of the decoding process. In some implementations of adaptive decoding, instead of the decoder using fixed rule values ​​across a given iteration for all bits in the LDPC code of the data being decoded, the decoding parameters (e.g., flip thresholds) adaptively change for each block during decoding based on the decoder's status (e.g., metrics) (e.g., real-time status within each decoding iteration).

[0039] The decoder status may include one or more of the following: syndrome weight, column weight of the parity-check matrix, the LDPC code being decoded, the bit position of the bit or variable node, the iteration index, the block index, and whether the bit (or symbol) is inverted or not (e.g., inversion status). Thus, the adaptive controller 136 may set or select decoding parameters (e.g., inversion threshold) based on the real-time status of the decoder in addition to the iteration number or bit inversion status. In some aspects, the adaptive controller uses the sum of syndrome values ​​(current syndrome weight, parity-check constraint) in the LDPC decoder 130 as the decoder status for adaptively selecting or setting decoding rules. In other words, as the decoder's current syndrome weight changes in real time, the adaptive controller 136 changes the decoding parameters (e.g., inversion threshold) in the decoder in real time or on the fly during a decoding iteration.

[0040] In the context of blocks of variable nodes 408 or bit nodes, the LDPC decoder 130 or adaptive controller 136 can divide the matrix or graph of variable bits 408 or data bits into blocks or other suitable subsets of variable bits. For example, a block in a decoder may include multiple bits in an LDPC graph (such as a data set being decoded) with bit nodes of the same or different types or degrees. In one implementation, the adaptive controller 136 divides the data to be decoded, or the entire LDPC code, into multiple M blocks. One block may contain or correspond to one type of bit, while another block may contain or correspond to another type of bit. In general, the number of bit types "T" in the data being decoded may be the same as or different from the number "M" of blocks the data was divided into. Thus, the adaptive LDPC decoder may be configured to divide or form bits of data into two types (T=2), but there are three different blocks (M=3). As an example, multiple blocks may cover the same type, such as two blocks covering a first bit type, one block covering a second bit type, etc. As an example, consider variable nodes divided into three block types, as shown at 418 in Figure 4. In this example, block 1 420 contains a first subset of type 2 variable nodes 408, block 2 422 contains a second subset of type 2 variable nodes 408 of different bit positions (or bit position ranges, e.g., bits 1-3, 4-6, etc.), block 3 424 contains a subset of type 3 variable nodes 408, etc.

[0041] 5 illustrates at 500 an example algorithm that an adaptive LDPC decoder can implement in accordance with various aspects. While described in the context of a bit-flipping decoder, aspects of algorithm 500 may also be applied to other types of decoders, including symbol-flipping decoders or the like. In general, a bit-flipping decoder can implement a hard-decision decoding algorithm for an LDPC code. As an example, at decoding iteration number i, a decoder or processing block calculates the number of unfilled check nodes connected to variable node j (e.g., variable node 408), which is (for variable node j) U j The decoder or processing block then applies this number to the bit-flip threshold (t i ) and the number of unsatisfied check nodes U j If σ exceeds the threshold, the decoder flips the variable node j (flipping the value of bit j), otherwise it retains the bit value for the variable node (does not flip the value of bit j). During iterations, the adaptive decoder can perform this bit-flip comparison for each bit of a subset or block of bits using multiple different decoding parameters 132 (e.g., thresholds).

[0042] In aspects, the adaptive controller 136 can alter, select, or modify the decoding parameters based on the status of the decoder, which may include one or more of various metrics 134. For example, the adaptive controller 136 may be configured to select the decoding parameters 132 based on the bit-flip status and syndrome weights of the variable nodes. In some implementations, the adaptive controller includes or can access a table of decoding parameters (e.g., bit-flip thresholds) that are accessed or selected based on the bit-flip status and syndrome weights of the variable nodes. Thus, the table includes the current syndrome weight of the decoder and a syndrome weight range and threshold pair (t) that is selected based on whether variable node j is equal to the received bit j of the channel. 1(i) , t 2(i)In the context of this example, the adaptive controller selects a threshold pair based on the decoder's current syndrome weights, and then calculates whether the variable node j is inverted (t 1(i) , inverted threshold) or not (t 2(i) , the uninverted threshold) based on the number of unsatisfied check nodes connected to variable node j (U j ) to one of a pair of threshold values. Based on this comparison, the decoder or processing block determines the number of unfilled check nodes U j exceeds a selected threshold, flip the value of bit node j; otherwise, retain the bit value for the variable node (do not flip the value of bit j). LDPC decoder 130 may continue this process throughout the decoding iterations, selecting multiple different bit-flip thresholds for the variable nodes based on the decoder's syndrome weights and the bit-flip status of the variable nodes. Alternatively or additionally, adaptive controller 136 may use any combination of decoding metrics, such as two or more of the syndrome weights, the bit position of the data or variable node, which LDPC code is implemented by the LDPC decoder, the order (e.g., bit type) of one or more bits of data, the LDPC decoder's block index, and the LDPC decoder's iteration index. At the end of an iteration, the LDPC decoder or adaptive controller calculates a syndrome update sum, and the decoded output (e.g., decoded_word) is stored. These iterations of decoding may be repeated for multiple iterations (i=1, 2, 3, . . . , K) until the sum of the syndromes (syndrome weight) reaches 0 or the maximum allowed number of iterations K is reached.

[0043] Returning to the algorithm shown in FIG. 5, an adaptive LDPC decoder can implement the operations of the algorithm to decode data received from a channel, such as a storage channel or a communication channel. At 502, the adaptive LDPC decoder receives bits to be decoded from the channel, and in some implementations, divides a graph or matrix of bits into blocks of bits for processing during decoding iterations. The adaptive decoder may determine or divide the received data into multiple subsets or portions for decoding. For example, the adaptive decoder may divide the data into two portions, three portions, four portions, etc. At 504, the adaptive LDPC decoder or adaptive controller determines current decoding metrics, which may include syndrome weights, column weights of a parity-check matrix, the LDPC code being decoded, a block index, whether a bit (or symbol) is inverted or not (e.g., inversion status), or the like. At 506, the adaptive LDPC decoder may determine an iteration index for the current decoding iteration being performed by the decoder, which if exceeded at 508 may indicate a decoding failure of completing decoding of the bit after multiple iterations. Otherwise, the adaptive LDPC decoder or adaptive controller determines at 510 an inversion threshold for a portion (e.g., a subset or block) of the current bit nodes being decoded.

[0044] At 512, the adaptive LDPC decoder flips bits for the portion of the current bits where the number of unsatisfied checks is greater than a threshold, and then updates the decoder's syndrome at 514. Note that the decoder's syndrome may be changed or updated after each bit is flipped, and the decoder may track the syndrome updates or syndrome weights for each bit flip, which may allow for dynamic adjustment of the decoding rules or thresholds. Thus, the adaptive decoder may process multiple portions of the received data or bits (e.g., three to six subsets of data) using multiple respective sets of decoding parameters (e.g., three to six sets of adaptively selected decoding parameters). The adaptive LDPC decoder sums the syndrome updates at the end of a decoding iteration at 516, and if the sum of the syndromes is equal to zero, the adaptive LDPC decoder provides the decoded data as successfully decoded at 518. Otherwise, the adaptive LDPC decoder feeds back the current iteration of the decoded bits, including the inverted bits, for another iteration of decoding by the adaptive LDPC decoder. This algorithm may be repeated until the syndrome sum reaches zero or the adaptive LDPC decoder reaches the maximum number of allowed decoding iterations.

[0045] As another example, consider FIG. 6, which illustrates at 600 an algorithm for adaptive LDPC decoding with a threshold adjusted based on the LDPC decoder's syndrome. While described in the context of a bit-flip decoder, aspects of algorithm 600 may also be applied to other types of decoders, including symbol-flip decoders or the like. At 602, the adaptive LDPC decoder receives bits to be decoded from the channel, and in some implementations, divides a graph or matrix of bits into blocks of bits for processing during a decoding iteration. At 604, the adaptive LDPC decoder or adaptive controller determines whether the bits are equal to the received bits or whether the bits were inverted from their original value upon reception (e.g., bit-flip status). The adaptive decoder determines at 606 a block index for the currently decoded bit and at 608 a running total of the syndrome value. Alternatively or additionally, the adaptive decoder may determine the block index based on the respective bit positions of the bit nodes or variable nodes in the graph. At 610, the adaptive LDPC decoder may determine an iteration index for the current decoding iteration being performed by the decoder, which, if exceeded at 612, may indicate a decoding failure upon completion of bit decoding after multiple iterations. Otherwise, at 614, the adaptive LDPC decoder or adaptive controller reads or accesses the flip threshold for the current block of bits in the current decoding iteration. Thus, the adaptive LDPC decoder may obtain the bit flip (or symbol flip) threshold based on the syndrome weights, the bit flip status, and the block index of the current subset of bits being decoded.

[0046] At 616, the adaptive LDPC decoder flips bits in the current block of bits for which the number of unsatisfied checks is greater than a threshold, and then updates the decoder's syndrome at 618. Note that the decoder's syndrome may be changed or updated after each bit is flipped, and the decoder may track the syndrome updates or syndrome weights for each bit flip, which may allow for dynamic adjustment of the decoding rules or thresholds. The adaptive LDPC decoder sums the syndrome updates at the end of a decoding iteration at 620, and if the syndrome sum is equal to zero, the adaptive LDPC decoder provides the decoded data as a successful decode at 622. Otherwise, the adaptive LDPC decoder feeds back the current iteration of the decoded bits, including the flipped bits, for another iteration of decoding by the adaptive LDPC decoder. This algorithm may be repeated until the syndrome sum reaches zero or the adaptive LDPC decoder reaches the maximum number of allowed decoding iterations.

[0047] As an example, consider a decoding process that includes two iterations of decoding an LDPC code using aspects of adaptive decoding. In this example, assume that the adaptive LDPC decoder is decoding an LDPC code of length N, which has two types of bits (Type A (e.g., degree 3) and Type B (e.g., degree 2)) that are divided into three blocks (M=3). In this example, assume that Type A bits are covered by the first block and Type B bits are covered by the second and third blocks. If the adaptive LDPC decoder performs bit-flipping decoding in decoding iteration i, for each block in this decoding iteration, the adaptive LDPC decoder compares the number of unsatisfied check nodes (Uj) connected to variable node j with a threshold selected based on the current syndrome weight. In some implementations, the adaptive LDPC decoder selects a threshold from a threshold table stored in or accessible by the decoder based on the syndrome weight. In the context of the current example, assume that in the first iteration (iteration index=1), the adaptive LDPC decoder decodes Type A bits. Because the Type A bits are covered by one block (block 1), the adaptive LDPC decoder processes this one block by accessing the threshold value associated with the block index of 1. As an example, consider Table 1, which provides access to the threshold value for block index 1 based on the syndrome weight range and bit flip status (t1 or t2). [Table 1]

[0048] When processing this block of bit nodes, the adaptive LDPC decoder will access and use bit flip thresholds based on the decoder's current status or metric. For example, if the decoder's syndrome weight is between 175 and 200, the adaptive LDPC decoder will assign a threshold pair (a 1,k-1 , b 1,k-1) and the syndrome weight of the decoder is between 200 and 225, the adaptive LDPC decoder assigns a threshold pair (a 1,k , b 1,k ) and the syndrome weight of the decoder is between 225 and 250, the adaptive LDPC decoder assigns a threshold pair (a 1,k+1 , b 1,k+1 ), etc. Based on the threshold entry selected from the table, the adaptive LDPC decoder performs bit flipping using the threshold, where U j If is greater than the selected threshold, the decoder flips the bit; otherwise, the decoder retains the bit value. In aspects, this continues as the adaptive LDPC decoder updates syndrome weights and selects or changes thresholds on the fly.

[0049] After completing the first iteration, the adaptive LDPC decoder proceeds to the second iteration (iteration index=2), during which the Type B bits are decoded as block 2 bits and block 3 bits of the LDPC code. Because the Type B bits are covered by two different blocks, the adaptive LDPC decoder may access two different tables with different block indexes, examples of which are shown as Table 2 for block index 2 and Table 3 for block index 3. [Table 2]

[0050] In the context of the second iteration, for block index 2, the adaptive LDPC decoder will access Table 2 and use the bit flip thresholds based on the decoder's current status or metric. For example, if the decoder's syndrome weight is between 175 and 200, the adaptive LDPC decoder will assign a threshold pair (a 2,k-1 , b 2,k-1 ) and the syndrome weight of the decoder is between 200 and 225, the adaptive LDPC decoder assigns a threshold pair (a2,k , b 2,k ) and the syndrome weight of the decoder is between 225 and 250, the adaptive LDPC decoder assigns a threshold pair (a 2,k+1 , b 2,k+1 ), etc. [Table 3]

[0051] For the bits of block index 3, which may be processed before, after, or in parallel with the bits of block index 2, the adaptive LDPC decoder accesses Table 3 and uses bit flip thresholds based on the decoder's current status or metric. For example, if the decoder's syndrome weight is between 175 and 200, the adaptive LDPC decoder assigns a threshold pair (a 3,k-1 , b 3,k-1 ) and the syndrome weight of the decoder is between 200 and 225, the adaptive LDPC decoder assigns a threshold pair (a 3,k , b 3,k ) and the syndrome weight of the decoder is between 225 and 250, the adaptive LDPC decoder assigns a threshold pair (a 3,k+1 , b 3,k+1 ), and so on. Continuing with this example, for each block of a given iteration, the adaptive LDPC decoder may use multiple different tables based on the decoder's status and / or metrics as the adaptive LDPC decoder implements the bit-flipping algorithm to decode the LDPC code. Thus, for iterations after the second iteration, the adaptive LDPC decoder proceeds in the same manner by accessing the threshold table corresponding to the particular iteration and the particular block or blocks being decoded during that iteration. As described herein, adaptive LDPC decoding may proceed until the syndrome weight reaches zero or the adaptive LDPC decoder reaches a maximum iteration limit (K).

[0052] Adaptive LDPC Decoding Techniques The following discussion describes adaptive LDPC decoding techniques that may enable an LDPC decoder to decode channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance. These techniques may be implemented using any of the environments and entities described herein, such as LDPC decoder 130 and adaptive decoder controller 136. These techniques include various methods illustrated in FIGS. 7-10, each of which is illustrated as a set of operations that may be performed by one or more entities.

[0053] These methods are not necessarily limited to the order of operations shown in the associated figures. Rather, any of these operations may be repeated, skipped, replaced, or reordered to implement various aspects described herein. Furthermore, these methods may be used in combination with each other, in whole or in part, whether performed by the same entity, separate entities, or any combination thereof. For example, these methods may be combined to implement adaptive LDPC decoding, adaptively setting LDPC decoder parameters (e.g., bit-flip thresholds) based on decoder status to decode channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance. Portions of the following discussion refer to the operating environment 100 of FIG. 1 and various entities or configurations in FIGS. 2-6 as examples. Such references should not be construed as limiting the described aspects to the operating environment 100, entities, or configurations, but rather as describing one of various examples. Alternatively or additionally, the operations of these methods may be implemented by or using the entities described in connection with the system-on-chip of FIG. 11 and / or the storage system controller of FIG.

[0054] FIG. 7 illustrates an example method 700 for adaptive LDPC decoding according to various aspects, including operations performed by or using the LDPC decoder 130, the decoding parameters 132, the decoding metrics 134, or the adaptive controller 136 associated with the adaptive LDPC decoder.

[0055] At 702, data is provided to an LDPC decoder, which may be configured as an adaptive LDPC decoder or may include an adaptive controller. The data may be received from a channel, such as a storage channel or a communication channel. For example, the data may be received from a storage channel via a storage medium interface or from a communication channel via a transceiver. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of a data codeword) may be inverted or erroneous. Thus, the bits of the received or read data may include inverted bits or bit errors in the ECC coding of the data. In aspects, the adaptive LDPC decoder divides or distributes the graph or matrix data into multiple portions or subsets (e.g., blocks) for processing during decoding iterations.

[0056] At 704, the LDPC decoder processes the first portion of data using a first parameter effective to change the status of the decoder. To process the first portion of data, the adaptive LDPC decoder flips bits or symbols of the first portion of bit nodes or variable nodes based on the first parameter. The first parameter may include a decoding rule or a decoding threshold for processing the bits of the first portion of data. The LDPC decoder may select the first parameter for decoding the first portion of data based on one or more metrics of the decoder, where the one or more metrics may include a syndrome weight, a bit flip status, a column weight, a block index, or the like. The change in the decoder status may include updating the syndrome weight of the decoder, where the syndrome weight may be changed or updated each time a bit or symbol of the LDPC code is flipped from its current value to a different value.

[0057] At 706, the LDPC decoder selects second parameters of the LDPC decoder based on the status of the decoder. The second parameters may include a decoding rule or a decoding threshold for processing bits of the first portion of data. The LDPC decoder may select second parameters for decoding the second portion of data based on one or more metrics of the decoder, where the one or more metrics may include a syndrome weight, a bit-flip status, a column weight, a bit position, a block index, or the like. In aspects, the adaptive LDPC decoder selects or updates parameters or thresholds for decoding a portion of the bits at least once during a decoding iteration to prevent bits to be decoded from being decoded using only one bit-flip threshold.

[0058] At 708, the LDPC decoder processes the second portion of the data using the second parameters. To process the second portion of the data, the adaptive LDPC decoder flips bits or symbols of the second portion of the bit nodes or variable nodes based on the second parameters (e.g., a bit flip threshold). The second parameters may include a decoding rule or a decoding threshold for processing the bits of the second portion of the data. Processing the second portion of the data may also effect a change in the status of the decoder (including another update of the decoder's syndrome weights), which may be changed or updated each time a bit or symbol of the LDPC code is flipped from its current value to a different value. From operation 708, method 700 may return to operation 706 to process another portion of the data during the immediate iteration, or may proceed to operation 710 to determine whether the bit of the data has been decoded. Operations 706 and 708 may be repeated iteratively until all portions of the data have been processed and one decoding iteration has been completed.

[0059] At 710, the controller of the LDPC decoder determines whether the data has been decoded. In some cases, the LDPC decoder calculates a sum of syndrome updates to determine whether the decoder's syndrome weight has reached zero, i.e., whether the bits of data have been successfully decoded. If the LDPC decoder's syndrome weight is not zero, method 700 may return to operation 702 and feed the partially decoded bits back to the decoder for another decoding iteration. Alternatively, the LDPC decoder may compare the iteration index with a maximum iteration threshold, and if the maximum iteration threshold is exceeded, the LDPC decoder may abort the decoding operation and provide the currently decoded bits as the LDPC decoder's output at operation 712.

[0060] FIG. 8 illustrates an example method 800 for implementing adaptive LDPC decoding based on a decoder's syndrome, including operations performed by or using an LDPC decoder 130, decoding parameters 132, decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder.

[0061] At 802, data is provided to an LDPC decoder, which may be configured as an adaptive LDPC decoder or may include an adaptive controller. The data may be received from a channel, such as a storage channel or a communication channel. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of a data codeword) may be inverted or erroneous. Thus, the bits of the received or read data may include inverted bits or bit errors in the ECC coding of the data. In aspects, the adaptive LDPC decoder divides or distributes the graph or matrix data into blocks of bits or subsets of bits for processing during decoding iterations. For example, the adaptive LDPC decoder may divide the data into at least two portions of bits for decoding, and in some implementations may divide the data into three portions, four portions, or any suitable number of portions (e.g., based on the quality (bit error rate) of the received data and / or the complexity of the decoder).

[0062] At 804, the LDPC decoder processes the first block of data using a first threshold setting and updates the syndrome of the LDPC decoder. To process the first block of data, the adaptive LDPC decoder flips bits or symbols of the first block of bit nodes or variable nodes based on a first threshold setting, such as those described in connection with FIG. 5 or FIG. 6. The LDPC decoder may select the first threshold setting for decoding the first block of data based on one or more metrics of the decoder, which may include syndrome weights, bit-flip status, column weights, bit positions, block indexes, or the like. The syndrome or syndrome weights of the decoder may be changed or updated each time a bit or symbol of the LDPC code is flipped from its current value to a different value.

[0063] At 806, the adaptive controller of the LDPC decoder modifies the first threshold setting based on the syndrome of the LDPC decoder to provide a second threshold setting. Additionally, the LDPC decoder may modify the first threshold setting based on another metric of the data being decoded or the decoder, which may include column weights of a parity check matrix, bit positions of bit nodes or variable nodes, bit reversal status, block index, or the like. In aspects, the adaptive LDPC decoder accesses a table of threshold values ​​to select the second threshold setting as described in connection with FIG. 5 or FIG. 6. Thus, the adaptive LDPC decoder may process or decode each of the portions of the plurality of data bits using a respective set of decoding parameters that are dynamically selected based on the state of the LDPC decoder.

[0064] At 808, the LDPC decoder processes the second block of data using a second threshold setting and updates the syndrome of the LDPC decoder. To process the second block of data, the adaptive LDPC decoder inverts bits or symbols of the second block of bit nodes or variable nodes based on a second threshold setting (e.g., a bit-flip threshold). Processing the bits of the second block of data updates the syndrome of the decoder, which may be changed or updated each time a bit or symbol of the LDPC code is inverted from its current value to a different value. From operation 808, the LDPC decoder may return to operation 806 and modify the current threshold setting of the LDPC decoder based on the updated syndrome resulting from processing the second block of data or a subsequent block of data (e.g., a block in another block iteration) to process the next block of data. Operations 806 and 808 may be repeated iteratively until all blocks or bit types of data have been processed, completing one decoding iteration. Alternatively, the LDPC decoder may proceed to operation 810, where it determines whether the data has been decoded based on the LDPC decoder's updated syndrome sums.

[0065] At 810, the LDPC decoder determines whether the data has been decoded based on the decoder's updated syndrome sum. In some cases, the LDPC decoder determines whether the decoder's syndrome weight has reached zero, i.e., whether the decoding of the bits of the data has been successful. If the LDPC decoder's syndrome weight is not zero, method 800 may return to operation 804 at 812 and feed the partially decoded bits back to the decoder for another decoding iteration. Alternatively, the LDPC decoder may compare the iteration index with a maximum iteration threshold, and if the maximum iteration threshold is exceeded, the LDPC decoder may abort the decoding operation. Once the data has been successfully decoded or the maximum number of iterations has been reached, the LDPC decoder may provide the decoded bits as the decoder's output at operation 814.

[0066] 9A and 9B illustrate an example method 900 for selecting decoding parameters of an adaptive LDPC decoder based on the status of the decoder, including operations performed by or using the LDPC decoder 130, the decoding parameters 132, the decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder.

[0067] At 902, an LDPC decoder receives or is provided with bits to be decoded. The data may be received from a channel, such as a storage channel or a communication channel. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of a data codeword) may be inverted or erroneous. In aspects, an adaptive decoder may determine portions or subsets of data from the received data, which may then be processed using decoding parameters adaptively selected or determined for each portion or subset of data (e.g., bits).

[0068] At 904, a status of the LDPC decoder is determined based on one or more metrics of the LDPC decoder. Generally, determining the status of the decoder may include determining decoder state information and / or metrics of bit nodes or variable nodes of the data graph being decoded. As shown in FIG. 9A, the LDPC decoder may determine at 906 whether a bit value is equal to a received bit value (e.g., bit flip status), determine at 908 a block index of the LDPC decoder, determine at 910 a sum of vectors or syndrome values ​​of the LDPC decoder, or determine at 912 an iteration index of the LDPC decoder.

[0069] At 914, an adaptive controller of the LDPC decoder selects decoding parameters based on the status of the LDPC decoder. For example, based on the status and / or metrics of the decoder, the adaptive controller may access a table of bit flip threshold settings and select a bit flip threshold setting that corresponds to the current state or status of the decoder, such as those described in connection with Figure 5 or Figure 6. From operation 914, the method proceeds to operation 916, as shown at 901 in Figure 9B.

[0070] At 916, the LDPC decoder flips at least some of the bits based on the decoding parameters. Generally, the adaptive LDPC decoder flips bits in the current block of bits for which the number of unsatisfied checks is greater than a threshold, and then updates the decoder's syndrome at 918. Note that the decoder's syndrome may be changed or updated after each bit is flipped, and the decoder may track syndrome updates or syndrome weights for each bit flip, which may allow for dynamic adjustment of the decoding rules or thresholds.

[0071] At 920, a syndrome sum is calculated. In aspects, the adaptive LDPC decoder sums the syndrome updates at the end of a decoding iteration, and if the syndrome sum is equal to zero, the adaptive LDPC decoder provides the decoded data as a successful decode at 922. Otherwise, the adaptive LDPC decoder returns to operation 902 and feeds back the current iteration of decoded bits, including inverted bits, for another iteration of decoding by the adaptive LDPC decoder. The operations of method 900 may be repeated until the syndrome sum reaches zero or the adaptive LDPC decoder reaches the maximum number of decoding iterations allowed.

[0072] 10 illustrates an example method 1000 for selecting parameters of an adaptive LDPC decoder based on results of processing data using a combination of parameters, including operations performed by or using LDPC decoder 130, decoding parameters 132, decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder. In aspects, method 1000 may be implemented as a “greedy” threshold optimization, where a cost function in the optimization may be configured to maximize the number of corrected bits for each block of decoded bit nodes. For example, method 1000 may be used to optimize the threshold table described in connection with FIG. 6 for any suitable number of iteration indexes and / or block indexes.

[0073] At 1002, data for an iteration index of an LDPC decoder is loaded. The data may be training data, randomized data, or live data of an LDPC code obtained from a channel. Optionally, at 1004, current parameters of the LDPC decoder are accessed, which may include previously optimized parameters or parameters currently configured as threshold settings for the decoder.

[0074] At 1006, data at a block index of the LDPC decoder is selected for decoding. In some implementations, method 1000 is performed iteratively for m blocks by stepping through each block index from 1 to m−1. At 1008, parameters of the LDPC decoder for the block index of the currently selected data or bit node are initialized. This may include setting a bit-flip threshold for the data at the block index being processed. At 1010, the data at the block index is processed by the LDPC decoder using the parameters, and decoder performance may be monitored during processing. Optionally, the data is processed by running a performance simulation using the currently optimized thresholds stored in the threshold table for all previous iterations from 1 to i−1 and for blocks 1 to m−1 in iteration i. At 1012, one or more of the decoding parameters are modified, so that multiple combinations of decoding parameters or thresholds may be evaluated by the performance simulation. Optionally, performance simulations may be run simultaneously for all possible threshold combinations for the current block index m in the iteration i being evaluated or simulated.

[0075] At 1014, results of processing the data for the block index using multiple different parameters are compared, and at 1016, parameters for the block index are selected based on the comparison of the results. For example, after processing results generated from a performance simulation, an optimal threshold value that results in the largest number of corrected bits in this block may be selected. From operation 1016, the method may proceed to the next block and process the next block using multiple different combinations of parameters, for example, until all blocks in the iteration have been exhausted. After all blocks in the iteration have been processed, the method may proceed to operation 1018, where parameters (e.g., optimal parameters or threshold values) for this iteration index are selected based on the processing results of each block, or threshold values ​​for the block index are selected based on the decoding results.

[0076] After the parameters for the iteration index are selected from operation 1018, the method may return to operation 1002 to load data for another iteration index into the LDPC decoder and iteratively process the data for that index, block by block, to determine parameters for another iteration index of the decoder. Thus, the operations of method 1000 may be performed iteratively to process multiple blocks for each iteration index, thereby providing optimal decoding thresholds for the multiple iteration indexes. After the decoding parameters or thresholds for one or more iteration indexes of the LDPC decoder have been determined, method 1000 may proceed to operation 1020 to store the parameters in the LDPC decoder. In aspects, the LDPC decoder or adaptive controller stores the optimal decoding parameters or thresholds in a table based on the iteration number index, block index, and syndrome weight range, for example, providing a table similar to those described herein.

[0077] (System on Chip and Controller) 11 illustrates an example system-on-chip (SoC) 1100 environment in which various aspects of adaptive LDPC decoding may be implemented. The SoC 1100 may be implemented in any suitable system or device, such as a smartphone, netbook, tablet computer, access point, network-attached storage device, camera, smart appliance, printer, set-top box, server, data storage center, solid-state drive (SSD), hard disk drive (HDD), optical storage drive, holographic storage system, storage drive array, memory module, automotive computing system, or aggregate storage controller, or any other suitable type of device (e.g., others described herein). Although described in the context of an SoC, the entities in FIG. 11 may be implemented as other types of integrated circuits or embedded systems, such as an application-specific integrated-circuit (ASIC), a memory controller, a storage controller, a communications controller, an application-specific standard product (ASSP), a digital signal processor (DSP), a programmable SoC (PSoC), a system-in-package (SiP), or a field-programmable gate array (FPGA).

[0078] The SoC1100 may be integrated with electronic circuitry, microprocessors, memory, input-output (I / O) control logic, communication interfaces, firmware, and / or software that help provide the functionality of a computing device, host system, or storage system, such as any of the devices or components (e.g., storage drives or storage arrays) described herein. The SoC1100 may also include an integrated data bus or interconnect fabric (not shown) that couples various components of the SoC for control signaling, data communication, and / or routing between components. The integrated data bus, interconnect fabric, or other components of the SoC1100 may be exposed or accessed through an external port, a parallel data interface, a serial data interface, a fabric-based interface, a peripheral component interface, or any other suitable data interface. For example, components of the SoC1100 may access or control external storage media, processing blocks, neural networks, data sets, or AI models through an external interface or an off-chip data interface.

[0079] In this example, SoC 1100 includes various components, such as input / output (I / O) control logic 1102 and a hardware-based processor 1104 (processor 1104), e.g., a microprocessor, processor core, application processor, DSP, or the like. SoC 1100 also includes memory 1106, which may include any type and / or combination of RAM, SRAM, DRAM, non-volatile memory, ROM, one-time programmable (OTP) memory, multiple-time programmable (MTP) memory, flash memory, and / or other suitable electronic data storage. In some aspects, processor 1104 and code stored on memory 1106 are implemented as a storage system controller or storage aggregator to provide various functionality associated with adaptive LDPC decoding. In the context of the present disclosure, memory 1106 stores data, code, instructions, or other information via non-transitory signals and does not include carrier waves or transitory signals. Alternatively or additionally, SoC1100 may include a data interface (not shown) for accessing additional or expandable off-chip storage media such as solid-state memory (e.g., flash or NAND memory), magnetic-based memory media, or optical-based memory media.

[0080] SoC 1100 may also include firmware 1108, applications, programs, software, and / or an operating system, which may be embodied as processor-executable instructions maintained on memory 1106 for execution by processor 1104 to implement the functionality of SoC 1100. SoC 1100 may also include other communication interfaces, such as a transceiver interface for controlling or communicating with components of a local on-chip (not shown) or off-chip communication transceiver. Thus, in some aspects, SoC 1100 may be implemented or configured as a communication transceiver capable of implementing aspects of adaptive LDPC decoding to process data received over a communication channel. Alternatively or additionally, the transceiver interface may also include or implement a signal interface for communicating radio frequency (RF), intermediate frequency (IF), or baseband frequency signals off-chip to facilitate wired or wireless communication through a transceiver, physical layer transceiver (PHY), or media access controller (MAC) coupled to SoC 1100. For example, SoC 1100 may include a transceiver interface configured to enable storage over a wired or wireless network, e.g., providing a network-attached storage (NAS) volume with adaptive LDPC decoding for communicated and / or stored data.

[0081] SoC 1100 also includes LDPC decoder 130, processing block 214, and adaptive controller 136, which may be implemented separately as shown or combined with a storage component, a host controller, a data interface, or a data transceiver. In accordance with various aspects of adaptive LDPC decoding, LDPC decoder 130 and adaptive controller 136 process a first portion of data (e.g., a block of data) of the channel using first parameters effective to change the status of the decoder (e.g., syndrome weights) and select second parameters based on the status of the decoder. LDPC decoder 130 may then be configured with the second parameters and process a second portion of data (e.g., another block of data) using the second parameters, which may further update the status of the LDPC decoder. LDPC decoder 130 provides decoded data for the channel based on at least the processing of the first portion of data using the first parameters and the processing of the second portion of data using the second parameters. Any of these entities may be embodied as entirely separate or combined components, as described in connection with various aspects presented herein. For example, the adaptive controller may be implemented as part of the LDPC decoder 130 or processing block 214 of a storage controller or a communications transceiver. Examples of these components and / or entities or their corresponding functionality are described in connection with the respective components or entities of the environment 100 of FIG. 1, or the respective configurations shown in FIGS. 2-6, and / or methods 700-1000 of FIGS. 7-10. The LDPC decoder 130 or adaptive controller 136 may be implemented, in whole or in part, as processor-executable instructions maintained by memory 1106 and executed by processor 1104 to implement various aspects and / or features of adaptive LDPC decoding.

[0082] The adaptive LDPC decoder 130 and / or the processing block 214 may be implemented independently or in combination with any suitable components or circuitry for implementing aspects described herein. For example, the adaptive LDPC decoder 130 or the processing block 214 may be implemented as part of a DSP, a processor / storage bridge, an I / O bridge, a graphics processing unit, a memory controller, a storage controller, an arithmetic logic unit (ALU), or the like. The adaptive LDPC decoder 130 may also be provided integrated with other entities of the SoC 1100, such as integrated with the processor 1104, memory 1106, storage medium interface, or firmware 1108 of the SoC 1100. Alternatively or additionally, the adaptive LDPC decoder 130, the processing block 214, and / or other components of the SoC 1100 may be implemented as hardware, firmware, fixed logic circuitry, or any combination thereof.

[0083] As another example, consider FIG. 12 , which illustrates an exemplary storage system controller 1200 with one or more aspects of adaptive LDPC decoding. In various aspects, storage system controller 1200 or any combination of its components may be implemented as a storage drive controller, a distributed storage center controller (e.g., between a host and an SSD), a storage media controller, a NAS controller, a fabric interface, an NVMe target, or a storage aggregation controller for storage media. In some cases, storage system controller 1200 is implemented similarly to or with components of SoC 1100 as described in connection with FIG. 11 . In other words, an instance of SoC 1100 may be configured as a storage system controller, such as storage system controller 1200, that manages storage media (e.g., NAND flash-based media or magnetic media) with aspects of adaptive LDPC decoding.

[0084] As shown in FIG. 12 , storage system controller 1200 includes input / output (I / O) control logic 1202 and processor 1204, e.g., a microprocessor, processor core, application processor, DSP, or the like. In some aspects, processor 1204 and firmware of storage system controller 1200 may be implemented to provide various functionality associated with adaptive LDPC decoding, such as that described in connection with any of methods 700 through 1000. Storage system controller 1200 also includes host interface 1206 (e.g., SATA, PCIe, NVMe, or fabric interface) and storage media interface 1208 (e.g., NAND interface, read / write channel), which enable access to a host system and storage media, respectively. Storage system controller 1200 may also include flash translation layer 1210 (FTL 1210), SRAM (not shown), and / or a DRAM controller (not shown). In some aspects of adaptive LDPC decoding, the FTL 1210 interacts with the LDPC decoder 130 and / or the adaptive controller 136 to decode data read from a storage medium operably coupled to the storage medium interface 1208.

[0085] In this example, storage system controller 1200 also includes instances of processing block 214, LDPC decoder 130, decoding parameters 132, decoding metrics 134, and adaptive controller 136. Any or all of these components may be implemented separately as shown, or may be combined with processor 1204, host interface 1206, storage media interface 1208, flash transition layer 1210, and / or implemented as an adaptive LDPC decoder in storage system controller 1200. Examples of these components and / or entities or their corresponding functionality are described in conjunction with the respective components or entities of environment 100 of FIG. 1 or the respective configurations shown in FIGS. 2-6. In accordance with various aspects of adaptive LDPC decoding, LDPC decoder 130 and adaptive controller 136 process a first portion of the channel's data (e.g., a block of data) using a first parameter effective to change the decoder's status (e.g., syndrome weights) and select a second parameter based on the decoder's status. LDPC decoder 130 may then be configured with second parameters and process a second portion of the data (e.g., another block of data) using the second parameters, which may further update the status of the LDPC decoder. LDPC decoder 130 provides decoded data for the channel based on at least the processing of the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively selecting or changing decoding parameters (e.g., bit-flip or symbol-flip thresholds) based on the decoder status, adaptive LDPC decoder 130 may decode the channel data with fewer decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

[0086] The following describes several examples of adaptive LDPC decoding according to one or more aspects. Example 1: A method for adaptive low-density parity-check decoding includes: processing, by a low-density parity-check (LDPC) decoder, a first portion of data of a channel using a first parameter effective to change a status of the LDPC decoder; selecting a second parameter for the LDPC decoder based on the status of the LDPC decoder; processing a second portion of the data using the second parameter by the LDPC decoder; and providing decoded data of the channel based on at least the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. Example 2: The method of any of the above examples further includes receiving the data from the channel and providing the data of the channel to the LDPC decoder. Example 3: The method of any of the above examples, wherein receiving the data of the channel includes receiving the data from a storage channel via a storage medium interface; or receiving the data from a communication channel via a transceiver. Example 4: The method of any of the above examples, further including, after processing at least a portion of the second portion of the data, selecting third parameters for the LDPC decoder based on a status of the LDPC decoder; processing the third portion of the data using the third parameters by the LDPC decoder; and providing decoded data for the channel based on at least the processing of the first portion of the data with the first parameters, the processing of the second portion of the data with the second parameters, and the processing of the third portion of the data with the third parameters.Example 5: In the method according to any of the above examples, the status of the LDPC decoder includes one of: a syndrome weight of the LDPC decoder; a column weight of the parity-check matrix; a bit position of a bit of the data; an LDPC code implemented by the LDPC decoder to decode the data; a degree of one or more bits of the data; a block index of the LDPC decoder; or an iteration index of the LDPC decoder. Example 6: In the method according to any of the above examples, the first parameter or the second parameter includes one of: an LDPC decoding rule; an LDPC decision threshold value; a bit-flip threshold for inverted bits; a bit-flip threshold for non-inverted bits; a symbol-flip threshold for inverted symbols; or a symbol-flip threshold for non-inverted symbols. Example 7: In the method according to any of the above examples, the processing of the first portion of the data by the LDPC decoder includes inverting bit values ​​of variable nodes representing corresponding bits in the first portion of the data; or the processing of the second portion of the data by the LDPC decoder includes inverting bit values ​​of variable nodes representing corresponding bits in the second portion of the data. and determining a plurality of blocks of data from the data, the plurality of blocks including at least the first block of data and the second block of data, wherein the status of the decoder on which the second parameter is selected includes an index of the second block of data. Example 9: A method according to any of the above examples, wherein each of the plurality of blocks of data includes a bit node type corresponding to an order of a bit node in a parity check matrix of the LDPC decoder; and determining the plurality of blocks includes forming each of the plurality of blocks with one bit node type of the data from at least two types of bit nodes defined for the LDPC decoder.Example 10: A method as recited in any of the above examples, wherein the first portion of the data and the second portion of the data are processed during one iteration of the LDPC decoder; and the status of the LDPC decoder includes an intermediate status of the LDPC decoder obtained during the one iteration of the processing of the data of the channel. Example 11: A method as recited in any of the above examples, wherein the data includes data read from a storage medium; and the storage medium includes one of an optical storage medium, a magnetic storage medium, a holographic storage medium, a solid-state storage medium, a NAND flash memory, a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash, a quad-level cell (QLC) flash, or a NOR cell flash. Example 12: An apparatus includes a data interface configured for communication of data over a channel; a low-density parity-check (LDPC) decoder; and an adaptive controller for the LDPC decoder, the adaptive controller configured to implement any of the methods recited in the above examples. Example 13: A system-on-chip (SoC) includes: a media interface for accessing a storage medium of a storage media system; a host interface for communicating with a host system; a low-density parity-check (LDPC) decoder; and an adaptive controller for the LDPC decoder configured to implement any of the methods described in the above examples.

[0087] Although adaptive LDPC decoder subject matter has been described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the particular examples, features, or operations described herein, including the order in which they may be performed.

Claims

1. 1. A method for adaptive low density parity check decoding, comprising: processing, by a low density parity check (LDPC) decoder, a first portion of data for the channel using a first parameter effective to change a status of the LDPC decoder; selecting second parameters of the LDPC decoder based on the status of the LDPC decoder; processing a second portion of the data using the second parameters with the LDPC decoder; and providing decoded data for the channel based on at least the steps of processing the first portion of the data with the first parameters and processing the second portion of the data with the second parameters. A method for providing

2. The method of claim 1 , further comprising receiving the data from the channel and providing the data of the channel to the LDPC decoder.

3. The receiving of the data on the channel includes: receiving said data from a storage channel via a storage medium interface; or receiving said data from a communication channel via a transceiver; 3. The method of claim 2, comprising:

4. The status of the LDPC decoder is the syndrome weights of the LDPC decoder; Column weights of the parity check matrix; the bit position of the data bit; an LDPC code implemented by the LDPC decoder to decode the data; the order of one or more bits of said data; a block index of the LDPC decoder; or Iteration index of the LDPC decoder The method of claim 1 , comprising one of:

5. The first parameter or the second parameter is LDPC decoding rules; LDPC decision threshold value; Bit flip threshold for flipped bits; Bit flip threshold for non-flip bits; a symbol inversion threshold for the inverted symbols; or Symbol inversion threshold for non-inverted symbols The method of claim 1 , comprising one of:

6. said processing said first portion of said data by said LDPC decoder comprises inverting bit values ​​of variable nodes representing corresponding bits in said first portion of said data; or said processing said second portion of said data by said LDPC decoder comprises inverting bit values ​​of variable nodes representing corresponding bits in said second portion of said data. The method of claim 1.

7. the first portion of the data corresponds to a first block of the data; the second portion of the data corresponds to a second block of the data; and The method further comprises determining a plurality of blocks of the data from the data, the plurality of blocks including at least the first block of data and the second block of data; the status of the decoder on which the second parameter is selected includes an index of the second block of data; The method of claim 6.

8. each of the plurality of blocks of data includes a bit node type corresponding to a bit node degree in a parity check matrix of the LDPC decoder; and determining the plurality of blocks includes forming each of the plurality of blocks with one bit node type of the data from at least two types of bit nodes defined for the LDPC decoder. The method of claim 7.

9. The first portion of the data and the second portion of the data are processed during one iteration of the LDPC decoder; and the status of the LDPC decoder includes intermediate status of the LDPC decoder obtained during the one iteration of the processing of the data of the channel.

9. The method according to any one of claims 1 to 8.

10. a data interface configured for communication of data over the channel; a low density parity check LDPC decoder; and an adaptive controller for the LDPC decoder, the adaptive controller comprising: processing a first block of data received from the channel using a first parameter by the LDPC decoder, the first parameter being effective to modify a metric of the LDPC decoder; selecting second parameters of the LDPC decoder based on the metrics of the LDPC decoder; processing a second block of data using the second parameters with the LDPC decoder; and providing decoded data for the channel based on at least the processing of the first block using the first parameters and the processing of the second block using the second parameters. It is configured as follows: Device.

11. the data interface comprises a storage medium interface, and the device is further configured to read the data from a storage medium operatively coupled to the device via the storage medium interface; or the data interface having a data transceiver, the device further configured to receive the data over the channel from a transmitter via the data transceiver.

11. The apparatus of claim 10.

12. The metrics of the LDPC decoder are intermediate metrics of iterations of decoding the data from the channel; and The metric of the LDPC decoder is the syndrome weights of the LDPC decoder; Column weights of the parity check matrix; the bit position of the data bit; an LDPC code implemented by the LDPC decoder to decode the data; the order of one or more bits of said data; a block index of the LDPC decoder; or Iteration index of the LDPC decoder [0033] 11. The apparatus of claim 10.

13. The first parameter or the second parameter of the LDPC decoder is LDPC decoding rules; LDPC decision threshold value; Bit flip threshold for flipped bits; Bit flip threshold for non-flip bits; a symbol inversion threshold for the inverted symbols; or Symbol inversion threshold for non-inverted symbols 13. The apparatus of claim 12, comprising one of:

14. The adaptive controller is further configured to determine, from the data, a plurality of blocks of the data including at least the first block of data and the second block of data; and the metric of the decoder on which the second parameter is selected includes an index of the second block of data; 14. The apparatus of claim 13.

15. each of the plurality of blocks of data includes a bit node type corresponding to a bit node degree in a parity check matrix of the LDPC decoder; and To determine the plurality of blocks, the adaptive controller is configured to form each of the plurality of blocks with one bit node type of the data from at least two types of bit nodes defined for the LDPC decoder.

15. The apparatus of claim 14.

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