Inter-core communication system for multi-core processor, inter-core communication method for multi-core processor, and multi-core processor

Abstract

The present application discloses an inter-core communication system, method, apparatus, and storage medium for a multi-core processor, the system including an inter-core communication device connected to a plurality of systems including a first system and a second system, the inter-core communication device including: an internal memory management module for receiving a descriptor request command sent by the first system and determining a descriptor pointer corresponding to the descriptor request command, the first system storing data awaiting transmission in an internal memory corresponding to the descriptor pointer; a queue management module for enqueuing the descriptor pointer in a specified queue after receiving an enqueue request sent by the first system; and an interrupt module for dequeuing a descriptor in a queue specified by an interrupt service program of the second system after the number of enqueues corresponding to the specified queue reaches a predetermined threshold, the second system reading the data awaiting transmission in the internal memory corresponding to the dequeued descriptor command.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to a Chinese patent application filed on October 11, 2022, bearing application number 202211263547.1, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of processors, and more particularly to a system, method, device, and storage medium for inter-core communication in a multi-core processor. [Background technology]

[0003] Currently, inter-core communication technology in multi-core processors generally relies on a mailbox post module to achieve interaction. However, this post module mainly provides interrupt-based communication services to the CPU, and the CPU participates in the interaction. This means that such inter-core communication technology requires the CPU to participate in operations such as message copying, queue space maintenance, and message channel access arbitration, which increases thread usage and reduces CPU performance. Summary of the Invention [Problem to be solved by the invention]

[0004] The main object of the present application is to provide a system, method, device, and storage medium for inter-core communication in a multi-core processor, and to solve the technical problem of how to reduce CPU utilization during inter-core communication and improve CPU performance.

[0005] In order to achieve the above object, the present application provides an inter-core communication method and system for a multi-core processor, including an inter-core communication device connected to a plurality of systems including a first system and a second system, the inter-core communication device comprising: an internal memory management module for receiving a descriptor request command sent by the first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data waiting to be transmitted in an internal memory corresponding to the descriptor pointer; a queue management module for enqueuing the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; and an interrupt module for dequeuing a descriptor in the specified queue by an interrupt service program of the second system after the number of enqueues corresponding to the specified queue reaches a preset threshold, wherein the second system reads data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction.

[0006] In order to achieve the above object, the present application further provides an inter-core communication method for a multi-core processor used in the inter-core communication system for a multi-core processor described above, receiving a descriptor request command sent by a first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data awaiting transmission in an internal memory corresponding to the descriptor pointer; enqueueing the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; After the number of enqueues corresponding to the specified queue reaches a preset threshold, an interrupt service program of the second system dequeues a descriptor in the specified queue, and the second system reads data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction.

[0007] In order to achieve the above object, the present application further provides an inter-core communication device for a multi-core processor, which includes a memory, a processor, and an inter-core communication program for a multi-core processor that is stored in the memory and can run on the processor, and when the inter-core communication program for a multi-core processor is executed by the processor, it realizes the steps of the inter-core communication method for a multi-core processor as described above.

[0008] In order to achieve the above object, the present application further provides a storage medium including a computer-readable storage medium, in which an inter-core communication program for a multi-core processor is stored, and when the inter-core communication program for a multi-core processor is executed by a processor, the steps of the inter-core communication method for a multi-core processor as described above are realized. [Effects of the Invention]

[0009] This application provides an inter-core communication device connected to multiple systems, and by entrusting the management of message data and message space when each system performs inter-core communication to an internal memory management module and a queue management module, and by having the internal memory management module complete the application of descriptor pointers and the queue management module complete the queue management corresponding to the descriptor pointers, there is no need for the CPU within the system itself to process, thereby ensuring normal data transmission between each system and reducing CPU usage during inter-core communication and improving CPU performance. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of a terminal / device structure of a hardware running environment according to an embodiment of the present application; [Figure 2] 1 is a schematic diagram of an overall frame in an inter-core communication system of a multi-core processor of the present application. [Figure 3]1 is a schematic diagram illustrating the internal structure of an inter-core communication device in an inter-core communication system of a multi-core processor according to the present application. [Figure 4] 1 is a schematic diagram of the internal structure of an internal memory management module in the inter-core communication system of the multi-core processor of the present application; [Figure 5] 1 is a schematic diagram illustrating the internal structure of a queue management module in an inter-core communication system of a multi-core processor according to the present application. [Figure 6] 1 is a schematic diagram of a flow chart for performing inter-core communication in an inter-core communication system of a multi-core processor of the present application. [Figure 7] 1 is a schematic flow diagram illustrating how multiple systems simultaneously access an inter-core communication device in an inter-core communication system of a multi-core processor of the present application. [Figure 8] 1 is a schematic diagram of a queue warning interrupt in an inter-core communication system of a multi-core processor of the present application; [Figure 9] 1 is a flow diagram of an inter-core communication method for a multi-core processor of the present application.The realization of the object, functions, features and advantages of the present application will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] It should be understood that the specific embodiments described herein are for purposes of interpretation of the present application only, and not for purposes of limiting the present application.

[0012] As shown in FIG. 1, FIG. 1 is a schematic diagram of a terminal structure of a hardware running environment according to the embodiment of the present application.

[0013] The terminal in the embodiment of the present application is an inter-core communication device of a multi-core processor.

[0014] As shown in FIG. 1, the terminal may include a processor 1001, e.g., a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to realize communication between these components. The user interface 1003 may include a display and an input unit, e.g., a keyboard, and may further include a standard wired interface and a wireless interface. The network interface 1004 may include a standard wired interface and a wireless interface (e.g., a Wi-Fi interface). The memory 1005 may be a high-speed memory or a non-volatile memory, e.g., a magnetic disk memory. The memory 1005 may be a storage device separate from the processor 1001.

[0015] In some embodiments, the terminal may further include a camera, an RF (Radio Frequency) circuit, a sensor, an audio circuit, a WiFi module, etc. Here, the sensor may be, for example, a light sensor, a motion sensor, or other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, where the ambient light sensor can adjust the brightness of the display according to the brightness of the ambient light, and the proximity sensor can turn off the display and / or backlight when the terminal device is moved close to the ear. Of course, the terminal device may also be configured with other sensors such as a gyro, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be described further here.

[0016] As will be appreciated by those skilled in the art, the terminal structure shown in FIG. 1 does not constitute a limitation on the terminal, which may include more or fewer components than those shown, or any combination of components, or different arrangements of components.

[0017] As shown in FIG. 1, memory 1005, which is a computer storage medium, may include an operating system, a network communication module, a user interface module, and an inter-core communication program for a multi-core processor.

[0018] In the terminal shown in FIG. 1, the network interface 1004 is mainly connected to a background server and is used to communicate data with the background server, and the user interface 1003 is mainly connected to a client (user side) and is used to communicate data with the client. The processor 1001 calls an inter-core communication program of the multi-core processor stored in the memory 1005, receiving a descriptor request command transmitted by a first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data waiting to be transmitted in an internal memory corresponding to the descriptor pointer; enqueueing the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; The method may be used to execute an operation in which an interrupt service program of a second system dequeues a descriptor in the specified queue after the number of enqueues corresponding to the specified queue reaches a predetermined threshold, and the second system reads data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction.

[0019] Referring to FIG. 2 , the present application provides an inter-core communication system for a multi-core processor. In a first embodiment of the inter-core communication system for a multi-core processor, the inter-core communication system for a multi-core processor includes an inter-core communication device 300 connected to a plurality of systems, the plurality of systems including a first system 100 and a second system 200, and the inter-core communication device 300: an internal memory management module 310 for receiving a descriptor request command sent by the first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data waiting to be transmitted in the internal memory corresponding to the descriptor pointer; a queue management module 320 for enqueuing the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; and an interrupt module 330 for dequeuing a descriptor in the specified queue by an interrupt service program of the second system after the number of enqueues corresponding to the specified queue reaches a preset threshold, wherein the second system reads data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction.

[0020] In current inter-core communication methods, the CPU must participate in operations such as message copying, queue space maintenance, and message channel access arbitration, which increases thread utilization and reduces CPU performance. Therefore, in this embodiment, inter-core communication is realized based on a shared internal memory plus interrupt service mechanism. The inter-core communication device 300 mainly includes an internal memory management module 310 and a queue management module 320. Both the internal memory management module 310 and the queue management module 320 are provided with on-chip buffer pools and use an AXI (Advanced eXtensible Interface, bus protocol) bus interface to actively access off-chip DDR (Double Data Rate) to read and write descriptor pointers in the internal memory. At the same time, the CPU configures the internal memory management module 310 and the queue management module 320 through the AXI bus interface. The internal memory management module 310 manages descriptor pointers in a FIFO (First Input First Output) manner and provides the CPU with a descriptor pointer request and release interface. The queue management module 320 manages the descriptor pointers in a first-in, first-out queue manner and provides the CPUs with an interface for enqueuing and dequeuing the descriptor pointers. Therefore, in this embodiment, a core CPU on one side of the communication may obtain a descriptor pointer after passing through the internal memory management module 310 and enqueue it to the queue management module 320, and a core CPU on the other side of the communication may dequeue the descriptor pointer from the queue management module 320 to obtain the descriptor pointer and read the communication data based on the descriptor pointer.

[0021] In this embodiment, before inter-core communication of the multi-core processor is performed, the inter-core communication system of the multi-core processor must be configured, which may include two parts: module initialization and interrupt registration. Here, in the module initialization part, suppose the inter-core communication system of the multi-core processor has two systems, namely, a first system 100 and a second system 200, and the first system 100 has one core, CPU0, and the second system 200 has one core, CPU1. Therefore, either CPU0 or CPU1 can perform initialization and configuration for each module. For example, when CPU0 performs initialization and configuration for each module, CPU0 can access the control register of the internal memory management module 310 via the AXI_Slave interface and configure the register with the number of different types of buffer blocks to calculate the DDR internal memory size occupied by the buffer blocks. CPU0 can then allocate the internal memory for this segment and configure the start address and end address in the control register. CPU0 accesses the control register of the queue management module 320 via the AXI_Slave interface, configures the number of queue elements in each queue in this module register, and then calculates the size of the DDR internal memory that the queue management module 320 needs to manage based on the product of the number of queues, the number of queue elements in each queue, and the size of the queue element. After allocating this segment of internal memory, CPU0 configures the start address and end address of the internal memory in the module control register. After enabling the module and writing to the control register, CPU0 completes the initialization and configuration of the internal memory management module 310 and the queue management module 320.

[0022] In the interrupt registration part, the internal memory request interface and the internal memory release interface of the internal memory management module 310 both have abnormal interrupt sources, and when CPU0 initializes the internal memory management module 310 via the AXI_Slave interface, it enables and configures the descriptor request and release abnormal interrupt sources (i.e., configurable functions), and each queue of the queue management module 320 has an enqueue request interrupt source, a dequeue request abnormal interrupt source, and a queue warning interrupt source, and when CPU0 initializes the queue management module 320 via the AXI_Slave interface, it enables and configures the abnormal interrupt source and warning interrupt source, and also configures the warning depth of the queue warning interrupt. The queue warning interrupt mechanism during enqueueing is shown in Figure 2. For example, if the queue warning depth n=1 configured by CPU0, CPU0 triggers a warning interrupt after enqueuing to queue 0 once. This interrupt is also called a queue-full interrupt. For example, if the queue warning depth n>1 configured by CPU0, CPU0 triggers a warning interrupt after enqueuing to queue 0 n times. This interrupt is also called a queue-full interrupt. After an interrupt occurs in a queue, the interrupt status can be cleared by configuring the relevant register. In this embodiment, CPU1 registers a warning interrupt for a specified queue. When CPU0 enqueues to this queue the number of times it reaches the warning depth, it triggers the warning interrupt and enters CPU1's interrupt service program. In this embodiment, the triggering of each interrupt service flow is implemented by the interrupt module 330.

[0023] In this embodiment, once module initialization and interrupt registration for each module are complete, subsequent inter-core communication operations can be performed. At this time, a descriptor enqueue operation can be performed. That is, CPU0 can access the internal memory management module 310 based on the data size of the data waiting to be transmitted by the first system 100 and send a descriptor request command to the internal memory management module 310. Upon receiving the descriptor request command, the internal memory management module 310 determines whether the current internal memory is sufficient. If the internal memory is sufficient, it determines a descriptor pointer corresponding to the descriptor request command and sends information indicating that the descriptor pointer request was successful to CPU0 in the first system 100. CPU0 then stores the data waiting to be transmitted in the internal memory pointed to by the descriptor pointer. However, if the internal memory management module 310 determines that the current internal memory is insufficient or there is another abnormality, it determines that the application descriptor pointer application has failed. When it determines that the application has failed and has previously registered a descriptor application abnormal interrupt, it enters the application abnormal interrupt service program of CPU0 to perform interrupt service processing. That is, at this time, the interrupt module 330 is triggered.

[0024] After the first system 100 requests a descriptor pointer, it may perform a descriptor enqueue operation, and the CPU0 may enqueue the descriptor in a register by accessing the descriptor in the queue management module 320, and enqueue the descriptor pointer to a specified queue in the queue management module 320. For example, the first system 100 may send an enqueue request to the queue management module 320. Similarly, if an enqueue abnormal interrupt is registered, the enqueue abnormal interrupt service program of the CPU0 is entered upon an enqueue failure.

[0025] After the descriptor pointer is enqueued to the designated queue, the interrupt module 330 detects the queue depth of the designated queue, and triggers a warning interrupt for the designated queue after the number of enqueues reaches a preset threshold (any threshold preset by the user). CPU1 in the second system 200 enters its interrupt service program to register a warning interrupt for the queue. Then, to dequeue the descriptor, CPU1 accesses the queue management module 320 in the interrupt service program to obtain the queue depth of the designated queue, i.e., the number of data transmissions by CPU0, and performs a dequeue operation of the descriptor pointer based on the queue depth, i.e., dequeues all the descriptor pointers in the designated queue in order. Finally, when entering the descriptor release stage, once CPU1 obtains the descriptor pointer, it can read the data written by CPU0 from the internal memory pointed to by this descriptor pointer. After CPU1 has used this internal memory space, it writes the descriptor pointer to the descriptor release register and returns the descriptor pointer to the internal memory management module 310, thereby completing the inter-core data interaction process between CPU0 and CPU1 in the multi-core heterogeneous platform, that is, completing the inter-core data interaction between the first system 100 and the second system 200.

[0026] For example, as shown in FIG. 6, the first system 100 is configured by CPU0, which includes performing module initialization and configuration, registering an interrupt and enabling the configuration, and CPU1 registering an interrupt and enabling the configuration. CPU0 then performs an internal memory request. The internal memory management module buffers the request operation; if not, an abnormal interrupt is generated. If so, CPU0 obtains the internal memory descriptor pointer, writes data to the internal memory, and performs an enqueue request. The queue management module then performs the enqueue operation. If not, an abnormal interrupt is generated. If so, the queue depth is detected to have reached the warning depth; if not, the queue depth is incremented by 1. If so, the queue triggers a warning interrupt, and CPU1 then performs a dequeue request. The queue management module then performs the dequeue operation; if not, an abnormal interrupt is generated. If so, CPU1 obtains the internal memory descriptor pointer, CPU1 performs an internal memory release, and the internal memory management module buffers the release operation; if not, an abnormal interrupt is generated; if so, the next inter-core data communication is performed.

[0027] In this embodiment, when each system communicates between cores, the management of message data and message space is left to the internal memory management module and queue management module. The application of descriptor pointers is completed by the internal memory management module, and queue management corresponding to the descriptor pointers is completed by the queue management module. This eliminates the need for the CPU within the system itself to process the data. This ensures normal data transmission between each system, reduces CPU usage during inter-core communication, and improves CPU performance.

[0028] Based on the above first embodiment, a second embodiment of the inter-core communication system of a multi-core processor of the present application is proposed. Referring to FIG. 4 , in the inter-core communication system of a multi-core processor, an internal memory management module 310 includes a first bus interface 311, a first register 312, a buffer 313, and an on-chip memory 314, and the internal memory management module 310 is connected to each of the systems and an off-chip memory 400 via the first bus interface 311; the first register 312 is used to, after receiving a descriptor pointer request command sent by the first system 100, determine a descriptor pointer corresponding to the descriptor request command and store the descriptor pointer in the on-chip memory 314; The buffer 313 is used to read the descriptor pointers in the off-chip memory 400 into the on-chip memory 314 after the number of descriptor pointers in the on-chip memory 314 becomes smaller than a preset number, and to read the descriptor pointers in the on-chip memory 314 into the off-chip memory 400 after the number of descriptor pointers in the on-chip memory 314 becomes larger than the preset number.

[0029] In this embodiment, the first bus interface 311 in the internal memory management module 310 may include two types of first bus interfaces 311, for example, two types of AXI bus interfaces. The buffer 313 may be an on-chip memory structure such as a FIFO buffer and an on-chip memory 314. Here, the two types of AXI bus interfaces may include an AXI slave interface and an AXI master interface. The AXI slave interface is used by the CPU0 to read and write registers of the internal memory management module 310, and the AXI master interface is used by the internal memory management module 310 to autonomously access the off-chip memory 400.

[0030] In this embodiment, the internal memory management module 310 manages the descriptor pointers in a two-stage storage manner, that is, it stores some of the descriptor pointers in the on-chip memory 314 and stores the other part in the off-chip memory 400. A FIFO buffer is used to control the number of descriptor pointers in the on-chip memory. When the number of descriptor pointers in the on-chip RAM is less than a preset number (any number preset by the user), the FIFO controller accesses the off-chip memory 400 via the AXI_Master interface and reads some of the descriptor pointers therefrom into the on-chip memory 314. Conversely, when the number of descriptor pointers in the on-chip memory 314 exceeds the preset number, the FIFO controller writes the excess descriptor pointers to the off-chip memory 400.

[0031] In this embodiment, the internal memory management module 314 is provided with a first bus interface 311, a first register 312, a buffer 313, and an on-chip memory 314. When the first system 100 and the second system 200 perform inter-core communication, a descriptor pointer can be applied for using the first register 312, and the descriptor pointer is stored using the buffer 313, making it easy for the first system to store data waiting to be transmitted in the internal memory corresponding to the descriptor pointer, thereby ensuring the effective progress of inter-core communication.

[0032] In one embodiment, referring to FIG. 4, the first register 312 includes: a control register 3121 for, after receiving a descriptor pointer request command sent by the first system 100, determining a descriptor pointer corresponding to the descriptor request command and storing the descriptor pointer in the on-chip memory 314; a descriptor request register 3122 for providing a descriptor pointer request interface to the first system 100; a descriptor release register 3123 for providing a descriptor pointer release interface to the first system 100; and a statistics register 3124 for collecting statistics on the number of operations on the descriptor pointer.

[0033] In this embodiment, the control register 3121 is used for configuring the CPU's internal memory management module 310, the descriptor request register 3122 and the descriptor release register 3123 are used to provide the CPU with an interface for requesting and releasing internal memory descriptors, and the statistics register 3124 is used to keep statistics on the number of descriptor operations.

[0034] In this embodiment, the first register 312 is divided into multiple registers, including a control register 3121, a descriptor request register 3122, a descriptor release register 3123, and a statistics register 3124, according to different functions, which facilitates the first system 100 to sequentially request descriptor pointers in the internal memory management module 310 and to perform subsequent inter-core communication operations based on the descriptor pointers.

[0035] In one embodiment, referring to FIG. 5 , a queue management module 320 includes a second bus interface 321, a second register 322, a queue controller 323, and an on-chip memory 314, the queue management module 320 being connected to each of the system and off-chip memory 400 via the second bus interface 321; the second register 322 is used by the queue controller 323 to determine a designated queue corresponding to the descriptor pointer after receiving an enqueue request sent by the first system 100, and enqueue the descriptor pointer to the designated queue; The queue controller 323 is used to read the descriptor pointers in the off-chip memory 400 after the descriptor pointers in the on-chip memory 314 become less than a preset number.

[0036] In this embodiment, as shown in FIG. 5, the second bus interface 321 in the queue management module 320 may also include two types, or two types of AXI bus interfaces. Here, the two types of AXI bus interfaces may include an AXI slave interface and an AXI master interface. The AXI slave interface is used by the CPU0 to read and write registers in the queue management module 320, and the AXI master interface is used by the queue management module 320 to autonomously access the off-chip memory 400. The structure of the queue management module 320 in this embodiment is similar to the structure of the internal memory management module 310. Descriptor pointers in the queues are stored in the on-chip memory 314 in a head-to-tail manner. The queue controller 323 maintains the number of descriptor pointers corresponding to each queue in the on-chip memory 314 and performs enqueue and dequeue operations on the descriptor pointers corresponding to each queue in the on-chip memory 314 in a first-in, first-out manner. After the descriptor pointer of a specified queue in the on-chip memory 314 becomes smaller than a preset number (any number preset by the user), the descriptor pointer in the off-chip memory 400 is accessed voluntarily via the AXI Master interface and read into the on-chip memory. Here, the descriptor enqueue register and the descriptor dequeue register are used to provide the CPU with an internal memory descriptor enqueue interface and dequeue interface, and the statistics register is used for statistics on the number of times the queue is dequeued and enqueued. Here, the second register 322 in the queue management module 320 has a structure similar to that of the first register 312 in the internal memory management module 310, and similarly includes a control register, a descriptor enqueue register, a descriptor dequeue register, and a statistics register.

[0037] When the first system 100 performs an enqueue operation, it may achieve the enqueue operation by accessing the second register 322 in the queue management module 320. After receiving an enqueue request, the second register first determines the designated queue corresponding to the descriptor pointer. If the designated queue cannot be determined, an enqueue abnormal interrupt is registered, and the enqueue abnormal interrupt service program of the CPU0 in the first system 100 is entered upon an enqueue failure. If the designated queue can be determined, the descriptor pointer is enqueued to the designated queue.

[0038] In this embodiment, the queue management module 320 is configured with a second bus interface 321, a second register 322, a queue controller 323 and an on-chip memory 314, so that after the first system 100 requests a descriptor pointer, it stores it sequentially in a designated queue, and the subsequent second system 200 can easily extract it from the designated queue, thereby completing the inter-core communication operation.

[0039] In one embodiment, referring to FIG. 3, the inter-core communication device 300 further includes a bus interface module 340, and the internal memory management module 310 and the queue management module 320 are connected to each of the systems via the bus interface module 340.

[0040] In this embodiment, the bus interface module 340 may be an AXI slave module and an AXI master module, and is connected to the AXI slave interface in the internal memory management module 310 and the AXI slave interface in the queue management module 320 via the AXI slave module, respectively, and is connected to the AXI master interface in the internal memory management module 310 and the AXI master interface in the queue management module 320 via the AXI master module, respectively. The AXI slave module and AXI master module are then connected to each system via an externally provided AXI system bus, thereby realizing the connection between each module and each system in this embodiment.

[0041] In this embodiment, the inter-core communication device is further provided with a bus interface module 340, which establishes a connection between an external system and the inter-core communication device 300, thereby ensuring the normal progress of subsequent inter-core communication.

[0042] In one embodiment, referring to FIG. 3 , the inter-core communication device 300 further includes an arbitration module 350 connected to the memory management module 310 and the queue management module 320, respectively. When the arbitration module 350 detects that multiple systems are accessing the inter-core communication device 300 simultaneously, the arbitration module 350 is used to arbitrate accesses of each of the systems according to a predetermined communication order and respond to the accesses of each of the systems sequentially.

[0043] In this embodiment, if multiple cores simultaneously access the internal memory management module 310 and the queue management module 320, as shown in Figure 2, when CPU0 in the first system 100 and CPU1 in the second system simultaneously request descriptors of the same size, i.e., simultaneously access the same internal memory request interface of the internal memory management module, the arbitration module 350 first responds to the access request of CPU0 using a preset serial access method, and then responds to the access request of CPU1 once the internal memory management module 310 has successfully allocated a buffer block descriptor of the corresponding size. Note that when multiple cores release descriptors through the same internal memory release interface and enqueue and dequeue queue elements through the same dequeue interface, the operation flow of the arbitration module 350 is the same as when multiple cores request internal memory. For example, as shown in FIG. 3, the arbitration module 350 is connected to the internal memory management module 310 and the queue management module 320, respectively; the interrupt module 330 is connected to the internal memory management module 310 and the queue management module 320, respectively; and the internal memory management module 310 and the queue management module 320 are both connected to the bus interface module 340, where the bus interface module 340 includes an AXI slave module and an AXI master module.

[0044] 7, when CPU0 makes an internal memory request for buffer block 0 and CPU1 also makes an internal memory request for buffer block 0, the internal memory request interface for buffer block 0 is first determined and the request interrupt is sent via the arbitration module. If it is determined that CPU0 makes the internal memory request first, the internal memory management module responds to the internal memory request for CPU0, and then responds to the internal memory request for CPU1. However, when an enqueue request for queue 0 by CPU0 and an enqueue request for queue 0 by CPU1 exist simultaneously, the queue management module first determines the enqueue request interface for queue 0, and then arbitrates the requests via the arbitration module. Then the queue management module responds to the enqueue request for CPU0, and after the response is complete, the queue management module responds to the enqueue request for CPU1.

[0045] In this embodiment, an arbitration module is further configured in the inter-core communication device, so that when multiple systems access the inter-core communication device simultaneously, the arbitration module can arbitrate access according to a pre-set communication order, making it easier to ensure the effective progress of the systems' access to the inter-core communication device.

[0046] In one embodiment, the interrupt module 330 is also used to issue an error interrupt after the internal memory management module 310 experiences an error, and to issue an error interrupt after the queue management module 320 experiences an error.

[0047] In this embodiment, the interrupts in the interrupt module 330 may include an abnormal interrupt when the internal memory is requested or released in the internal memory management module 310, an abnormal interrupt when an enqueue request or a dequeue request is made in the queue management module 320, a queue not empty warning interrupt, and a queue full warning interrupt. For example, as shown in Figure 8, when CPU0 detects that the queue warning depth is 1, CPU1 registers a queue warning interrupt and enables the warning interrupt. After CPU0 requests to enqueue to queue 0, the queue management module performs an enqueue request operation; if not, an error interrupt is triggered by the interrupt module; if so, CPU1 obtains the internal memory descriptor pointer.

[0048] In this embodiment, the interrupt module 330 may be used to issue an abnormal interrupt when an abnormality occurs in the internal memory management module 310 and the queue management module 320, thereby ensuring the effective progress of inter-core communication and preventing the occurrence of an abnormality from affecting the security of the inter-core communication system of the multi-core processor.

[0049] Referring to FIG. 9 , the present application provides an inter-core communication method for a multi-core processor, and in a third embodiment of the inter-core communication method for a multi-core processor, the inter-core communication method for a multi-core processor is applied to the inter-core communication system for a multi-core processor in any one of the above embodiments, a step S10 of receiving a descriptor request command sent by a first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data waiting to be transmitted in an internal memory corresponding to the descriptor pointer; Step S20: after receiving an enqueue request sent by the first system, enqueue the descriptor pointer to a designated queue; and a step S30 of dequeuing a descriptor in the specified queue by an interrupt service program of the second system after the number of enqueues corresponding to the specified queue reaches a preset threshold, and a step S30 of the second system reading data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction.

[0050] Here, the process realized by each step of the inter-core communication method of a multi-core processor may be referred to in each embodiment of the inter-core communication system of a multi-core processor of the present application, and will not be further described here.

[0051] In addition, the present application further provides an inter-core communication device for a multi-core processor, which includes a memory, a processor, and an inter-core communication program for a multi-core processor stored in the memory, and the processor is used to execute the inter-core communication program for the multi-core processor to realize the steps of each embodiment of the inter-core communication method for a multi-core processor.

[0052] The present application further provides a storage medium, which may be a computer-readable storage medium, having one or more programs stored therein, the one or more programs being executed by one or more processors to implement the steps of each embodiment of the inter-core communication method of the multi-core processor.

[0053] The specific embodiments of the computer-readable storage medium of the present application are basically the same as the above-mentioned embodiments of the inter-core communication method of the multi-core processor, and will not be further described here.

[0054] It should be noted that, in this context, the terms "comprises," "including," or any other variations thereof, are intended to cover a non-exclusive "inclusion," whereby a process, method, article, or system that includes a set of elements not only includes those elements, but also includes other elements not expressly listed, or further elements inherent in such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising one of" does not exclude the presence of other identical elements in a process, method, article, or system that includes that element.

[0055] The numbers of the examples in the present application above are for descriptive purposes only and do not represent the superiority or inferiority of the examples.

[0056] As will be apparent to those skilled in the art from the description of the above embodiments, the methods of the above embodiments may be realized in the form of software plus a necessary general-purpose hardware platform, or of course, in hardware, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of the present application, in substance or in part contributing to the prior art, may be expressed in the form of a software product, which is stored in a storage medium (e.g., ROM / memory, magnetic disk, optical disk) as described above, and includes some instructions that cause a terminal device (which may be a mobile phone, computer, server, air conditioner, network device, etc.) to execute the methods described in each embodiment of the present application.

[0057] The above are merely selective examples of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent flow conversion made using the contents of the specification and accompanying drawings of the present application, or any direct or indirect operation in other related technical fields, are all similarly included in the patent protection scope of the present application. [Explanation of symbols]

[0058] 100 First System 200 Second System 300 Inter-core communication device 400 Off-chip Memory 310 Internal Memory Management Module 320 Queue Management Module 330 Interrupt Module 340 Bus Interface Module 350 Arbitration Module 311 First Bus Interface 312 First Register 313 buffer 314 On-chip Memory 3121 Control Register 3122 Descriptor Application Register 3123 Descriptor Release Register 3124 Statistics Registers 321 Second Bus Interface 322 Second Register 323 Queue Controller 1001 processor 1002 communication bus 1003 User Interface 1004 Network Interface 1005 memory

Claims

1. An inter-core communication system for a multi-core processor including an inter-core communication device connected to a plurality of systems including a first system and a second system, an internal memory management module configured to receive a descriptor request command sent by the first system and determine a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data waiting to be transmitted in the internal memory corresponding to the descriptor pointer; a queue management module configured to enqueue the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; an interrupt module that is set by an interrupt service program of the second system to dequeue a descriptor in the designated queue after the number of enqueues corresponding to the designated queue reaches a preset threshold, wherein the second system reads data waiting for transmission in an internal memory corresponding to the dequeued descriptor instruction; Inter-core communication system for multi-core processors.

2. the internal memory management module includes a first bus interface, a first register, a buffer, and an on-chip memory, the internal memory management module being connected to each of the system and off-chip memories via the first bus interface; the first register is configured to, after receiving a descriptor pointer request command sent by the first system, determine a descriptor pointer corresponding to the descriptor pointer request command and store the descriptor pointer in the on-chip memory; the buffer is configured to read the descriptor pointers in the off-chip memory into the on-chip memory after the number of descriptor pointers in the on-chip memory becomes smaller than a predetermined number, and to read the descriptor pointers in the on-chip memory into the off-chip memory after the number of descriptor pointers in the on-chip memory becomes greater than the predetermined number; The inter-core communication system of a multi-core processor according to claim 1 .

3. The first register comprises: a control register configured to, after receiving a descriptor pointer request command sent by the first system, determine a descriptor pointer corresponding to the descriptor request command and store the descriptor pointer in the on-chip memory; a descriptor request register configured to provide a descriptor pointer request interface to the first system; a descriptor release register configured to provide a descriptor pointer release interface to the first system; a statistics register configured to record the number of operations of the descriptor pointer; The inter-core communication system of a multi-core processor according to claim 2 .

4. the queue management module includes a second bus interface, a second register, a queue controller, and an on-chip memory, the queue management module being connected to each of the systems and the off-chip memory via the second bus interface; the second register is configured to, after receiving an enqueue request sent by the first system, determine a designated queue corresponding to the descriptor pointer by the queue controller, and enqueue the descriptor pointer to the designated queue; the queue controller is configured to read the descriptor pointer in the off-chip memory after the descriptor pointer in the on-chip memory becomes less than a preset number; The inter-core communication system of a multi-core processor according to claim 1 .

5. the inter-core communication device further includes a bus interface module, and the internal memory management module and the queue management module are connected to each of the systems via the bus interface module; The inter-core communication system of a multi-core processor according to claim 1 .

6. the inter-core communication device further includes an arbitration module connected to the internal memory management module and the queue management module, respectively, and the arbitration module is configured to, when detecting that a plurality of systems are accessing the inter-core communication device simultaneously, arbitrate access for each of the systems according to a predetermined communication order and respond to the access for each of the systems sequentially. The inter-core communication system of a multi-core processor according to claim 1 .

7. The interrupt module is further configured to generate an abnormal interrupt after an abnormality occurs in the internal memory management module, and to generate an abnormal interrupt after an abnormality occurs in the queue management module. The inter-core communication system of a multi-core processor according to claim 1 .

8. 8. An inter-core communication method for a multi-core processor that is applied to the inter-core communication system for a multi-core processor according to claim 1, comprising: receiving a descriptor request command sent by a first system and determining a descriptor pointer corresponding to the descriptor request command, wherein the first system stores data awaiting transmission in an internal memory corresponding to the descriptor pointer; enqueueing the descriptor pointer to a designated queue after receiving an enqueue request sent by the first system; and after the number of enqueues corresponding to the specified queue reaches a preset threshold, dequeuing the descriptor in the specified queue by an interrupt service program of a second system, wherein the second system reads data awaiting transmission in an internal memory corresponding to the dequeued descriptor instruction. A method for inter-core communication in a multi-core processor.

9. An inter-core communication device for a multi-core processor, The multi-core processor inter-core communication device includes a memory, a processor, and a multi-core processor inter-core communication program stored in the memory and running on the processor, and when the multi-core processor inter-core communication program is executed by the processor, the device realizes the steps of the multi-core processor inter-core communication method according to claim 8. Inter-core communication device for multi-core processors.

10. A storage medium, an inter-core communication program for a multi-core processor is stored, and when the inter-core communication program for a multi-core processor is executed by a processor, the steps of the inter-core communication method for a multi-core processor according to claim 8 are realized; storage medium.

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