Bit-length control for linear regression-based affine merge candidate derivation

Abstract

An exemplary device for coding video data comprises a memory configured to store the video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce the bit length of one or more input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks. The one or more processors are configured to perform the linear regression operation and derive an affine motion model based on performing the linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of the video data based on the affine motion model.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 481,590, filed October 5, 2023, and U.S. Provisional Patent Application No. 63 / 379,555, filed October 14, 2022, the entire contents of which are incorporated herein by reference. U.S. Patent Application No. 18 / 481,590, filed October 5, 2023, claims the benefit of U.S. Provisional Patent Application No. 63 / 379,555, filed October 14, 2022.

[0002] TECHNICAL FIELD This disclosure relates to video encoding and decoding. [Background technology]

[0003] Digital video capabilities may be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite wireless telephones, so-called "smartphones," video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video coding techniques such as those described in standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), ITU-T H.266 / Versatile Video Coding (VVC), and extensions to such standards, as well as proprietary video codecs / formats such as AOMedia Video1 (AV1) developed by the Alliance for Open Media. By implementing such video coding techniques, video devices may transmit, receive, encode, decode, and / or store digital video information more efficiently.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. In block-based video coding, video slices (e.g., video pictures or portions of video pictures) may be partitioned into video blocks, which are also sometimes referred to as coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in intra-coded (I) slices of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in inter-coded (P or B) slices of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the Invention

[0005] Generally, this disclosure describes techniques for bit-length control for linear regression-based affine merge candidate derivation. For example, the techniques described herein may apply bit-length control to input variables and intermediate results to meet commonly defined bit-length thresholds, e.g., for hardware implementations of video coders (e.g., video encoders and / or video decoders). A video coder may use several different decisions and calculations to encode and / or decode video data. When implementing such a video coder in hardware, it may be impractical or impossible to successfully implement the video coder without constraint(s) on the bit-lengths of input values ​​and / or intermediate values. For example, without bit-length limitations, certain decisions and / or calculations may cause data overflow. Therefore, it may be desirable to keep the bit-lengths of values ​​in a hardware-implemented video coder to 64 bits or less so that the video coder can be successfully implemented in hardware. This disclosure describes techniques for controlling the bit-lengths of input and intermediate values ​​for linear regression-based affine merge candidate derivation.

[0006] In one example, a method includes controlling the bit length of input variables for a linear regression operation, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; performing a linear regression operation on the controlled bit length input variables; deriving an affine motion model based on performing the linear regression operation; and coding a current block of video data based on the affine motion model.

[0007] In another example, a device includes a memory configured to store video data and one or more processors communicatively coupled to the memory, wherein the one or more processors are configured to control a bit length of input variables for a linear regression operation, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform a linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and code a current block of video data based on the affine motion model.

[0008] In another example, a device includes means for controlling the bit length of input variables for a linear regression operation to generate one or more reduced bit length input variables, the one or more input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; means for performing a linear regression operation on the controlled bit length input variables; means for deriving an affine motion model based on performing the linear regression operation; and means for coding a current block of video data based on the affine motion model.

[0009] In another example, a computer-readable storage medium is encoded with instructions that, when executed, cause one or more programmable processors to control the bit length of input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform the linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and code a current block of video data based on the affine motion model.

[0010] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating an example video encoding and decoding system in which techniques of this disclosure may be implemented. [Figure 2A] FIG. 1 is a conceptual diagram illustrating an example of sub-block-based temporal motion vector prediction. [Figure 2B] FIG. 1 is a conceptual diagram illustrating an example of sub-block-based temporal motion vector prediction. [Figure 3] FIG. 1 is a conceptual diagram illustrating exemplary positions of spatially inherited affine merge candidates. [Figure 4] FIG. 10 is a conceptual diagram illustrating exemplary locations of candidate positions for constructed affine merge modes. [Figure 5] 1 is a conceptual diagram illustrating an example template and example reference samples for the template in a reference picture. [Figure 6] 1 is a conceptual diagram illustrating an example template for a block and an example reference sample for the template, along with motion of the sub-blocks using motion information of the sub-blocks of a current block. [Figure 7] FIG. 1 is a conceptual diagram illustrating exemplary non-adjacent spatial neighboring blocks used to derive non-adjacent affine candidates. [Figure 8] FIG. 10 is a conceptual diagram illustrating other example non-adjacent spatial neighboring blocks used to derive non-adjacent affine candidates. [Figure 9] FIG. 10 is a conceptual diagram illustrating example neighboring block positions for obtaining motion information to construct affine history merge candidates. [Figure 10] FIG. 10 is a conceptual diagram illustrating an example of using motion information to search for non-adjacent affine CUs and derive non-refinement candidates. [Figure 11]FIG. 10 is a conceptual diagram illustrating an example of sub-block information used to derive refinement candidates. [Figure 12] 10 is a flowchart illustrating an example bit-length control technique for linear regression-based affine merge candidate derivation, in accordance with one or more aspects of the present disclosure. [Figure 13] FIG. 2 is a block diagram illustrating an example video encoder that may implement the techniques of this disclosure. [Figure 14] FIG. 2 is a block diagram illustrating an example video decoder that may implement the techniques of this disclosure. [Figure 15] 10 is a flowchart illustrating an example method for encoding a current block, in accordance with techniques of this disclosure. [Figure 16] 10 is a flowchart illustrating an example method for decoding a current block, in accordance with techniques of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Some video coding techniques, for example, when performing linear regression-based affine merge candidate derivation, are defined to employ bit lengths that may be impractical or impossible to implement in hardware. For example, the techniques described herein may apply bit length control to input variables and / or intermediate results to satisfy a commonly defined bit length threshold, for example, for a hardware implementation of a video coder (e.g., a video encoder and / or a video decoder). The commonly defined bit length threshold may be a threshold that is practical to implement in a hardware-based video coder. Defining a common bit length threshold may be desirable because not limiting the bit lengths of input variables and / or intermediate results may result in data overflow. Different implementations may address data overflow in different ways, which may cause one decoder to decode the same encoded video data differently from that of another decoder. Therefore, it may be desirable to limit the bit lengths of input variables and / or intermediate results to satisfy the commonly defined bit length threshold.

[0013] This disclosure therefore describes techniques for ensuring that the bit lengths of values ​​used in linear regression-based affine merge candidate derivation do not exceed a commonly defined bit length threshold, thus facilitating hardware implementation of such video coders. A hardware implementation may be preferable over a software implementation, such as in a mobile device, because a hardware implementation may be more processing power efficient than a software implementation.

[0014] 1 is a block diagram illustrating an example video encoding and decoding system 100 that may implement techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. Generally, video data includes any data for processing video. Thus, video data may include raw uncoded video, coded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0015] 1, in this example, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116. Specifically, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may be or include any of a wide range of devices, such as a desktop computer, a notebook (i.e., laptop) computer, a mobile device, a tablet computer, a set-top box, a telephone handset such as a smartphone, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, a broadcast receiver device, etc. In some cases, source device 102 and destination device 116 may be capable of wireless communication and thus may be referred to as wireless communication devices.

[0016] In the example of FIG. 1 , source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. According to this disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 may be configured to apply techniques for a bitlength control solution for linear regression-based affine merge candidate derivation. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, source device and destination device may include other components or configurations. For example, source device 102 may receive video data from an external video source, such as an external camera. Similarly, destination device 116 may interface with an external display device rather than including an integrated display device.

[0017] System 100 as shown in FIG. 1 is merely an example. In general, any digital video encoding and / or decoding device may implement techniques for bit-length control solutions for linear regression-based affine merge candidate derivation. Source device 102 and destination device 116 are merely examples of coding devices, such that source device 102 generates coded video data that destination device 116 transmits. This disclosure refers to devices that perform coding (encoding and / or decoding) of data as “coding” devices. Accordingly, video encoder 200 and video decoder 300 represent examples of coding devices, specifically, video encoders and video decoders, respectively. In some examples, source device 102 and destination device 116 may operate in a substantially symmetrical manner, such that source device 102 and destination device 116 each include video encoding and decoding components. Thus, system 100 may support unidirectional or bidirectional video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0018] Generally, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a continuous series of pictures (also called “frames”) of the video data to video encoder 200, which encodes the picture data. Video source 104 of source device 102 may include a video capture device such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface that receives video from a video content provider. As a further alternative, video source 104 may generate computer-graphics-based data as source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes the captured video data, pre-captured video data, or computer-generated video data. Video encoder 200 may reorder the pictures from the order in which they were received (sometimes referred to as “display order”) into a coding order for coding. Video encoder 200 may generate a bitstream containing the encoded video data. Source device 102 may then output the encoded video data via output interface 108 to computer-readable medium 110, for receipt and / or retrieval by input interface 122 of destination device 116, for example.

[0019] Memory 106 of source device 102 and memory 120 of destination device 116 represent general-purpose memory. In some examples, memory 106, 120 may store raw video data, e.g., raw video from video source 104 and raw decoded video data from video decoder 300. Additionally or alternatively, memory 106, 120 may store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. While memory 106 and memory 120 are shown separate from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may also include internal memory for functionally similar or equivalent purposes. Furthermore, memory 106, 120 may store, e.g., encoded video data output from video encoder 200 and input to video decoder 300. In some examples, portions of memory 106, 120 may be allocated as one or more video buffers, for example, to store raw decoded video data and / or encoded video data.

[0020] The computer-readable medium 110 may represent any type of medium or device capable of transferring encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to transmit encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. The output interface 108 may modulate a transmission signal containing the encoded video data, and the input interface 122 may demodulate a received transmission signal in accordance with a communication standard such as a wireless communication protocol. The communication medium may comprise any wireless or wired communication medium, such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful for facilitating communication from the source device 102 to the destination device 116.

[0021] In some examples, source device 102 may output encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a DVD, a CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium that stores encoded video data.

[0022] In some examples, source device 102 may output encoded video data to file server 114 or another intermediate storage device, which may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or download.

[0023] File server 114 may be any type of server device capable of storing encoded video data and transmitting the encoded video data to destination device 116. File server 114 may represent a web server (e.g., for a website), a server configured to provide file transfer protocol services (such as File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or Enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. The file server 114 may additionally or alternatively implement one or more HTTP streaming protocols, such as Dynamic Adaptive Streaming over HTTP (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, etc.

[0024] Destination device 116 may access the encoded video data from file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on file server 114. Input interface 122 may be configured to operate according to any one or more of the various protocols mentioned above to retrieve or receive media data from file server 114, or other such protocols to retrieve media data.

[0025] Output interface 108 and input interface 122 may represent a wireless transmitter / receiver, a modem, a wired network component (e.g., an Ethernet card), a wireless communication component operating according to any of the various IEEE 802.11 standards, or other physical components. In examples in which output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to a cellular communication standard such as 4G, 4G-LTE (Long Term Evolution), LTE Advanced, 5G, etc. In some examples in which output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to other wireless standards such as the IEEE 802.11 standard, the IEEE 802.15 standard (e.g., ZigBee), the Bluetooth standard, etc. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, source device 102 may include an SoC device that performs the functionality attributed to video encoder 200 and / or output interface 108, and destination device 116 may include an SoC device that performs the functionality attributed to video decoder 300 and / or input interface 122.

[0026] The techniques of this disclosure may be applied to video coding supporting any of a variety of multimedia applications, such as over-the-air television broadcast, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded on a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0027] The input interface 122 of the destination device 116 receives the coded video bitstream from the computer-readable medium 110 (e.g., a communications medium, a storage device 112, a file server 114, etc.). The coded video bitstream may include signaling information defined by the video encoder 200 that is also used by the video decoder 300, such as syntax elements having values ​​that describe the characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0028] Although not shown in FIG. 1, in some examples, the video encoder 200 and the video decoder 300 may each be integrated with an audio encoder and / or an audio decoder, and may include appropriate MUX-DEMUX units or other hardware and / or software to handle multiplexed streams that include both audio and video in a common data stream.

[0029] The video encoder 200 and the video decoder 300 may each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to implement the techniques of this disclosure. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (CODEC) in the respective device. Devices including the video encoder 200 and / or the video decoder 300 may implement the video encoder 200 and / or the video decoder 300 in processing circuitry, such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular telephone, or any other type of device described herein.

[0030] The video encoder 200 and the video decoder 300 may operate according to a video coding standard such as ITU-T H.265, also known as High Efficiency Video Coding (HEVC), or an extension thereof, such as multiview and / or scalable video coding extensions. Alternatively, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards, such as ITU-T H.266, also known as Generic Video Coding (VVC). In other examples, the video encoder 200 and the video decoder 300 may operate according to a proprietary video codec / format such as AOMedia Video1 (AV1), an extension of AV1, and / or a successor version of AV1 (e.g., AV2). In other examples, the video encoder 200 and the video decoder 300 may operate according to other proprietary formats or industry standards. However, the techniques of this disclosure are not limited to any particular coding standard or format. In general, video encoder 200 and video decoder 300 may be configured to perform the techniques of this disclosure with any video coding technique that uses linear regression-based affine merge candidate derivation. For example, the bit depth control techniques disclosed herein may be used to meet a commonly defined bit depth threshold.

[0031] In general, the video encoder 200 and the video decoder 300 may perform block-based coding of pictures. The term “block” generally refers to a structure containing data to be processed (e.g., encoded, decoded, or otherwise used in an encoding and / or decoding process). For example, a block may include a two-dimensional matrix of luminance and / or chrominance data samples. In general, the video encoder 200 and the video decoder 300 may code video data represented in YUV (e.g., Y, Cb, Cr) format. That is, rather than coding red, green, and blue (RGB) data for picture samples, the video encoder 200 and the video decoder 300 may code luminance and chrominance components, which may include both red and blue chrominance components. In some examples, the video encoder 200 converts received RGB-format data to a YUV representation before encoding, and the video decoder 300 converts the YUV representation to RGB format. Alternatively, pre-processing and post-processing units (not shown) may perform these conversions.

[0032] This disclosure may generally refer to coding (e.g., encoding and decoding) a picture as including the process of encoding or decoding data for a picture. Similarly, this disclosure may refer to coding a block of a picture as including the process of encoding or decoding data for the block, e.g., predictive and / or residual coding. A coded video bitstream generally includes a series of values ​​of syntax elements that represent coding decisions (e.g., coding modes) and the partitioning of a picture into blocks. Thus, references to coding a picture or a block should generally be understood as coding values ​​of the syntax elements that form the picture or block.

[0033] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (such as video encoder 200) partitions coding tree units (CTUs) into CUs according to a quadtree structure. That is, the video coder partitions CTUs and CUs into four equal, non-overlapping squares, and each node of the quadtree has either zero or four child nodes. A node with no child nodes may be called a "leaf node," and a CU of such a leaf node may include one or more PUs and / or one or more TUs. The video coder may further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents the partitioning of TUs. In HEVC, a PU represents inter-predicted data, and a TU represents residual data. An intra-predicted CU includes intra-prediction information, such as an intra-mode indication.

[0034] As another example, video encoder 200 and video decoder 300 may be configured to operate according to VVC. According to VVC, a video coder (such as video encoder 200) partitions a picture into multiple CTUs. Video encoder 200 may partition the CTUs according to a tree structure, such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple partition types, such as the separation between CUs, PUs, and TUs in HEVC. The QTBT structure includes two levels: a first level partitioned according to quadtree partitioning and a second level partitioned according to binary tree partitioning. The root node of the QTBT structure corresponds to a CTU. The leaf nodes of the binary tree correspond to CUs.

[0035] In the MTT partitioning structure, blocks may be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of triple tree (TT) (also called ternary tree (TT)) partitioning. A triple tree partitioning or triple tree partitioning is a partitioning in which a block is divided into three sub-blocks. In some examples, a triple tree partitioning or triple tree partitioning divides a block into three sub-blocks without splitting the original block through the center. The partition types in MTT (e.g., QT, BT, and TT) can be symmetric or asymmetric.

[0036] When operating according to the AV1 codec, the video encoder 200 and the video decoder 300 may be configured to code video data in blocks. In AV1, the largest coding block that can be processed is called a superblock. In AV1, a superblock can be either 128x128 luma samples or 64x64 luma samples. However, in successor video coding formats (e.g., AV2), a superblock can be defined by a different (e.g., larger) luma sample size. In some examples, a superblock is the top level of a block quadtree. The video encoder 200 may further partition the superblock into smaller coding blocks. The video encoder 200 may partition the superblock and other coding blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N / 2xN, NxN / 2, N / 4xN, and NxN / 4 blocks. The video encoder 200 and the video decoder 300 may perform separate prediction and transform processes for each of the coding blocks.

[0037] AV1 also defines tiles of video data. A tile is a rectangular array of superblocks that may be coded independently of other tiles. That is, video encoder 200 and video decoder 300 may encode and decode coding blocks within a tile, respectively, without using video data from other tiles. However, video encoder 200 and video decoder 300 may perform filtering across tile boundaries. Tiles may be uniform or non-uniform in size. Tile-based coding may enable parallel processing and / or multithreading for encoder and decoder implementations.

[0038] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luminance and chrominance components, and in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luminance component and another QTBT / MTT structure for both chrominance components (or two QTBT / MTT structures for each chrominance component).

[0039] Video encoder 200 and video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, superblock partitioning, or other partitioning structures.

[0040] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples for a picture having three sample arrays, or a CTB of samples for a picture coded using three separate color planes and syntax structures used to code a monochrome picture or samples. A CTB may be an N×N block of samples for some value of N, partitioned to divide the components into CTBs. A component is an array or a single sample from one of the three arrays (luma and two chroma) that make up a picture in 4:2:0, 4:2:2, or 4:4:4 color format, or a single sample from an array or arrays that make up a picture in monochrome format. In some examples, a coding block is an M×N block of samples for some values ​​of M and N, partitioned to divide the CTB into coding blocks.

[0041] Blocks (e.g., CTUs or CUs) may be grouped in various ways within a picture. As an example, a brick may refer to a rectangular region of a CTU row within a particular tile within a picture. A tile may be a rectangular region of CTUs within a particular tile column and a particular tile row within a picture. A tile column refers to a rectangular region of CTUs with a height equal to the height of the picture and a width specified by a syntax element (e.g., in a picture parameter set). A tile row refers to a rectangular region of CTUs with a height specified by a syntax element (e.g., in a picture parameter set) and a width equal to the width of the picture.

[0042] In some examples, a tile may be partitioned into multiple bricks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple bricks may also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile. Bricks within a picture may also be arranged as slices. A slice may be an integer number of bricks of a picture that may be contained exclusively within a single network abstraction layer (NAL) unit. In some examples, a slice includes either several complete tiles or only a continuous sequence of complete bricks of one tile.

[0043] This disclosure may use "N x N" and "N by N," e.g., 16 x 16 samples or 16 by 16 samples, interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in the vertical and horizontal dimensions. Generally, a 16 x 16 CU has 16 samples in the vertical direction (y = 16) and 16 samples in the horizontal direction (x = 16). Similarly, an N x N CU generally has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. Samples within a CU may be arranged in rows and columns. Furthermore, a CU does not necessarily have to have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU may include N x M samples, where M is not necessarily equal to N.

[0044] Video encoder 200 encodes video data for a CU that represents prediction and / or residual information and other information. The prediction information indicates how the CU will be predicted to form a predictive block for the CU. The residual information generally represents sample-by-sample differences between the samples of the CU before encoding and the predictive block.

[0045] To predict a CU, video encoder 200 may generally form a predictive block for the CU through inter prediction or intra prediction. Inter prediction generally refers to predicting a CU from data of a previously coded picture, and intra prediction generally refers to predicting a CU from previously coded data of the same picture. To perform inter prediction, video encoder 200 may generate a predictive block using one or more motion vectors. Video encoder 200 may generally perform a motion search to identify a reference block that closely matches the CU, for example, with respect to the difference between the CU and the reference block. Video encoder 200 may calculate a difference metric using a sum of absolute difference (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), or other such difference calculation to determine whether the reference block closely matches the current CU. In some examples, video encoder 200 may predict the current CU using unidirectional prediction or bidirectional prediction.

[0046] Some examples of VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In affine motion compensation mode, video encoder 200 may determine two or more motion vectors that represent non-translational motion, such as zooming in or out, rotation, perspective movement, or other irregular motion types.

[0047] To perform intra prediction, video encoder 200 may select an intra prediction mode to generate a predicted block. Some examples of VVC provide 67 intra prediction modes, including various directional modes, as well as a planar mode and a DC mode. Generally, video encoder 200 selects an intra prediction mode that describes neighboring samples relative to a current block (e.g., a block of a CU) and predicts samples of the current block therefrom. Assuming that video encoder 200 codes CTUs and CUs in raster scan order (left to right, top to bottom), such samples may generally be above, above and to the left, or to the left of the current block in the same picture as the current block.

[0048] The video encoder 200 encodes data representing a prediction mode for the current block. For example, in the case of an inter prediction mode, the video encoder 200 may encode data representing which of various available inter prediction modes is used as well as motion information for the corresponding mode. In the case of unidirectional or bidirectional inter prediction, for example, the video encoder 200 may encode motion vectors using an advanced motion vector prediction (AMVP) mode or a merge mode. The video encoder 200 may use a similar mode to encode motion vectors for an affine motion compensation mode.

[0049] AV1 includes two general techniques for encoding and decoding coding blocks of video data. The two general techniques are intra-prediction (e.g., intra-frame prediction or spatial prediction) and inter-prediction (e.g., inter-frame prediction or temporal prediction). In the context of AV1, when predicting a block of a current frame of video data using an intra-prediction mode, the video encoder 200 and the video decoder 300 do not use video data from other frames of the video data. In most intra-prediction modes, the video encoder 200 encodes the block of the current frame based on the difference between sample values ​​in the current block and predicted values ​​generated from reference samples in the same frame. The video encoder 200 determines the predicted values ​​generated from the reference samples based on the intra-prediction mode.

[0050] Following prediction, such as intra- or inter-prediction, of a block, the video encoder 200 may calculate residual data for the block. The residual data, such as a residual block, represents sample-by-sample differences between the block and a prediction block for that block formed using a corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to generate transform data in the transform domain rather than the sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. In addition, the video encoder 200 may apply a secondary transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, or a Karhunen-Loeve transform (KLT), following the initial transform. The video encoder 200 generates transform coefficients following application of the one or more transforms.

[0051] As described above, following any transform that generates transform coefficients, the video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, the video encoder 200 may truncate an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift of the value to be quantized.

[0052] Following quantization, the video encoder 200 may scan the transform coefficients, generating a one-dimensional vector from a two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place transform coefficients with higher energy (and therefore lower frequency) at the front of the vector and transform coefficients with lower energy (and therefore higher frequency) at the back of the vector. In some examples, the video encoder 200 may use a predefined scan order to scan the quantized transform coefficients to generate a serialized vector and then entropy code the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform adaptive scanning. After scanning the quantized transform coefficients to form the one-dimensional vector, the video encoder 200 may entropy code the one-dimensional vector, for example, according to context-adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy code values ​​for syntax elements describing metadata associated with the encoded video data for use by the video decoder 300 in decoding the video data.

[0053] To implement CABAC, video encoder 200 may assign a context in a context model to a symbol to be transmitted. The context may relate, for example, to whether neighboring values ​​of the symbol are zeroed. A probability determination may be based on the context assigned to the symbol.

[0054] Video encoder 200 may further generate syntax data, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data, for example, within a picture header, a block header, a slice header, or other syntax data, such as a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS), to video decoder 300. Video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data.

[0055] In this manner, video encoder 200 may generate a bitstream including coded video data, e.g., syntax elements that describe partitions of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Finally, video decoder 300 may receive the bitstream and decode the coded video data.

[0056] Generally, video decoder 300 performs a reciprocal process to that performed by video encoder 200 to decode encoded video data of a bitstream. For example, video decoder 300 may decode values ​​for syntax elements of a bitstream using CABAC in a manner that is reciprocal but substantially similar to the CABAC encoding process of video encoder 200. The syntax elements may define partition information for the partition of a picture into CTUs and the partition of each CTU according to a corresponding partition structure, such as a QTBT structure, to define the CUs of the CTU. The syntax elements may further define prediction information and residual information for blocks of video data (e.g., CUs).

[0057] The residual information may be represented, for example, by quantized transform coefficients. The video decoder 300 may dequantize and inverse transform the quantized transform coefficients of the block to reconstruct a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-prediction or inter-prediction) and related prediction information (e.g., motion information for inter-prediction) to form a predictive block for the block. The video decoder 300 can then combine the predictive block and the residual block (sample by sample) to reconstruct the original block. The video decoder 300 may also perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0058] This disclosure may generally refer to “signaling” some information, such as a syntax element. The term “signaling” may generally refer to communication of values ​​for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values ​​for syntax elements within a bitstream. Generally, signaling refers to generating values ​​within a bitstream. As mentioned above, source device 102 may forward the bitstream to destination device 116 in substantially real time or non-real time, which may occur, for example, when storing syntax elements in storage device 112 for later retrieval by destination device 116.

[0059] According to the techniques of this disclosure, a video coder, such as video encoder 200 or video decoder 300, can control (e.g., reduce or limit) the bit length of input variables for a linear regression operation, perform the linear regression operation on the controlled bit length input variables, derive an affine motion model based on performing the linear regression operation, and code a current block of video data based on the affine motion model.

[0060] Versatile Video Coding (VVC) (e.g., J. Chen, Y. Ye and S. Kim, "Algorithm description for Versatile Video Coding and Test Model 9 (VTM 9)"), Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 18 thVVC (see Meeting: by Teleconference, 15-24 April 2020, JVET-R2002) is a recent video coding standard developed by the Joint Video Experts Team (JVET) of ITU-T and ISO / IEC that achieves substantial compression capabilities beyond HEVC for a wider range of applications. The VVC specification was finalized in July 2020 and published by both ITU-T and ISO / IEC. The VVC specification specifies normative bitstream and picture formats, high-level syntax (HLS) and coding unit-level syntax, and parsing and decoding processes. VVC also specifies profile / tier / level (PTL) restrictions, byte stream formats, hypothetical reference decoders, and supplemental enhancement information (SEI) in annexes.

[0061] Starting in April 2021, JVET has been developing the Enhanced Compression Model (ECM) software to enhance compression capabilities beyond VVC (e.g., M. Coban, F.L. Leannec and J. Strom, "Algorithm description for Enhanced Compression Model 2 (ECM 2)," Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11,23 rd (See Meeting: by Teleconference, 7-16 July 2021, JVET-W2025). The set of coding tools within the ECM software encompasses all functional blocks within a hybrid video coding framework (e.g., a video coding framework that uses prediction), including intra prediction, inter prediction, transform and coefficient coding, in-loop filtering, and entropy coding. The techniques of this disclosure may be applied to ECM, as well as state-of-the-art video codecs such as VVC, AV1, and / or future video codecs.

[0062] 2A-2B are conceptual diagrams illustrating an example of sub-block-based temporal motion vector prediction (SbTMVP). As shown in FIGS. 2A-2B, SbTMVP predicts motion vectors of sub-CUs (e.g., sub-blocks) within a current CU. First, video encoder 200 or video decoder 300 may examine the spatial neighborhood A1 of current block 150 in FIG. 2A. If A1 has a motion vector that uses a co-located picture as its reference picture, this motion vector is selected to be the motion shift to be applied. If no such motion vector is identified, the motion shift is set to (0, 0). For example, video encoder 200 or video decoder 300 may determine whether A1 has a motion vector that uses a co-located picture as its reference picture and select a motion shift based on the determination.

[0063] Second, the motion shift identified above is added to the coordinates of the current block of the current picture 154 to obtain sub-CU level motion information (motion vector and reference index) from the co-located picture 152, as shown in FIG. 2B. For example, the video encoder 200 or the video decoder 300 may add the motion shift to the coordinates of the current block. The example of FIG. 2B assumes that the motion shift is set to the motion of block A1. After the motion information of the co-located sub-CU is identified, the video encoder 200 or the video decoder 300 may convert the motion information into a motion vector and a reference index of the current sub-CU in a manner similar to the TMVP (Temporal Motion Vector Prediction) process of VVC, and temporal motion scaling is applied to align the reference picture of the temporal motion vector with the reference picture of the current CU.

[0064] The SbTMVP predictor is added as the first entry to a list of sub-block-based merge candidates, followed by affine merge candidates. SbTMVP differs from TMVP in the following two aspects: TMVP predicts motion at the CU level, while SbTMVP predicts motion at the sub-CU level. TMVP fetches temporal motion vectors from co-located blocks in a co-located picture (the co-located block is the bottom-right or center block with respect to the current CU), while SbTMVP applies a motion shift before fetching temporal motion information from a co-located picture, where the motion shift is obtained from the motion vector of one of the spatial neighboring blocks of the current CU. For example, video encoder 200 or video decoder 300 may determine an SbTMVP predictor and add such predictor as the first entry to a list of sub-block-based merge candidates.

[0065] Next, the sub-block merge candidate list will be described. The following four types of sub-block merge candidates are used to form the sub-block merge candidate list, where the first entry is SbTMVP and the other entries are affine merge candidates. The determination of SbTMVP is as described above.

[0066] Inherited affine merge candidates (I-AffineMVPs) extrapolated from the CPMVs (control point motion vectors) of neighboring CUs may also be used in the sub-block merge candidate list. There are up to two inherited affine candidates in the sub-block merge candidate list, which are derived from the affine motion models of neighboring blocks, for example, one from the left-neighboring CU and one from the top-neighboring CU. For example, video encoder 200 or video decoder 300 may determine inherited affine candidates and add up to two such candidates in the sub-block merge candidate list.

[0067] FIG. 3 is a conceptual diagram illustrating exemplary positions of spatially inherited affine merge candidates. Candidate block positions are shown in FIG. 3 for the current block 156. For the left predictor, the scan order is A0->A1, and for the top predictor, the scan order is B0->B1->B2. Only the first inherited candidate from each group is selected. No pruning check is performed between two inherited candidates. When a neighboring affine CU containing the scan position is identified, control point motion vectors (CPMVs) from the identified affine CU are used to derive CPMVs of affine merge candidates for the current CU (e.g., current block 156).

[0068] The video encoder 200 or the video decoder 300 may also add a constructed affine merge candidate (C-AffineMVP) derived using the translational MVs of neighboring CUs to the sub-block merge candidate list. A constructed affine candidate means that the candidate is constructed by combining neighboring translational motion information of each control point.

[0069] Figure 4 is a conceptual diagram illustrating exemplary locations of candidate positions for the constructed affine merge mode. Motion information for control points is derived from designated spatial and temporal neighboring blocks of the current block 400 shown in Figure 4. CPMVk (k=1, 2, 3, 4) represents the kth control point. For CPMV1, the B2->B3->A2 block is checked, and the MV of the first available block is used. For CPMV2, the B1->B0 block is checked, and for CPMV3, the A1->A0 block is checked. If TMVP is available, it is used as CPMV4. The following combinations of control point MVs are used to construct affine merge candidates in a given order with at most six different candidates: {CPMV1, CPMV2, CPMV3}, {CPMV1, CPMV2, CPMV4}, {CPMV1, CPMV3, CPMV4}, {CPMV2, CPMV3, CPMV4}, {CPMV1, CPMV2}, {CPMV1, CPMV3}. A combination of three CPMVs constructs a six-parameter affine merge candidate, and a combination of two CPMVs constructs a four-parameter affine merge candidate. To avoid the motion scaling process, related combinations of control point MVs can be discarded if the reference indices of the control points are different.

[0070] Video encoder 200 or video decoder 300 may also add 0MV to the sub-block merge candidate list if the list is not full after the inherited and constructed affine merge candidates have been checked. 0MV is inserted until the list is full.

[0071] Next, we describe adaptive reordering of merge candidates (ARMC). In ECM, merge candidates are adaptively reordered through the use of template matching (TM). The reordering technique is applied to the regular merge candidate list, the TM merge candidate list, and the affine merge candidate list (sub-block merge candidate list excluding SbTMVP candidates). In the TM merge mode, merge candidates are reordered before the TM refinement process.

[0072] After the merge candidate list is constructed, the merge candidates are divided into several subgroups. For example, the video encoder 200 or the video decoder 300 may divide the merge candidates into subgroups. The subgroup size is set to 5 for the regular merge mode and the TM merge mode. The subgroup size is set to 3 for the affine merge mode. The merge candidates within each subgroup are sorted in ascending order according to their TM-based cost values. For simplicity, merge candidates within the last but not the first subgroup are not sorted.

[0073] The TM cost of a merge candidate can be measured, for example, by the sum of absolute differences (SAD) between the template samples of the current block and their corresponding reference samples. The template comprises a set of reconstructed samples neighboring the current block. The template's reference samples are positioned according to the motion information of the merge candidate.

[0074] 5 is a conceptual diagram illustrating an exemplary template and exemplary reference samples of the template in a reference picture. When a merge candidate for a current block of a current picture 500 utilizes bi-prediction (e.g., has a reference picture in reference list 0 502 and a reference picture in reference list 1 504), the reference samples of the merge candidate's template are also generated by bi-prediction, as shown in FIG. 5. For a sub-block-based merge candidate with a sub-block size equal to W×H, the top template comprises several sub-templates with a size of W×1, and the left template comprises several sub-templates with a size of 1×H. As shown in FIG. 6, motion information of sub-blocks in the first row and first column of the current block is used to derive the reference samples of each sub-template. For example, the video encoder 200 or the video decoder 300 may use bi-prediction to derive the reference samples of each sub-template.

[0075] Figure 6 is a conceptual diagram illustrating an example template and example reference samples for a current block, along with the motion of the sub-blocks using motion information of the sub-blocks of the current block. A current picture 602 includes a current block 600. A co-located picture 604 includes a co-located block 606. For a sub-block-based merging candidate with a sub-block size equal to W × H, the top template includes several sub-templates 608 with a size of W × 1, and the left template includes several sub-templates 610 with a size of 1 × H. As shown in Figure 6, the motion information of the sub-blocks in the first row and first column of the current block 600 is used to derive reference samples for each sub-template.

[0076] FIG. 7 is a conceptual diagram illustrating exemplary non-adjacent spatial neighboring blocks used to derive non-adjacent affine candidates. Next, non-adjacent affine merge candidates will be described. Currently, in the normal merge list construction process of ECM, non-adjacent merge candidates are added as a new category of regular merge candidates. For example, the non-adjacent merge candidate is currently a non-adjacent merge candidate in block 700. A non-adjacent merge candidate scanning pattern as shown in FIG. 7 is used to search for non-adjacent merge candidates. Non-adjacent merge candidates may be useful in improving normal merge mode performance. Therefore, to further improve the performance of the sub-block merge mode, the video encoder 200 or the video decoder 300 can search for non-adjacent affine CUs and add the non-adjacent affine merge candidates to the sub-block merge candidate list. In some examples, the video encoder 200 or the video decoder 300 may reuse the same non-adjacent merge scanning pattern to search for non-adjacent affine CUs instead. The scanning order may follow the index in ascending order, as shown in FIG. 7. After the non-adjacent affine CU is found, the video encoder 200 or the video decoder 300 can either directly derive the CPMV of the non-adjacent affine CU from the non-adjacent position to the current CU position, or use the motion vector field of the non-adjacent affine CU to derive the affine model of the current CU through a linear regression process.

[0077] FIG. 8 is a conceptual diagram illustrating another example of non-adjacent spatial neighbors used to derive non-adjacent affine candidates. The extension of non-adjacent merge candidates to non-adjacent affine merge candidates was proposed at the JVET-X conference, and various scan patterns can be designed. W. Chen, X. Xiu, Y.-W. Chen, H.-J. Jhu, C.-W. Kuo, N. Yan, and X. Wang, "AHG12: Non-adjacent spatial neighbors for affine merge mode," JVET-X0151, October 2021, describes a scan pattern different from that of FIG. 7, as shown in FIG. 8.

[0078] The scanning order may follow that shown in Figure 8. For example, non-adjacent affine CUs may follow the scanning order of Figure 8. Non-adjacent spatial neighboring blocks of the current block 800 are checked based on their distance to the current block 800, i.e., from near to far. At a particular distance, the video encoder 200 or the video decoder 300 may scan horizontally from right to left and vertically from bottom to top.

[0079] By using any of the above scanning patterns, non-adjacent affine CU(s) can be identified and their corresponding motion vector field(s) can potentially be used as input to a linear regression process to derive an affine model of the current CU.

[0080] Next, we will describe history-based affine merge candidates. History merge candidates were introduced during the VVC standardization process, which buffers motion vectors of previously decoded CUs and uses them for motion vector prediction of the current CU. Similar to the extension of non-adjacent merge candidates to non-adjacent affine merge candidates, the concept of history-based merge candidates can also be extended to history-based affine merge candidates.

[0081] FIG. 9 is a conceptual diagram illustrating exemplary neighboring block positions for obtaining motion information to construct affine history merge candidates. A practical example of history-based affine merge candidate construction can be found in K. Zhang, L. Zhang, Z. Deng, N. Zhang, and Y. Wang, "EE2-3.12-related: Extensions of history-parameter-based affine model inheritance," JVET-Y0161, January 2022. In this proposal, two different categories of affine history tables are proposed. In one type of affine history table, only affine parameters from previously decoded CUs are buffered. Multiple tables are created, each corresponding to a given reference index and reference list. In this design, for a particular affine history table, all affine history entries share the same reference picture. When using a history table to construct affine merge candidates for a current block, such as current block 900, spatial neighboring block positions are first determined, as shown in FIG. 9.

[0082] The reference list and reference index from the spatial neighboring block current block 900 are used to determine the affine history table. The motion vector serves as a base motion vector, and together with one of the entries in the affine history table, an affine merge candidate or motion vector field for the current CU may be derived. For example, video encoder 200 or video decoder 300 may derive an affine merge candidate or motion vector field for the current CU.

[0083] In another type of affine history table, not only the affine parameters but also the top-left CPMV and top-left coordinate of a previously decoded CU are buffered. A reference index and a reference list are also used and inherited by the current CU. Construction of an affine merge candidate can be performed using only one of the entries in the affine history table without additional information. The video encoder 200 or the video decoder 300 may use the buffered top-left CPMV, affine parameters, top-left coordinate, and coordinate of the current CU to derive an affine model for the current CU. Meanwhile, since the top-left coordinate of a previously decoded CU is buffered, the video encoder 200 or the video decoder 300 may also directly access the motion vector field of the decoded CU.

[0084] Next, we will discuss multivariate linear regression. Multivariate linear regression, also known as multiple regression, is a statistical technique that can be used to analyze the relationship between a single dependent variable and several independent variables. The goal of multiple regression analysis is to use independent variables, whose values ​​are known, to predict the value of a single dependent variable, which is unknown. Each predictor value is weighted, and the weights indicate their relative contribution to the overall prediction, and the weights are summed to form the prediction. The general model of multivariate linear regression is given by Equation 1. Y=a+b1X1+b2X2+...+b n X n (1)

[0085] where Y is the dependent variable and X1,...,X n are n independent variables. Weights a, b1, ..., b n In calculating , the least squares method can be applied to minimize the mean square error between the statistical observation sample and the estimated value.

[0086] In VVC, the motion vector of each sub-block is derived based on a linear model. To better represent zoom-in / out, rotation, perspective motion, and other irregular motion, block-based affine transformation motion compensation prediction is applied. The motion vector at the sample location (x, y) of the sub-block center is derived as follows:

[0087]

number

[0088] Here, mv x For example, mv 0x ,mv 1x and MV 2x are the horizontal motion vector components of the corresponding top-left, top-right, and bottom-left control point motion vectors (CPMVs), which are known for a given affine model. W and H are the width and height of the current CU, which are also known. In this case, mv x The formula for deriving can be written as a linear regression formula. This is mv y This observation allows the affine motion model to be equivalently expressed by two linear equations in matrix form as follows:

[0089]

number

[0090]

number

[0091] Using the above equations, the derivation of an affine motion model may be equivalent to the derivation of several coefficients in a linear equation. The estimation of such linear coefficients can be solved by multivariate linear regression. For example, the video encoder 200 or the video decoder 300 may use multivariate linear regression to derive the affine model.

[0092] To apply multivariate linear regression to affine model derivation, the video encoder 200 or the video decoder 300 may collect motion vector information and its corresponding sub-block coordinates. The coordinates may be independent variables, and the motion vector components may be dependent variables. Given N motion vectors and their corresponding sub-block center coordinates, the affine model parameters can be derived using the following formula (see, for example, R. Ghaznavi-Youvalarim, A. Aminlou, and J. Lainema, “Regression-Based Motion Vector Field for Video Coding,” IEEE Transactions on Circuits and Systems for Video Technology, Volume: 31, Issue: 5, May 2021):

[0093]

number

[0094]

number

[0095] B c,d and for the construction of the A matrix, the following formula is used:

[0096]

number

[0097] In this method, an optimal affine model can be derived to best describe an input motion vector, given its corresponding coordinates in the minimum mean square error sense.

[0098] To elaborate, an example is now given to show how a linear model can be output from an input motion vector field. Suppose the video encoder 200 or the video decoder 300 collects motion information from several motion vector fields, and the N motion vectors are calculated as {(mv x0 ,mv y0 ),(mv x1 ,mv y1 ),...,(mv xN-1 ,mv yN-1 )} and the corresponding center coordinates are {(x0,y0),(x1,y1),...,(x N-1 ,y N-1 )}.

[0099] In a first step, the video encoder 200 or the video decoder 300 determines an anchor coordinate that serves as the origin of the output linear model, instead of using (0, 0), which is the top-left coordinate of the entire picture to avoid large value(s) in the calculation. This step is also performed to facilitate deriving affine merge candidates after the linear model parameters are derived from the linear regression process. Typically, the video encoder 200 or the video decoder 300 chooses the top-left coordinate of the current CU as the origin. (x tl ,y tl ), the coordinates of each sub-block are expressed as (x tl ,y tl The relative coordinates are calculated by subtracting {(x0-x t1 ,y0-y t1 )(x1-x t1 ,y1-y t1 )...,(x N-1 -x t1 ,y N-1 -y t1 )}. x i '=x i -xtl y i '=y i -y tl where i∈{0,1,...,N-1}, and therefore {(x0',y0'),(x1',y1'),...,(x N-1 ',y N-1 ')}.

[0100] With respect to motion vectors, the video encoder 200 or the video decoder 300 can also optionally choose an initial motion vector to subtract to avoid large values ​​in the calculations, although this is not required since motion vector values ​​are relatively small compared to coordinate values. Also, motion vectors can have negative values, and subtracting a negative value from a positive value will only result in an even larger positive value.

[0101] The output linear model parameters may be estimated using the mean square error (MSE) minimization method for the N available neighboring MVs, where the MSE is calculated as the sum of the estimated MVs {(mv x0 ',mv y0 '),(mv x1 ',mv y1 '),...,(mv xN-1 ',mv yN-1 ')} and the actual value of the input MV {(mv x0 ,mv y0 ),(mv x1 ,mv y1 ),...,(mv xN-1 ,mv yN-1 )}.

[0102]

number

[0103] Mathematically, the solution to MSE minimization is given by equation (4) above.

[0104] Parameter b x,0 For example, the derivation of matrix A is A with i,j∈{0,1,2}. i,j =suml'l' i,j where l'0 is x' for each sub-block, l'1 is y' for each sub-block, and l'2=1 for all sub-blocks.

[0105]

number

[0106] b x,0 Regarding matrix B when deriving matrix B, x,0 is required. From equation (9),

[0107]

number

[0108]

number

[0109]

number

[0110]

number

[0111]

number

[0112]

number

[0113] Matrices A and B x,0 Using the coefficient

[0114]

number

[0115] Applying a similar procedure to the other coefficients, all linear model parameters

[0116]

number

[0117] Using the estimated parameters, the affine merge candidate for the current CU is (mv tl ,mv tl ), mv tr ,mv tr ),(mv bl ,mv bl The top-left, top-right, and bottom-left CPMVs, denoted as ), can be derived using equation (2), which is equal to: (mv tl , mv tl )=(b x2 ,b y2 ) (mv tr , mv tr )=(b x0 W+b x2 ,b y0 W+b y2 ) (mv bl , mv bl )=(b x1 H+b x2 ,b y1 H+b y2 ) W and H are the width and height of the current CU. x and y in equation (2) are replaced by the relative distance from the top-left position of the current CU to the position of the corresponding CPMV.

[0118] Next, we will explain linear regression-based affine merge candidates. In ECM6.0, Y. Zhang, H. Huang, V. Seregin, M. Coban, and M. Karczewicz, "EE2-2.1: Regression-based affine candidate derivation," Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 27 th We adopt the linear regression-based affine merge candidate derivation proposed in the Meeting: by Teleconference, 13-22 July 2022, JVET-AA0107. In this proposal, two types of linear regression-based affine merge candidates are derived: unrefined candidates and refined candidates. For both types of candidates, the derivation process is the same, only different sub-block motion information is used as input.

[0119] FIG. 10 is a conceptual diagram illustrating an example of using motion information to search for non-adjacent affine CUs and derive unrefined candidates. For unrefined candidates, only sub-block motion information from non-adjacent affine CUs is used as input to the linear regression process. FIG. 10 shows an example of input to the linear regression process to derive unrefined linear regression-based affine merge candidates for a current block 1000. As mentioned above, a specific scanning pattern can be used when searching for non-adjacent affine CUs. Once a non-adjacent affine CU, e.g., block 1002 as shown in FIG. 10, is identified, {(mv x0 ,mv y0 ),(mv x1 ,mv y1 ),...,(mv xN-1 ,mv yN-1)} and the sub-block motion vectors denoted by {(x0,y0),(x1,y1),...,(x N-1 ,y N-1 Each of the motion information of the sub-blocks containing the center coordinates denoted by {} is input into a linear regression process to derive unrefined affine merge candidates.

[0120] 11 is a conceptual diagram illustrating an example of sub-block information used to derive refinement candidates. For refinement candidates, in addition to motion information from sub-blocks with hash filling 1100 in non-adjacent affine CUs (representing non-adjacent blocks 1102), motion information from template sub-blocks 1104, represented by unfilled blocks in FIG. 11, may further be included as input to the linear regression process.

[0121] The linear regression process for deriving both non-refined and refined candidates is the same as that following the mathematical derivation described above. The only difference is the information on which sub-blocks should be used as input to the linear regression process. For example, the video encoder 200 or the video decoder 300 may employ such a linear regression process to derive both non-refined and refined candidates.

[0122] Generally, when implementing an algorithm design in hardware, integer arithmetic is preferred over floating-point arithmetic. Within the scope of integer arithmetic design, only limited (or reduced) bit lengths may be available. Typically, for integer arithmetic, the maximum bit length used is 64. Considering the maximum allowable values ​​of coordinates x and y, motion vectors, and the number of input sub-blocks, when these variables exceed a certain bit length, intermediate results may exceed the maximum allowable bit length during the linear regression process. As mentioned above, the matrix B c,d For the construction of A and B, the following formula can be used:

[0123]

number

[0124] In the current ECM design, the maximum allowed bit length of a motion vector component is 18 bits. In the linear regression process, the input motion vector is left-shifted by 2 bits to maintain high accuracy during calculation. In addition, when a delta motion vector value can be used, the delta calculation further increases the bit length because the video encoder 200 or video decoder 300 may subtract a negative value from a positive value. Therefore, the input motion vector delta component can be up to 21 bits.

[0125] For delta x and y coordinates, the coordinates can approach two CTU widths or heights. The maximum allowable CTU width or height is 256, and two CTU widths or heights is 512, which requires 10 bits in binary representation. However, since delta x and y can only approach, but never reach, two CTU widths or heights, the maximum number of bits required to represent delta x and y is 9 bits.

[0126] In terms of the number of sub-blocks, refinement candidates require a larger number of sub-blocks than non-refinement candidates. In the extreme case, both the affine CU and the current CU are 256x256. If the width and height of the sub-blocks are equal to 4, then the total number of sub-blocks N = (256 / 4 * 256 / 4)+(256+128 * 2) / 4+(256+128) / 4=4320. This number requires 13 bits for its binary representation.

[0127] If l0=x, l1=y and l2=1, the matrix A can be derived as follows:

[0128]

number

[0129] For a 3x3 matrix, its determinant can be calculated by the following formula:

[0130]

number

[0131] For each element of matrix A, the maximum number of bits required to hold the calculation result is:

[0132]

number

[0133]

number

[0134] Cascade Multiplication M 0,0 ×M 1,1 ×M 2,2 M is the sum of the number of bits required to represent each of the matrix elements. 1,1 and M 2,2 are 31 and 13 bits, respectively. Therefore, the bit length required to hold this result is 31+31+13=75 bits, which exceeds the commonly used integer bit length threshold of 64 bits.

[0135] matrix B c,d For matrix B, the situation can be exacerbated because the dynamic range of the delta motion vector components is much larger than that of the delta coordinates. As mentioned before, the number of bits required for the delta motion vector components is 21, while the number of bits required for the delta coordinates is 9. In one example, the matrix B x,0 Given the expression:

[0136]

number

[0137]

number

[0138]

number

[0139]

number

[0140] The same bit length requirements apply to other matrices. c,d , c∈{x,y} denotes the horizontal and vertical delta motion vector components, and d∈{0,1,2} denotes which columns in matrix A correspond to which columns in matrix B c,d It indicates whether the matrix B should be replaced when deriving c,d It is easy to see that the maximum number of bits required to hold the determinant result of may exceed 64 bits.

[0141] After the determinant values ​​are derived, according to Cramer's rule, the linear regression parameters can be calculated by the following formula:

[0142]

number

[0143] where det(B c,d ) and det(A) are the matrix B c,d and represents the determinant of A. For a given motion vector component, e.g., the horizontal component, one of the three linear regression parameters is the matrix B x,d can be derived without calculating the corresponding determinant of x0 and b x1 A linear model mv is assumed x =xb x0 +yb x1 +b x2If it has already been calculated according to:

[0144]

number

[0145]

number

[0146]

number

[0147]

number

[0148] From the above equations, the video encoder 200 or the video decoder 300 can calculate the following three determinants, which are det(A), det(B), x,0 ) and det(B x,1 )

[0149]

number

[0150]

number

[0151] Furthermore, division operations are generally undesirable in hardware implementations and are usually approximated by multiplications and right bit shifts. Typically, a lookup table for multiplications and a fixed number of right bit shifts is used. In order to reuse the same logic to calculate all linear regression parameters, the same denominator should be used for all parameters. Therefore, the parameter b x0 and b x1 The derivation of is modified as follows:

[0152]

number

[0153] Therefore, each determinant must be multiplied by the number of input sub-blocks, which again increases the bit length. Also, as mentioned above, division is approximated by a multiplication and a right bit shift. A multiplication followed by a right bit shift also results in a higher bit length requirement to hold the intermediate results.

[0154] Based on the above observations, bit-length control may be beneficial in the linear regression process to ensure a feasible hardware implementation. Therefore, this disclosure describes a bit-length control solution for linear regression-based affine merge candidate derivation. The bit-length control is applied to input variables and intermediate results to satisfy a commonly defined bit-length threshold in the hardware implementation. For example, the video encoder 200 or video decoder 300 may control the bit-length of input variables for linear regression. The video encoder 200 or video decoder 300 may perform linear regression on the controlled bit-length input variables. The video encoder 200 or video decoder 300 may derive an affine motion model based on performing the linear regression operation. The video encoder 200 or video decoder 300 may code the current block of video data based on the affine motion model. In some examples, the video encoder 200 or video decoder 300 may determine affine motion information based on the affine motion model. In some examples, the affine motion information includes affine motion candidates. For example, the output of the linear regression may be an affine motion model from which affine motion candidates may be derived or determined. In some examples, the output of the linear regression may include affine motion candidates.

[0155] Next, the bit length control for the input delta coordinates will be described. As described above, the currently used anchor coordinates are the anchor coordinates of the upper left position of the current CU. Therefore, the delta coordinates can be used to approximate the distance between the sub-block and the current CU. Non-adjacent affine CUs or template sub-blocks may not be too far from the current CU because the farther the sub-block is located, the lower the correlation may be. Therefore, the video encoder 200 or the video decoder 300 may set the upper limit thresholds of delta x and y so that the sub-block is relatively close. On the other hand, due to this constraint, the bit lengths of delta x and y can also be reduced. In one example, the threshold of the delta coordinates is set to N bits (excluding the sign bit), and only sub-blocks having both delta x values and delta y values within the range of [-(1<<N), (1<<N)-1] are used as inputs to the linear regression process. If the sub-block has delta coordinates outside the range, this sub-block is skipped. In one example, N = 8. In this way, the video encoder 200 or the video decoder 300 can ensure that each sub-block used in the linear regression process is within one CTU distance from the anchor position.

[0156] Next, bit length control for the input delta motion vector will be described. For example, when searching for a motion vector by motion estimation, a search range is defined. Only the reference picture area within the search range is examined. Therefore, generally, a motion vector having a value that is too large should not occur. However, some other techniques may use the motion vector along with scaling. For example, in the case of TMVP, the motion vector is scaled based on the POC distance. After being selected as TMVP multiple times, a cascade of scalings may occur that causes the TMVP to finally become a very large value. Overall, such motion vectors are generally rare and have low accuracy. Based on this, video encoder 200 or video decoder 300 may also adopt a threshold to adjust the delta motion vector component value. Defining the bit length threshold of the delta motion vector component as N bits (excluding the sign bit), in one example, if the motion vector component value is outside the range of [-(1 << N), (1 << N) - 1], this sub-block is not used. In a second example, instead of skipping the sub-block, the motion vector is clipped to the range of [-(1 << N), (1 << N) - 1] and can still be used. In a third example, the motion vector may be wrapped by modulo operation. For example, defining the horizontal delta motion vector component as deltaMVx, if deltaMVx is greater than (1 << N) - 1 or less than -(1 << N), deltaMVx % (1 << N) is used instead. In one application example, video encoder 200 or video decoder 300 can set N = 12, whereby the motion vector dynamic range becomes [-(1 << 12), (1 << 12) - 1]. In ECM, the current motion vector accuracy is 1 / 16 pixel. Therefore, the motion vector dynamic range regarding the number of samples is [-(1 << 8), (1 << 8) - 1], which is one CTU.

[0157] Next, the bit length control for the number of input sub-blocks will be described. Regarding the number of input sub-blocks, for those sub-blocks from non-adjacent affine CUs, since they already belong to the same linear model, the video encoder 200 or the video decoder 300 may only require three sub-blocks to derive the linear model. For the template sub-blocks of the current CU, they are usually similar to each other within a given area, and thus, the video encoder 200 or the video decoder 300 may not need all of them. Based on the analysis, when setting the bit length for the number of sub-blocks to N bits, a total number M = (1 << N) - 1 of sub-blocks can be used. In one example,

[0158] [Number] sub-blocks from the template area are used, and

[0159] [Number] sub-blocks from non-adjacent affine CUs are used. Different distributions of the number of sub-blocks used from non-adjacent affine CUs and the template area can be adopted to emphasize the importance of either the non-adjacent affine CUs or the template area. In a second example, more sub-blocks from non-adjacent affine CUs than from the template are used. For example,

[0160] [Number] only [Number] sub-blocks from the template area can be used, while

[0161] [Number] sub-blocks may be used. In a third example, the number of sub-blocks used from the template area is first determined. If we define the maximum number of sub-blocks allowed for the template area as T and the number of available sub-blocks from the template area as T', then S=min(T,T') sub-blocks from the template area can be used. Then, the number of sub-blocks that can be used from non-adjacent affine CUs is set to MS. In one example, video encoder 200 or video decoder 300 can set N=8, which means there can be up to 255 sub-blocks. Correspondingly, the number of sub-blocks from the template area is set to MS.

[0162]

number

[0163]

number

[0164] Next, the selection of input sub-blocks will be described. As described above, when the total number of available sub-blocks exceeds a predetermined upper limit, some of the sub-blocks may be excluded from the input. Different techniques can be used to perform the selection. In one example, the video encoder 200 or the video decoder 300 may collect sub-blocks having a given scanning order until the number of sub-blocks reaches a threshold. In a second example, the video encoder 200 or the video decoder 300 may use sub-sampling to select sub-blocks having a given sub-sample ratio. In a third example, a combination of the first two examples can be used. For example, template sub-blocks are sub-sampled, but sub-blocks of non-adjacent affine CUs are selected using the technique described in the first example.

[0165] Next, bit length control for linear regression output parameters will be described. This section describes the analysis of the range of the output linear regression parameters. According to the techniques of this disclosure, the bit length of the linear regression operation output parameters can be controlled. Assuming that the dynamic range of the input delta motion vector is M bits, knowing that the minimum delta coordinate between the center coordinate of the sub-block and the anchor coordinate (the anchor coordinate is defined as the top-left coordinate of the current CU) is 2 pixels, taking the affine parameter a as an example, based on its derivation formula:

[0166]

number

[0167] Next, adaptive bit-depth control for ECM affine RMVF (regression-based motion vector field) derivation will be described. Based on the ECM implementation of the affine RMVF derivation process above, this disclosure details those aspects that may lead to bit-depth overflow. Also, different techniques are introduced above to adjust input and output variables from linear regression. This section of this disclosure describes an example of how to address the aforementioned bit-depth issue by using the affine RMVF derivation flow used in ECM together with the examples described herein. For example, the video encoder 200 or the video decoder 300 may employ the bit-depth control techniques described herein.

[0168] As mentioned above, matrices A and B c,d The bit depth of each matrix element is as follows:

[0169]

number

[0170] Based on the following determinant

[0171]

number

[0172] The bit lengths of matrix A are the addition of a series of numbers having (31+31+13) bits, (31+22+22) bits, (22+31+22) bits, (31+22+22) bits, (31+31+13) bits, and (22+31+22) bits, which is equivalent to adding six numbers having 75 bits. Adding six numbers having the same bit length increases the bit length of the result by an additional three bits. Therefore, the maximum number of bits required for the determinant of matrix A is 78 bits.

[0173] Similarly, matrix B c,d In this case, the determinant is the addition of a series of numbers with (43+31+13) bits, (43+22+22) bits, (34+31+22) bits, (43+22+22) bits, (43+31+13) bits, and (34+31+13) bits. This ends up with a bit length requirement of 90 bits.

[0174] To ensure that the maximum number of bits does not exceed the 64-bit bit length limit, video encoder 200 or video decoder 300 may set an upper threshold for each of the input variables, including the delta x and y coordinates, the delta horizontal and vertical motion vector components, and the number of input sub-blocks, as described above. For example, video encoder 200 or video decoder 300 may set an upper threshold for each of the input variables, including the delta x and y coordinates, the delta horizontal and vertical motion vector components, and the number of input sub-blocks, to reduce or limit the number of bits.

[0175] In one example, the video encoder 200 or the video decoder 300 may reduce or limit the bit length of the delta x and y coordinates to 8 bits. If a sub-block is in a position such that the delta x component or the delta y component is greater than 8 bits, the video encoder 200 or the video decoder 300 may skip this sub-block as input to the linear regression. The bit length limit of the delta horizontal and vertical motion vector components may be set to 12 bits, and if a delta motion vector component exceeds the threshold, it is clipped to the allowed range. With respect to the number of sub-blocks, the bit length threshold may be set to 8 bits. If the number of sub-blocks is 8 bits, there may be a maximum of 255 sub-blocks. The number of sub-blocks used from the template area may first be determined. In some examples, the number of sub-blocks used from the template area may be limited to be less than 127. Based on the pattern of the template region, the total number of sub-blocks from the template area may be calculated using the formula (2 * W+1.5 *The number of sub-blocks from the template area can be calculated by (H) / 4. When the current CU size is 128x128, the number of sub-blocks from the template area is 112, which is still less than 127. However, currently, in ECM, the maximum allowed CU size is 256. Therefore, if the CU width or height is 256, the video encoder 200 or video decoder 300 may perform corresponding sub-sampling in the horizontal template row scan or vertical template column scan at a sub-sampling ratio of 1 / 2. In this way, the video encoder 200 or video decoder 300 can ensure that the number of sub-blocks used from the template area does not exceed a limit (e.g., 127). When the number of available sub-blocks from the template area is less than a predetermined limit, all sub-blocks may be used. If the number of actual sub-blocks found in the template area is defined as T, the maximum number of sub-blocks allowed from a non-adjacent affine CU is 255-T. If the number of available non-adjacent affine sub-blocks is greater than a threshold, the first available 255-T sub-blocks in raster scan order may be used. Once these thresholds are defined, matrices A and B c,d The maximum number of bits required for the determinant value of is 59 bits and 63 bits, which satisfies the bit depth limit.

[0176] The linear regression parameters are b x2 It is calculated by dividing the determinants of the two matrices except for b. x2 is calculated using the following formula:

[0177]

number

[0178] However, in this method, the value of the determinant is further multiplied by coefficients that differ in both the numerator and denominator, and therefore the bit length may exceed 64 bits.

[0179] As an example, in order to prevent the bit length from exceeding 64 bits, the video encoder 200 or the video decoder 300 may use the derived b x0 and b x1 We can use Cramer's rule, which has already been used to derive:

[0180]

number

[0181] matrix B x,2 , the bit depth of each element is:

[0182]

number

[0183] From the determinant calculation formula, determinant B x,2 The maximum bit depth of is 71 bits. x2 Even if we replace the derivation formula with Cramer's rule, the determinant can still exceed the bit depth limit. One solution is to scale both the numerator and denominator according to the number of input sub-blocks. Define the number of input sub-blocks as iNum, the bit length of the variable x as MSB(x), and the scaling shift for both the numerator and denominator is scaleshift,

[0184]

number

[0185] next

[0186]

number

[0187] For the denominator, if MSB(det(A)) is not greater than scaleshift, after the right shift it becomes 0. To avoid division by 0, if MSB(det(A))≦scaleshift, video encoder 200 or video decoder 300 may set the denominator to 1.

[0188] As mentioned before, the final division is approximated by a multiplication and a right bit shift. The multiplier is taken from a predetermined lookup table, and the index used to reference the lookup table is determined by the denominator, or equivalently, the determinant of matrix A. In the current design, the lookup table size is defined to be 64. Subsequently, the 6 most significant bits of det(A) are derived and used as the reference index. Define the bit length of variable x as MSB(x). The index used for the lookup table is calculated by:

[0189]

number

[0190] When derived with an index, the multiplier is defined by referencing a lookup table and can be denoted by lookup[index]. A fixed 15-bit right shift is required, corresponding to the bit length of the currently used lookup table. The division result is calculated using the following formula: b c,d =(det(B c,d ) * lookup[index])≫(15+shiftA) In the formula, shiftA=(MSB(det(A))-6)<0?0:(MSB(det(A))-6),shiftA needs to be added because the denominator performs a right bit shift by shiftA bits, and correspondingly, the numerator should perform the same shift.

[0191] Typically, during the affine parameter derivation process, the affine parameters are kept highly accurate by performing a left bit shift of MaxCuDepth, where 2^MaxCuDepth is the maximum allowed CTU size. In linear regression, the same method of keeping the affine parameters highly accurate can be used. If this bit shift is also performed, the video encoder 200 or the video decoder 300 may take this into account in bit length control. Therefore, b c,d The formula to derive is as follows: b c,d =(det(B c,d ) * lookup[index])≫(15+shiftA))< <MaxCuDepth

[0192] Currently, in ECM, MaxCuDepth is defined as 8. Since MaxCuDepth<15, we get b c,d =(det(B c,d ) * lookup[index])≫(15+shiftA-MaxCuDepth)

[0193] The maximum bit length of lookup[index] is 15 bits, and the intermediate result (det(B c,d ) * To keep lookup[index] within the 64-bit range, det(B c,d ) must be 48 bits or less. Therefore, you may add additional bit shifts on either side of the operator ">>" in the expression. The additional right bit shift, defined as rightshiftNum, is

[0194]

number

[0195] b c,d The final formula for deriving is b c,d =((det(B c,d) >> rightshiftNum * lookup[index]) >> (15 + shiftA - MaxCuDepth - rightshiftNum)

[0196] To avoid negative bit shifts, 15 + shiftA - MaxCuDepth - rightshiftNum can be clipped. Define the final right shift variable as finalshift,

[0197]

Number

[0198] In a different way, the video encoder 200 or the video decoder 300 can skip the operation for calculating MSB(det(B c,d )) by always shifting det(B c,d ) 15 bits to the right. In this way, the video encoder 200 or the video decoder 300 can also ensure that the numerator stays within the 64 - bit range. Setting rightshiftNum = 15, b c,d = ((det(B c,d )) >> 15) * lookup[index]) >> (shiftA - MaxCuDepth)

[0199] Similarly, shiftA - MaxCuDepth may be clipped to a non - negative value.

[0200] Finally, the output linear regression parameters may be clipped within the range of [-(1 << M), (1 << M) - 1], where M is set to 20 in the current solution. A

[0201] 12 is a flowchart illustrating an example bit-length control technique for linear regression-based affine merge candidate derivation according to one or more aspects of the present disclosure. The video encoder 200 or the video decoder 300 may control the bit-length of input variables for the linear regression operation, where the input variables include at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing the number of sub-blocks (1200). For example, the video encoder 200 or the video decoder 300 may control (e.g., reduce or limit) the bit-length of the one or more delta coordinates, the one or more delta motion vectors, and / or the value representing the number of sub-blocks to generate one or more reduced-bit-length input variables. For example, if the bit-length of a potential input variable is long (e.g., greater than a threshold), the video encoder 200 or the video decoder 300 may clip the value of the input variable or skip using the input variable associated with some sub-blocks.

[0202] The video encoder 200 or the video decoder 300 may perform a linear regression operation on the controlled bit-length input variables (1202). For example, the video encoder 200 or the video decoder 300 may use the input variables whose bit-lengths are controlled as inputs to the linear regression operation.

[0203] The video encoder 200 or the video decoder 300 may derive an affine motion model based on performing a linear regression operation (1204). For example, the video encoder 200 or the video decoder 300 may generate affine motion candidates (e.g., affine motion vector predictor candidates) based on performing a linear regression operation.

[0204] Video encoder 200 or video decoder 300 may code the current block of video data based on an affine motion model (1206). For example, video encoder 200 may encode the video data based on an affine motion model, or video decoder 300 may decode the video data based on an affine motion model.

[0205] In some examples, the input variables include one or more delta coordinates. In some examples, as part of controlling the bit length of the input variables, the video encoder 200 or video decoder may determine that at least one of the bit lengths of the delta x value or the delta y value of the one or more delta coordinates is greater than a delta x delta y bit length threshold, where the delta x value includes a value indicating the distance in the x direction between a current sub-block of the current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating the distance in the y direction between the current sub-block and a y anchor coordinate of the current block. Based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold, the video encoder 200 or video decoder 300 may skip the current sub-block as an input to the linear regression operation. In some examples, the delta x delta y bit length threshold is 8 bits.

[0206] In some examples, the input variables include one or more delta motion vectors. In some examples, as part of controlling the bit length of the input variables, the video encoder 200 or the video decoder 300 may determine that the bit length of the delta motion vector components is greater than a delta motion vector bit length threshold and, based on the bit length of the delta motion vector components being greater than the delta motion vector bit length threshold, skip the current sub-block as input to the linear regression operation. In some examples, as part of controlling the bit length of the input variables, the video encoder 200 or the video decoder 300 may determine that the bit length of the delta motion vector components is greater than a delta motion vector bit length threshold and, based on the bit length of the delta motion vector components being greater than the delta motion vector bit length threshold, clip the delta motion vector components to a length of the delta motion vector bit length threshold. In some examples, the delta motion vector bit length threshold is 12 bits.

[0207] In some examples, as part of controlling the bit length of the input variables, video encoder 200 or video decoder 300 may determine whether the bit length of the delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold. Based on a determination that the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, video encoder 200 or video decoder 300 may use an alternative delta motion vector component instead of the delta motion vector component as an input to the linear regression operation, the alternative delta motion vector component having a smaller bit length than the delta motion vector component.

[0208] In some examples, as part of controlling the bit length of the input variables, the video encoder 200 or the video decoder 300 may reduce the bit length of the value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length. In some examples, the predetermined bit length is 8 bits.

[0209] In some examples, as part of controlling the bit length of the input variables, the video encoder 200 or the video decoder 300 may select a subset of sub-blocks of a current block of video data to use as inputs to one or more input variables for the linear regression operation, the subset of sub-blocks being less than the total number of sub-blocks in the current block. In some examples, the video encoder 200 or the video decoder 300 may determine a first number of sub-blocks in a template area and a second number of sub-blocks in non-adjacent affine blocks, where the non-adjacent affine blocks are blocks of video data that are not adjacent to the current block and are coded using the affine mode. In some examples, the first number includes M / 2 and the second number includes M / 2, where M represents the number of sub-blocks used in the linear regression operation. In some examples, the first number includes M / 4 and the second number includes M / M / 4, where M represents the number of sub-blocks used in the linear regression operation.

[0210] In some examples, the video encoder 200 or the video decoder 300 may determine T, the maximum number of allowed sub-blocks for the template area, and determine T', the number of available sub-blocks from the template area, where the first number S comprises S=min(T,T'), the second number M comprises M, and M represents the number of sub-blocks used in the linear regression operation.

[0211] In some examples, as part of selecting the subset of sub-blocks, the video encoder 200 or the video decoder 300 may select the sub-blocks in scan order. In some examples, as part of selecting the subset of sub-blocks, the video encoder 200 or the video decoder 300 may subsample using a predetermined sub-sample ratio. In some examples, as part of selecting the subset of sub-blocks, the video encoder 200 or the video decoder 300 may subsample the sub-blocks in the template area using a predetermined sub-sample ratio and select non-adjacent affine sub-blocks in scan order until the number of selected sub-blocks is equal to the second number.

[0212] In some examples, as part of selecting the subset of sub-blocks, the video encoder 200 or the video decoder 300 may determine whether at least one of the height or width of the current CU of the current block is equal to 256. In such examples, the video encoder 200 or the video decoder 300 may perform sub-sampling in at least one of the horizontal template row scan of the template area or the vertical template column scan of the template area using a sub-sampling ratio of 1 / 2 based on a determination that at least one of the height or width of the current CU is equal to 256. The video encoder 200 or the video decoder 300 may determine a total number T of sub-blocks of the template area and determine whether the total number of available non-adjacent affine sub-blocks is greater than 255−T. The video encoder 200 or the video decoder 300 may use the first 255−T available non-adjacent affine sub-blocks in raster scan order as inputs for the linear regression operation based on a determination that the total number of available non-adjacent affine sub-blocks is greater than 255−T.

[0213] In some examples, the video encoder 200 or the video decoder 300 may limit the bit length of one or more linear regression operation output parameters. In some examples, as part of limiting the bit length of one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip one or more linear regression operation output parameters. In some examples, as part of clipping one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip each of the one or more linear regression operation output parameters to the same number of bits. In some examples, as part of clipping one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip at least one parameter of the one or more linear regression operation output parameters to a different number of bits than other parameters of the one or more linear regression operation output parameters. In such an example, as part of clipping at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters, video encoder 200 or video decoder 300 may clip the first linear regression calculation output parameter to the range of [-(1<<(M+N)),(1<<(M+N))-1] and clip the second linear regression calculation output parameter and the third linear regression calculation output parameter to the range of [-(1<<(M-1)),(1<<(M-1))-1, where M=12 and N=8.

[0214] In some examples, the video encoder 200 or the video decoder 300 may determine affine motion candidates based on an affine motion model.

[0215] 13 is a block diagram illustrating an example video encoder 200 that may implement the techniques of this disclosure. Figure 13 is provided for purposes of explanation and should not be considered limiting of the techniques broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes video encoder 200 in accordance with VVC and HEVC techniques. However, the techniques of this disclosure may be implemented by video encoding devices configured for other video coding standards and video coding formats, such as AV1 and successors to the AV1 video coding format.

[0216] 13 , the video encoder 200 includes a video data memory 230, a mode select unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode select unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 may be implemented in one or more processors or processing circuits. For example, the units of the video encoder 200 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Moreover, video encoder 200 may include additional or alternative processors or processing circuitry that perform these and other functions.

[0217] Video data memory 230 may store video data to be encoded by components of video encoder 200. Video encoder 200 may receive video data stored in video data memory 230, for example, from video source 104 (FIG. 1). DPB 218 may function as a reference picture memory that stores reference video data for use in predicting subsequent video data by video encoder 200. Video data memory 230 and DPB 218 may be formed by any of a variety of memory devices, such as DRAM, including synchronous dynamic random access memory (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same memory device or separate memory devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as shown, or may be off-chip relative to those components.

[0218] In this disclosure, references to video data memory 230 should not be construed as limited to memory internal to video encoder 200 unless specifically stated so, or to memory external to video encoder 200 unless specifically stated so. Rather, references to video data memory 230 should be understood as a reference memory that stores video data that video encoder 200 receives for encoding (e.g., video data for a current block to be encoded). Memory 106 of FIG. 1 may also provide temporary storage of outputs from various units of video encoder 200.

[0219] The various units in FIG. 13 are shown to aid in understanding the operations performed by video encoder 200. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. A fixed-function circuit refers to a circuit that provides a specific function, and the operations that may be performed are predefined. A programmable circuit refers to a circuit that may be programmed to perform various tasks, and provides flexibility in the operations that may be performed. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. While a fixed-function circuit may execute software instructions (e.g., receive parameters or output parameters), the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be different circuit blocks (fixed function or programmable), and in some examples, one or more of the units may be an integrated circuit.

[0220] Video encoder 200 may include arithmetic logic units (ALUs), elementary function units (EFUs), digital circuits, analog circuits, and / or a programmable core formed from programmable circuits. In examples in which the operations of video encoder 200 are implemented using software executed by programmable circuits, memory 106 (FIG. 1) may store software instructions (e.g., object code) that video encoder 200 receives and executes, or a separate memory (not shown) within video encoder 200 may store such instructions.

[0221] The video data memory 230 is configured to store the received video data. The video encoder 200 may retrieve pictures of the video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be raw video data to be encoded.

[0222] The mode select unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode select unit 202 may include additional functional units that perform video prediction according to other prediction modes. By way of example, the mode select unit 202 may include a palette unit, an intra block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, etc.

[0223] The mode selection unit 202 generally coordinates multiple coding passes to test combinations of coding parameters and the resulting rate-distortion values ​​for such combinations. The coding parameters may include partitioning of CTUs into CUs, prediction modes for CUs, transform types for residual data of CUs, quantization parameters for residual data of CUs, etc. The mode selection unit 202 may ultimately select a combination of coding parameters that has a better rate-distortion value than the other tested combinations.

[0224] Video encoder 200 may partition a picture retrieved from video data memory 230 into a series of CTUs and encapsulate one or more CTUs within a slice. Mode select unit 202 may partition the CTUs of the picture according to a tree structure, such as the MTT structure, QTBT structure, superblock structure, or quadtree structure described above. As described above, video encoder 200 may form one or more CUs from partitioning the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks."

[0225] In general, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for a current block (e.g., the current CU, or in HEVC, the overlapping portion of the PU and TU). In the case of inter prediction of the current block, the motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks among one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 may calculate a value representing how similar a potential reference block is to the current block according to, for example, the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), etc. The motion estimation unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block under consideration. Motion estimation unit 222 may identify the reference block with the lowest value resulting from these calculations, indicating the reference block that most closely matches the current block.

[0226] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of a current block in the current picture. In some examples, in forming the motion vectors, the motion estimation unit 222 may perform the technique of FIG. 12. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, in the case of unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, while in the case of bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then generate a predictive block using the motion vectors. For example, the motion compensation unit 224 may use the motion vectors to retrieve data for the reference block. As another example, if the motion vectors have fractional sample precision, the motion compensation unit 224 may interpolate values ​​for the predictive block according to one or more interpolation filters. Additionally, in the case of bidirectional inter prediction, the motion compensation unit 224 may retrieve data for two reference blocks identified by respective motion vectors and combine the retrieved data, for example, through sample-by-sample averaging or weighted averaging.

[0227] When operating according to the AV1 video coding format, the motion estimation unit 222 and the motion compensation unit 224 may be configured to encode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using translational motion compensation, affine motion compensation, overlapped block motion compensation (OBMC), and / or synthetic inter-intra prediction.

[0228] As another example, in the case of intra prediction or intra-predictive coding, intra prediction unit 226 may generate a predictive block from samples neighboring a current block. For example, in the case of a directional mode, intra prediction unit 226 may generally mathematically combine values ​​of neighboring samples and populate these calculated values ​​in a defined direction across the current block to generate a predictive block. As another example, in the case of a DC mode, intra prediction unit 226 may calculate an average of neighboring samples for the current block and generate a predictive block to include this resulting average for each sample of the predictive block.

[0229] When operating according to the AV1 video coding format, intra prediction unit 226 may be configured to encode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, chroma-from-luma (CFL) prediction, intra block copy (IBC), and / or color palette mode. Mode select unit 202 may include additional functional units that perform video prediction according to other prediction modes.

[0230] The mode select unit 202 provides the prediction block to the residual generation unit 204. The residual generation unit 204 receives a raw, uncoded version of the current block from the video data memory 230 and the prediction block from the mode select unit 202. The residual generation unit 204 calculates sample-by-sample differences between the current block and the prediction block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, the residual generation unit 204 may also determine differences between sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0231] In examples in which mode select unit 202 partitions CUs into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. Video encoder 200 and video decoder 300 may support PUs having various sizes. As mentioned above, the size of a CU may refer to the size of the luma coding block of the CU, and the size of a PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, video encoder 200 may support a PU size of 2N×2N or N×N for intra prediction, and a symmetric PU size of 2N×2N, 2N×N, N×2N, N×N, or similar for inter prediction. Video encoder 200 and video decoder 300 may also support asymmetric partitioning of PU sizes of 2N×nU, 2N×nD, nL×2N, and nR×2N for inter prediction.

[0232] In examples where mode select unit 202 does not further partition CUs into PUs, each CU may be associated with a luma coding block and a corresponding chroma coding block. As described above, the size of a CU may refer to the size of the luma coding block of the CU. Video encoder 200 and video decoder 300 may support CU sizes of 2N×2N, 2N×N, or N×2N.

[0233] For other video coding techniques, such as intra block copy mode coding, affine mode coding, and linear model (LM) mode coding, as some examples, mode select unit 202 generates a predictive block for the current block being coded via a respective unit associated with the coding technique. In some examples, such as palette mode coding, mode select unit 202 may not generate a predictive block, but instead may generate syntax elements that indicate how to reconstruct the block based on a selected palette. In such modes, mode select unit 202 may provide these syntax elements to entropy coding unit 220 to be coded.

[0234] As described above, the residual generation unit 204 receives video data for a current block and a corresponding predictive block. The residual generation unit 204 then generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates sample-by-sample differences between the predictive block and the current block.

[0235] Transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, transform processing unit 206 may perform multiple transforms on the residual block, e.g., a linear transform and a quadratic transform such as a rotational transform. In some examples, transform processing unit 206 does not apply a transform to the residual block.

[0236] When operating according to AV1, transform processing unit 206 may apply one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), an inverse ADST (e.g., ADST in reverse order), and an identity transform (IDTX). When using an identity transform, the transform is skipped in one of the vertical or horizontal directions. In some examples, the transform process may be skipped.

[0237] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to generate a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode select unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may result in loss of information, and therefore, the quantized transform coefficients may be less accurate than the original transform coefficients generated by the transform processing unit 206.

[0238] Inverse quantization unit 210 and inverse transform processing unit 212 may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to reconstruct a residual block from the transform coefficient block. Reconstruction unit 214 may generate a reconstructed block that corresponds to the current block (possibly with some distortion) based on the reconstructed residual block and the predictive block generated by mode select unit 202. For example, reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the predictive block generated by mode select unit 202 to generate the reconstructed block.

[0239] Filter unit 216 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blockiness artifacts along the edges of a CU. The operations of filter unit 216 may be skipped in some examples.

[0240] When operating according to AV1, filter unit 216 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blockiness artifacts along the edges of a CU. In other examples, filter unit 216 may apply a constrained directional enhancement filter (CDEF), which may be applied after deblocking and may include application of a non-separable, nonlinear, low-pass directional filter based on estimated edge directions. Filter unit 216 may also include a loop restoration filter, which may be applied after the CDEF and may include a separable symmetric normalized Wiener filter or a dual autoinduction filter.

[0241] Video encoder 200 stores the reconstructed blocks in DPB 218. For example, in examples where the operations of filter unit 216 are not performed, reconstruction unit 214 may store the reconstructed blocks in DPB 218. In examples where the operations of filter unit 216 are performed, filter unit 216 may store the filtered reconstructed blocks in DPB 218. Motion estimation unit 222 and motion compensation unit 224 may retrieve reference pictures formed from the reconstructed (and possibly filtered) blocks from DPB 218 to inter-predict blocks of a later-encoded picture. Additionally, intra-prediction unit 226 may use the reconstructed blocks of the current picture in DPB 218 to intra-predict other blocks in the current picture.

[0242] Generally, entropy encoding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 may entropy encode predictive syntax elements (e.g., motion information for inter-prediction or intra-mode information for intra-prediction) from mode select unit 202. Entropy encoding unit 220 may perform one or more entropy encoding operations on syntax elements, which are other examples of video data, to generate entropy-encoded data. For example, entropy encoding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, an Exponential-Golomb coding operation, or another type of entropy coding operation on the data. In some examples, entropy encoding unit 220 may operate in a bypass mode in which syntax elements are not entropy coded.

[0243] Video encoder 200 may output a bitstream that includes entropy-encoded syntax elements needed to reconstruct blocks of a slice or picture. Specifically, entropy encoding unit 220 may output the bitstream.

[0244] The entropy coding unit 220 may be configured as a symbol-to-symbol adaptive multi-symbol arithmetic coder according to AV1. A syntax element in AV1 includes an alphabet of N elements, and a context (e.g., a probability model) includes a set of N probabilities. The entropy coding unit 220 may store the probabilities as n-bit (e.g., 15-bit) cumulative distribution functions (CDFs). The entropy coding unit 220 may perform recursive scaling to update the context, using an update factor based on the alphabet size.

[0245] The operations described above are described with respect to blocks. Such descriptions should be understood as operations on luma coding blocks and / or chroma coding blocks. As described above, in some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a CU. In some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a PU.

[0246] In some examples, operations performed with respect to luma coding blocks need not be repeated for chroma coding blocks. As one example, operations identifying motion vectors (MVs) and reference pictures for luma coding blocks need not be repeated to identify MVs and reference pictures for chroma blocks. Rather, the MVs of luma coding blocks may be scaled to determine the MVs of chroma blocks, and the reference pictures may be the same. As another example, the intra prediction process may be the same for luma coding blocks and chroma coding blocks.

[0247] Video encoder 200 represents an example of a device configured to encode video data, including a memory configured to store video data and one or more processing units implemented in circuitry and configured to control (e.g., reduce or limit) the bit length of input variables for a linear regression operation, perform a linear regression operation on the controlled bit length input variables, derive an affine motion model based on performing the linear regression operation, and encode a current block of video data based on the affine motion model.

[0248] 14 is a block diagram illustrating an example video decoder 300 that may implement the techniques of this disclosure. Figure 14 is provided for purposes of explanation and does not limit the techniques broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes a video decoder 300 in accordance with VVC and HEVC techniques. However, the techniques of this disclosure may be implemented by video coding devices configured for other video coding standards.

[0249] In the example of Figure 14, the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a DPB 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 may be implemented in one or more processors or processing circuits. For example, the units of the video decoder 300 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Moreover, the video decoder 300 may include additional or alternative processors or processing circuits that perform these and other functions.

[0250] Prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. Prediction processing unit 304 may include additional units that perform prediction according to other prediction modes. By way of example, prediction processing unit 304 may include a palette unit, an intra block copy unit (which may form part of motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, video decoder 300 may include more, fewer, or different functional components.

[0251] When operating in accordance with AV1, the motion compensation unit 316 may be configured to decode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using translational motion compensation, affine motion compensation, OBMC, and / or synthetic inter-intra prediction, as described above. The intra prediction unit 318 may be configured to decode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or color palette mode, as described above.

[0252] CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of video decoder 300. The video data stored in CPB memory 320 may be retrieved, for example, from computer-readable medium 110 (FIG. 1). CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from the encoded video bitstream. CPB memory 320 may also store video data other than syntax elements of coded pictures, such as temporary data representing output from various units of video decoder 300. DPB 314 generally stores decoded pictures that video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory 320 and DPB 314 may be formed by any of a variety of memory devices, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 may be provided by the same memory device or separate memory devices. In various examples, CPB memory 320 may be on-chip with other components of video decoder 300, or may be off-chip relative to those components.

[0253] Additionally or alternatively, in some examples, video decoder 300 may retrieve coded video data from memory 120 (FIG. 1). That is, memory 120 may store data such as those discussed above for CPB memory 320. Similarly, memory 120 may store instructions to be executed by video decoder 300 when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300.

[0254] The various units shown in FIG. 14 are presented to aid in understanding the operations performed by video decoder 300. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. As with FIG. 13, fixed-function circuits refer to circuits that provide a specific function and have predefined operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and offer flexibility in the operations that can be performed. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. While a fixed-function circuit may execute software instructions (e.g., receive parameters or output parameters), the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be different circuit blocks (fixed function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0255] Video decoder 300 may include a programmable core formed from ALUs, EFUs, digital circuits, analog circuits, and / or programmable circuits. In examples where the operations of video decoder 300 are performed by software executing on programmable circuits, on-chip or off-chip memory may store software instructions (e.g., object code) that video decoder 300 receives and executes.

[0256] The entropy decoding unit 302 may receive the encoded video data from the CPB and entropy decode the video data to recover the syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0257] Generally, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 300 may perform a reconstruction operation on each block individually (the block currently being reconstructed, i.e., decoded, may be referred to as the “current block”).

[0258] The entropy decoding unit 302 may entropy decode syntax elements that define the quantized transform coefficients of the quantized transform coefficient block as well as transform information, such as a quantization parameter (QP) and / or a transform mode indication(s). The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine the degree of quantization, and similarly the degree of inverse quantization, that the inverse quantization unit 306 should apply. The inverse quantization unit 306 may, for example, perform a bitwise left-shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0259] After the inverse quantization unit 306 forms the transform coefficient blocks, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient blocks to generate residual blocks associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse transform, or another inverse transform to the transform coefficient blocks.

[0260] Further, prediction processing unit 304 generates a predictive block according to the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 may generate a predictive block. In this case, the prediction information syntax element may indicate a reference picture in DPB 314 from which to retrieve a reference block, as well as a motion vector that identifies the location of the reference block in the reference picture relative to the location of the current block in the current picture. Motion compensation unit 316 may generally perform the inter-prediction process in a manner substantially similar to that described with respect to motion compensation unit 224 (FIG. 13). In some examples, when performing the inter-prediction process, motion compensation unit 316 may perform the technique of FIG. 12.

[0261] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, intra prediction unit 318 may generate a predictive block according to the intra-prediction mode indicated by the prediction information syntax element. Again, intra prediction unit 318 may generally perform the intra-prediction process in a manner substantially similar to that described with respect to intra prediction unit 226 (FIG. 13). Intra prediction unit 318 may retrieve data of neighboring samples for the current block from DPB 314.

[0262] The reconstruction unit 310 may reconstruct the current block using the predictive block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the predictive block to reconstruct the current block.

[0263] Filter unit 312 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 312 may perform a deblocking operation to reduce blockiness artifacts along the edges of the reconstructed blocks. The operations of filter unit 312 are not necessarily performed in all instances.

[0264] The video decoder 300 may store the reconstructed blocks in the DPB 314. For example, in examples where the operations of the filter unit 312 are not performed, the reconstruction unit 310 may store the reconstructed blocks in the DPB 314. In examples where the operations of the filter unit 312 are performed, the filter unit 312 may store the filtered reconstructed blocks in the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as samples of the current picture for intra prediction and previously decoded pictures for subsequent motion compensation. Furthermore, the video decoder 300 may output the decoded pictures (e.g., decoded video) from the DPB 314 for later display on a display device, such as the display device 118 of FIG. 1 .

[0265] In this manner, the video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data and one or more processing units implemented in circuitry that are configured to control (e.g., reduce or limit) the bit length of input variables of a linear regression operation, apply the linear regression operation to the controlled bit length input variables, derive an affine motion model based on performing the linear regression operation, and decode a current block of video data based on the affine motion model.

[0266] 15 is a flowchart illustrating an example method for encoding a current block in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video encoder 200 (FIGS. 1 and 13), it should be understood that other devices may be configured to implement methods similar to the method of FIG. 15.

[0267] In this example, video encoder 200 first predicts the current block (350). For example, video encoder 200 may form a predictive block for the current block. When forming the predictive block, video encoder 200 (e.g., motion estimation unit 222) may perform the technique of FIG. 12. Video encoder 200 may then calculate a residual block for the current block (352). To calculate the residual block, video encoder 200 may calculate the difference between the original uncoded block and the predictive block for the current block. Video encoder 200 may then transform the residual block and quantize the transform coefficients of the residual block (354). Next, video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or following the scan, video encoder 200 may entropy code the transform coefficients (358). For example, video encoder 200 may encode the transform coefficients using CAVLC or CABAC. Video encoder 200 may then output the entropy-coded data for the block (360).

[0268] 16 is a flowchart illustrating an example method for decoding a current block of video data in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (FIGS. 1 and 14), it should be understood that other devices may be configured to implement methods similar to the method of FIG. 16.

[0269] The video decoder 300 may receive entropy-coded data for the current block, such as entropy-coded prediction information and entropy-coded data for transform coefficients of a residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy-coded data to determine prediction information for the current block and reconstruct transform coefficients of the residual block (372). The video decoder 300 may predict the current block using, for example, an intra-prediction mode or an inter-prediction mode indicated by the prediction information for the current block to calculate a predictive block for the current block (374). When predicting the current block, the video decoder 300 (e.g., motion compensation unit 316) may perform the techniques of FIG. 12. The video decoder 300 may then inverse-scan the reconstructed transform coefficients to generate a block of quantized transform coefficients (376). The video decoder 300 may then dequantize the transform coefficients and apply an inverse transform to the transform coefficients to generate a residual block (378). Video decoder 300 may finally decode the current block by combining the predictive block and the residual block (380).

[0270] The following numbered clauses illustrate one or more aspects of the devices and techniques described in this disclosure.

[0271] Clause 1A. A method for coding video data, the method comprising: reducing a bit length of one or more input variables for linear regression; performing linear regression on the one or more input variables, wherein the one or more input variables have a reduced bit length; deriving an affine motion model based on performing the linear regression on the one or more input variables having the reduced bit length; and coding the video data based on the affine motion model.

[0272] Clause 2A. The method of clause 1A, further comprising determining affine motion information based on an affine motion model.

[0273] Clause 3A. The method of clause 2A, wherein the affine motion information includes affine motion candidates.

[0274] Clause 4A. The method of any of clauses 1A-3A, wherein the one or more input variables include at least one of a delta coordinate, a delta motion vector, a number of sub-blocks, or a selected sub-block.

[0275] Clause 5A. The method of any of Clauses 1A to 4A, wherein reducing the bit length of the one or more input variables includes determining that at least one of a bit length of a delta x value or a bit length of a delta y value is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in an x ​​direction between a current sub-block of a current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating a distance in a y direction between the current sub-block and a y anchor coordinate of the current block; and skipping the current sub-block as input to the one or more input variables for the linear regression based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold.

[0276] Clause 6A. The method of clause 5A, wherein the delta x delta y bit length threshold is 8 bits.

[0277] Clause 7A. A method according to any of clauses 1A to 4A, wherein reducing the bit length of one or more input variables includes determining that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold, and skipping the current sub-block as input to one or more input variables for linear regression based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0278] Clause 8A. The method of clause 7A, wherein the delta motion vector bit length threshold is 12 bits.

[0279] Clause 9A. A method according to any one of clauses 1A to 8A, wherein reducing the bit length of one or more input variables comprises reducing the number of sub-blocks used in the linear regression from at least one of the template area or non-adjacent affine blocks, wherein the non-adjacent affine blocks are blocks of video data that are not adjacent to the current block and are coded using an affine mode.

[0280] Clause 10A. A method according to any of clauses 1A to 9A, wherein reducing the bit length of one or more input variables includes selecting a subset of sub-blocks of a current block of video data for use as input to one or more input variables for the linear regression, wherein the subset of sub-blocks is less than the total number of sub-blocks in the current block.

[0281] Clause 11A. The method of any of clauses 1A to 10A, further comprising reducing the bit length of one or more intermediate values ​​of the linear interpolation.

[0282] Clause 12A. The method of clause 11A, wherein reducing the bit length of one or more intermediate values ​​of the linear interpolation includes right-shifting the denominator of the equation and right-shifting the numerator of the equation.

[0283] Clause 13A. The method of any of clauses 1A to 12A, further comprising limiting the bit length of one or more linear regression output parameters.

[0284] Clause 14A. The method of clause 13A, wherein limiting the bit length of one or more linear regression output parameters comprises clipping the one or more linear regression output parameters.

[0285] Clause 15A. The method of clause 14A, wherein clipping the one or more linear regression output parameters includes clipping each of the one or more linear regression output parameters to the same number of bits.

[0286] Clause 16A. The method of clause 14A, wherein clipping the one or more linear regression output parameters includes clipping at least one parameter of the one or more linear regression output parameters to a different number of bits than other parameters of the one or more linear regression output parameters.

[0287] Clause 17A. The method of any of clauses 1A to 16A, wherein the coding includes decoding.

[0288] Clause 18A. The method of any of clauses 1A to 17A, wherein coding comprises encoding.

[0289] Clause 19A. A device for coding video data, the device comprising one or more means for performing the method according to any of clauses 1A to 18A.

[0290] Clause 20A. A device according to clause 19A, wherein the one or more means comprise one or more processors implemented in circuitry.

[0291] Clause 21A. The device of clause 19A or 20A, further comprising a memory for storing video data.

[0292] Clause 22A. The device of any of clauses 19A to 21A, further comprising a display configured to display the decoded video data.

[0293] Clause 23A. The device of any of clauses 19A to 22A, wherein the device includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0294] Clause 24A. A device according to any one of clauses 19A to 23A, wherein the device comprises a video decoder.

[0295] Clause 25A. The device of any of clauses 19A to 24A, wherein the device comprises a video encoder.

[0296] Clause 26A. A computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to perform any of the methods of clauses 1A to 18A.

[0297] Clause 1B. A method for coding video data, comprising: controlling a bit length of an input variable for a linear regression operation, the input variable including at least one of: a) one or more delta coordinates; b) one or more delta motion vectors; or c) a value representing a number of sub-blocks; performing a linear regression operation on the controlled bit length input variable; deriving an affine motion model based on performing the linear regression operation; and coding a current block of video data based on the affine motion model.

[0298] Clause 2B. The method of Clause 1B, wherein controlling the bit lengths of the input variables includes determining that a bit length of at least one of a delta x value or a delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in an x ​​direction between a current sub-block of a current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating a distance in a y direction between the current sub-block and a y anchor coordinate of the current block; and skipping the current sub-block as an input to the linear regression operation based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold.

[0299] Clause 3B. The method of clause 2B, wherein the delta x delta y bit length threshold is 8 bits.

[0300] Clause 4B. A method according to any one of clauses 1B to 3B, wherein controlling the bit length of the input variables includes determining that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold, and skipping the current sub-block as input to the linear regression operation based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0301] Clause 5B. A method according to any one of clauses 1B to 3B, wherein controlling the bit length of the input variable includes determining that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold, and clipping the delta motion vector component to a length equal to the delta motion vector bit length threshold based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0302] Clause 6B. The method of clause 5B, wherein the delta motion vector bit length threshold is 12 bits.

[0303] Clause 7B. A method according to any one of clauses 1B to 3B, wherein controlling the bit length of the input variables includes determining whether the bit length of the delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold, and using an alternative delta motion vector component having a bit length less than the delta motion vector component as an input to the linear regression operation instead of the delta motion vector component based on a determination that the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold.

[0304] Clause 8B. The method of any of clauses 1B to 7B, wherein controlling the bit length of the input variable includes reducing the bit length of a value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length.

[0305] Clause 9B. The method of clause 8B, wherein the predetermined bit length is 8 bits.

[0306] Clause 10B. A method according to clause 8B or 9B, wherein controlling the bit length of the input variables includes selecting a subset of sub-blocks of a current block of video data for use in the linear regression operation, the subset of sub-blocks being less than the total number of sub-blocks in the current block, and the method further includes determining a first number of sub-blocks within the template area and determining a second number of sub-blocks within non-adjacent affine blocks, wherein the non-adjacent affine blocks are blocks of video data that are not adjacent to the current block and are coded using an affine mode.

[0307] Clause 11B. The method of clause 10B, wherein the first number comprises M / 2 and the second number comprises M / 2, where M represents the number of sub-blocks used in the linear regression calculation.

[0308] Clause 12B. The method of clause 10B, wherein the first number comprises M / 4 and the second number comprises MM / 4, where M represents the number of sub-blocks used in the linear regression calculation.

[0309] Clause 13B. The method of clause 10B, further comprising determining T, the maximum number of sub-blocks allowed for the template area, and determining T', the number of available sub-blocks from the template area, wherein the first number S is equal to min(T,T'), the second number is equal to MS, and M represents the number of sub-blocks used in the linear regression operation.

[0310] Clause 14B. The method of any of clauses 10B-13B, wherein selecting a subset of the sub-blocks includes selecting the sub-blocks in scan order.

[0311] Clause 15B. The method of any of clauses 10B-13B, wherein selecting a subset of sub-blocks includes sub-sampling using a predetermined sub-sampling ratio.

[0312] Clause 16B. The method of any of clauses 10B to 13B, wherein selecting a subset of subblocks includes subsampling the subblocks in the template area using a predetermined subsampling ratio, and selecting non-adjacent affine subblocks in scan order until the number of selected subblocks is equal to a second number.

[0313] Clause 17B. A method according to any one of clauses 10B to 13B, wherein selecting a subset of sub-blocks includes determining whether at least one of the heights or widths of a current CU of the current block is equal to 256; performing sub-sampling in at least one of a horizontal template row scan of the template area or a vertical template column scan of the template area using a sub-sampling ratio of 1 / 2 based on a determination that at least one of the heights or widths of the current CU is equal to 256; determining a total number T of sub-blocks in the template area; determining whether the total number of available non-adjacent affine sub-blocks is greater than 255-T; and based on a determination that the total number of available non-adjacent affine sub-blocks is greater than 255-T, using the first 255-T available non-adjacent affine sub-blocks in raster scan order as inputs for a linear regression operation.

[0314] Clause 18B. The method of any of clauses 1B to 17B, further comprising limiting the bit length of one or more linear regression calculation output parameters.

[0315] Clause 19B. The method of clause 18B, wherein limiting the bit length of one or more linear regression calculation output parameters includes clipping the one or more linear regression calculation output parameters.

[0316] Clause 20B. The method of clause 19B, wherein clipping the one or more linear regression calculation output parameters includes clipping each of the one or more linear regression calculation output parameters to the same number of bits.

[0317] Clause 21B. The method of clause 19B, wherein clipping the one or more linear regression calculation output parameters includes clipping at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters.

[0318] Clause 22B. The method of clause 21B, wherein clipping at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters includes clipping a first linear regression calculation output parameter to the range of [-(1<<(M+N)),(1<<(M+N))-1], and clipping a second linear regression calculation output parameter and a third linear regression calculation output parameter to the range of [-(1<<(M-1)),(1<<(M-1))-1], wherein M=12 and N=8.

[0319] Clause 23B. The method of any of clauses 1B-22B, further comprising determining affine motion candidates based on an affine motion model.

[0320] Clause 24B. A device for coding video data, comprising: a memory configured to store the video data; and one or more processors communicatively coupled to the memory, wherein the one or more processors are configured to control a bit length of input variables for a linear regression operation, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform a linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and code a current block of the video data based on the affine motion model.

[0321] Clause 25B. The device of clause 24B, wherein as part of controlling the bit lengths of the input variables, the one or more processors are configured to: determine that a bit length of at least one of a delta x value or a delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in an x ​​direction between a current sub-block of a current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating a distance in a y direction between the current sub-block and a y anchor coordinate of the current block; and skip the current sub-block as an input to the linear regression operation based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold.

[0322] Clause 26B. The device of clause 25B, wherein the delta x delta y bit length threshold is 8 bits.

[0323] Clause 27B. A device described in any of clauses 24B to 26B, wherein as part of controlling the bit length of the input variables, the one or more processors are configured to determine that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold, and to skip the current sub-block as input to the linear regression operation based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0324] Clause 28B. A device described in any of clauses 24B to 26B, wherein as part of controlling the bit length of the input variable, the one or more processors are configured to determine that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold, and clip the delta motion vector component to a length of the delta motion vector bit length threshold based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0325] Clause 29B. The device of clause 28B, wherein the delta motion vector bit length threshold is 12 bits.

[0326] Clause 30B. The device of any of Clauses 24B to 26B, wherein as part of controlling the bit length of the input variables, the one or more processors are configured to determine whether the bit length of the delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold, and based on a determination that the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, use an alternative delta motion vector component having a bit length less than the delta motion vector component as an input to the linear regression operation instead of the delta motion vector component.

[0327] Clause 31B. A device described in any of clauses 24B to 30B, wherein as part of controlling the bit length of the input variables, the one or more processors are configured to reduce the bit length of a value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length.

[0328] Clause 32B. The device of clause 31B, wherein the predetermined bit length is 8 bits.

[0329] Clause 33B. The device of clause 31B or 32B, wherein as part of controlling the bit length of the input variables, the one or more processors are configured to select a subset of sub-blocks of a current block of video data for use as input to one or more input variables for the linear regression operation, the subset of sub-blocks being less than the total number of sub-blocks in the current block, and the one or more processors are further configured to determine a first number of sub-blocks within a template area and a second number of sub-blocks within non-adjacent affine blocks, the non-adjacent affine blocks being blocks of video data that are not adjacent to the current block and are coded using an affine mode.

[0330] Clause 34B. The device of clause 33B, wherein the first number comprises M / 2 and the second number comprises M / 2, where M represents the number of sub-blocks used in the linear regression operation.

[0331] Clause 35B. The device of clause 33B, wherein the first number comprises M / 4 and the second number comprises MM / 4, where M represents the number of sub-blocks used in the linear regression calculation.

[0332] Clause 36B. The device of clause 33B, wherein the one or more processors are further configured to determine T, a maximum number of allowable sub-blocks for the template area, and determine T', a number of available sub-blocks from the template area, wherein the first number S is equal to min(T,T'), the second number is equal to MS, and M represents the number of sub-blocks used in the linear regression operation.

[0333] Clause 37B. The device of any of clauses 33B-36B, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to select the sub-blocks in scan order.

[0334] Clause 38B. The device of any of clauses 33B to 36B, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to sub-sample using a predetermined sub-sampling ratio.

[0335] Clause 39B. A device described in any of clauses 33B to 36B, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to sub-sample the sub-blocks in the template area using a predetermined sub-sampling ratio and select non-adjacent affine sub-blocks in scan order until the number of selected sub-blocks is equal to a second number.

[0336] Clause 40B. The device of any of Clauses 33B to 36B, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to determine whether at least one of the height or width of a current CU of the current block is equal to 256, and based on a determination that at least one of the height or width of the current CU is equal to 256, perform sub-sampling in at least one of a horizontal template row scan of the template area or a vertical template column scan of the template area using a sub-sampling ratio of 1 / 2, determine a total number T of sub-blocks of the template area, determine whether the total number of available non-adjacent affine sub-blocks is greater than 255-T, and based on a determination that the total number of available non-adjacent affine sub-blocks is greater than 255-T, use the first 255-T available non-adjacent affine sub-blocks in raster scan order as inputs for a linear regression operation.

[0337] Clause 41B. The device of any of clauses 24B to 40B, wherein the one or more processors are further configured to limit the bit length of one or more linear regression calculation output parameters.

[0338] Clause 42B. The device of clause 41B, wherein as part of limiting the bit length of the one or more linear regression calculation output parameters, the one or more processors are configured to clip the one or more linear regression calculation output parameters.

[0339] Clause 43B. The device of clause 42B, wherein as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip each of the one or more linear regression operation output parameters to the same number of bits.

[0340] Clause 44B. The device of clause 42B, wherein as part of clipping the one or more linear regression calculation output parameters, the one or more processors are configured to clip at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters.

[0341] Clause 45B. The device of clause 44B, wherein as part of clipping at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters, the one or more processors are configured to clip the first linear regression calculation output parameter to the range of [-(1<<(M+N)),(1<<(M+N))-1] and clip the second linear regression calculation output parameter and the third linear regression calculation output parameter to the range of [-(1<<(M-1)),(1<<(M-1))-1], where M=12 and N=8.

[0342] Clause 46B. The device of any of clauses 24B-45B, wherein the one or more processors are further configured to determine affine motion candidates based on an affine motion model.

[0343] Clause 47B. The device of any of clauses 24B to 46B, further comprising a display configured to display the decoded video data.

[0344] Clause 48B. The device of any of clauses 24B to 47B, wherein the device includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0345] Clause 49B. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to control the bit length of input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform the linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and code a current block of video data based on the affine motion model.

[0346] Clause 50B. A device for coding video data, comprising: means for controlling a bit length of input variables for a linear regression operation to generate one or more reduced bit length input variables, the one or more input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; means for performing the linear regression operation on the controlled bit length input variables; means for deriving an affine motion model based on performing the linear regression operation; and means for coding a current block of video data based on the affine motion model.

[0347] It should be recognized that, in some examples, some acts or events of any of the techniques described herein may be performed in a different order, added, merged, or omitted entirely (e.g., not all acts or events described may be required to practice the techniques). Moreover, in some examples, acts or events may be performed in parallel rather than sequentially, for example, through multithreading, interrupt processing, or multiple processors.

[0348] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which correspond to tangible media such as data storage media, or communication media, including any medium that facilitates transfer of a computer program from one place to another, for example, according to a communication protocol. As such, computer-readable media may generally correspond to (1) tangible computer-readable storage media that is non-transitory, or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures to implement the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0349] By way of example, and not limitation, such computer-readable storage media may comprise one or more of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but instead cover non-transitory tangible storage media. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0350] The instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the terms "processor" and "processing circuitry," as used herein, may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or may be incorporated into a combined codec. The techniques may also be implemented entirely in one or more circuits or logic elements.

[0351] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units have been described in this disclosure to highlight functional aspects of devices configured to implement the disclosed techniques, but they do not necessarily require realization by different hardware units. Rather, as described above, the various units may be combined in a codec hardware unit or may be provided by a collection of interoperable hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware.

[0352] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. 1. A method for coding video data, comprising: Controlling the bit length of input variables for a linear regression operation, the input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; performing said linear regression operation on a controlled bit length input variable; deriving an affine motion model based on performing the linear regression operation; coding the current block of video data based on the affine motion model.

2. controlling the bit length of the input variable determining that a bit length of at least one of a delta x value or a delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in an x ​​direction between a current sub-block of the current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating a distance in a y direction between the current sub-block and a y anchor coordinate of the current block; and skipping the current sub-block as an input to the linear regression operation based on the bit length of at least one of the value of delta x or the value of delta y being greater than the delta x delta y bit length threshold.

3. The method of claim 2 , wherein the delta x delta y bit length threshold is 8 bits.

4. controlling the bit length of the input variable determining that a bit length of the delta motion vector component is greater than a delta motion vector bit length threshold; and skipping a current sub-block as input to the linear regression operation based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

5. controlling the bit length of the input variable determining that a bit length of the delta motion vector component is greater than a delta motion vector bit length threshold; and clipping the delta motion vector component to a length of the delta motion vector bit length threshold based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

6. The method of claim 5 , wherein the delta motion vector bit length threshold is 12 bits.

7. controlling the bit length of the input variable determining whether a bit length of the delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold; 2. The method of claim 1, further comprising: using an alternative delta motion vector component as an input to the linear regression operation instead of the delta motion vector component based on a determination of whether the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, wherein the alternative delta motion vector component has a smaller bit length than the delta motion vector component.

8. The method of claim 1 , wherein controlling the bit length of the input variables comprises reducing the bit length of a value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length.

9. 9. The method of claim 8, wherein the predetermined bit length is 8 bits.

10. and wherein controlling the bit lengths of the input variables includes selecting a subset of sub-blocks of a current block of the video data for use in the linear regression operation, the subset of sub-blocks being less than a total number of sub-blocks in the current block, and the method further comprises: determining a first number of sub-blocks in the template area; 9. The method of claim 8, further comprising: determining a second number of sub-blocks in a non-adjacent affine block, the non-adjacent affine block being a block of the video data that is not adjacent to the current block and that is coded using an affine mode.

11. The method of claim 10 , wherein the first number comprises M / 2 and the second number comprises M / 2, where M represents the number of sub-blocks used in the linear regression operation.

12. 11. The method of claim 10, wherein the first number comprises M / 4 and the second number comprises M-M / 4, where M represents the number of sub-blocks used in the linear regression operation.

13. determining T, the maximum number of sub-blocks allowed for the template area; determining a number T′ of available sub-blocks from the template area; 11. The method of claim 10, wherein the first number S is equal to min(T,T') and the second number is equal to M-S, where M represents the number of sub-blocks used in the linear regression operation.

14. The method of claim 10 , wherein selecting the subset of sub-blocks comprises selecting sub-blocks in scan order.

15. The method of claim 10 , wherein selecting the subset of sub-blocks comprises sub-sampling using a predetermined sub-sampling ratio.

16. said selecting said subset of sub-blocks; subsampling sub-blocks within the template area using a predetermined subsampling ratio; and selecting non-adjacent affine sub-blocks in scan order until the number of selected sub-blocks is equal to the second number.

17. said selecting said subset of sub-blocks; Determining whether at least one of a height or a width of a current CU of the current block is equal to 256; performing subsampling in at least one of a horizontal template row scan of the template area or a vertical template column scan of the template area at a subsampling ratio of ½ based on a determination that at least one of the height or the width of the current CU is equal to 256; determining a total number T of sub-blocks in the template area; determining whether the total number of available non-adjacent affine sub-blocks is greater than 255-T; and using the first 255−T available non-adjacent affine sub-blocks in raster scan order as inputs for the linear regression operation based on a determination that the total number of available non-adjacent affine sub-blocks is greater than 255−T.

18. The method of claim 1 , further comprising limiting the bit length of one or more linear regression calculation output parameters.

19. 20. The method of claim 18, wherein limiting the bit length of one or more linear regression calculation output parameters comprises clipping the one or more linear regression calculation output parameters.

20. 20. The method of claim 19, wherein clipping the one or more linear regression operation output parameters comprises clipping each of the one or more linear regression operation output parameters to the same number of bits.

21. 20. The method of claim 19, wherein clipping the one or more linear regression calculation output parameters comprises clipping at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters.

22. clipping the at least one parameter of the one or more linear regression calculation output parameters to a different number of bits than other parameters of the one or more linear regression calculation output parameters; clipping the first linear regression calculation output parameters to the range of [-(1<<(M+N)), (1<<(M+N))-1]; clipping the second linear regression calculation output parameter and the third linear regression calculation output parameter to the range of [-(1<<(M-1)), (1<<(M-1))-1; 22. The method of claim 21, wherein M=12 and N=8.

23. The method of claim 1 , further comprising determining affine motion candidates based on the affine motion model.

24. 1. A device for coding video data, comprising: a memory configured to store the video data; one or more processors communicatively coupled to the memory, Controlling the bit length of input variables for the linear regression operation, the input variables including at least one of: a) one or more delta coordinates; b) one or more delta motion vectors; or c) a value representing a number of sub-blocks; performing said linear regression operation on a controlled bit length input variable; deriving an affine motion model based on performing the linear regression operation; one or more processors configured to code the current block of video data based on the affine motion model.

25. As part of controlling the bit lengths of the input variables, the one or more processors: determining that a bit length of at least one of a delta x value or a delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in an x ​​direction between a current sub-block of the current block and an x ​​anchor coordinate of the current block, and the delta y value includes a value indicating a distance in a y direction between the current sub-block and a y anchor coordinate of the current block; 25. The device of claim 24, configured to skip the current sub-block as input to the linear regression operation based on the bit length of at least one of the value of delta x or the value of delta y being greater than the delta x delta y bit length threshold.

26. 26. The device of claim 25, wherein the delta x delta y bit length threshold is 8 bits.

27. As part of controlling the bit lengths of the input variables, the one or more processors: determining that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold; 25. The device of claim 24, configured to skip a current sub-block as input to the linear regression operation based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

28. As part of controlling the bit lengths of the input variables, the one or more processors: determining that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold; 25. The device of claim 24, configured to clip the delta motion vector component to a length equal to the delta motion vector bit length threshold based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

29. 30. The device of claim 28, wherein the delta motion vector bit length threshold is 12 bits.

30. As part of controlling the bit lengths of the input variables, the one or more processors: determining whether a bit length of the delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold; 25. The device of claim 24, configured to use an alternative delta motion vector component as an input to the linear regression operation instead of the delta motion vector component based on a determination of whether the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, the alternative delta motion vector component having a smaller bit length than the delta motion vector component.

31. 25. The device of claim 24, wherein as part of controlling the bit length of the input variables, the one or more processors are configured to reduce the bit length of a value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length.

32. 32. The device of claim 31, wherein the predetermined bit length is 8 bits.

33. As part of controlling the bit lengths of the input variables, the one or more processors are configured to select a subset of sub-blocks of a current block of the video data to use as inputs to the one or more input variables for the linear regression operation, the subset of sub-blocks being less than a total number of sub-blocks in the current block, and the one or more processors are configured to: determining a first number of sub-blocks in the template area; 32. The device of claim 31 , further configured to determine a second number of sub-blocks in a non-adjacent affine block, the non-adjacent affine block being a block of the video data that is not adjacent to the current block and that is coded using an affine mode.

34. 34. The device of claim 33, wherein the first number comprises M / 2 and the second number comprises M / 2, where M represents a number of sub-blocks used in the linear regression operation.

35. 34. The device of claim 33, wherein the first number comprises M / 4 and the second number comprises M-M / 4, where M represents a number of sub-blocks used in the linear regression operation.

36. the one or more processors: determining T, the maximum number of sub-blocks allowed for the template area; and further configured to determine a number T′ of available sub-blocks from the template area; 34. The device of claim 33, wherein the first number S is equal to min(T, T') and the second number is equal to M-S, where M represents the number of sub-blocks used in the linear regression operation.

37. 34. The device of claim 33, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to select sub-blocks in scan order.

38. 34. The device of claim 33, wherein as part of selecting the subset of sub-blocks, the one or more processors are configured to sub-sample using a predetermined sub-sampling ratio.

39. As part of selecting the subset of sub-blocks, the one or more processors: subsampling sub-blocks within the template area using a predetermined subsampling ratio; 34. The device of claim 33, configured to select non-adjacent affine sub-blocks in scan order until the number of selected sub-blocks is equal to the second number.

40. As part of selecting the subset of sub-blocks, the one or more processors: Determining whether at least one of the height or width of the current CU of the current block is equal to 256; based on a determination that at least one of the height or the width of the current CU is equal to 256, performing subsampling in at least one of a horizontal template row scan of the template area or a vertical template column scan of the template area at a subsampling ratio of 1 / 2; determining a total number T of sub-blocks in the template area; determining whether the total number of available non-adjacent affine sub-blocks is greater than 255-T; 34. The device of claim 33, configured to use the first 255−T available non-adjacent affine sub-blocks in raster scan order as inputs for the linear regression operation based on a determination that the total number of available non-adjacent affine sub-blocks is greater than 255−T.

41. 25. The device of claim 24, wherein the one or more processors are further configured to limit a bit length of one or more linear regression operation output parameters.

42. 42. The device of claim 41 , wherein as part of limiting a bit length of one or more linear regression operation output parameters, the one or more processors are configured to clip the one or more linear regression operation output parameters.

43. 43. The device of claim 42, wherein as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip each of the one or more linear regression operation output parameters to the same number of bits.

44. 43. The device of claim 42, wherein as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip at least one parameter of the one or more linear regression operation output parameters to a different number of bits than other parameters of the one or more linear regression operation output parameters.

45. As part of clipping the at least one parameter of the one or more linear regression operation output parameters to a different number of bits than other parameters of the one or more linear regression operation output parameters, the one or more processors: clipping the first linear regression calculation output parameters to the range of [-(1<<(M+N)), (1<<(M+N))-1]; clipping the second linear regression calculation output parameter and the third linear regression calculation output parameter to a range of [-(1<<(M-1)), (1<<(M-1))-1; 45. The device of claim 44, wherein M=12 and N=8.

46. The device of claim 24 , wherein the one or more processors are further configured to determine affine motion candidates based on the affine motion model.

47. 25. The device of claim 24, further comprising a display configured to display the decoded video data.

48. 25. The device of claim 24, wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

49. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to: controlling bit lengths of input variables for a linear regression operation to generate one or more reduced bit length input variables, said input variables including at least one of: a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; performing said linear regression operation on a controlled bit length input variable; deriving an affine motion model based on performing the linear regression operation; A non-transitory computer-readable storage medium that causes a current block of video data to be coded based on the affine motion model.

50. 1. A device for coding video data, comprising: means for controlling a bit length of input variables for a linear regression operation to generate one or more reduced bit length input variables, said one or more input variables comprising at least one of: a) one or more delta coordinates; b) one or more delta motion vectors; or c) a value representing a number of sub-blocks; means for performing said linear regression operation on controlled bit length input variables; means for deriving an affine motion model based on performing the linear regression operation; means for coding the current block of video data based on the affine motion model.

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