Systems and methods for memory optimization for multi-user RLC

Abstract

The method includes transmitting, by a processing circuit, a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE; in response to the packet being received, allocating, by the processing circuit, a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being transmitted; and in response to successful completion of the AM, returning, by the processing circuit, the packet chunk to the shared memory pool.

Description

[Technical Field]

[0001] The present description relates to a system for memory optimization for multi-user RLC and methods of using the same. [Background technology]

[0002] A cellular network is a telecommunications system in which mobile devices (e.g., mobile phone devices) communicate by radio waves through one or more local antennas at cellular base stations (e.g., cell towers). Cellular service is provided to a coverage area that is divided into small geographic areas called cells. Each cell is served by a separate low-power multi-channel transceiver and antenna at the cellular base station. Mobile devices within a cell communicate through that cell's antenna on multiple and individual frequency channels assigned by the base station from a common pool of frequencies used by the cellular network.

[0003] The Radio Access Network (RAN) is the part of a telecommunications system that implements radio access technology. The RAN resides between devices such as mobile phones, computers, or remote control machines and provides connectivity to the Core Network (CN). Depending on the standard, mobile phones and other wirelessly connected devices are variously known as User Equipment (UE), Terminal Equipment (TE), Mobile Station (MS), etc. Summary of the Invention

[0004] In one embodiment, the method includes transmitting, by a processing circuit, a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE; in response to the packet being received, allocating, by the processing circuit, a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being transmitted; and in response to successful completion of the AM, returning, by the processing circuit, the packet chunk to the shared memory pool.

[0005] In an embodiment, the apparatus includes a processor and a memory storing instructions that, when executed by the processor, cause the processor to cause a processing circuit to send a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE, and, in response to the packet being received, cause the processing circuit to allocate a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being transmitted, and, in response to the AM completing successfully, cause the processing circuit to return the packet chunk to the shared memory pool.

[0006] In an embodiment, a non-transitory computer-readable medium having stored thereon instructions that, in response to being executed by the processor, cause the processor to cause a processing circuit to send a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE, in response to the packet being received, cause the processing circuit to allocate a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being sent, and in response to the AM completing successfully, cause the processing circuit to return the packet chunk to the shared memory pool.

[0007] Aspects of the embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with standard industry practice, various features are not drawn to scale. In some embodiments, the dimensions of various features have been arbitrarily increased or decreased for clarity of discussion. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a system for memory optimization (MOMR) for multi-user radio link control (RLC), according to an embodiment.

[0009] [Figure 2] FIG. 1 is a block schematic diagram of a memory pool for MOMR, according to an embodiment.

[0010] [Figure 3] FIG. 1 is a flow diagram of a method for MOMR, according to an embodiment.

[0011] [Figure 4] FIG. 1 is a high-level functional block diagram of a processor-based system according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following disclosure provides many different embodiments or examples for implementing the particular features of the described subject matter. To simplify the embodiments, example components, values, operations, materials, arrangements, and the like are described below. These are, of course, examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, and the like are contemplated. For example, forming a first feature over a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and further includes embodiments in which an additional feature is formed between the first and second features such that the first and second features cannot be in direct contact. Additionally, some embodiments may repeat reference numbers and / or letters in multiple instances. This repetition is for the purposes of brevity and clarity and does not dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms such as below, below, lower, above, upper, etc. are used herein for ease of description to describe the relationship of one element or feature to another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] In one embodiment, memory optimization for multi-user radio link control (RLC) is discussed.

[0015] Recently, the European Telecommunications Standards Institute (ETSI) released the 5G new radio (NR) RLC protocol specification (3GPP® TS38.322, Version 15.3.0, Release 15), which is incorporated herein by reference in its entirety. The ETSI release introduced an 18-bit RLC sequence number, which increases the RLC window length to 131,072 bits.

[0016] ETSI is an independent, not-for-profit information and communications standards organization. ETSI supports the development and testing of global technical standards for information and communications technology (ICT)-enabled systems, applications and services.

[0017] RLC is a Layer 2 radio link protocol used in Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), and 5G over the air interface. This protocol is described by 3GPP in Technical Standards (TS) 25.322 for UMTS, TS 36.322 for LTE, and TS 38.322 for 5G New Radio (NR). RLC resides above the 3GPP Medium Access Control (MAC) layer and below the Packet Data Convergence Protocol (PDCP) layer. The tasks of the RLC protocol are (1) transmission of upper layer protocol data units (PDUs) in one of three modes: acknowledged mode (AM), unacknowledged mode (UM), and transparent mode (TM); (2) error correction via ARQ (for AM data transmission); (3) concatenation, segmentation, and reassembly of RLC service data units (SDUs) (UM and AM); (4) resegmentation of RLC data PDUs (AM); (5) reordering of RLC data PDUs (UM and AM); (6) duplicate detection (UM and AM); (7) RLC SDU discard (UM and AM); (8) RLC re-establishment; and (9) protocol error detection and recovery.

[0018] With each UE being 131,072 bits and each gNodeB (GNB is a 3GPP-compliant implementation of a 5G-NR base station that includes independent network functions, implementing 3GPP-compliant NR RAN protocols) supporting hundreds and thousands of users, this requires a significant memory allocation (number of users * 131072), in response to an increase to 18-bit RLC sequence numbers. In a non-limiting example, for 10 UEs, the memory supports 1.31 Mbits, for 100 UEs, 13.10 Mbits, for 1,000 UEs, 131.07 Mbits, and for 10,000 UEs, 1.31 Gbits.

[0019] Although each UE needs to store 131,072 bits, not all UEs require this memory simultaneously. Therefore, each UE's memory budget is costed by the size of each GNB's memory. In telecommunications and computer networking, a network packet is a formatted unit of data carried by a packet-switched network. A packet consists of control information and user data, the latter also known as the payload. The control information provides data for delivering the payload (e.g., source and destination network addresses, error detection codes, or sequencing information). Typically, the control information is found in the packet header and trailer. A typical packet contains 1,000 or 1,500 bytes (8,000 or 12,000 bits). Therefore, 131,072 bits correlate to approximately 11 packets.

[0020] In one embodiment, N chunks of packets / sequences are created (N is a positive integer). In one embodiment, these chunks are common across users. In one embodiment, memory is allocated to users from a memory pool based on the number of packets for which the UE's RLC has not been acknowledged during AM. Thus, memory cannot be reserved for each UE operatively connected to the gNB, but instead memory is allocated from a common queue during AM, thus reducing overall memory requirements. The memory footprint is reduced, and therefore costs.

[0021] In one embodiment, the total memory for the RLC is divided into multiple chunks of N packets each. In one embodiment, a GNB UE uses a chunk of memory to perform AM until the UE is fully acknowledged (e.g., often a portion of a sequence is not received or acknowledged, and therefore a retransmission of the sequence is performed, which requires more bit / byte / packet space). In one embodiment, the UE requests chunks with N packets in each chunk to store AM data. In one embodiment, for the (Q+P)th packet (P is a positive integer), a new chunk is requested, and the second chunk is used for the next N packets. At the same time, other UEs request other chunks with open packets (e.g., not being used to store AM data).

[0022] In one embodiment, when confirmation of successful reception of the sequence is received at the UE during AM, the chunk is returned to the memory pool. In one embodiment, not all UEs reserve the entire chunk, but the memory pool can be actively scaled up to the entire chunk for each UE in AM.

[0023] In one embodiment, there are N chunks across three sectors, with each sector containing X UEs. For each UE in an active AM, a chunk is assigned to the UE upon receiving a sequence packet. This chunk holds the next N requested packets for the UE. In one embodiment, the chunk is the next N consecutive packets. In one embodiment, the chunk is the next N non-consecutive packets. In response to receiving the (Q+P)th packet (e.g., if the UE is having difficulty achieving acknowledgment in the AM, more packets are requested), a new chunk is requested and the old chunk is linked to the new chunk. In response to a positive acknowledgment of receipt of the packet from the UE, the packet pointer is released from the chunk, in response the packet is released and the chunk is returned to the memory pool.

[0024] FIG. 1 is a schematic diagram of a system for memory optimization of multi-user RLC (MOMR) 100, according to an embodiment.

[0025] The MOMR system 100 includes a CN 102 communicatively connected to a RAN 104 via a transport network 106 communicatively connected to base stations 108A and 108B (hereinafter, base stations 108), where antennas 110 are wirelessly connected to UEs 112 located within geographic coverage cells 114A and 114B (hereinafter, geographic coverage cells 114). The CN 102 includes one or more service providers 116.

[0026] The CN 102 (also known as a backbone) is the portion of a computer network that interconnects networks, providing a pathway for exchanging information between different local area networks (LANs) or sub-networks. In one embodiment, the CN 102 ties together diverse networks within the same building, different buildings in a campus environment, or across a wide geographic area.

[0027] In one embodiment, the RAN 104 is a Global System for Mobile Communications (GSM) RAN, a GSM / EDGE RAN, a UMTS RAN (UTRAN), an Evolved UMTS Terrestrial Radio Access Network (E-UTRAN), an Open RAN (O-RAN), or a Cloud RAN (C-RAN). The RAN 104 resides between the UE 112 (e.g., a mobile phone, a computer, or any remote control machine) and the CN 102. In one embodiment, the RAN 104 is a C-RAN for simplified representation and explanation. In one embodiment, a baseband unit (BBU) replaces the C-RAN.

[0028] In a hierarchical telecommunications network, the transport network 106 of the MOMR system 100 includes intermediate links between the CN 102 and the RAN 104. The two main methods of mobile backhaul implementation are fiber-based backhaul and wireless point-to-point backhaul. Other methods, such as copper-based wireline, satellite communications, and point-to-multipoint wireless technologies, are being phased out in 4G and 5G networks as capacity and latency requirements become higher. Backhaul refers to the network side that communicates with the Internet. The connection between the base station 108 and the UE 112 begins with the transport network 106 connected to the CN 102. In one embodiment, the transport network 106 includes wireline, fiber optic, and wireless components. The wireless section includes the use of microwave bands and mesh and edge network topologies that use high-capacity wireless channels to get packets to microwave or fiber links.

[0029] In one embodiment, the base station 108 is a gNB base station that connects 5G New Radio (NR) devices (e.g., 5G phones) to a 5G core network using an NR air interface. In one embodiment, the base station 108 is a lattice tower or freestanding tower, guyed tower, monopole tower, and hidden tower (e.g., towers designed to resemble trees, cacti, water towers, signs, light poles, and other types of structures). In one embodiment, the base station 108 is a cellular-enabled mobile device site where antennas and electronic communications equipment are typically located atop a radio mast, tower, or other elevated structure to create a cell (or adjacent cells) within the network. The elevated structure typically supports an antenna 110 and one or more sets of transmitters / receivers (transceivers), digital signal processors, control electronics, remote radio heads (RRHs), primary and backup power sources, and a shelter. Base stations are known by other names, such as base transceiver station, mobile telephone mast, or cellular base station. In one embodiment, other edge devices are configured to wirelessly communicate with the UEs. Edge devices provide an entry point into a service provider CN, such as CN 102. Examples include routers, routing switches, integrated access devices (IADs), multiplexers, and various metropolitan area network (MAN) and wide area network (WAN) access devices.

[0030] In at least one embodiment, antenna 110 is a sector antenna. In some embodiments, antenna 110 is a type of directional microwave antenna with a sector-shaped radiation pattern. In some embodiments, the sector is designed to have a radius of 60°, 90°, or 120°, with a few extra degrees added to ensure overlap. Furthermore, sector antennas are mounted in multiples when wider or full-circle coverage is desired. In some embodiments, antenna 110 is a rectangular antenna, sometimes referred to as a panel antenna or wireless antenna, used to transmit and receive radio waves or data between mobile devices or other devices and base stations. In some embodiments, antenna 110 is a circular antenna. In some embodiments, antenna 110 operates at microwave or ultra-high frequency (UHF) frequencies (300 MHz to 3 GHz). In other examples, antennas 110 are selected for their size and directionality. In some embodiments, antenna 110 is a multiple-input, multiple-output (MIMO) antenna, which simultaneously transmits and receives two or more data signals over the same wireless channel by taking advantage of multipath propagation.

[0031] In one embodiment, the UE 112 is a computer or computing system. Additionally or alternatively, the UE 112 has a user interface (UI) 422 ( FIG. 4 ), such as a liquid crystal display (LCD), light-emitting diode (LED), or organic light-emitting diode (OLED) screen interface, such as a touchscreen interface with digital buttons and a keyboard or physical buttons along with a physical keyboard. In one embodiment, the UE 112 connects to the Internet and interconnects with other devices. Additionally or alternatively, the UE 112 incorporates a built-in camera, voice and videophone call capabilities, video games, and global positioning system (GPS) functionality. Additionally or alternatively, the UE executes an operating system (OS) that allows capability-specific third-party apps to be installed and executed. In one embodiment, the UE 112 is a computer (such as a tablet computer, netbook, digital media player, digital assistant, graphing calculator, handheld game console, handheld personal computer (PC), laptop, mobile internet device (MID), personal digital assistant (PDA), pocket calculator, portable intermediate player, or ultra-mobile PC), a mobile phone (such as a camera phone, feature phone, smartphone, or phablet), a digital camera (such as a digital camcorder, or digital still camera (DSC), digital video camera (DVC), or front-facing camera), a pager, a personal navigation device (PND), a wearable computer (such as a calculator watch, smart watch, head-mounted display, earphone, or biometric device), or a smart card.

[0032] In one embodiment, the geographic coverage cell 114 includes a shape and a size. In one embodiment, the geographic coverage cell 114 is a macrocell (covering 1 Km to 30 Km), a microcell (covering 200 M to 2 Km), or a picocell (covering 4 M to 200 M). In one embodiment, the geographic coverage cell is circular, elliptical ( FIG. 1 ), sector-shaped, or lobed, although the geographic coverage cell 114 may be configured in almost any shape or size. The geographic coverage cell 114 represents the geographic area in which the antennas 110 and the UEs 112 are configured to communicate.

[0033] A service provider 116 or CSP is a company, vendor, customer, or organization that provides Internet backbone access directly to Internet service providers and sells bandwidth or network access to subscribers (using UEs), usually through access to a Network Access Point (NAP). Service providers are sometimes called backbone providers, Internet providers, or vendors. Service providers include telecommunications companies, data carriers, wireless communication providers, Internet service providers, and cable television operators that offer high-speed Internet access.

[0034] In a 5G RAN architecture, the BBU functionality is split into two functional units: a distributed unit (DU) 120 responsible for real-time L1 and L2 scheduling functions, and a centralized unit (CU) 118 responsible for non-real-time, higher-level L2 and L3. In a 5G Cloud RAN, such as the RAN 104, the DU's servers and associated software are hosted at a site, such as a base station 108, or at an edge cloud (e.g., a data center or central office), depending on transport availability and fronthaul interfaces. The split between the DU 120 and the RU 122 varies depending on the specific use case and implementation.

[0035] The CU 118 is responsible for non-real-time RRC and PDCP protocol stack functions, including RRC (Radio Resource Control Protocol, a Layer 3 (network layer) protocol used between a UE such as the UE 112 and a base station such as the base station 108), SDAP (Service Data Adaptation Protocol, which maps Quality of Service (QoS)), and PDCP protocol layers. The CU 118 is deployed in the cloud to support the integrated deployment of core network UPF (User Plane Function, which is a function that connects data to the Internet via the RAN) and edge computing. The CU 118 and the DU 120 are connected via an F1 interface. One CU manages one or more DUs.

[0036] The DU software is deployed on-site, such as in a base station 108, on a COTS (commercial off-the-shell) server. The DU software is typically deployed on-site near the RU 122 and runs the RLC (Radio Link Control), MAC, and parts of the PHY layer (the layer most closely associated with the physical connection between devices).

[0037] The RU 122 is a radio hardware unit that converts radio signals transmitted to and from the antenna 110 into digital signals for transmission over a packet network. The RU 122 handles the digital front end (DFE) and lower PHY layer, as well as digital beamforming functions. The RU is deployed on-site.

[0038] FIG. 2 is a block schematic diagram of a memory pool for MOMR 200, according to one embodiment.

[0039] FIG. 3 is a flow diagram of a method for MOMR 300, according to one embodiment.

[0040] 2 and 3 are described together to provide an understanding of the operation of the memory pools for MOMR system 100 and MOMR 200 through the method for MOMR 300. In one embodiment, the method for MOMR 300 is a functional overview of the memory pools for MOMR system 100 and MOMR 200. The method for MOMR 300 is performed by processing circuitry 402, which is described below with respect to FIG. 4. In one embodiment, some or all of the operations of the method for MOMR 300 are performed in accordance with instructions 406, which is described below with respect to FIG. 4.

[0041] The method for MOMR 300 includes operations 302-312, although these operations are not necessarily performed in the order shown. Operations may be added, substituted, reordered, and / or deleted as appropriate in accordance with the spirit and scope of the embodiments. In some embodiments, one or more of the operations of the method for MOMR 300 are repeated. In some embodiments, the operations of the method for MOMR 300 are performed sequentially unless otherwise specified.

[0042] In one embodiment, the memory pool for MOMR 200 is included with a DU, such as DU 120. In one embodiment, the memory pool for MOMR 200 is a DU shared memory pool for RLC acknowledged mode (AM) data storage.

[0043] In 5G NR, RLC has three different operating modes: Transparent Mode (TM), Unacknowledged Mode (UM), and AM, each mode transmitting and receiving data and serving different logical channels. In one embodiment, characteristics of RLC AM include: (1) buffering performed on transmission and reception, (2) segmentation performed on transmission and reassembly on reception, (3) feedback mechanism for unacknowledged acknowledgments (ACKs) / (NACKs) for RLC PDUs, (4) data for (signaling radio bearers) SRB1 / SRB2 / SRB3 and data radio bearers (DRBs), (5) sequence number (SN) size (12, 18) bits, (6) RLC AM mode complete / segmented SDUs are associated with SNs, and (7) 1 RLC SDU = 1 RLC PDU.

[0044] In AM, each RLC PDU is transmitted in ascending packet order and stored in memory pool 200. Since RLC AM supports ARQ (initiated in response to the RLC entity sender initiating a polling procedure that triggers a STATUS report from the AM RLC entity receiver) to ensure reliable delivery, an RLC STATUS PDU message is transmitted by the UE to indicate the status of the RLC PDUs received by the UE.

[0045] In operation 302 of the method for MOMR 300, N (N is a positive integer) packet chunks 202 are created across sectors, such as M (M is a positive integer) sectors 204, with each sector configured to support X (X is a positive integer) UEs per sector. In one embodiment, M is 3. In one embodiment, a packet chunk, such as packet chunk 202, includes N packets. In one embodiment, the packet chunks are created by processing circuitry 402 of FIG. 4. In one embodiment, memory pool 200 includes M sectors, such as sector 204, and is total memory because RLC is divided into multiple packet chunks. In one embodiment, each of packet chunks 202 is common to all UEs (e.g., UEs 206A, 206B, 206C, and 206D). In one embodiment, common describes packet chunks accessible to any UE, excluding packet chunks such as packet chunks 202A, 202B, 202C, 202D, 202E, and 202F. The process flows from operation 302 to operation 304.

[0046] In operation 304 of the method for MOMR 300, packet chunks, such as packet chunk 202, are allocated to UEs, such as UEs 206A, 206B, 206C, or 206D, from sectors, such as sector 204, included in memory pool 200 based on the number of unacknowledged packets for the UE RLC. In an embodiment, memory is not reserved per UE, but instead allocated from shared memory pool 200, thus reducing overall memory requirements. The memory footprint is reduced. Memory allocation is not required per UE, thus reducing additional memory costs. In an embodiment, shared memory pool 200 and packet chunks 202 are common to all UEs, and upon AM completion, packet chunks 202 allocated to a UE are open backed up for use by another UE. In an embodiment, a gNB user uses packet chunks in memory. In an embodiment, a UE requests packet chunks to store up to N packets in each packet chunk. The process flows from operation 304 to operation 306.

[0047] At operation 306 of the method for MOMR 300, in response to receiving the (Q+P)th packet, a new packet chunk is requested. In an embodiment, a new packet chunk is requested before the (Q+P)th packet, and the new packet chunk is used for the next N packets. In FIG. 2, in a non-limiting example, UE1 206A is assigned packet chunk 202A, UE2 206B is assigned packet chunk 202B, UE3 206C is assigned packet chunk 202C, and UE 206D is assigned packet chunk 202D. Continuing with the non-limiting example, in response to UE2 206B receiving the (Q+P)th packet, a new packet chunk 202E is requested and assigned. Continuing with the non-limiting example, in response to UE4 206D receiving the (Q+P)th packet, a new packet chunk 202F is requested and assigned. The process flows from operation 306 to operation 308 .

[0048] At operation 308 of the method for MOMR 300, in response to the new packet chunk being allocated, the old packet chunk is linked to the new chunk. Continuing with the non-limiting example above, packet chunk 202B is linked to packet chunk 202E (each having a common UE 206B), and packet chunk 202D is linked to packet chunk 202F (each having a common UE 206D). The process flows from operation 308 to operation 310.

[0049] In operation 310 of the method for MOMR 300, in response to a positive acknowledgment (ACK) of receipt of the packet from the UE, the packet pointer is released from the packet chunk. In computer science, a pointer is an object in many programming languages ​​that stores a memory address, which is another value located in computer memory or, in some cases, memory-mapped computer hardware. A pointer references a location in memory, and retrieving the value stored at that location is known as retrieving the pointer's dereference. By analogy, a page number in a book's index can be considered a pointer to the corresponding page. Retrieving such pointer dereference is accomplished by turning to the page with a given page number and reading the text found on that page.

[0050] In one embodiment, other UEs are still using packets remaining in the chunk. In one embodiment, the UE reserves the full memory contained in the packet chunk even if full memory is not needed. In one embodiment, each packet chunk scales up to use the full memory of each packet chunk for the UE. The process flows from operation 310 to operation 312.

[0051] In operation 312 of the method for MOMR 300, packet chunks are returned to the memory pool in response to all packets being released. In one embodiment, packet chunks, such as packet 202, are returned to shared memory pool 200 upon receipt of an acknowledgment (ACK) indicating successful receipt of the packet at the UE. In one embodiment, each UE in a cell, such as cells 114A and 114B, does not need packet chunks (e.g., is not operating in AM), but instead requests packet chunks during AM.

[0052] 4 is a block diagram of a processing circuit 400 for optimizing memory for multi-user RLC, according to one embodiment. In one embodiment, the processing circuit 400 for optimizing memory for multi-user RLC is a general-purpose computing device that includes a hardware processor 402 and a non-transitory computer-readable storage medium 404. The storage medium 404 is encoded with, i.e., stores, among other things, computer program code 406, i.e., a set of executable instructions, such as algorithm or method 300. Execution of the instructions 406 by the hardware processor 402 represents (at least in part) a method for optimizing memory for multi-user RLC that implements some or all of the methods described herein (hereinafter, the described processes and / or methods) according to one or more embodiments.

[0053] The processor 402 is electrically coupled to a computer-readable storage medium 404 via a bus 408. The processor 402 is further electrically coupled to an I / O interface 410 by the bus 408. A network interface 412 is further electrically connected to the processor 402 via the bus 408. The network interface 412 is connected to a network 414 such that the processor 402 and the computer-readable storage medium 404 connect to external elements via the network 414. The processor 402 is configured to execute computer program code 406 encoded in the computer-readable storage medium 404 to cause the processing circuit 400 to optimize memory for multi-user RLC so as to enable it to perform some or all of the described processes and / or methods. In one or more embodiments, the processor 402 is a central processing unit, a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or other suitable processing unit.

[0054] In one or more embodiments, computer-readable storage medium 404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 404 includes semiconductor or solid-state memory, magnetic tape, removable computer diskettes, random access memory (RAM), read-only memory (ROM), rigid magnetic disks, and / or optical disks. In one or more embodiments using optical disks, computer-readable storage medium 404 includes a compact disk-read-only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0055] In one or more embodiments, the storage medium 404 stores computer program code 406 configured to cause the processing circuit 400 to optimize memory for multi-user RLC so as to enable it to perform some or all of the described processes and / or methods. In one or more embodiments, the storage medium 404 further stores information such as algorithms that facilitate performing some or all of the described processes and / or methods.

[0056] The processing circuit 400 for optimizing memory for multi-user RLC includes an I / O interface 410. The I / O interface 410 is coupled to external circuitry. In one or more embodiments, the I / O interface 410 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor direction keys for communicating information and commands to the processor 402.

[0057] The processing circuit 400 for creating permanent URLs further includes a network interface 412 coupled to the processor 402. The network interface 412 enables the processing circuit 400 to create permanent URLs for communication with a network 414 to which one or more computer systems are connected. The network interface 412 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as ETHERNET, IEEE-864, etc. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more processing circuits 400 for creating permanent URLs.

[0058] The processing circuit 400 for creating permanent URLs is configured to receive information via an I / O interface 410. The information received via the I / O interface 410 includes one or more of instructions, data, design rules, and / or other parameters for processing by the processor 402. The information is transferred to the processor 402 via a bus 408. The processing circuit 400 for optimizing memory for multi-user RLC is configured to receive information related to a UI 422 via the I / O interface 410. The information is stored in the computer-readable medium 404 as a user interface (UI) 422.

[0059] In some embodiments, some or all of the described processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in to a software application.

[0060] In one embodiment, the method includes transmitting, by a processing circuit, a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE; in response to the packet being received, allocating, by the processing circuit, a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being transmitted; and in response to successful completion of the AM, returning, by the processing circuit, the packet chunk to the shared memory pool.

[0061] In an embodiment, the method further includes, before transmitting the packet to the UE to initiate AM between the DU and the UE, creating, by the processing circuitry, N packet chunks (N is a positive integer) to be included in the shared memory pool.

[0062] In an embodiment, the method further includes creating, by the processing circuitry, M sectors of the packet chunk, where M is a positive integer, wherein the N packet chunks are distributed across the M sectors.

[0063] In an embodiment, the method further includes distributing, by the processing circuitry, X UEs per sector, where X is a positive integer.

[0064] In an embodiment, the method further includes requesting, by the processing circuitry, an additional packet chunk for the UE based on a next request packet being transmitted to the UE that exceeds a packet size of the packet chunk.

[0065] In one embodiment, the packet size of the packet chunk and the additional packet chunk is Q packets (Q is a positive integer), and the next request packet is the (Q+P)th packet received (P is a positive integer).

[0066] In an embodiment, the method further includes linking, by the processing circuitry, additional packet chunks to the packet chunk.

[0067] In some embodiments, the method further includes removing the packet pointer from the packet chunk before returning the packet chunk to the shared memory pool.

[0068] In one embodiment, the apparatus includes a processor and a memory storing instructions that, when executed by the processor, cause the processor to, by a processing circuit, send a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE; in response to the packet being received, cause the processing circuit to allocate a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being transmitted; and in response to the AM completing successfully, cause the processing circuit to return the packet chunk to the shared memory pool.

[0069] In an embodiment, the instructions, in response to being executed by the processor, further cause the processor to create, by the processing circuitry, N packet chunks (N is a positive integer) to be included in the shared memory pool prior to transmitting the SN to the UE to initiate AM between the DU and the UE.

[0070] In one embodiment, the instructions, in response to being executed by the processor, further cause the processor to create, by the processing circuitry, M sectors of the packet chunk (M is a positive integer), such that the N packet chunks are distributed across the M sectors.

[0071] In an embodiment, the instructions, in response to being executed by the processor, further cause the processor to, by the processing circuitry, distribute X UEs per sector, where X is a positive integer.

[0072] In an embodiment, the instructions, in response to being executed by the processor, further cause the processor to request, by the processing circuitry, an additional packet chunk for the UE based on a next requested packet being sent to the UE that exceeds a packet size of the packet chunk.

[0073] In one embodiment, the packet size of the packet chunk and the additional packet chunk is Q packets (Q is a positive integer), and the next request packet is the (Q+P)th packet received (P is a positive integer).

[0074] In some embodiments, the instructions, in response to being executed by the processor, further cause the processor, by the processing circuitry, to link additional packet chunks to the packet chunk.

[0075] In some embodiments, the instructions, in response to being executed by the processor, further cause the processor to remove the packet pointer from the packet chunk before returning the packet chunk to the shared memory pool.

[0076] In an embodiment, a non-transitory computer-readable medium having stored thereon instructions that, in response to being executed by the processor, cause the processor to cause a processing circuit to send a packet to a user equipment (UE) to initiate an acknowledgement mode (AM) between a distributed unit (DU) and the UE, in response to the packet being received, cause the processing circuit to allocate a packet chunk included in a shared memory pool from the DU to the UE to which the packet is being sent, and in response to the AM completing successfully, cause the processing circuit to return the packet chunk to the shared memory pool.

[0077] In an embodiment, the instructions, in response to being executed by the processor, further cause the processor to create, by the processing circuitry, N packet chunks (N is a positive integer) to be included in the shared memory pool prior to transmitting the packet to the UE to initiate AM between the DU and the UE.

[0078] In one embodiment, the instructions, in response to being executed by the processor, further cause the processor to create, by the processing circuitry, M sectors of the packet chunk (M is a positive integer), such that the N packet chunks are distributed across the M sectors.

[0079] In an embodiment, the instructions, in response to being executed by the processor, further cause the processor to, by the processing circuitry, distribute X UEs per sector, where X is a positive integer.

[0080] The foregoing outlines features of certain embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will readily appreciate that this disclosure may be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as those incorporated herein. Those skilled in the art should further recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the embodiments.

Claims

1. transmitting, by a processing circuit, a packet to a user equipment (UE) to initiate an acknowledged mode (AM) between the distributed unit (DU) and the UE; In response to receiving the packet, allocating, by the processing circuitry, packet chunks contained in a shared memory pool from the (DU) to the UE to which the packet is being transmitted; returning, by the processing circuitry, the packet chunk to the shared memory pool in response to the AM completing successfully; A method comprising:

2. creating, by the processing circuitry, N packet chunks (N being a positive integer) to be included in the shared memory pool before transmitting the packet to the UE to initiate the AM between the DU and the UE; The method of claim 1 further comprising:

3. creating, by the processing circuitry, M sectors of packet chunks, where M is a positive integer, and the N packet chunks are distributed across the M sectors; The method of claim 2 further comprising:

4. distributing X UEs per sector (X being a positive integer) by the processing circuitry; The method of claim 3 further comprising:

5. requesting, by the processing circuitry, an additional packet chunk for the UE based on a next request packet being transmitted to the UE that exceeds a packet size of the packet chunk; The method of claim 1 further comprising:

6. the packet size of the packet chunk and the additional packet chunk is Q packets (Q is a positive integer); The next request packet is the (Q+P)th packet received (P is a positive integer). The method of claim 5.

7. linking, by the processing circuitry, the additional packet chunk to the packet chunk. The method of claim 5 further comprising:

8. removing the packet pointer from the packet chunk before returning the packet chunk to the shared memory pool. The method of claim 1 further comprising:

9. a processor; and a memory storing instructions that, in response to being executed by the processor, cause the processor to: causing a processing circuit to transmit a packet to a user equipment (UE) to initiate an acknowledged mode (AM) between the distributed unit (DU) and the UE; In response to receiving the packet, causing the processing circuitry to allocate a packet chunk included in a shared memory pool from the (DU) to the UE to which the packet is being transmitted; causing the processing circuitry to return the packet chunk to the shared memory pool in response to the AM completing successfully. Device.

10. The instructions, in response to being executed by the processor, further cause the processor to: causing the processing circuit to create N packet chunks (N is a positive integer) to be included in the shared memory pool before transmitting the packet to the UE to initiate the AM between the DU and the UE; 10. The apparatus of claim 9.

11. The instructions, in response to being executed by the processor, further cause the processor to: causing the processing circuitry to create M sectors of packet chunks, where M is a positive integer, and the N packet chunks are distributed across the M sectors.

11. The apparatus of claim 10.

12. The instructions, in response to being executed by the processor, further cause the processor to: distributing X UEs per sector (X being a positive integer) by the processing circuitry; 12. The apparatus of claim 11.

13. The instructions, in response to being executed by the processor, further cause the processor to: causing the processing circuit to request an additional packet chunk for the UE based on a next request packet being transmitted to the UE that exceeds a packet size of the packet chunk; 10. The apparatus of claim 9.

14. the packet size of the packet chunk and the additional packet chunk is Q packets (Q is a positive integer); The next request packet is the (Q+P)th packet received (P is a positive integer).

14. The apparatus of claim 13.

15. The instructions, in response to being executed by the processor, further cause the processor to: linking, by the processing circuitry, the additional packet chunk to the packet chunk.

14. The apparatus of claim 13.

16. The instructions, in response to being executed by the processor, further cause the processor to: removing a packet pointer from the packet chunk before returning the packet chunk to the shared memory pool; 10. The apparatus of claim 1.

17. In response to being executed by a processor, the processor: causing a processing circuit to transmit a packet to a user equipment (UE) to initiate an acknowledged mode (AM) between the distributed unit (DU) and the UE; In response to receiving the packet, causing the processing circuitry to allocate a packet chunk included in a shared memory pool from the (DU) to the UE to which the packet is being transmitted; In response to the AM completing successfully, the processing circuitry returns the packet chunk to the shared memory pool. A non-transitory computer-readable medium having instructions stored thereon.

18. The instructions, in response to being executed by the processor, further cause the processor to: causing the processing circuit to create N packet chunks (N is a positive integer) to be included in the shared memory pool before transmitting the packet to the UE to initiate the AM between the DU and the UE; 20. The non-transitory computer-readable medium of claim 17.

19. The instructions, in response to being executed by the processor, further cause the processor to: causing the processing circuitry to create M sectors of packet chunks, where M is a positive integer, and the N packet chunks are distributed across the M sectors.

20. The non-transitory computer-readable medium of claim 18.

20. The instructions, in response to being executed by the processor, further cause the processor to: distributing X UEs per sector (X being a positive integer) by the processing circuitry; 20. The non-transitory computer-readable medium of claim 19.

Images