Display panel and display device

Abstract

At least one embodiment of the present disclosure provides a display panel and a display device, the display panel including a base substrate, an active layer, a gate, and a source / drain electrode layer stacked in this order on the base substrate, and a planarization layer disposed on a side of the source / drain electrode layer away from the base substrate, wherein the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the source / drain electrode layer and the active layer onto the base substrate, and the thickness of the source / drain electrode layer is greater than the thickness of the gate in a direction perpendicular to a major surface of the base substrate, and by designing the gate, the source / drain electrode layer, and the active layer to have the above structural relationship, the flatness of the planarization layer disposed on the source / drain electrode layer can be reduced, i.e., the surface of the planarization layer can be made flatter, thereby improving the display effect of the display panel.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202211394700.4, filed on November 9, 2022, the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present disclosure relate to a display panel and a display device. [Background technology]

[0003] Currently, the most widely used display devices include thin film transistor liquid crystal displays (TFT-LCDs) and active matrix organic light emitting diode (AMOLED) displays, etc. Active matrix organic light emitting diode (AMOLED) displays have the advantages of long life, high display brightness, high contrast, and a wide color gamut.

[0004] An organic light emitting diode display device using an active matrix organic light emitting diode as a light emitting element is thinner and lighter than a conventional liquid crystal display device, and the organic light emitting diode display device also has the characteristics of fast response, wide viewing angle, and low driving voltage, so that the organic light emitting diode display device can be widely used in cellular phones, personal digital assistants, televisions, and monitors. An organic light emitting diode display device mainly includes a cathode, an emitting layer, and an anode, and in an active matrix organic light emitting diode display device, each sub-pixel has a switching transistor and a driving transistor, and the switching transistor and the driving transistor can be adjusted to make the emitting layer of the organic light emitting diode display device emit light. Summary of the Invention [Means for solving the problem]

[0005] At least one embodiment of the present disclosure provides a display panel and a display device, in which the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the source / drain electrode layer and the active layer onto the base substrate, and the thickness of the source / drain electrode layer is greater than the thickness of the gate in a direction perpendicular to the main surface of the base substrate; by designing the gate, the source / drain electrode layer, and the active layer to have the above structural relationship, the flatness of the planarization layer located on the source / drain electrode layer can be reduced, i.e., the surface of the planarization layer can be made flatter, thereby improving the display effect of the display panel.

[0006] At least one embodiment of the present disclosure provides a display panel including a base substrate, an active layer, a gate, and a source / drain electrode layer stacked in this order on the base substrate, and a planarization layer provided on a side of the source / drain electrode layer away from the base substrate, wherein a normal projection of the gate onto the base substrate is located within a normal projection of the source / drain electrode layer and the active layer onto the base substrate, and a thickness of the source / drain electrode layer is greater than a thickness of the gate in a direction perpendicular to a main surface of the base substrate.

[0007] For example, in a display panel according to at least one embodiment of the present disclosure, a gate insulating layer is provided between the active layer and the gate, an interlayer insulating layer is provided between the gate and the source / drain electrode layer, the source / drain electrode layer includes a first source / drain electrode and a second source / drain electrode provided opposite each other, the first source / drain electrode is electrically connected to the active layer via a first via structure that passes through the interlayer insulating layer and the gate insulating layer in that order, the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the first source / drain electrode onto the base substrate, and the second source / drain electrode is electrically connected to the active layer via a second via structure that passes through the interlayer insulating layer and the gate insulating layer in that order.

[0008] For example, in a display panel according to at least one embodiment of the present disclosure, the end of the first source / drain electrode away from the second source / drain electrode is electrically connected to the active layer through the first via structure.

[0009] For example, a display panel according to at least one embodiment of the present disclosure further includes a plurality of data lines, the plurality of data lines being arranged in the same layer as the source / drain electrode layer, and the plurality of data lines being electrically connected to corresponding second source / drain electrodes, respectively.

[0010] For example, a display panel according to at least one embodiment of the present disclosure further includes a pixel definition layer provided on a side of the planarization layer away from the base substrate, the pixel definition layer including a main body portion and an opening region between adjacent main body portions.

[0011] For example, a display panel according to at least one embodiment of the present disclosure further includes a first electrode provided on a side of the planarization layer away from the base substrate, the first electrode being provided in the opening region, and the first electrode being electrically connected to the first source / drain electrode through a third via structure penetrating the planarization layer.

[0012] For example, a display panel according to at least one embodiment of the present disclosure includes a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged adjacent to each other in order, and the orthogonal projection of the first source / drain electrode corresponding to the first color sub-pixel onto the base substrate has a first metal area S M1 and the orthogonal projection of the first source-drain electrode corresponding to the second color subpixel onto the base substrate has a second metal area S M2 and the orthogonal projection of the first source-drain electrode corresponding to the third color subpixel onto the base substrate has a third metal area S M3 the first metal area S M1 is the second metal area S M2 the second metal area S M2 is the third metal area S M3 is less than.

[0013] For example, in a display panel according to at least one embodiment of the present disclosure, the first color subpixel, the second color subpixel, and the third color subpixel are red subpixels, green subpixels, and blue subpixels, respectively, and the first color subpixel has a first subpixel area S P1 and the second color subpixel has a second subpixel area S P2 and the third color subpixel has a third subpixel area S P3 and

number

[0014] For example, in a display panel according to at least one embodiment of the present disclosure, the area ratio F1 of the first source-drain electrode corresponding to the first color subpixel, the area ratio F2 of the first source-drain electrode corresponding to the second color subpixel, and the area ratio F3 of the first source-drain electrode corresponding to the third color subpixel are 55%, 50%, and 30%, respectively.

[0015] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of subpixels are arranged in an array, and in the row direction, the width of the first source-drain electrode corresponding to the first color subpixel is equal to or less than the width of the first source-drain electrode corresponding to the adjacent second color subpixel, and the width of the first source-drain electrode corresponding to the second color subpixel is equal to or less than the width of the first source-drain electrode corresponding to the adjacent third color subpixel.

[0016] For example, in a display panel according to at least one embodiment of the present disclosure, different positions corresponding to the planarization layer have different flatnesses, and the flatness of the planarization layer increases with a decrease in the area ratio of the first source-drain electrode corresponding to each of the subpixels.

[0017] For example, in a display panel according to at least one embodiment of the present disclosure, the first flatness F of the planarization layer corresponding to the first color subpixel is P1 is the second flatness F of the planarization layer corresponding to the second color subpixel P2 the second flatness F of the planarization layer corresponding to the second color subpixel is less than or equal to P2 is the third flatness F of the planarization layer corresponding to the third color subpixel P3 The following is the result.

[0018] For example, in a display panel according to at least one embodiment of the present disclosure, the first flatness is:

number

number

number

[0019] For example, in a display panel according to at least one embodiment of the present disclosure,

number

[0020] For example, in a display panel according to at least one embodiment of the present disclosure, an equation obtained by performing polynomial fitting on the average flatness x of the planarization layer and the area ratio y of the first source-drain electrode corresponding to each of the subpixels is:

number

[0021] For example, in a display panel according to at least one embodiment of the present disclosure, an equation obtained by performing polynomial fitting on the average flatness x of the planarization layer and the area ratio y of the first source-drain electrode corresponding to each of the subpixels is:

number

number

[0022] For example, in a display panel according to at least one embodiment of the present disclosure, the first flatness F P1 , the second flatness F P2 and the third flatness F P3 The magnitudes are 1.5%, 2% and 2.5%, respectively.

[0023] For example, a display panel according to at least one embodiment of the present disclosure further includes a power supply voltage signal line provided on a side of the third color subpixel that is away from the second color subpixel.

[0024] For example, in a display panel according to at least one embodiment of the present disclosure, the power supply voltage signal line includes a first power supply voltage signal line and a second power supply voltage signal line that are stacked, the first power supply voltage signal line is provided in the same layer as the source / drain electrode layer, the second power supply voltage signal line is provided in the same layer as the gate, the first power supply voltage signal line has an integral structure, and the second power supply voltage signal line includes a notch.

[0025] For example, in a display panel according to at least one embodiment of the present disclosure, the power supply voltage signal line and the data line connected to the third color subpixel are respectively arranged on both sides of the third color subpixel, and the power supply voltage signal line and the data line connected to the third color subpixel are arranged opposite each other, and in a direction from the power supply voltage signal line to the data line connected to the third color subpixel, the width of the first power supply voltage signal line is larger than the width of the second power supply voltage signal line.

[0026] For example, in a display panel according to at least one embodiment of the present disclosure, an edge of the second power supply voltage signal line away from the data line connected to the third color subpixel is aligned with an edge of the first power supply voltage signal line away from the data line connected to the third color subpixel, and an edge of the second power supply voltage signal line close to the data line connected to the third color subpixel is located on the side of the edge of the first power supply voltage signal line close to the data line connected to the third color subpixel away from the data line connected to the third color subpixel.

[0027] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first power supply voltage signal line is two to four times the width of the second power supply voltage signal line.

[0028] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first power supply voltage signal line is 10 microns to 30 microns, and the width of the second power supply voltage signal line is 2 microns to 20 microns.

[0029] For example, in a display panel according to at least one embodiment of the present disclosure, the orthogonal projection of the main body portion included in the pixel definition layer onto the base substrate, the orthogonal projection of the first power supply voltage signal line onto the base substrate, and the orthogonal projection of the second power supply voltage signal line onto the base substrate at least partially overlap.

[0030] For example, in a display panel according to at least one embodiment of the present disclosure, each of the plurality of data lines includes a first sub-data line and a second sub-data line arranged in a stacked manner, the first sub-data line is arranged in the same layer as the source / drain electrode layer, the second sub-data line is arranged in the same layer as the gate, the first sub-data line has an integral structure, the second sub-data line includes a notch, and each of the data lines is electrically connected to the first source / drain electrode of the corresponding sub-pixel via the first sub-data line.

[0031] For example, in a display panel according to at least one embodiment of the present disclosure, in a direction from the power supply voltage signal line to the data line connected to the third color subpixel, the width of the first sub-data line is larger than the width of the second sub-data line.

[0032] For example, in a display panel according to at least one embodiment of the present disclosure, on the same data line, an edge of the second sub-data line away from the sub-pixel connected to the data line on which it is located is aligned with an edge of the corresponding first sub-data line away from the sub-pixel electrically connected to it, and an edge of the second sub-data line close to the sub-pixel connected to the data line on which it is located is located on the side away from the corresponding sub-pixel of the edge of the corresponding first sub-data line close to the sub-pixel electrically connected to it.

[0033] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first sub-data line is two to four times the width of the second sub-data line in the same data line.

[0034] For example, in a display panel according to at least one embodiment of the present disclosure, in the same data line, the width of the first sub-data line is 2 microns to 20 microns, and the width of the second sub-data line is 2 microns to 10 microns.

[0035] For example, in a display panel according to at least one embodiment of the present disclosure, the orthogonal projection onto the base substrate of the main body portion included in the pixel definition layer, the orthogonal projection onto the base substrate of the first sub-data line included in the same data line, and the orthogonal projection onto the base substrate of the second sub-data line at least partially overlap.

[0036] For example, in a display panel according to at least one embodiment of the present disclosure, the thickness of the source-drain electrode layer is 3 to 7 times the thickness of the gate.

[0037] For example, a display panel according to at least one embodiment of the present disclosure further includes a plurality of gate lines, the plurality of gate lines intersecting the plurality of data lines to define a plurality of pixel areas, each of the pixel areas corresponding to one of the sub-pixels.

[0038] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of gate lines are provided in the same layer as the source-drain electrode layer, the gate lines intersect with the second sub-data lines, and the gate lines are spaced apart from the first sub-data lines.

[0039] For example, a display panel according to at least one embodiment of the present disclosure further includes a first initial signal line, a second initial signal line, and a power supply voltage connecting line, the power supply voltage connecting line is configured to be connected to the power supply voltage signal line, and the first initial signal line, the second initial signal line, and the power supply voltage connecting line are all provided in the same layer as the source / drain electrode layer and are provided in parallel to the gate line.

[0040] For example, a display panel according to at least one embodiment of the present disclosure further includes an initial signal line connecting line, the initial signal line connecting line being arranged on a side of the second color subpixel that is close to the third color subpixel, the initial signal line connecting line and the data line connected to the second color subpixel being arranged opposite to each other on both sides of the second color subpixel, and the initial signal line connecting line crossing both the first initial signal line and the second initial signal line.

[0041] For example, in a display panel according to at least one embodiment of the present disclosure, the initial signal line connecting line includes a first sub-initial signal line connecting line and a second sub-initial signal line connecting line that are stacked, the first sub-initial signal line connecting line is arranged in the same layer as the source / drain electrode layer, the second sub-initial signal line connecting line is arranged in the same layer as the gate, the first sub-initial signal line connecting line has an integral structure, and the second sub-initial signal line connecting line includes a notch.

[0042] For example, in a display panel according to at least one embodiment of the present disclosure, in a direction from the initial signal line connecting line to the data line connected to the second color subpixel, the width of the first sub initial signal line connecting line is larger than the width of the second sub initial signal line connecting line.

[0043] For example, in a display panel according to at least one embodiment of the present disclosure, the edge of the second sub-initial signal line connecting line away from the second color subpixel is aligned with the edge of the first sub-initial signal line connecting line away from the second color subpixel, and the edge of the second sub-initial signal line connecting line close to the second color subpixel is located on the side away from the second color subpixel of the edge of the first sub-initial signal line connecting line close to the second color subpixel.

[0044] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first sub-initial signal line connecting line is two to three times the width of the second sub-initial signal line connecting line.

[0045] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first sub-initial signal line-connecting line is 2 microns to 20 microns, and the width of the second sub-initial signal line-connecting line is 2 microns to 10 microns.

[0046] For example, a display panel according to at least one embodiment of the present disclosure further includes a power supply voltage signal transmission line, the power supply voltage signal transmission line being arranged on a side of the first color subpixel adjacent to the second color subpixel, and the power supply voltage signal transmission line and the data line connected to the first color subpixel being arranged on both sides of the first color subpixel facing each other.

[0047] For example, in a display panel according to at least one embodiment of the present disclosure, the power supply voltage signal transmission line includes a first power supply voltage signal transmission line and a second power supply voltage signal transmission line that are stacked, the first power supply voltage signal transmission line is provided in the same layer as the source / drain electrode layer, the second power supply voltage signal transmission line is provided in the same layer as the gate, the first power supply voltage signal transmission line has an integral structure, and the second power supply voltage signal transmission line includes a notch.

[0048] For example, in a display panel according to at least one embodiment of the present disclosure, in a direction from the power supply voltage signal transmission line to the data line connected to the first color subpixel, the width of the first power supply voltage signal transmission line is larger than the width of the second power supply voltage signal transmission line.

[0049] For example, in a display panel according to at least one embodiment of the present disclosure, an edge of the second power supply voltage signal transmission line away from the data line connected to the first color subpixel is aligned with an edge of the first power supply voltage signal transmission line away from the data line connected to the first color subpixel, and an edge of the second power supply voltage signal transmission line close to the data line connected to the first color subpixel is located on the side of the edge of the first power supply voltage signal transmission line close to the data line connected to the first color subpixel that is away from the data line connected to the first color subpixel.

[0050] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first power supply voltage signal transmission line is two to three times the width of the second power supply voltage signal transmission line.

[0051] For example, in a display panel according to at least one embodiment of the present disclosure, the width of the first power supply voltage signal transmission line is 2 microns to 30 microns, and the width of the second power supply voltage signal transmission line is 2 microns to 10 microns.

[0052] For example, in a display panel according to at least one embodiment of the present disclosure, the data lines extend in a first direction, the gate lines extend in a second direction, and the first direction and the second direction are perpendicular to each other.

[0053] For example, in a display panel according to at least one embodiment of the present disclosure, in the first direction, a width of the first power supply voltage signal line is W1, a width of the first sub-data line is W2, a width of the first sub-initial signal line connecting line is W3, a width of the source-drain electrode layer corresponding to the third color subpixel is W4, a width of the source-drain electrode layer corresponding to the second color subpixel is W5, a width of the source-drain electrode layer corresponding to the first color subpixel is W6, a width of a first gap between the first sub-initial signal line connecting line and the second color subpixel is W7, a gap between the second color subpixel and the first power supply voltage signal transmission line is W8, and a width of the first power supply voltage signal transmission line is W9, and W1 is equal to or approximately equal to W4,

number

[0054] For example, in a display panel according to at least one embodiment of the present disclosure, the line width spacing ratio of each of the gate lines is:

number

number

number

[0055] For example, in a display panel according to at least one embodiment of the present disclosure, the gradient K of the undulations of the planarization layer em and the gate line width spacing ratio K ws The equation obtained by polynomial fitting to

number

number

[0056] For example, a display panel according to at least one embodiment of the present disclosure further includes a light-emitting element provided on a side of the first electrode away from the base substrate, the light-emitting element including a light-emitting layer and an organic functional layer stacked with the light-emitting layer, the light-emitting layer being formed by a printing process, and the organic functional layer being formed by a vapor deposition process.

[0057] For example, in a display panel according to at least one embodiment of the present disclosure, the light-emitting elements include a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and the ratio of the thickness of the red light-emitting layer included in the red light-emitting element to the peak wavelength of the red light ranges from 0.15 to 0.4, the ratio of the thickness of the green light-emitting layer included in the green light-emitting element to the peak wavelength of the green light ranges from 0.15 to 0.3, and the ratio of the thickness of the blue light-emitting layer included in the blue light-emitting element to the peak wavelength of the blue light ranges from 0.1 to 0.2.

[0058] For example, in a display panel according to at least one embodiment of the present disclosure, the range of the ratio between the sum of the thicknesses of the organic functional layers corresponding to the multiple red light-emitting layers and the peak wavelength of the red light is 0.2 to 0.4, the range of the ratio between the sum of the thicknesses of the organic functional layers corresponding to the multiple green light-emitting layers and the peak wavelength of the green light is 0.2 to 0.3, and the range of the ratio between the sum of the thicknesses of the organic functional layers corresponding to the multiple blue light-emitting layers and the peak wavelength of the blue light is 0.15 to 0.25.

[0059] At least one embodiment of the present disclosure further provides a display device including the display panel according to any one of the above aspects.

[0060] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be apparent that the drawings described below are only related to some embodiments of the present disclosure and do not limit the present disclosure. [Brief explanation of the drawings]

[0061] [Figure 1A] 1 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure. [Figure 1B] FIG. 10 is a schematic cross-sectional view of another display panel according to at least one embodiment of the present disclosure. [Figure 2A] 1 is a schematic planar structure diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a schematic planar structure diagram of a single active layer in FIG. 2A. [Figure 2C] 2B is a schematic planar structural diagram when the active layer and the gate in FIG. 2A are overlapped. [Figure 3] 1 is a schematic planar structure diagram of a sub-pixel and corresponding source / drain electrode layers according to at least one embodiment of the present disclosure. [Figure 4] 2 is a schematic cross-sectional view of a sub-pixel and a corresponding source / drain electrode layer according to at least one embodiment of the present disclosure. FIG. [Figure 5]FIG. 10 is a schematic planar structure diagram of another sub-pixel and corresponding source / drain electrode layers according to at least one embodiment of the present disclosure. [Figure 6] FIG. 10 is a schematic cross-sectional view of another sub-pixel and corresponding source-drain electrode layer according to at least one embodiment of the present disclosure. [Figure 7] FIG. 10 is a schematic planar structure diagram of yet another display panel in accordance with at least one embodiment of the present disclosure. [Figure 8A] 1 is a schematic plan view of a power supply voltage signal line according to at least one embodiment of the present disclosure; [Figure 8B] FIG. 8B is a schematic planar structure diagram of a single active layer in FIG. 8A. [Figure 8C] 8B is a schematic planar structural diagram when a part of the active layer, gate, and data line in FIG. 8A are overlapped. [Figure 9] FIG. 10 is a schematic cross-sectional view of yet another display panel according to at least one embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic planar structure diagram of yet another display panel in accordance with at least one embodiment of the present disclosure. [Figure 11] 1 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure. [Figure 12] FIG. 10 is a schematic planar structure diagram of yet another display panel in accordance with at least one embodiment of the present disclosure. [Figure 13] 1 is a schematic diagram of a circuit structure of a display panel according to at least one embodiment of the present disclosure. [Figure 14] FIG. 10 is a schematic diagram of a circuit structure of another display panel in accordance with at least one embodiment of the present disclosure. [Figure 15] FIG. 10 is a schematic cross-sectional view of yet another display panel according to at least one embodiment of the present disclosure. [Figure 16] FIG. 1 is a block diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0062] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without creative work fall within the scope of protection of the present disclosure.

[0063] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by those skilled in the art. The words "first," "second," and similar words used in this disclosure do not denote order, number, or importance, but are merely used to distinguish different components. Similar words such as "comprise" or "comprise" mean that the element or item appearing before the word covers the elements or items listed after the word and their equivalents, but does not exclude other elements or items. Similar words such as "connect" or "coupled" are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," and "right" are used only to indicate relative positions, and if the absolute position of the described object changes, the relative positions may also change accordingly.

[0064] Currently, widely used display devices include thin film transistor (TFT) liquid crystal displays (LCDs) and active matrix organic light emitting diode (AMOLED) displays, and AMOLED display devices have advantages such as long life, high display brightness, high contrast, and a wide color gamut. AMOLED display devices typically include a planarization layer disposed on a pixel driving circuit, and the planarization layer's flatness significantly affects the performance of the AMOLED display device. By adjusting the ratio of the capacitor area to the pixel area of ​​each subpixel, the numerical value of the ratio of the capacitor area to the pixel area of ​​each subpixel and the corresponding size relationship can be set, thereby improving the flatness of the planarization layer on the pixel driving circuit. Furthermore, the flatness of the planarization layer can also be improved by adjusting the width of each signal line and the spacing between adjacent signal lines.

[0065] At least one embodiment of the present disclosure provides a display panel, the display panel including: a base substrate; an active layer, a gate, and a source / drain electrode layer stacked in order on the base substrate; and a planarization layer provided on a side of the source / drain electrode layer away from the base substrate, wherein the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the source / drain electrode layer and the active layer onto the base substrate; and the thickness of the source / drain electrode layer is greater than the thickness of the gate in a direction perpendicular to the main surface of the base substrate; and by designing the gate, the source / drain electrode layer, and the active layer to have the above structural relationship, the flatness of the planarization layer located on the source / drain electrode layer can be reduced, i.e., the surface of the planarization layer can be made flatter, thereby improving the display effect of the display panel.

[0066] For example, FIG. 1A is a schematic cross-sectional structure diagram of a display panel according to at least one embodiment of the present disclosure. As shown in FIG. 1A, the display panel 100 includes a base substrate 101, an active layer 102, a gate 103, and a source / drain electrode layer 104, which are sequentially stacked on the base substrate 101, and a planarization layer 105 provided on the side of the source / drain electrode layer 104 that is away from the base substrate 101. The orthogonal projection of the gate 103 onto the base substrate 101 is located within the orthogonal projection of the source / drain electrode layer 104 and the active layer 102 onto the base substrate 101. That is, the orthogonal projection of the source / drain electrode layer 104 onto the base substrate 101 covers the orthogonal projection of the gate 103 onto the base substrate 101, and the orthogonal projection of the active layer 102 onto the base substrate 101 covers the orthogonal projection of the gate 103 onto the base substrate 101. The orthogonal projection of the conductive layer 102 onto the base substrate 101 also covers the orthogonal projection of the gate 103 onto the base substrate 101, and the thickness of the source / drain electrode layer 104 is greater than the thickness of the gate 103 in a direction perpendicular to the main surface of the base substrate 101. The source / drain electrode layer 104 is provided to cover the gate 103, thereby reducing the problem of steps due to the difference in thickness between different metal layers and making it possible to maintain most of the planarization layer in a flat state at least in a position corresponding to the pixel opening region. Furthermore, the thickness of the source / drain electrode layer 104 is provided to be greater than the thickness of the gate 103, thereby further reducing the influence of steps due to the gate 103, which has a certain thickness, on the flatness of the planarization layer 105.

[0067] For example, the design in FIG. 1A can reduce the flatness of the planarization layer 105 located on the source / drain electrode layer 104, i.e., the orthogonal projection of the gate 103, which has the smallest orthogonal projection area, onto the base substrate 101 is located within the orthogonal projection of the source / drain electrode layer 104 onto the base substrate 101, and the source / drain electrode layer 104 is located directly above the gate 103 and covers the entire gate 103, thus making it possible to reduce the flatness of the planarization layer 105 corresponding to the pixel area.

[0068] For example, FIG. 2A is a schematic planar structure diagram of a display panel according to at least one embodiment of the present disclosure. Referring to FIGS. 1A and 2A together, the area of ​​the source / drain electrode layer 104 is larger than the area of ​​the gate 103, and the edges of the source / drain electrode layer 104 extend beyond the edges of the gate 103, i.e., the source / drain electrode layer 104 completely covers the gate 103, thereby minimizing the problem of the high flatness of the planarization layer 105 due to the presence of the gate 103.

[0069] For example, Figure 2B is a schematic planar view of the single active layer in Figure 2A, and Figure 2C is a schematic planar view of the active layer and gate in Figure 2A when they are overlapped. As shown in Figure 2B, the active layer 102 has a full-layer structure, including a rectangular shape on the left and a long shape on the right, which are connected to form an integrated structure. As shown in Figure 2C, in the planar structure in which the active layer 102 and gate 103 are overlapped, both of the two branches of the gate 103 overlap with the long shape of the active layer 102, and the portions of the gate 103 parallel to the two branches also overlap with the long shape of the active layer 102.

[0070] For example, as shown in FIG. 1A , a gate insulating layer 106 is provided between the active layer 102 and the gate 103, an interlayer insulating layer 107 is provided between the gate 103 and the source / drain electrode layer 104, the source / drain electrode layer 104 includes a first source / drain electrode 1041 and a second source / drain electrode 1042 arranged opposite each other, the first source / drain electrode 1041 is electrically connected to the active layer 102 via a first via structure 1081 that passes through the interlayer insulating layer 107 and the gate insulating layer 106 in that order, the orthogonal projection of the gate 103 onto the base substrate 101 is located within the orthogonal projection of the first source / drain electrode 1041 onto the base substrate 101, and the second source / drain electrode 1042 is electrically connected to the active layer 102 via a second via structure 1082 that passes through the interlayer insulating layer 107 and the gate insulating layer 106 in that order.

[0071] For example, the orthogonal projection of the gate, which has the smallest orthogonal projection area, onto the base substrate is located within the orthogonal projection of the source / drain electrode layer onto the base substrate, i.e., the source / drain electrode layer is directly above the gate and covers the entire gate, thus making it possible to reduce the flatness of the planarization layer corresponding to the pixel area.

[0072] 1A, the end of the first source / drain electrode 1041 away from the second source / drain electrode 1042 is electrically connected to the active layer 102 through a first via structure 1081. In this manner, the first source / drain electrode 1041 can completely cover the gate 103, thereby minimizing the problem of the planarization layer 105 becoming less flat due to the presence of the gate 103. In addition, the voltage retention capability of the drive transistor may be improved by increasing the area of ​​the source / drain electrode layer included in the storage capacitor.

[0073] In FIG. 1A, the second via structure 1082 is provided at a position corresponding to the edge of the second source / drain electrode 1042, and the first via structure 1081 is similarly provided at a position corresponding to the edge of the first source / drain electrode 1041, both being provided at the right edge; however, embodiments of the present disclosure are not limited to this; the first via structure 1081 may be provided at a position corresponding to the center of the first source / drain electrode 1041, and the second via structure 1082 may be provided at a position corresponding to the center of the second source / drain electrode 1042; the first via structure 1081 may be provided at the left edge of the first source / drain electrode 1041, and the second via structure 1082 may be provided at a position corresponding to the center of the second source / drain electrode 1042; or the first via structure 1081 may be provided at the left edge of the first source / drain electrode 1041, and the second via structure 1082 may be provided at the right edge of the second source / drain electrode 1042; and embodiments of the present disclosure are not limited to this.

[0074] For example, as shown in FIG. 1A , on the side of the active layer 102 close to the base substrate 101, a light-shielding layer 109 is further provided on the base substrate 101, a first insulating layer 110 is provided on the light-shielding layer 109, and a pixel definition layer 111 is provided on the side of the planarization layer 105 away from the base substrate 101, the pixel definition layer 111 includes body portions 111 a and opening regions 111 b between adjacent body portions 111 a, and one-color sub-pixels are respectively formed in the opening regions 111 b, i.e., the body portions 111 a separate adjacent sub-pixels.

[0075] For example, as shown in FIG. 1A , to further improve the flatness of the planarization layer, the contact position between the first source / drain electrode 1041 and the active layer 102 is adjusted, i.e., the position of the first via structure 1081 is optimized. The position of the electrical connection between the first electrode 112 and the first source / drain electrode 1041 is adjusted, i.e., the position of the third via structure 113 is optimized. This can increase the area of ​​the storage capacitor and further improve the voltage retention capability of the corresponding drive transistor. Furthermore, the design in FIG. 1A can also increase the electrode area of ​​the first source / drain electrode layer included in the storage capacitor, thereby improving the flatness of the planarization layer located on the source / drain electrode layer. The pixel circuit structure included in the display panel shown in FIG. 1A may be a 4T1C structure capable of internal compensation, and the drive transistor may be two thin film transistors connected in series.

[0076] For example, in at least one embodiment of the present disclosure, the display panel 100 further includes a plurality of data lines 114, which are disposed in the same layer as the source / drain electrode layer 104, and each of the plurality of data lines 114 is electrically connected to a corresponding second source / drain electrode 1042. For example, as shown in FIG. 2A , only one data line 114 is shown, and the data line 114 is electrically connected to the second source / drain electrode 1042 through a second via structure 1082, and the other data lines have the same connection relationship with the corresponding second source / drain electrode 1042, and a redundant description will be omitted here.

[0077] For example, as shown in FIG. 1A, the display panel 100 further includes a first electrode 112 arranged on the side of the planarization layer 105 away from the base substrate 101, the first electrode 112 being arranged in the opening region 111b, and the first electrode 112 being electrically connected to the first source-drain electrode 1041 through a third via structure 113 arranged in the planarization layer 105, thereby realizing the driving function of the driving transistor for the subpixel, and the portion of the first electrode 112 away from the edge of the second source-drain electrode 1042 being electrically connected to the first source-drain electrode 1041.

[0078] For example, providing the first source / drain electrode 1041 having the above structure is advantageous for improving the flatness of the planarization layer 105, i.e., reducing the roughness of the planarization layer 105, thereby improving the flatness of the first electrode 112 and the light-emitting layer, organic functional layer, etc., provided on the first electrode 112 and included in the light-emitting element, thereby improving the uniformity of the light emitted by the light-emitting element.

[0079] The first source / drain electrode functions as one electrode of the storage capacitor. The first source / drain electrode has an integral structure and a large area, allowing it to cover a large area of ​​the pixel region. The thickness of the first source / drain electrode exceeds 500 nm, thereby improving the flatness of the planarization layer. The larger the metal area of ​​the first source / drain electrode, the better the improvement in the flatness of the planarization layer. The planar shape of the first source / drain electrode may be rectangular, square, or irregular, as long as it matches the planar shape of the pixel region, and the embodiments of the present disclosure are not limited thereto. For example, in one example, the planar area of ​​the first source / drain electrode is larger than the planar area of ​​the gate, the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the first source / drain electrode layer onto the base substrate, and the edge of the first source / drain electrode layer exceeds the edge of the gate.

[0080] Furthermore, FIG. 1A shows only a portion of the layer structure of the display panel, and does not show all of the layer structure of the display panel. For structures not shown, reference may be made to conventional structures, and the embodiments of the present disclosure are not limited thereto.

[0081] For example, the formation of the display panel 100 in FIG. 1A includes the following process steps: providing a base substrate 101, sequentially depositing a first buffer layer thin film and a second buffer layer thin film on the base substrate 101, performing a patterning process to form a buffer layer, depositing a monocrystalline silicon thin film on the buffer layer, performing a dehydrogenation, hydrogen fluoride cleaning and excimer laser annealing process to form a polycrystalline silicon layer, then performing an etching process under mask shielding to complete the first masking process, doping the polycrystalline silicon layer with boron trifluoride, then cleaning with hydrogen fluoride, performing a second masking process on the polycrystalline silicon layer under mask, then doping with sulfur hexafluoride, then performing a third masking process on the polycrystalline silicon layer, then nitrogen doping, then depositing a gate insulating layer thin film, depositing a gate material on the gate insulating layer thin film, then performing a fourth masking process on the gate material. a masking process, etching to form a gate, further depositing an interlayer insulating film material on the gate, a fifth masking process, etching to form an interlayer insulating layer, depositing a source / drain electrode layer thin film, a sixth masking process, etching to form a source / drain electrode layer, depositing a passivation layer on the source / drain electrode layer, a seventh masking process, etching to form a passivation layer, depositing a planarization layer thin film on the passivation layer, an eighth masking process to form a planarization layer, depositing a first electrode material on the planarization layer, then performing a ninth patterning process on the first electrode material to form a first electrode, then depositing a pixel-defining layer thin film on the first electrode, and performing a tenth masking process on the pixel-defining layer thin film to form a pixel-defining layer. That is, the entire manufacturing process includes 10 masking processes.

[0082] 1A , the light-shielding layer 109 has a thickness of 2510 angstroms and is made of molybdenum metal. The first buffer layer has a thickness of 500 angstroms and the second buffer layer has a thickness of 1100 angstroms, and both the first buffer layer and the second buffer layer are made of silicon oxide. The active layer 102 has a thickness of 500 angstroms and is made of nitrogen-containing low-temperature polycrystalline silicon. The gate insulating layer 106 has a thickness of 1100 angstroms and is made of silicon oxide. The gate 103 has a thickness of 2510 angstroms and is made of molybdenum metal. The interlayer insulating layer 107 has a thickness of 5600 angstroms and is made of silicon oxide or silicon nitride. The source / drain electrode layer 104 has a thickness of 7000 angstroms and includes a three-layer stack structure, i.e., two titanium metal layers sandwiched between one aluminum metal layer, each 500 angstroms thick, and the intermediate aluminum metal layer having a thickness of 6000 angstroms. An insulating layer on the source / drain electrode layer 104 has a thickness of 4460 angstroms and is made of silicon oxynitride. A planarization layer 105 on the insulating layer has a thickness of 49000 angstroms and is made of a photocurable resin material. A first electrode 112 is provided on the planarization layer 105 and has a thickness of 1660 angstroms. A pixel definition layer 111 is provided on the first electrode 112 and has a thickness of 10900 angstroms and is made of an organic insulating material. A black matrix is ​​disposed on the pixel definition layer 111, the black matrix having a thickness of 10,600 angstroms and made of a black resin material. The display panel further includes red, green, and blue light-emitting layers, each having a thickness of 25,800 angstroms and made of an organic light-emitting material. The display panel further includes an optical adhesive, the optical adhesive having a thickness of 80,000 angstroms.

[0083] For example, as can be seen from the above example, the thickness of the source / drain metal layer is large, and the source / drain metal layer can reduce the non-uniformity and unevenness of the thin film of the wiring and pixel structure on the side closest to the base substrate, thereby improving the flatness of the planarization layer located on the side of the source / drain electrode layer away from the base substrate.

[0084] For example, FIG. 1B is a cross-sectional structural schematic diagram of another display panel according to at least one embodiment of the present disclosure. As shown in FIG. 1B , the display panel 100 includes a base substrate 101, an active layer 102, a gate 103, and a source / drain electrode layer 104, which are sequentially stacked on the base substrate 101, and a planarization layer 105 provided on the side of the source / drain electrode layer 104 away from the base substrate 101. The orthogonal projection of the gate 103 onto the base substrate 101 is located within the orthogonal projection of the source / drain electrode layer 104 and the active layer 102 onto the base substrate 101. That is, the orthogonal projection of the source / drain electrode layer 104 onto the base substrate 101 covers the orthogonal projection of the gate 103 onto the base substrate 101. The orthogonal projection of the active layer 102 onto the base substrate 101 also covers the orthogonal projection of the gate 103 onto the base substrate 101, and in the direction perpendicular to the main surface of the base substrate 101, the thickness of the source / drain electrode layer 104 is greater than the thickness of the gate 103, and the source / drain electrode layer 104 is arranged to cover the gate 103, thereby reducing the problem of steps caused by thickness differences between different metal layers and making it possible to maintain a large portion of the planarization layer in a flat state at least at the position corresponding to the pixel opening region, and furthermore, the thickness of the source / drain electrode layer 104 is greater than the thickness of the gate 103, thereby further reducing the impact of steps caused by the gate 103, which has a certain thickness, on the flatness of the planarization layer 105.

[0085] 1B , an end of the first source-drain electrode 1041 adjacent to the second source-drain electrode 1042 is electrically connected to the active layer 102 through a first via structure 1081, which penetrates the gate insulating layer 106 and the interlayer insulating layer 107. The first electrode 112 is electrically connected to the first source-drain electrode 1041 through a third via structure 113 provided in the planarization layer 105, thereby realizing the driving function of the driving transistor for the subpixel, and the intermediate portion of the first electrode 112 is electrically connected to the first source-drain electrode 1041.

[0086] Note that Figure 1B shows two branches of gate 103, and the two branches of the gate are connected to each other. In the cross-sectional view shown in Figure 1B, the branch of gate 103 located between the first source-drain electrode 1041 and the second source-drain electrode 1042 is not covered by the first source-drain electrode 1041. However, in the plan view shown in Figure 2A, the orthogonal projection of the branch of gate 103 onto the base substrate 101 is located within the orthogonal projection of the first source-drain electrode 1041 onto the base substrate 101, and the orthogonal projection of the branch of gate 103 onto the base substrate 101 is also located within the orthogonal projection of the active layer 102 onto the base substrate 101.

[0087] 3 is a schematic planar structure diagram of a subpixel and corresponding source / drain electrode layers according to at least one embodiment of the present disclosure, and FIG. 4 is a schematic cross-sectional structure diagram of a subpixel and corresponding source / drain electrode layers according to at least one embodiment of the present disclosure. As shown in FIG. 3, the display panel 100 includes a plurality of subpixels 120, each of which includes a first color subpixel 121, a second color subpixel 122, and a third color subpixel 123 that are arranged adjacent to each other. As also shown in FIG. 2A, each of the subpixels 120 corresponds to one data line 114. The orthogonal projection of the first source / drain electrode 1041a corresponding to the first color subpixel 121 onto the base substrate 101 has a first metal area S M1 and the orthogonal projection of the first source-drain electrode 1041b corresponding to the second color subpixel 122 onto the base substrate 101 has a second metal area S M2The orthogonal projection of the first source-drain electrode 1041c corresponding to the third color subpixel 123 onto the base substrate 101 has a third metal area S M3 and the first metal area S M1 is the area of ​​the second metal S M2 The second metal area S is M2 is the third metal area S M3 That is, the areas of the first source-drain electrodes 1041 corresponding to the first color sub-pixels 121, the second color sub-pixels 122, and the third color sub-pixels 123 that emit light of different colors are different. M1 is the area of ​​the second metal S M2 The second metal area S is less than M2 is the third metal area S M3 is less than.

[0088] In an AMOLED display device, the red, green, and blue light-emitting materials have different light-emitting efficiencies and lifetimes, so that the red subpixel driving circuit that drives the red subpixels to emit light, the green subpixel driving circuit that drives the green subpixels to emit light, and the blue subpixel driving circuit that drives the blue subpixels to emit light in the pixel array have different storage capacitor areas, and / or the red subpixel driving transistor that drives the red subpixels to emit light, the green subpixel driving transistor that drives the green subpixels to emit light, and the blue subpixel driving transistor that drives the blue subpixels to emit light all have different sizes and areas, so that different driving currents can be supplied to the red, green, and blue light-emitting materials, respectively, and different storage capacitances can be provided when the red, green, and blue subpixel driving transistors maintain different driving currents. For example, currently, the lifetime of a blue AMOLED is shorter than both the lifetimes of the red and green AMOLEDs. Therefore, it is possible to achieve desired color characteristics, such as white balance, by reducing the driving current of the blue subpixel driving transistor and then increasing the light-emitting area of ​​the blue subpixel. For example, the first color sub-pixel 121, the second color sub-pixel 122, and the third color sub-pixel 123 may be red, green, and blue sub-pixels, respectively.

[0089] 3 shows a first color subpixel 121, a second color subpixel 122, and a third color subpixel 123 and their internal storage capacitors. Each storage capacitor includes two opposing layers of thin metal film electrodes and one or more layers of insulating medium. The area of ​​the storage capacitor is defined as the area of ​​one of the layers of thin metal film electrodes. For example, the two opposing layers of thin metal film electrodes included in the storage capacitor may be a first source / drain electrode and a gate. For example, the area of ​​the thin metal film electrode away from the base substrate (first source / drain electrode) is selected as the area of ​​the storage capacitor, or the area of ​​the thin metal film electrode (first source / drain electrode) close to the planarization layer is selected as the area of ​​the storage capacitor.

[0090] For example, as shown in FIG. 4 , the display panel 100 includes a first color subpixel driving circuit 124, a second color subpixel driving circuit 125, and a third color subpixel driving circuit 126 arranged in sequence on a base substrate 101. The first color subpixel driving circuit 124 includes a first source-drain electrode 1041a corresponding to the first color subpixel 121, the second color subpixel driving circuit 125 includes a first source-drain electrode 1041b corresponding to the second color subpixel 122, and the third color subpixel driving circuit 126 includes a first source-drain electrode 1041c corresponding to the third color subpixel 123.

[0091] The embodiments of the present disclosure improve the flatness of the planarization layer by adjusting the ratio between the area of ​​each subpixel and the area of ​​the first source / drain electrode corresponding to each subpixel.

[0092] For example, the area S of the storage capacitor m and the area of ​​the pixel region S p The ratio of the area to the area is defined as the area ratio.

number

[0093] The area of ​​the pixel region S p includes the area of ​​the storage capacitor but does not include the wiring area of ​​each signal line.

[0094] Furthermore, the metal thin film electrode away from the base substrate of the storage capacitor may be a first source / drain electrode, and a planarization layer covers the first source / drain electrode, and the planarization layer may or may not be in direct contact with the first source / drain electrode.

number

number

[0095] For example, in one example, the area ratio F m1 is 62.3333, and the flatness F of the planarization layer corresponding to the first color subpixel p1 is 1.2546, and the area ratio of the second color subpixel F m2 is 59.2626, and the flatness F of the planarization layer corresponding to the second color subpixel p2 is 1.4906, and the area ratio F m3 is 39.6856, and the flatness F of the planarization layer corresponding to the third color subpixel p3 is 2.0768.

[0096] For example, after fitting, it was found that the flatness of the planarization layer corresponding to the subpixels of different colors increases with the decrease of the area ratio of the subpixels. After fitting various methods, it was found that the accuracy of polynomial fitting was higher than that of linear fitting, higher than that of exponential fitting, higher than that of logarithmic fitting, and the polynomial formed after polynomial fitting was

number

number

[0097] For example, in one example, the multiple subpixels 120 are arranged in an array. In the row direction in which the subpixels are arranged, i.e., the direction along the X-axis in FIG. 3 , the width of the first source-drain electrode 1041a corresponding to the first-color subpixel 121 is equal to or smaller than the width of the first source-drain electrode 1041b corresponding to the adjacent second-color subpixel 122, and the width of the first source-drain electrode 1041b corresponding to the second-color subpixel 122 is equal to or smaller than the width of the first source-drain electrode 1041c corresponding to the adjacent third-color subpixel 123.

[0098] For example, in one example, the subpixels 120 are arranged in an array. In the row direction in which the subpixels are arranged, i.e., the direction along the X-axis in FIG. 4 , the overall length of the first color subpixel drive circuit 124 is less than the overall length of the second color subpixel drive circuit 125 and less than the overall length of the third color subpixel drive circuit 126.

[0099] The direction parallel to the Y axis is the column direction in which the sub-pixels are arranged, and the direction parallel to the Z axis is the direction perpendicular to the main surface of the base substrate 101.

[0100] For example, the first color subpixel 121, the second color subpixel 122, and the third color subpixel 123 are red, green, and blue subpixels, respectively, and the first color subpixel 121 has a first subpixel area S P1 and the second color subpixel 122 has a second subpixel area S P2 and the third color subpixel 123 has a third subpixel area S P3 and

number

[0101] For example, in a display panel according to at least one embodiment of the present disclosure, the area ratio F1 of the first source-drain electrode 1041a corresponding to the first color subpixel 121, the area ratio F2 of the first source-drain electrode 1041b corresponding to the second color subpixel 122, and the area ratio F3 of the first source-drain electrode 1041c corresponding to the third color subpixel 123 are 55%, 50%, and 30%, respectively.

[0102] For example, in one example, different positions corresponding to the planarization layer 105 have different flatness, and the flatness of the planarization layer 105 increases with the decrease in the area ratio of the first source-drain electrode 1041 corresponding to each subpixel 120, that is, the flatness of the planarization layer 105 corresponding to the red subpixel, the green subpixel, and the blue subpixel is different.

[0103] For example, in one example, the first flatness F of the planarization layer 105 corresponding to the first color subpixel 121 P1 is the second flatness F of the planarization layer 105 corresponding to the second color subpixel 122 P2 and the second flatness F of the planarization layer 105 corresponding to the second-color subpixel 122 is equal to or less than the second flatness F P2 is the third flatness F of the planarization layer 105 corresponding to the third color subpixel 123 P3 The following is the result.

[0104] For example, in one example, the first flatness is

number

number

number

[0105] For example, in one example, the formula

number

[0106] For example, the equation obtained by performing polynomial fitting on the average flatness x of the planarization layer 105 and the area ratio y of the first source-drain electrode 1041 corresponding to each sub-pixel 120 is as follows:

number

[0107] For example, the equation obtained by performing polynomial fitting on the average flatness x of the flattening layer 105 and the area ratio y of the first source / drain electrode 1041 corresponding to each sub-pixel 120 is:

number

number

[0108] For example, in one example, the first flatness F P1 , second flatness F P2 and third flatness F P3 The magnitudes are 1.5%, 2% and 2.5%, respectively.

[0109] 5 is a schematic planar structure diagram of another subpixel and corresponding source / drain electrode layer according to at least one embodiment of the present disclosure, and FIG. 6 is a schematic cross-sectional structure diagram of another subpixel and corresponding source / drain electrode layer according to at least one embodiment of the present disclosure. As shown in FIG. 5, the display panel 100 includes a plurality of subpixels 120, each of which includes a second color subpixel 122, a first color subpixel 121, and a third color subpixel 123 that are arranged adjacent to each other. As also shown in FIG. 2A, each of the subpixels 120 corresponds to one data line 114. The orthogonal projection of the first source / drain electrode 1041b corresponding to the second color subpixel 122 onto the base substrate 101 has a second metal area S M2The orthogonal projection of the first source-drain electrode 1041a corresponding to the first color subpixel 121 onto the base substrate 101 has a first metal area S M1 The orthogonal projection of the first source-drain electrode 1041c corresponding to the third color subpixel 123 onto the base substrate 101 has a third metal area S M3 and the second metal area S M2 is the area of ​​the first metal S M1 The first metal area S is M1 is the third metal area S M3 That is, the areas of the first source-drain electrodes 1041 corresponding to the first color sub-pixels 121, the second color sub-pixels 122, and the third color sub-pixels 123 that emit light of different colors are different. M2 is the area of ​​the first metal S M1 The first metal area S is less than M1 is the third metal area S M3 is less than.

[0110] In an AMOLED display device, the red, green, and blue light-emitting materials have different light-emitting efficiencies and lifetimes, so that the red subpixel driving circuit that drives the red subpixels to emit light, the green subpixel driving circuit that drives the green subpixels to emit light, and the blue subpixel driving circuit that drives the blue subpixels to emit light in the pixel array have different storage capacitor areas, and / or the red subpixel driving transistor that drives the red subpixels to emit light, the green subpixel driving transistor that drives the green subpixels to emit light, and the blue subpixel driving transistor that drives the blue subpixels to emit light all have different sizes and areas, so that different driving currents can be supplied to the red, green, and blue light-emitting materials, respectively, and different storage capacitances can be provided when the red, green, and blue subpixel driving transistors maintain different driving currents. For example, currently, the lifetime of a blue AMOLED is shorter than both the lifetimes of the red and green AMOLEDs. Therefore, it is possible to achieve desired color characteristics, such as white balance, by reducing the driving current of the blue subpixel driving transistor and then increasing the light-emitting area of ​​the blue subpixel. For example, the first color sub-pixel 121, the second color sub-pixel 122, and the third color sub-pixel 123 may be red, green, and blue sub-pixels, respectively.

[0111] 5 shows a first color subpixel 121, a second color subpixel 122, and a third color subpixel 123 and their internal storage capacitors. Each storage capacitor includes two opposing layers of thin metal film electrodes and one or more layers of insulating medium. The area of ​​the storage capacitor is defined as the area of ​​one of the layers of thin metal film electrodes. For example, the two opposing layers of thin metal film electrodes included in the storage capacitor may be a first source / drain electrode and a gate. For example, the area of ​​the thin metal film electrode away from the base substrate (first source / drain electrode) is selected as the area of ​​the storage capacitor, or the area of ​​the thin metal film electrode (first source / drain electrode) close to the planarization layer is selected as the area of ​​the storage capacitor.

[0112] For example, as shown in FIG. 6 , the display panel 100 includes a second color subpixel driving circuit 125, a first color subpixel driving circuit 124, and a third color subpixel driving circuit 126, which are sequentially arranged on a base substrate 101. The second color subpixel driving circuit 125 includes a first source-drain electrode 1041b corresponding to the second color subpixel 122, the first color subpixel driving circuit 124 includes a first source-drain electrode 1041a corresponding to the first color subpixel 121, and the third color subpixel driving circuit 126 includes a first source-drain electrode 1041c corresponding to the third color subpixel 123.

[0113] The embodiments of the present disclosure improve the flatness of the planarization layer by adjusting the ratio between the area of ​​each subpixel and the area of ​​the first source / drain electrode corresponding to each subpixel.

[0114] For example, the area S of the storage capacitor m and the area of ​​the pixel region S p The ratio of the area to the area is defined as the area ratio.

number

[0115] The area of ​​the pixel region S p includes the area of ​​the storage capacitor but does not include the wiring area of ​​each signal line.

[0116] Furthermore, the metal thin film electrode away from the base substrate of the storage capacitor may be a first source / drain electrode, and a planarization layer covers the first source / drain electrode, and the planarization layer may or may not be in direct contact with the first source / drain electrode.

number

number

[0117] For example, in one example, the area ratio F m2 is 62.3333, and the flatness F of the planarization layer corresponding to the second color subpixel p2 is 1.2546, and the area ratio of the first color subpixel F m1 is 59.2626, and the flatness F of the planarization layer corresponding to the first color subpixel p1 is 1.4906, and the area ratio F m3 is 39.6856, and the flatness F of the planarization layer corresponding to the third color subpixel p3 is 2.0768.

[0118] For example, after fitting, it was found that the flatness of the planarization layer corresponding to the subpixels of different colors increases with the decrease in the area ratio of the subpixels. After fitting various methods, it was found that the accuracy of polynomial fitting was higher than that of linear fitting, higher than that of exponential fitting, higher than that of logarithmic fitting, and the polynomial formed after polynomial fitting was

number

number

[0119] 5 , the width of the first source-drain electrode 1041b corresponding to the second-color subpixel 122 is equal to or less than the width of the first source-drain electrode 1041a corresponding to the adjacent first-color subpixel 121, and the width of the first source-drain electrode 1041a corresponding to the first-color subpixel 121 is equal to or less than the width of the first source-drain electrode 1041c corresponding to the adjacent third-color subpixel 123.

[0120] For example, in one example, the plurality of subpixels 120 are arranged in an array. In the row direction in which the subpixels are arranged, i.e., the direction along the X-axis in FIG. 6 , the overall length of the second-color subpixel drive circuit 125 is less than the overall length of the first-color subpixel drive circuit 124, and the overall length of the first-color subpixel drive circuit 124 is less than the overall length of the third-color subpixel drive circuit 126.

[0121] The direction parallel to the Y axis is the column direction in which the sub-pixels are arranged, and the direction parallel to the Z axis is the direction perpendicular to the main surface of the base substrate 101.

[0122] For example, the first color subpixel 121, the second color subpixel 122, and the third color subpixel 123 are red, green, and blue subpixels, respectively, and the first color subpixel 121 has a first subpixel area S P1 and the second color subpixel 122 has a second subpixel area S P2 and the third color subpixel 123 has a third subpixel area S P3 and

number

[0123] For example, in a display panel according to at least one embodiment of the present disclosure, the area ratio F2 of the first source-drain electrode 1041b corresponding to the second color subpixel 122, the area ratio F1 of the first source-drain electrode 1041a corresponding to the first color subpixel 121, and the area ratio F3 of the first source-drain electrode 1041c corresponding to the third color subpixel 123 are 55%, 50%, and 30%, respectively.

[0124] For example, in one example, different positions corresponding to the planarization layer 105 have different flatness, and the flatness of the planarization layer 105 increases with the decrease in the area ratio of the first source-drain electrode 1041 corresponding to each subpixel 120, that is, the flatness of the planarization layer 105 corresponding to the red subpixel, the green subpixel, and the blue subpixel is different.

[0125] For example, in one example, the second flatness F of the planarization layer 105 corresponding to the second color subpixel 122 P2 is the first flatness F of the planarization layer 105 corresponding to the first color subpixel 121 P1the first flatness F of the planarization layer 105 corresponding to the first-color subpixel 121 is less than or equal to P1 is the third flatness F of the planarization layer 105 corresponding to the third color subpixel 123 P3 The following is the result.

[0126] For example, in one example, the first flatness is

number

number

number

[0127] For example, in one example, the formula

number

[0128] For example, the equation obtained by performing polynomial fitting on the average flatness x of the planarization layer 105 and the area ratio y of the first source-drain electrode 1041 corresponding to each sub-pixel 120 is as follows:

number

[0129] For example, the equation obtained by performing polynomial fitting on the average flatness x of the flattening layer 105 and the area ratio y of the first source / drain electrode 1041 corresponding to each sub-pixel 120 is:

number

number

[0130] For example, in one example, the second flatness F P2 , first flatness F P1 and third flatness F P3 The magnitudes are 1.5%, 2% and 2.5%, respectively.

[0131] 7 is a schematic planar structure diagram of yet another display panel according to at least one embodiment of the present disclosure. As shown in FIG. 7, the display panel 100 further includes a power supply voltage signal line 127, which is provided on the side of the third color subpixel 123 away from the second color subpixel 122. The power supply voltage signal line 127 is not provided around the first color subpixel 121 and the second color subpixel 122.

[0132] The pixel region corresponding to the third-color subpixel 123 has the largest area, and the width of the power supply voltage signal line 127 is large in the direction in which the subpixels are arranged along the X-axis. Therefore, the power supply voltage signal line 127 is suitable for being provided at a position corresponding to the third-color subpixel 123, which has a large area.

[0133] For example, as shown in FIG. 7, the plurality of subpixels 120 include a first color subpixel 121, a second color subpixel 122, and a third color subpixel 123 arranged adjacent to each other in the first direction X, and the first color subpixel 121, the second color subpixel 122, and the third color subpixel 123 correspond to the first source-drain electrode 1041a, the first source-drain electrode 1041b, and the first source-drain electrode 1041c, respectively. The first source-drain electrode 1041a is electrically connected to the active layer 102 through a first via structure 1081a that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106, the first source-drain electrode 1041b is electrically connected to the active layer 102 through a first via structure 1081b that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106, and the first source-drain electrode 1041c is electrically connected to the active layer 102 through a first via structure 1081c that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106. The first color subpixel 121, the second color subpixel 122, and the third color subpixel 123 correspond to the second source-drain electrode 1042a, the first source-drain electrode 1042b, and the first source-drain electrode 1042c, respectively. The second source-drain electrode 1042a is electrically connected to the data line 114a through a second via structure 1082a that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106, the second source-drain electrode 1041b is electrically connected to the data line 114b through a second via structure 1082b that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106, and the second source-drain electrode 1041c is electrically connected to the data line 114c through a second via structure 1082c that sequentially penetrates the interlayer insulating layer 107 and the gate insulating layer 106. The gates 103 corresponding to the first, second, and third color subpixels 121, 122, and 123 each include two branch structures, which are connected to each other. The planar areas of the first source-drain electrodes 1041a, 1041b, and 1041c corresponding to the first color subpixel 121, the second color subpixel 122, and the third color subpixel 123, respectively, increase in order.

[0134] For example, in FIG. 7, the power supply voltage signal line 127, the data line 114a corresponding to the first color subpixel 121, the data line 114b corresponding to the second color subpixel 122, and the data line 114c corresponding to the third color subpixel 123 all have a two-layer structure that is stacked.

[0135] For example, FIG. 8A is a schematic planar structure diagram of a power supply voltage signal line according to at least one embodiment of the present disclosure. As shown in FIG. 8A , the power supply voltage signal line 127 and the data line 114 connected to the third color subpixel 123 are respectively arranged on opposite sides of the third color subpixel 123, the power supply voltage signal line 127 and the data line 114 connected to the third color subpixel 123 are arranged opposite each other, and in the direction from the power supply voltage signal line 127 to the data line 114 connected to the third color subpixel 123, the width of the first power supply voltage signal line 127a is larger than the width of the second power supply voltage signal line 127b.

[0136] In addition, in FIG. 8A, the second power supply voltage signal line 127b and the first power supply voltage signal line 127a do not overlap at the upper edge position, and in other positions, the orthogonal projection of the second power supply voltage signal line 127b onto the base substrate 101 is located within the orthogonal projection of the first power supply voltage signal line 127a onto the base substrate 101.

[0137] For example, as shown in FIG. 8A , the edge of the second power supply voltage signal line 127b away from the data line 114 connected to the third-color subpixel 123 is aligned with the edge of the first power supply voltage signal line 127a away from the data line 114 connected to the third-color subpixel 123, and the edge of the second power supply voltage signal line 127b close to the data line 114 connected to the third-color subpixel 123 is located on the side of the edge of the first power supply voltage signal line 127a close to the data line 114 connected to the third-color subpixel 123 that is away from the data line 114 connected to the third-color subpixel 123.

[0138] For example, the width of the first power supply voltage signal line 127a is two to four times the width of the second power supply voltage signal line 127b, e.g., two, three, or four times the width of the second power supply voltage signal line 127b, but the embodiments of the present disclosure are not limited thereto.

[0139] For example, in one example, the width of the first power supply voltage signal line 127a is 10 microns to 30 microns, and the width of the second power supply voltage signal line 127b is 2 microns to 20 microns. For example, in one example, the width of the first power supply voltage signal line 127a is 10 microns and the width of the second power supply voltage signal line 127b is 5 microns, in another example, the width of the first power supply voltage signal line 127a is 16 microns and the width of the second power supply voltage signal line 127b is 8 microns, in yet another example, the width of the first power supply voltage signal line 127a is 22 microns and the width of the second power supply voltage signal line 127b is 11 microns, and in yet another example, the width of the first power supply voltage signal line 127a is 30 microns and the width of the second power supply voltage signal line 127b is 15 microns, that is, the width of the first power supply voltage signal line 127a is twice the width of the second power supply voltage signal line 127b.

[0140] For example, in one example, the width of the first power supply voltage signal line 127a is 12 microns and the width of the second power supply voltage signal line 127b is 4 microns; in another example, the width of the first power supply voltage signal line 127a is 15 microns and the width of the second power supply voltage signal line 127b is 5 microns; and in yet another example, the width of the first power supply voltage signal line 127a is 30 microns and the width of the second power supply voltage signal line 127b is 10 microns, that is, the width of the first power supply voltage signal line 127a is three times the width of the second power supply voltage signal line 127b.

[0141] For example, in one example, the width of the first power supply voltage signal line 127a is 12 microns and the width of the second power supply voltage signal line 127b is 3 microns; in another example, the width of the first power supply voltage signal line 127a is 16 microns and the width of the second power supply voltage signal line 127b is 4 microns; in yet another example, the width of the first power supply voltage signal line 127a is 20 microns and the width of the second power supply voltage signal line 127b is 5 microns; in yet another example, the width of the first power supply voltage signal line 127a is 24 microns and the width of the second power supply voltage signal line 127b is 6 microns; and in yet another example, the width of the first power supply voltage signal line 127a is 28 microns and the width of the second power supply voltage signal line 127b is 7 microns, that is, the width of the first power supply voltage signal line 127a is four times the width of the second power supply voltage signal line 127b.

[0142] 9 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure, in which the power supply voltage signal line 127 includes a first power supply voltage signal line 127a and a second power supply voltage signal line 127b that are stacked, the first power supply voltage signal line 127a being provided in the same layer as the source / drain electrode layer 1041, the second power supply voltage signal line 127b being provided in the same layer as the gate 103, the first power supply voltage signal line 127a having an integral structure, and the second power supply voltage signal line 127b including a notch. The notch in the second power supply voltage signal line 127b allows current to flow through the entire first power supply voltage signal line 127a, thereby increasing the area through which the current flows.

[0143] For example, as shown in FIG. 9, the stacked first power supply voltage signal line 127a and second power supply voltage signal line 127b can reduce the resistance of the power supply voltage signal line 127, and the second power supply voltage signal line 127b includes a notch, thereby achieving electrical continuity with the first power supply voltage signal line 127a in the upper layer.

[0144] For example, as shown in FIG. 9, the first power supply voltage signal line 127a is provided in the same layer as the source / drain electrode layer 1041, and the second power supply voltage signal line 127b is provided in the same layer as the gate 103. Therefore, even if the first power supply voltage signal line 127a and the second power supply voltage signal line 127b have a two-layer structure, the degree of the step formed does not increase, and a new step is simply formed in a different position, so that the flatness of the flattening layer is not affected.

[0145] For example, the first power supply voltage signal line 127a has a full-layer structure, and the width of the first power supply voltage signal line 127a is larger, which allows the current flow area to be increased, thereby improving the operating efficiency of the power supply voltage signal line 127.

[0146] 9 , the orthogonal projection of the main body 111a, the orthogonal projection of the first power supply voltage signal line 127a, and the orthogonal projection of the second power supply voltage signal line 127b included in the pixel definition layer 111 onto the base substrate 101 at least partially overlap each other. The main body 111a, the first power supply voltage signal line 127a, and the second power supply voltage signal line 127b of the pixel definition layer 111 are stacked, which can raise the main body 111a and provide a larger space for forming the associated structures of the sub-pixels.

[0147] For example, as shown in both Figures 7 and 8A, each of the multiple data lines 114 includes a first sub-data line 114a and a second sub-data line 114b stacked together, the first sub-data line 114a is arranged in the same layer as the source / drain electrode layer 104, the second sub-data line 114b is arranged in the same layer as the gate 103, the first sub-data line 114a has an integral structure, and the second sub-data line 114b includes a notch, and each data line 114 is electrically connected to the first source / drain electrode 1041 of the corresponding sub-pixel 120 via the first sub-data line 114a.

[0148] For example, as shown in FIG. 7, the stacked first sub-data line 114a and second sub-data line 114b can reduce the resistance of the data line 114, and the second sub-data line 114b includes a notch, thereby realizing electrical conduction of the first sub-data line 114a in the upper layer.

[0149] For example, as shown in FIG. 7, the first sub-data line 114a is provided in the same layer as the source-drain electrode layer 1041, and the second sub-data line 114b is provided in the same layer as the gate 103. Therefore, even if the first sub-data line 114a and the second sub-data line 114b have a two-layer structure, the degree of the step formed does not increase, and a new step is simply formed in a different position, so that the flatness of the flattening layer is not affected.

[0150] For example, the first sub-data line 114a has a full-layer structure and is wider, so that the current flow area can be increased, thereby improving the operation efficiency of the data line 114.

[0151] For example, as shown in FIG. 7, in the direction of the data line 114 connected from the power supply voltage signal line 127 to the third color subpixel 123, the width of the first sub-data line 114a is greater than the width of the second sub-data line 114b.

[0152] In addition, the structure in which the first sub-data line 114a and the second sub-data line 114b are stacked may be the data line of the corresponding third color sub-pixel 123, or the data line of the corresponding first color sub-pixel 121 or second color sub-pixel 122, and the embodiments of the present disclosure are not limited thereto.

[0153] For example, as shown in FIG. 7, on the same data line 114, the edge of the second sub-data line 114b away from the sub-pixel 120 connected to the data line 114 on which it is located is aligned with the edge of the corresponding first sub-data line 114a away from the sub-pixel 120 electrically connected to it, and the edge of the second sub-data line 114b close to the sub-pixel 120 connected to the data line 114 on which it is located is located on the side away from the corresponding sub-pixel 120 of the edge of the corresponding first sub-data line 114a close to the sub-pixel 120 electrically connected to it.

[0154] For example, in a display panel according to at least one embodiment of the present disclosure, for the same data line 114, the width of the first sub-data line 114a is two to four times the width of the second sub-data line 114b, for example, the width of the first sub-data line 114a is two, three or four times the width of the second sub-data line 114b.

[0155] For example, the width of the first sub-data line 114a is 2 microns to 20 microns, and the width of the second sub-data line 114b is 2 microns to 10 microns in the same data line 114. This range can reduce the resistance of the data line 114 and increase the current flow area in the data line 114.

[0156] For example, in one example, the width of the first sub-data line 114a is 4 microns and the width of the second sub-data line 114b is 2 microns; in another example, the width of the first sub-data line 114a is 10 microns and the width of the second sub-data line 114b is 5 microns; in yet another example, the width of the first sub-data line 114a is 16 microns and the width of the second sub-data line 114b is 8 microns; and in yet another example, the width of the first sub-data line 114a is 20 microns and the width of the second sub-data line 114b is 10 microns, thereby making the width of the first sub-data line 114a twice that of the second sub-data line 114b.

[0157] For example, in one example, the width of the first sub-data line 114a is 6 microns and the width of the second sub-data line 114b is 2 microns; in another example, the width of the first sub-data line 114a is 12 microns and the width of the second sub-data line 114b is 4 microns; in yet another example, the width of the first sub-data line 114a is 15 microns and the width of the second sub-data line 114b is 5 microns; and in yet another example, the width of the first sub-data line 114a is 18 microns and the width of the second sub-data line 114b is 6 microns, thereby making the width of the first sub-data line 114a three times that of the second sub-data line 114b.

[0158] For example, in one example, the width of the first sub-data line 114a is 8 microns and the width of the second sub-data line 114b is 2 microns; in another example, the width of the first sub-data line 114a is 12 microns and the width of the second sub-data line 114b is 3 microns; in yet another example, the width of the first sub-data line 114a is 16 microns and the width of the second sub-data line 114b is 4 microns; and in yet another example, the width of the first sub-data line 114a is 20 microns and the width of the second sub-data line 114b is 5 microns, thereby making the width of the first sub-data line 114a four times the width of the second sub-data line 114b.

[0159] For example, the first sub-data line 114a has an inverted "L" shape in plan view, and is electrically connected to the second source / drain electrode 1042 via a horizontal line extending from the vertical line.

[0160] For example, as shown in FIG. 7, the power supply voltage signal line 127 and the data line 114 are both configured as a two-layer structure, thereby optimizing the pixel areas of the first color subpixel, the second color subpixel, and the third color subpixel and the area corresponding to the first source / drain electrode of the storage capacitor. On the premise that the power supply voltage signal line 127 and the data line 114 are both configured as a two-layer structure, the thickness of the planarization layer is measured, and the obtained related data is shown in Table 1 below.

[0161] [Table 1]

[0162] For example, in FIG. 7, the relationship between the flatness of the flattening layer and the ratio of the area of ​​the first source / drain electrode included in the storage capacitor to the pixel area satisfies the following formula:

[0163] Polynomial fitting:

number

number

number

number

number

[0164] For example, R 2 is a number between 0 and 1, and is the R of the trend line. 2 When R is equal to or close to 1, the reliability is highest, and conversely, the reliability is low. 2 is also called the coefficient of determination. R 2 The calculation method is R 2 = regression sum of squares (ssreg) / total sum of squares (sstotal), regression sum of squares = total sum of squares - residual sum of squares (ssresid), and polynomial accuracy > linear accuracy > exponential accuracy > logarithmic accuracy > power fitting accuracy.

[0165] For example, the coefficient signs of the polynomial fitting are the same, and the roughness of the planarization layer increases with the decrease of the capacitor / pixel area ratio. According to the data, the planarization layers in the capacitor regions of the red, green, and blue subpixels have different flatness F pand the flatness of the planarization layer corresponding to the different sub-pixels is a first flatness F of the planarization layer corresponding to the red sub-pixel. P1 is the second flatness F of the planarization layer corresponding to the green sub-pixel P2 and the second flatness F of the planarization layer corresponding to the green subpixel is less than or equal to P2 is the third flatness F of the planarization layer corresponding to the blue sub-pixel P3 The electrode widths of the storage capacitors in the pixel regions corresponding to the red, green, and blue subpixels satisfy the following: the electrode width of the storage capacitor corresponding to the red subpixel is equal to or smaller than the electrode width of the storage capacitor corresponding to the green subpixel, and the electrode width of the storage capacitor corresponding to the green subpixel is equal to or smaller than the electrode width of the storage capacitor corresponding to the blue subpixel. According to the data, the planarization layers corresponding to the red, green, and blue subpixels have different flatnesses, and the flatnesses are

number

number

number

[0166] For example, Figure 8B is a schematic planar view of the single active layer shown in Figure 8A, and Figure 8C is a schematic planar view of the active layer, gate, and data line shown in Figure 8A when they are partially overlapped. As shown in Figure 8B, the active layer 102 has a full-layer structure, including a rectangular shape on the left and a long shape on the right, which are connected to form an integrated structure. As shown in Figure 8C, in the planar view of the overlapping active layer 102 and gate 103, both branches of the gate 103 overlap with the long shape of the active layer 102, and the portions parallel to the two branches of the gate also overlap with the long shape of the active layer 102. The second sub-data line 114b, which is part of the data line, is also located in the same layer as the gate 103.

[0167] For example, as shown in FIG. 8A , the first color subpixel 121, the second color subpixel 122, and the third color subpixel 123 are red, green, and blue subpixels, respectively. In order to match the lifespan of the blue light-emitting organic light-emitting diode, the area of ​​the pixel region of the blue subpixel is increased, and a power supply voltage signal line 127 shared by the red, green, and blue subpixels is located at a position corresponding to the blue subpixel. In addition, in order to prevent cross-color interference between adjacent subpixels by increasing the step of the bank between adjacent subpixels, the power supply voltage signal line 127 and the data line 114 are designed as a two-layer structure in the pixel region corresponding to each subpixel, one layer of which is located in the same layer as the gate 103, and the other layer of which is located in the same layer as the source / drain electrode layer 104. The single-layer structure provided in the same layer as the source-drain electrode layer 104 of the power supply voltage signal line 127 is continuously wired in a single sub-pixel region, and the single-layer structure provided in the same layer as the source-drain electrode layer 104 of the data line 114 is also continuously wired in a single sub-pixel region. The single-layer structure provided in the same layer as the gate 103 of the power supply voltage signal line 127 is discontinuously wired in a single sub-pixel region, and the single-layer structure provided in the same layer as the gate 103 of the power supply voltage signal line 127 is narrowed in the pixel region, and its width is less than the width of the single-layer structure provided in the same layer as the source-drain electrode layer 104 of the power supply voltage signal line 127. The single-layer structure provided in the same layer as the gate 103 of the data line 114 is also discontinuously wired in a single sub-pixel region, and the single-layer structure provided in the same layer as the gate 103 of the data line 114 is narrowed in the pixel region, and its width is less than the width of the single-layer structure provided in the same layer as the source-drain electrode layer 104 of the data line 114.

[0168] In addition, the power supply voltage signal line 127 and the data line 114 are both formed as a two-layer structure, so that small protrusions are formed on the edges of each subpixel, thereby increasing the step height of the bank between adjacent subpixels, and the protrusions between adjacent subpixels have the functions of collecting and emitting light. The single-layer structure of the power supply voltage signal line 127 formed on the same layer as the gate 103 is cut in the middle, and the single-layer structure of the data line 114 formed on the same layer as the gate 103 is cut in the middle, and both the source / drain electrode layer 104 and the gate 103 can be made of molybdenum metal material. The power supply voltage signal line 127 and the data line 114 are formed as a two-layer structure, so that the high resistance of the thin wire made of molybdenum metal material can prevent overheating of the current and further poor transmission of electrical signals.

[0169] 9 , the orthogonal projections of the main body 111a included in the pixel definition layer 111 onto the base substrate 101, and the orthogonal projections of the first sub-data line 114a and the second sub-data line 114b included in the same data line 114 onto the base substrate 101 at least partially overlap. The main body 111a, the first sub-data line 114a, and the second sub-data line 114b of the pixel definition layer 111 are stacked, which can raise the main body 111a and form small protrusions on the pixel definition layer 111, thereby reducing crosstalk between light emitted by adjacent sub-pixels.

[0170] For example, as shown in FIG. 9 , the orthogonal projection of the left small protrusion on pixel definition layer 111 onto base substrate 101 overlaps with the orthogonal projection of data line 114 onto base substrate 101, the orthogonal projection of the right small protrusion on pixel definition layer 111 onto base substrate 101 overlaps with the orthogonal projection of power supply voltage signal line 127 onto base substrate 101, the heights of the left small protrusion and the right small protrusion on pixel definition layer 111 are both 0 to 200 nanometers, the thickness of the planarizing layer is 2 microns to 6 microns, and the thickness of gate 103 is 50 nanometers to 400 nanometers.

[0171] For example, as shown in FIGS. 1A and 9, the thickness of the source / drain electrode layer 1041 is 2.5 to 7 times the thickness of the gate 103, for example, 2.5 times, 3 times, 3.5 times, 4 times, 5 times, 5.5 times, 6 times, or 7 times the thickness of the gate 103.

[0172] If the thickness of the source / drain electrode layer 1041 is less than 2.5 times the thickness of the gate 103, the source / drain electrode layer 1041 cannot reduce the flatness of the planarization layer even though it covers the gate 103. If the thickness of the source / drain electrode layer 1041 is more than 7 times the thickness of the gate 103, the volume of the final display panel will be too large.

[0173] For example, FIG. 10 is a schematic planar structural diagram of yet another display panel according to at least one embodiment of the present disclosure. As shown in FIG. 10, the display panel 100 further includes a plurality of gate lines 115, which intersect with a plurality of data lines 114 to define a plurality of pixel regions 116, each of which corresponds to one sub-pixel 120, i.e., the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are respectively arranged in the corresponding pixel region 116.

[0174] For example, as shown in FIG. 10 , a plurality of gate lines 115 are provided in the same layer as the source-drain electrode layer 1041, and the gate lines 115 intersect with the second sub-data lines 114b, and the gate lines 115 are spaced apart from the first sub-data lines 114a. As long as the intersections between the gate lines 115 and the data lines 114 are ensured, the gate lines 115 may intersect with the first sub-data lines 114a, and the gate lines 115 may be spaced apart from the second sub-data lines 114b, or the gate lines 115 may intersect with both the first sub-data lines 114a and the second sub-data lines 114b, but the embodiments of the present disclosure are not limited thereto.

[0175] 10 , the display panel 100 further includes a first initial signal line 117, a second initial signal line 118, and a power supply voltage connecting line 119, which is configured to be connected to a power supply voltage signal line 127, thereby connecting the plurality of power supply voltage signal lines 127 together. For example, the first initial signal line 117, the second initial signal line 118, and the power supply voltage connecting line 119 are all disposed in the same layer as the source / drain electrode layer 1041, so that the first initial signal line 117, the second initial signal line 118, and the power supply voltage connecting line 119 can be formed in the same process step as the source / drain electrode layer 1041. The first initial signal line 117, the second initial signal line 118, and the power supply voltage connecting line 119 are all disposed in parallel to the gate lines 115.

[0176] For example, in one example, the line width of the first initial signal line 117 is 4.84 microns, the line width of the second initial signal line 118 is 3.3 microns, the line width of the power supply voltage connection line 119 is 6.16 microns, the line width of the gate line 115 adjacent to the power supply voltage connection line 119 is 6.6 microns, the line width of the gate line 115 located in the middle position is 3.3 microns, and the line width of the gate line 115 adjacent to the pixel region 116 is 3.96 microns. The distance between the first initial signal line 117 and the second initial signal line 118 is 4.4 microns, the distance between the second initial signal line 118 and the power supply voltage connection line 119 is 3.3 microns, the distance between the power supply voltage connection line 119 and the gate line 115 adjacent to the power supply voltage connection line 119 is 3.74 microns, the distance between the gate line 115 adjacent to the power supply voltage connection line 119 and the middle gate line 15 is 5.06 microns, and the distance between the middle gate line 15 and the gate line 115 adjacent to the pixel area 116 is 4.4 microns. Of course, the embodiments of the present disclosure are not limited to these, and the above line widths and distances may be other values.

[0177] For example, FIG. 11 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure. m is the width of the metal line, and S m denotes the spacing between adjacent metal lines. The line width spacing ratio is

number

number

[0178] For example, the relationship between the undulations and the line width spacing ratio is as follows:

[0179] Polynomial fitting relations:

number

number

number

number

number

[0180] As can be seen from the above equation, the gradient of the undulations of the planarization layer 105 in the metal wiring region first increases with an increase in the line-width-spacing ratio; when the line-width-spacing ratio exceeds 0.6, the gradient of the undulations of the planarization layer decreases with an increase in the line-width-spacing ratio; when the line-width-spacing ratio of the metal wiring is close to 0.5, the metal lines cause the planarization layer thereon to have the greatest roughness, resulting in the greatest undulations of the planarization layer thereon.

[0181] For example, FIG. 12 is a schematic planar structure diagram of yet another display panel according to at least one embodiment of the present disclosure. As shown in FIG. 12 , the display panel 100 further includes an initial signal line connecting line 130, which is disposed on the side of the second color subpixel 122 closest to the third color subpixel 123. The initial signal line connecting line 130 and the data line 114 connected to the second color subpixel 122 are disposed opposite each other on both sides of the second color subpixel 122. The initial signal line connecting line 130 crosses both the first initial signal line 117 and the second initial signal line 118.

[0182] 12, the initial signal line connecting line 130 includes a first sub-initial signal line connecting line 130a and a second sub-initial signal line connecting line 130b that are stacked, the first sub-initial signal line connecting line 130a being provided in the same layer as the source / drain electrode layer 1041, the second sub-initial signal line connecting line 130b being provided in the same layer as the gate 103, the first sub-initial signal line connecting line 130a having an integral structure, and the second sub-initial signal line connecting line 130b including a notch. The presence of the notch in the second sub-initial signal line connecting line 130b allows current to flow throughout the entire first sub-initial signal line connecting line 130a, thereby increasing the area through which current flows.

[0183] 12 , the width of the first sub-initial signal line connecting line 130a is greater than the width of the second sub-initial signal line connecting line 130b in the direction from the initial signal line connecting line 130 to the data line 114 connected to the second-color subpixel 122. Ignoring the portion of the second sub-initial signal line connecting line 130b that extends upward outside the first sub-initial signal line connecting line 130a, the orthogonal projection of the second sub-initial signal line connecting line 130b onto the base substrate 101 is located within the orthogonal projection of the first sub-initial signal line connecting line 130a onto the base substrate 101.

[0184] For example, as shown in FIG. 12 , the edge of the second sub-initial signal line connecting line 130b away from the second-color subpixel 122 is aligned with the edge of the first sub-initial signal line connecting line 130a away from the second-color subpixel 122, and the edge of the second sub-initial signal line connecting line 130b close to the second-color subpixel 122 is located on the side away from the second-color subpixel 122 of the edge of the first sub-initial signal line connecting line 130a close to the second-color subpixel 122.

[0185] For example, in one example, the width of the first sub-initial signal line connecting line 130a is 2 to 3 times the width of the second sub-initial signal line connecting line 130b, for example, the width of the first sub-initial signal line connecting line 130a is 2 times, 2.5 times, or 3 times the width of the second sub-initial signal line connecting line 130b.

[0186] For example, the width of the first sub-initial signal line connecting line 130a is 2 microns to 20 microns, and the width of the second sub-initial signal line connecting line 130b is 2 microns to 10 microns. In this way, the first sub-initial signal line connecting line 130a and the second sub-initial signal line connecting line 130b can satisfy the structural feature that their left edges are aligned and there is a gap between their right edges.

[0187] For example, in one example, the width of the first sub-initial signal line connecting line 130a is 4 microns, the width of the second sub-initial signal line connecting line 130b is 2 microns, the width of the first sub-initial signal line connecting line 130a is 8 microns, the width of the second sub-initial signal line connecting line 130b is 4 microns, the width of the first sub-initial signal line connecting line 130a is 12 microns, the width of the second sub-initial signal line connecting line 130b is 6 microns, and the width of the first sub-initial signal line connecting line 130a is 16 microns. The width of the first sub-initial signal line connecting line 130a is 18 microns, the width of the second sub-initial signal line connecting line 130b is 9 microns, the width of the first sub-initial signal line connecting line 130a is 20 microns, and the width of the second sub-initial signal line connecting line 130b is 10 microns, so that the width of the first sub-initial signal line connecting line 130a is twice the width of the second sub-initial signal line connecting line 130b.

[0188] For example, in one example, the width of the first sub-initial signal line connecting line 130a is 5 microns, the width of the second sub-initial signal line connecting line 130b is 2 microns, the width of the first sub-initial signal line connecting line 130a is 10 microns, the width of the second sub-initial signal line connecting line 130b is 4 microns, the width of the first sub-initial signal line connecting line 130a is 15 microns, the width of the second sub-initial signal line connecting line 130b is 6 microns, the width of the first sub-initial signal line connecting line 130a is 20 microns, and the width of the second sub-initial signal line connecting line 130b is 8 microns, thereby the width of the first sub-initial signal line connecting line 130a is 2.5 times the width of the second sub-initial signal line connecting line 130b.

[0189] For example, in one example, the width of the first sub-initial signal line connecting line 130a is 9 microns, the width of the second sub-initial signal line connecting line 130b is 3 microns, the width of the first sub-initial signal line connecting line 130a is 12 microns, the width of the second sub-initial signal line connecting line 130b is 4 microns, the width of the first sub-initial signal line connecting line 130a is 15 microns, the width of the second sub-initial signal line connecting line 130b is 5 microns, the width of the first sub-initial signal line connecting line 130a is 18 microns, and the width of the second sub-initial signal line connecting line 130b is 6 microns, thereby the width of the first sub-initial signal line connecting line 130a is three times the width of the second sub-initial signal line connecting line 130b.

[0190] 12 , the display panel 100 further includes a power supply voltage signal transmission line 131, which is disposed on a side of the first color subpixel 121 adjacent to the second color subpixel 122, and the power supply voltage signal transmission line 131 and the data line 114 connected to the first color subpixel 121 are disposed opposite each other on both sides of the first color subpixel 121. For example, in the first direction X, the overall width of the power supply voltage signal transmission line 131 is less than the overall width of the power supply voltage signal line 127.

[0191] 12 , in one example, the power supply voltage signal transmission line 131 includes a first power supply voltage signal transmission line 131a and a second power supply voltage signal transmission line 131b that are stacked, the first power supply voltage signal transmission line 131a being provided in the same layer as the source / drain electrode layer 104, the second power supply voltage signal transmission line 131b being provided in the same layer as the gate 103, the first power supply voltage signal transmission line 131a having an integral structure, and the second power supply voltage signal transmission line 131b including a notch. By providing the first power supply voltage signal transmission line 131a and the second power supply voltage signal transmission line 131b in the same layer, even if the first power supply voltage signal transmission line 131a and the second power supply voltage signal transmission line 131b have a two-layer structure, the level of the formed step does not increase, and only a new step is formed in a different position, so that the flatness of the planarization layer 105 is not affected.

[0192] 12, the stacked first power supply voltage signal transmission line 131a and second power supply voltage signal transmission line 131b can reduce the resistance of the power supply voltage signal transmission line 131, and the second power supply voltage signal transmission line 131b can achieve electrical continuity with the upper first power supply voltage signal transmission line 131a by including a notch. The notch in the second power supply voltage signal transmission line 131b allows current to flow throughout the entire first power supply voltage signal transmission line 131a, increasing the area through which the current flows.

[0193] 12 , the width of the first power supply voltage signal transmission line 131a is greater than the width of the second power supply voltage signal transmission line 131b in the direction from the power supply voltage signal transmission line 131 to the data line 114 connected to the first-color subpixel 121. Ignoring the portion of the second power supply voltage signal transmission line 131b that extends upward beyond the first power supply voltage signal transmission line 131a, the orthogonal projection of the second power supply voltage signal transmission line 131b onto the base substrate 101 is located within the orthogonal projection of the first power supply voltage signal transmission line 131a onto the base substrate 101.

[0194] For example, in one example, the edge of the second power supply voltage signal transmission line 131b that faces away from the data line 114 connected to the first color subpixel 121 is aligned with the edge of the first power supply voltage signal transmission line 131a that faces away from the data line 114 connected to the first color subpixel 131, and the edge of the second power supply voltage signal transmission line 131b that faces close to the data line 114 connected to the first color subpixel 121 is located on the side of the edge of the first power supply voltage signal transmission line 131a that faces close to the data line 114 connected to the first color subpixel 121 that faces away from the data line 114 connected to the first color subpixel 121.

[0195] For example, in one example, the width of the first power supply voltage signal transmission line 131a is 2 to 3 times the width of the second power supply voltage signal transmission line 131b, for example, the width of the first power supply voltage signal transmission line 131a is 2 times, 2.5 times, or 3 times the width of the second power supply voltage signal transmission line 131b.

[0196] For example, the width of the first power supply voltage signal transmission line 131a is 2 to 30 microns, and the width of the second power supply voltage signal transmission line 131b is 2 to 10 microns. In this way, the first power supply voltage signal transmission line 131a and the second power supply voltage signal transmission line 131b can satisfy the structural feature that their left edges are aligned and there is a gap between their right edges.

[0197] For example, in one example, the width of the first power supply voltage signal transmission line 131a is 4 microns, the width of the second power supply voltage signal transmission line 131b is 2 microns, the width of the first power supply voltage signal transmission line 131a is 8 microns, the width of the second power supply voltage signal transmission line 131b is 4 microns, the width of the first power supply voltage signal transmission line 131a is 12 microns, the width of the second power supply voltage signal transmission line 131b is 6 microns, and the width of the first power supply voltage signal transmission line 131a is 16 microns. The width of the first power supply voltage signal transmission line 131a is 18 microns, the width of the second power supply voltage signal transmission line 131b is 9 microns, the width of the first power supply voltage signal transmission line 131a is 20 microns, and the width of the second power supply voltage signal transmission line 131b is 10 microns, so that the width of the first power supply voltage signal transmission line 131a is twice the width of the second power supply voltage signal transmission line 131b.

[0198] For example, in one example, the width of the first power supply voltage signal transmission line 131a is 5 microns, the width of the second power supply voltage signal transmission line 131b is 2 microns, the width of the first power supply voltage signal transmission line 131a is 10 microns, the width of the second power supply voltage signal transmission line 131b is 4 microns, the width of the first power supply voltage signal transmission line 131a is 15 microns, the width of the second power supply voltage signal transmission line 131b is 6 microns, the width of the first power supply voltage signal transmission line 131a is 20 microns, and the width of the second power supply voltage signal transmission line 131b is 8 microns, so that the width of the first power supply voltage signal transmission line 131a is 2.5 times the width of the second power supply voltage signal transmission line 131b.

[0199] For example, in one example, the width of the first power supply voltage signal transmission line 131a is 9 microns, the width of the second power supply voltage signal transmission line 131b is 3 microns, the width of the first power supply voltage signal transmission line 131a is 12 microns, the width of the second power supply voltage signal transmission line 131b is 4 microns, the width of the first power supply voltage signal transmission line 131a is 15 microns, the width of the second power supply voltage signal transmission line 131b is 5 microns, the width of the first power supply voltage signal transmission line 131a is 18 microns, and the width of the second power supply voltage signal transmission line 131b is 6 microns, so that the width of the first power supply voltage signal transmission line 131a is three times the width of the second power supply voltage signal transmission line 131b.

[0200] For example, as shown in FIG. 12, the data lines 114 extend in a first direction X, and the gate lines 115 extend in a second direction Y, where the first direction X and the second direction Y are perpendicular to each other.

[0201] For example, as shown in FIG. 12 , in the first direction X, the width of the first power supply voltage signal line 127a is W1, the width of the first sub-data line 114a is W2, the width of the first sub-initial signal line connecting line 130a is W3, the width of the source-drain electrode layer 1041 corresponding to the third color subpixel 123 is W4, the width of the source-drain electrode layer 1041 corresponding to the second color subpixel 122 is W5, the width of the source-drain electrode layer 1041 corresponding to the first color subpixel 121 is W6, the width of the first gap D1 between the first sub-initial signal line connecting line 130a and the second color subpixel 122 is W7, the distance between the second color subpixel 122 and the first power supply voltage signal transmission line 131a is W8, and the width of the first power supply voltage signal transmission line 131a is W9, where W1 is equal to or approximately equal to W4,

number

[0202] For example, in one example, the line width spacing ratio of each gate line 115 is:

number

number

number

[0203] For example, in one example, the slope K of the undulations of the planarization layer 105 em and the line width spacing ratio K of the gate line 115 ws The equation obtained by polynomial fitting to

number

number

[0204] 12 , the width W1 of the first power supply voltage signal line 127a is 30 μm, the width of the blue subpixel storage capacitor is 30 μm, the maximum width of the data line is 3 μm, the width of the first sub-initial signal line connecting line 130a is 5 μm, the width of the green subpixel storage capacitor is 25 μm, the distance between the edge of the green subpixel closest to the first sub-initial signal line connecting line 130a and the first sub-initial signal line connecting line 130a is 5 μm, the distance between the edge of the green subpixel closest to the red subpixel and the first power supply voltage signal transmission line 131a is 10 μm, the width of the first power supply voltage signal transmission line 131a is 5 μm, and the width of the red subpixel storage capacitor is 25 μm. Designing the line widths and spacings described above can improve the flatness of the planarization layer, thereby alleviating the color cast problem.

[0205] For example, as shown in FIG. 12, the electrode block in the capacitor region of the first source / drain electrode 1041 is used to improve the flatness of the planarization layer 105. The film layer of the first source / drain electrode 1041 is thick, and the first source / drain electrode 1041 is closer to the planarization layer 105, which is advantageous for improving the flatness of the planarization layer 105, and the material of the gate line and the material of the source / drain electrode layer are the same.

[0206] 12, the light-shielding layer may be removed, thereby further reducing the process steps and the amount of metal material used, thereby lowering production costs. A vertical initial signal line connecting line 130 and a power supply voltage signal transmission line 131 are added, and the power supply voltage signal transmission line 131, the power supply voltage signal line 127, and the power supply voltage connecting line 119 form a plurality of grid lines crossing each other, thereby reducing resistance and voltage drop. The grid lines for the initial signal lines reduce resistance and voltage drop, ensuring stability of the initialization voltage. For example, in another example, instead of using two-layer wiring for the data lines in the pixel region, the vertical initial signal line connecting line 130 and the power supply voltage signal transmission line 131 designed at the boundary of the pixel are designed as two-layer wiring, one layer of which is located on the same layer as the gate and the other layer of which is located on the same layer as the first source / drain electrode, and the structure located on the same layer as the gate is disconnected in the central region of the pixel. Since the initial signal line connection line 130 and the power supply voltage signal transmission line 131 are used as a pixel bank, it is necessary to increase the thickness, thereby increasing the step of the pixel bank.

[0207] For example, Figure 13 is a schematic diagram of the circuit structure of a display panel according to at least one embodiment of the present disclosure. As shown in Figure 13, the gate of the first thin film transistor T1 is controlled by a gate line G1 and connected to a data line Data. The gate line G1 turns on the first thin film transistor T1, inputting a data signal Data to the gate of the third thin film transistor T3 and storing it in the storage capacitor Cst. The gate of the second thin film transistor T2 is controlled by a gate line G2 and connected to a second initial signal line VIN2. Between frames, the second thin film transistor T2 is turned on to erase the gate voltage of the third thin film transistor T3 stored in the previous frame, and the initial signal line VIN2 is written to the gate of the driving transistor T3. The third thin film transistor T3 is a driving transistor and has a driving function. To reduce the aspect ratio of the transistor, i.e., to increase the channel length, two transistors T3 and T3' are provided. The gates in the plan view shown in Figure 8C are disconnected in the middle, but are still connected. The drain of the driving transistor T3 is connected to the pixel electrode, which is then connected to the light emitting diode. The source of the driving transistor T3 is connected to the fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is controlled by the first initial signal line VIN1, and the source of the fourth thin film transistor T4 is connected to the power supply voltage signal line.

[0208] For example, FIG. 14 is a circuit structure schematic diagram of another display panel according to at least one embodiment of the present disclosure. In FIG. 14, the EM1 transistor can be regarded as the fourth thin film transistor T4, and FN can be regarded as the first initial signal line VIN1. For the operating principles of other transistors, please refer to the related descriptions in FIG. 13 above.

[0209] 15 is a schematic cross-sectional structure diagram of yet another display panel according to at least one embodiment of the present disclosure, and as shown in Fig. 15, the display panel 100 further includes a light-emitting element 150 and a second electrode 153 provided on the side of the first electrode 112 away from the base substrate 101, and the light-emitting element 150 includes a light-emitting layer 151 and an organic functional layer 152 laminated with the light-emitting layer 151. For example, in one example, the light-emitting layer 151 is formed by a printing process, and the organic functional layer 152 is formed by a vapor deposition process.

[0210] For example, as shown in FIG. 15, the light-emitting element 150 includes a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and the ratio of the thickness of the red light-emitting layer included in the red light-emitting element to the peak wavelength of the red light ranges from 0.15 to 0.4, the ratio of the thickness of the green light-emitting layer included in the green light-emitting element to the peak wavelength of the green light ranges from 0.15 to 0.4, and the ratio of the thickness of the blue light-emitting layer 1501c included in the blue light-emitting element to the peak wavelength of the blue light ranges from 0.1 to 0.2.

[0211] For example, blue light has the shortest wavelength and the highest energy, and the exciton extinction coefficient of the blue light-emitting material is the highest, so the thinner the thickness of the blue light-emitting layer, the better.

[0212] For example, the first electrode 112 has a three-layer structure, with the upper and lower layers of the first electrode 112 being made of tungsten oxide, and the intermediate layer between the upper and lower layers being made of aluminum metal, with the intermediate layer having a thickness of 180 nm to 191 nm, the electrode layer closest to the second electrode 153 having a thickness of 11 nm to 14 nm, and the other layer having a thickness of 4 nm to 7 nm. The second electrode 153 has a two-layer structure, with the layer closest to the first electrode 112 being made of indium oxide and having a thickness of 79 nm to 81 nm. The layer farther from the first electrode 112 in the two-layer structure being made of silver and having a thickness of 13 nm to 17 nm. The organic functional layer includes a hole transport layer, a hole injection layer, and an electron injection layer, and the electron injection layer has a two-layer structure, with the thickness of the side of the electron injection layer closest to the first electrode 112 being 3 nm to 7 nm and the thickness of the side of the electron injection layer away from the first electrode 112 being 25 nm to 27 nm.

[0213] For example, in one example, the first electrode 112 has a two-layer structure, the material of the layer of the first electrode 112 closest to the second electrode 153 is tungsten oxide and the thickness of the tungsten oxide is 12 nm, and the material of the layer of the first electrode 112 away from the second electrode 153 is aluminum metal and the thickness of the aluminum metal is 248 nm. The thickness of the layer structure of the electron injection layer on the side closest to the first electrode 112 is 7 nm, the thickness of the layer structure of the electron injection layer on the side away from the first electrode 112 is 8 nm, the material of the second electrode 153 is silver metal and the thickness is 26 nm, and a package layer is provided on the side of the second electrode 153 away from the first electrode 112.

[0214] For example, in one example, the ratio of the thickness of the printed red light-emitting layer to the red peak wavelength in the red subpixel ranges from 0.15 to 0.4. The ratio of the thickness of the printed green light-emitting layer to the peak wavelength in the green subpixel ranges from 0.15 to 0.3. The ratio of the thickness of the printed blue light-emitting layer to the peak wavelength in the blue subpixel ranges from 0.1 to 0.2. The wavelength of the blue light is 456.6 nm, the wavelength of the green light is 528.73 nm, and the wavelength of the red light is 619.47 nm.

[0215] For example, in one example, the ratio of the thickness of the printed red light-emitting layer in the red subpixel to the wavelength of red light is 0.2776, the ratio of the sum of the thicknesses of the printed red light-emitting layer and organic functional layers in the red subpixel to the wavelength of red light is 0.3244, the ratio of the thickness of the printed green light-emitting layer in the green subpixel to the wavelength of green light is 0.2118, the ratio of the sum of the thicknesses of the printed green light-emitting layer and organic functional layers in the green subpixel to the wavelength of green light is 0.2667, the ratio of the thickness of the printed blue light-emitting layer in the blue subpixel to the wavelength of blue light is 0.1533, and the ratio of the sum of the thicknesses of the printed blue light-emitting layer and organic functional layers in the blue subpixel to the wavelength of blue light is 0.2168.

[0216] In another example, the ratio of the thickness of the printed red light-emitting layer in the red subpixel to the wavelength of red light is 0.2034, the ratio of the total thickness of the printed red light-emitting layer and organic functional layer in the red subpixel to the wavelength of red light is 0.2276, the ratio of the thickness of the printed green light-emitting layer in the green subpixel to the wavelength of green light is 0.1872, the ratio of the total thickness of the printed green light-emitting layer and organic functional layer in the green subpixel to the wavelength of green light is 0.2156, the ratio of the thickness of the printed blue light-emitting layer in the blue subpixel to the wavelength of blue light is 0.1424, and the ratio of the total thickness of the printed blue light-emitting layer and organic functional layer in the blue subpixel to the wavelength of blue light is 0.1752.

[0217] For example, in one example, the range of the ratio between the sum of the thicknesses of the multiple red light-emitting layers 1501a and the corresponding organic functional layer 152 (red organic functional layer 152a) and the peak wavelength of the red light is 0.2 to 0.4, the range of the ratio between the sum of the thicknesses of the multiple green light-emitting layers 1501b and the corresponding organic functional layer 152 (green organic functional layer 152b) and the peak wavelength of the green light is 0.2 to 0.3, and the range of the ratio between the sum of the thicknesses of the multiple blue light-emitting layers and the corresponding organic functional layer 152 (blue organic functional layer 152c) and the peak wavelength of the blue light is 0.15 to 0.25.

[0218] For example, a vapor deposition process can form thin films or small molecules layer by layer on a base substrate by physical deposition. Therefore, the uniformity of a printing process is inferior to that of a vapor deposition process. Typically, an emissive layer is formed on a structure in which a first electrode, a planarization layer, and a thin film transistor are stacked in sequence. Therefore, an emissive layer formed by a vapor deposition process has excellent shape retention properties and has the same or very similar thickness in each part of the stacked structure. A printing process uses a nozzle to drop a liquid with fluid and viscous properties, resulting in different thicknesses in the recessed and protruding parts of the stacked structure, resulting in poor uniformity of the thin film thickness. A structure with different thicknesses of an emissive layer at different locations can lead to inconsistent light-emitting properties and color cast. To improve these properties, embodiments of the present disclosure adjust the layout and line width of signal lines in pixel areas of different colors.

[0219] That is, the embodiments of the present disclosure improve the flatness of the planarization layer by adjusting the line widths of various signal lines, such as the first initial signal line, the second initial signal line, the power supply voltage connection line, and the gate line, or the spacing between adjacent signal lines.

[0220] For example, at least one embodiment of the present disclosure further provides a display device, which includes any one of the display panels described above. For example, Fig. 16 is a block diagram of a display device according to at least one embodiment of the present disclosure, and as shown in Fig. 16, the display device 200 includes a display panel 100. For example, the display panel 100 may be a display panel according to any one of the embodiments of the present disclosure.

[0221] For example, the display device 200 may be a display device having a display function, such as a display, an OLED display panel, an OLED television, a liquid crystal display panel, a liquid crystal display television, a QLED display panel, a QLED television, electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component having a display function and a touch function.

[0222] A display panel and a display device according to at least one embodiment of the present disclosure have at least one of the following beneficial technical effects.

[0223] (1) According to at least one embodiment of the display panel of the present disclosure, the orthogonal projection of the gate onto the base substrate is located within the orthogonal projection of the source / drain electrode layer and the active layer onto the base substrate, and the thickness of the source / drain electrode layer is greater than the thickness of the gate in the direction perpendicular to the main surface of the base substrate. By designing the gate, the source / drain electrode layer, and the active layer to have the above structural relationship, the flatness of the planarization layer located on the source / drain electrode layer can be reduced, i.e., the surface of the planarization layer can be made flatter, thereby improving the display effect of the display panel.

[0224] (2) In a display panel according to at least one embodiment of the present disclosure, the power supply voltage signal line includes a first power supply voltage signal line and a second power supply voltage signal line that are stacked together, the first power supply voltage signal line is provided in the same layer as the source / drain electrode layer, the second power supply voltage signal line is provided in the same layer as the gate, the first power supply voltage signal line has an integral structure, and the second power supply voltage signal line includes a notch. The presence of the notch in the second power supply voltage signal line allows current to flow through the entire first power supply voltage signal line, thereby increasing the area through which the current flows.

[0225] (3) In a display panel according to at least one embodiment of the present disclosure, the power supply voltage signal line and the data line are both provided as a two-layer laminated structure, and therefore small protrusions are formed on the edges of each subpixel, thereby increasing the step of the bank between adjacent subpixels, and the protrusions between adjacent subpixels have the functions of collecting and emitting light.

[0226] The following points need to be explained.

[0227] (1) The drawings of the embodiments of the present disclosure only relate to the structures of the embodiments of the present disclosure, and other structures may refer to the general design.

[0228] (2) For clarity, in the drawings illustrating the embodiments of the present disclosure, the thicknesses of layers or regions are exaggerated or reduced, i.e., the drawings are not drawn to actual scale.

[0229] (3) Where no contradiction exists, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0230] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and the scope of protection of the present disclosure shall be in accordance with the scope of protection of the claims.

Claims

1. It is a display panel, Base board and An active layer, gate and source / drain electrode layer are sequentially stacked on the base substrate, The source-drain electrode layer includes a planarization layer provided on the side away from the base substrate, A display panel characterized in that the orthographic projection of the gate onto the base substrate lies within the orthographic projection of the source-drain electrode layer and the active layer onto the base substrate, and in a direction perpendicular to the main surface of the base substrate, the thickness of the source-drain electrode layer is greater than the thickness of the gate.

2. A gate insulating layer is provided between the active layer and the gate, and an interlayer insulating layer is provided between the gate and the source-drain electrode layer. The source-drain electrode layer includes a first source-drain electrode and a second source-drain electrode provided opposite each other. The first source-drain electrode is electrically connected to the active layer via a first via structure that sequentially penetrates the interlayer insulating layer and the gate insulating layer, and the orthographic projection of the gate onto the base substrate lies within the orthographic projection of the first source-drain electrode onto the base substrate. The display panel according to claim 1, characterized in that the second source-drain electrode is electrically connected to the active layer via a second via structure that sequentially penetrates the interlayer insulating layer and the gate insulating layer.

3. The display panel according to claim 2, characterized in that the end of the first source-drain electrode that is separated from the second source-drain electrode is electrically connected to the active layer via the first via structure.

4. The display panel according to claim 2, further comprising a plurality of data lines, wherein the plurality of data lines are provided in the same layer as the source-drain electrode layer, and each of the plurality of data lines is electrically connected to the corresponding second source-drain electrode.

5. The display panel according to claim 4, further comprising a pixel definition layer provided on the side of the planarization layer away from the base substrate, wherein the pixel definition layer includes a main body portion and an aperture region between adjacent main body portions.

6. The display panel according to claim 5, further comprising a first electrode provided on the side of the planarized layer away from the base substrate, wherein the first electrode is provided in the opening region, and the first electrode is electrically connected to the first source-drain electrode via a third via structure penetrating the planarized layer.

7. The array includes a plurality of subpixels, the plurality of subpixels including a first color subpixel, a second color subpixel, and a third color subpixel arranged adjacent to each other in order, and the orthogonal projection of the first source-drain electrode corresponding to the first color subpixel onto the base substrate is the first metal area S Ｍ１ The orthographic projection of the first source-drain electrode corresponding to the second color subpixel onto the base substrate is the second metal area S Ｍ２ The orthographic projection of the first source-drain electrode corresponding to the third color subpixel onto the base substrate is the third metal area S Ｍ３ The first metal area S Ｍ１ The second metal area S Ｍ２ The following applies: The second metal area S Ｍ２ The third metal area S Ｍ３ A display panel according to any one of claims 4 to 6, characterized in that it is less than [amount].

8. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, and the first color sub-pixel has a first sub-pixel area S Ｐ１ and the second color sub-pixel has a second sub-pixel area S Ｐ２ and the third color sub-pixel has a third sub-pixel area S Ｐ３ and [Math 1] F １ F ２ and F ３ These are the area ratio of the first source-drain electrode corresponding to the first color subpixel, the area ratio of the first source-drain electrode corresponding to the second color subpixel, and the area ratio of the first source-drain electrode corresponding to the third color subpixel, respectively, F １ is F ２ That's all. F ２ is F ３ The display panel according to claim 7, characterized in that it is larger than [the specified size].

9. Area ratio F of the first source-drain electrode corresponding to the first color subpixel １ , the area ratio F of the first source-drain electrode corresponding to the second color subpixel ２ and the area ratio F of the first source-drain electrode corresponding to the third color subpixel. ３ The display panel according to claim 8, characterized in that the sizes of the elements are 55%, 50%, and 30%, respectively.

10. The display panel according to claim 9, characterized in that the plurality of subpixels are arranged in an array, and in the row direction, the width of the first source-drain electrode corresponding to the first color subpixel is less than or equal to the width of the first source-drain electrode corresponding to the adjacent second color subpixel, and the width of the first source-drain electrode corresponding to the adjacent third color subpixel is less than or equal to the width of the first source-drain electrode corresponding to the adjacent third color subpixel.

11. The display panel according to claim 10, characterized in that different positions corresponding to the planarization layer have different degrees of flatness, and the flatness of the planarization layer increases with decreasing area ratio of the first source-drain electrode corresponding to each subpixel.

12. The first flatness F of the planarization layer corresponding to the first color subpixel Ｐ１ The second flatness F of the planarization layer corresponding to the second color subpixel is Ｐ２ The second flatness F of the planarization layer corresponding to the second color subpixel is as follows: Ｐ２ The third flatness F of the planarization layer corresponding to the third color subpixel is Ｐ３ The display panel according to claim 11, characterized in that it is as follows:

13. The first flatness is, [Math 2] The second flatness is, [Math 3] The third flatness is, [Math 4] The display panel according to claim 12, wherein H1 and H1' are the maximum and minimum thicknesses of the planarization layer corresponding to the first color subpixel, respectively; H2 and H2' are the maximum and minimum thicknesses of the planarization layer corresponding to the second color subpixel, respectively; H3 and H3' are the maximum and minimum thicknesses of the planarization layer corresponding to the third color subpixel, respectively; and T is the average thickness of the planarization layer. [Request Item 14] [Number 5] The display panel according to claim 12, characterized in that it is the same as the present invention.

15. The equation obtained by performing a polynomial fitting on the average flatness x of the planarization layer and the area ratio y of the first source-drain electrode corresponding to each sub-pixel is: [Math 6] The display panel according to claim 11, characterized in that the range of a is 0 to -30, the range of b is 20 to 60, and the range of c is 0 to 40.

16. The equation obtained by performing a polynomial fitting on the average flatness x of the planarization layer and the area ratio y of the first source-drain electrode corresponding to each sub-pixel is: [Number 7] The coefficient of determination is, [Number 8] The display panel according to claim 15, characterized in that it is the same as the present invention.

17. The first flatness F Ｐ１ , the second flatness F Ｐ２ and the third flatness F Ｐ３ The display panel according to claim 12, characterized in that the sizes of the elements are 1.5%, 2%, and 2.5%, respectively.

18. The display panel according to claim 12, further comprising a power supply voltage signal line provided on the side of the third color subpixel that is away from the second color subpixel.

19. The display panel according to claim 18, wherein the power supply voltage signal line includes a first power supply voltage signal line and a second power supply voltage signal line that are stacked, the first power supply voltage signal line is provided in the same layer as the source drain electrode layer, the second power supply voltage signal line is provided in the same layer as the gate, the first power supply voltage signal line has an integral structure, and the second power supply voltage signal line includes a notch.

20. The display panel according to claim 19, characterized in that the power supply voltage signal line and the data line connected to the third color subpixel are provided on both sides of the third color subpixel, and the power supply voltage signal line and the data line connected to the third color subpixel are provided opposite each other, and in the direction from the power supply voltage signal line to the data line connected to the third color subpixel, the width of the first power supply voltage signal line is greater than the width of the second power supply voltage signal line.

21. The display panel according to claim 19, characterized in that the edge of the second power supply voltage signal line away from the data line connected to the aforementioned third color subpixel is aligned with the edge of the first power supply voltage signal line away from the data line connected to the aforementioned third color subpixel, and the edge of the second power supply voltage signal line close to the data line connected to the aforementioned third color subpixel is located on the side of the edge of the first power supply voltage signal line close to the data line connected to the aforementioned third color subpixel that is away from the data line connected to the aforementioned third color subpixel.

22. The display panel according to claim 20, characterized in that the width of the first power supply voltage signal line is 2 to 4 times the width of the second power supply voltage signal line.

23. The display panel according to claim 22, characterized in that the width of the first power supply voltage signal line is 10 to 30 microns, and the width of the second power supply voltage signal line is 2 to 20 microns.

24. The display panel according to claim 19, characterized in that the orthographic projection of the main body portion included in the pixel definition layer onto the base substrate, the orthographic projection of the first power supply voltage signal line onto the base substrate, and the orthographic projection of the second power supply voltage signal line onto the base substrate overlap at least partially.

25. The display panel according to claim 18, wherein each of the plurality of data lines includes a first sub-data line and a second sub-data line provided in a stack, the first sub-data line is provided in the same layer as the source-drain electrode layer, the second sub-data line is provided in the same layer as the gate, the first sub-data line has an integral structure, the second sub-data line includes a notch, and each of the data lines is electrically connected to the first source-drain electrode of the corresponding sub-pixel via the first sub-data line.

26. The display panel according to claim 25, characterized in that, in the direction from the power supply voltage signal line to the data line connected to the third color subpixel, the width of the first subdata line is greater than the width of the second subdata line.

27. The display panel according to claim 26, characterized in that, on the same data line, the edge of the second sub-data line away from the sub-pixel connected to the data line on which it is located is aligned with the edge of the corresponding first sub-data line away from the sub-pixel electrically connected to it, and the edge of the second sub-data line close to the sub-pixel connected to the data line on which it is located is located on the side away from the corresponding sub-pixel of the edge of the corresponding first sub-data line close to the sub-pixel electrically connected to it.

28. The display panel according to claim 26, characterized in that, in the same data line, the width of the first sub-data line is 2 to 4 times the width of the second sub-data line.

29. The display panel according to claim 28, characterized in that, in the same data line, the width of the first sub-data line is 2 microns to 20 microns, and the width of the second sub-data line is 2 microns to 10 microns.

30. The display panel according to claim 27, characterized in that the orthographic projection of the main body portion included in the pixel definition layer onto the base substrate, the orthographic projection of the first sub-data line included in the same data line onto the base substrate, and the orthographic projection of the second sub-data line onto the base substrate overlap at least partially.

31. The display panel according to claim 1, characterized in that the thickness of the source-drain electrode layer is 2.5 to 7 times the thickness of the gate.

32. The display panel according to claim 25, further comprising a plurality of gate lines, wherein the plurality of gate lines intersect with the plurality of data lines to define a plurality of pixel regions, and each of the pixel regions corresponds to one of the subpixels.

33. The display panel according to claim 32, characterized in that the plurality of gate lines are provided in the same layer as the source-drain electrode layer, the gate lines intersect with the second sub-data line, and the gate lines are spaced apart from the first sub-data line.

34. The display panel according to claim 33, further comprising a first initial signal line, a second initial signal line, and a power supply voltage connection line, wherein the power supply voltage connection line is configured to be connected to the power supply voltage signal line, and the first initial signal line, the second initial signal line, and the power supply voltage connection line are all provided in the same layer as the source-drain electrode layer and are provided parallel to the gate line.

35. The display panel according to claim 34, further comprising an initial signal line connection line, wherein the initial signal line connection line is provided on the side of the second color subpixel adjacent to the third color subpixel, the data lines connected to the initial signal line connection line and the second color subpixel are provided facing each other on both sides of the second color subpixel, and the initial signal line connection line intersects with both the first initial signal line and the second initial signal line.

36. The display panel according to claim 35, wherein the initial signal line connection line includes a first sub-initial signal line connection line and a second sub-initial signal line connection line provided in a stack, the first sub-initial signal line connection line is provided in the same layer as the source-drain electrode layer, the second sub-initial signal line connection line is provided in the same layer as the gate, the first sub-initial signal line connection line has an integral structure, and the second sub-initial signal line connection line includes a notch.

37. The display panel according to claim 36, characterized in that, in the direction from the initial signal line connection to the data line connected to the second color subpixel, the width of the first subinitial signal line connection is greater than the width of the second subinitial signal line connection.

38. The display panel according to claim 36, characterized in that the edge of the second sub-initial signal line connection that moves away from the second color subpixel is aligned with the edge of the first sub-initial signal line connection that moves away from the second color subpixel, and the edge of the second sub-initial signal line connection that moves close to the second color subpixel is located on the side of the edge of the first sub-initial signal line connection that moves away from the second color subpixel.

39. A display device characterized by including the display panel described in claim 1.

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