Display device and manufacturing method thereof

Abstract

A display device and a manufacturing method thereof are provided, the display device including: a data conductive layer disposed on a substrate; a passivation layer disposed on the data conductive layer and including a first opening; a protective layer disposed on the passivation layer; a via layer disposed on the protective layer and including a second opening overlapping the first opening; a connection electrode spaced apart from a pixel electrode disposed on the via layer and disposed within the first and second openings; a pixel defining (defining) film disposed on the pixel electrode and the connection electrode and including an opening hole overlapping the second opening; a light-emitting layer disposed on the pixel defining (defining) film; and a common electrode disposed on the light-emitting layer and electrically connected to a first power wiring, the data conductive layer including a data base layer, a data main metal layer, and a data capping layer, the first power wiring including a wiring connection structure formed such that the data main metal layer is recessed relative to a side surface of the data capping layer, and the common electrode is electrically connected to the data main metal layer by the wiring connection structure.

Description

[Technical Field]

[0001] The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] Display devices are becoming increasingly important with the development of multimedia. In response to this, various display devices such as liquid crystal display devices (LCDs) and organic light emitting diode display devices (OLEDs) are being developed.

[0003] Among display devices, self-emitting display devices include self-emitting elements, e.g., organic light-emitting elements. The self-emitting elements may include two opposing electrodes and an emitting layer interposed therebetween. When the self-emitting element is an organic light-emitting element, electrons and holes provided from the two electrodes recombine in the emitting layer to generate excitons, which then change from an excited state to a ground state to emit light.

[0004] Self-luminous display devices do not require a light source such as a backlight unit, so they consume less power and can be constructed in a lightweight and thin form. They also have high-quality characteristics such as a wide viewing angle, high brightness and contrast, and fast response speed, and are therefore attracting attention as next-generation display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a display device including power supply wiring that is arranged in a display area, to which a voltage is applied, and that is electrically connected to a common electrode.

[0006] An object of the present invention is to provide a display device in which damage to the power supply wiring is prevented when the power supply wiring is connected to the common electrode, and a method for manufacturing the same.

[0007] The problems to be solved by the present invention are not limited to those mentioned above, and further technical problems not mentioned here will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment for solving the above problem includes: (1) a data conductive layer including a first power wiring disposed on a substrate; (2) a passivation layer disposed on the data conductive layer and including a first opening exposing at least a portion of the first power wiring; (3) a protection layer disposed on the passivation layer; (4) a via layer disposed on the protection layer and including a second opening partially overlapping the first opening; (5) a pixel electrode disposed on the via layer and a connection electrode spaced apart from the pixel electrode and at least a portion of which is disposed within the first opening and the second opening; and a pixel pixel electrode and a pixel electrode disposed on the connection electrode and including an opening hole overlapping the second opening. (6) a pixel defining (defining) film, (7) a light-emitting layer disposed on the light-emitting layer and at least a portion of which is disposed on the pixel electrode and the connection electrode, and (8) a common electrode disposed on the light-emitting layer and electrically connected to the first power wiring, wherein (i) the data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer, and (ii) the first power wiring includes a wiring connection structure formed so that the data main metal layer is recessed more than a side surface of the data capping layer, and the common electrode is electrically connected to the data main metal layer by the wiring connection structure.

[0009] A portion of the protective layer below the via layer may be recessed from the sidewall of the second opening.

[0010] The protective layer may include silicon oxide, silicon nitride, or silicon oxynitride.

[0011] At least a portion of the connection electrode may be disposed on a side surface of the first power supply wiring on the data main metal layer.

[0012] The first power wiring may include a first sidewall that overlaps the first opening and the second opening, respectively, and on which the wiring connection structure is formed, a second sidewall that overlaps the first opening, does not overlap the second opening, and is covered by the passivation layer, and a third sidewall that does not overlap the first opening and the second opening, respectively, and is covered by the via layer.

[0013] The second sidewall and the third sidewall of the first power supply wiring may extend parallel to each other on the side surfaces of the data main metal layer and the data capping layer.

[0014] The connection electrode may be disposed to cover a side surface of the data main metal layer of the first power supply wiring.

[0015] The first power supply wiring may include a wiring opening that penetrates the first power supply wiring, and the first opening and the second opening may be arranged to overlap a portion of the wiring opening.

[0016] The wire connection structure may be formed on a first sidewall of the wire opening, the first sidewall overlapping the first opening and the second opening.

[0017] Among the sidewalls of the wiring opening, the sidewalls that do not overlap with at least one of the first opening and the second opening may be covered by the passivation layer or the via layer, and the sidewalls may be aligned with the side surfaces of the data main metal layer and the data capping layer.

[0018] The semiconductor device may further include a second power supply wiring spaced apart from the first power supply wiring, and the first opening and the second opening may be arranged to overlap one side of the first power supply wiring and not overlap the second power supply wiring.

[0019] The wiring connection structure may be formed in the first power supply wiring at portions overlapping the first opening and the second opening.

[0020] The first power wiring may include a first sub-wiring and a second sub-wiring that are at least partially separated from each other, and the first opening and the second opening may be arranged to overlap one side of the first sub-wiring and not overlap the second sub-wiring.

[0021] The wiring connection structure may be formed in the first sub-wiring at portions overlapping the first opening and the second opening.

[0022] A display device according to one embodiment for solving the above problem includes: (1) a data conductive layer including a first power wiring disposed on a substrate; (2) a passivation layer disposed on the data conductive layer and including a first opening exposing at least a portion of the first power wiring; (3) a protection layer disposed on the passivation layer; (4) a via layer disposed on the protection layer and including a second opening partially overlapping the first opening; (5) a pixel electrode disposed on the via layer and a pixel defining (defining) film disposed on the via layer, at least a portion of which is disposed directly on the protection layer within the second opening and including an opening hole overlapping the second opening; and (6) a pixel defining (defining) film disposed on the pixel defining (defining) film, a light-emitting layer, a portion of which is disposed on the pixel electrode and the connection electrode; and (7) a common electrode disposed on the light-emitting layer and electrically connected to the first power wiring, wherein (i) the data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer, (ii) the protection layer is recessed inward below the pixel definition film, and (iii) the first power wiring includes a wiring connection structure formed such that the data main metal layer is recessed more than the side of the data capping layer, and the common electrode is electrically connected to the data main metal layer by the wiring connection structure.

[0023] According to one embodiment of the present invention, a method for manufacturing a display device includes the steps of: forming a first power wiring on a substrate, the first power wiring including a data base layer, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer; forming a passivation layer disposed on the first power wiring and having a first opening that partially exposes the first power wiring; forming a protective layer disposed on the passivation layer and covering the first power wiring exposed by the first opening; forming a via layer disposed on the protective layer, partially overlapping the first opening, and having a second opening that exposes the protective layer; etching the protective layer exposed through the second opening and etching the exposed portion of the first power wiring to form a wiring connection structure in which the data main metal layer is recessed from the data capping layer; and forming a common electrode disposed on the via layer, at least a portion of which is disposed in the second opening and electrically connected to the data main metal layer of the wiring connection structure.

[0024] The protective layer may include silicon oxide, silicon nitride, or silicon oxynitride.

[0025] The etching of the protection layer may be performed by an isotropic etching process using the via layer as a mask, and the protection layer may be formed so that a portion thereof is recessed below the via layer.

[0026] Before the step of forming the common electrode, the method may further include a step of forming a connection electrode disposed on the via layer and at least a portion of which is disposed within the second opening, and a light-emitting layer disposed on the connection electrode, wherein at least a portion of the connection electrode is disposed on a side of the data main metal layer, and the common electrode is disposed on the connection electrode.

[0027] The method may further include, before the step of etching the protective layer, forming a pixel defining film disposed on the via layer and at least a portion of which is disposed within the second opening, and the step of etching the protective layer may be performed by an isotropic etching process using the pixel defining film as a mask.

[0028] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0029] According to an embodiment, a display device may include a protective layer formed by an organic insulating material during a manufacturing process to prevent oxidation of a metal layer of a power wiring. When forming a power wiring electrically connected to a common electrode in a display area, the protective layer protects the metal layer of the power wiring, thereby preventing poor electrical connection between the common electrode and the power wiring.

[0030] In the display device, the connection structure is formed within the display area, and a voltage drop in the potential applied to the common electrode can be prevented.

[0031] The effects of the embodiments are not limited to the above-mentioned examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a schematic perspective view of a display device according to an embodiment; [Figure 2] 2 is a cross-sectional view taken along the line X1-X1' in FIG. [Figure 3] 1 is a schematic cross-sectional view of a display device according to an embodiment. [Figure 4] 1 is a pixel circuit diagram of a display device according to an embodiment; [Figure 5] 1 is a cross-sectional view illustrating a portion of a display substrate of a display device according to an embodiment. [Figure 6] FIG. 2 is a plan view showing a portion of power supply wiring of a display device according to an embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII′ in FIG. 6. [Figure 8] FIG. 8 is an enlarged view of part A in FIG. 7. [Figure 9] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 15] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 16] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 17] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 18] 1A to 1C are diagrams illustrating stages in a manufacturing process of a display device according to an embodiment. [Figure 19] FIG. 10 is a plan view showing a part of a power supply wiring of a display device according to another embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX′ in FIG. 19. [Figure 21] 20A to 20C are diagrams showing stages in the manufacturing process of the display device of FIG. 19. [Figure 22] 20A to 20C are diagrams showing stages in the manufacturing process of the display device of FIG. 19. [Figure 23] 20A to 20C are diagrams showing stages in the manufacturing process of the display device of FIG. 19. [Figure 24] FIG. 10 is a cross-sectional view showing a portion of a power supply wiring of a display device according to another embodiment. [Figure 25] 25A to 25C are cross-sectional views showing a part of the manufacturing process of the display device of FIG. 24. [Figure 26] 25A to 25C are cross-sectional views showing a part of the manufacturing process of the display device of FIG. 24. [Figure 27] 25A to 25C are cross-sectional views showing a part of the manufacturing process of the display device of FIG. 24. [Figure 28] FIG. 10 is a plan view showing a part of a power supply wiring of a display device according to another embodiment. [Figure 29] FIG. 29 is a cross-sectional view taken along the line N1-N1′ in FIG. 28. [Figure 30] FIG. 10 is a plan view showing a portion of power supply wiring of a display device according to a further embodiment. [Figure 31] 31 is a cross-sectional view taken along the line N2-N2' in FIG. 30. [Figure 32] 10 is a cross-sectional view showing a wiring connection structure of a display device according to another embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0033] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0034] When an element or layer is referred to as being "on" another element or layer, this includes being immediately above or between other elements, with other layers or elements intervening. Similarly, when referred to as being "below," "left," and "right," this includes being immediately adjacent to another element, or with other layers or materials intervening. Like reference numerals throughout the specification refer to like elements.

[0035] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0036] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0037] 1 is a schematic perspective view of a display device according to an embodiment, and FIG. 2 is a cross-sectional view taken along line X1-X1' in FIG.

[0038] 1 and 2, a display device 1 displays moving or still images. The display device 1 refers to any electronic device that provides a display screen. For example, the display device 1 may include a television, a laptop computer, a monitor, a billboard, the Internet of Things, a mobile phone, a smartphone, a tablet PC (Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, a game console, a digital camera, a camcorder, and the like that provide a display screen.

[0039] Examples of the display device 1 include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, etc. In the following, an organic light emitting diode display device will be described as an example of the display device 1, but the present invention is not limited thereto and may be applied to other display devices as long as the same technical concept is applicable.

[0040] The shape of the display device 1 can be varied in various ways. For example, the display device 1 can have a horizontally long rectangle, a vertically long rectangle, a square, a rectangle with rounded corners (vertices), other polygonal shapes, a circle, or the like. The shape of the display area DA of the display device 1 can also be similar to the overall shape of the display device 1. FIGS. 1 and 2 illustrate a display device 1 having a rectangular shape extending in a first direction DR1 and a second direction DR2. Here, a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2 can be the thickness direction of the display device 1.

[0041] The display device 1 may include a display area DA and a non-display area NDA. The display area DA is the area where the screen is displayed, and the non-display area NDA is the area where the screen is not displayed. The display area DA is also called the active area, and the non-display area NDA is also called the inactive area. The display area DA may generally occupy the center of the display device 1.

[0042] The display device 1 includes a display substrate 10, a color conversion substrate 20 facing the display substrate 10, and may further include a sealing part 50 that connects the display substrate 10 and the color conversion substrate 20, and a filler 70 filled between the display substrate 10 and the color conversion substrate 20.

[0043] The display substrate 10 may include elements and circuits for displaying images, for example, pixel circuits such as switching elements, and pixel defining layers and self-light emitting elements that define light emitting regions and non-light emitting regions in the display area DA (described later). In an exemplary embodiment, the self-light emitting elements may include at least one of organic light emitting diodes, quantum dot light emitting diodes, inorganic-based micro light emitting diodes (e.g., micro LEDs), and inorganic-based nano-sized light emitting diodes (e.g., nano LEDs). For convenience of explanation, the following description will be given assuming that the self-light emitting elements are organic light emitting elements.

[0044] The color conversion substrate 20 is located on the display substrate 10 and faces the display substrate 10. In some embodiments, the color conversion substrate 20 may include a color conversion pattern layer that converts the color of incident light. In some embodiments, the color conversion substrate 20 may include at least one of a color filter and a wavelength conversion pattern layer as the color conversion pattern layer. In some embodiments, the color conversion substrate 20 may include both the color filter and the wavelength conversion pattern layer.

[0045] In the non-display area NDA, a sealing unit 50 may be located between the display substrate 10 and the color conversion substrate 20. The sealing unit 50 may be arranged along the edges of the display substrate 10 and the color conversion substrate 20 in the non-display area NDA and may surround the display area DA on a plane. The display substrate 10 and the color conversion substrate 20 may be coupled to each other via the sealing unit 50.

[0046] In some embodiments, the sealing member 50 is made of an organic material. For example, the sealing member 50 may be made of an epoxy resin, but is not limited thereto.

[0047] In some embodiments, the sealing portion 50 is positioned to overlap the thin film encapsulation layer ENC of the display substrate 10. In other words, the sealing portion 50 may be positioned between the thin film encapsulation layer ENC and the color conversion substrate 20 in the non-display area NDA. In some embodiments, the sealing portion 50 may be in direct contact with the thin film encapsulation layer ENC.

[0048] A filler 70 is positioned in the space between the display substrate 10 and the color conversion substrate 20, which is surrounded by the sealing portion 50. The filler 70 fills the space between the display substrate 10 and the color conversion substrate 20.

[0049] In some embodiments, filler 70 is made of a light-transmitting material. In some embodiments, filler 70 is made of an organic material. Exemplary filler 70 may be made of a silicon-based organic material, an epoxy-based organic material, or a mixture of a silicon-based organic material and an epoxy-based organic material.

[0050] In some embodiments, the filler 70 is made of a material having an extinction coefficient of substantially zero. The refractive index and the extinction coefficient are correlated, and the extinction coefficient decreases as the refractive index decreases. When the refractive index is 1.7 or less, the extinction coefficient can converge to substantially zero. In some embodiments, the filler 70 is made of a material having a refractive index of 1.7 or less, thereby preventing or minimizing absorption of light provided by the self-luminous element through the filler 70. In some embodiments, the filler 70 is made of an organic material having a refractive index of 1.4 to 1.7.

[0051] 3 is a schematic cross-sectional view of a display device according to an embodiment, showing the schematic cross-sectional structures of a display substrate 10 and a color conversion substrate 20.

[0052] Referring to Figure 3, a top-emission display device is shown in which light L is emitted in the opposite direction (towards the second substrate 21) rather than towards the first substrate 11 on which the light-emitting layer EML is formed, but the display device 1 is not limited to this.

[0053] 2, the display device 1 may include an emitting layer EML, a thin-film encapsulation layer ENC covering the emitting layer EML, wavelength conversion layers WCL1 and WCL2 disposed above the thin-film encapsulation layer ENC, and a transparent layer TPL. In one embodiment, the display device 1 may include a display substrate 10 and a color conversion substrate 20 facing the display substrate 10. The emitting layer EML, thin-film encapsulation layer ENC, wavelength conversion layers WCL1 and WCL2, and transparent layer TPL may be included in either the display substrate 10 or the color conversion substrate 20.

[0054] For example, the display substrate 10 may include a first substrate 11, an emitting layer EML disposed on one surface of the first substrate 11, and a thin-film encapsulation layer ENC disposed on the emitting layer EML. The color conversion substrate 20 may include a second substrate 21, and wavelength conversion layers WCL1 and WCL2 and a transparent layer TPL disposed on one surface of the second substrate 21 facing the first substrate 11.

[0055] A filler 70 is disposed between the thin film encapsulation layer ENC and the wavelength conversion layers WCL1, WCL2 and the light-transmitting layer TPL. The filler 70 can bond the display substrate 10 and the color conversion substrate 20 together while filling the space between them.

[0056] The first substrate 11 of the display substrate 10 may be an insulating substrate. The first substrate 11 may include a transparent material. For example, the first substrate 11 may include a transparent insulating material such as glass or quartz. The first substrate 11 may be a rigid substrate. However, the first substrate 11 is not limited to the above examples. The first substrate 11 may include a plastic such as polyimide, and may have flexible properties that allow it to bend, fold, and roll.

[0057] A plurality of pixel electrodes PXE are arranged on one surface of the first substrate 11. A plurality of pixel electrodes PXE are arranged for each light-emitting area EMA. The pixel electrodes PXE of adjacent light-emitting areas EMA are separated from each other. A circuit layer CCL is arranged on the first substrate 11. The circuit layer CCL is arranged between the first substrate 11 and the pixel electrodes PXE. A detailed description of the circuit layer CCL will be given later.

[0058] The pixel electrode PXE may be a first electrode, e.g., an anode electrode, of the light-emitting diode. The pixel electrode PXE may have a stacked film structure in which a high-work-function material layer, such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and a reflective material layer, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof, are stacked. The high-work-function material layer may be disposed above the reflective material layer and adjacent to the light-emitting layer EML. The pixel electrode PXE may have a multi-layer structure such as, but not limited to, ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO.

[0059] The pixel defining layer PDL is disposed on one surface of the first substrate 11. The pixel defining layer PDL is disposed on the pixel electrode PXE and may include an aperture that exposes the pixel electrode PXE. The aperture that exposes the pixel electrode PXE may be defined to penetrate the pixel defining layer PDL. The pixel defining layer PDL and its aperture separate the emissive area EMA from the non-emissive area NEM. The pixel defining layer PDL may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). The pixel-defining (defining) layer PDL may also comprise an inorganic material.

[0060] The emitting layer EML is disposed on the pixel defining layer PDL. The emitting layer EML is disposed on each pixel electrode PXE within the opening of the pixel defining layer PDL, and is disposed so as to cover the upper surface of the pixel defining layer PDL. Unlike the pixel electrodes PXE, the emitting layers EML in different emitting regions EMA may not be separated but may form a common layer. In one embodiment, when the display device 1 is an organic light-emitting display device, the emitting layer EML may include an organic layer containing an organic material. The organic layer may include an organic emitting layer and, optionally, may further include a hole injection / transport layer and / or an electron injection / transport layer as an auxiliary layer for assisting light emission. In another embodiment, when the display device 1 is a micro LED display device, a nano LED display device, or the like, the emitting layer EML may include an inorganic material such as an inorganic semiconductor.

[0061] In some embodiments, the emissive layer EML may have a tandem structure including multiple organic emissive layers stacked in the thickness direction and a charge generation layer disposed therebetween. The stacked organic emissive layers may emit light of the same wavelength or different wavelengths. At least some of the layers of the emissive layer EML of each pixel PX may be separated from the same layers of adjacent pixels PX.

[0062] In one embodiment, the wavelength of light emitted by each light-emitting layer EML may be the same for each color light-emitting region EMA. For example, if the light-emitting layer EML of each color pixel PX emits blue light or ultraviolet light and the color conversion substrate 20 includes a wavelength conversion layer WCL and a transparent layer TPL, each light-emitting region EMA can display a different color.

[0063] In another embodiment, the wavelength of light emitted by each emitting layer EML may be different for each different emitting region EMA. For example, the emitting layer EML in the first emitting region may emit a first color, the emitting layer EML in the second emitting region may emit a second color, and the emitting layer EML in the third emitting region may emit a third color. In this case, the emitting layers EML in the different emitting regions EMA may be separated from each other and may be disposed within openings in the pixel defining layer PDL.

[0064] The common electrode CME is disposed on the light-emitting layer EML. The common electrode CME is connected to each of the light-emitting regions EMA without distinction. The common electrode CME may be a full-surface electrode disposed across the entire light-emitting region EMA without distinction. The common electrode CME may be a second electrode, such as a cathode electrode, of the light-emitting diode.

[0065] The common electrode CME may include a layer of a material having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The common electrode CME may further include a transparent metal oxide layer disposed on the layer of the material having a low work function.

[0066] The pixel electrode PXE, the emitting layer EML, and the common electrode CME can form a light-emitting element (for example, an organic light-emitting element). Light emitted from the emitting layer EML is emitted upward via the common electrode CME.

[0067] The thin-film encapsulation layer ENC is disposed on the common electrode CME. The thin-film encapsulation layer ENC may include at least one thin-film encapsulation layer. For example, the thin-film encapsulation layer may include a first inorganic film ENC1, an organic film ENC2, and a second inorganic film ENC3. The first inorganic film ENC1 and the second inorganic film ENC3 may each include silicon nitride, silicon oxide, or silicon oxynitride. The organic film ENC2 may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0068] The color conversion substrate 20 is disposed above the thin film encapsulation layer ENC to face the display substrate 10. The second substrate 21 of the color conversion substrate 20 may include a transparent material. The second substrate 21 may include a transparent insulating material such as glass or quartz. The second substrate 21 may be a rigid substrate. However, the second substrate 21 is not limited to the above examples. The second substrate 21 may include a plastic such as polyimide, and may have flexible properties that allow it to bend, fold, and roll.

[0069] The second substrate 21 may be the same substrate as the first substrate 11, but may be made of a different material, thickness, transmittance, etc. For example, the second substrate 21 may have a higher transmittance than the first substrate 11. The second substrate 21 may be thicker or thinner than the first substrate 11.

[0070] A light blocking member BM is disposed on one surface of the second substrate 21 facing the first substrate 11 along the boundary of the light emitting region EMA. The light blocking member BM overlaps the pixel defining layer PDL of the display substrate 10 and is located in the non-light emitting region NEM. The light blocking member BM may include openings that expose one surface of the second substrate 21 that overlaps the light emitting region EMA. The light blocking member BM may be formed in a grid shape in a plan view.

[0071] The light-blocking member BM is made of an organic material. The light-blocking member BM can absorb external light to reduce color distortion caused by external light reflection. The light-blocking member BM also serves to prevent light emitted from the light-emitting layer EML from penetrating into the adjacent light-emitting region EMA.

[0072] In one embodiment, the light blocking member BM can absorb all visible light wavelengths. The light blocking member BM can include a light-absorbing material. For example, the light blocking member BM is made of a material used as a black matrix of the display device 1.

[0073] In other embodiments, the light blocking member BM can absorb light of a specific wavelength among visible light wavelengths and transmit light of other specific wavelengths. For example, the light blocking member BM can include the same material as one of the color filter layers CFL. In one embodiment, the light blocking member BM is made of the same material as the blue color filter layer (see "CFL3"). In some embodiments, the light blocking member BM can be formed integrally with the blue color filter layer. However, this is not limiting, and the light blocking member BM can also be omitted.

[0074] The color filter layer CFL is disposed on one surface of the second substrate 21 on which the light blocking member BM is disposed. The color filter layer CFL is disposed on one surface of the second substrate 21 exposed through the opening of the light blocking member BM. Furthermore, a portion of the color filter layer CFL may also be disposed on an adjacent light blocking member BM.

[0075] The color filter layer CFL may include a first color filter layer CFL1 disposed in the first light-emitting region, a second color filter layer CFL2 disposed in the second light-emitting region, and a third color filter layer CFL3 disposed in the third light-emitting region. Each color filter layer CFL may include a colorant such as a dye or pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Although the drawings illustrate a case where adjacent color filter layers CFL are spaced apart from each other on the light-blocking member BM, adjacent color filter layers CFL may also at least partially overlap on the light-blocking member BM.

[0076] The first capping layer 22 is disposed on the color filter layer CFL. The first capping layer 22 prevents impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color filter layer CFL. The first capping layer 22 also prevents colorants in the color filter layer CFL from diffusing into different components.

[0077] The first capping layer 22 is in direct contact with one surface (the lower surface in FIG. 2) of the color filter layer CFL. The first capping layer 22 is made of an inorganic material. For example, the first capping layer 22 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, silicon oxynitride, etc.

[0078] The partition walls PTL may be disposed on the first capping layer 22. The partition walls PTL are located in the non-light-emitting regions NEM. The partition walls PTL may be disposed to overlap the light-blocking members BM. The partition walls PTL may include openings that expose the color filter layers CFL. The partition walls PTL may include, but are not limited to, a photosensitive organic material. The partition walls PTL may further include a light-blocking material.

[0079] The wavelength conversion layer WCL and / or the light-transmitting layer TPL are disposed in the spaces exposed by the openings of the partition walls PTL. The wavelength conversion layer WCL and the light-transmitting layer TPL may be formed by an inkjet process using the partition walls PTL as banks, but are not limited to this.

[0080] In an embodiment in which the light-emitting layer EML emits a third color, the wavelength-converting layer WCL may include a first wavelength-converting pattern WCL1 disposed in the first light-emitting region and a second wavelength-converting pattern WCL2 disposed in the second light-emitting region, and a transparent layer TPL may be disposed in the third light-emitting region.

[0081] The first wavelength-converting pattern WCL1 may include a first base resin BRS1 and a first wavelength-converting material WCP1 disposed within the first base resin BRS1. The second wavelength-converting pattern WCL2 may include a second base resin BRS2 and a second wavelength-converting material WCP2 disposed within the second base resin BRS2. The transparent layer TPL may include a third base resin BRS3 and a scatterer SCP disposed therein.

[0082] The first, second, and third base resins BRS1, BRS2, ​​and BRS3 may include a light-transmitting organic material. For example, the first, second, and third base resins BRS1, BRS2, ​​and BRS3 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first, second, and third base resins BRS1, BRS2, ​​and BRS3 may all be made of the same material, but are not limited thereto.

[0083] The scatterer SCP may be metal oxide particles or organic particles. Examples of the metal oxide include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), and tin oxide (SnO2). Examples of the organic particle material include acrylic resin and urethane resin.

[0084] The first wavelength conversion material WCP1 may convert a third color to a first color, and the second wavelength conversion material WCP2 may convert a third color to a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP to improve wavelength conversion efficiency.

[0085] The transparent layer TPL disposed in the third light-emitting region transmits the third color light incident from the light-emitting layer EML while maintaining its wavelength. The scatterers SCP of the transparent layer TPL can adjust the emission path of the light emitted through the transparent layer TPL. The transparent layer TPL does not need to include a wavelength conversion material.

[0086] The second capping layer 23 is disposed on the wavelength conversion layer WCL and the transparent layer TPL. The second capping layer 23 is made of an inorganic material. The second capping layer 23 includes a material selected from the materials listed as the materials for the first capping layer 22. The second capping layer 23 and the first capping layer 22 may be made of the same material, but are not limited to this.

[0087] A filler 70 is disposed between the display substrate 10 and the color-conversion substrate 20. The filler 70 fills the space between the display substrate 10 and the color-conversion substrate 20 and also serves to bond them together. The filler 70 is disposed between the thin-film encapsulation layer ENC of the display substrate 10 and the second capping layer 23 of the color-conversion substrate 20. The filler 70 may be made of a silicon-based organic material, an epoxy-based organic material, or the like, but is not limited thereto.

[0088] FIG. 4 is a pixel circuit diagram of a display device according to an embodiment.

[0089] Referring to FIG. 4, a display device 1 according to an embodiment may include a light emitting element ED, three transistors T1, T2, T3, and one storage capacitor Cst for each pixel.

[0090] The light emitting element ED emits light in response to a current supplied via the first transistor T1. The light emitting element ED includes a first electrode, a second electrode, and at least one light emitting element disposed therebetween. The light emitting element can emit light in a specific wavelength band in response to an electrical signal transmitted from the first electrode and the second electrode.

[0091] One end of the light-emitting element ED is connected to the source electrode of the first transistor T1, and the other end can be connected to a second voltage wiring VSL to which a low potential voltage (hereinafter, the second power supply voltage) lower than the high potential voltage (hereinafter, the first power supply voltage) of the first voltage wiring VDL is supplied.

[0092] The first transistor T1 adjusts a current flowing from a first voltage line VDL to which a first power supply voltage is supplied to the light emitting element ED according to a voltage difference between the gate electrode and the source electrode. As an example, the first transistor T1 may be a driving transistor for driving the light emitting element ED. The gate electrode of the first transistor T1 may be connected to a source electrode of the second transistor T2, the source electrode may be connected to a first electrode of the light emitting element ED, and the drain electrode may be connected to the first voltage line VDL to which the first power supply voltage is applied.

[0093] The second transistor T2 is turned on by the scan signal of the first scan line SL1 to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the first scan line SL1, the source electrode is connected to the gate electrode of the first transistor T1, and the drain electrode is connected to the data line DTL.

[0094] The third transistor T3 is turned on by a scan signal of the second scan line SL2 to connect the initialization voltage line VIL to one end of the light emitting element ED, and has a gate electrode connected to the second scan line SL2, a drain electrode connected to the initialization voltage line VIL, and a source electrode connected to one end of the light emitting element ED or the source electrode of the first transistor T1.

[0095] In one embodiment, the source and drain electrodes of each of the transistors T1, T2, and T3 are not limited to those described above, and may be reversed. Furthermore, each of the transistors T1, T2, and T3 may be formed as a thin film transistor. Although FIG. 3 mainly illustrates the case where each of the transistors T1, T2, and T3 is formed as an N-type metal oxide semiconductor field effect transistor (MOSFET), this is not limiting. That is, each of the transistors T1, T2, and T3 may be formed as a P-type MOSFET, or some of the transistors may be formed as N-type MOSFETs and the other parts may be formed as P-type MOSFETs.

[0096] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1 and stores the difference voltage between the gate voltage and the source voltage of the first transistor T1.

[0097] 3, the gate electrode of the second transistor T2 may be connected to the first scan line SL1, and the gate electrode of the third transistor T3 may be connected to the second scan line SL2. The first scan line SL1 and the second scan line SL2 may be different scan lines, and the second transistor T2 and the third transistor T3 may be turned on by scan signals applied to the different scan lines, but are not limited thereto.

[0098] In some embodiments, the gate electrodes of the second transistor T2 and the third transistor T3 may be connected to the same scan line, and the second transistor T2 and the third transistor T3 may be turned on simultaneously by a scan signal applied to the same scan line.

[0099] 5 is a cross-sectional view of a display substrate of a display device according to an embodiment, showing the cross-sectional structure of a light-emitting element ED and a circuit layer CCL disposed in a light-emitting area EMA of a display substrate 10.

[0100] 5, the circuit layer CCL includes a semiconductor layer 150, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 11. The semiconductor layer 150 may include an oxide semiconductor. The plurality of conductive layers may include a lower metal layer 120, a gate conductive layer 130, a data conductive layer 140, and a pixel electrode PXE. The plurality of insulating layers may include a buffer layer 161, a gate insulating layer 162, an interlayer insulating layer 163, a passivation layer 164, a protective layer 165, and a via layer 166.

[0101] The lower metal layer 120 is disposed on the first substrate 11. The lower metal layer 120 may be a light-shielding layer that protects the semiconductor layer 150 from external light. The lower metal layer 120 has a patterned shape. The lower metal layer 120 may be disposed in the transistor region TRR. The lower metal layer 120 may be disposed from below to cover at least the channel region of the upper semiconductor layer 150, and may further be disposed to cover the entire semiconductor layer 150. The lower metal layer 120 is electrically connected to the source electrode SEL of the driving transistor through the first contact hole CNT1, and may function to suppress changes in the voltage of the driving transistor. The lower metal layer 120 may be formed of a Ti / Cu bilayer in which a titanium layer and a copper layer are stacked, but is not limited thereto.

[0102] The buffer layer 161 is disposed on the lower metal layer 120. The buffer layer 161 is disposed to cover the entire surface of the first substrate 11 on which the lower metal layer 120 is formed. The buffer layer 161 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. In one embodiment, the buffer layer 161 is SiN x / SiO x The membrane may comprise a double membrane.

[0103] The semiconductor layer 150 is disposed on the buffer layer 161. The semiconductor layer 150 is disposed in the transistor region TRR and forms a channel region of the transistor. The semiconductor layer 150 includes an oxide semiconductor. The oxide semiconductor is, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), or the like. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z In one embodiment, semiconductor layer 150 comprises indium tin zinc oxide (IGZO).

[0104] A gate insulating layer 162 may be disposed on the semiconductor layer 150. The gate insulating layer 162 may be formed in the same pattern as the gate conductive layer 130 described below. The sidewalls of the gate insulating layer 162 may be generally aligned with the sidewalls of the gate conductive layer 130, but are not limited thereto. The gate insulating layer 162 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 162 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In one embodiment, the gate insulating layer 162 is made of SiO x The membrane comprises:

[0105] The gate conductive layer 130 is disposed on the gate insulating layer 162. The gate electrode GEL of the transistor region TRR is made of the gate conductive layer 130. In the drawing, the gate conductive layer 130 is illustrated as having a single layer structure, but is not limited to this. The gate conductive layer 130 may be made of one or more layers, similar to the data conductive layer 140 described below. The gate conductive layer 130 may include titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), nickel (Ni), copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), IZO, ITO, IZTO, etc.

[0106] An interlayer insulating layer 163 is disposed on the gate conductive layer 130. The interlayer insulating layer 163 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc. In one embodiment, the interlayer insulating layer 163 is made of SiO x N y The compound comprises:

[0107] The data conductive layer 140 is disposed on the interlayer insulating layer 163. The source electrode SEL and the drain electrode DEL of the transistor region TRR are formed of the data conductive layer 140. The source electrode SEL and the drain electrode DEL may be connected to the semiconductor layer 150 via second contact holes CNT2 that penetrate the interlayer insulating layer 163. The source electrode SEL may also be connected to the lower metal layer 120 via first contact holes CNT1 that penetrate the interlayer insulating layer 163 and the buffer layer 161.

[0108] The data conductive layer 140 may have a stacked structure including a data conductive metal layer 141 and a data capping layer 142 disposed on the data conductive metal layer 141. The data conductive metal layer 141 may be formed of a single layer or multiple layers. For example, the data conductive metal layer 141 may further include a data base layer 141b disposed below the data main metal layer 141a in addition to a data main metal layer 141a. The data base layer 141b, the data main metal layer 141a, and the data capping layer 142 are all made of conductive materials. No insulating layer is interposed between the respective constituent layers of the data conductive layer 140 that overlap in the thickness direction. The data base layer 141b, the data main metal layer 141a, and the data capping layer 142 may be patterned using a single mask process. In one embodiment, sidewalls of the respective constituent layers may be aligned with each other. In some embodiments, the sidewalls of the upper layers constituting the data conductive layer 140 do not protrude outward compared to the lower layers. That is, the data conductive layer 140 may not include a protruding tip structure of the upper layer. In such embodiments, the sidewalls of the lower layers of the data conductive layer 140 may be aligned or protrude outward relative to the sidewalls of the upper layers.

[0109] In the display device 1 according to an embodiment, the data capping layer 142 of the data conductive layer 140, which contacts the common electrode CME of the light emitting element ED in the non-light emitting region NEM, may include a protruding end portion protruding from a sidewall of the data main metal layer 141a. In the display device 1, the common electrode CME disposed over the entire surface of the display area DA contacts the data conductive layer 140 in the non-light emitting region NEM of the display area DA, and the common electrode CME may contact the data main metal layer 141a below the protruding end portion of the data conductive layer 140. This will be described in more detail below.

[0110] The data base layer 141b may improve the deposition properties, such as adhesion, of the data main metal layer 141a or prevent reactive substances from penetrating into the data main metal layer 141a from the underlying interlayer insulating layer 163. The data base layer 141b may include a transparent electrode containing a metal material such as titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni), or an alloy thereof, or any one of indium (In), zinc (Zn), tin (Sn), gallium (Ga), and aluminum (Al). For example, the data base layer 141b may include titanium (Ti), but is not limited to this.

[0111] The data main metal layer 141a mainly plays a role in transmitting signals and is made of a low-resistance material. The data main metal layer 141a has a thickness greater than that of the data base layer 141b and the data capping layer 142 and is made of a material with lower resistance. The data main metal layer 141a may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), molybdenum (Mo), etc. In one embodiment, the data main metal layer 141a may include copper (Cu).

[0112] The data capping layer 142 covers and protects the data main metal layer 141a from above. The data capping layer 142 can protect the data main metal layer 141a from layers disposed above the data conductive layer 140 and from etchants and other chemicals used during the manufacturing process (e.g., the process of forming the third contact hole CNT3). It also prevents the upper via layer 166 from directly contacting the data main metal layer 141a during the process, thereby preventing the data main metal layer 141a from being corroded by the material of the via layer 166. The data capping layer 142 can also prevent the material (e.g., copper) forming the data main metal layer 141a from diffusing into the adjacent upper layer. The data capping layer 142 can be in direct contact with the data main metal layer 141a.

[0113] The data capping layer 142 may include a transparent electrode such as ITO, IZO, IZTO, IGTO, GZO, or GZTO. Alternatively, the data capping layer 142 may include both the transparent electrode and an alloy of titanium (Ti) and molybdenum (Mo). For example, the data capping layer 142 may be composed of a multilayer such as Ti / Mo / ITO. In one embodiment, the data conductive layer 140 may include a triple layer of Ti / Cu / ITO or may have a stacked structure of Ti / Cu / Ti / Mo / ITO.

[0114] The passivation layer 164 is disposed on the data conductive layer 140. The passivation layer 164 serves to cover and protect the data conductive layer 140. The passivation layer 164 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

[0115] The protective layer 165 is disposed on the passivation layer 164. The protective layer 165 can serve to protect the data conductive layer 140 together with the passivation layer 164.

[0116] In one embodiment, the protective layer 165 may prevent oxide formation due to contact between the data conductive layer 140 and the via layer 166 thereover during the process of forming a wiring connection structure, which will be described later. When forming a wiring connection structure in which the common electrode CME and the data conductive layer 140 are in contact with each other, the protective layer 165 is disposed to cover the data conductive layer 140, thereby preventing the organic material of the via layer 166 from directly contacting the data conductive layer 140. The protective layer 165 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. While the protective layer 165 is illustrated as being formed as a single layer in the drawings, the present invention is not limited thereto. The protective layer 165 may also be formed as a double layer or a multi-layer (stacked layer) containing the above materials.

[0117] The via layer 166 is disposed on the protective layer 165. The via layer 166 may include an organic insulating material to planarize the upper surface. The via layer 166 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). The via layer 166 may further include, but is not limited to, a photosensitive material. In one embodiment, the via layer 166 includes polyimide.

[0118] The pixel electrode PXE is disposed on the via layer 166. The material constituting the pixel electrode PXE is as described with reference to Figure 3. In one embodiment, the pixel electrode PXE comprises a triple layer of ITO / Ag / ITO.

[0119] The pixel electrode PXE is disposed in the display area DA, but not in the non-display area NDA. The pixel electrode PXE may overlap the transistor region TRR and the capacitor region CPR in the display area DA, but is not limited to this. The pixel electrode PXE may be connected to the source electrode SEL of the driving transistor through a third contact hole CNT3 that penetrates the via layer 166, the protective layer 165, and the passivation layer 164.

[0120] The pixel defining layer PDL is disposed on the pixel electrode PXE. The material constituting the pixel defining layer PDL is as described with reference to Figure 3. In one embodiment, the pixel defining layer PDL comprises polyimide.

[0121] The pixel definition layer PDL is disposed in the display area DA, but not in the non-display area NDA. The pixel definition layer PDL is disposed so as to overlap the edge of the pixel electrode PXE. The pixel definition layer PDL may also be disposed so as to overlap the third contact hole CNT3. The pixel definition layer PDL may completely fill the internal space of the third contact hole CNT3. The pixel definition layer PDL is also disposed on the via layer 166 where the pixel electrode PXE is not formed.

[0122] The emitting layer EML and the common electrode CME are disposed on the pixel electrode PXE and the pixel defining film PDL. The emitting layer EML and the common electrode CME are disposed over the entire display area DA, and may be disposed on the pixel electrode PXE and the pixel defining film PDL in the emitting area EMA, and on a wiring connection structure (to be described later) in the non-emitting area NEM.

[0123] The common electrode CME may be electrically connected to an external power supply wiring in the non-display area NDA and a low-potential signal may be applied thereto. However, to prevent a voltage drop of a signal applied to the common electrode CME across the entire display area DA, which has a large area, the common electrode CME may also be electrically connected to a power supply wiring to which a low-potential signal is applied within the display area DA. In the display device 1 according to an embodiment, the common electrode CME may be connected to a power supply wiring of the circuit layer CCL in a non-emitting area NEM of the display area DA. The non-emitting area NEM is an area where no light-emitting elements ED are disposed, and the common electrode CME disposed on the pixel defining layer PDL may be electrically connected to a power supply wiring disposed below the via layer 166 through an opening that exposes a portion of the power supply wiring.

[0124] Fig. 6 is a plan view showing a portion of the power supply wiring of a display device according to an embodiment. Fig. 7 is a cross-sectional view taken along line VII-VII' in Fig. 6. Fig. 6 is a plan view showing the overlapping relationship between the common electrode CME and the first power supply wiring VL1 arranged in the non-light-emitting region NEM in the display substrate 10 of the display device 1.

[0125] 6 and 7, the display device 1 according to an embodiment may include a wiring connection structure to which the common electrode CME disposed in the display area DA is electrically connected. The data conductive layer 140 may include a wiring connection structure disposed in the display area DA, and the common electrode CME may be connected to the wiring connection structure of the data conductive layer 140. According to an embodiment, in the display device 1, the first power wiring VL1 of the data conductive layer 140 may include the wiring connection structure, thereby electrically connecting to the common electrode CME. The common electrode CME may be connected to an external power wiring in the non-display area NDA, and may be connected to the first power wiring VL1 in the display area DA to apply a low potential signal.

[0126] The first power wiring VL1 is arranged in the non-light-emitting area NEM of the display area DA. The first power wiring VL1 is arranged around the area where the plurality of pixel electrodes PXE are arranged. The first power wiring VL1 may be arranged to extend to the non-display area NDA, where it may be connected to an external power wiring to apply a low potential voltage. Although the drawing shows a portion of the first power wiring VL1 extending in the first direction DR1, the first power wiring VL1 may be arranged to surround the area where the plurality of pixel electrodes PXE are arranged.

[0127] According to one embodiment, the first power wiring VL1 may include a wiring opening S_CNT penetrating therethrough. The wiring opening S_CNT is formed to penetrate the first power wiring VL1, and a wiring connection structure may be formed on one sidewall of the wiring opening S_CNT of the first power wiring VL1. A passivation layer 164 and a via layer 166 may be disposed on the first power wiring VL1, and one sidewall of the wiring opening S_CNT may be exposed by openings P_CNT and V_CNT between the passivation layer 164 and the via layer 166. A wiring connection structure may be formed on the exposed sidewall. This will be described later.

[0128] The passivation layer 164 is disposed on the data conductive layer 140 and covers the first power line VL1. The passivation layer 164 may include a first opening P_CNT penetrating therethrough. The first opening P_CNT may be formed to have a length measured in the first direction DR1 greater than that of the line opening S_CNT. However, the first opening P_CNT may be formed to partially overlap the line opening S_CNT of the first power line VL1 and not completely expose the line opening S_CNT. For example, the first opening P_CNT may be formed to overlap one sidewall of the line opening S_CNT to expose the one sidewall but not overlap the other sidewall on the opposite side. The first opening P_CNT may be formed so as not to completely overlap the line opening S_CNT. The first power supply wiring VL1 is covered with the passivation layer 164, but a portion around the wiring opening S_CNT may be exposed by the first opening P_CNT. A wiring connection structure may be formed in the portion of the first power supply wiring VL1 exposed by the first opening P_CNT.

[0129] The protective layer 165 is disposed on the passivation layer 164. The protective layer 165 can be penetrated by the second opening V_CNT of the via layer 166 disposed thereon. A portion of the protective layer 165 exposed by the second opening V_CNT of the via layer 166 can be etched and removed, thereby causing a portion of the protective layer 165 to be recessed inside the via layer 166.

[0130] The via layer 166 is disposed on the protective layer 165 and the passivation layer 164. The via layer 166 may include a second opening V_CNT penetrating therethrough. The second opening V_CNT may be formed to have a length measured in the first direction DR1 greater than that of the first opening P_CNT. However, the second opening V_CNT may be formed to partially overlap the first opening P_CNT of the passivation layer 164 and not completely expose the first opening P_CNT. For example, the second opening V_CNT may be formed to overlap one sidewall of the first opening P_CNT, exposing the one sidewall, but not overlapping the other sidewall on the opposite side. The second opening V_CNT may be formed so as not to completely overlap the first opening P_CNT. The passivation layer 164 and the first power wiring VL1 are covered by the via layer 166, but a portion around the first opening P_CNT may be exposed by the second opening V_CNT. A wiring connection structure may be formed in the portion of the first power wiring VL1 exposed by the second opening V_CNT.

[0131] The first power supply wiring VL1 may include, among the inner sidewalls of the wiring opening S_CNT, a first sidewall S1 overlapping each of the openings P_CNT and V_CNT, a second sidewall S2 overlapping the first opening P_CNT but not overlapping the second opening V_CNT, and a third sidewall S3 not overlapping each of the openings P_CNT and V_CNT. The first sidewall S1 may be a sidewall of the first wiring portion VL1a and exposed by the openings P_CNT and V_CNT. The second sidewall S2 and the third sidewall S3 may be sidewalls of the second wiring portion VL1b and covered by the passivation layer 164, the protective layer 165, or the via layer 166.

[0132] According to one embodiment, the first power supply wiring VL1 may include a first wiring portion VL1a which is a portion exposed by the openings P_CNT and V_CNT, and a second wiring portion VL1b which is covered by the passivation layer 164, the protective layer 165, and the via layer 166. The first wiring portion VL1a and the second wiring portion VL1b may each be a portion of the first power supply wiring VL1. The first power supply wiring VL1 may essentially include the first wiring portion VL1a exposed by the openings P_CNT and V_CNT, and the second wiring portion VL1b which is the other portion.

[0133] The connection electrode PBR is disposed on the via layer 166. The connection electrode PBR may be disposed in the same layer as the pixel electrode PXE and may include the same material. The connection electrode PBR may be disposed to overlap the openings P_CNT, V_CNT, and the wiring opening S_CNT. A portion of the connection electrode PBR is disposed on the via layer 166, and another portion is disposed in the openings P_CNT, V_CNT, and the wiring opening S_CNT, and may be disposed on the side of the first power supply wiring VL1, the passivation layer 164, and the via layer 166. The connection electrode PBR may be in contact with the data conductive layer 140 (described later) or a wiring connection structure of the first power supply wiring VL1. Like the protective layer 165 (described later), the connection electrode PBR can prevent oxidation of the data main metal layer 141a of the data conductive layer 140.

[0134] A pixel defining film PDL, an emitting layer EML, and a common electrode CME may be disposed on the connecting electrode PBR. The pixel defining (defining) film PDL may be formed to expose the second opening V_CNT in addition to the pixel electrode PXE. Alternatively, the pixel defining (defining) film PDL may include an opening hole that exposes the second opening V_CNT. Since the emitting layer EML and the common electrode CME are disposed over the entire display area DA, they may be disposed on the connecting electrode PBR that is exposed because the pixel defining (defining) film PDL is not disposed.

[0135] FIG. 8 is an enlarged view of part A in FIG.

[0136] Referring to FIG. 8 in addition to FIGS. 6 and 7, a display device 1 according to an embodiment may include a wiring connection structure formed on the data conductive layer 140 or the first power wiring VL1, in which the data main metal layer 141a is recessed inward relative to the data capping layer 142. The wiring connection structure may include a tip of the data capping layer 142 protruding from a side edge of the data main metal layer 141a. The tip of the data capping layer 142 may partially disconnect the connection electrodes PBR, the emission layer EML, and the common electrode CME arranged in the openings P_CNT and V_CNT. The connection electrodes PBR, the emission layer EML, and the common electrode CME may each be partially disposed on the tip of the data capping layer 142, and the disconnected portions may be disposed below the tip. The connection electrode PBR, the emission layer EML, and the common electrode CME may be in contact with the side surfaces of the data main metal layer 141a exposed below the tips. The common electrode CME may be in contact with the data main metal layer 141a in the first wiring portion VL1a of the first power supply wiring VL1, thereby being electrically connected thereto. A low potential voltage may be applied to the common electrode CME via the first power supply wiring VL1, and a voltage drop may be prevented by applying the low potential voltage within the display area DA.

[0137] A wiring connection structure including a tip of the data capping layer 142 may be formed only on the first wiring portion VL1a of the first power supply wiring VL1. The first power supply wiring VL1 may have a wiring connection structure formed only on the first sidewall S1 exposed by the openings P_CNT and V_CNT in the wiring opening S_CNT, but not on the second sidewall S2 or the third sidewall S3. That is, the first power supply wiring VL1 may have a tip formed only on the first wiring portion VL1a including the first sidewall S1 in the wiring opening S_CNT, while the second wiring portion VL1b including the second sidewall S2 and the third sidewall S3 may have a smooth side surface covered by the passivation layer 164 or the via layer 166. The first wiring portion VL1a may have an exposed side surface of the data main metal layer 141a, but the second wiring portion VL1b may not. The common electrode CME may be partially disconnected and in contact with the data main metal layer 141a by a tip formed on the first sidewall S1 of the first power wiring VL1. When a tip is formed on each sidewall of the wiring opening S_CNT, the portion of the common electrode CME that contacts the data main metal layer 141a may be disposed independently within the wiring opening S_CNT and may not be electrically connected to the common electrode CME of the light-emitting element ED. Therefore, the positions and sizes of the openings P_CNT and V_CNT can be designed so that the tip is formed only on the first sidewall S1 of the wiring opening S_CNT.

[0138] According to an embodiment, the display device 1 includes a protection layer 165 disposed on the data conductive layer 140, which can prevent the data main metal layer 141a of the data conductive layer 140 from contacting the via layer 166 or the pixel defining layer PDL during the process of forming the wiring connection structure. The first sidewall S1 of the wiring opening S_CNT of the first power wiring VL1 is exposed through the passivation layer 164 and the openings P_CNT and V_CNT of the via layer 166, and the data main metal layer 141a can be etched from the data capping layer 142 during the etching process to form the wiring connection structure. In this process, if the data main metal layer 141a with its exposed side surface comes into contact with the via layer 166 or the pixel defining layer PDL, an oxide can be formed on the exposed side surface. For example, in one embodiment in which the data main metal layer 141a includes copper (Cu), copper (Cu) may form copper oxide (CuOx) due to moisture when in contact with an organic insulating material, which may interfere with the electrical connection between the common electrode CME and the data main metal layer 141a.

[0139] To prevent this, the display device 1 may include a protective layer 165 that covers exposed side surfaces of the data conductive layer 140 or the first power wiring VL1 and prevents oxygen from being formed on the side surfaces of the data main metal layer 141a during the process of forming the wiring connection structure. When the via layer 166 including the second opening V_CNT is formed, the protective layer 165 may cover the inner side surfaces of the first power wiring VL1 exposed by the wiring opening S_CNT. Thereafter, during the process of removing the protective layer 165, a portion of the protective layer 165 may be recessed into the via layer 166, and the data main metal layer 141a may also be recessed into the data capping layer 142, thereby forming the wiring connection structure.

[0140] In one embodiment, the display device 1 may include a connection electrode PBR to prevent oxidation of the data main metal layer 141a due to a pixel definition layer PDL formed after the via layer 166. After etching the protective layer 165 to expose the side surfaces of the data main metal layer 141a, the connection electrode PBR may be disposed before forming the pixel definition layer PDL. The connection electrode PBR may contact and cover at least a portion of the side surfaces of the data main metal layer 141a, thereby preventing oxidation of the data main metal layer 141a during the formation of the pixel definition layer PDL. While the drawings illustrate an example in which the connection electrode PBR covers only a portion of the side surfaces of the data main metal layer 141a, this is not limiting. Depending on the process conditions for forming the connection electrode PBR, the side surfaces of the data main metal layer 141a may be completely covered by the connection electrode PBR.

[0141] The display device 1 according to an embodiment may include a wiring connection structure to apply a low potential voltage to the common electrode CME within the display area DA, thereby preventing a voltage drop of the low potential voltage. The display device 1 may include a protection layer 165 disposed on the data conductive layer 140, thereby preventing damage to the data conductive layer 140 during a process of forming the wiring connection structure connected to the common electrode CME.

[0142] The manufacturing process of the display device 1 will be described below with reference to other drawings.

[0143] 9 to 18 are diagrams sequentially showing the manufacturing process of a display device according to one embodiment. 9 to 18 sequentially show the process of forming a wiring connection structure of the display device 1. 9, 11, 13, and 16 show planar structures in the process of forming the wiring connection structure, and 10, 12, 14, 15, 17, and 18 show cross-sectional structures.

[0144] 9 and 10, a first power supply wiring VL1 including a wiring opening S_CNT is formed on an interlayer insulating layer 163. The first power supply wiring VL1 is arranged in a non-light-emitting region NEM in the display area DA where no pixel electrode PXE is arranged. The wiring opening S_CNT is formed to penetrate the first power supply wiring VL1.

[0145] The first power wiring VL1 is included in the data conductive layer 140 and may include a data conductive metal layer 141 and a data capping layer 142 disposed on the data conductive metal layer 141. The structure of the data conductive layer 140 has been described above. The sidewall of the data main metal layer 141a of the first power wiring VL1 may be exposed through the wiring opening S_CNT.

[0146] 11 and 12, a passivation layer 164 including a first opening P_CNT is formed on the first power wiring VL1, and a protective layer 165 is formed on the passivation layer 164. The first opening P_CNT may partially overlap the wiring opening S_CNT. The portion of the first power wiring VL1 that overlaps with the first opening P_CNT may not be covered by the passivation layer 164, but the portion that does not overlap with the first opening P_CNT may be covered by the passivation layer 164. In a portion of the first power wiring VL1, the side surface of the data main metal layer 141a may not be covered by the passivation layer 164, but in another portion, the side surface of the data main metal layer 141a may be covered by the passivation layer 164.

[0147] The protective layer 165 is disposed on the passivation layer 164, the first power wiring VL1, and the interlayer insulating layer 163. The protective layer 165 may be formed to cover all of the underlying layers without forming a contact hole. The portion of the first power wiring VL1 that overlaps with the first opening P_CNT may be covered by the protective layer 165. For example, the inner sidewall of the portion of the first power wiring VL1 that overlaps with the first opening P_CNT may be protected by the protective layer 165.

[0148] 13 to 15, after a via layer 166 including a second opening V_CNT is formed on a protective layer 165, the protective layer 165 is etched to form a wiring connection structure for the first power wiring VL1.

[0149] The second opening V_CNT may partially overlap with the first opening P_CNT and the wiring opening S_CNT. A portion of the first power supply wiring VL1 that overlaps with the first opening P_CNT and the second opening V_CNT is not covered by the passivation layer 164 or the via layer 166, but a portion that overlaps with the first opening P_CNT and does not overlap with the second opening V_CNT may be covered by the via layer 166. A side surface of the data main metal layer 141a of a portion of the first power supply wiring VL1 is not covered by the passivation layer 164 or the via layer 166, but another portion may have a side surface of the data main metal layer 141a covered by at least one of the passivation layer 164 or the via layer 166.

[0150] Because the via layer 166 includes an organic insulating material, the data conductive layer 140 may be exposed to moisture during the formation process. In particular, the first power line VL1 may have a side surface of the data main metal layer 141a of the data conductive layer 140 exposed through the line opening S_CNT. However, because the display device 1 includes the protective layer 165 that prevents the data main metal layer 141a from being exposed to organic materials or moisture during the manufacturing process, the data main metal layer 141a may be prevented from being oxidized during the formation process of the via layer 166.

[0151] After the via layer 166 is formed, the protective layer 165 is etched using the via layer 166 as a mask to form a wiring connection structure for the first power wiring VL1. According to an embodiment, the process of etching the protective layer 165 in the manufacturing process of the display device 1 may be an isotropic etching process using the via layer 166 as a mask. In this process, a portion of the protective layer 165 may be recessed below the via layer 166. Furthermore, the data main metal layer 141a of the data conductive layer 140 may also be recessed inward from the data capping layer 142, and a tip may be formed in the data conductive layer 140 due to the data capping layer 142. The data base layer 141b has a slower etching rate than the data main metal layer 141a and may have a structure that protrudes beyond the side of the data main metal layer 141a. According to an embodiment, the protective layer 165 may include a material that protects the data main metal layer 141a and is quickly removed by the isotropic etching process. For example, the protective layer 165 can include a material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0152] During the etching process, a wiring connection structure may be formed in a portion of the first power wiring VL1 that overlaps with the openings P_CNT and V_CNT, while no wiring connection structure may be formed in a portion that does not overlap with at least one of the openings P_CNT and V_CNT. For example, a portion of the first power wiring VL1 may become a first wiring portion VL1a having a structure in which the data main metal layer 141a is recessed, and another portion may become a second wiring portion VL1b having smooth side surfaces. The side surface of the first wiring portion VL1a may become a first sidewall S1 on which a wiring connection structure is formed, and the side surface of the second wiring portion VL1b may become a second sidewall S2 or a third sidewall S3 on which no wiring connection structure is formed and which is covered by the passivation layer 164 or the via layer 166.

[0153] 16 to 18, the connection electrode PBR is formed on the via layer 166, and then the pixel defining layer PDL, the light emitting layer EML, and the common electrode CME are formed.

[0154] The connection electrode PBR may be disposed in the same layer as the pixel electrode PXE and may include the same material. The connection electrode PBR may be disposed to cover all of the openings P_CNT, V_CNT, and wiring opening S_CNT, and may be formed to cover the sidewall of the via layer 166, the sidewall of the passivation layer 164, and the sidewall of the first wiring portion VL1a of the first power supply wiring VL1. A portion of the connection electrode PBR may be disposed on a side surface of the data main metal layer 141a of the first wiring portion VL1a. In some embodiments, the connection electrode PBR may cover only a portion of the side surface of the data main metal layer 141a, and the connection may be terminated at the tip of the data capping layer 142. However, this is not limited thereto. The connection electrode PBR may completely cover the side surface of the data main metal layer 141a, and the connection may be terminated at the tip of the data capping layer 142. By having the connection electrode PBR cover at least a portion of the side surface of the data main metal layer 141a, the data main metal layer 141a can be prevented from being oxidized in the process of forming the pixel definition film PDL disposed thereon.

[0155] The light-emitting layer EML and the common electrode CME disposed on the pixel definition film PDL are disposed over the entire display area DA and are disposed so as to cover the connection electrode PBR. A portion of each of the light-emitting layer EML and the common electrode CME is disposed on the side surface of the data main metal layer 141a of the first wiring portion VL1a, and the connection may be interrupted at the tip of the data capping layer 142.

[0156] In an embodiment in which the connection electrode PBR partially covers the side surface of the data main metal layer 141a, at least a portion of the light-emitting layer EML and the common electrode CME may be in direct contact with the side surface of the data main metal layer 141a. However, this is not limitative. In an embodiment in which the connection electrode PBR completely covers the side surface of the data main metal layer 141a, the light-emitting layer EML and the common electrode CME do not directly contact the side surface of the data main metal layer 141a, and the common electrode CME may be electrically connected to the data main metal layer 141a via the connection electrode PBR.

[0157] The common electrode CME is disconnected at its tip, so that a portion thereof remains above the tip, and another portion thereof is electrically connected to the data main metal layer 141a below the tip. As described above, only a portion of the sidewall of the first power supply wiring VL1 includes a wiring connection structure, and the other portion may be covered by the passivation layer 164 or the via layer 166. Therefore, the remaining portion of the common electrode CME disposed within the wiring opening S_CNT is not completely isolated from the portion disposed on the pixel defining (defining) film PDL, and can receive a low potential voltage. Furthermore, because a portion of the sidewall inside the wiring opening S_CNT is covered by the passivation layer 164 or the via layer 166, the slope due to the difference in height from the pixel defining (defining) film PDL to the interlayer insulating layer 163 can be reduced. Therefore, it is possible to prevent the material from being cut off in the process in which the common electrode CME contacts the pixel defining (defining) film PDL with the data main metal layer 141a of the data conductive layer 140.

[0158] Other embodiments of the display device 1 will be described below with reference to other drawings.

[0159] Fig. 19 is a plan view showing a part of the power supply wiring of a display device according to another embodiment, and Fig. 20 is a cross-sectional view taken along line XX-XX' in Fig. 19.

[0160] 19 and 20, in a display device 1_1 according to one embodiment, the same opening V_CNT may penetrate the passivation layer 164_1 and the via layer 166_1. The opening V_CNT may penetrate the passivation layer 164_1 during the formation process of the via layer 166_1, and the inner sidewalls of the passivation layer 164_1 and the via layer 166_1 may be formed parallel to each other. This embodiment differs from the embodiment of FIG. 6 in that the process of forming the opening is shortened, thereby reducing the number of manufacturing steps.

[0161] 21 to 23 are diagrams sequentially showing the manufacturing process of the display device of FIG.

[0162] 21 and 22, the manufacturing process of the display device 1_1 may include a step of sequentially forming a passivation layer 164_1, a protective layer 165, and a via layer 166_1 on the first power wiring VL1 including the wiring opening S_CNT, and then forming an opening V_CNT penetrating these layers. In the display device 1_1, the sidewall of the wiring opening S_CNT of the first power wiring VL1 may be protected by the passivation layer 164_1. The step of forming the opening V_CNT may be performed by an isotropic etching process, and a portion of the protective layer 165 may be recessed into the via layer 166_1. Furthermore, in the same etching process, the data main metal layer 141a may be recessed at a portion of the sidewall of the first power wiring VL1 that overlaps the opening V_CNT, thereby forming a wiring connection structure.

[0163] 23, a connection electrode PBR, an emission layer EML, and a common electrode CME are formed on the opening V_CNT to electrically connect the common electrode CME to the first power wiring VL1 of the data conductive layer 140. The display device 1_1 according to this embodiment can shorten the contact hole formation process.

[0164] FIG. 24 is a cross-sectional view showing a part of a power supply wiring of a display device according to another embodiment.

[0165] 24, in a display device 1_2 according to an embodiment, the process of etching the protective layer 165 may be performed after forming the pixel defining (defining) film PDL_2. A portion of the pixel defining (defining) film PDL_2 is disposed within the second opening V_CNT, and the inner sidewall of the via layer 166 may be covered by the pixel defining (defining) film PDL_2. The pixel defining (defining) film PDL_2 may serve as a mask in the process of etching the protective layer 165, and a portion of the pixel defining (defining) film PDL_2 may be disposed directly on the protective layer 165. Because a wiring connection structure is formed on the first power wiring VL1 after the formation of the pixel defining (defining) film PDL_2, the connection electrode PBR may be omitted. The data main metal layer 141a, whose sidewall is exposed in the first power wiring VL1, may directly contact the emission layer EML and the common electrode CME.

[0166] 25 to 27 are cross-sectional views sequentially showing some of the manufacturing steps of the display device of FIG.

[0167] 25 and 26, in the manufacturing process of the display device 1_2, after forming the passivation layer 164 including the openings P_CNT and V_CNT and the via layer 166, the pixel defining film PDL_2 is formed without etching the protective layer 165. A portion of the pixel defining (defining) film PDL_2 is disposed within the second opening V_CNT, and the first opening P_CNT and the protective layer 165 are disposed so as to be partially exposed. When the pixel defining (defining) film PDL_2 is formed, the sidewall of the first power wiring VL1 is protected by the protective layer 165, so that the data main metal layer 141a can be prevented from being oxidized.

[0168] 27, the protective layer 165 is etched using the pixel definition film PDL_2 as a mask to form a wiring connection structure for the first power wiring VL1. After the wiring connection structure is formed, the light emitting layer EML and the common electrode CME can be formed, and the common electrode CME can be electrically connected to the first power wiring VL1.

[0169] In this process, the wiring connection structure is formed after the pixel definition (definition) film PDL_2 is formed, so the connection electrode PBR can be omitted. Also, since the pixel definition (definition) film PDL_2 is partially disposed within the openings P_CNT and V_CNT, the gradient due to the difference in height from the pixel definition (definition) film PDL_2 to the interlayer insulating layer 163 can be reduced. This makes it possible to reduce discontinuity of the material of the common electrode CME on the pixel definition (definition) film PDL_2.

[0170] In the above embodiment, since the first power supply wiring VL1 includes the wiring opening S_CNT, a wiring connection structure may be formed on the inner sidewall of the wiring opening S_CNT. However, if the common electrode CME can be electrically connected to the first power supply wiring VL1, the wiring connection structure does not necessarily have to be formed through the wiring opening S_CNT. For example, the wiring connection structure may be formed on the side surface of the first power supply wiring VL1 extending in one direction, or one first power supply wiring VL1 may be branched into two sub-wirings and the wiring connection structure may be formed on the side surface of the sub-wiring.

[0171] 28 is a plan view showing a part of the power supply wiring of a display device according to another embodiment, and FIG 29 is a cross-sectional view taken along line N1-N1' in FIG 28.

[0172] 28 and 29, a display device 1_3 according to an embodiment includes a first power wiring VL1_3 and a second power wiring VL2 spaced apart therefrom, and a wiring connection structure may be disposed on one of both sides of the first power wiring VL1_3 that faces the second power wiring VL2. The first opening P_CNT of the passivation layer 164 may overlap one side of the first power wiring VL1_3 but not overlap the second power wiring VL2. The second opening V_CNT of the via layer 166 may also overlap one side of the first power wiring VL1_3 but not overlap the second power wiring VL2. The wiring connection structure may be formed in portions of the first power wiring VL1_3 that overlap the openings P_CNT and V_CNT. For example, the portions of the first power supply wiring VL1_3 that overlap with the openings P_CNT and V_CNT may be the first wiring portion VL1a, and the other portions may be the second wiring portion. On one side of the first power supply wiring VL1_3, the data main metal layer 141a may be partially recessed, and a tip of the data capping layer 142 may be formed.

[0173] The passivation layer 164 and the via layer 166 may be disposed to cover the second power wiring VL2. The second power wiring VL2 is not exposed by the openings P_CNT and V_CNT, and no wiring connection structure is formed thereon, so the side surface is smooth. The second power wiring VL2 is a wiring covered by the passivation layer 164, and even if a common electrode CME is disposed thereon, it may not be electrically connected to it. The common electrode CME may be electrically connected to the first power wiring VL1_3 via a wiring connection structure formed on one side of the first power wiring VL1_3, so that a low potential voltage may be applied thereto.

[0174] In the display device 1_3 of this embodiment, the first power wiring VL1_3 does not include the wiring opening S_CNT, and may have a wiring connection structure on a side facing another adjacent wiring. Although the drawings illustrate the second power wiring VL2 as an example of another wiring disposed on the data conductive layer 140, the other wiring adjacent to the first power wiring VL1_3 is not necessarily limited to the second power wiring VL2. The second power wiring VL2 is illustrated as another member disposed on the same data conductive layer 140, and may be replaced with a conductive pattern, an electrode, or the like other than a power wiring.

[0175] Fig. 30 is a plan view showing a part of the power supply wiring of a display device according to a further embodiment, and Fig. 31 is a cross-sectional view taken along line N2-N2' in Fig. 30.

[0176] Referring to Figures 30 and 31, in one embodiment of a display device 1_4, a first power wiring VL1_4 includes a plurality of sub-wirings SVL1, SVL2 that are separated from each other in a portion thereof, and a wiring connection structure is formed on the side of one of the sub-wirings SVL1, SVL2.

[0177] The first power wiring VL1_4 may include a first sub-wiring SVL1 and a second sub-wiring SVL2. The first sub-wiring SVL1 and the second sub-wiring SVL2 may be wirings to which a low potential voltage is applied. The first power wiring VL1_4 may include a plurality of sub-wirings SVL1 and SVL2 extending from the non-display area NDA. However, this is not limited thereto, and the first power wiring VL1_4 may extend and then branch into a plurality of sub-wirings SVL1 and SVL2. In this case, the sub-wirings SVL1 and SVL2 may be separated from each other in the area where the wiring connection structure is formed, but may be integrated with each other in other areas to form the first power wiring VL1_4.

[0178] The wiring connection structure is disposed on one of both sides of the first sub-wiring SVL1 that faces the second sub-wiring SVL2. The first opening P_CNT of the passivation layer 164 may overlap one side of the first sub-wiring SVL1 but not overlap the second sub-wiring SVL2. The second opening V_CNT of the via layer 166 may also overlap one side of the first sub-wiring SVL1 but not overlap the second sub-wiring SVL2. The wiring connection structure may be formed in portions of the first sub-wiring SVL1 that overlap the openings P_CNT and V_CNT. For example, the portions of the first sub-wiring SVL1 that overlap the openings P_CNT and V_CNT may be the first wiring portion VL1a, and the other portions may be the second wiring portion. The data main metal layer 141a may be partially recessed on one side of the first sub-wiring SVL1, forming a tip of the data capping layer 142.

[0179] The passivation layer 164 and the via layer 166 may be disposed to cover the second sub-wiring SVL2. The second sub-wiring SVL2 is not exposed by the openings P_CNT and V_CNT, and no wiring connection structure is formed thereon, so its side surface is smooth. The second sub-wiring SVL2 is a wiring covered by the passivation layer 164, and may not be electrically connected to the common electrode CME even if it is disposed thereon. The common electrode CME may be electrically connected to the first sub-wiring SVL1 and the first power supply wiring VL1_4 via a wiring connection structure formed on one side of the first sub-wiring SVL1, and a low potential voltage may be applied to the common electrode CME.

[0180] 32 is a cross-sectional view showing a wiring connection structure of a display device according to another embodiment of the present invention, and is an enlarged view of a portion of the display device 1_5 corresponding to FIG.

[0181] Referring to FIG. 32 , in a display device 1_5 according to an embodiment, the connection electrode PBR may be disposed to completely cover the side surface of the data main metal layer 141a of the data conductive layer 140. As described above, the area of ​​the connection electrode PBR disposed on the exposed side surface of the data main metal layer 141a may vary depending on the formation process of the connection electrode PBR or process variations. In the display device 1_5 according to this embodiment, the exposed side surface of the data main metal layer 141a may be completely covered and protected by the connection electrode PBR. The common electrode CME may be disposed on the connection electrode PBR on the side surface of the data main metal layer 141a together with the light-emitting layer EML. The common electrode CME may be electrically connected to the data main metal layer 141a and the first power line VL1 via the connection electrode PBR.

[0182] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting.

Claims

1. a data conductive layer including a first power wiring disposed on the substrate; a passivation layer disposed on the data conductive layer, the passivation layer including a first opening exposing at least a portion of the first power wiring; a protective layer disposed on the passivation layer; a via layer disposed on the protective layer and including a second opening partially overlapping the first opening; a pixel electrode disposed on the via layer, and a connection electrode spaced apart from the pixel electrode and at least a portion of which is disposed within the first opening and the second opening; a pixel defining film disposed on the pixel electrode and the connection electrode, the pixel defining film including an opening that overlaps the second opening; a light-emitting layer disposed on the pixel-defining film and at least a portion of which is disposed over the pixel electrode and the connecting electrode; and a common electrode disposed on the light emitting layer and electrically connected to the first power wiring; the data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer; a common electrode electrically connected to the data main metal layer by the wiring connection structure;

2. The display device according to claim 1 , wherein a portion of the protection layer below the via layer is recessed from the sidewall of the second opening.

3. The display device of claim 2 , wherein the protective layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

4. The display device according to claim 1 , wherein at least a portion of the connection electrode is disposed on a side surface of the first power supply wiring in the data main metal layer.

5. the first power wiring overlaps the first opening and the second opening, respectively, and a first sidewall on which the wiring connection structure is disposed; a second sidewall overlapping the first opening, not overlapping the second opening, and covered by the passivation layer; and The display device according to claim 1 , further comprising a third sidewall that does not overlap the first opening and the second opening and is covered by the via layer.

6. The display device of claim 5 , wherein the second sidewall and the third sidewall of the first power supply wiring extend parallel to each other on the side surfaces of the data main metal layer and the data capping layer.

7. The display device according to claim 1 , wherein the connection electrode is disposed so as to cover a side surface of the data main metal layer of the first power supply wiring.

8. a wiring opening that penetrates the first power supply wiring; The display device according to claim 1 , wherein the first opening and the second opening are arranged so as to overlap a portion of the wiring opening.

9. The display device according to claim 8 , wherein the wiring connection structure is disposed on a first sidewall of the wiring opening that overlaps with the first opening and the second opening.

10. a sidewall of the wiring opening that does not overlap with at least one of the first opening and the second opening is covered with the passivation layer or the via layer; The display device of claim 9 , wherein the sidewalls are formed by side surfaces of the data main metal layer and the data capping layer extending parallel to each other.

11. further including a second power supply wiring spaced apart from the first power supply wiring, The display device according to claim 1 , wherein the first opening and the second opening are arranged so as to overlap one side of the first power supply wiring and not to overlap the second power supply wiring.

12. The display device according to claim 11 , wherein the wiring connection structure is formed in the first power supply wiring at a portion overlapping the first opening and the second opening.

13. the first power supply wiring includes a first sub-wiring and a second sub-wiring, at least a portion of which is separated from each other; The display device according to claim 1 , wherein the first opening and the second opening are arranged so as to overlap one side of the first sub-wiring and not to overlap the second sub-wiring.

14. The display device according to claim 13 , wherein the wiring connection structure is disposed in a portion of the first sub-wiring that overlaps with the first opening and the second opening.

15. a data conductive layer including a first power wiring disposed on the substrate; a passivation layer disposed on the data conductive layer, the passivation layer including a first opening exposing at least a portion of the first power wiring; a protective layer disposed on the passivation layer; a via layer disposed on the protective layer and including a second opening partially overlapping the first opening; a pixel electrode disposed on the via layer; and a pixel defining film disposed on the via layer, the pixel defining film including an opening hole at least a portion of which is disposed directly on the protective layer within the second opening and overlapping the second opening; a light-emitting layer disposed on the pixel-defining film and at least a portion of which is disposed over the pixel electrode and the connecting electrode; and a common electrode disposed on the light emitting layer and electrically connected to the first power wiring; the data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer; the protective layer is recessed inwardly beneath the pixel-defining membrane; the first power wiring includes a wiring connection structure formed such that the data main metal layer is recessed relative to a side surface of the data capping layer, and the common electrode is electrically connected to the data main metal layer by the wiring connection structure.

16. forming a first power wiring including a data base layer on a substrate, a data main metal layer disposed on the data base layer, and a data capping layer disposed on the data main metal layer; forming a passivation layer disposed on the first power wiring and including a first opening that partially exposes the first power wiring; and forming a protection layer disposed on the passivation layer and covering the first power wiring exposed by the first opening; forming a via layer disposed on the protective layer, the via layer including a second opening partially overlapping the first opening and exposing the protective layer; etching the protection layer exposed through the second opening and etching the exposed portion of the first power wiring to form a wiring connection structure in which the data main metal layer is recessed from the data capping layer; and A method for manufacturing a display device, comprising: forming a common electrode disposed on the via layer, at least a portion of which is disposed within the second opening, and electrically connected to the data main metal layer of the wiring connection structure.

17. The method of manufacturing a display device according to claim 16 , wherein the protective layer includes silicon oxide, silicon nitride, or silicon oxynitride.

18. the etching of the protection layer is performed by an isotropic etching process using the via layer as a mask; The method for manufacturing a display device according to claim 16 , wherein the protective layer is formed so that a portion thereof is recessed below the via layer.

19. Before forming the common electrode, forming a connection electrode disposed on the via layer and at least a portion of which is disposed within the second opening, and a light-emitting layer disposed on the connection electrode; At least a portion of the connection electrode is disposed on a side surface of the data main metal layer, The method for manufacturing a display device according to claim 16 , wherein the common electrode is disposed on the connection electrode.

20. before etching the protective layer, forming a pixel-defining film disposed on the via layer and at least a portion of the pixel-defining film disposed within the second opening; 18. The method of claim 17, wherein the etching of the protective layer is performed by an isotropic etching process using the pixel defining layer as a mask.

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