Silicon carbide epitaxial wafer manufacturing

Abstract

A method for producing silicon carbide (SiC) epitaxial wafers in a wafer growth system (1), the wafer growth system including an outer container, an insulating container disposed inside the outer container, a growth container (2) disposed inside the insulating container, and a heating device disposed outside the outer container for heating the inside of the growth container (2). The method includes providing a polycrystalline SiC source material (3) into the growth container (2) and providing a single-crystal SiC substrate (4) into the growth container (2) substantially parallel to the source material (3), the substrate (4) having a thickness of ≦5·10 16 cm -3 and increasing the temperature in the growth container (2) to the sublimation temperature of the source material (3). 18 cm -3 and maintaining the temperature within the growth container (2) until a conductive layer (6) of single crystal SiC is grown on the substrate (4). The substrate (4) and the grown conductive layer (6) together define an epitaxial boule. The method further includes cooling the epitaxial boule to room temperature and slicing the epitaxial boule through the substrate (4) in a plane substantially parallel to the grown conductive layer (6) into excess substrate (8) and epitaxial wafers including a substrate layer (7) having the conductive layer (6) grown thereon.

Description

[Technical Field]

[0001] The present invention relates generally to the manufacture of silicon carbide epitaxial wafers. [Background technology]

[0002] Semiconductor materials and devices are found in all kinds of electronic devices. One application is power semiconductor devices, or power devices. Power devices function to convert and / or control electrical energy between an energy source and an energy consumer. Power devices are found in power grids, computer power supplies, smartphone power management, and automotive electronics, to name a few.

[0003] Silicon carbide (SiC) is a next-generation semiconductor material that has attracted attention in the power device industry. The use of SiC enables more energy-efficient power devices with reduced cooling requirements and higher system integration density. However, technological solutions for the production of SiC semiconductor materials are still needed.

[0004] SiC epitaxial wafers are generally thin semiconductor disks formed by two main layers: a highly doped layer and a lightly doped layer. The highly doped layer is commonly known as the conduction layer. The lightly doped layer is commonly known as the drift layer.

[0005] The quality of the drift layer is crucial to the quality of the final product. The quality of the drift layer is defined by the defect density. Typical defects in the drift layer are downfalls (carbon particles), carrot defects, triangular stacking faults, basal plane dislocations (BPDs), bar stacking faults, threading screw dislocations, and threading edge dislocations.

[0006] Conventionally, SiC epitaxial wafers are fabricated by depositing a drift layer on a conductive layer: a highly doped conductive substrate (conductive layer) is fabricated in a physical vapor transport (PVT) furnace, followed by crystal slicing, grinding, and polishing, and then a lightly doped layer (drift layer) is deposited on the substrate by chemical vapor deposition (CVD).

[0007] The quality of a drift layer deposited on a conductive substrate is determined not only by the level of process control, but also by the crystalline quality of the conductive substrate. This is because defects in the conductive substrate propagate to the drift layer during growth. Therefore, the quality of the conductive substrate is a limiting factor in producing high-quality epitaxial wafers. Currently, it is believed that it is impossible to achieve a completely defect-free drift layer using existing technology.

[0008] Another problem in prior art processes relates to stress in the drift layer. When the drift layer is grown on the conduction layer, stress accumulates in the drift layer. This is due, for example, to the smaller volume of the drift layer compared to the conduction layer. The volume difference is due to doping, which causes the crystal lattice to expand or contract depending on the type of dopant atoms (and their respective radii) and the doping concentration. Stress in the drift layer can occur during growth or during post-growth cooling, causing slippage of crystal planes and, for example, the formation of stacking faults.

[0009] Another parameter affecting the quality of current epitaxial wafers is doping uniformity, a problem that affects not only the conduction layer but also the drift layer. Currently, the doping uniformity of the conduction layer is generally around 20%, meaning the difference in doping concentration between the most and least doped regions of the material is 20%. For example, doping uniformity at this level can lead to variations in the resistivity of the material, which in turn negatively impacts yield (usable wafer area). This, in turn, negatively impacts the temperature distribution within the material. Furthermore, during growth (doping), non-uniform doping can affect growth characteristics and impair the uniformity of the growth surface, which, of course, also impacts yield.

[0010] Therefore, there is a need for a technical solution for the manufacture of SiC epitaxial wafers to further reduce the defect density of the SiC epitaxial wafers. definition

[0011] Doping: Doping is the process of increasing the number of charge carriers in a crystal structure. The net doping concentration is determined by the number of electron donors (N d ) and the number of electron acceptors (N a ) Nitrogen atoms are common electron donors. Boron and aluminum atoms are common electron acceptors. The net doping concentration can be measured in a variety of ways. For example, the concentration of doping atoms can be measured through secondary ion mass spectrometry (SIMS), the concentration of ionized doping atoms can be measured through capacitance voltage (CV) measurements, and the concentration of charge carriers can be measured through Hall measurements.

[0012] n-type doping: Doping with atoms that can supply electrons, which are negative charge carriers, to a crystal structure. A common n-type dopant is nitrogen. Doping is typically achieved by introducing a dopant gas, such as nitrogen gas, during material growth. The final doping type (n-type or p-type) of a material is determined by the most abundant p-type or n-type electrically active atoms.

[0013] p-type doping: Doping with atoms that can provide positive charge carriers, called holes. Aluminum is a common p-type dopant, and doping is usually carried out by introducing a dopant gas such as trimethylaluminum (TMA) gas, or by using a source material containing aluminum, or alternatively, by introducing a powder such as aluminum carbide powder (Al4C3). Boron is another common p-type dopant. The final doping type of a material (n-type or p-type) is determined by the most abundant p-type or n-type electrically active atoms.

[0014] Epitaxial wafer: A single crystal SiC wafer comprising a highly doped SiC conduction layer and a lightly doped SiC drift layer. As used herein, a highly doped SiC layer is defined as a SiC layer having a doping concentration of ≥ 1·10 18 cm -3 In this specification, a low doping concentration is understood to be ≦5·10 16 cm -3 , preferably ≦1·10 16 cm -3 It is understood that Summary of the Invention [Problem to be solved by the invention]

[0015] The object of the present invention is to overcome at least some of the problems outlined above. [Means for solving the problem]

[0016] In a first aspect of the present disclosure, this is achieved by providing a method for producing silicon carbide (SiC) epitaxial wafers in a wafer growth system including an outer container, an insulating container disposed inside the outer container, a growth container disposed inside the insulating container, and a heating device disposed outside the outer container for heating the inside of the growth container. The method includes providing a polycrystalline SiC source material into the growth container and providing a single-crystal SiC substrate into the growth container substantially parallel to the source material, the substrate having a thickness of ≦5·10 16 cm -3 and increasing the temperature in the growth container to the sublimation temperature of the source material; and 18 cm -3 maintaining the temperature within the growth container until a conductive layer of single crystal SiC is grown on the substrate, the substrate and the grown conductive layer together defining an epitaxial boule; cooling the epitaxial boule to room temperature; and slicing the epitaxial boule through the substrate in a plane substantially parallel to the grown conductive layer into epitaxial wafers including excess substrate and a substrate layer having the conductive layer grown thereon.

[0017] This novel method allows the production of high-quality epitaxial wafers, which can improve device performance, such as reducing electrical losses due to lower resistivity, as well as reliability, such as reducing the risk of bipolar degradation. By providing a high-quality, low-doped substrate, it is possible to completely avoid growing low-doped material on high-doped material during epitaxial wafer production. One advantage of this is that the quality of the low-doped material (drift layer) is no longer limited by the quality of the conduction layer; that is, defects present in the conduction layer cannot propagate to the drift layer.

[0018] Another advantage is that prior art techniques do not introduce translational stress from the highly doped material to the lightly doped material, whereas with the claimed method, such translational stress is no longer a limiting factor in the quality of the lightly doped material (drift layer).

[0019] Another advantage is improved device yield, which is related to the percentage of working components on a wafer. The improved quality achieved by the claimed method and the reduction in defects formed during epitaxial growth results in improved device yield.

[0020] Another advantage of growing a conductive layer on a lightly doped substrate is that the doping uniformity of the conductive layer is improved, which leads to more uniform temperature distribution, more uniform growth characteristics, more uniform resistivity, and improved yield.

[0021] Another advantage of growing the conductive layer on a lightly doped substrate is that the defect density requirements for the conductive layer are less stringent than those for the drift layer, which means that the requirements for the surface preparation of the substrate are less stringent compared to the prior art. Defects due to imperfect surface preparation, such as scratches or etch pits, can be tolerated in the conductive layer, but the same defects in the drift layer would render it unusable.

[0022] This novel method is made possible at least by applying a sublimation growth process, which offers a high level of process control and control over crystal growth and, therefore, crystal quality. Prior art processes for growing a drift layer on a conduction layer cannot be applied to sublimation growth because, at the sublimation temperature of SiC, dopants in the conduction layer are released into the gas phase and, through diffusion, contaminate the drift layer grown on top of it.

[0023] In some embodiments, the doping concentration of the substrate is ≦1·10 16 cm -3 is.

[0024] In some embodiments, the substrate, and thus the substrate layer of the epitaxial wafer, is n-type doped.

[0025] In some embodiments, the substrate, and thus the substrate layer of the epitaxial wafer, is p-type doped.

[0026] In some embodiments, the thickness of the substrate is ≧100 μm.

[0027] In some embodiments, the substrate is substantially free of basal plane dislocations.

[0028] In some embodiments, the substrate is substantially free of stacking faults.

[0029] In some embodiments, the conductive layer is grown on the carbon face of the substrate.

[0030] Generally, crystals grown on the carbon face have better crystalline quality than comparable crystals grown on the silicon face. Additionally, surface preparation of the carbon face is easier, less time-consuming, and more cost-effective than surface preparation of the silicon face. In prior art processes, a conductive layer / highly doped substrate is typically grown on the carbon face of a seed crystal. Subsequently, a drift layer is grown on the silicon face of the highly doped substrate, e.g., during CVD. Thus, the claimed method provides a manufacturing process that further utilizes the better crystalline quality afforded by growth on the carbon face in the production of epitaxial wafers. Specifically, a manufacturing process in which silicon face growth can be completely avoided.

[0031] In some embodiments, the method includes repeating the method at least once, and the method further includes reusing the excess substrate as a substrate for the growth container.

[0032] Reusing the substrate for subsequent growth runs / cycles makes the process more time- and cost-effective.

[0033] In a second aspect of the present disclosure, ≦5·10 16 cm -3 and a substrate layer of single-crystal SiC with a doping concentration of ≥ 1·10 18 cm -3 and a conductive layer of single-crystal SiC having a doping concentration of ≦5·10. The epitaxial wafer is formed by providing a polycrystalline SiC source material in a growth container and providing a single-crystal SiC substrate in the growth container substantially parallel to the source material, the substrate having a doping concentration of ≦5·10. 16 cm -3 and increasing the temperature in the growth container to the sublimation temperature of the source material; and 18 cm -3 maintaining a temperature within the growth container until a grown conductive layer of monocrystalline SiC having a doping concentration of 0.15 to 1.05 is grown on the substrate, wherein the substrate and grown conductive layer together define an epitaxial boule; cooling the epitaxial boule to room temperature; and slicing the epitaxial boule through the substrate in a plane substantially parallel to the grown conductive layer into excess substrate and epitaxial wafers including a substrate layer with the grown conductive layer thereon.

[0034] In some embodiments, the doping concentration of the substrate layer of the epitaxial wafer is ≦1·10 16 cm -3 is.

[0035] In some embodiments, the substrate layer of the epitaxial wafer is n-type doped.

[0036] In some embodiments, the substrate layer of the epitaxial wafer is p-type doped.

[0037] In some embodiments, the substrate layer of the epitaxial wafer is substantially free of basal plane dislocations.

[0038] The presence of BPDs is detrimental to devices fabricated on epitaxial wafers because they can lead to degradation of the bipolar devices.

[0039] In some embodiments, the substrate layer of the epitaxial wafer is substantially free of stacking faults.

[0040] In some embodiments, the conductive layer is grown on the carbon face of the substrate. [Brief explanation of the drawings]

[0041] The invention will now be described, by way of example only, with reference to the accompanying drawings in which: [Figure 1] FIG. 1 illustrates a system according to the present disclosure for growing epitaxial wafers. [Figure 2] FIG. 1 illustrates a method according to the present disclosure. [Figure 3a] 1A-1D illustrate various stages in the fabrication of an epitaxial wafer according to the present disclosure. [Figure 3b] 1A-1D illustrate various stages in the fabrication of an epitaxial wafer according to the present disclosure. [Figure 3c] 1A-1D illustrate various stages in the fabrication of an epitaxial wafer according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0042] Exemplary embodiments are described below for a method of producing silicon carbide (SiC) single crystal epitaxial wafers. These embodiments are merely exemplary, and those skilled in the art will recognize that there are many other embodiments that may be implemented within the scope of the present invention using the teachings of the present disclosure. In the drawing figures, like reference numerals designate the same or corresponding elements throughout the several views. It will be understood that these figures are for illustrative purposes only and are not intended to limit the scope of the present disclosure in any way. References to directions such as up or down, upward or downward, etc., should be understood as being within the normal operation of the system disclosed herein.

[0043] One objective of the present disclosure is to provide a novel method for producing high-quality epitaxial wafers by growing a highly doped single crystal material on a lightly doped single crystal material. This method is in direct opposition to current common practice. The following disclosure is based on the discovery that by providing a lightly doped substrate that is essentially free of basal plane dislocations and essentially free of stacking faults, high-quality epitaxial wafers can be produced according to the disclosed method.

[0044] First, a system 1 for growing epitaxial wafers will be described with reference to Figures 1a and 1b.

[0045] 1a and 1b illustrate a growth system 1 for growing epitaxial wafers. Specifically, an epitaxial boule is grown in the system 1 shown in FIGS. 1a and 1b. According to the present disclosure, an epitaxial boule is a precursor to an epitaxial wafer. An epitaxial boule is defined herein as a disk of single-crystal SiC that includes two essentially parallel layers. The first layer is a substrate 4, which may also be referred to as a drift layer precursor, and is thicker than the final drift layer. The second layer is a conductive layer 6.

[0046] Unlike what is disclosed in the prior art, the present disclosure involves growing heavily doped single crystal SiC on a lightly doped single crystal SiC substrate 4. The heavily doped SiC is ≧1·10 18 cm -3 A low doping concentration is understood to be ≦5 10 16 cm -3 , preferably ≦ 1 10 16 cm -3 It is understood that the doping concentration can be measured, for example, through secondary ion mass spectrometry.

[0047] The growth system 1 is a physical vapor transport system. The growth system 1 is configured for sublimation epitaxy, which refers to the growth of epitaxial wafers or boules through sublimation. The growth system 1 may be configured, for example, for a rapid sublimation growth process (FSGP). The growth system 1 generally includes an inner container 2, an insulating container, and an outer container. The inner container 2 is disposed within the insulating container during operation. The insulating container is disposed within the outer container during operation. The growth system 1 further includes heating means. The heating means is disposed outside the outer container and is configured to heat the cavity of the inner container 2. The heating means may be configured for inductive heating, for example in the form of an induction coil. The heating means may be configured for resistive heating.

[0048] The heating means may be movable relative to the outer container. To this end, the growth system 1 may comprise a transport system arranged to move the heating means. The heating means may be movable in the vertical direction. The heating means may be movable along the height of the outer container. This allows for precise control of the temperature within the cavity of the inner container 2. This further allows for control of the rate of temperature increase and decrease. This further allows for control of the temperature drop within the cavity of the inner container 2. This temperature drop is the temperature difference between two positions within the cavity of the inner container 2, one of which is located vertically above the other during normal operation.

[0049] The temperature within the cavity of the inner container 2 can be further controlled by varying the design of the inner container 2, the insulating container, and the outer container. This design can relate to the wall thickness of each container. This design can relate to the relative sizes between the containers.

[0050] The inner container 2 may include an upper portion 2a and a bottom portion 2b. The upper portion 2a may be placed on top of the bottom portion 2b. The upper portion 2a may be sealingly engaged with the bottom portion 2b, for example, by having a fit between the top and bottom portions 2b or by providing threads on these portions. The interiors of the upper and bottom portions 2a and 2b together may define the cavity of the inner container 2. The inner container 2 may be cylindrical. The inner container 2 may be made of high-density graphite. The inner container 2 may be made of a material suitable for withstanding high temperatures, such as above 1500°C. The inner container 2 may be made of a material suitable for the type of heating means, in each case. For example, if the growth system 1 includes induction heating means, the material of the inner container 2 shall be suitable for heating by induction, and may be high-density graphite.

[0051] The insulating container may be cylindrical and may be made of insulating graphite foam. The outer container may be cylindrical and may be made of quartz. The insulating container is preferably provided to thermally insulate the inner container 2.

[0052] The growth system 1 may include a pump for evacuating the cavity of the inner container 2. The pump may include an inlet located in the cavity of the inner container 2 for pumping a gas into the cavity. The gas may be argon. The pump may include an outlet located in the cavity of the inner container 2 for pumping the gas out of the cavity.

[0053] A pump and associated inlets and outlets may further be arranged to pump a dopant gas into the cavity. The dopant gas may be nitrogen gas. The dopant gas may be for increasing the doping concentration during growth of the grown epitaxial layer. The system according to the present disclosure provides a uniform distribution of the dopant gas within the inner container 2, which may improve properties such as, for example, doping uniformity.

[0054] The growth system 1 may include a carbon getter arranged to maintain a stable and proper Si / C stoichiometry during growth. The carbon getter may be arranged within the cavity of the inner container 2. The growth system 1 may include multiple carbon getters.

[0055] In the cavity of the inner container 2, a source material 3 and a substrate 4 are provided in the process of growing a conductive layer 6. The substrate 4 may be disposed above the source material 3 in the cavity of the inner container 2. The substrate 4 may be disposed below the source material 3 in the cavity of the inner container 2.

[0056] The source material 3 is a monolithic polycrystalline SiC source material 3. The source material 3 may have a columnar fine grain structure. The grain size of the source material 3 may be 1 to 250 μm. The grain size of the source material 3 may be 1 to 100 μm. The microstructure may be a cubic microstructure. The source material 3 may be n-type doped. The source material 3 may be p-type doped.

[0057] The substrate 4 is a monolithic single crystal SiC substrate. The crystal structure of the substrate 4 can be 4H polytype, 6H polytype, 15R polytype, 3C polytype, or other suitable polytype. The substrate 4 has a crystal structure of ≦5·10 16 cm -3 , preferably ≦1·10 16 cm -3 This means that the difference in the concentration of electron donors and electron acceptors is ≦5·10 16 cm -3, preferably ≦1·10 16 cm -3 It means that the substrate 4 is less than 0.5 μm. The substrate 4 may be n-type doped. The substrate 4 may be fabricated by sublimation growth. The substrate 4 may be fabricated by a separate process carried out in the growth system 1 according to the present disclosure.

[0058] The substrate 4 is essentially free of stacking faults. Preferably, the substrate 4 is completely free of stacking faults. Stacking faults are planar defects in the microstructure caused by lattice stresses, referred to as high stacking fault energy.

[0059] The substrate 4 is essentially free of basal plane dislocations. Preferably, the substrate 4 is completely free of basal plane dislocations (BPDs). BPDs are microstructural defects in materials that can arise during growth of the substrate 4 or during cooling of the substrate 4 after growth. The presence of BPDs is detrimental to epitaxial wafers because defects can propagate from the substrate 4 to the grown layers during growth. The BPD concentration can be measured by counting the BPDs. This counting can be manual or computer-assisted. The counting is preferably performed after appropriate surface preparation, such as etching, and after appropriate magnification, for example, by optical microscopy or scanning electron microscopy.

[0060] The SiC substrate 4 has a crystalline structure comprising alternating layers of carbon and silicon, and the substrate 4 includes a carbon side known as the carbon-face or C-face, and a silicon side known as the silicon-face or Si-face. The substrate 4 is preferably positioned within the cavity of the inner container 2 with the C-face facing the source material 3. Thus, when the conductive layer 6 is grown thereon, it will be grown on the C-face.

[0061] The substrate 4 can be disposed on at least one support 5, and preferably, at least two supports 5 are used. The support 5 preferably positions the source material 3 and the substrate 4 such that the distance between them is shorter than the average mean free path of vapor species sublimating from the source material 3. In one embodiment, the at least one support 5 has an upper portion 2a and a bottom portion 2b, and the upper portion 2a of the support 5 contacts the outer edge of the substrate 4. In one embodiment, the bottom portion 2b of the support 5 rests on the source material 3. In one embodiment, the bottom portion 2b rests on the bottom of the inner container 2. In an alternative embodiment, the at least one support has a distal portion and a proximal portion, the proximal portion is fixedly disposed on the inner surface of the inner container 2, the distal portion extends horizontally toward the center of the inner container 2, and the substrate 4 rests on the distal portion. The support 5 shown in FIGS. 1a and 1b is a pyramidal support 5 that minimizes the contact area between the support 5 and the substrate 4.

[0062] This method will now be described with reference to FIG.

[0063] Step S1 of the method comprises providing a monolithic polycrystalline source material 3 in an inner container 2 of a growth system 1, and providing a monolithic single crystal substrate 4 above the source material 3 in the inner container 2. The substrate 4 is positioned at a distance of 0.5-2 mm above the source material 3, preferably at a distance of 0.7-1.3 mm above the source material 3, and more preferably at a distance of 1 mm above the source material 3. This arrangement is shown in Figure 1a.

[0064] Step S2 of the method comprises evacuating the inner container 2 to provide a clean environment for growth. The inner container 2 can be evacuated to a pressure of 1 mbar, preferably ≦1 mbar, more preferably ≦0.1 mbar.

[0065] Step S3 of the method includes purging the inner container 2 with an inert gas, such as argon gas. The purpose of purging the inner container 2 with the inert gas is to ensure a clean environment for growth, and the inert gas may scrub any air residue. The inert gas also serves the purpose of suppressing sublimation of unwanted gas species, as will be described in more detail below with reference to step S4. In one exemplary embodiment, the inert gas is introduced into the chamber until a pressure in the range of 1 mbar to 10 mbar is reached. In another exemplary embodiment, the inert gas is introduced until a pressure in the range of 150 mbar to 950 mbar, preferably 700 mbar, is reached.

[0066] In step S4, the temperature inside the inner container 2 is increased by a heating means to the sublimation temperature of the source material 3. The theoretical temperature at which sublimation of the substrate 4 begins may be ≧1500°C. During the increasing step S4, the temperature inside the inner container 2 may be increased to a sublimation temperature of 1650-2050°C. The temperature may be increased to, for example, 1800°C, 1950°C, 1975°C, 2050°C, or any other suitable sublimation temperature.

[0067] The inert gas introduced into the inner container 2 during step S3 has the effect of suppressing the sublimation of gas species that sublimate at low temperatures (below the sublimation temperature), thereby preventing the growth of such gas species on the substrate 4 during step S4, in which the temperature is increased. Therefore, by controlling the pressure within the inner container 2, it is possible to control the sublimation from the substrate 4. In one embodiment, the pressure during the increasing step S4 can be kept constant in the range of 1 mbar to 10 mbar. In one embodiment, the pressure during the increasing step S4 can be reduced, for example, at a pumping rate of 1 mbar / min to 10 mbar / min, preferably 5 mbar / min, until a pressure in the range of 0.01 mbar to 10 mbar, preferably 0.1 mbar to 10 mbar, more preferably 0.1 mbar to 5 mbar, is reached.

[0068] In step S5, the temperature inside the inner container 2 is maintained. During step S5, the conductive layer 6 begins to grow on the substrate 4. The desired growth rate can be in the interval of 1 μm / h to 1 mm / h. Preferably, the growth rate is maintained between 10 μm / h and 500 μm / h. The desired growth rate depends on the balance between productivity and quality. In one embodiment, the sublimation temperature is maintained at 1950°C, and with the above settings, a growth rate of approximately 90 μm / h is obtained. Those skilled in the art will know at what temperature the desired growth rate is obtained. The temperature is maintained until a conductive layer 6 of the desired thickness is grown on the substrate 4. The desired thickness of the conductive layer 6 can be ≧5 μm. The desired thickness of the conductive layer 6 can be ≧10 μm. The desired thickness of the conductive layer 6 can depend on the intended use of the epitaxial wafer.

[0069] In step S6, the heating element is turned off and the substrate 4 is allowed to cool to room temperature. The substrate 4 is preferably cooled within the inner container 2. During step S6, the inner container 2 may be backfilled with an inert gas to reach atmospheric pressure. The inert gas may be argon.

[0070] During steps S1 to S6, an epitaxial boule is produced, which comprises a substrate 4 and a conductive layer 6 grown thereon, which is shown in Figure 1b.

[0071] The conductive layer 6 grown during steps S1-S6 has a doping uniformity of ≦15%, preferably ≦10%, more preferably ≦5%, and most preferably ≦2%. The doping uniformity is determined by comparing the measured doping concentrations in various regions of the conductive layer, preferably the most and least doped regions.

[0072] In step S7, the epitaxial boule is sliced ​​through the substrate 4. The epitaxial boule is preferably sliced ​​through the substrate 4 in a plane AA substantially parallel to the grown conductive layer 6. The plane AA can be seen in FIG. 3b. The slicing process divides the epitaxial boule into two parts. The first part is an epitaxial wafer including the conductive layer 6 and a substrate layer defining the drift layer 7. The second part takes the form of excess substrate 8. The thickness of the drift layer 7 depends on the intended use of the epitaxial wafer. For example, the thickness may depend on the voltage rating at which devices fabricated from the epitaxial layer will be used. The epitaxial boule can be sliced ​​to achieve a drift layer 7 having a thickness of approximately 10 μm per 1000 V.

[0073] In one embodiment, the drift layer 7 is 5 μm thick and suitable for use in a 600 V voltage class device. In another embodiment, the drift layer 7 is 10 μm thick and suitable for use in a 1000 V voltage class device. In another embodiment, the drift layer 7 is 10 μm thick and suitable for use in a 1200 V voltage class device. These exemplary epitaxial wafers may be used, for example, in Schottky barrier diodes.

[0074] In one embodiment, the drift layer 7 is 16 μm, suitable for use in a 1700 V voltage class device. In one embodiment, the drift layer 7 is 30 μm, suitable for use in a 3300 V voltage class device. In one embodiment, the drift layer 7 is 60 μm, suitable for use in a 6500 V voltage class device. These exemplary epitaxial wafers may be used, for example, in metal oxide semiconductor field effect transistors or junction barrier Schottky diodes.

[0075] The slicing process can be performed by a laser separation process or a laser lift-off process. A laser separation process can involve, for example, irradiating the epitaxial boule with a laser at a given depth corresponding to the desired thickness of the layer to be removed. This irradiation can affect the bonding between these layers, such as separating the carbon and silicon crystal layers from each other. Alternatively, the slicing process can be performed by a wire saw or other separation process. Furthermore, the slicing process can also be referred to as a splitting process.

[0076] The method may further include post-processing of the epitaxial wafer, such as step surface and edge grinding, chemical mechanical polishing, or wafer cleaning.

[0077] The method according to the present disclosure further includes repeating the method at least once, wherein when step S1 of the method is repeated, excess substrate 8 generated during slicing in a previous run is provided as substrate 4 in step S1.

[0078] In one example, the substrate 4 is initially 1400 μm thick. A conductive layer 6 is grown on the substrate 4 until the conductive layer 6 is 350 μm thick. Thus, the total thickness of the epitaxial boule is 1750 μm. During slicing, the epitaxial boule is divided into an epitaxial wafer, including the conductive layer 6 having a thickness of 350 μm and the drift layer 7 having a thickness of 10 μm, and a surplus substrate 8. Theoretically, the surplus substrate 8 has a thickness of 1390 μm; however, because additional material is removed during slicing, in this example, the surplus substrate 8 has a thickness of 1240 μm. The 1240 μm surplus substrate 8 can then be used as the substrate 4 in the next run while repeating the method. This can be repeated until the substrate 4 is completely consumed. The number of times the substrate 4 can be reused depends on the initial thickness of the substrate 4.

[0079] 3a-3c show schematic diagrams of a substrate 4 and a conductive layer 6 at various stages in the process of manufacturing a SiC epitaxial wafer. In FIG. 3a, only the substrate 4 is shown, prior to the growth of the conductive layer 6. FIG. 3a shows the substrate 4 as it is provided in the inner container 2 of the growth system 1 (S1). FIG. 3b shows the substrate as it is after the conductive layer 6 has been grown on it (S6). The substrate 4 and conductive layer 6 in FIG. 3b can thus be viewed as representing an epitaxial boule. Line AA, as described above, represents a plane essentially parallel to the grown conductive layer 6. Plane AA can be viewed as perpendicular to the growth direction of the grown conductive layer 6. FIG. 3c shows the epitaxial wafer, including the conductive layer 6, the drift layer 7, and the excess substrate 8, after a slicing step (S7) through the plane represented by line AA. The relative thicknesses between the substrate 4 and the conductive layer 6 in the figures should not be considered as limiting the scope of the present disclosure. The relative thickness between the excess substrate 8 and the epitaxial wafer in the figures shall not be considered as limiting the scope of the present disclosure.

[0080] Although preferred embodiments of the SiC epitaxial wafer and its manufacturing method and system have been disclosed above, those skilled in the art will recognize that modifications may be made thereto within the scope of the appended claims without departing from the spirit of the invention.

[0081] All of the above-mentioned alternative embodiments or parts of the embodiments can be freely combined with each other or employed separately, as long as the combination is not contradictory, without departing from the inventive idea.

Claims

1. A method for manufacturing a silicon carbide (SiC) epitaxial wafer in a wafer growth system (1), wherein the wafer growth system is Outer container and An insulating container positioned inside the outer container, A growth container (2) is placed inside the aforementioned insulating container, The growing container (2) includes a heating device located outside the outer container for heating the inside of the outer container, The aforementioned method, The polycrystalline SiC source material (3) is supplied into the growth container (2), The method involves supplying a single-crystal SiC substrate (4) into the growth container (2) so as to be substantially parallel to the source material (3), wherein the substrate (4) has a size of ≤ 5.10 １６ cm －３ Having a doping concentration of, Raising the temperature inside the growth container (2) to the sublimation temperature of the source material (3), Thickness ≥ 10 μm and doping concentration ≥ 1.10 １８ cm －３ Maintaining the temperature inside the growth container (2) until the single-crystal SiC conductive layer (6) grows on the substrate (4), thereby defining an epitaxial boule together with the substrate (4) and the grown conductive layer (6). The epitaxial boule is cooled to room temperature, A method comprising slicing the epitaxial boule through the substrate (4) in a plane substantially parallel to the grown conductive layer (6) into an epitaxial wafer comprising an excess substrate (8) and a substrate layer (7) having the grown conductive layer (6) thereon.

2. The doping concentration of the substrate (4) is ≤ 1.10 １６ cm －３ The method according to claim 1.

3. The method according to claim 1, wherein the thickness of the substrate (4) is ≥ 100 μm.

4. The method according to claim 1, wherein the substrate (4) is substantially free of basal plane dislocations.

5. The method according to claim 1, wherein the substrate (4) is substantially free of stacking faults.

6. The method according to claim 1, wherein the conductive layer (6) is grown on the carbon surface of the substrate (4).

7. The method according to claim 1, further comprising repeating the method at least once, wherein the method further comprises reusing the surplus substrate (8) as the substrate (4) of the growth container (2).

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