Switch-type matching circuit and radio transceiver circuit including the same

Abstract

To provide a switching type matching circuit suitable for a radio transmission / reception circuit.SOLUTION: In the bidirectional amplifier circuit 10, the switchable matching circuit 20 includes a first 1 / 4 wavelength transformer 21, a second 1 / 4 wavelength transformer 22 wider than the first 1 / 4 wavelength transformer 21, a third 1 / 4 wavelength transformer 23 wider than the second 1 / 4 wavelength transformer 22, and a fourth 1 / 4 wavelength transformer 24 wider than the third 1 / 4 wavelength transformer 23, which are connected in a ring shape, and a switch 25 connected between a connection point of the first 1 / 4 wavelength transformer and the second 1 / 4 wavelength transformer and a ground potential. And a switch 26 connected between a connection point of the third quarter-wave transformer and the fourth quarter-wave transformer and a ground potential, wherein a first input / output end P1 of the connection point of the second quarter-wave transformer and the third quarter-wave transformer is matched to Z0, and a second input / output end P2 of the connection point of the first quarter-wave transformer and the fourth quarter-wave transformer is configured to be switchable so as to be matched to ZH or ZL by complementary opening and closing of the switches 25 and 26.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a switching-type matching circuit, and more particularly to a matching circuit suitable for a wireless transceiver circuit. [Background technology]

[0002] The received power in wireless communications decreases in proportion to the square of the RF (radio frequency) signal wavelength. For this reason, when the RF frequency is in the millimeter wave band of 20 to 100 GHz, or even in the sub-terahertz or terahertz bands of 100 to 300 GHz, the received power becomes extremely low. While increasing the transmission power or antenna gain would improve this, there are limits to how far this can be achieved. Therefore, beamforming is used, which increases antenna gain by arranging multiple antennas in an array and adjusting the phase of the radio waves transmitted and received by each antenna to enhance directionality (see, for example, Non-Patent Documents 1 and 2).

[0003] In beamforming transceivers for the millimeter wave to terahertz bands, antennas are mounted on a chip at a pitch of about half a wavelength, and a transceiver circuit is placed directly below each chip antenna. When the RF frequency is in the sub-terahertz or terahertz band, the antenna pitch becomes about several hundred microns, so the transceiver circuit must be laid out in an extremely small area. Therefore, it is important to find a way to reduce the size of the transceiver circuit. A bidirectional transceiver circuit is known as an example of a technology for miniaturizing a transceiver circuit (see, for example, Non-Patent Document 3). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Ahmed, Amr et al. “140-GHz 2-D Scalable On-Grid 8x8-Element Transmit-Receive Phased Arrays With Up / Down Converters Demonstrating a 5.2-m Link at 16 Gbps.” IEEE Transactions on Microwave Theory and Techniques 72 (2024): 2852-2868. [Non-patent document 2] Yoshida, Takeshi et al. “A 2D Beam-Steerable 252-285-GHz 25.8-Gbit / s CMOS Receiver Module.” 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2023): 1-3. [Non-patent document 3] Pang, Jian et al. “A 28.16-Gb / s Area-Efficient 60-GHz CMOS Bidirectional Transceiver for IEEE 802.11ay.” IEEE Transactions on Microwave Theory and Techniques 68 (2020): 251-262. Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional bidirectional transmitter / receiver circuits incorporate a bidirectional amplifier circuit that amplifies both the transmit and receive IF (intermediate frequency) signals. In a bidirectional amplifier circuit, the impedance at the input / output terminals changes when the input / output direction changes, so it is necessary to switch the impedance matching with the characteristic impedance of the transmission line.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a switching matching circuit suitable for a radio transceiver circuit and a radio transceiver circuit including the same. [Means for solving the problem]

[0007] According to one aspect of the present invention, a frequency converter includes a first quarter-wave transformer, a second quarter-wave transformer wider than the first quarter-wave transformer, a third quarter-wave transformer wider than the first quarter-wave transformer, and a fourth quarter-wave transformer wider than the first quarter-wave transformer, connected in a circular configuration; a first switch connected between a junction of the first quarter-wave transformer and the second quarter-wave transformer and ground potential; and a second switch connected between a junction of the third quarter-wave transformer and the fourth quarter-wave transformer and ground potential. The present invention provides a switchable matching circuit configured such that a connection point between a four-wavelength transformer and the third quarter-wavelength transformer serves as a first input / output terminal, the impedance of the first input / output terminal matching a characteristic impedance, and a connection point between the first quarter-wavelength transformer and the fourth quarter-wavelength transformer serves as a second input / output terminal, and the first switch and the second switch complementarily open and close to switchably match the impedance of the second input / output terminal to a high impedance or a low impedance.

[0008] Furthermore, according to another aspect of the present invention, there is provided a radio transceiver circuit comprising: a bidirectional amplifier circuit configured to be reversible in input / output direction; the above-described first and second switchable matching circuits; and a mixer connected to a first input / output terminal of the bidirectional amplifier circuit, wherein the first input / output terminal of the first switchable matching circuit is connected to a first transmission line on an antenna side and the second input / output terminal is connected to the mixer, the first input / output terminal of the second switchable matching circuit is connected to a second transmission line and the second input / output terminal is connected to a second input / output terminal of the bidirectional amplifier circuit, and the impedances of the second input / output terminals of the two switchable matching circuits are switched to be opposite to each other in response to reversal of the input / output direction of the bidirectional amplifier circuit. [Effects of the Invention]

[0009] According to the present invention, while one input / output terminal is fixed to a characteristic impedance, the other input / output terminal can be switched to high impedance or low impedance, thereby enabling impedance matching between a circuit in which the input / output direction is reversed and the input / output impedance is switched and a transmission line. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a bidirectional amplifier circuit according to an example. [Figure 2] 1 is a Smith chart of a π-type matching circuit connected between FETs. [Figure 3] FIG. 10 is a configuration diagram of a bidirectional amplifier circuit according to another example. [Figure 4] FIG. 1 is a diagram illustrating a configuration of an example of a switching matching circuit. [Figure 5] 1 is a Smith chart of a switching matching circuit. [Figure 6] FIG. 10 is a diagram illustrating the configuration of a switching matching circuit according to another example. [Figure 7] 1 is a block diagram of a wireless transceiver circuit according to a first example. [Figure 8] FIG. 10 is a block diagram of a wireless transceiver circuit according to a second example. [Figure 9] FIG. 10 is a block diagram of a wireless transceiver circuit according to a third example. [Figure 10] FIG. 10 is a block diagram of a wireless transceiver circuit according to a fourth example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present invention, and are not intended to limit the subject matter described in the claims. Furthermore, the dimensions of each component depicted in the drawings, the detailed shapes of the details, and the like may differ from the actual ones.

[0012] <Bidirectional amplifier circuit> 1 is a configuration diagram of an example bidirectional amplifier circuit. The bidirectional amplifier circuit 10 is configured by connecting multiple amplifier circuits 11 in cascade. The bidirectional amplifier circuit 10 can be switched between a mode in which a signal is input from the left of the illustrated configuration, passed through the multiple amplifier circuits 11, amplified, and output to the right (for convenience, this mode is referred to as a TX (transmission) mode), and a mode in which a signal is input from the right, passed through the multiple amplifier circuits 11, amplified, and output to the left (for convenience, this mode is referred to as an RX (reception) mode).

[0013] Each amplifier circuit 11 is configured as a grounded-gate circuit. Specifically, the amplifier circuit 11 includes a field-effect transistor (FET) 12, a choke inductor 13 connected to an input / output terminal T1 that can be one of the source and drain of the FET 12, and a choke inductor 14 connected to an input / output terminal T2 that can be the other of the source and drain.

[0014] The FET 12 may be either an n-type or a p-type. The FET 12 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a MESFET (Metal-Semiconductor Field-Effect Transistor), a JFERT (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), or the like. Furthermore, the FET 12 may be configured with a bipolar CMOS such as SiGeBiCMOS in addition to a silicon CMOS. The choke inductors 13 and 14 may be an air-core coil, a ferrite bead, a toroidal core inductor, a multilayer chip inductor, a magnetic core inductor, a short stub, a spiral inductor formed by wiring on a semiconductor, a transmission line, or the like.

[0015] The choke inductor 13 is configured so that one end thereof is selectively applied with either the power supply voltage VDD or the ground potential GND. On the other hand, the choke inductor 14 is configured so that one end thereof is selectively applied with the other of VDD and GND. In other words, when VDD is applied to the choke inductor 13, GND is applied to the choke inductor 14, and conversely, when GND is applied to the choke inductor 13, VDD is applied to the choke inductor 14.

[0016] When VDD is applied to the choke inductor 13 and GND is applied to the choke inductor 14, the input / output terminal T1 of the FET 12 has a high impedance Z H The input / output terminal T2 has a low impedance Z L Conversely, when GND is applied to the choke inductor 13 and VDD is applied to the choke inductor 14, the input / output terminal T1 of the FET 12 becomes Z L and the input / output terminal T2 is Z HSince the gate-grounded circuit is a circuit with low impedance input and high impedance output, by switching the voltage applied to the choke inductors 13 and 14, the input / output directions of the individual amplifier circuits 11 are reversed, and the input / output direction of the bidirectional amplifier circuit 10 is also reversed.

[0017] The back gate of the FET 12 is grounded, and a bias voltage is applied to the gate. The gate bias may be constant, but considering that the signal power in the TX mode is larger than that in the RX mode, the gate bias is changed to V in the TX mode in conjunction with the switching of the applied voltage to the choke inductors 13 and 14. GTX , V in RX mode GRX In each drawing of the present application, the operating modes of the bidirectional amplifier circuit 10, the voltages applied to the gate of the FET 12 and the choke inductors 13 and 14 in each mode, and the impedance of any node in the circuit are shown separated by a slash ( / ).

[0018] Focusing on two adjacent first and second amplifier circuits 11, when VDD is applied to the choke inductor 13 of the first amplifier circuit 11, GND is applied to the choke inductor 14 of the second amplifier circuit 11. Conversely, when GND is applied to the choke inductor 13 of the first amplifier circuit 11, VDD is applied to the choke inductor 14 of the second amplifier circuit 11. Therefore, if two adjacent amplifier circuits 11 are connected by directly connecting the input / output terminal T1 of the FET 12 of the first amplifier circuit 11 to the input / output terminal T2 of the FET 12 of the second amplifier circuit 11, a current path is formed from the VDD of the choke inductor 13 of the first amplifier circuit 11 to the GND of the choke inductor 14 of the second amplifier circuit 11, or from the VDD of the choke inductor 14 of the second amplifier circuit 11 to the GND of the choke inductor 13 of the first amplifier circuit 11, resulting in a power supply short. To prevent this, the two adjacent amplifier circuits 11 are connected to each other via a DC blocking circuit 15. In the simplest configuration, DC blocking circuit 15 can be configured with capacitor 16 .

[0019] Furthermore, when attention is paid to the two adjacent first and second amplifier circuits 11 from the viewpoint of input / output impedance, the input / output terminal T1 of the FET 12 of the first amplifier circuit 11 is Z H When this occurs, the input / output terminal T2 of the FET 12 of the second amplifier circuit 11 is Z L Conversely, when the input / output terminal T1 of the FET 12 of the first amplifier circuit 11 is Z L When this occurs, the input / output terminal T2 of the FET 12 of the second amplifier circuit 11 is Z H That is, when a circuit consisting of DC blocking circuit 15 and choke inductor 13 of first amplifier circuit 11 and choke inductor 14 of second amplifier circuit 11 connected to both ends of DC blocking circuit 15 is used as π-type matching circuit 17, π-type matching circuit 17 has a capacitance of Z H to Z L To, Z L to Z H Therefore, it is necessary to be able to convert the impedance between them.

[0020] This can be expressed in a Smith chart as shown in Figure 2. Figure 2 is a Smith chart of the π-type matching circuit 17. If the characteristic impedance is Z0, then Z0 2 =Z L Z H The above-mentioned impedance mutual conversion becomes possible if the π-type matching circuit 17 is configured so that the following holds: If the inductance of the choke inductors 13 and 14 is L, the capacitance of the capacitor 16 is C, and the angular frequency of the input signal to the bidirectional amplifier circuit 10 is ω0, then: C=1 / (ω0√(Z L Z H )) …(1) L=√(Z L Z H ) / ω0…(2) That is, by setting the element values ​​of the choke inductors 13 and 14 and the capacitor 16 to the values ​​expressed by equations (1) and (2), the π-type matching circuit 17 can be H to Z L To, Z L to Z H In other words, the impedance can be converted into the other impedance.

[0021] For simplicity, the above explanation only considers the resistive component of the impedance, but in reality, the impedance at the input and output terminals T1 and T2 often becomes a complex impedance due to the influence of the parasitic capacitance of the FET 12. However, since the reactance component can be canceled out by appropriately adjusting the L values ​​of the choke inductors 13 and 14, it is easy to make the circuit characteristics of the π-type matching circuit 17 as shown in the Smith chart of Figure 2.

[0022] In order to realize the impedance conversion represented by the Smith chart of Figure 2, the input / output terminal T1 of the FET 12 of the first amplifier circuit 11 and the input / output terminal T2 of the FET 12 of the second amplifier circuit 11 may be connected to each other via a quarter-wave transmission line in two adjacent first and second amplifier circuits 11. Figure 3 is a configuration diagram of a bidirectional amplifier circuit 10 according to another example. The difference from the bidirectional amplifier circuit 10 of Figure 1 is that the DC blocking circuit 15 is composed of a quarter-wave transformer 18 and capacitors 19 connected to both ends of the transformer. The rest of the configuration is the same as in Figure 1, so a redundant description will be omitted.

[0023] In the bidirectional amplifier circuit 10 of FIG. 3, the π-type matching circuit 17 is composed of the choke inductor 13 of the first amplifier circuit 11, the choke inductor 14 of the second amplifier circuit 11, the quarter-wave transformer 18, and the capacitors 19 connected to both ends of the transformer 18. The π-type matching circuit 17 in the bidirectional amplifier circuit 10 of FIG. 3 also has a Z H to Z L To, Z L to Z H In other words, the impedance can be converted into the other impedance.

[0024] <Switching type matching circuit> When the input / output direction of the bidirectional amplifier circuit 10 is reversed, the impedance of the input / output terminal becomes Z H From Z L Or Z L From Z HTherefore, a matching circuit that matches the bidirectional amplifier circuit 10, whose input / output terminal impedances are switchable, with a transmission line having a characteristic impedance Z0 needs to be able to switch the impedance on the bidirectional amplifier circuit 10 side.

[0025] 4 is a diagram showing the configuration of an example of a switching matching circuit, in which the switching matching circuit 20 is shown connected to a bidirectional amplifier circuit 10 for convenience's sake.

[0026] The switching matching circuit 20 includes four quarter-wave transformers 21, 22, 23, and 24 and two switches 25 and 26. The quarter-wave transformers 21, 22, 23, and 24 are specifically transmission lines each having a length of a quarter wavelength. The quarter-wave transformer 21 has the narrowest line width, the quarter-wave transformer 22 is wider than the quarter-wave transformer 21, the quarter-wave transformer 23 is wider than the quarter-wave transformer 22, and the quarter-wave transformer 24 is wider than the quarter-wave transformer 23 and is the widest. In other words, the impedances of the quarter-wave transformers 21, 22, 23, and 24 are set to Z H2 , Z H1 , Z L1 , Z L2 Then, the magnitude relationship is Z H2 >Z H1 >Z L1 >Z L2 This becomes:

[0027] The quarter-wave transformers 21, 22, 23, and 24 are connected in a ring shape. For example, the quarter-wave transformers 21, 22, 23, and 24 can be configured as a ring-shaped transmission line with a total length of one wavelength, in which the line width changes every quarter wavelength.

[0028] Switch 25 is connected between the connection point or midpoint of quarter-wave transformers 21 and 22 and GND. Switch 26 is connected between the connection point or midpoint of quarter-wave transformers 23 and 24 and GND. Switches 25 and 26 can be implemented by switching transistors such as MOSFETs. Unlike the signal amplification FET 12 used in bidirectional amplifier circuit 10, the MOSFETs used in switches 25 and 26 can be optimized for switching functions, thereby minimizing losses.

[0029] The connection point or midpoint of the quarter-wave transformers 22 and 23 is the input / output port P1, and the connection point or midpoint of the quarter-wave transformers 21 and 24 is the input / output port P2. A transmission line 40 having Z0 is connected to the input / output port P1. The input / output port IO1 of the bidirectional amplifier circuit 10 is connected to the input / output port P2. The input / output port T1 of the FET 12 of the amplifier circuit 11 in the terminal stage of the bidirectional amplifier circuit 10 corresponds to the input / output port IO1.

[0030] If the input / output terminal IO1 of the bidirectional amplifier circuit 10 and the input / output terminal P2 of the switching matching circuit 20 were directly connected, a current path would be created from VDD of the choke inductor 13 of the amplifier circuit 11 in the terminal stage of the bidirectional amplifier circuit 10 to GND via the quarter-wave transformer 24 and switch 26, resulting in a short circuit of the power supply. To prevent this, the input / output terminal IO1 of the bidirectional amplifier circuit 10 and the input / output terminal P2 of the switching matching circuit 20 are connected to each other via a DC blocking capacitor 27.

[0031] The switches 25 and 26 open and close complementarily in response to a reversal of the input / output direction of the bidirectional amplifier circuit 10. That is, when the bidirectional amplifier circuit 10 switches to the RX mode, the switch 25 closes and the switch 26 opens, and when the bidirectional amplifier circuit 10 switches to the TX mode, the switch 25 opens and the switch 26 closes. Note that in each drawing of the present application, the operating states (closed = ON, open = OFF) of the switches 25 and 26 in each mode of the bidirectional amplifier circuit 10 are shown separated by a slash ( / ).

[0032] When the switches are closed and the midpoints of the two quarter-wave transformers are grounded, these quarter-wave transformers become short stubs and the impedance becomes infinite. In TX mode, switch 25 is open and switch 26 is closed, quarter-wave transformers 23 and 24 appear open from input / output terminals P1 and P2, and the impedances of quarter-wave transformers 21 and 22 come into effect. In this case, the impedances of input / output terminals P1 and P2 are Z0 and Z2, respectively. H If this is the case, the bidirectional amplifier circuit 10 in the TX mode and the transmission line 40 can be impedance-matched.

[0033] On the other hand, when switch 26 is open and switch 25 is closed, quarter-wave transformers 21 and 22 appear open from input / output terminals P1 and P2, and the impedances of quarter-wave transformers 23 and 24 come into effect. In this case, the impedances of input / output terminals P1 and P2 are Z0 and Z2, respectively. L If this is the case, the bidirectional amplifier circuit 10 in the RX mode and the transmission line 40 can be impedance-matched.

[0034] This can be expressed in a Smith chart as shown in Figure 5. Figure 5 is a Smith chart of the switching matching circuit 20. In the TX mode, the impedances of the input and output terminals P1 and P2 are Z0 and Z2, respectively. H To achieve this, the impedance Z at the midpoint of the quarter-wave transformers 21 and 22 must be MH Z MH =√(Z0Z H ) and for that, Z H2 = 4 √(Z0Z H 3 ), Z H1 = 4 √(Z0 3 Z H ) in the RX mode. L To achieve this, the impedance Z at the midpoint of the quarter-wave transformers 23 and 24 must be ML Z ML =√(Z LZ0) and for that, Z L1 = 4 √(Z L Z0 3 ), Z L2 = 4 √(Z L 3 Z0).

[0035] Fig. 6 is a configuration diagram of a switched matching circuit 20 according to another example. The switched matching circuit 20 of Fig. 6 can also achieve the impedance conversion represented by the Smith chart of Fig. 5. It differs from the switched matching circuit 20 of Fig. 4 in that a switch 26 is connected between VDD and the connection point or midpoint of the quarter-wave transformers 23 and 24, and the capacitor 27 and the choke inductor 13 connected thereto, which were present in Fig. 4, are omitted. The rest of the configuration is the same as in Fig. 4, so a redundant explanation will be omitted.

[0036] 6, the input / output terminal P2 of the switching matching circuit 20 is also the input / output terminal IO1 of the bidirectional amplifier circuit 10, and is also the input / output terminal T1 of the amplifier circuit 11 at the end stage of the bidirectional amplifier circuit 10. In the RX mode, the switch 25 is closed and the switch 26 is open, and the input / output terminal P2 of the switching matching circuit 20 is Z L and GND is applied to the input / output terminal T1 via the switch 25 and the quarter-wave transformer 21. On the other hand, in the TX mode, the switch 25 is open and the switch 26 is closed, and the input / output terminal P2 of the switching matching circuit 20 is Z H At the same time, VDD is applied to the input / output terminal T1 via the switch 26 and the quarter-wave transformer 24.

[0037] In this way, the switching matching circuit 20 in FIG. 6 can achieve the impedance conversion shown in the Smith chart in FIG. 5 without shorting out the power supply even when directly connected to the bidirectional amplifier circuit 10 without using a capacitor.

[0038] Next, several examples of wireless transceiver circuits that transmit and receive 275 GHz RF signals will be described as application examples of the bidirectional amplifier circuit 10 and the switched matching circuit 20. All of these wireless transceiver circuits can be used as front-end circuits located directly below each chip antenna in a beamforming transceiver.

[0039] <First application example> 7 is a block diagram of a wireless transceiver circuit according to a first example. The wireless transceiver circuit 100A according to this example includes two bidirectional amplifier circuits 10, a DBM (double balanced mixer) 30A, two switching type matching circuits 20A, and two switching type matching circuits 20B. Note that although the switching type matching circuits 20A and 20B are both switching type matching circuits 20, they are referred to by different reference numerals because their switching operations are opposite to each other.

[0040] The two bidirectional amplifier circuits 10 amplify a 125 GHz differential IF signal. That is, one bidirectional amplifier circuit 10 amplifies one side of the differential IF signal, and the other bidirectional amplifier circuit 10 amplifies the other side of the differential IF signal. In the figure, the bidirectional amplifier circuit 10 is shown as being configured by alternately connecting FETs 12 and π-type matching circuits 17.

[0041] The input / output terminals IO1 of the two bidirectional amplifier circuits 10 are connected to the DBM 30A, which is connected to the input / output terminals P2 of the two switching matching circuits 20A, and the input / output terminals P1 of the two switching matching circuits 20A are connected to a transmission line 40A leading to the antenna 200. More specifically, the transmission line 40A includes a balun 41 that alternately converts single-ended signals and differential signals, and the input / output terminals P1 of the two switching matching circuits 20A are connected to the differential input / output terminals of the balun 41. A 150 GHz differential LO (local oscillation) signal is input to the DBM 30A, which upconverts the 125 GHz differential IF signal to a 275 GHz differential RF signal and downconverts the 275 GHz differential RF signal to a 125 GHz differential IF signal.

[0042] The input / output terminals IO2 of the two bidirectional amplifier circuits 10 are connected to the input / output terminals P2 of the two switching matching circuits 20B, and the input / output terminals P1 of the two switching matching circuits 20B are connected to a transmission line 40B that is connected to an IF signal processing circuit (not shown). More specifically, the transmission line 40B includes a balun 41 that alternately converts single-ended signals and differential signals, and the input / output terminals P1 of the two switching matching circuits 20B are connected to the differential input / output terminals of the balun 41.

[0043] In the wireless transceiver circuit 100A, the impedances of the input / output terminals P2 of the two switching matching circuits 20A and the input / output terminals P2 of the two switching matching circuits 20B are switched in conjunction with the reversal of the input / output directions of the two bidirectional amplifier circuits 10. That is, in the RX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO1 and an amplified differential IF signal is output from the input / output terminal IO2, and the input / output terminals P2 of the two switching matching circuits 20A are switched to Z L The input / output terminals P2 of the two switching matching circuits 20B are Z H On the other hand, in the TX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO2 and an amplified differential IF signal is output from the input / output terminal IO1, and the input / output terminals P2 of the two switching matching circuits 20A are switched to Z H The input / output terminals P2 of the two switching matching circuits 20B are Z L respectively.

[0044] <Second application example> 8 is a block diagram of a wireless transceiver circuit according to a second example. A wireless transceiver circuit 100B according to this example includes two bidirectional amplifier circuits 10, an SBM (single balanced mixer) 30B, a switching matching circuit 20A, and two switching matching circuits 20B. Note that although the switching matching circuits 20A and 20B are both switching matching circuits 20, they are referred to by different reference numerals because their switching operations are opposite to each other.

[0045] The two bidirectional amplifier circuits 10 amplify a 125 GHz differential IF signal. That is, one bidirectional amplifier circuit 10 amplifies one side of the differential IF signal, and the other bidirectional amplifier circuit 10 amplifies the other side of the differential IF signal. In the figure, the bidirectional amplifier circuit 10 is shown as being configured by alternately connecting FETs 12 and π-type matching circuits 17.

[0046] The input / output ports IO1 of the two bidirectional amplifier circuits 10 are connected to the SBM 30B, which is connected to the input / output port P2 of the switching matching circuit 20A, and the input / output port P1 of the switching matching circuit 20A is connected to a transmission line 40A that is connected to the antenna 200. A 150 GHz differential LO signal is input to the SBM 30B, and upconversion from the 125 GHz differential IF signal to a 275 GHz single-ended RF signal and downconversion from the 275 GHz single-ended RF signal to a 125 GHz differential IF signal are performed.

[0047] The input / output terminals IO2 of the two bidirectional amplifier circuits 10 are connected to the input / output terminals P2 of the two switching matching circuits 20B, and the input / output terminals P1 of the two switching matching circuits 20B are connected to a transmission line 40B that is connected to an IF signal processing circuit (not shown). More specifically, the transmission line 40B includes a balun 41 that alternately converts single-ended signals and differential signals, and the input / output terminals P1 of the two switching matching circuits 20B are connected to the differential input / output terminals of the balun 41.

[0048] In the wireless transceiver circuit 100B, the impedances of the input / output terminal P2 of the switching matching circuit 20A and the input / output terminal P2 of the two switching matching circuits 20B are switched in conjunction with the reversal of the input / output directions of the two bidirectional amplifier circuits 10. That is, in the RX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO1 and an amplified differential IF signal is output from the input / output terminal IO2, and the input / output terminal P2 of the switching matching circuit 20A is switched to Z L The input / output terminals P2 of the two switching matching circuits 20B are Z HOn the other hand, in the TX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO2 and an amplified differential IF signal is output from the input / output terminal IO1, and the input / output terminal P2 of the switching matching circuit 20A is switched to Z H The input / output terminals P2 of the two switching matching circuits 20B are Z L respectively.

[0049] 7, the wireless transceiver circuit 100B uses an SBM 30B as a mixer, thereby reducing the number of switching matching circuits 20A required in the wireless transceiver circuit 100A from two to one, and omitting the balun 41 in the transmission line 40A, thereby reducing the circuit size. However, in the wireless transceiver circuit 100B, local leaks are superimposed on the received signal. Furthermore, although local leaks are not superimposed on the transmitted signal, an RF image signal is generated.

[0050] <Third application example> 9 is a block diagram of a wireless transceiver circuit according to a third example. The wireless transceiver circuit 100C according to this example includes a bidirectional amplifier circuit 10, two SBMs 30B, a matching network 31, a switching matching circuit 20A, and a switching matching circuit 20B. Note that although the switching matching circuits 20A and 20B are both switching matching circuits 20, they are referred to by different reference numerals because their switching operations are reversed.

[0051] The bidirectional amplifier circuit 10 amplifies a single-ended IF signal of 125 GHz. In the figure, the bidirectional amplifier circuit 10 is shown as being configured by alternately connecting FETs 12 and π-type matching circuits 17.

[0052] The input / output port IO1 of the bidirectional amplifier circuit 10 is connected to one SBM 30B, and the other SBM 30B is connected to the input / output port P2 of the switching matching circuit 20A, and the input / output port P1 of the switching matching circuit 20A is connected to a transmission line 40A that is connected to the antenna 200. The differential input / output ports of the two SBMs 30B are connected to each other via a matching network 31, and a 75 GHz differential LO signal is input. By using two mixers in this way and inputting a 75 GHz differential LO signal, which is half the 150 GHz frequency, to each SBM 30B, mixing can be performed with a differential LO signal of 150 GHz, which is double the frequency overall.

[0053] An input / output terminal IO2 of the bidirectional amplifier circuit 10 is connected to an input / output terminal P2 of the switching matching circuit 20B, and an input / output terminal P1 of the switching matching circuit 20B is connected to a transmission line 40B that is connected to an IF signal processing circuit (not shown).

[0054] In the wireless transceiver circuit 100C, the impedances of the input / output terminal P2 of the switching matching circuit 20A and the input / output terminal P2 of the switching matching circuit 20B are switched in conjunction with the reversal of the input / output direction of the bidirectional amplifier circuit 10. That is, in the RX mode, the input / output direction of the bidirectional amplifier circuit 10 is switched so that an IF signal is input to the input / output terminal IO1 and an amplified IF signal is output from the input / output terminal IO2, and the input / output terminal P2 of the switching matching circuit 20A is switched to Z L The input / output terminal P2 of the switching matching circuit 20B is Z H On the other hand, in the TX mode, the input / output direction of the bidirectional amplifier circuit 10 is switched so that an IF signal is input to the input / output terminal IO2 and an amplified IF signal is output from the input / output terminal IO1, and the input / output terminal P2 of the switching matching circuit 20A is switched to Z H The input / output terminal P2 of the switching matching circuit 20B is Z L respectively.

[0055] 8, the wireless transceiver circuit 100C has two SBMs 30B configured, which allows the frequency of the differential LO signals input to each SBM 30B to be halved to 75 GHz, thereby reducing the power consumption of the amplifier circuit for the differential LO signals (not shown).Furthermore, because only one bidirectional amplifier circuit 10 is required, the circuit size can be reduced and local leak of the received signal can be eliminated.

[0056] <Fourth Application Example> 10 is a block diagram of a wireless transceiver circuit according to a fourth example. A wireless transceiver circuit 100D according to this example includes two bidirectional amplifier circuits 10, two DBMs 30A, two switching matching circuits 20A, and two switching matching circuits 20B. Note that although the switching matching circuits 20A and 20B are both switching matching circuits 20, they are referred to by different reference numerals because their switching operations are opposite to each other.

[0057] The two bidirectional amplifier circuits 10 amplify a 125 GHz differential IF signal. That is, one bidirectional amplifier circuit 10 amplifies one side of the differential IF signal, and the other bidirectional amplifier circuit 10 amplifies the other side of the differential IF signal. In the figure, the bidirectional amplifier circuit 10 is shown as being configured by alternately connecting FETs 12 and π-type matching circuits 17.

[0058] The input / output terminals IO1 of the two bidirectional amplifier circuits 10 are connected to one DBM 30A, and the other DBM 30A is connected to the input / output terminals P2 of two switching matching circuits 20A. Furthermore, the input / output terminals P1 of the two switching matching circuits 20A are connected to a transmission line 40A leading to an antenna 200. More specifically, the transmission line 40A includes a balun 41 that alternately converts single-ended signals and differential signals, and the input / output terminals P1 of the two switching matching circuits 20A are connected to the differential input / output terminals of the balun 41. The differential input / output terminals of the two DBMs 30A are connected to each other, and a 75 GHz differential LO signal is input to each. By using a two-stage mixer in this way and inputting a 75 GHz differential LO signal, half the 150 GHz frequency, to each DBM 30B, mixing can be performed with a differential LO signal of 150 GHz, double the overall frequency.

[0059] The input / output terminals IO2 of the two bidirectional amplifier circuits 10 are connected to the input / output terminals P2 of the two switching matching circuits 20B, and the input / output terminals P1 of the two switching matching circuits 20B are connected to a transmission line 40B that is connected to an IF signal processing circuit (not shown). More specifically, the transmission line 40B includes a balun 41 that alternately converts single-ended signals and differential signals, and the input / output terminals P1 of the two switching matching circuits 20B are connected to the differential input / output terminals of the balun 41.

[0060] In the wireless transceiver circuit 100D, the impedances of the input / output terminals P2 of the two switching matching circuits 20A and the input / output terminals P2 of the two switching matching circuits 20B are switched in conjunction with the reversal of the input / output directions of the two bidirectional amplifier circuits 10. That is, in the RX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO1 and an amplified differential IF signal is output from the input / output terminal IO2, and the input / output terminals P2 of the two switching matching circuits 20A are switched to Z L The input / output terminals P2 of the two switching matching circuits 20B are Z HOn the other hand, in the TX mode, the input / output directions of the two bidirectional amplifier circuits 10 are switched so that a differential IF signal is input to the input / output terminal IO2 and an amplified differential IF signal is output from the input / output terminal IO1, and the input / output terminals P2 of the two switching matching circuits 20A are switched to Z H The input / output terminals P2 of the two switching matching circuits 20B are Z L respectively.

[0061] Compared to the wireless transceiver circuit 100A in FIG. 7, the wireless transceiver circuit 100D has a two-stage DBM30A configuration, which allows the frequency of the differential LO signal input to each DBM30A to be halved to 75 GHz, thereby reducing the power consumption of the amplifier circuit for the differential LO signal (not shown).

[0062] Effect The bidirectional amplifier circuit 10 according to this embodiment can reverse the input / output direction of a signal by swapping the source and drain of the FET 12. This eliminates the need for separate transistors for input and output directions, allowing the overall circuit size to be reduced. Furthermore, because no transistors are idle and all transistors are active, gain reduction due to the parasitic capacitance of idle transistors is eliminated, allowing basic characteristics to be maintained at a good level.

[0063] Furthermore, the switching matching circuit 20 according to this embodiment has one input / output terminal (input / output terminal P1) fixed to Z0 while the other input / output terminal (input / output terminal P2) is set to Z H or Z L This allows impedance matching between the bidirectional amplifier circuit and the transmission line 4, in which the input / output direction is reversed and the input / output impedance is switched.

[0064] <<Variations>> In the radio transceiver circuits 100A to 100D, it is not necessary to use a combination of the bidirectional amplifier circuit 10 according to the embodiment and the switching matching circuit 20. The above-described bidirectional amplifier circuit 10 may be combined with a switching matching circuit having a configuration other than that described above, or the above-described switching matching circuit 20 may be combined with a bidirectional amplifier circuit 10 having a configuration other than that described above.

[0065] As described above, the embodiments have been described as examples of the technology of the present invention. For this purpose, the accompanying drawings and detailed description have been provided. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to exemplify the above technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential. Furthermore, because the above-described embodiments are intended to exemplify the technology of the present invention, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents. [Explanation of symbols]

[0066] 10 Bidirectional amplifier circuit 11 Amplification circuit IO1 Input / Output Terminal (First Input / Output Terminal) IO2 Input / Output Terminal (First Input / Output Terminal) 12 FET (Field Effect Transistor) T1 input / output terminal (first input / output terminal) T2 input / output terminal (second input / output terminal) 13 Choke inductor (first choke inductor) 14 Choke inductor (second choke inductor) 15 DC interruption circuit 16 Capacitors 17 π-type matching circuit 18 1 / 4 wavelength transformer 19 Capacitor 20 Switched matching circuit 20A Switched Matching Network (First Switched Matching Network) 20B Switched Matching Circuit (Second Switched Matching Circuit) P1 input / output terminal (first input / output terminal) P2 input / output terminal (second input / output terminal) 21 Quarter Wave Transformer (First Quarter Wave Transformer) 22 Quarter Wave Transformer (Second Quarter Wave Transformer) 23 Quarter Wave Transformer (Third Quarter Wave Transformer) 24 Quarter Wave Transformer (Fourth Quarter Wave Transformer) 25 Switch (First Switch) 26 Switch (Second Switch) 100A~100D Wireless transmitter / receiver circuit 200 Antennas 30A DBM (mixer) 30B SBM (mixer) 40A transmission line (first transmission line) 40B Transmission Line (Second Transmission Line)

Claims

1. a first quarter-wave transformer, a second quarter-wave transformer wider than the first quarter-wave transformer, a third quarter-wave transformer wider than the first quarter-wave transformer, and a fourth quarter-wave transformer wider than the first quarter-wave transformer, connected in a ring; a first switch connected between a junction point of the first quarter-wave transformer and the second quarter-wave transformer and a ground potential; a second switch connected between a connection point of the third quarter-wave transformer and the fourth quarter-wave transformer and a ground potential; a connection point between the second quarter-wave transformer and the third quarter-wave transformer is used as a first input / output end, and the impedance of the first input / output end matches a characteristic impedance; a connection point between the first quarter-wave transformer and the fourth quarter-wave transformer serving as a second input / output end, and a switchable matching circuit configured such that the first switch and the second switch are complementarily opened and closed to match the impedance of the second input / output end to a high impedance or a low impedance.

2. a first quarter-wave transformer, a second quarter-wave transformer wider than the first quarter-wave transformer, a third quarter-wave transformer wider than the first quarter-wave transformer, and a fourth quarter-wave transformer wider than the first quarter-wave transformer, connected in a ring; a first switch connected between a junction point of the first quarter-wave transformer and the second quarter-wave transformer and a ground potential; a second switch connected between a connection point of the third quarter-wave transformer and the fourth quarter-wave transformer and a power supply voltage; a connection point between the second quarter-wave transformer and the third quarter-wave transformer is used as a first input / output end, and the impedance of the first input / output end matches a characteristic impedance; a connection point between the first quarter-wave transformer and the fourth quarter-wave transformer serving as a second input / output end, and a switchable matching circuit configured such that the first switch and the second switch are complementarily opened and closed to match the impedance of the second input / output end to a high impedance or a low impedance.

3. A bidirectional amplifier circuit configured so that the input / output direction can be reversed; a first and a second switching matching circuit according to claim 1 or 2; a mixer connected to a first input / output terminal of the bidirectional amplifier circuit, the first input / output terminal of the first switched matching circuit is connected to a first transmission line on an antenna side, and the second input / output terminal is connected to the mixer; the first input / output terminal of the second switched matching circuit is connected to a second transmission line, and the second input / output terminal is connected to a second input / output terminal of the bidirectional amplifier circuit; a bidirectional amplifier circuit configured to switch the impedances of the second input and output terminals of the two switching matching circuits so that they are opposite to each other in response to a reversal of the input and output directions of the bidirectional amplifier circuit;

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