Gaming machine

Abstract

To provide a game machine capable of enriching a generator performance without trouble.SOLUTION: This device is provided with a driver DV5 for rotationally driving a DC motor, a cam member for converting the rotational motion of the DC motor into linear motion, and a control means 50 for controlling the driver DV5, and the control means 50 regulates the rotation of the DC motor by designating the rotational direction and rotational torque of the DC motor.SELECTED DRAWING: Figure 68

Description

[Technical Field]

[0001] The present invention relates to a gaming machine that performs a lottery process based on game actions and executes image effects corresponding to the lottery results, and in particular to a gaming machine that can stably execute impressive accessory effects and image effects. [Background technology]

[0002] A pinball game machine such as a pachinko machine is configured with a symbol start opening on the game board, a symbol display unit that displays a series of symbol changes based on multiple displayed symbols, and a jackpot opening with an opening / closing plate. When a detection switch on the symbol start opening detects the passage of a game ball, the machine enters a winning state. After the game ball is paid out as a prize ball, the displayed symbols on the symbol display unit change for a predetermined period of time. When the symbols then stop in a predetermined pattern, such as 7-7-7, the machine enters a jackpot state, and the jackpot opening is repeatedly opened, creating a game state advantageous to the player.

[0003] Whether or not such a game state occurs is determined by a jackpot lottery, which is executed on the condition that a gaming ball enters the symbol start slot, and the above-mentioned symbol variation action is based on the result of this lottery. For example, if the lottery result is a winning state, a presentation action called a reach action is executed for about 20 seconds, and then special symbols are aligned. On the other hand, a similar reach action may be executed even in a losing state, and in this case, the player will closely watch the progression of the presentation action while strongly hoping for a jackpot state. Then, if the predetermined symbol is aligned on the stop line at the end of the symbol variation action, the player is guaranteed a jackpot state.

[0004] The pattern change operation is usually performed in a liquid crystal display unit (Patent Documents 1 to 4), and the H x V dot pixels that make up the liquid crystal display unit are driven in synchronization with an operating clock CK (=dot clock DCK) to update the display. In order to smoothly perform the display update operation (frame update), certain conditions, such as those shown in Figure 42(g), are required for the pulse widths of the horizontal synchronization signal HS and the vertical synchronization signal VS, and the timing between each synchronization signal HS, Vs and the transmission timing of the image signal.

[0005] Under the driving conditions shown in the figure, the pulse width PWh of the horizontal synchronizing signal HS is 96 clocks of the operating clock CK, and the front porch FPh and back port BPh required before and after the horizontal synchronizing signal PWh are specified as 16 and 48 clocks of the operating clock CK, respectively. On the other hand, the pulse width PWv of the vertical synchronizing signal VS is 2 lines, and the front porch FPv and back port BPv required before and after the vertical synchronizing signal VS are specified as 19 and 33 lines, respectively.

[0006] The external control device that controls the LCD display unit repeatedly supplies the LCD display unit with a horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh), as well as an image signal that corresponds to the number of pixels on the display screen.

[0007] In addition to the pattern changing action using the LCD display, a preview effect may also be performed in which a movable object called a "gimmick" moves appropriately to give an uncertain advance notice of the lottery result. Also, even after a jackpot state has been reached, the bonus effect may be performed to effectively excite the player.

[0008] The props are usually driven and controlled by a stepping motor, but bipolar drive motors are mainly used because they are easy to control (Patent Documents 5 and 6). Also known is a vibration effect in which props such as sword sheaths vibrate up and down (Patent Document 7). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2017-093633 [Patent Document 2] Japanese Patent Application Publication No. 2017-093632 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-159030 [Patent Document 4] Japanese Patent Application Laid-Open No. 2016-159029 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-007258 [Patent Document 6] Japanese Patent Application Publication No. 2018-153304 [Patent Document 7] Japanese Patent Application Publication No. 2018-192168 Summary of the Invention [Problem to be solved by the invention]

[0010] However, in this type of gaming machine, there is a strong demand for more complex and varied effects, especially for image effects using liquid crystal displays. There is also a demand for more varied bonus effects. Here, to achieve the vibration effect of vibrating the device, a cam member is inserted to convert the rotational motion of the DC motor into linear motion (Patent Document 7), but there is also the problem of the DC motor overheating depending on the player's operation. That is, a DC motor generally increases its motor current in response to an increase in torque, and if a player grips the vibration device tightly, the motor current increases in response to the increase in torque, and in the worst case, the motor coil windings may burn out. Furthermore, no configuration is known that increases the rotational torque while avoiding the occurrence of an overcurrent state in a vibration effect in which the device vibrates slightly.

[0011] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a gaming machine in which various presentation actions, including role presentations, are further improved. [Means for solving the problem]

[0012] In order to achieve the above object, the present invention provides an amusement machine comprising a driver for driving a DC motor to rotate, a transmission means for transmitting the rotational motion of the DC motor, and a control means for controlling the driver, wherein the control means regulates the rotation of the DC motor by specifying the rotation direction and rotational torque of the DC motor to the driver. [Effects of the Invention]

[0013] According to the present invention, the rotation direction and rotation torque of the DC motor are regulated by the control means, allowing for trouble-free and abundant role-playing effects and sophisticated performance. In other words, even if a player strongly restrains the vibrator, the drive current is not increased to increase torque (see Figure 68(b)), eliminating the risk of overheating and the risk of the coil windings burning out. Furthermore, according to the present invention, the rotation torque of the DC motor can be freely controlled, allowing for a variety of role-playing effects, such as vibrations, and the DC motor can be stopped simply by setting the rotation torque to 0. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a perspective view showing a pachinko machine according to an embodiment of the present invention; [Figure 2] 2 is a front view showing the gaming area of ​​the gaming machine of FIG. 1. [Figure 3] FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] 1 is a diagram illustrating specifications of a display device. [Figure 5] FIG. 2 is a block diagram illustrating the internal configuration of the display device. [Figure 6] 1 is a diagram illustrating the circuit configuration and operation of a power supply control circuit. [Figure 7] 2 is a block diagram showing in some detail the circuit configuration of the performance control unit of the gaming machine of FIG. 1. FIG. [Figure 8]10 is a diagram illustrating a composite chip that constitutes a performance control unit. [Figure 9] FIG. 5 is a block diagram showing the internal configuration of the CPU circuit shown in FIG. [Figure 10] This is an illustration of the memory map of the CPU circuit's built-in CPU (performance control CPU). [Figure 11] 1 is a diagram illustrating various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) for a DMAC. [Figure 12] 1 is a diagram illustrating an index space, an index table, a virtual drawing space, and a drawing area. [Figure 13] FIG. 2 is a block diagram illustrating the internal configuration of a data transfer circuit together with related circuit configurations. [Figure 14] FIG. 2 is a block diagram showing the internal configuration of a display circuit together with related circuit configurations. [Figure 15] 10 is a diagram illustrating a data valid signal ENAB output from a VDP circuit. [Figure 16] 10 is a flowchart illustrating a power reset operation after a CPU reset. [Figure 17] 17 is a flowchart illustrating a memory section initialization process that is part of FIG. 16. [Figure 18] 17 is a flowchart illustrating a main introduction process and an interrupt process, which are part of FIG. 16. [Figure 19] 10 is a flowchart illustrating a CGROM initialization process that is part of the main installation process. [Figure 20] 10 is a flowchart illustrating the operation of another embodiment using interrupt processing. [Figure 21] 19 is a flowchart illustrating the main introduction process following FIG. 18, and the process up to the steady-state process. [Figure 22] 22 is a flowchart illustrating the steady-state processing following FIG. 21. [Figure 23] 1 is a diagram illustrating the configuration of a display list. [Figure 24]10 is a flowchart showing a DL issuing process for issuing a display list DL. [Figure 25] 25 is a flowchart illustrating an operation when a DMAC is involved in the operation of FIG. 24. [Figure 26] 26 is a flowchart illustrating an operation subsequent to the processing of FIG. 25. [Figure 27] 10 is a flowchart illustrating a routine process when a preloader is used. [Figure 28] 28 is a flowchart illustrating a part of FIG. 27. [Figure 29] 28 is a flowchart illustrating another part of FIG. 27. [Figure 30] 10 is a time chart showing the operation of each part of the VDP in an embodiment in which a preloader is not used. [Figure 31] 10 is a time chart showing the operation of each part of the VDP in an embodiment using a preloader. [Figure 32] FIG. 10 is a block diagram showing the overall circuit configuration of another embodiment. [Figure 33] FIG. 33 is a block diagram showing a portion of FIG. 32 in some detail. [Figure 34] 10 is a time chart illustrating the operation of another embodiment. [Figure 35] 10 is a diagram illustrating yet another embodiment. [Figure 36] 10 is a diagram illustrating an embodiment in which a set value is repeatedly set. [Figure 37] 1 is a diagram illustrating a circuit configuration of an embodiment using a built-in audio circuit. [Figure 38] 10 is a flowchart illustrating an initial setting operation of the audio circuit. [Figure 39] 10 is a diagram illustrating another embodiment of a power reset operation after a CPU reset. [Figure 40] 10 is a time chart showing an example of a memory read operation and a memory write operation. [Figure 41] 10 is a diagram illustrating another embodiment. [Figure 42] 1 is a diagram illustrating a method of driving a general display device. [Figure 43] 1 is a diagram illustrating a display list. [Figure 44] 10 is a diagram illustrating a zoom preview. [Figure 45] 10 is a diagram illustrating a CPU process for realizing a rotation operation. [Figure 46] 1 is a diagram showing the basis of a calculation formula. [Figure 47] 4 is a time chart showing the deformation operations of the backlight unit and the liquid crystal display unit when the power is turned on. [Figure 48] 10 is a time chart showing another transformation operation of the backlight unit and the liquid crystal display unit when the power is turned on. [Figure 49] FIG. 2 is a block diagram illustrating a circuit configuration for realizing a special effect. [Figure 50] This diagram illustrates the internal configuration of the serial port and the connection relationship with the motor driver and sensor board. [Figure 51] 4 is a diagram illustrating an internal configuration of a sensor substrate. [Figure 52] 1 is a diagram illustrating a motor driver. [Figure 53] 10 is a diagram illustrating the operation of a bridge driving circuit. [Figure 54] 4 is a time chart illustrating a constant current control operation. [Figure 55] 1 is a detailed diagram of a portion of a motor driver. [Figure 56] This diagram illustrates the relationship between the drive data received by the motor driver and the drive currents of phases A and B. [Figure 57] FIG. 2 is a block diagram showing the internal configuration of a motor driver. [Figure 58] 10 illustrates the relationship between the stepping clock and the drive current that is controlled to be a constant current. [Figure 59] FIG. 2 is a block diagram showing the internal configuration of a motor controller. [Figure 60] 1 is a diagram illustrating various driving methods. [Figure 61] This shows the details of the timer interrupt process, and is a detailed version of the contents of FIG. 22(b). [Figure 62] 4 is a time chart illustrating the operation of the motor controller. [Figure 63] 10 is a time chart illustrating the operation of a serial port. [Figure 64] This is a diagram illustrating a spiral shaft and an example of a role-playing device effect. [Figure 65] This is a diagram explaining the use of a DC motor for prop production. [Figure 66] 1 is a diagram illustrating a driving procedure of a DC motor. [Figure 67] 1 is a diagram illustrating a control method and control performance of a DC motor. [Figure 68] 1 is a diagram illustrating an embodiment in which a DC motor is continuously rotated in one direction. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described in detail below with reference to the following embodiments. FIG. 1 is a perspective view of a pachinko machine GM according to this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached so as to be able to open and close via hinges 2 fixed to the outer frame 1. A game board 5 is detachably attached to the inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be able to open and close. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the "front door member." The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may also be referred to as the "game frame."

[0016] Illuminated lamps such as LED lamps are arranged in a roughly C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right sides and on the lower side of the glass door 6. The two upper speakers output audio for the left and right channels R and L, respectively, and the lower speaker is configured to output low-pitched sounds.

[0017] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0018] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is normally inactive, but when the game state is in the button chance state, a built-in lamp lights up and the button becomes operable. The button chance state is a game state that is set as needed.

[0019] In addition, a rotary switch-type volume switch VLSW is located below the chance button 11, and by operating the volume switch VLSW, the player can adjust the speaker volume in eight stages, from silent (=0) to the highest level (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial setting volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality alert sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume, regardless of the volume initially set by the attendant or the volume set by the player.

[0020] On the right side of the upper tray 8, there is provided an operation panel 12 for operating the ball lending operation for the card-type ball lending machine, which is provided with a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of game balls for a specified amount, and a return switch that commands the return of the card when the game ends.

[0021] As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in approximately the center of the guide rail 13. A movable effect body (not shown) is stored in a concealed state below the central opening HO, and during the movable preview effect, the movable effect body rises and becomes exposed, thereby realizing a preview effect with a predetermined reliability. Here, the preview effect is an effect that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the preview effect means the probability that the jackpot state will occur.

[0022] A main display device DS1 consisting of a large (e.g., 1280 horizontal x 1024 vertical pixels) liquid crystal color display is disposed in the central opening HO, and a movable sub-display device DS2 consisting of a small (e.g., 480 horizontal x 800 vertical pixels) liquid crystal color display is disposed to the right of the main display device DS1. The main display device DS1 is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that variably displays specific symbols related to the jackpot state as well as animated background images and various characters. This display device DS1 has special symbol display units Da-Dc in the center and a normal symbol display unit 19 in the upper right corner. The special symbol display units Da-Dc may execute reach effects that anticipate the arrival of a jackpot state, and appropriate preview effects are executed in and around the special symbol display units Da-Dc.

[0023] The sub display device DS2 normally displays image information in a static state with its display screen tilted at an angle that is easy for the player to see. However, during a predetermined preview performance, the tilt angle is changed to an angle that is easy for the player to see, and the predetermined preview image is displayed while moving to the left side in the figure.

[0024] In other words, the sub-display device DS2 of the embodiment is not just a display device, but also functions as a movable display device that executes preview effects. Here, the preview effects by the sub-display device DS2 are set to have a high reliability, so players will pay attention to the movement of the sub-display device DS2 with great anticipation. The sub-display device DS2 also consists of a sub-LCD unit MONI and an LED backlight unit BL.

[0025] The game area where the game balls fall and move is provided with a first symbol start opening 15a, a second symbol start opening 15b, a first big prize opening 16a, a second big prize opening 16b, a normal prize opening 17, and a gate 18. Each of these winning openings 15 to 18 has a detection switch inside, so that it can detect the passage of the game balls.

[0026] Above the first symbol start opening 15a, there is arranged a performance stage 14 configured so that the gaming ball that has entered from the introduction opening IN can move in a seesaw or roulette shape and then enter the first symbol start opening 15. When the gaming ball enters the first symbol start opening 15, the variable operation of the special symbol display sections Da to Dc is started.

[0027] The second pattern starting port 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0028] The normal symbol display unit 19 displays normal symbols, and when a gaming ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time and stops by displaying a stopping symbol determined by a random number value for lottery that is extracted at the time the gaming ball passes through the gate 18.

[0029] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first symbol starting opening 15a, and the second large prize opening 16b is configured to correspond to the first symbol starting opening 15b.

[0030] In other words, when a game ball enters the first pattern start port 15a, the special pattern display sections Da to Dc begin to change, and then when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the slide plate of the first jackpot entry port 16a opens forward, making it easier for the game ball to enter.

[0031] On the other hand, as a result of the varying operation initiated by the entry of a gaming ball into the second symbol start opening 15b, when a predetermined jackpot symbol is aligned in the special symbol display sections Da to Dc, a special game representing a second jackpot is initiated, and the opening and closing plate of the second large winning opening 16b is opened to facilitate the entry of the gaming ball. The gaming value of the special game (jackpot state) varies depending on the aligned jackpot symbols, etc., but which gaming value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the gaming ball.

[0032] In a typical jackpot state, after the opening / closing plate of the jackpot opening 16 is opened, the opening / closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered. This operation may continue up to, for example, 15 times, and is controlled to be advantageous to the player. If the stopped symbol after the change of the special symbol display sections Da to Dc is a specific symbol among the special symbols, a special benefit is given in which the game after the special game ends will be in a high probability state (probability variable state).

[0033] Fig. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI arranged on the payout control board 25, and Fig. 3(c) is a diagram explaining the specifications of the main display device DS1 used in this embodiment.

[0034] First, the specifications of the main display device DS1 used in this embodiment will be described with reference to Figure 3(c). As explained above, this display device DS1 is a liquid crystal color display with 1280 horizontal and 1024 vertical pixels, and is configured so that adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) in the left-right direction are received by the receiver RV (RVa+RVb) via separate LVDS (Low Voltage Differential Signaling) transmission paths. Therefore, in this embodiment, in accordance with this dual link specification, the ODD signal is transmitted via the first transmission path LVDS1, and the EVEN signal is transmitted via the second transmission path LVDS2 (lower right of Figure 3(a)).

[0035] Furthermore, in this display device DS1, the frequency of the operation clock CK (see FIG. 42) that defines the internal operation of the display device DS1 is specified to be in the range of 40 MHz to 70 MHz (typical value = 54 MHz). This operation clock CK corresponds to the LVDS clock CLK described later, but for the sake of convenience, the frequency of the operation clock CK will be assumed to be a typical value of 54 MHz below. Also, a configuration will be described in which the update time FR (Frame Rate) required to update one frame of image with a 54 MHz operation clock CK is made to coincide with approximately 1 / 60 seconds.

[0036] This display device DS1 is configured to simultaneously process two adjacent pixels on the left and right of the display screen using a single operating clock CK, based on the ODD signal received from the first transmission path LVDS1 and the EVEN signal received from the second transmission path LVDS2. As a result, the pixel data for 1280 pixels on one horizontal line is updated in an operating time of 640 / 54 MHz = 11.85 μS, and this operation is repeated for 1024 lines, updating one frame of 1280 x 1024 pixel image display. The image is updated line by line in a non-interlaced manner, from the first line → the second line → the 1024th line.

[0037] 3(c), the specifications of the display device DS1 stipulate that a typical waiting time (blank period) of 204 clocks be provided in the horizontal direction, and a typical waiting time (blank period) of 42 rows be provided in the vertical direction. Therefore, the actual screen update period FR taking these blank periods into consideration is calculated based on the typical values ​​described above as (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 mS, so the frame rate FR is approximately 1 / 60 Hz.

[0038] Note that the horizontal waiting time WTh and the vertical waiting time WTv each have a specified tolerance for their typical values, and in practice, values ​​different from the typical values ​​described above can be selected. However, to set the frame rate FR to 1 / 60 seconds, the horizontal and vertical waiting times WTh / WTv must be accurately set so that (WTh+640)×(WTv+1024) / 54MHz=1 / 60 seconds.

[0039] On the other hand, this display device DS1 does not particularly need to receive the horizontal synchronizing signal HS and the vertical synchronizing signal VS, but it does require the transmission of an H-level data valid signal ENAB when transmitting the ODD and EVEN signals. In other words, when significant signals (ODD / EVEN signals) are being transmitted to the transmission paths LVDS1 and LVDS2, the data valid signal ENAB must be at an active level (H).

[0040] Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the performance control board 23 and the main display device DS1 are LVDS-connected via a dual-link transmission path of an LVDS clock CLK with a frequency of 54 MHz (= 1 / 2 the dot clock DCK) (Figs. 5 and 14(a)). Also, in the VDP circuit 52 of this embodiment, a horizontal blank period WTh and a vertical blank period WTv that satisfy the specifications of the main display device DS1 are provided, and when image data (ODD / EVEN signals) are output, the data valid signal ENAB is set to an active level (H level).

[0041] That is, as shown in Fig. 4(b), the data valid signal ENAB is configured to be H level only during the horizontal display period THd of the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always L level during the vertical synchronization period TV other than the vertical display period TVd. Note that the horizontal blanking period WTh and the vertical blanking period WTv adopt values ​​different from their respective typical values ​​(WTh = 204 / WTv = 42), but specific design values ​​will be described later with reference to Fig. 15.

[0042] In either case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal via the differential signal lines RA2 / RB2 in each operating cycle of the LVDS clock CLK. The data valid signal ENAB shown in Figures 4(b) and 4(c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous DE signal on the time axis. Note that the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted on the differential signal lines RA2 / RB following the DE signal (data valid signal ENAB), but the main display device DS1 used in this embodiment does not utilize these synchronization signals VS and HS.

[0043] However, the display device DS1 does not prohibit the transmission of the horizontal synchronizing signal HS or the vertical synchronizing signal VS. However, the internal operations defined by these synchronizing signals are not executed. In other words, the horizontal line feed timing of the display line is defined to be optimal for the internal circuitry of the display device DS1 based on the falling edge of the data valid signal ENAB and the number of operating clocks CK (corresponding to the LVDS clock CLK) (640 = 1280 / 2 in this embodiment) after the rising edge of the data valid signal ENAB, regardless of the received horizontal synchronizing signal HS (downward arrow in FIG. 4(b)).

[0044] The same is true for the vertical line feed timing after one frame of image display, which is determined to be optimal for the internal circuitry of the display device DS1 based on the number of consecutive data valid signals ENAB of a predetermined pulse width (1024 in this embodiment) and is not affected by the received vertical synchronization signal VS (downward arrow in FIG. 4(c)). In this way, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or the vertical synchronization signal VS to the display device DS1, so there is no need to optimally set the pulse widths PWh / PWv of the synchronization signals HS and VS, the front ports FPh / FPv, and the back ports BPh / BPv, and the control burden on the performance control unit 23 and the VDP circuit 52 is greatly reduced.

[0045] Furthermore, the internal operation of the display device DS1 is to execute horizontal and vertical line feed operations at optimal timing based on its own internal configuration, eliminating the risk of unnatural display behavior.Incidentally, in the case of a display device that operates based on an externally received horizontal synchronizing signal HS or vertical synchronizing signal VS, if the pulse width of the synchronizing signals HS and VS or the front porch period and back porch period before and after the synchronizing signals HS and VS are inappropriate, normal display behavior may be impaired.

[0046] 4(a), the first differential signal LVDS1 using differential signal lines RA0 to RA3 and RACLK transmits odd-numbered pixels (ODD signal on side A), and the second differential signal LVDS2 using differential signal lines RB0 to RB3 and RBCLK transmits even-numbered pixels (EVEN signal on side B). In this way, in this embodiment, by transmitting two types of ODD signals and EVEN signals over a dual-link transmission path, the frequency of the dot clock DCK can be reduced by half, which improves noise resistance and also increases the transmission distance.

[0047] On the other hand, the main display device DS1 has a built-in conversion receiver RV for the ODD signal and the EVEN signal transmitted over the dual link transmission line, and restores the RGB signal from the two LVDS signals (ODD signal and EVEN signal) to display one frame of image (1280 x 1024 dots). As explained above, each RGB signal is composed of 8 bits, so the main display device DS1 can display an image with a gradation of 2 8 ×2 8 ×2 8 A full color image is displayed.

[0048] 5 is a block diagram illustrating the internal configuration of the liquid crystal display unit MONI of a display device DS1 composed of a main liquid crystal display unit MONI and an LED backlight unit BL, particularly illustrating the internal configuration of the liquid crystal display unit MONI together with the relevant parts of the VDP circuit 52. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (side A), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second LVDS line (side B). Of the 8-bit RGB data transmitted over the differential lines RA0 / RB0, image data R0-R5 and G0 are extracted, and image data G1-G5 and B0-B1 are extracted from the differential lines RA1 / RB1.

[0049] Moreover, image data B2-B5, DE signal, VS signal, and HS signal are extracted from the differential line RA2 / RB2, and image data G6-G7, R6-R7, and B6-B7 are extracted from the differential line RA3 / RB3. Here, the DE signal is nothing but the data valid signal ENAB. Also, as mentioned above, the extracted VS signal and HS signal are not used.

[0050] Next, the LVDS clock CLK of the differential lines RACK / RBCK is supplied to a PLL circuit to generate an operating clock CK with the same frequency of 54 MHz as the LVDS clock CLK. This operating clock CK regulates the internal operation of the liquid crystal controller LCD_CTL, which processes image data corresponding to two adjacent RGB pixels (8 bits x 3 x 2) on the left and right of the liquid crystal panel LCD in unison, in synchronization with a single operating clock CK.

[0051] Therefore, a pixel with 1280 (=640 x 2) dots in the horizontal direction will be processed in 11.85 μS (=640 / 54 MHz), which is the processing time for 640 clocks. Each pixel is made up of three basic RGB pixels, and the image data for each of the three basic RGB pixels is one byte long and has a gradation of 2. 8 ×2 8 ×2 8 Therefore, the image data for all pixels (1280 dots) on one line is 3×1280 bytes long overall.

[0052] As shown in Figure 5, the LCD controller LCD_CNT divides 1280 source signal lines into 2 8It appropriately controls the source driver SDV, which is driven by a drive signal with (=256) gradations, and the gate driver GDV, which controls the ON / OFF of 1024 gate signal lines. Specifically, the liquid crystal controller LCD_CNT realizes image update operations at a frame rate FR=1 / 60 Hz by appropriately operating each component based on the DE signal extracted from the LVDS transmission line and the operating clock CK. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

[0053] In this embodiment, the source driver SDV is configured with 10 driver elements, each with 384 output terminals. As explained above, all pixels (1280 dots) on one line of the liquid crystal panel LCD are composed of 3 x 1280 basic pixels of three colors, RGB, for a total of 10 driver elements to drive them. Image data DAT is sequentially supplied to these 10 driver elements from the liquid crystal controller LCD_CNT, and is transferred appropriately based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, analog-converted drive signals are supplied to 3840 source signal lines. As explained above, the time required to update all pixels (1280 dots) on one line of the liquid crystal panel LCD is 11.85 μS (= 640 / 54 MHz).

[0054] Meanwhile, the LCD controller LCD_CNT updates the gate signal lines to be driven by supplying a gate start signal GS and a gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured with four driver elements, each with 256 output terminals.

[0055] The update timing of the gate signal line is determined based on the falling edge of the DE signal and the operating clock CK, and the horizontal line feed period of the gate signal line is counted by the operating clock CK, and is calculated as 640 + 204 clocks in typical value calculation (see FIG. 3(c)). Based on the number of DE signals (1024), the gate signal line to be driven is reset to its initial state, and the gate start signal GS is output at the optimal timing, and the output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal line is counted by the operating clock CK, and is calculated as 42 + 1024 clocks in typical value calculation (see FIG. 3(c)). However, as explained above, in this embodiment, the display device DS1 is operated using a design different from the typical value (see FIG. 15).

[0056] The above display operation requires that a power supply voltage of 5V is supplied to the main LCD display unit MONI when the LED backlight unit BL is lit. Therefore, in this embodiment, a power supply control circuit SPY is provided to operate the LCD display unit MONI and the backlight unit BL in a coordinated manner. The power supply control circuit SPY receives three types of DC voltages (3.3V, 5V, 12V) from the performance interface board 22, and also receives various power supply control signals (STBY, PWM, PS1, PS2) from the performance control CPU 63 of the composite chip 50 (see FIG. 7(a)).

[0057] The power supply control circuit SPY then supplies a DC voltage of 5V as the power supply voltage for the main LCD display unit MONI at the optimal timing (see Figures 6(c) and 6(g)). The power supply control circuit SPY also controls the supply of a DC voltage of 12V as the power supply voltage for the backlight unit BL, and controls the BL_EN terminal and PWM terminal of the LED backlight unit BL to the appropriate H / L levels to achieve optimal lighting operation.

[0058] 6(a) is a circuit diagram showing the circuit configuration of the power supply control circuit SPY and its relationship with the backlight unit BL and the liquid crystal display unit MONI. As shown in the figure, this power supply control circuit SPY is mainly composed of a first switch circuit having a transistor Tr1 and a MOS transistor Q1, a second switch circuit having a transistor Tr2 and a MOS transistor Q2, a third switch circuit having a transistor Tr3 and a MOS transistor Q3, a fourth switch circuit having a transistor Tr4 and a MOS transistor Q4, and a buffer circuit SBUF that receives various control signals.

[0059] The buffer circuit SBUF is a high-speed Schmitt buffer (for example, TC74VHC9125) that uses the 3.3V DC voltage supplied from the performance interface board 22 as its power supply voltage, and operates with a non-inverted input / output relationship. That is, the performance control CPU 63 of the composite chip 50 outputs power supply control signals (STBY, PWM, PS1, PS2) with a theoretical H / L width of 3.3V based on the power supply voltage of 3.3V, and the buffer circuit SBUF that receives these outputs control signals (STBY, PWM, PS1, PS2) of the same logic (see Figure 7(a)).

[0060] As shown in Figure 6(a), the four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are all connected to ground via pull-down resistors Rpd, and are configured so that when the control signals are in a HiZ (high impedance) state, such as when the connector is disconnected or when the power is turned on, all control signals are at L level.

[0061] Next, in the first to fourth switch circuits, the transistors Tr1 to Tr4 are all NPN bipolar transistors that are driven to perform switching operations. That is, when the corresponding control signal PS1 / STBY / PWM / PS2 is at H level, each transistor Tr1 / Tr2 / Tr3 / Tr4 operates ON based on the voltage division ratio of the bias resistor, while when the control signal PS1 / STBY / PWM / PS2 is at L level, no current flows through the bias resistor and the transistor Tr1 / Tr2 / Tr3 / Tr4 operates OFF.

[0062] When transistors Tr1 and Tr4 are OFF, the collector outputs of each transistor Tr1 and Tr4 are both higher than 3.3V (12V / 5V). When MOS transistor Q1 is ON and transistors Tr2 and Tr3 are OFF, the collector outputs of each transistor Tr2 and Tr3 are approximately 12V. In this sense, each transistor Tr1 to Tr4, together with the bias resistor, constitutes a level shift circuit that increases the logic H level of the power supply control signals (STBY, PWM, PS1, PS2).

[0063] The bias resistors for the transistors Tr1 to Tr4 are R11+R12, R21+R22, R31+R32, and R41+R42, respectively, and voltages determined by the voltage division ratios of the bias resistors are supplied to the base terminals of the transistors Tr1 to Tr4.

[0064] In this embodiment, the level shift circuits (Tr1 to Tr4) described above are provided, which makes it possible to increase the luminance of the backlight while significantly reducing the power consumption of the performance control unit 23. That is, while the power supply voltage (12V) of the backlight unit BL is set to the highest possible level, the logic H level of the power supply control signals (STBY, PWM, PS1, PS2) can be set to an arbitrary low level (3.3V).

[0065] On the other hand, the MOS transistors Q1 to Q4 are all Pch type, and perform switching operations according to the ON / OFF states of the transistors Tr1 to Tr4, and when in ON operation, the source terminal S and the drain terminal D are substantially in a conductive state.

[0066] Specifically, first, the MOS transistor Q1 receives a DC voltage of 12V at its source terminal S supplied by the performance interface board 22, and when the transistor Tr1 turns ON based on the H-level control signal PS1, the MOS transistor Q1 also turns ON based on the voltage across the bias resistor Rb1 which transitions to a conductive state in response, and outputs a DC voltage of 12V to the drain terminal D.

[0067] This 12V DC voltage is supplied to the backlight section BL via an RC filter circuit and a Zener diode. The RC filter circuit is composed of a 3.3kΩ resistor and a 47μF conductive polymer capacitor (a hybrid capacitor that uses an electrolyte that combines a conductive polymer and an electrolyte instead of the electrolyte found in an aluminum electrolytic capacitor).

[0068] This hybrid capacitor is a cylindrical SMD (Surface Mount Device) with a rated voltage of 25V and a diameter of 6.3mm and a height of 5.8mm. When powered by 5V, the capacitance is maintained at less than -10% of the nominal value (47μF). The nominal equivalent series resistance (ESR) is 50mΩ.

[0069] In a typical circuit configuration, a 47 μF electrolytic capacitor is connected in parallel with a ceramic capacitor (0.1 μF) such as an MLCC (Multilayer Ceramic Capacitor), but in this embodiment, a single hybrid capacitor achieves the desired smoothing and decoupling operations, without consuming space for other circuit elements.

[0070] Incidentally, no other smoothing capacitors or decoupling capacitors are placed within a radius of at least 20 mm from the conductive polymer capacitor. Furthermore, in this embodiment, the decoupling capacitor is surface mounted, and unlike normal electrolytic capacitors, the through-hole mounting method is not used, which has the advantage of reducing the placement space.

[0071] In addition, the top surface of the surface-mounted cylinder is marked with the number "47" indicating the capacitance and the rank symbol "E" indicating the rated voltage of 25V, and the direction of the negative polarity is identified with a black symbol, making it easy to check the components on the board by visual inspection.

[0072] In this embodiment, the MOS transistor Q1 is specifically designed to have an ON resistance between the source S and drain D of 25 mΩ or more and 35 mΩ or less. Therefore, even if a drive current (drain current ID) of 2.5 A flows steadily, the voltage drop in the MOS transistor Q1 is 0.1 V or less, and the power loss is suppressed to approximately 0.22 W (= 2.5 * 2.5 * 35 / 1000). The ON resistance is measured under pulse drive conditions of VGS = -10 V and ID = -4.5 A.

[0073] Furthermore, transistors Q2 and Q3 each receive the voltage at drain terminal D of transistor Q1 at their source terminal S. Therefore, when MOS transistor Q1 is in the ON state and transistors Tr2 and Tr3 are turned ON based on the H-level control signal STBY / PWM, MOS transistors Q2 and Q3 are also turned ON based on the voltage across bias resistors Rb2 and Rb3, which transition to a conducting state in response. As a result, a DC voltage of 12 V is output to drain terminal D of MOS transistors Q2 and Q3, respectively, via transistor Q1, which is in the ON state.

[0074] This DC voltage of 12V is output as a control signal STBY from the drain terminal D of MOS transistor Q2, and is also output as a control signal PWM from the drain terminal D of MOS transistor Q3. The control signal STBY is supplied to the BL_EN terminal (backlight enable) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd, and the control signal PWM is supplied to the PWM terminal (pulse width modulation) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd.

[0075] In this embodiment, by setting the pull-down resistors Rpd to approximately 33 kΩ, the current flowing through the pull-down resistors Rpd due to a DC voltage of 12 V (STBY / PWM) is suppressed to approximately 0.36 mA. This eliminates the need to select expensive elements for the MOS transistors Q2 and Q3. In this embodiment, elements with an ON resistance between the source S and drain D of 2.5 Ω or more and 3.8 Ω or less are used. Note that the ON resistance was measured under pulse drive conditions of VGS = -4.5 V and ID = -100 mA.

[0076] Next, the backlight unit BL will be described. The backlight unit BL is configured to have N × M light emitting diodes (LEDs) aligned vertically and horizontally, and a driver DVL that outputs negative logic drive pulses to synchronously light up the N × M light emitting diodes. This driver DVL is configured to have a BL_EN terminal that specifies whether or not internal operation is enabled, a PWM terminal that specifies the duty ratio of the negative logic drive pulses using positive logic in the range of 10% to 100%, and output terminals LED1 to LEDn that output drive pulses.

[0077] As explained above, the power supply control circuit SPY supplies the control signal STBY to the BL_EN terminal, and the control signal PWM to the PWM terminal. When the control signal STBY is at H level (12V), the internal circuit of the driver DVL operates, enabling drive pulses to be output from the output terminals LED1 to LEDn. These drive pulses are negative logic pulses that are the logical inversion of the control signal PWM.

[0078] As described above, the drive pulse in this embodiment is a negative logic pulse obtained by logically inverting the control signal PWM supplied to the PWM terminal, so the closer the duty ratio of the control signal PWM is to 100%, the longer the L level period of the output terminals LED1 to LEDn becomes, and the higher the average current flowing through the light emitting diodes becomes, resulting in brighter backlight light.On the other hand, the closer the duty ratio is to 10%, the lower the average current through the light emitting diodes becomes, resulting in dimmer backlight light.

[0079] Therefore, the light emission intensity of the backlight can be changed by appropriately changing the duty ratio of the control signal (control pulse) PWM. For example, the backlight can be dimmed in a demo mode when no player is present. However, in this embodiment, to avoid the complexity of such light emission control, the duty ratio of the control signal is maintained at 100%, and the control signal PWM does not change to a pulse shape, but is steadily maintained at an H level (12V) in the operating state. Therefore, the output terminals LED1 to LEDn of the driver DVL steadily maintain an L level when the backlight unit BL is operating.

[0080] The BL_EN terminal and the PWM terminal are both connected to ground via a pull-down resistor Rpd. Therefore, when the MOS transistor Q2 is in the OFF state and the control signal STBY is in the HiZ state, the driver DVL is in the non-operating state, and the output terminals LED1 to LEDn are in the HiZ state, so that all the light-emitting diodes are turned off.

[0081] Furthermore, when the MOS transistor Q3 is OFF and the control signal PWM is in the HiZ state, even if the control signal STBY is at H level, the duty ratio is maintained at 0%, so that the output terminals LED1 to LEDn maintain H level (12V) and all light-emitting diodes are turned off. Therefore, when the power is turned on and no significant image data is being transferred, or when the power supply control circuit SPY is operating abnormally, the backlight is turned off, thereby preventing unnatural image display. The pull-down resistors Rpd connected between the four input terminals of the buffer circuit SBUF and ground are also intended for the same purpose.

[0082] Next, we will explain the relationship between the fourth switch circuit, which has transistor Tr4 and MOS transistor Q4, and the main LCD display unit MONI. As explained above, transistor Tr4 of the fourth switch circuit is turned ON / OFF based on the H / L level of the control signal PS2.

[0083] On the other hand, the MOS transistor Q4 receives a DC voltage of 5V at its source terminal S supplied by the performance interface board 22, and when the transistor Tr1 turns ON, the MOS transistor Q4 also turns ON based on the voltage across the bias resistor Rb4, which in response transitions to a conductive state, and outputs a DC voltage of 5V to the drain terminal D.

[0084] This DC voltage of 5V is supplied to the liquid crystal display unit MONI shown in Figure 5 via an RC filter circuit and a Zener diode, and is used as the power supply voltage for the liquid crystal display unit MONI. In this embodiment, a device with an ON resistance between source S and drain D of 48 mΩ or more and 65 mΩ or less is used as MOS transistor Q4. Therefore, even if a drive current (drain current ID) of 1.5 A is steadily applied, for example, the voltage drop across MOS transistor Q1 is 0.1 V or less, and power loss is suppressed to approximately 0.15 W (= 1.5 * 1.5 * 65 / 1000). Note that the ON resistance was measured under pulse drive conditions of VGS = -4.5 and ID = -2.5 A.

[0085] Next, the circuit operation of the power supply control circuit SPY will be described with reference to Figures 6(b) to 6(j). After power is turned on, the composite chip 50 starts its control operation after an assertion period in which the system reset signal SYS maintains the L level (timing T1 in Figure 6(d)). Then, 1000 mS after timing T1, the performance control CPU 63 of the composite chip 50 transitions the control signals PS1 and PS2 to the H level (timing T2).

[0086] Then, based on the H-level control signal PS1, the MOS transistor Q1 turns ON, and the supply of 12V DC to the backlight unit BL begins. Based on the H-level control signal PS2, the MOS transistor Q4 turns ON, and the supply of 5V DC to the liquid crystal display unit MONI begins. However, at this timing T2, the control signals STBY and PWM remain at L level, so the backlight unit BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no risk of an unnatural image being displayed.

[0087] Next, after about 5 mS has elapsed from timing T2, the performance control CPU 63 starts the initialization operation of the display clock and display circuit 74. The details of this control will be described later, but these operations are one of the initialization operations before the operation of the VDP circuit 52 starts, and at this stage, no significant image signal is output to the display device DS1.

[0088] Thereafter, the performance control CPU 63 initializes the display register appropriately, and then starts the operation of the display circuit 74 and the LVDS circuit 80 (timing T4). Therefore, after timing T4, the LVDS signal as a significant image signal is repeatedly output to the display device DS1 every 1 / 60 seconds (see FIG. 6(f)).

[0089] However, at timing T4, the control signal PWM remains at L level, so the backlight does not emit light. That is, at timing T3, the performance control CPU 63 transitions the control signal STBY to H level to control the driver DVL to an operable state, but at timing T4, the control signal PWM is still at L and the duty ratio of the drive pulse is 0%, so the backlight unit BL remains off.

[0090] Meanwhile, the performance control CPU 63 starts the operation of the display circuit 74 and the LVDS circuit 80 (SS4 in FIG. 21), and at time T5, more than 300 mS later, transitions the control signal PWM to the H level (SS6 in FIG. 21), transitioning the backlight unit BL to a light-emitting state with a duty ratio of 100%. If the operation at time T5 is executed, for example, by timer interrupt processing, at time T5, the liquid crystal display unit MONI has already received the LVDS signal as a significant image signal repeatedly every 1 / 60 seconds, and an image based on that image signal will be displayed. In other words, since the steady-state processing (ST4 to ST14 in FIG. 22) is started immediately after the processing of step SS6 in FIG. 21, the initial screen based on the display list DL is displayed at time T5.

[0091] However, as shown in Figure 21, when the performance control CPU 63 executes a 300 ms standby process (step SS5 in Figure 21), the display list DL has not yet been issued at timing T5, so the display content will be a screen based on the VRAM (frame buffer FBa) after power-on. Therefore, taking this into consideration, it is preferable to clear the VRAM (especially the frame buffers FBa and FBb) to zero after power-on. However, even if the VRAM is not cleared to zero, there is no problem because the random image is displayed only for a moment at most when the gaming hall opens for business. In other words, immediately after the processing of step SS6 in Figure 21, the regular process (ST4 to ST14 in Figure 22) is started, and the initial screen based on the display list DL is displayed.

[0092] In this embodiment, the program is designed so that the program execution time from timing T2 to timing T4 is within 20 ms. This is because it is recommended that the display device DS1 used in this embodiment should start transmitting an image signal (LVDS signal) within a predetermined time τ (for example, 20 ms) after power is applied to the liquid crystal display unit MONI.

[0093] In this embodiment, the timing of power supply to the liquid crystal display unit MONI is delayed by about one second using the control signal PS2, based on the above requirement. If power supply to the liquid crystal display unit MONI were to start simultaneously with power-on, it would be extremely impossible to start transmitting an LVDS signal within the predetermined time τ (e.g., 20 mS) thereafter due to the assertion period and program execution time (processing time for SP1 to SP10) (see timing T4).

[0094] The main display device DS1 has been explained in detail above, but the operation of the sub-display device DS2 is essentially the same, and by performing the operation shown in Figure 6(b), the sub-LCD display unit MONI and backlight unit BL operate in a consistent manner to prevent inappropriate display.

[0095] The sub-display device DS2 operates in the same manner as shown in Fig. 42, based on the horizontal synchronizing signal HS and vertical synchronizing signal VS received from the VDP circuit 52. However, it is also preferable to configure the sub-control device DS2 so that it operates based on the data valid signal ENAB, rather than based on the horizontal synchronizing signal HS or vertical synchronizing signal VS. The data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, rather than in the form of a discrete DE signal (see the lower right of Fig. 14(a)).

[0096] Next, returning to Fig. 3(a), the overall circuit configuration of the pachinko machine GM will be explained. As shown in Fig. 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) together with AC 24V, a main control board 21 that is responsible for central and overall game control operations, a performance interface board 22 equipped with circuit elements SND for sound performance, a performance control board 23 that executes lamp performance, sound performance, and image performance in an integrated manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the performance control board 23 and the display devices DS1 and DS2, a payout control board 25 that controls the payout motor M to pay out game balls based on control commands CMD' received from the main control board 21, and a launch control board 26 that launches game balls in response to player operations.

[0097] The performance interface board 22, performance control board 23, and liquid crystal interface board 24 are directly connected via male and female connectors without using wiring cables. This allows the storage space for the entire board to be minimized even if the circuit configuration of each electronic circuit is made complex and advanced, and noise resistance can be improved by shortening the connection lines.

[0098] As shown in the figure, the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

[0099] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 incorporating computer circuits such as a VDP circuit (Video Display Processor) 52 and an embedded CPU circuit 51. Therefore, in this specification, the main control unit 21, the performance control unit 23, and the payout control unit 25 are sometimes referred to functionally as the control boards 21, 25, and 23, the circuits mounted on the performance interface board 22, and the LCD interface board 24, and the operations realized by these circuits. The performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0100] This pachinko machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Figure 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 outside of that, and is installed in a fixed position in the game hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All except the frame side member 1 is the board side member GM2.

[0101] As shown in the dashed-line frame in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are each fixed in appropriate locations on the inner frame 3. Meanwhile, a main control board 21 and a performance control board 23 are fixed to the back of the gaming board 5, along with display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3, which are centrally located in one place.

[0102] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0103] The DC 35V is used to drive the ball-feeding solenoid and launch solenoid involved in the launching of gaming balls, and to drive the electromagnetic solenoids that open and close the electric tulip (variable winning device) and the large winning slot 16. The DC 12V is used to drive the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier. Meanwhile, the DC 5V is used as the power supply voltage for the one-chip microcomputers on the payout control board 25 and main control board 21, and for the logic elements mounted on each control board. The DC 5V is stepped down by the DC / DC converter on the performance interface board 22, and the stepped down voltages at various levels are then used as the power supply voltage for various computer circuits (such as the composite chip 50 and the audio processor 27).

[0104] The backup power supply BAK is a DC 5V power supply for maintaining the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0105] On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with an electric double layer capacitor that can retain the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0106] In this embodiment, unlike conventional equipment configurations, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC 24V voltage, is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies the AC 24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that is powered by the DC voltage of 5V received from the power supply board 20 and turns ON based on the light emitted by the photodiode D, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON state of the phototransistor TR. The photodiode D and phototransistor TR together form a photocoupler PH.

[0107] In the above configuration, after power is turned on, the photocoupler PH quickly switches to the ON state, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power subsequently drops abnormally for some reason (normally due to a power outage), the photocoupler PH switches to the OFF state, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer on the payout control board 25 and also to the one-chip microcomputer on the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal-level power supply abnormality signal ABN executes a backup process to store necessary information in its own internal RAM. As explained above, the information in the internal RAM is maintained by the backup power supply BAK, allowing game operation to resume as it was before the power was turned off after power is turned on.

[0108] As shown in Figure 3(a), the performance interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit 52 and an embedded CPU circuit 51. Hereinafter, the embedded CPU circuit may be abbreviated as the CPU circuit.

[0109] The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect a rise in power supply voltage when power is turned on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates the reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. The reset signal RT3 then resets the power supply to only the audio memory 28 and is transmitted directly to the performance control board 23.

[0110] As shown in Figure 7(a), the reset signal RT3 transmitted to the performance control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and is output as a system reset signal SYS, which resets the power supply to the CPU circuit 51 and VDP circuit 52 (see Figures 7(a) and 7(d)).

[0111] After power is turned on, the reset signal RT3 generated by the reset circuit RST3 remains at L level for a predetermined time as a power reset signal, and then rises to H level. However, if thereafter either one or more of the DC voltage 12V or DC voltage 5V drops (usually when the power is turned off), the system reset signal SYS also drops to L level in response to the drop in the level of the reset signal RT3, and the CPU circuit 51 and VDP circuit 52 of the performance control board 23 enter an operation stop state.

[0112] This system reset signal SYS also changes based on the output of the WDT circuit 58 (which is normally at H level). Therefore, when the reset signal RT3 is at H level and the output of the WDT circuit 58 drops to L level due to a program runaway or the like, the system reset signal SYS also changes to L level, causing an abnormal reset of the CPU circuit 51 and the VDP circuit 52 (see FIG. 7(d)).

[0113] On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3 V generated by dropping the 5 V distributed from the power supply board 20. This reset signal RT4 resets the power supply of the audio processor 27 as a power supply reset signal when the power is turned on.

[0114] As shown in the figure, the reset circuit RST4 is also supplied with the system reset signal SYS returned from the performance control board 23, so when the CPU circuit 51 or VDP circuit 52 is abnormally reset, the sound processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the sound performance returns to its initial state along with the image and lamp performance, and there is no risk of unnatural sound performance continuing.

[0115] Next, the dispensing control board 25, which is the frame side member GM1, and the main control unit 21, which is the board side member GM2, are each equipped with reset circuits RST1 and RST2, and are configured so that when the power is turned on, a power reset signal is generated and each computer circuit is power reset.

[0116] In this way, in this embodiment, the reset circuits RST1 to RST4 are arranged in the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, and the system reset signal SYS is not transmitted between the circuit boards. In other words, since there is no wiring cable for transmitting the system reset signal SYS, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0117] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the dispensing control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, each CPU will be forcibly reset.

[0118] Furthermore, the main control unit 21 is provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcomputer of each control unit 21, 25.

[0119] Furthermore, as explained earlier, the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25 receive a power supply abnormality signal ABN from the power supply monitor MNT located in the dispensing control unit 25, and initiate the necessary termination processing prior to a power outage or closing of business.

[0120] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball count signal indicating the payout operation of game balls, a status signal CON relating to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0121] The main control unit 21 also receives switch signals from the detection switches built into each winning slot 16-18 on the gaming board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Furthermore, each switch signal indicating the winning status of the symbol start slot 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and the power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0122] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connector C2 (see Figures 3(a) and 7(a)). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as a drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the game frame and is used as a drive voltage for solenoids that move movable objects back and forth.

[0123] Meanwhile, the DC voltage of 5V is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to two DC / DC converters DC1 and DC2 to generate 3.3V and 1.0V (see FIG. 7(a)). The generated DC voltages of 3.3V and 1.0V are supplied to the audio processor 27 as power supply voltages for I / O (input / output) and the chip core, respectively. The DC voltage of 3.3V also serves as the base voltage for the power reset signal RT4 generated by the reset circuit RST4.

[0124] The 5V DC voltage distributed to the performance interface board 22 is distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC1. The 3.3V DC voltage distributed to the performance control board 23 is then supplied to the composite chip 50, PROM 53, and CGROM 55 as a power supply voltage.

[0125] As shown in Figure 7(a), two DC / DC converters DC3 and DC4 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as a power supply voltage.

[0126] As shown in Fig. 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Fig. 7(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0127] 7(a), the input buffer 44 of the performance interface board 22 receives switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0128] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, in FIG. 7(a), the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives outputs SN0 to SNn from origin sensors that grasp the current positions of the movable performance elements (the rotational positions of the performance motors M1 to Mn), and transmits these to the CPU circuit 51 of the performance control board 23.

[0129] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers the serial signal received from the performance control board 23 to each driver IC. Specifically, the serial signal is a lamp (motor) drive signal SDATA and a clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronization system, and lamp performances using a large number of LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn are executed.

[0130] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 in synchronization with the clock signal CK0 via the frame relay boards 35 and 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting status of all the lamps at once.

[0131] The above points also apply to the lamp driving board 30, where the driver IC of the lamp driving board 30 receives the lamp driving signal SDATA1 for the lamp group CH1 in synchronization with the clock signal CK1, and simultaneously updates the lighting state of the lamp group CH1 when the operation control signal ENABLE1 changes to the active level.

[0132] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted in clock synchronization to drive the lamp group CH2, and also receives a motor drive signal transmitted in clock synchronization to drive the performance motor group M1 to Mn, which is made up of multiple stepping motors. The lamp drive signal and motor drive signal are a series of serial signals SDATA2 that are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives these signals updates the drive states of the lamp group CH2 and the motor group M1 to Mn when the operation control signal ENABLE2 changes to the active level.

[0133] Next, the audio circuit SND will be explained. As shown in Fig. 7(a), the performance interface board 22 is equipped with an audio processor (audio synthesis circuit) 27 that reproduces audio signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the performance control board 23, an audio memory 28 that stores compressed audio data, which is the original data of the audio signals to be reproduced, and a digital amplifier 29 that receives the audio signals output from the audio processor 27.

[0134] The sound processor 27 is configured with a built-in WDT circuit that automatically resets the setting values ​​of the internal circuit to default values ​​(initial values) when the internal circuit operates abnormally, and a sound control register SRG. The sound processor 27 accesses the sound memory 28 based on the operating parameters (setting values ​​by sound commands) received from the performance control CPU 63 in the sound control register SRG, and reproduces and outputs the required sound signals.

[0135] As shown in FIG. 7(a), the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. 26 ×16) of data can be stored.

[0136] The sound control register SRG is divided into register banks 1 to 6, each identified by a register number from 00H to FFH. Therefore, a predetermined setting operation is realized by the performance control CPU 63 specifying the register bank and then writing a 1-byte operation parameter to the sound control register SRG of the predetermined register number (1 byte long).

[0137] In this embodiment, the register numbers (00H to FFH) of the audio control register SRG correspond to the address space CS3 of the performance control CPU 63. For example, when setting an operating parameter YYH in the audio control register SRG with register number XXH, the performance control CPU 63 writes XXH to address zero of the address space CS3, and then writes YYH to address 1. In other words, the performance control CPU 63 writes XXH and YYH to its data bus in that order. In this specification, the subscript H and the prefix 0X / 0x indicate that the numerical value is expressed in hexadecimal.

[0138] In this specification, the address space CS0 to CS7 refers to external memory (excluding built-in memory) for the CPU circuit 51, which can specify the memory type (including whether it is volatile or not) and the data bus width (8 / 16 / 32 bits). This address space CS0 to CS7 is selected by different chip select signals CS0 to CS7, and is configured to be configurable so that the READ / WRITE control signal that functions during READ / WRITE access can be optimized according to the memory type. This setting operation is executed by the bus state controller 66.

[0139] 7(e) illustrates the setting operation of the sound register SRG by the performance control CPU 63, showing the contents of the 2-bit address bus A1-A0 and the 1-byte data bus D7-D0. In this embodiment, the chip select signal CS3 is set at power-on so that it automatically becomes active when the address space CS3 is accessed; this will be described later with reference to FIGS. 9 and 16.

[0140] In any case, in this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by a 13-bit phrase number NUM (000H to 1FFFH), and a maximum of 8192 types (=2 13 ), each stored in correspondence with a phrase number NUM. The phrase number NUM is specified by the setting value (operation parameter) of the voice command transmitted from the performance control CPU 63 to the voice control register SRG of the voice processor 27.

[0141] As described above, the audio memory 28 having the above configuration is powered on and reset by the reset signal RT3, and the audio processor 27 is powered on and reset by the reset signal RT4. As shown in Figure 7(c), the reset signal RT4 rises to H level after a predetermined assertion period ASRT (L level section) after power-on. In this embodiment, the internal circuitry of the audio processor 27 then automatically functions and initialization sequence processing is executed. Note that this initialization sequence processing is an internal operation executed in a predetermined procedure, and the performance control CPU 63 cannot access the audio register SRG while the initialization sequence processing is in operation.

[0142] When the internal initialization sequence process is completed, the interrupt signal IRQ_SND for the CPU circuit 51 changes to L level, and the CPU circuit 51 (performance control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND.Then, the interrupt signal IRQ_SND is returned to H level based on a predetermined command, the details of which will be described later with reference to Figure 18(c).

[0143] As shown in Figure 7(a), the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (real time clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 can arbitrarily access the internal registers (which have 4-bit address values).

[0144] Furthermore, the effect data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus and the lower 16 bits of the data bus of the CPU circuit 51. When the chip is selected by the chip select signal CS4, the game performance information and other information stored in the SRAM (effect data memory) 39 can be appropriately read / written by the CPU circuit 51. In the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are assigned to the clock circuit 38 and are therefore not used by the SRAM 39.

[0145] The clock circuit 38 and the effect data memory 39 are powered by a secondary battery (not shown), which is charged appropriately by the power supply voltage from the power supply board 20 during game operation. Therefore, even after power is cut off, the clock circuit 38 continues to measure time, and the game performance information stored in the effect data memory 39 is permanently stored (non-volatile). The clock circuit (RTC) 38 is configured to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, the alarm interrupt is used to update the daily game performance information at the end of business each day.

[0146] As shown on the right side of Figure 7(a), the performance control board 23 is equipped with a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 that stores the control program for the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 that can access large amounts of data at high speed, and a CGROM 55 that stores large amounts of CG data required for performance control.

[0147] 10, in this embodiment, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the DRAM (Dynamic Random Access Memory) 54 configured as a DDR (Double-Data-Rate 3) is located in the address space CS5 selected by the chip select signal CS5.

[0148] 8(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a VDP circuit 52 that generates image data based on the issued display list DL and drives the display devices DS1 and DS2. The CPU circuit 51 and the VDP circuit 52 are connected via a CPUIF circuit 56 that relays data sent and received between them.

[0149] The VDP circuit 52 has a built-in audio circuit SND that performs the same function as the audio processor 27, but the first embodiment described below does not utilize the audio circuit SND. However, if the audio circuit SND built into the VDP circuit 52 is utilized, as in the last embodiment described below, the audio memory 28 and audio processor 27 will not be required.

[0150] First, the CPU circuit 51 receives the oscillation output (for example, 100 / 3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies the frequency (for example, by 8) to generate a CPU operating clock of about 266.7 MHz (see FIG. 14(b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby providing EMI (Electromagnetic Interference) countermeasures to prevent radio interference / electromagnetic disturbance.

[0151] In this embodiment, the CPU operating clock can be generated based on the output of oscillator OSC2 (described later) instead of oscillator OSC1, making oscillator OSC1 unnecessary. However, in a configuration using a single oscillator, the frequency multiplication ratio of the PLL circuit is a fixed value (e.g., 5) that is the same as that of the system clock (described below), so the frequency of the CPU operating clock is 200 MHz (= 40 MHz × 5), the same as that of the system clock of VDP circuit 52.

[0152] While this configuration has the advantage of sharing the operating cycles of the built-in CPU circuit 51 and VDP circuit 52, it contradicts the desire to maximize the speed of CPU operation. In other words, since VDP operation cannot be accelerated beyond a certain point, it is not possible to reliably meet the demand for faster CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operating cycles of the VDP circuit 52 and the CPU circuit 51. Furthermore, providing a separate oscillator OSC1 can also improve the EMI countermeasures described above.

[0153] Taking the above into consideration, the VDP circuit 52 will now be explained. The VDP circuit 52 receives the oscillation output (40 MHz) of oscillator OSC2, which is separate from oscillator OSC1, at its PLLREF terminal, and after frequency multiplication by a PLL (Phase Locked Loop) circuit, uses the result as the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly determined by the value set at a predetermined setting terminal, and in this embodiment, the setting value at the setting terminal (a 3-bit PLLMD terminal) is a fixed value of 5, so the system clock for the VDP circuit 52 is 200 MHz (= 40 MHz × 5) (see FIG. 14(b)).

[0154] In this embodiment, a dot clock DCK that defines the operation of the display circuits 74A to 74C is A ~DCK C The DDR clock of the external DRAM 54 is also generated based on the oscillation output (40 MHz) of the oscillator OSC2. That is, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

[0155] As will be described later with reference to FIGS. 14 and 15, the display circuits 74A to 74C usually drive display devices with different specifications, so a dot clock DCK that defines the operation of each of the display circuits 74A to 74C is used. A ~DCK CIt is necessary to make the display circuits 74A to 74C correspond to the specifications of the display device to be driven. Based on this requirement, in this embodiment, the display circuits 74A to 74C receive one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC, and convert it into the dot clock DCK A ~DCK C It is configured so that it can also be configured as follows.

[0156] When this configuration is used, it is not necessary to design the multiplication and division ratios described later, and it is not necessary to set the VDP register RGij. A ~DCK C That is, the dot clock frequency F of the main display device DS1 can be easily optimized. DOT1 The oscillation frequency F DOT1 A dedicated oscillator circuit DCLKA is provided, and the dot clock frequency F of the sub-display device DS2 is DOT2 The oscillation frequency F DOT2 It is also possible to provide a dedicated oscillator circuit DCLKB.

[0157] However, when such a configuration is adopted, dedicated oscillator circuits are required corresponding to the number of display devices, which makes the device configuration complicated. Therefore, in this embodiment, in order to simplify the device configuration, the dot clock DCK of the display circuits 74A / 74B is generated based on the oscillation output (40 MHz) of the oscillator OSC2. A / DCK B Specifically, as shown in FIG. 14(b), for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×108) and division process (1 / 40) to generate a dot clock DCK with a frequency of 108 MHz. A is generated.

[0158] Similarly, for the display circuit 74B that drives the sub-display device DS2, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×108) and a frequency division process (1 / 160) to obtain a frequency F dot = 27MHz dot clock DCK BDesigning these multiplication and division ratios is quite complicated, and it would be easier to provide a dedicated oscillator circuit, but in this embodiment, emphasis is placed on simplifying the device configuration, and no dedicated oscillator circuit is provided.

[0159] In any case, the dot clock DCK A ~DCK C is set individually for each of the display circuits 74A to 74C, but these dot clocks DCK A ~DCK C In the following description, the dot clock DCK is sometimes referred to as the "display clock DCK." A and DCK B For convenience, this is sometimes abbreviated as "dot clock DCK."

[0160] In this embodiment, since the configuration of low-speed LVDS output is not adopted, the LVDS clock CLK of the LVDS signal output via the display circuit 74A is also the dot clock DCK A The frequency of the LVDS clock CLK is 108 MHz, generated through the same generation process as in Example 1. However, since a dual link transmission line is used in this example, the actual frequency of the LVDS clock CLK is 54 MHz, as explained in relation to Figure 4. If a single link transmission line is used, the frequency of the LVDS clock CLK is 108 MHz.

[0161] As described above, in this embodiment, the oscillation output (40 MHz) of oscillator OSC2 is used as the reference clock for the system clock, dot clock DCK, and DDR clock. Considering this importance, oscillator OSC2 is configured to operate at the same power supply voltage of 3.3 V as VDP circuit 52, and to oscillate and output the reference clock when output enable terminal OE is at H level (=3.3 V). If the power supply voltage of 3.3 V were to drop below a predetermined level, normal operation would be impossible, and a non-maskable interrupt (NMI) would be generated.

[0162] The composite chip 50 is also provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setting program) executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL = H) or in some other memory (HBTSL = L). As shown in the figure, in this embodiment, HBTSL is set to the L level, and address zero of the address space CS0 of the performance control CPU 63 is assigned to a location other than CGROM; specifically, the address space CS0 is assigned to the control memory 53.

[0163] On the other hand, when the HBTSL terminal is set to the H level (see dashed line), address zero of the address space CS0 of the performance control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64 / 32 / 16 bits) of the CGROM 55 are determined based on the input values ​​to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal, respectively. These points will be discussed further below with reference to Figure 39.

[0164] Next, we will explain the CPUIF circuit 56, which relays data transmitted and received between the CPU circuit 51 and the VDP circuit 52. As shown in Figure 8(a), the CPUIF circuit 56 is connected to a control memory (PROM) 53 that stores control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 57 having a storage capacity of about 2 MB, each of which is configured to be accessible from the CPU circuit 51. As explained above, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in the address space CS6 selected by the chip select signal CS6.

[0165] A DL buffer BUF is allocated in this work memory (RAM) 57 for temporarily storing a display list DL containing a series of instruction commands specifying each frame of the display devices DS1, DS2. In this embodiment, the series of instruction commands include texture load commands such as a TXLOAD command for reading and decoding (expanding) image material (texture) from CGROM 55, texture setting commands such as a SETINDEX command having the function of specifying in advance the VRAM area (index space) to decode (expand), primitive drawing commands such as a SPRITE command for arranging the image material after decoding (expanding) at a predetermined position in the virtual drawing space, environment setting commands such as a SETDAVR command and a SETDAVF command for specifying the drawing area to actually draw on the display device out of the images drawn in the virtual drawing space by the drawing commands, and an index table control command (WRIDXTBL) related to the index table IDXTBL that manages the index space.

[0166] Figure 12(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the actual drawing area in frame buffers FBa and FBb that temporarily store image data to be output to display devices DS1 and DS2.

[0167] Next, the CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcomputer, and is configured with a performance control CPU 63 that comprehensively controls image performance based on a control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU if the program goes out of control, an internal RAM 59 with a storage capacity of approximately 16 kbytes and used as a CPU work area, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without going through the CPU 63, a serial input / output port (SIO) 61 with multiple input ports Si and output ports So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output ports Po, and an operation control register REG in which setting values ​​are set to control the operation of each of the above components. However, in this embodiment, which is provided with an external WDT circuit 58, the watchdog timer (WDT) built into the CPU circuit 51 is not utilized.

[0168] For convenience, the term "input / output port" is used in this specification, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p and the input / output circuit 64s described below.

[0169] The parallel input / output port 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 63 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p.

[0170] Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. The strobe signal STB is also supplied to the interrupt terminal of the performance control CPU 63 via the input / output circuit 64p, thereby activating the reception interrupt process. Therefore, the performance control CPU 63, which has grasped the control command CMD based on the reception interrupt process, will perform a performance lottery or the like to uniformly control the sound performance, lamp performance, motor performance, and image performance corresponding to this control command CMD.

[0171] Although not particularly limited, in this embodiment, an SMC circuit (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp and motor effects. The SMC circuit 78 is a composite controller incorporating an LED controller and a motor controller, and is configured to output serial signals in a clock-synchronized manner. The motor controller is configured to output latch pulses at any timing based on the set value in a predetermined control register 70, and is also configured to input serial signals in a clock-synchronized manner.

[0172] Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC circuit 78 in synchronization with the clock signal, while a latch pulse is output as the operation control signal ENABLE at an appropriate timing. Also, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are configured to be input serially in clock synchronization.

[0173] 7(a), the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 are transmitted to the predetermined drive boards 30, 31, and 37 via the output buffers 41 to 43. In addition, the origin sensor signals SN0 to SNn are serially input to the SMC circuit 78 from the motor lamp drive board 31 via the input / output buffer 43.

[0174] However, in this embodiment, it is not essential to use the SMC circuit 78. That is, since the CPU circuit 51 has a built-in general-purpose serial input / output port SIO61, it is also possible to use these to execute lamp effects and motor effects.

[0175] 8(a), clock signals CK0-CK2 and drive signals SDATA0-SDATA2 are output via an input / output circuit 64s internally connected to the serial input / output port SIO61, and operation control signals ENABLE0-ENABLE2 are output via an input / output circuit 64p. Note that although the terms input / output port and input / output circuit are used for convenience, it is the output port and output circuit that actually function.

[0176] Here, the serial output port SO is configured to have a 16-stage FIFO register built in (see Figure 50(a)). The DMAC circuit 60 is configured to start up upon receiving an operation start instruction (see Figure 22(b) ST18) from the performance control CPU 63, read the necessary drive data in order from the lamp / motor drive table (see Figure 22(b)), and DMA transfer it to the FIFO register of the serial output port SO. The drive data accumulated in the FIFO register is serially output from the serial output port SO in a clock-synchronized manner. The DMAC circuit has multiple DMA channels (for example, seven), and is configured to DMA transfer lamp drive data using the third DMA channel, which has a lower priority, and DMA transfer motor drive data using the first DMA channel, which has the highest priority.

[0177] The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit register with a register number (address value) starting from 0xFF400000, and is configured to be WRITE / READ accessible from the performance control CPU 63 as appropriate (see FIG. 10). Therefore, due to the influence of noise, etc., there is a possibility that an unreasonable value may be set in the operation control register REG.

[0178] However, for example, the combined chip 50 can be abnormally reset by intentionally executing an infinite loop process to activate the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij in the VDP circuit 52 is also returned to the default value (initial value), thereby resolving the abnormal state.

[0179] FIG. 7(b) illustrates the circuit configuration related to this reset operation and explains the reset mechanism characteristic of this embodiment. In this specification, the VDP register represented as RGij does not refer to the operation control register REG built into the CPU circuit 51, but rather to one of the control registers 70 (see FIG. 10) that control the internal operation of the VDP circuit 52. Also, the system control circuit 520 shown in FIG. 7(b) refers to the internal control circuit of the VDP circuit 52 that functions based on the setting value of the VDP register RGij (one of the control registers 70 in FIG. 10) (see FIG. 7(a)). The VDP register RGij is located in address space CS7, which is selected by the chip select signal CS7, in the address map of the performance control CPU 63.

[0180] 7(b), the composite chip 50 is configured so that the internal circuitry can be reset via three OR gates G2 to G4, which receive the logically inverted system reset signal SYS. However, in this embodiment, as shown by the dashed line, the built-in WDT is not enabled, so the input and output terminals of the OR gate G2 are directly connected.

[0181] In either case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST on the condition that a predetermined keyword string (encrypted string for reset) is received from the parallel input / output port (PIO) 62.

[0182] The internal circuitry of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the circuit other than the display circuit in the VDP circuit 52, and each is configured to receive reset signals from the first to third reset paths from OR gates G2 to G4.

[0183] First, OR gate G2, whose input and output terminals are directly connected, is associated with the first reset path and is configured to reset the entire CPU circuit 51 based on the system reset signal SYS bar. Furthermore, OR gate G3 is associated with the second reset path and is configured to receive the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK and to reset the entire VDP circuit 52 based on OR logic.

[0184] This second reset path is used not only for power reset operation when the power is turned on, but also when the performance control CPU 63 detects a predetermined abnormality and abnormally resets the entire VDP circuit 52 to return it to its initial state. Specifically, if it is determined that a serious abnormality has occurred based on a predetermined status register RGij that indicates the internal operation of the VDP circuit 52, the pattern check circuit CHK generates a reset signal RST, thereby abnormally resetting the entire VDP circuit 52. The display circuit 74 is abnormally reset via the second reset path → third reset path via OR gate G4.

[0185] Meanwhile, the internal circuits built into the VDP circuit 52 are configured so that they can be individually reset when necessary via a fourth reset path. The internal circuits that can be individually reset include the index table IDXTBL, data transfer circuit 72, preloader 73, display circuit 74, drawing circuit 76, SMC circuit 78, and audio circuit SND shown in Fig. 8(a), and the ICM circuit shown in Fig. 13.

[0186] The method for realizing the individual reset operation is as shown at the bottom of Figure 7(b). For example, the display circuit 74 is reset via the fourth reset path 4A → the third reset path by writing the first reset value to a predetermined VDP register RGij (system command register).

[0187] Furthermore, each internal circuit (72, 73, 74, 76, SND, ...) of the VDP circuit 52 is individually reset by (1) writing a setting value that identifies the target circuit to the first VDP register RGij (reset RQ register), and then (2) writing a second reset value to a predetermined VDP register RGij (system command register) (fourth reset path 4B). Note that, although not used in this embodiment, the audio circuit SND can be reset not only by resetting via the fourth reset path 4B, but also by writing a reset value to a predetermined VDP register (circuit setting command register) (fourth reset path 4C).

[0188] Because this embodiment has the above configuration, not only does the entire VDP circuit 52 automatically return to its initial state when power is turned on or a program crash occurs, but each component can also be returned to its initial state as needed to recover from an abnormal situation. For example, when the drawing circuit 76 freezes due to a lack of READ / WRITE access to the internal VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see ST16a in FIG. 22(d)). The same is true for the preloader 73 and the data transfer circuit 72. When a predetermined abnormality occurs, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 29), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in FIG. 24 and FIG. 29).

[0189] Furthermore, when an underrun abnormality occurs continuously in which the generation of display data does not keep up with the display timing every 1 / 60 seconds, the display circuit 74 is individually initialized via a fourth reset path 4A or a fourth reset path 4B (see ST10c in FIG. 22). These individual reset operations will be described in more detail later in relation to the program processing described in FIG. 22 and subsequent figures.

[0190] The above describes the reset mechanism characteristic of this embodiment. When any of the reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the setting value of the VDP register RGij corresponding to that internal circuit returns to the same default value as after power-on.

[0191] Next, we will return to the internal configuration of the CPU circuit 51 and continue explaining its characteristic circuit configuration. Figure 9 is a block diagram showing in some detail the internal configuration of the CPU circuit 51. The CPU circuit 51 is configured to include many characteristic circuits in addition to the internal RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

[0192] First, the CPU circuit 51 has a separate CPU fetch bus for instructions and a separate CPU memory access bus for data, realizing a Harvard architecture. This means that the CPU core (performance control CPU) 63's fetch operation of reading instructions from memory does not conflict with memory access operations, allowing for continuous fetch operations and achieving high-speed processing.

[0193] The CPU core 63 is also configured with a plurality of (e.g., 15) register banks RB0 to RB14, and is configured to be able to select whether to use them. In an operating state in which the use of register bank RBi is permitted, at the start of interrupt processing, the register values ​​(each 32 bits long) of the CPU's built-in registers (e.g., 19 registers) are automatically saved to an empty register bank RBi.

[0194] Furthermore, when a predetermined restore command is executed at the end of interrupt processing, for example, 19 saved data items are automatically restored to the corresponding built-in registers. This eliminates the need to execute the PUSH command 19 times at the start of interrupt processing and the POP command 19 times at the end of interrupt processing, as is the case with conventional configurations, thereby achieving high-speed processing.

[0195] Furthermore, the CPU circuit 51 of the embodiment is provided with an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, thereby realizing Harvard cache operation, and further speeding up program processing by utilizing cached data when accessing the same address. Furthermore, the bus bridge 65, a controller for peripheral bus (1), a controller for peripheral bus (2), and a controller for peripheral bus (3) are provided, thereby appropriately connecting the internal bus with peripheral bus (1), peripheral bus (2), and peripheral bus (3).

[0196] 9, the bus state controller 66 operates based on appropriate settings in the operation control register REG to optimize memory READ and WRITE operations with various memory devices connected to the CPU circuit 51. The memory READ and WRITE operations are executed, for example, at the operation timings shown in Fig. 40, but the operation timings of the address data output from the address bus (28 bits), the READ data read to the READ data bus (32 bits), the WRITE data written to the WRITE data bus (32 bits), and control signals such as chip select signals CS0 to CS7 are appropriately specified in accordance with the characteristics of each memory device based on the settings in the operation control register REG.

[0197] Separate read and write data buses are provided, enabling high-speed operation through the Harvard architecture described above. In this specification, the address bus (28 bits), read data bus (32 bits), and write data bus (32 bits) are sometimes collectively referred to as external buses to distinguish them from the internal buses and peripheral buses (1) to (3) shown in Figure 9.

[0198] 10 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates the address map for the performance control CPU 63 accessed via the bus state controller 66. First, each of the address spaces CS0 to CS7 is specified to have a maximum of 64 MB (=0x4000000H=67108864).

[0199] As explained above, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51, which can specify the memory type (including whether it is volatile or not) and the data bus width (8 / 16 / 32 bits). In this embodiment, as shown in Figures 9(b) and 10, the control memory (PROM) 53 is located in address space CS0, the audio control register SRG of the audio processor 27 is located in address space CS3, the internal register of the clock circuit 38 and the SRAM 39 are located in address space CS4, the external DRAM (DDR) 54 is located in address space CS5, the work memory 57 is located in address space CS6, and the VDP register RGij is located in address space CS7. The address spaces CS1 and CS2 will not be described here.

[0200] 10, the address space CS0 to CS7 is reserved not only for address values ​​0x00000000 to 0x1FFFFFFF (cache-enabled space) but also for address values ​​0x20000000 to 0x3FFFFFFF (cache-disabled space). This allows the use of the cache function to be selected arbitrarily by invalidating the cache based on the internal operation of the CPU circuit 51 when address bit A29=1, and validating the cache when address bit A29=0.

[0201] Therefore, in this embodiment, of the total 32-bit address information (bits A31 to A0), even if the value of bit A29 is either 1 or 0, as long as the values ​​of the remaining 31 bits (bits A31 to A30 and bits A28 to A0) are the same, the same address in the same memory is indicated. For example, whether address 0x18000000 is accessed for READ or address 0x38000000 is accessed for READ, the same data will be read from address zero of the work memory 57. Note that when address 0x18000000 is accessed for READ, the read data is stored in the cache, but FIG. 9(b) illustrates the access operation when the cache is enabled / disabled.

[0202] However, it is also possible to disable the cache operation for the instruction cache and / or operand cache based on the setting value of a predetermined operation control register REG. However, in this embodiment, after power-on, the cache operation for the instruction cache and operand cache is enabled, and then the cache operation is disabled as necessary by accessing the cache-disabled space.

[0203] 10, addresses 0x40000000 and beyond are internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the cache address array space. Addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are allocated to built-in peripheral modules, specifically, to the operation control register REG of the CPU circuit. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

[0204] Continuing with the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multi-function timer unit MTU are circuits that count external signals supplied to the CPU circuit 51 or count a count clock obtained by multiplying or dividing the internal clock, and generate an interrupt signal or the like when the count result reaches a predetermined value. Although not particularly limited, in this embodiment, the multi-function timer unit MTU is used to generate a 1 ms interrupt signal and a 20 μS interrupt signal. The multi-function timer unit MTU is also used to realize a clock timer TM that measures the elapsed time after the CPU is reset.

[0205] Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, and starts interrupt processing (interrupt handlers) based on predefined priorities. Here, IRQ_CMD is a command reception interrupt signal that should receive a control command CMD, IRQ_SND is an end interrupt signal that indicates that the audio processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

[0206] In this embodiment, the command reception interrupt IRQ_CMD has the highest interrupt priority, followed by the 20 μS interrupt → 1 ms interrupt → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → IRQ_RCT (see Figure 18(d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not being output from the oscillator OSC2, as explained above.

[0207] In any interrupt processing, the register values ​​(each 32 bits long) of the CPU's multiple built-in registers are automatically saved to one of the free register banks RBi. Then, when a predetermined restore command is executed at the end of the interrupt processing, the saved data is automatically restored to the corresponding built-in register.

[0208] Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of this embodiment is a circuit that repeats data transfers from a transfer source (Source) to a transfer destination (Destination) in a predetermined DMA transfer mode for a predetermined number of times for each predetermined data transfer unit, based on the setting value of a predetermined operation control register REG. Note that multiple channels, DMAC0 to DMACn, each having the same internal configuration, are provided and can operate in parallel. However, priorities are determined (Channel 0 >... > Channel n), and during parallel operation in channel arbitration operation mode, the operation of the DMACi with the higher priority is prioritized through channel arbitration at a predetermined timing.

[0209] As an example of utilization of the DMAC circuit 60, in an embodiment in which the serial output port SO functions (see the dashed line in FIG. 10(a)), the operation control register REG of the CPU circuit 51 specifies the top address of the lamp / motor drive table (top value of the source address), the address of the input register of the serial output port SO (fixed value of the destination address), the data transfer unit (8 bits), and the number of transfers. Then, upon receiving an operation start instruction from a predetermined operation control register REG, the DMAC circuit 60 DMA-transfers the drive data to a predetermined destination address while updating the source address. Then, when all DMA transfers are completed, a DMAC interrupt (operation end interrupt) is generated.

[0210] This is almost the same in the case of the embodiment (Fig. 25, Fig. 29(c)) in which the display list DL is issued by the DMAC circuit 60. That is, the performance control CPU 63 sets the starting address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a predetermined operation control register REG of the CPU circuit 51. These points will be described further below with reference to Fig. 25.

[0211] Generally, DMA transfer modes include cycle steal transfer mode, in which bus control is released midway through a unit operation (R operation / W operation) of a DMA transfer so that the DMA operation does not occupy the memory bus; burst transfer (pipeline transfer) mode, in which bus control is not released until a specified number of transfers are completed, such as by consecutively performing multiple R operations or W operations; and demand transfer mode, in which DMA operation continues while a DMA transfer request (demand) received from another device is active. However, the DMAC circuit 60 of this embodiment functions in cycle steal transfer mode, which provides a memory release period of at least one cycle between the start of read access (R operation) and the start of write access (W operation) during DMA transfer, thereby preventing any disruption to the operation of the performance control CPU 63.

[0212] Figure 11 is a diagram explaining cycle steal transfer operation (a1) and pipeline transfer (a2). As shown in Figure 11(a1), the DMAC circuit 60 functioning in cycle steal transfer mode operates with at least one cycle between the read access activation (R) and write access activation (W) of one data transfer, and this empty cycle allows the performance control CPU 63 to use the bus. As is clear from the comparison between Figure 11(a1) and Figure 11(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in cycle steal transfer mode, the bus is released to the CPU for each read access, so CPU operation is not significantly delayed.

[0213] For example, in an embodiment in which the DMAC circuit 60 is used when issuing the display list DL to the VDP circuit 52, the data transfer unit (one operand) for one cycle is set to 32 x 2 bits, and the source address of the internal RAM 59 in which the display list DL is stored is incremented appropriately (+8 for each operand transfer), and a DMA transfer operation is performed for the transfer port register TR_PORT (see Figure 13) of the data transfer circuit 72 specified by a fixed address.

[0214] As will be described later, in this embodiment, the required number of NOP (no operation) commands are added to the display list DL to adjust the overall data size to a fixed value (for example, 4 x 64 = 256 bytes, or an integer multiple thereof), and the issuance of the display list DL is completed by repeating one operand transfer of 32 bits x 2 times 32 times (or an integer multiple thereof). Note that even if the drawing circuit 76 executes a NOP command, it is in a no operation state, and in fact, no change occurs.

[0215] Furthermore, when classifying the operating modes in terms of DMA transfer conditions, there are generally three types: single operand transfer (see Figure 11(b1)), consecutive operand transfer (see Figure 11(b2)), and non-stop transfer (see Figure 11(b3)).

[0216] Here, single operand transfer refers to an operating mode in which the transfer of one operand is repeated each time a DMA transfer request is issued, and a DMA interrupt request occurs when the byte count, which counts the number of transferred bytes, reaches zero, as shown in Figure 11(b1).Next, continuous operand transfer refers to an operating mode in which DMA transfer is repeated with one DMA request until the byte count reaches zero, as shown in Figure 11(b2).

[0217] In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time one operand transfer is completed, and the transfer of the current channel continues (channel arbitration operation mode) provided that there is no DMA request for a channel with a higher priority. Therefore, in this embodiment, the single operand transfer method is used for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. During parallel operation, the DMACi of the optimal channel is used so that channel arbitration is performed in the order of priority: motor data > display list DL > lamp data.

[0218] On the other hand, nonstop transfer is an operating mode in which channel arbitration is not performed, and as shown in Fig. 11(b3), DMA transfer is continuously repeated with one DMA request until the byte count reaches zero. In this embodiment, in the memory section initialization process at power-on (SP8 in Fig. 16), programs and data are DMA transferred using nonstop transfer.

[0219] Having explained the CPU circuit 51 above, we will now explain the VDP circuit 52. Connected to the VDP circuit 52 are a CGROM 55 that stores compressed data that constitutes the still and moving images that make up the image presentation, an external DRAM (Dynamic Random Access Memory) 54 with a storage capacity of about 4 Gbit, a main display device DS1, and a sub-display device DS2. The DRAM 54 is preferably configured with DDR3 (Double-Data-Rate 3 SDRAM).

[0220] Here, as shown in Figure 14(b), the DRAM 54 receives a DDR clock generated based on the oscillation output (40 MHz) of the oscillator OSC2. Also, the DRAM 54 of the embodiment has a built-in refresh counter, and the self-refresh function is enabled at the time of initial setting (SP4 in Figure 16), so refresh control operation by the performance control CPU 63 is not required.

[0221] Although not particularly limited, in this embodiment, the CGROM 55 is configured as a flash SSD (solid state drive) made up of NAND flash memory with a storage capacity of approximately 62 Gbit, and is configured to acquire the required compressed data via serial transmission. This eliminates the problem of skew (difference in transmission speed for each bit of data) that inevitably occurs in parallel transmission, enabling extremely high-speed transmission operations. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed using an HSS (High Speed ​​Serial) method that complies with Serial ATA.

[0222] Regardless of whether or not it uses the HSS method compliant with Serial ATA, NAND-type flash memory is more mechanically stable than a hard disk and allows for high-speed access, but because it is a sequential access memory, it has problems with random access compared to DRAM or SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is performed in which a group of compressed data (CG data) is read into DRAM 54 prior to the drawing operation, thereby achieving smooth random access of the CG data during the drawing operation. Incidentally, the access speed decreases in the following order: built-in VRAM > external DRAM > CGROM.

[0223] The VDP circuit 52, in detail, comprises a group of control registers 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the performance control CPU 63; an internal VRAM (video RAM) 71 of about 48 MB that is used when generating image data to be displayed on the display devices DS1 and DS2; a data transfer circuit 72 that executes data transmission and reception between each section within the chip and data transmission and reception with the outside of the chip; an index table IDXTBL that can identify address information of the source and destination for the internal VRAM 71; a preloader 73 that executes a preload operation that reads and accesses the CGROM 55 prior to a drawing operation; a graphics decoder (GDEC) 75 that decodes (decodes and expands / expands) compressed data read from the CGROM 55; a drawing circuit 76 that generates image data for one frame of each of the display devices DS1 and DS2 by appropriately combining still image data and video data after decoding (expanding); a geometry engine 77 that generates a three-dimensional image by appropriate coordinate conversion as part of the operation of the drawing circuit 76; The display device 70 is configured to include three display circuits 74A-74C (A / B / C) capable of executing appropriate image processing in parallel, an output selection unit 79 that appropriately selects and outputs the output of the three display circuits 74 (A / B / C), an LVDS unit 80 that converts the image data output by the output selection unit 79 into an LVDS signal, an SMC circuit 78 that can transmit and receive serial data, a CPUIF unit 81 that relays data transmission and reception with the CPUIF circuit 56, a CG bus IF unit 82 that relays data reception from the CGROM 55, a DRAMIF unit 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF unit 84 that relays data transmission and reception with the built-in VRAM 71 (see FIG. 8(a)). An audio circuit SND is also built in.

[0224] 8(b) illustrates the relationship between the CPUIF unit 81, CG bus IF unit 82, DRAMIF unit 83, and VRAMIF unit 84 and the control register group 70, CGROM 55, DRAM 54, and built-in VRAM 71. As illustrated, CG data acquired from CGROM 55 is transferred, for example, as preload data to the preload area of ​​the external DRAM 54 via the data transfer circuit 72 and DRAMIF unit 83.

[0225] However, the above-described preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, but may be the built-in VRAM 71. Therefore, for example, in an embodiment in which the preload operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF unit 84 (FIG. 8(b)).

[0226] In this embodiment, the built-in VRAM 71 requires a decompression area for compressed data read from the CGROM 55, a frame buffer area for storing image data specifying each ARGB information (32 bits = 8 × 4) of W × H display pixels of the display device, and a Z buffer area for storing depth information for each display pixel. In the ARGB information, A means 8-bit alpha plane data, and RGB means 8-bit data of the three primary colors.

[0227] Here, each of the above-mentioned areas of the built-in VRAM 71 is indirectly accessed based on the various instruction commands (such as the textures and sprites mentioned above) written in the display list DL by the performance control CPU 63, but it would be cumbersome to specify the destination address and source address of the built-in VRAM 71 for each READ / WRITE access. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as index space) required for drawing operations is secured, and an index number is assigned to each index space, making it possible to access based on the index number.

[0228] Specifically, after the CPU is reset, the internal VRAM 71 is roughly divided into three types of memory areas, and the required number of index spaces is secured in each memory area. Then, an index table IDXTBL (see Figure 12(a)) is constructed to associate and store the index spaces with index numbers, thereby enabling subsequent operations based on the index numbers.

[0229] This index space may need to be (1) added after initial processing or, conversely, (2) released. Therefore, a flag area FG is provided in the index table IDXTBL to determine whether the timing for the addition / release process is possible and whether the process has actually been completed during the operation of the performance control CPU 63 for the addition / release. The built-in VRAM 71 is broadly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an optional area (c), as described below. The index table IDXTBL is divided into three sections corresponding to these three types of memory areas (a1, a2), (b), and (c) (Figure 12(a)). As shown in the figure, in this embodiment, a first AAC area (a1) and a second AAC area (a2) are secured as the AAC area (a), but this is not particularly limited, and only one of them may be used. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as AAC area (a).

[0230] In this embodiment, the built-in VRAM 71 is configured to be divisible into (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and which has a memory cache function, (b) a page area in which, for example, a two-dimensional space of 4096 bits x 128 lines is used as the unit space and an index space can be secured within a range of an integer multiple of this, and (c) an arbitrary area in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily (see FIG. 12(b)). However, to facilitate the internal operation of the VDP circuit 52, the space start address STx of the index space, which is arbitrarily set in the arbitrary area (c), must have the lowest 11 bits set to 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0231] After the CPU is reset, the maximum value of the address space required for each area and the area start address (lower 11 bits = 0) are specified, and the AAC area (a1), second AAC area (a2), and page area (b) are secured, with the remaining memory area becoming the optional area (c). To facilitate the internal operation of the VDP circuit 52, the maximum value of the address space for the AAC area is specified in units of 2048 bits, and the maximum value of the address space for the page area is an integer multiple of the unit space of 4096 bits x 128 lines described above.

[0232] Next, the required number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When using the optional area (c), in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be set arbitrarily as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

[0233] In any case, the first and second AAC areas (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 52. Therefore, for example, if the decoding destination is specified as AAC area (a) by the SETINDEX command, which is a texture setting command, then it is sufficient to specify the source address of CGROM 55 and the horizontal and vertical size after expansion (decoding) in the TXLOAD (texture load) command that reads CG data from CGROM 55. Therefore, in this embodiment, the decoding destination for still images (textures) such as characters that appear temporarily during preview performances, and for I-stream moving images, is set to AAC area (a).

[0234] Since both AAC areas (a) are provided with a memory cache function, for example, if the same texture from CGROM 55 is read into AAC area (a) multiple times, the decoded data cached in AAC area (a) can be used from the second time onwards, making it possible to reduce unnecessary read accesses and decoding processes. However, since old data is automatically destroyed when AAC area (a) is used up, in this embodiment, when using AAC area (a), the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are stored in the second AAC area (a2).

[0235] Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview performance, background images when the background screen is constructed with still images, etc. In such cases, the SETINDEX command, which is a texture setting command, sets the decoding destination to the second AAC area (a2), and after the TXLOAD command decodes the texture of the characters, background images, etc. into the second AAC area (a2), the second AAC area (a2) is not used, thereby protecting the decoded results.

[0236] Then, after that, if the SETINDEX command is used to specify the second AAC area (a2) as the decoding destination and the same TXLOAD command is executed to re-acquire the acquired texture, the acquired texture will be a cache hit, so it is possible to eliminate the time required for READ access to CGROM 55 and the decoding process. As will be described later, this cache hit function is also exerted by preload data pre-read into the preload area, but the significance lies in the fact that the preload data that is a cache hit in the preload area is compressed data before decoding, whereas the cache hit in the AAC area is decompressed data after decoding.

[0237] The term "texture" generally refers to the feel and texture of an object's surface, but in this specification it is used to include not only sprite image data that makes up a still image, image data that makes up one frame of a video, and image data pasted onto drawing primitives such as triangles and rectangles, but also image data after decoding. When copying image data within the internal VRAM 71 (hereinafter referred to as "moving" for convenience), the source image data is set as a texture using the SETINDEX command, a texture setting command, and then the SPRITE command is executed.

[0238] When the SPRITE command is executed, the source Source image data is technically drawn in the virtual drawing space shown in Figure 12(c), but if the correspondence between the drawing area in the virtual drawing space that is actually drawn on the display device and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then when drawing in the virtual drawing space using the SPRITE command, the source Source image data will be drawn in a specified index space (frame buffer) (see Figure 12(c)).

[0239] In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured for each area, and each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and the performance control CPU 63 can freely assign index numbers in the range of 0 to 255 to the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuit).

[0240] Therefore, in this embodiment, as shown in Figure 12(a), a pair of frame buffers FBa are reserved in the arbitrary area (c) for the display device DS1, and index numbers 255 and 254 are assigned to both of the double-buffer structure. That is, index space 255 and index space 254, which are used by switching between them in a toggle manner, are reserved as frame buffer FBa for the main display device DS1. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of horizontal pixels of the display device DS1. Note that each pixel is specified by 32-bit ARGB information, so the horizontal size of 1280 means 32 x 1280 = 40960 bits (a multiple of 256 bits).

[0241] Furthermore, another pair of frame buffers FBb are reserved in the arbitrary area (c) for the display device DS2, and index numbers 252 and 251 are assigned to both sides of the double buffer structure. That is, index space 252 and index space 251 are reserved as frame buffer FBb for the sub-display device DS2. These index spaces 252 and 251 have a horizontal size of 480, corresponding to the number of horizontal pixels of the display device DS2. In this case as well, each pixel is specified by 32-bit ARGB information, so the horizontal size of 480 means 32 x 480 = 15,360 bits (a multiple of 256 bits).

[0242] The reason why frame buffers FBa and FBb are reserved in the arbitrary area (c) is that the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (=256 bits=8 pixels), and as described above, if it matches the number of horizontal pixels of display devices DS1 and DS2, no wasted space will be generated in the reserved area.On the other hand, the page area (b) can only be set to horizontal / vertical sizes that are integer multiples of the unit space of 128 pixels x 128 lines.

[0243] However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (for example, 2048 lines). Therefore, in the frame buffer FBa, only an area with a horizontal size of 1280 and a vertical size of 1024 becomes the valid data area for the main display device DS1. The same is true for the sub-display device DS2, where in the frame buffer FBb, only an area with a horizontal size of 480 and a vertical size of 800 becomes the valid data area for the sub-display device DS2 (see FIGS. 12(c) and 22(e)).

[0244] This point will be discussed further below, but in any event, the frame buffers FBa and FBb have double buffers (255 / 254, 252 / 251) that are alternately used as the drawing area for the drawing circuit 76, and the double buffers (255 / 254, 252 / 251) that are alternately used as the display area for the display circuits 74A and 74B. Note that in this embodiment, a missing number (253) occurs because a Z buffer that stores depth information of display pixels is not used, but if a Z buffer were to be used, the index spaces 253 and 250 of index numbers 253 and 250 in the arbitrary area (c) would become the Z buffers for the display devices DS1 and DS2.

[0245] Furthermore, in this embodiment, when an additional index space (memory area) is reserved in the arbitrary area (c) where the frame buffers FBa and FBb are reserved, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is reserved in the arbitrary area (c) as a working area for preview effects in which effect images made up of characters and other still images are made to appear in a part of the display screen in an appropriate rotated position as needed.

[0246] However, the use of a work area is not essential, and index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, the horizontal size of 12 8 Since it is possible to secure an index space with dimensions that are multiples of a square unit space of (=4096 bits) x vertical size 128, it is suitable for handling small-sized performance images.

[0247] In this embodiment, the background image is also composed of moving images, and the image presentation is realized almost entirely with moving images. In particular, during a variation presentation, a large number of moving images (usually 10 or more) are simultaneously drawn. All of these moving images are stored in the CGROM 55 in a compressed state as a series of moving image frames, and are classified into I-stream moving images composed only of I-frames and IP-stream moving images composed of I-frames and P-frames. Here, an I-frame (Intra-coded frame) refers to a frame in which the input image is compressed as is, independent of other screens. On the other hand, a P-frame (Predictive-coded frame) refers to a frame that undergoes forward predictive coding, and requires an I-frame or P-frame located in the past in time.

[0248] Therefore, in this embodiment, IP stream video is expanded in the page area (b) rather than the AAC area (a) where there is a concern that old data may be destroyed. That is, a large number of index spaces (IDX0 to IDX1) are allocated in the page area (b) where an index space of a multiple of horizontal size 128 × vertical size 128 can be secured. N) is secured so that a series of video frames are always decoded using the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded into index space IDX1, video MV2 is expanded into index space IDX2, and so on, with video MVi being expanded into index space IDXi.

[0249] To explain the video MVi more specifically, the SETINDEX command specifies in advance that the IP stream video MVi will be decoded to index space (i) of index number i in page area (b), and then the TXLOAD command is executed to obtain one video frame of the IP stream video MVi.

[0250] Then, one video frame (any of a series of video frames) on CGROM 55 specified by the TXLOAD command is first retrieved into the AAC area (a), and then the GDEC (graphics decoder) 75, which starts automatically, decodes and expands the retrieved video frame into the index space (i) of the page area (b).

[0251] On the other hand, in this embodiment, I-stream video is treated the same as still images, and the SETINDEX command specifies that "the decoding destination of I-stream video MVj is the first AAC area (a1)," and then the TXLOAD command is executed. As a result, video frames are acquired in the first AAC area (a1), and then the automatically activated GDEC75 expands the decoded data to the first ACC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify an index number. Note that the expansion volume required for the index space, i.e., the horizontal and vertical sizes of the decoded texture (video frame), are specified by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0252] Incidentally, IP stream video MVi and I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 where the kth (1≦k≦N) video frame is stored, as well as the horizontal and vertical sizes after expansion. Although not limited in any way, in an embodiment in which still images are hardly used, most of the 48 MB address space of the internal VRAM 71 (approximately 30 MB) is allocated to the page area (b). In an embodiment in which still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, and the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

[0253] It is also possible to provide a dedicated GDEC (graphics decoder) circuit to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is built into VDP circuit 52, it will be sufficient to specify the start address of the compressed video data to the GDEC circuit in the decoding process of compressed video data made up of N compressed video frames, eliminating the need to specify the start address for each of the N compressed video frames.

[0254] However, if multiple dedicated GDEC circuits like this were built in for each compression algorithm, the internal configuration of the VDP circuit 52 would become even more complex. Therefore, in this embodiment, a software GDEC is used, and decoding of data such as IP stream video, I stream video, still images, and other α values ​​is achieved through software processing corresponding to each compression algorithm. The difference in processing time between hardware processing and software processing is not a significant issue; the processing time that matters is primarily the access (READ) time from the CGROM 55.

[0255] 8(a), the data transfer circuit 72 is a circuit that executes a data transfer operation in a DMA (Direct Memory Access) manner between a resource (storage medium) within the VDP circuit and an external storage medium, with the resource being the transfer source port and the external storage medium being the transfer destination port. Figure 13 is a block diagram showing the internal configuration of this data transfer circuit 72 together with the related circuit configuration.

[0256] 13, the data transfer circuit 72 is configured to transmit and receive data to and from the CGROM 55, DRAM 54, and built-in VRAM 71 via an integrated connection bus ICM having a router function. The CGROM 55 and DRAM 54 are accessed via a CG bus IF unit 82 and a DMA MIF unit 83.

[0257] Meanwhile, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and preloader 73 via a transfer port register TR_PORT built into the data transfer circuit 72. The CPU circuit 51 and data transfer circuit 72 are connected bidirectionally, but when issuing a display list DL, the transfer port register TR_PORT functions as a data write port that accepts one unit of data that makes up the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 72d.

[0258] As shown in the figure, the performance control CPU 63 can make WRITE access to the transfer port register TR_PORT via the CPUIF unit 81, but when the DMAC circuit 60 is used, the DMAC circuit 60 makes direct WRITE access to the transfer port register TR_PORT. The series of instruction commands written to the transfer port register TR_PORT (that is, the series of instruction commands that make up the display list DL) are automatically stored in 32-bit units in the CPU bus control unit 72d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

[0259] In addition, this data transfer circuit 72 performs data transmission and reception operations on the transmission paths of three channels ChA to ChC, and has a ChA control circuit 72a (N=130 stages) having a FIFO buffer with a FIFO structure (64 bits x N stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

[0260] The instruction command sequence (display list DL) stored in the CPU bus control unit 72d is then transferred to either the drawing circuit 76 or the preloader 73 based on the setting value of the data transfer register RGij (one type of various control registers 70) by the performance control CPU 63. As shown by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and then to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

[0261] In this embodiment, the ChB control circuit 72b and the ChC control circuit 72c are specialized for the transfer operation of the display list DL, and the data accumulated in the FIFO buffer of the CPU bus control unit 72d is transferred as part of the display list DL to the drawing circuit 76 or the display list analyzer of the preloader 73 via the FIFO buffer of the ChB control circuit 72b or the ChC control circuit 72c, respectively.

[0262] The drawing circuit 76 then starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 73 executes the necessary preload operations based on the transferred display list DL. By the preload operation, the CG data in the CGROM 55 is pre-fetched into a preload area secured in the DRAM 54, and the display list DL with the texture source address changed in response to a TXLOAD command or the like (hereinafter referred to as a rewrite list DL') is saved in a DL buffer area BUF' secured in the DRAM 54.

[0263] On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. Furthermore, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 72a functions, for example, when (a) compressed data from the CGROM 55 is transferred to the built-in VRAM 71, (b) compressed data from the CGROM 55 is preloaded (read ahead) and transferred to the external DRAM 54, and (c) read-ahead data from the preload area is transferred to the built-in VRAM 71.

[0264] Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above can be executed in parallel with the issuance operation of the display list DL (ST8 in FIG. 22, PT11 in FIG. 27) and the transfer operation of the rewrite list DL' (PT10 in FIG. 27). The ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously. For example, the processing of step PT10 in FIG. 27 in which the ChB control circuit 72b functions and the processing of step PT11 in which the ChC control circuit 72c functions can be executed in parallel. However, since there is only one transfer port register TR_PORT, when one of them (72b / 72c) is using the transfer port register TR_PORT, the other (72c / 72b) cannot access the transfer port register TR_PORT.

[0265] During operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f controls the ChA control circuit 72a based on the index table IDXTBL to arbitrate data communication with the built-in VRAM 71. In an embodiment in which the preloader 73 is functioning, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see FIG. 28(b)).

[0266] As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various storage resources (Resources) and a data transfer destination arbitrarily selected from various storage resources (Resources). As can be seen from Fig. 13, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPUIF unit 56, CG bus IF unit 82, and DRAMIF unit 83.

[0267] Furthermore, the amount of data transferred between the external device in which the ChA control circuit 72a functions, such as the amount of data to be obtained at one time from the CGROM 55 (memory sequential READ), is enormous compared to the display list DL in which the ChB control circuit 72b or the ChC control circuit 72c functions, and the data transfer amounts are significantly different between the two.

[0268] While it would be possible to configure these various data transfers so that the unit data volume and total transfer data volume could be precisely set, this would complicate the control operations within the VDP and hinder smooth transfer operations. Therefore, in this embodiment, a minimum data volume Dmin for data transfer is uniquely defined, and the total transfer data volume is limited to an integer multiple of the minimum data volume DTmin, thereby achieving fast and smooth data transfer operations. While not particularly limited, in the data transfer circuit 72 of this embodiment, the minimum data volume Dmin (unit data volume) is set to 256 bytes, and the total transfer data volume is limited to an integer multiple of this volume.

[0269] Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 72d in 32-bit increments is transferred to the ChB control circuit 72b and the ChC control circuit 72c when the total amount reaches the minimum data amount Dmin, and is stored in each FIFO buffer.

[0270] The display list DL is made up of a series of instruction commands, but in this embodiment, corresponding to the write unit (32 bits) of the transfer port register TR_PORT, the display list DL is made up only of instruction commands whose command length is an integer multiple of 32 bits (N>0). Therefore, the drawing circuit 76 and preloader 73 that receive the instruction commands of the display list DL via the data transfer circuit 72 can quickly and smoothly start command analysis processing (DL analyze). Note that the command length of an integer multiple of 32 bits does not necessarily mean that all of the bits are significant, but also includes insignificant bits (don't care bits), meaning that it is an integer multiple of 32 bits.

[0271] Next, the preloader 73 will be described. As briefly explained above, the preloader 73 is a circuit that interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72c) and transfers the CG data in the CGROM 55 referenced by the TXLOAD command to a preload area in the DRAM 54 in advance. Furthermore, the preloader 73 stores a rewrite list DL' in which the reference destination of the CG data for this TXLOAD command is rewritten to the address after transfer in the DL buffer BUF' of the DRAM 54. Note that the DL buffer BUF' and the preload area are reserved in advance during the initial processing after the CPU is reset (SS3 in FIG. 21).

[0272] The rewrite list DL' is then transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b of the data transfer circuit 72 when the drawing operation of the drawing circuit 76 starts. The drawing circuit 76 then executes the drawing operation based on the rewrite list DL'. Therefore, based on the TXLOAD command or the like, CG data that should originally be obtained from the CGROM 55 is obtained from the preload area of ​​the DRAM 54 as preload data that has been pre-read into the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and preload data that has been cache-hit in the preload area is repeatedly reused.

[0273] In this embodiment, the preload area is set in the external DRAM 54, which has sufficient storage capacity, so the cache hit function described above functions effectively. Furthermore, the large storage capacity of the external DRAM 54 makes it possible to perform multiple preloading, for example, preloading multiple frames of CG data all at once. That is, multiple preloading is achieved by appropriately setting the operating period of the preloader 73, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the VDP circuit 52 during intermittent operation.

[0274] However, in the following explanation, for convenience, an embodiment without multiple preloading will be described, and therefore, it is assumed that the preloader 73 of the embodiment completes the preloading operation for one frame during one operation period (δ). Note that, as will be described later with reference to Figure 22, in this embodiment, the operation period δ during intermittent operation of the VDP circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS1.

[0275] Next, the drawing circuit 76 is a circuit that sequentially analyzes the instruction command sequences of the display list DL and the rewrite list DL′ transferred via the data transfer circuit 72, and works in cooperation with the graphics decoder 75, the geometry engine 77, etc. to draw one frame of image for each of the display devices DS1 and DS2 in the frame buffer formed in the VRAM 71.

[0276] As described above, in the embodiment in which the preloader 73 is activated, the CG data in the rewrite list DL' is referenced not in the CGROM 55 but in the preload area set in the DRAM 54. This allows for rapid sequential access to CG data generated during rendering by the rendering circuit 76, making it possible to render high-resolution moving images with rapid movement without any problems. In other words, according to this embodiment, complex and sophisticated image presentation can be achieved while utilizing an inexpensive SATA module as the CGROM 55.

[0277] Regardless of whether the preloader 73 is enabled or disabled, even if data corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 76 cannot detect this. Furthermore, the drawing circuit 76 may freeze due to noise or other factors, causing an abnormal stop of READ / WRITE access to the internal VRAM 71. Therefore, in this embodiment, if the drawing circuit 76 detects an irrational instruction command (a bit sequence that cannot be analyzed) or if there is no READ / WRITE access to the internal VRAM 71 for a certain period of time, a drawing abnormality interrupt is generated (drawing abnormality interrupt is enabled). This point will be described later with reference to FIG. 22(d).

[0278] Next, as explained with reference to FIG. 12, the frame buffer FB allocated in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a read area, and the two areas are used alternately. In this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa / FBb are allocated, as shown in FIG. 12. Therefore, the drawing circuit 76 draws one frame's worth of image data in the drawing area (write area) of the frame buffer FBa for display device DS1, and also draws one frame's worth of image data in the drawing area (write area) of the frame buffer FBa for display device DS2. Note that while image data is being written to the drawing area, the display circuit 74 reads image data from the other read area (display area) and outputs it to each of the display devices DS1 and DS2.

[0279] The display circuit 74 is a circuit that reads image data from the frame buffers FBa and FBb, performs final image processing, and outputs the result (see FIG. 14(a)). The final image processing includes, for example, scaling processing using a scaler to enlarge or reduce the image, subtle color correction processing, and dithering processing to minimize quantization errors across the entire image. The digital RGB signal (total of 24 bits) that has undergone these image processing steps is then typically output together with a horizontal synchronization signal HS, a vertical synchronization signal VS, and so on.

[0280] 14(a), in this embodiment, three display circuits A / B / C are provided that perform the above operations in parallel, and each of the display circuits 74A-74C reads image data from its corresponding frame buffer FBa / FBb / FBc and performs the above final image processing. However, in this embodiment, since there are only two display devices, the frame buffer FBc is not reserved and the display circuit 74C does not function.

[0281] The specifications of the main display device DS1 reveal that it must receive adjacent odd and even pixels (ODD and EVEN) via separate LVDS (Low Voltage Differential Signaling) transmission paths at the receiver RV (RVa+RVb). The main display device DS1's operating clock CK frequency must be approximately 40-70 MHz (typically 54 MHz), and the horizontal and vertical wait times WTh and WTv must be set so that (WTh+640) × (WTv+1024) / 54 MHz ≒ 1 / 60 seconds. Furthermore, when outputting image data (ODD / EVEN signals) to the main display device DS1, it must output an active-level data enable signal ENAB.

[0282] Therefore, the display circuit 74A must output signals that satisfy all of the above specifications. Figures 15(a) to 15(e) illustrate various signals output from the display circuit 74A. First, the frequency of the dot clock (LVDS clock) DCK must be determined. In this embodiment, the main display device DS1 is operated by an operating clock CK with a typical value of 54 MHz, so the designed dot clock DCK (in the VDP circuit 52) ​​is set to 108 MHz (= 54 × 2).

[0283] This is because in a display panel LCD (see Figure 15(f)) with 1280 dots horizontally and 1024 lines vertically, two adjacent pixels on the left and right are processed at once in synchronization with the 54 MHz operating clock CK, which is essentially equivalent to operating with a 108 MHz dot clock DCK.

[0284] Then, various operation parameters that define the operation of the display circuit 74A are defined based on a dot clock DCK with a frequency of 108 MHz. First, it is necessary to set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1 / 60 second. However, for the operation parameters WTh and WTv of the display circuit 74A, it is necessary to satisfy (WTh + 1280) × (WTv + 1024) / 108 MHz ≈ 1 / 60 second.

[0285] Also, regarding the horizontal / vertical standby times WTh / WTv, it is necessary to consider the allowable range in the specifications of the display device DS1. Therefore, in this embodiment, the horizontal standby time WTh is counted with a dot clock DCK of 108 MHz and set to 382 clocks, and the vertical standby time WTv is set to 59 lines. Therefore, the time required for updating an image for one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) is 1 / 60 second. <000110>

[0286] This relationship defines the update period FR [seconds] of the display device DS1. Using the frequency F of the dot clock DCK, the number of cycles THc of the horizontal synchronization, and the number of lines TVl of the vertical synchronization described later, FR = THc × TVl / F dot becomes. Here, if the update period FR is too long, there is a risk of abnormalities such as flicker. On the other hand, if the update period FR is too short, the display device cannot execute normal update processing. Therefore, it should be defined within the range of 0.95 / 60 < FR [seconds] < 1.05 / 6. dot 0.

[0287] Corresponding to this setting, the data valid signal ENAB is at L level during the waiting time WTh (=382 / 108MHz) corresponding to 382 clocks in the image update operation of each line, and then becomes active level (H) during the active section (=1280 / 108MHz) corresponding to 1280 clocks (Fig. 15(c)). As shown in Fig. 15(d) and Fig. 15(e), during the active section of the data valid signal ENAB, image data is output so that the image update operation for one line of 1280 dot pixels is completed within a predetermined time (11.85µS=1280 / 108MHz). In other words, 1280 pixel data (Pixel Data) are output in synchronization with 1280 dot clocks DCK. The display device DS1 has a gradation of 2 8 ×2 8 ×2 8 Since a full color image is displayed, the pixel data for one pixel is 3 x 8 bits long.

[0288] In this embodiment, the main display device DS1 outputs a vertical synchronizing signal VS and a horizontal synchronizing signal HS, even though they are not required. The vertical synchronizing signal VS is output within a vertical wait time WTv, and the horizontal synchronizing signal HS is output within a horizontal wait time WTh. For ease of understanding, FIGS. 15(a) and 15(b) show the respective operating periods. Also, in FIG. 15(f), a rectangular frame defined by TH×TV (=1083×1662 clocks) is indicated with circles at the top left and bottom right vertices, along with the notation "Start of display operation" and "End of display operation." These circles represent the "V blank start" that defines the operating period of the display circuit 74A, which starts every 1 / 60 seconds. Because the 1083×1662 clocks that define the display operation coincide with 1 / 60 seconds, the elapsed time from the "start of display operation" to the "end of display operation" (the operating period of the display circuit 74A) is 1 / 60 seconds. The "V blank start" will be described later with reference to FIG.

[0289] 14, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into dual links by dividing the 108 MHz dot clock DCK by two, and transmits them to the LVDS unit 80a and the LVDS unit 80b, respectively (see FIG. 14(a) and FIG. 5). Each of the LVDS units 80a and 80b then converts the image data (a total of 24-bit digital RGB signal) into first and second LVDS signals, adds a pair that transmits a clock signal (54 MHz = 108 / 2), and outputs a total of five pairs of differential signals LVDS1 and LVDS2 to the main display device DS1 via two paths (see FIG. 14(a) and FIG. 4).

[0290] As explained above, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for the adjacent pixel are processed at the same timing, so the frequency of the actual operating clock CK matches the 108 MHz dot clock DCK output by the display circuit 74A.

[0291] The above has described the display circuit 74A, which generates images to be transmitted to the main display device DS1, but the display circuit 74B generates image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and is transmitted to the sub-display device DS2 together with the vertical synchronization signal VS and horizontal synchronization signal HS.

[0292] In addition to the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB section 80c, but of course these signals are transmitted as continuous signals rather than as discrete values ​​as in the case of an LVDS transmission line (see Figure 14(a)).

[0293] In this embodiment, each of the display circuits 74A to 74B is provided with an underrun counter URCNTa to URCNTc that counts an underrun abnormality, which occurs when display data is not generated in time for the display timing (see FIG. 15). The counter values ​​of these underrun counters URCNTa to URCNTc are configured to be automatically incremented for each VBLANK when an underrun abnormality occurs.

[0294] Next, the SMC circuit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a motor controller. It outputs LED drive signals and motor drive signals in synchronization with a clock signal to an LED / Motor driver (a driver IC incorporating a shift register) mounted on an external board, and is also configured to be able to output latch pulses at appropriate timing.

[0295] Regarding the internal circuitry and its operation of the VDP circuit 52 described above, the operation content to be executed by the internal circuitry is defined by the operation parameters (setting values) set in the control register group 70 by the performance control CPU 63, and the execution state of the VDP circuit 52 can be determined by reading the operation status values ​​of the control register group 70. The control register group 70 refers to the numerous VDP registers RGij mapped to an address space of about 1 MB (0 to FFFFFH) on the memory map of the performance control CPU 63, and the performance control CPU 63 executes the WRITE (setting) operation of the operation parameters and the READ operation of the operation status values ​​via the CPUIF unit 81 (see FIG. 8(b)).

[0296] The control register group 70 (VDP register RGij) includes a "system control register" into which initial setting values ​​for system operations such as interrupt operations are written, an "index table register" that determines the AAC area (a) and page area (b) in the built-in VRAM and is used to construct or change the index table IDXTBL, a "data transfer register" into which setting values ​​for data transfer processing by the data transfer circuit 72 between the performance control CPU 63 and the internal circuitry of the VDP circuit 52 are written, a "GDEC register" that specifies the execution status of the graphics decoder 75, a "drawing register" into which instruction commands and setting values ​​for the drawing circuit 76 are written, a "preloader register" into which setting values ​​for the operation of the preloader 73 are written, a "display register" into which setting values ​​for the operation of the display circuit 74 are written, an "LED control register" into which setting values ​​for the LED controller (SMC circuit 78) are written, a "motor control register" into which setting values ​​for the motor controller (SMC circuit 78) are written, and an "audio control register SRG" into which setting values ​​for the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

[0297] In any case, in the following description, one or more registers RGij included in the control register group 70 will be referred to either by the individual names described above or collectively as VDP registers RGij. In either case, the performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values ​​to predetermined VDP registers RGij. Specifically, the performance control CPU 63 realizes predetermined image performances based on the display list DL, which is updated at appropriate time intervals, and the setting values ​​to predetermined VDP registers RGij. In this embodiment, the performance control CPU 63 is also responsible for lamp performances and motor performances, so the VDP registers RGij also include LED control registers and motor control registers.

[0298] Next, the unified control operation of image effects, sound effects, motor effects, and lamp effects, which is realized by the composite chip 50 incorporating the CPU circuit 51 and VDP circuit 52 described above, will be explained.

[0299] In this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 16(a)) due to power-on or abnormal reset, and is configured to transition to main control processing (SP10) by the performance control program Main and the interrupt processing program (vector handler) Vopt after passing through initial setting processing (SP1-SP9) by the initial setting program (boot program) Pinit. The processing contents of the introductory part of the main control processing are described in FIG. 18(a), and the processing contents of the main part are described in FIG. 22(a). Note that the processing of step SP27 in FIG. 18 does not include the processing of steps SS1-SS3 in FIG. 21(a).

[0300] Based on the above, the power-on reset operation will be explained with reference to Fig. 16(a). When the system reset signal SYS is maintained at L level for a predetermined period (assertion period), such as when the power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to predetermined default values.

[0301] Then, when the system reset signal SYS changes to H level (negate level) (see timing T1 in Figure 6(d)), in this embodiment, the clock timer TM (Figure 9(a)) starts operating to measure the elapsed time after the CPU reset (SP1). Also, 32-bit data from the first address of address space CS0 is set in the program counter PC of the performance control CPU 63, and the following 32-bit data is set in the stack pointer SP (SP1). In Figures 10 and 17(c), the top area of ​​memory that stores the initial values ​​of the program counter PC and stack pointer SP is called the vector table VECT.

[0302] 16(b), this vector table VECT stores vector numbers that specify priority and interrupt causes, etc., in association with address information. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the address information stored therein is the start address of the interrupt processing program executed upon an NMI interrupt. Also, vector number 64 is an internal interrupt (VDP_IRQ0) from the VDP, and the address information stored therein is the start address of the interrupt processing program executed upon a VDP_IRQ0 interrupt.

[0303] 18(d), the columns for vector numbers smaller than vector number 64 store the start addresses of the interrupt processing programs for the control command receive interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 ms timer interrupt. On the other hand, the columns for vector numbers larger than vector number 64 store the start addresses of the interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) with a lower priority than VDP_IRQ 1.

[0304] Furthermore, in the vector table VECT, vector number 0 and vector number 1 are defined as setting values ​​that should be automatically set in the program counter and stack pointer of the CPU at power-on reset. As shown in Fig. 16(b), in this embodiment, as an internal operation at power-on reset (reset assert period), 4-byte data "****" is set in the program counter PC, and 4-byte data "++++" is set in the stack pointer SP. Note that "****" is the start address value of the initial setting program Pinit (SP1 to SP9 in Fig. 16) stored in a non-volatile manner in the address space CS0, and "++++" is the address value of the beginning or end of a stack area secured in the internal RAM 59, which functions in a LIFO (Last-In First-Out) manner.

[0305] In this embodiment, the register bank RBi is effectively used, so the stack area is not consumed during interrupt processing, and so a large memory capacity is not required. In other words, in this embodiment, the stack area is used exclusively for function processing and subroutine processing.

[0306] As a result of the above operations, the performance control CPU 63 will then execute the initial setting program Pinit written after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG, which defines the operation of the bus state controller 66 (Fig. 9). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in Fig. 7(d) when the system reset signal SYS maintains the L level), and is set to the slowest READ access operation (default access operation) so that no matter what memory device the address space CS0 is configured with, READ access can be performed without any problems.

[0307] Therefore, in order to change this default access operation to an optimal access operation, first, an optimal value is set in a predetermined operation control register REG that specifies the operation of the bus state controller 66 (Fig. 9) for the address space CS0 (SP1). That is, in order to optimize the memory READ operation when accessing the PROM 53 that stores the initial setting program Pinit (SP1 to SP9), the performance control program MainB (SP10 and following), constant data, etc. according to the memory device, the bus width and whether or not page access is enabled are set, and the operation timing of the chip select signal CS0, the READ control signal, the WRITE control signal, and other signals are optimally set (see Fig. 40).

[0308] As a result of the above settings, the processing from step SP2 onwards will be executed by optimally reading the program stored in address space CS0 from memory. Next, in order to optimise the READ / WRITE access operation when accessing VDP register RGij, the performance control CPU 63 sets an optimal value in a predetermined operation control register REG that defines the operation of the bus state controller 66 (Fig. 9) for VDP register RGij (SP2).

[0309] As explained earlier, in this embodiment, the VDP register RGij is located in the address space CS7 of the performance control CPU 63, so a predetermined value is written to a predetermined operation control register REG in order to optimally set the operation timing of the chip select signal CS7 and other control signals.

[0310] Next, the register value of a specific VDP register RGij is read, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is a check to see whether the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and this check is to see whether or not the VDP circuit 52 can normally accept commands from the CPU circuit 51 (i.e., settings to the VDP register RGij, etc.).

[0311] Then, if it is confirmed by the device code read process (SP3) that the system clock has stabilized, normal operation of the VDP circuit 52 can be expected, and setting processing for the specified VDP register RGij is executed (SP4 to SP6). In the processing of step SP4, first, the endian setting (big / little) and data bus width when the performance control CPU 63 accesses the VDP register RGij are set (SP40), and the interrupt significance level (H / L) is set for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit (SP41).

[0312] In this embodiment, the most significant bit of the set value is set to big endian, which is stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits, but if these set values ​​are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

[0313] Furthermore, in the processing of step SP4, the frequency of the display clock is set based on the value set in a predetermined system control register RGij (SP42 to SP44). Specifically, for the display circuits 74A and 74B, the generation of dot clocks DCKA and DCKB based on a 40 MHz reference clock (output of oscillator OSC2) is set in the predetermined system control register RGij (SP42), and the multiplication ratio and division ratio for this reference clock are appropriately specified for each display circuit (SP43). Also, the start of operation of display circuit 74B is set in the predetermined system control register RGij so as to synchronize with the start of operation of display circuit 74A (SP44). Furthermore, the LVDS sampling clock is set to be the same as the dot clock DCKA of display circuit A (SP43).

[0314] In these processes, the dot clock DCK is set separately for the display circuits 74A and 74B, and the frequency of the dot clock DCKA for the main display device DS1 applied to the display circuit 74A is set to 108 MHz as explained above. On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz, corresponding to 480 horizontal x 800 vertical pixels.

[0315] Furthermore, in the processing of step SP4, the LVDS section 80 is set to be used as a dual link (a pair of LVDS transmission paths) (SP45), and based on the set value of a predetermined system control register RGij, the operating state of the LVDS section 80 is switched from a masked state (Default state) that outputs zero to an unmasked state that follows the output of the display circuit 74 (SP45). Note that when the LVDS section 80 is used as a single link (single LVDS transmission path), settings to that effect are made in the processing of step SP45.

[0316] As shown in Figure 6(f), as a result of the processing of step SP45, the operation of the LVDS unit 80 switches from the default state to the non-masked state, and thereafter, after timing T4 when the display circuit 74 starts operating (see SS4 in Figure 21), the ODD signal and the EVEN signal are supplied to the LVDS units 80a and 80b via the output selection unit 79, and the LVDS signal (LVDS1 / LVDS2) is transmitted to the display device DS1 via the dual link (see Figure 14(a)). Note that the LVDS sampling clock is set to 108 MHz, the same as the dot clock DCKA of the display circuit A, but in this embodiment, since a dual link configuration is adopted, the LVDS sampling clock in each dual link is 54 MHz (see Figure 4).

[0317] Furthermore, in the processing of step SP4, a setting is made to operate the DDR (DRAM 54) based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 8(a)) (SP46). As explained with reference to FIG. 8(a), the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal. Also, by setting appropriate values ​​in a register built into the DDR (DRAM 54), the self-refresh function (Self-Refresh Operation) of the DRAM 54 is enabled, and other settings are made to ensure normal operation of the DRAM 54 (SP47). Through the above processing, the DRAM 54 is brought into a state where it can operate normally, and the subsequent data transfer operation from the PROM 53 to the DRAM 54 (SP8) and the execution of the control program transferred to the DRAM 54 (SP10) are realized without any problems.

[0318] Next, address spaces CS1 to CS6 are defined (SP5) to realize the memory map shown in Fig. 10. As explained above, address space CS3 is assigned to the internal register of audio processor 27, address space CS4 is assigned to the internal register of RTC 38 and the address space of SRAM 39, address space CS5 is assigned to external DRAM (DDR) 54, and address space CS6 is assigned to work memory 57 of the built-in CPU.

[0319] It is fixedly specified that the VDP register RGij is assigned to the address space CS7, so there is no need to define the address space CS7. Also, it is fixedly specified in advance that the address space CS0 is located at address 0x000000000 in the memory map of the CPU circuit 51 and thereafter, and based on this specification, whether the address space CS0 is allocated to the CGROM 55 or to another memory device is specified by the H / L level of the HBTSL terminal.

[0320] As explained above, in this embodiment, the HBTSL terminal is set to L, which indicates that the address space CS0 is defined in addition to the CGROM 55. The specific bus width and optimal access operation of the control memory 53 other than the CGROM 55 have already been set in step SP1, so the processing of step SP5 is not required for the address space CS0 either.

[0321] Next, for the address spaces CS1 to CS6 defined in the processing of step SP5, predetermined values ​​are written to predetermined operation control registers REG regarding the bus width when accessing each address space CSi and whether or not page access is to be performed (SP6). Also, predetermined values ​​are written to predetermined operation control registers REG to optimally set the chip select signal CSi and other signals (SP6). These processes are similar to the processes of steps SP1 and SP2, and the chip select signal CSi, READ control signal, WRITE control signal, and other operation timings are optimally set by the write processing to the operation control registers that define the operation of the bus state controller 66 (FIG. 9).

[0322] Next, for the WDT circuit 58 that has already started operating, a clear signal is output to the WDT circuit 58 to avoid an abnormal reset (SP7). This is done in consideration of the fact that the WDT circuit 58 automatically starts operating after power is turned on, and similar processing is executed repeatedly thereafter. The processing of step SP9 is stored in the control memory 53 as a subroutine SP7, and until the end of step SP9, the subroutine SP7 in the control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to the external DRAM 54 is called and executed.

[0323] Next, of the programs and data stored in address space CS0, the vector handler Vopt (interrupt processing program), error recovery processing program Piram, performance control program MainB, variable D with initial value, and constant data C shown in Figures 16(b) and 17(c) are transferred to external DRAM 54 or internal RAM 59 (SP8). Note that variable D with initial value means initial value data stored in a specified variable area. This memory section initialization process (SP8) is a process of transferring programs and data in order to speed up performance control processing, and is a process of avoiding access to ROM, which has a slower access speed.

[0324] Next, a setting is made to use register bank RBi (SP9). As a result, register banks RB0 to RB14 will function thereafter during interrupt processing, speeding up interrupt processing and reducing stack area consumption.

[0325] The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 17(c)). Then, once the execution of this initial setting program Pinit is completed, the main control processing is executed by the performance control program Main (SP10). Here, the execution of the main control processing means the execution of the "performance control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer processing of step SP8 (see FIG. 16(b)).

[0326] The processing of the "Performance Control Program Main" is divided into the main introduction processing shown in Figure 18(a) and the upper part of Figure 21, and the main main processing shown in the lower part of Figure 21 and Figure 22(a). The specific contents will be explained based on Figure 18(a) and Figures 21 and 22, but before that, the memory section initialization processing (SP8) will be explained. As shown in Figure 17(a), in the memory section initialization processing (SP8), the DMACs of multiple channels are first initialized to a stopped state. Note that this processing is merely a formality just to be sure.

[0327] Once the above processing is completed, the DMACi of the specified channel is started, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is DMA transferred by the nonstop transfer method (see FIG. 11(b3)) to the internal RAM 59. In this embodiment, since the interrupt processing program Vopt is transferred to the internal RAM 59, appropriate abnormality handling processing can be performed even when an abnormality occurs in the external DRAM 54.

[0328] The subsequent processing is the same, and is executed in a nonstop transfer mode using the DMACi of a predetermined channel, and the error recovery processing program Piram is DMA transferred to the internal RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the internal RAM 59, the peripheral circuits can be reliably reset during the error recovery processing. For example, if the error recovery processing program Piram were transferred to an external DRAM 54 other than the internal RAM 59, the external DRAM 54 could not be reset during the error recovery processing.

[0329] Next, the performance control program Main is DMA transferred to the external DRAM 54 (SP63), and the constant data C is DMA transferred to the external DRAM 54 (SP64). The constant data includes lottery data used for performance lottery, and lamp drive data and motor drive data in the various drive data tables shown in Figure 22(b). In addition, a variable D with an initial value is DMA transferred to the external DRAM 54 (SP65), and all of these are executed by a non-stop transfer method using the DMACi of a specified channel.

[0330] Finally, clear data is written to the beginning of variable area B in the external DRAM (SP66). If this beginning address is assumed to be ADb, then in the subsequent DMA transfer process, the source address is initially set to ADb and the destination address is initially set to ADb+1, and then the clear data is diffused while the address values ​​ADb and ADb+1 are incremented, thereby clearing variable area B (SP67).

[0331] The processing of steps SP61 to SP66 and step SP67 explained above are all similar operations, as shown in Figure 17(b). That is, first, for the DMACi of a predetermined channel, the following DMA transfer conditions are set (1) cycle steal transfer mode, (2) nonstop transfer method, and (3) the source and destination address values ​​are incremented (SP68).

[0332] Next, the initial values ​​of the source address and destination address are set (SP69), the transfer size is set, and interrupts are disabled (SP70), and then the DMA transfer operation is started (SP71). Note that the settings in steps SP68 to SP71 are all realized by setting the values ​​in a predetermined operation control register REG.

[0333] In the initialization process for this memory section, DMA transfer end interrupts are prohibited (SP70), so after starting the DMA transfer operation, the status flag of the specified operation control register REG is repeatedly read and accessed to wait for the DMA transfer to end (SP72). However, taking into account the processing time until the operation ends, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, when the DMA transfer ends, the DMACi is stopped based on the setting operation of the specified operation control register REG.

[0334] Next, the operation details of the main control processing (main introduction processing + main main processing) will be explained based on Figures 18(a) to 22. With regard to the main control processing (main introduction processing + main main processing), the main introduction processing (SP20 to SP27) is shown in the upper part of Figure 18(a) and Figure 21, and the initial setting processing (SS1 to SS6), which is part of the main main processing, is shown in the lower part of Figure 21. Furthermore, the details of the regular processing (ST4 to ST14), which is the remainder of the main main processing, are shown in Figure 22.

[0335] As shown in Fig. 18(a), the main installation process first specifies the bus width and ROM device type for the CGROM 55 (SP20). Specifically, as shown in Fig. 19(a), a predetermined VDP register RGij (e.g., a CG bus status register) that specifies the operating status of the CG bus that controls the interface with the CGROM 55 is accessed for READ (SP80), and it is determined whether the operation of the CG bus can be set (SP81).

[0336] If the value of the CG bus Status register is 1, it means that the internal circuitry of the CG bus is undergoing resetting, and that the value set in the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), the operating parameters such as (1) enable / disable of each device section SPAi, (2) ROM device type, and (3) data bus width are set in the specified VDP register RGij for each device section (SPA0 to SPAn) that can be defined corresponding to the memory devices that make up the CGROM (SP82).

[0337] 18(a), in this embodiment, the CGROM 55 can be divided into a plurality of areas (device sections), and for example, for each device section (SPA0 to SPAn), the memory device and data bus width can be selected. The memory devices are broadly classified into, for example, (1) the SATA module (AHSI / F) used in this embodiment, (2) memory elements using a parallel I / F (Interface), and (3) memory elements using a sequential I / F, and for each of the broadly classified memory devices, a specific memory device can be selected, and the data bus width, etc. can be specified as desired.

[0338] Next, to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn), predetermined operating parameters are set in predetermined VDP registers RGij (SP83). The operating parameters include setting values ​​that define the operation timing of the chip select signal and other control signals (such as the READ control signal). Furthermore, when a memory device using a sequential I / F format is selected, the output timing of the address latch and the number of read clocks are also specified to realize the operation shown in Figure 19(b).

[0339] Therefore, it is possible to combine different types of memory devices to configure the CGROM 55. However, in this embodiment, the CGROM 55 is configured using only SATA modules, and only the device section (SPA0) is enabled, while the other device sections (SPA1 to SPAn) are disabled.

[0340] In any case, once the setting process of steps SP82 to SP83 is completed, a predetermined value is written to a predetermined VDP register RGij in order to put the setting process into effect (SP84). This is done in consideration of the fact that it takes a predetermined time for the internal circuitry of the CG bus to be able to operate in response to the setting process of steps SP82 to SP83, and while the internal circuitry is operating, the value of the CG bus Status register (see SP80) is 0.

[0341] Therefore, thereafter, the CG bus Status register is repeatedly accessed for READ (SP85), and processing is terminated after confirming that the value of the Status register has returned from 1 to 0 (SP86). Note that regardless of the predetermined number of determinations, if the value of the Status register has not returned from 1 to 0, processing of step SP66 may be terminated. However, in this case, the game processing will begin in a state where the CGROM cannot be accessed normally, and the WDT circuit 58 will then be activated at some point, causing the composite chip 50 to enter an abnormal reset state. In this case, the power-on reset operation will be executed again.

[0342] On the other hand, after the processing of step SP20 in FIG. 18 is executed normally, the internal circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing (SP21).

[0343] Next, after starting a predetermined timer measurement operation for the multifunction timer unit MTU (SP22), permission setting values ​​are written to predetermined operation control registers REG for internal interrupts and internal interrupts to set the interrupt permission state (SP23).

[0344] As a result, various interrupts shown in Figure 18(d) may occur thereafter. Normally, at this timing, the sound processor 27 has completed its initialization sequence, so the end interrupt signal IRQ_SND should have dropped to L level, as shown in Figure 7(c). Therefore, the interrupt processing shown in Figure 18(c) is started, and the performance control CPU 63 initializes the error flag ERR to 1, performs READ access to the address space CS3 (SP30), obtains the value of a predetermined sound register SRG of the sound processor 27, and determines whether the initialization sequence has ended normally (SP31).

[0345] If the initialization sequence does not end normally, the performance control CPU 63 writes a reset command to a predetermined audio register SRG of the audio processor 27 (SP32) and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR determines whether or not to execute the audio processor initialization process (SP26), and error flag ERR=1 is the execution condition for step SP26.

[0346] Meanwhile, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND at H level, and when the initialization sequence is completed, the end interrupt signal IRQ_SND drops to L level, resulting in the process of Figure 18(c) being executed again.

[0347] The above describes an exceptional case where the initialization sequence does not end normally, but normally, following step SP31, the processing of step SP32 is executed, and the performance control CPU 63 returns the termination interrupt signal IRQ_SND from L level to H level by writing a predetermined value to a predetermined sound register SRG (SP34).

[0348] Finally, by writing a predetermined value to a predetermined voice register SRG, READ / WRITE access to all voice registers SRG is permitted (SP35). As a result of this processing, the necessary setting processing can be executed in the subsequent voice processor initialization processing (SP26).

[0349] An example of a Maskable Interrupt corresponding to the interrupt permission setting in step SP23 has been explained above, but a Non-Maskable Interrupt based on the oscillation cessation of oscillator OSC2 can be activated at any timing. As explained above, the operating clock (CPU system clock) of circuits other than the built-in CPU (performance control CPU 63) is generated by multiplying the frequency of the output clock of oscillator OSC2 using a PLL (Phase Locked Loop), and if the oscillation of oscillator OSC2 is halted, normal operation of the VDP circuit 52 thereafter is impossible.

[0350] Meanwhile, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by a PLL, allowing program processing to continue. Furthermore, the interrupt processing program is stored in the internal RAM 59. Therefore, the performance control CPU 63 issues an abnormality notification by sound or lamp (SP28) and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification may be, for example, an audio notification stating, "An abnormality has occurred. Please contact an attendant immediately." The reason for continuing to output the clear signal to the WDT circuit 58 is to avoid an abnormal reset operation. In other words, in the event of a serious abnormality that causes the oscillator OSC1 to stop operating, repeated abnormal reset operations would likely prevent the device from returning to normal.

[0351] 18(b) and 18(c), we will return to Fig. 18(a) for further explanation. In step SP24, necessary areas are write-protected to protect the program area of ​​the external DRAM 54. Next, the clock circuit 38, which is battery-powered when the power is cut off, is checked for normal operation when the power is cut off, and the alarm interrupt is reset just to be sure (SP25).

[0352] Then, on condition that the error flag ERR=1, the necessary setting values ​​are written to the built-in register (voice register SRG) of the voice processor 27 to execute initialization processing (SP26). Note that if the error flag ERR=0, the process waits for a predetermined time until the error flag ERR=1, but if the time limit is exceeded, the process transitions to an infinite loop process to start the WDT circuit 58.

[0353] Next, the power supply control circuit SPY is controlled to prepare for the startup of the display device DS1, and necessary setting values ​​are written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP27). The processing of step SP27 is shown in detail as the processing of steps SP50 to SP57 in FIG.

[0354] Although the above describes an embodiment in which the end interrupt signal IRQ_SND is received from the audio processor, it is also preferable to omit the interrupt processing in Fig. 18(c). Fig. 20 shows a modified embodiment in which a 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

[0355] 20 shows a part of the 1 ms timer interrupt process, and realizes four stages of operation based on the value (0 / 1 / 2 / 3) of the operation management flag FLG, which is initially set to 0. Note that the IRQ_SND output terminal of the audio processor 27 is open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed to the H level.

[0356] In the 1 ms timer interrupt process, first, if it is determined in the process of step SP42 that the operation management flag FLG=0, it is confirmed that the initialization sequence of the audio processor 27 has ended normally (SP43). If it has ended normally, a predetermined value is written to a predetermined audio register SRG to clear the interrupt signal (IRQ_SND) (SP46), and the operation management flag FLG is set to 1 (SP47). The processes of steps SP43 and SP46 are the same as the processes of steps SP31 and SP34 in Figure 18(c).

[0357] On the other hand, if the initialization sequence has not ended normally, a reset command is written to a predetermined voice register SRG, causing the voice processor 27 to start the initialization sequence (SP44), and the operation management flag FLG is reset to zero (SP45). The processing in step SP44 corresponds to the processing in step SP32 in Figure 18(c).

[0358] Normally, the operation management flag FLG becomes 1 after the processing of step SP47, so at the next 1 ms timer interrupt, a predetermined value is written to a predetermined voice register to permit access to all voice registers (SP48), and the operation management flag FLG is set to 2 (SP49). The processing of step SP48 corresponds to the processing of step SP35 in Figure 18(c).

[0359] Next, in the 1 ms timer interrupt with operation management flag FLG=2, as in step SP26 of Figure 18(a), the necessary setting value is written to the built-in register (voice register SRG) of the voice processor 27, initialization processing is performed (SP50), and the operation management flag FLG=3 is set.

[0360] The operation management flag FLG=3 indicates a normal voice control state, and voice control proceeds by setting necessary operation parameters in necessary voice registers SRG (SP52).

[0361] The above describes a method for checking whether the initialization sequence of the audio processor 27 has ended normally by an interrupt process caused by an interrupt signal (IRQ_SND) (SP31 in FIG. 18(c)) and a method for checking by a 1 ms timer interrupt process (SP43 in FIG. 20), but the present invention is not limited to these methods. For example, it is also preferable to determine whether the initialization sequence of the audio processor 27 has ended normally as part of the process of step SP26 in FIG. 18.

[0362] The above explains the overview of the main introduction process (SP20 to SP26 in Figure 18). Below, based on Figures 21 and 22, we will explain the details of the processing of step SP27 (startup preparation processing + initialization processing) and the operation of the main main processing process (SS1 to SS6 and ST4 to ST14).

[0363] As shown in Figure 21, in processing step SP27, the performance control CPU 63 first checks the clock timer TM and confirms that one second has passed since the performance control CPU 63 started operating (timing T1 in Figure 6(d)) while outputting a clear signal to the WDT circuit 58 (SP50). This is to maintain the display device DS1 in a non-operating state until the VDP circuit 52 actually starts operating. Furthermore, because a clear signal is output to the WDT circuit 58, activation of the WDT circuit 58 is reliably prevented, and there is no risk of the initialization processing up to this point being wasted, such as an abnormal reset of the composite chip 50 (this significance is the same in the standby processing below).

[0364] Next, the performance control CPU 63 changes the control signals PS1 and PS2 to the power supply control circuit SPY from L level to H level (SP51). This process corresponds to the operation at timing T2 shown in Figure 6(g) and Figure 6(h), and the control signals PS1 and PS2 are maintained at H level thereafter.

[0365] When the control signal PS1 goes high, the MOS transistor Q1 turns on and the backlight unit BL is supplied with a power supply voltage of 12 V. However, at this timing T2, the BL_EN terminal and the PWM terminal of the driver DVL of the backlight unit BL are both low, so the backlight unit BL does not emit light.

[0366] Furthermore, when the control signal PS2 goes high, the MOS transistor Q4 turns on and the liquid crystal display unit MONI is supplied with the power supply voltage 5. However, at this timing T2, the backlight unit BL is turned off, so there is no risk of an unnatural image being displayed.

[0367] After processing of step SP51 is completed, the performance control CPU 63 next determines the refresh mode based on the setting value of the specified VDP register RGij, sets the refresh period of the built-in VRAM 71 and the initial value of the row address (refresh address), and performs initialization processing of the built-in VRAM 71 (SP52).

[0368] The VRAM 71 of the embodiment is configured as a DRAM (Dynamic Random Access Memory), and the charge stored in the memory cells is gradually lost due to leakage current within the device. Therefore, in this embodiment, for example, a distributed refresh method is adopted in which all rows in the device are refreshed at the refresh period specified in the processing of step SP52, thereby preventing the loss of charge in the memory cells. Therefore, even if there are memory cells in the VRAM 71 that are not accessed for a long time, there is no risk of the data being lost. Note that the refresh mode is not limited to the distributed refresh method, and a concentrated refresh method can also be adopted.

[0369] Next, the necessary setting values ​​are written to the VDP register RGij, the display clock DCK is initialized, and the display circuit 74 is initialized (SP54). Note that this processing is nothing more than an operation for performing a hardware reset on the corresponding internal circuit.

[0370] Next, the control signal STBY to the power supply control circuit SPY is changed from L level to H level (SP56). This process corresponds to the operation at timing T3 shown in FIG. 6(i), and the H level of the control signal STBY is maintained thereafter. At this timing T3, the driver DVL of the backlight unit BL has already been supplied with a power supply voltage of 12V (timing T2), so the driver DVL is in an operable state. However, since the control control signal PWM is still maintained at L level, the backlight unit BL does not emit light.

[0371] Next, the execution of the processing of step SP4 in Fig. 16 and the execution of the processing of step SP54 in Fig. 21 are confirmed by read access to a predetermined VDP register (status register STS) RGij (SP57). Specifically, first, it is confirmed by the status register STS(1) that the display clock set in the processing of step SP4 in Fig. 16 has stabilized.

[0372] Next, the status register STS(2) is used to confirm that initialization of the display circuit has been completed successfully in response to the processing in step SP54. Subsequently, for the LVDS circuit 80 for which dual link setting was established in the processing in step SP45, the status register STS(3) is used to confirm that initialization of each section LVDS1 / LVDS2 has been completed successfully. Once it is confirmed that all initializations have been completed successfully, the main installation processing ends (SP57).

[0373] Next, the subsequent processing will be described for an embodiment in which the preloader does not function. As shown in Figures 21 to 22(a), the main body processing is divided into VDP initial setting processing (SS1 to SS6) that is executed after the CPU is reset, and thereafter, regular processing (ST4 to ST14) that is repeatedly executed every 1 / 30 seconds.

[0374] The steady-state processing (ST4 to ST14) is initiated when the interrupt counter VCNT reaches VCNT≧2 (ST4), so the operating period δ of the steady-state processing is 1 / 30 seconds. This operating period δ is none other than the actual operating period δ of the VDP circuit 52, which operates intermittently under the control of the performance control CPU 63. The reason for setting the judgment condition as VCNT≧2 is to take into consideration the possibility that the steady-state processing (ST4 to ST14) may be abnormally prolonged and the timing of VCNT=2 may be missed, but it is also designed to prevent a situation where VCNT=3 occurs.

[0375] Based on the above, the VDP initial setting process will now be explained. As shown in Figure 21, in this embodiment, in the VDP initial setting process, the built-in VRAM 71 with a storage capacity of 48 MB is divided into an ACC area (a) with appropriate storage capacity, a page area (b), and a free area (c) (SS1). Specifically, for the ACC area (a1, a2) and the page area (b), the start addresses and total required data sizes of each area are set in a predetermined index table register RGij (SS1). Then, the reserved ACC area (a1, a2) and the remaining area not included in the page area (b) become the free area (c).

[0376] Here, the area start addresses of the first and second ACC areas (a1, a2) and the page area (b) must each have the lowest 11 bits set to 0, but can be arbitrarily selected in 2048-bit units (selection in increments of 256 addresses, with 1 address = 1 byte). The total data size can also be arbitrarily selected within the range of an integer multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

[0377] In this embodiment, certain conditions are imposed on the area settings of the ACC area (a1, a2) and the page area (b). This is to eliminate as much wasted area as possible from the built-in VRAM 71, which has a limited memory capacity, while also facilitating the internal operation of the VDP circuit 52. In other words, if the memory capacity of the built-in VRAM 71 is increased indiscriminately, there are concerns that manufacturing costs will rise and the chip area will become larger. On the other hand, if free area settings that completely eliminate wasted area are allowed, internal processing will become more complicated and it will be difficult to shorten the processing time for VRAM access. Note that certain restrictions are imposed on the allocation of index space, which will be explained below, for the same reason.

[0378] Continuing the explanation based on the above, following the processing of step SS1, the necessary index space IDXi is reserved for the page area (b) and the arbitrary area (c) (SS2). Specifically, the necessary information is set in a predetermined index table register RGij to reserve the index space IDXi for each of the areas (b) and (c).

[0379] For example, when an index space IDXi is set in the page area (b), multiple information (vertical and horizontal multiple information for the unit space) of an arbitrary horizontal size Hx and an arbitrary vertical size Wx corresponding to an arbitrary index number i is set in a predetermined index table register RGij (SS2).

[0380] As explained earlier, the index space IDXi of the page area (b) has a unit space of 128 horizontal lines x 128 vertical lines, and one pixel is specified by 32 bits of information, so based on the settings of the horizontal size Hx and vertical size Wx, an index space IDXi with a data size (bit length) = 32 x 128 x Hx x 128 x Wx is secured. The start address (space start address) of the index space IDXi of the page area (b) is automatically assigned internally.

[0381] Furthermore, when an index space IDXi is provided in the arbitrary area (c), an arbitrary start address (space start address) STx and multiple information of an arbitrary horizontal size Hx are set in a predetermined index table register RGij corresponding to an arbitrary index number i (SS2). Here, "arbitrary" means that predetermined conditions are assumed, and the horizontal size Hx is arbitrarily determined in 256-bit units, and the lower 11 bits of the start address STx are 0, so that it is arbitrarily determined in 2048-bit units. As explained above, the vertical size of the arbitrary area is fixed to 2048 lines, so that an index space with a data size (bit length) = 2048 × Hx is secured after the start address STx based on the setting of the horizontal size Hx.

[0382] Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces each having a horizontal size of 1280 x vertical lines of 2048 are specified with an index number and set in one or more predetermined index table registers RGij, and as the frame buffer FBb of the sub-display device DS2, a pair of index spaces each having a horizontal size of 480 x vertical lines of 2048 are specified with an index number and set in one or more predetermined index table registers RGij. Note that if the number of horizontal pixels of the display device does not match an integral multiple of 256 bits / 32 bits, the horizontal size of each index space is set to a value that is larger than the number of horizontal pixels of the display device and is an integral multiple of 256 / 32=8, thereby minimizing the generation of wasted memory area.

[0383] As described above, the required number of index spaces IDXi are generated by setting the required size information and address information for the page area (b) and the arbitrary area (c) in the predetermined index table register RGij (SS2). Corresponding to this setting process (SS2), an index table IDXTBL that specifies the address information and size information for each index space IDXi is automatically constructed. As shown in FIG. 12(a), the index table IDXTBL stores the start address of each index space IDXi along with other required information, and is referenced when transferring data within the VDP circuit 52 or when acquiring data from an external storage resource (see FIG. 13). Since the index space IDXi for the AAC area (a) is automatically generated and automatically deleted when needed, the setting process of step SS2 is unnecessary.

[0384] As shown in Figures 12(a) and 12(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), each of which is assigned an index number. In an embodiment that does not use a Z-buffer, a pair of index spaces 255 and 254, assigned with index numbers 255 and 254, are secured as frame buffer FBa. Furthermore, a pair of index spaces 252 and 251, assigned with index numbers 252 and 251, are secured as frame buffer FBb. In this embodiment, a work area (index space 0) with index number 0 is also secured in the arbitrary area (c).

[0385] In this embodiment, the page area (a) is allocated a required number of index spaces IDXi to serve as decode areas for IP stream video, and index numbers i are assigned to each. However, initially, only the index space IDX0 for the background video (IP stream video) is allocated. Then, depending on the needs of the image presentation (variation presentation or preview presentation), the index space IDXj in the page area (a) is increased based on the setting process for the index table register RGij or the instruction command of the display list DL, and then, when it is no longer needed, the index space IDXj is released. That is, FIG. 12(a) shows the index table IDXTBL during normal operation.

[0386] The index space of the ACC area (a) is automatically generated when necessary based on the instruction command written in the display list DL, and the starting address of the automatically generated index space IDXj and other necessary information are automatically set in the index table IDXTBL. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

[0387] The above operation of reserving index space is realized mainly by the setting operation to the index table register RGij included in the control register group 70, but following the processing of steps SS1 to SS2, the necessary setting operation (SS3) is performed on other VDP registers RGij, thereby enabling steady operation (intermittent operation) of the VDP circuit 52 shown in Figures 30 to 31.

[0388] In this embodiment, the necessary setting process (SS3) includes at least steps SS30 to SS39. Note that steps SS30 to SS37 do not limit the order of the processes, and can be executed in any order regardless of the order described below.

[0389] In this embodiment, first, predetermined operating parameters (number of lines and number of pixels) are written to a predetermined display register RGij that defines the operation of the display circuit 74, thereby setting the number of display lines and horizontal pixels for each display device DS1, SD2 (SS30). In this embodiment, the number of horizontal pixels for the main display device DS1 is 1280 dots, and the number of display lines is 1024 rows. The number of horizontal pixels for the sub-display device DS2 is 480 dots, and the number of display lines is 80 rows. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the effective data area (the dashed line area in Figure 22(e)) to which the display circuits 74A, 74B should access for READ are specified in each frame buffer FBa, FBb.

[0390] Next, the number of cycles THc in the horizontal period TH and the horizontal waiting time WTh are set for each display device DS1, SD2 by writing predetermined operating parameters (THc, WTh) to a predetermined display register RGij that defines the operation of the display circuit 74 (SS31). Also, the number of lines TVl in the vertical period TV and the vertical waiting time WTv are set for each display device DS1, SD2 by writing predetermined operating parameters (TVl, WTv) to the predetermined display register RGij (SS32).

[0391] As explained with reference to FIG. 15, the main display device DS1 is set with a horizontal cycle count THc of 1662 and a vertical cycle count TVl of 1083. The horizontal wait time WTh is set to 382 and a vertical wait time WTv of 59 lines. Meanwhile, the sub-display device DS2 is set with a horizontal cycle count THc of 519 and a vertical cycle count TVl of 867, with a horizontal wait time WTh of 39 and a vertical wait time WTv of 67 lines. Note that THc - WTh = 519 - 39 = 480 and TVl - WTv = 867 - 67 = 800, which matches the pixel count of the sub-display device (480 horizontal x 800 vertical).

[0392] In any case, the frequency F of the dot clock DCK is dot(=108MHz) is determined, and the number of cycles THc (=1662) of the horizontal period TH and the number of lines TVl (=1083) of the vertical period TV are determined for the main display device DS1 by the processing of steps SS30 to SS32. As a result, the display period of one frame is determined as follows: THc×TVl / F dot Specifically, the display period of one frame is determined to be 1083×1662 / 108MHz=16.667mS, and the frame rate FR is determined to be 1 / 60 seconds.

[0393] For the sub-display device DS2, for example, the frequency F of the dot clock DCK is dot = 27 MHz, the number of cycles in the horizontal period THc = 519, and the number of lines in the vertical period TVl = 867, it is determined that 519 x 867 / 27 MHz = 16.66 mS.

[0394] Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS33). Also, for the sub-display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS34).

[0395] As explained above, the main display device DS1 does not require the horizontal synchronizing signal HS or the vertical synchronizing signal VS, and therefore the above processing (SS33 to SS34) for the main display device DS1 is not required. However, if the setting processing of steps SS33 to SS34 is omitted, the default values ​​set at the time of power reset will function, and in reality, the display device 74A will also output the horizontal synchronizing signal HS and the vertical synchronizing signal VS.

[0396] According to the default values, for example, a horizontal synchronization signal HS with a pulse width of 40 clocks is output, which becomes active 16 clocks after the V blank start timing, and a vertical synchronization signal VS with a pulse width of 3 lines is output, which becomes active in synchronization with the V blank start timing.

[0397] This operation means that a horizontal synchronization signal HS with a horizontal front porch HPv=16, pulse width PWh=40, and horizontal back porch BPv=326 is output to the main display device DS1 during the horizontal wait time WTh=382 clocks, and a vertical synchronization signal VS with a vertical front porch HPv=0, pulse width PWv=3, and vertical back porch BPv=56 is output during the vertical wait time WTv=59 lines. However, as mentioned above, these synchronization signals are ignored by the main display device.

[0398] In order to prevent the synchronization signals HS and VS based on the default values ​​from being output, a configuration may be adopted in which a predetermined system control register RGij is set so that the horizontal synchronization signal HS and the vertical synchronization signal VS are not output. When such a mask setting is provided, the output terminal of the horizontal synchronization signal HS and the output terminal of the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

[0399] Next, a predetermined system control register RGij is set to allow V blank interrupts (SS35). As a result, in this embodiment, a VBLANK start interrupt occurs in response to the V blank start timing, which occurs every 16.667 mS (1 / 60 seconds), as shown in Figure 22(c). This V blank interrupt timing determines the start timing of the regular processing (ST5 to ST14) of the performance control CPU 63, and also indicates the start timing of the display period for the display circuits 74A and 74B (the end timing of the previous display period).

[0400] Next, predetermined operating parameters (address values) are written to predetermined display registers RGij to specify the vertical and horizontal display start positions for each frame buffer FBa and FBb (SS36). As a result, the effective data areas whose vertical and horizontal dimensions were specified in step SS34 are determined on the frame buffers FBa and FBb. Here, the vertical and horizontal display start positions are relative address values ​​in each index space, and in the example shown in Figure 22(e), the display start position is (0,0).

[0401] Here, the "display area" refers to the index space (frame buffers FBa and FBb) from which the display circuits 74A and 74B should read image data to drive the display devices DS1 and DS2, and refers to either of the double buffers in the frame buffers FBa and FBb, which each have a double buffer structure. However, the display circuits 74A and 74B actually read image data only from the "valid data area" specified in steps SS30 and SS36 in display area (0) or display area (1).

[0402] Next, the display register RGij(DSPAINDEX) for the display circuit 74A that drives the main display device DS1 and the display register RGij(DSPBINDEX) for the display circuit 74B that drives the sub-display device DS2 are set to "display area (0)" and "display area (1)", respectively, to define each display area (SS37).

[0403] Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of index number 254 in the VRAM arbitrary area (c) is defined as the "display area (0)", and the index space 255 of index number 255 in the VRAM arbitrary area (c) is defined as the "display area (1)" (SS37).

[0404] Furthermore, for frame buffer FBb, index space 251 of index number 251 in VRAM arbitrary area (c) is designated as the "display area (0)," and index space 252 of index number 252 in VRAM arbitrary area (c) is designated as the "display area (1)" (SS37). Defining the "display area" in the initialization process (SS3) is not particularly limited, and the index space (display area) that the display circuit 74 should access to read image data may be toggled every operating cycle δ. It is also preferable to clear the display areas (0) and (1) of frame buffers FBa and FBb to zero at this timing, in which case unnatural images will not be displayed on the display device.

[0405] In this embodiment, once the initial setting including the above processes (SS30 to SS37) is completed, a predetermined prohibition value is set in the first type prohibition setting register RGij so that the setting value in the predetermined system control register RGij is not subsequently changed due to the influence of noise or the like (first prohibition setting SS38).

[0406] Here, the setting values ​​that are prohibited from being written in the future include (1) setting values ​​related to the display clock DCK of the display devices DS1 and DS2, (2) setting values ​​related to the LVDS sampling clock, (3) setting values ​​related to the selection operation of the output selection circuit 79, and (4) the synchronization relationship between the multiple display devices DS1 and DS2 (the dependency of the display circuit 74B on the operation cycle of the display circuit 74A). Note that although software processing exists to cancel the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it as needed.

[0407] Next, a predetermined inhibit value is set in the second type inhibit setting register RGij, thereby inhibiting writing to the VDP register RGij of the initial setting system (second inhibit setting SS39). Here, the registers to be inhibited include the VDP register RGij related to step SP4 and steps SS30 to SS37.

[0408] On the other hand, by setting a predetermined prohibition value in the third type prohibition setting register RGij, it is also possible to set prohibitions on a large number of VDP registers, including the VDP registers related to the setting processing of steps SS1 to SS3 (third prohibition setting). However, this is not used as a general rule in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be released at will by writing a release value to the predetermined release register RGij, and it is also possible to change the set value during normal operation.

[0409] Once the above processing is completed, in step SP52 of FIG. 21, the status register (4) is referenced to confirm that the operation of the built-in VRAM 71, which specifies the refresh cycle, has been stabilized (that is, the initialization has been completed successfully) (SS40).

[0410] Through the above processing, it is confirmed based on the values ​​of the status registers (1) to (4) that the internal VRAM 71, the display circuit 74, and the LVDS circuit 30 have all completed the initialization processing normally. Next, a specified value is written to the specified display register RGij (DSPACTL / DSPBCTL) to start the operation of the display circuits 74A and 74B (SS4a), and a specified value is written to the specified system control register RGij (SYSDSPLVDS1MD / SYSDSPLVDS2MD) to output the output data from the display circuit 74A from the LVDS circuit 80 (LVDS1 / LVDS2) (SS4b).

[0411] This operation is none other than the processing at timing T4 in Figure 6(e), and in this embodiment, the program is designed to execute the processing of steps SS4a and SS4b within a predetermined time τ (e.g., 20 mS) from timing T2. Then, in response to the start of operation of the display circuits 74A, 74B and the LVDS circuit 80 (timing T4), the clock timer TM is restarted from zero (SS4c). Note that the processing procedure of steps SS4a to SS4b is not necessarily limited. Even if the processing of steps SS4a to SS4b were executed in reverse order, useless image data would only be output from the LVDS circuit 80 for a moment, and there would be no problem because the backlight unit BL would be turned off.

[0412] In any case, in this embodiment, in response to the processing of steps SS4a to SS4b described above, the display circuit 74 enters a V blank start state every 1 / 60 seconds, and the LVDS circuit (LVDS1 / LVDS2) 80 operates, thereby repeating the display operation shown in Fig. 15. In Fig. 15, the start timing and end timing of the display operation indicated by circles indicate the V blank start timing.

[0413] Based on this V-blank start timing, a horizontal reference point TH0 (= horizontal reference time) and a vertical reference point (= vertical reference time) TV0 for the operation of the display circuit 74 are defined, and the display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal waiting time WTh has elapsed from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until the vertical waiting time WTv has elapsed from the vertical reference point TV0.

[0414] Furthermore, because the display circuit 74B operates in synchronization with the display device 74A (SP4 in FIG. 16), the start and end timings of the display operation for the sub-display device DS2 are also the same as those for the main display device DS1. Therefore, by setting the frame period (519×867 / 27) for the sub-display device DS2 shorter than the frame period (1083×1662 / 108) for the sub-display device DS2, the update process for the sub-display device DS2 is set to be completed when the V blank starts.

[0415] After the processing of step SS4, which has the above significance, is completed, the process next waits for 300 mS based on the clock timer TM (SS5), and then the control signal PWM to the power supply control circuit SPY transitions from L level to H level (SS6). As a result, the backlight unit BL enters a light-emitting state, and the liquid crystal display unit MONI, which has started operating before, begins display operation based on the image data received from the display circuit 74A. As explained above, since the display list has not been issued at this timing, the contents of the VRAM are displayed as is. Therefore, it is preferable to leave the processing of steps SS5 to SS6 to timer interrupt processing (see dashed lines). If such a configuration is adopted, the display list DL has already been issued at timing T5, and the specified initial screen will be displayed on the display device DS1.

[0416] Next, the remaining part of the main main processing, the steady-state processing that is repeatedly executed at predetermined intervals, will be explained based on Figure 22. As shown in Figure 22, the operation of the performance control CPU 63 is composed of main control processing (a), timer interrupt processing (b) that starts every 1 ms, reception interrupt processing (not shown) that starts in response to control command CMD, VBLANK interrupt processing (c) that starts in response to a VBLANK signal that occurs at the start timing of the V blank (vertical blanking period) of the display device DS1, and drawing abnormality interrupt processing (d) that occurs when operation freezes or an irrational instruction command is detected. Note that explanation of the 20 μS interrupt processing will be omitted.

[0417] In the reception interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined reception buffer so that it can be referenced in the main control process (ST13), and the process ends. Also, in the VBLANK interrupt process (FIG. 22(b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start of the main control process, the operation start timing of 1 / 30 seconds is grasped based on the value of the interrupt counter VCNT, and the interrupt counter VCNT is cleared to zero (ST4).

[0418] On the other hand, the timer interrupt process includes a process (ST18) for acquiring an origin sensor signal and the like to progress the motor performance, and a lamp performance progress process (ST19), as shown in Figure 22 (b). The lamp performance and motor performance are controlled based on a performance scenario that centrally manages all performance operations, and when the performance start time managed by the performance counter EN is reached, the motor drive table and lamp drive table are identified in the performance scenario update process (ST11).

[0419] Then, the motor effect proceeds based on the identified motor drive table, and the lamp effect proceeds based on the identified motor drive table. As explained above, there is also an embodiment in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect proceeds every 1 mS, but the lamp effect proceeds at appropriate timings longer than 1 mS.

[0420] On the other hand, as shown in FIG. 22(d), in the drawing abnormality interrupt processing, the status register RGij indicating the operating state of the drawing circuit 76 is accessed for READ to identify the cause of the interrupt. Specifically, it is identified whether the drawing abnormality interrupt is (1) due to the detection of an abnormal instruction command (bit corruption) or (2) due to an operation abnormality (freeze) of the drawing circuit 76 (ST16a). If the drawing abnormality interrupt is due to the detection of an abnormal instruction command, a predetermined value is written to a predetermined system control register RGij to initialize the drawing circuit 76 (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in FIG. 7(b).

[0421] Next, after confirming the normal completion of the individual reset operation with a predetermined status register RGij, a group of operating parameters that define the operation of the drawing circuit 76 are reset to the predetermined drawing register RGij, and the process ends (ST16c). Then, after adjusting the stack area that stores the return address (release process that erases the return address after interrupt processing), the process proceeds to step ST13 (ST16c).

[0422] On the other hand, in the case of a drawing abnormality interrupt based on an operational abnormality of the drawing circuit 76, the process shifts to an infinite loop process (ST16d), which activates the WDT circuit 58 and resets the entire combined chip 50. If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 7(b)). In this case, after confirming that the reset operation of the VDP circuit 52 has been completed successfully, the process shifts to the process of steps ST4 and ST13. In order to avoid missing the control command CMD as much as possible, it is better to shift from step ST4 to step ST13, including in other cases.

[0423] When the entire composite chip 50 is reset, the previous effects disappear and the effect control returns completely to the initial state (power-on state), but when only the VDP circuit 52 is reset, the series of effect control can be continued, although there is a predetermined waiting time until the reset operation of the VDP circuit 52 is completed. Note that the effect control CPU 63 controls the image effect, lamp effect, and sound effect in a unified manner, so there is no unnatural gap between the effects.

[0424] The initial setting process of steps SS1 to SS3 described above is executed based on the initial value setting table SETTABLE (see Figure 36) which associates the register address value of the VDP register RGij with the setting value for that register RGij. Having described the initial setting process above, before describing the steady-state process (ST4 to ST14), we will now provide a brief description of the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the performance control CPU 63 based on Figures 30(a) and 31(b).

[0425] 30(a), the display list DLi completed by the performance control CPU 63 is issued to the drawing circuit 76 in its operation cycle (T1), and the drawing circuit 76 completes image data in frame buffers FBa and FBb through drawing operations based on the display list DLi. The completed image data in frame buffers FBa and FBb is then output by the display circuit 74 to display devices DS1 and DS2 in the next operation cycle T1+δ, and the display screen perceived by the player is created based on the subsequent drawing operations of display devices DS1 and DS2.

[0426] 31(a), the display list DLi completed by the performance control CPU 63 is issued to the preloader 73 in its operation cycle (T1), and the preloader 73 interprets the display list DLi and performs the necessary prefetching operation, while rewriting a portion of the display list DLi to complete the rewrite list DL'. The prefetched CG data and the rewrite list DL' are stored in appropriate locations in the DRAM 54.

[0427] Next, in the next operation cycle (T1+δ), the drawing circuit 76 obtains the rewrite list DL' from the DRAM 54 and completes the image data in the frame buffers FBa and FBb by performing drawing operations based on the rewrite list DL'. Then, in the next operation cycle (T1+2δ), the display circuit 74 outputs the completed image data in the frame buffers FBa and FBb to the display devices DS1 and DS2, and the display screen perceived by the player is created based on the subsequent drawing operations of the display devices DS1 and DS2.

[0428] The above has provided a brief explanation of the intermittent operation of the VDP circuit 52. In order to realize the operation shown in Figures 30 to 31, the performance control CPU 63, after initial processing (SS1 to SS3), repeatedly refers to the value of the interrupt counter VCNT and waits for the operation start timing to be reached, and when the operation start timing (the start timing of every other V blank) is reached, it clears the interrupt counter VCNT to zero (ST4).

[0429] Thereafter, steady operation is started. In this embodiment, first, it is determined whether or not the operation start conditions for starting steady operation are met (ST5). The timing for this determination is the timings T1, T1+δ, T1+2δ, ... shown in Figures 30 and 31, that is, the start timing of the vertical blanking period (VBLANK) of the display device DS1. The display timing of the display device DS2 is set during the initial setting (ST3) so that it is subordinate to the display timing of the display device DS1.

[0430] The operation start condition determined at the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is utilized. Therefore, we first describe an embodiment (FIG. 22) in which the preloader 73 is not utilized. In this case, the circuit configuration and program are designed so that the internal operation of the VDP proceeds as shown in the timing chart of FIG. 30(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should complete the drawing operation within that operation cycle (T1 to T1+δ). However, it cannot be said that there are no cases in which the drawing operation is not completed within that operation cycle (T1+2δ to T1+3δ), as in the case of the display list DL3 completed in the operation cycle (T1+2δ) of FIG. 30(a). Furthermore, there is a possibility that an underrun error occurs in the display circuit 74, in which display data generation is delayed for the display timing.

[0431] The determination process of step ST5 takes such a situation into consideration, and the performance control CPU 63 accesses a status register RGij (one of the control registers 70) that indicates the operating state of the drawing circuit 76, and determines at the timing of step ST5 whether the drawing circuit 76 has completed the necessary operations and whether an underrun abnormality exists. The presence or absence of an underrun abnormality is determined based on the underrun counters URCNTa to URCNTc. Also, in an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in Figure 30(a), the status information of the drawing register related to the drawing circuit 76 is read and accessed to confirm that the drawing operation based on the display list DL1 has ended.

[0432] If the operation start conditions are not met (abnormal / non-conformance), the abnormality flag ER, which counts the number of abnormalities, is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER, along with other serious abnormality flags ABN, is determined in the processing of steps ST9 and ST10, and assuming that the serious abnormality flag ABN is in the reset state, if the number of consecutive abnormalities is not high (ER≦2), the performance command analysis processing is executed (ST13), just as in the normal case.

[0433] Similarly, in the case of an Underrun abnormality, steps ST6 to ST8 are skipped. Then, a predetermined clear value is written to a predetermined system control register RGij, thereby initializing the display clock DCK (frequency) and the display circuit 74 (ST10c). After confirming that this initialization process has ended normally, the values ​​of a group of system control registers RGij that define the frequency of the display clock DCK and the operation of the display circuit 74 are reset to their predetermined values ​​(ST10c), and then the performance command analysis process is executed (ST13).

[0434] In the performance command analysis process (ST13), it is determined whether or not a control command CMD has been received from the main control board 21. If a control command CMD has been received, the control command CMD is analyzed and the necessary processing is performed (ST13). Here, the necessary processing includes a process for preparing to start a new variable performance based on the control command CMD that instructs the start of a variable performance, and a process for starting an error notification based on the control command CMD that indicates the occurrence of an error. Next, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

[0435] The above describes the case where there is a minor underrun error or the operation start conditions are not met and the error flag ER is ER≦2. In such cases, the process of toggling the display area read by the display circuit 74 (ST6) and the process of creating a display list (ST7) are skipped during that operation cycle, and the rendering scenario does not proceed (see ST8 to ST12). This is to prevent the output of image data from the frame buffers FBa and FBb in an incomplete state. Therefore, for example, during the operation cycle (T1+3δ) in Figure 30(a), the image rendering does not proceed, and a frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

[0436] To avoid dropping frames, it is possible to wait until the operation start condition is met. However, since there are many control processes (ST6 to ST12) that the performance control CPU 63 must execute, and it is necessary to secure processing time for each of them, in this embodiment, frame dropping occurs when the operation start condition is not met.

[0437] However, even if a frame drop occurs, the progress of the image effect is delayed by only about 1 / 30 to 2 / 30 of a second compared to the lamp effect and motor effect that proceed through interrupt processing (Fig. 22(b)), and the player will not notice this. Moreover, when a frame drop occurs, the effect scenario processing (ST11) including the update processing of the effect counter EN and the sound progress processing (ST12) are also skipped, so there is no risk of the start timing of the image effect, sound effect, lamp effect, motor effect, etc. being shifted in the reach effect, preview effect, or bonus effect that starts thereafter.

[0438] In other words, the performance scenario centrally manages the start timing of image performance, sound performance, lamp performance, and motor performance, as well as the performance content to be executed thereafter, and the start timing is controlled by a performance counter EN that is updated only under normal conditions, so that various performances will not be out of synchronization. For example, if there is a performance action that combines the sound of an explosion, an explosion image, the movement of a role-playing device, and a lamp flashing action, each of the above performance actions will start correctly synchronized even after a frame drop occurs.

[0439] The above has been explained for relatively minor abnormalities, but if the serious abnormality flag ABN is set, if there are many consecutive abnormalities (ER>2), or if an Underrun abnormality occurs repeatedly, an infinite loop state is entered after the judgment of step ST10 (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, and the composite chip 50 including the performance control CPU 63 is reset due to an abnormality. After that, the initial processing (SS1 to SS3) is re-executed, and it is expected that the root cause of the abnormal situation will be resolved.

[0440] This reset operation is performed by activating the WDT circuit 58, so the entire composite chip 50, including the CPU circuit 51, is reset (FIG. 7(b)). Therefore, in order to avoid resetting the CPU circuit 51, it is also preferable for the performance control CPU 63 to output a predetermined keyword string (for example, three 1-byte data items) to the pattern check circuit CHK and output a reset signal RST to the VDP circuit 52 (see ST100 in FIG. 36). In this case, after confirming that the reset operation of the VDP circuit 52 has been completed successfully (ST101), the process will proceed to steps ST4 and ST13.

[0441] In any case, in this abnormality, the sound circuit SND is also reset, so the image effect, sound effect, lamp effect, and motor effect will all return to their initial state. However, these reset operations have no effect on the main control unit 21 or the payout control unit 25, so there is no risk of the big win state disappearing or the prize balls disappearing.

[0442] The above describes abnormal situations, but in reality, even minor abnormalities rarely occur, and after the processing of step ST5, the "display area" of the frame buffers FBa and FBb that store the image data to be read by the display circuits 74A and 74B is toggled (ST6) based on the settings of the predetermined display registers RGij (DSPACTL / DSPBCTL). As explained above, "display area (0)" and "display area (1)" are defined in advance in the initialization processing (ST3), so in the processing of step ST6, it is determined whether the "display area" for the current frame buffers FBa and FBb is display area (0) or display area (1).

[0443] By executing step ST6, the display circuit 74A alternately reads image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ to drive the display device DS1. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) for each operation cycle δ to drive the sub-display device DS2. As explained above, the actual READ access by the display circuit 74 is limited to the valid data area in the display area (0) / display area (1).

[0444] In any case, in this embodiment, the "display area" switches for each operation cycle, so the display circuits 74A and 74B start output processing to the display devices DS1 and DS2 for the image data completed by the drawing circuit 76 in the immediately preceding operation cycle. However, since the processing of step ST5 starts at the start of the vertical blanking interval (V blank) of the main display device DS1, the output processing of the image data actually starts after the vertical blanking interval has ended. In Figure 30(a), the arrows shown in the display circuit column indicate the operation cycle of this output processing.

[0445] After the processing of step ST6 having the above significance is completed, the performance control CPU 63 then completes a display list DL that specifies the image data that the display circuit 74 should output to the display device in the next operating cycle (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) in RAM 59 is secured, and the display list DL is completed there (see FIG. 13).

[0446] The display list DL is configured by listing a series of instruction commands in an appropriate order and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands including the EODL command are limited to only instruction commands whose command length is an integer multiple of N (N>0) of 32 bits. As explained above, instruction commands consisting of an integer multiple of N of 32 bits may also include a don't care bit.

[0447] As described above, since the display list DL in this embodiment is composed only of instruction commands whose command length is an integer multiple of N (N>0) of 32 bits, the data volume value (total data amount) of the entire display list DL is always an integer multiple of the minimum unit of the command length (32 bits = 4 bytes). Furthermore, in this embodiment, taking into account the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data amount Dmin and also an integer multiple of the minimum unit of the instruction command (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to be either 256 bytes, 512 bytes, etc.

[0448] Here, it would be preferable to adjust the value to 256 bytes or 512 bytes as appropriate depending on the complexity of the presentation content, but in this embodiment, since there are two display devices and the sub-display device DS2 does not execute very complex image presentations, the data volume value of the display list DL is always adjusted to 256 bytes.

[0449] However, this method is not limited to this, and in the case of a gaming machine with three or more display devices or a gaming machine that executes complex image effects including the sub-display device DS2, the data volume value is adjusted to 512 bytes or 768 bytes. Also, it is preferable to adjust the data volume value of the display list DL to 256 bytes during normal effects, and to adjust the data volume value of the display list DL to 512 bytes or 768 bytes only when executing special effects.

[0450] However, in this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. Possible adjustment methods include a simple method (A) in which a 32-bit EODL command is followed by a 32-bit NOP (No Operation) command to fill in the missing area, or a standard method (B) in which the missing area is filled with a 32-bit NOP command and then a 32-bit EODL command is written at the end. A non-adjustment method (C) is also possible in which the data volume value (total data amount) of the display list DL is terminated with an EODL command without any adjustment, and dummy data is additionally transferred during operation of the data transfer circuit 72 to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

[0451] Here, when the standard method (B) is adopted, the command counter CNT is initially set to a specified value (64-1 corresponding to 256 bytes), and the command counter CNT is appropriately decremented each time a significant instruction command is written to the DL buffer area BUF. After a series of significant instruction commands have been written, NOP commands are written until the command counter CNT reaches zero, and finally an EODL command is written. In this embodiment, the instruction commands are limited to those whose command length is an integer multiple of 32 bits (N>0), so the above process is easy, and the decrement process of the command counter CNT corresponds to the integer N.

[0452] On the other hand, when the simple method (A) is adopted, it is sufficient to first fill the entire list buffer area (DL buffer BUF) with NOP commands when creating the display list DL, and so at first glance it appears to be superior to the standard method (B). Furthermore, from the viewpoint of simplicity, the no-adjustment method (C) also appears to be superior. However, this embodiment basically adopts the standard method (B), and adjusts the actual amount of data from the beginning of the display list DL to the EODL command, i.e., the amount of data up to the EODL command, to always be an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

[0453] This is because an embodiment that utilizes the preloader 73 is taken into consideration, and if the simple method (A) or the adjustment-free method (C) is adopted, the actual data amount of the display list DL up to the EODL command will be a random value, causing problems when the rewrite list DL' rewritten by the preloader 73 is transferred to the DRAM 54 and when the rewrite list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that when the rewrite list DL' is transferred to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when the rewrite list DL' is transferred to the drawing circuit 76, the ChB control circuit 72b functions (see FIG. 28). In either case, however, only the rewrite list DL' up to the EODL command is transferred.

[0454] The advantages of the standard method (B) of adjusting the data volume value of the display list DL have been explained above, but in an embodiment that does not use the preloader 73, the issued display list DL is simply processed by the drawing circuit 76, so there is no prohibition on using the simple method (A) or the adjustment-free method (C).

[0455] However, in the following explanation, regardless of whether the preloader 73 is used or not, the display list DL will be described in detail with reference to FIG. 23, on the assumption that the standard method (B) is adopted in principle.

[0456] Although not particularly limited, in this embodiment, the display list DL first contains a sequence of instruction commands (L11 to L16) related to the main display device DS1, and then contains a sequence of instruction commands (L17 to L20) related to the sub-display device DS2. Furthermore, the standard method (B) is employed to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that Figure 23 also essentially shows the procedure by which the performance control CPU 63 writes instruction commands into the list buffer area of ​​RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

[0457] As shown in Figure 23, an environment setting command (SETDAVR) is written at the beginning of the display list DL to specify the upper left base address (X, Y) in the index space IDX for the frame buffer FBa of the display device DS1 (L11). As explained with reference to Figure 12(a), in this embodiment, a pair of frame buffers FBa is reserved in the arbitrary area (c) for the display device DS1. Normally, the base address (X, Y) is set to (0, 0) corresponding to the valid data area for the display circuit 74, and the frame buffer FBa is used by the drawing circuit 76 from its beginning.

[0458] In Figure 12(c), the actual drawing area on the lower left is labeled L11, which means that the instruction command L11 has specified that the actual drawing area on frame buffer FBa begins at the base address (0,0) of frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies this actual drawing area have not yet been determined, and will be determined by instruction command (SETINDEX) L13, which will be described later. Note that instruction command L11 also specifies whether or not to use the Z-buffer.

[0459] Next, the environment setting command (SETDAVF) is used to set the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) in the virtual drawing space, thereby defining a drawing area with dimensions W x H (L12). Here, the virtual drawing space is a virtual two-dimensional space with an X dimension of ±8192 and a Y dimension of ±8192, which can be drawn using drawing command commands (such as the SPRITE command) (see Figure 12(c)).

[0460] This instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing content is actually reflected on the display device DS1, and the other non-drawing area. Also, the instruction command L12 (SETDAVF) associates the actual drawing area, whose start position (base address) is specified by the instruction command L11, with the drawing area in the virtual drawing space.

[0461] In other words, the instruction command L12 defines an actual drawing area (W x H) starting from the base address in the frame buffer FBa (for which the index space is undefined) that corresponds to the drawing area in the virtual drawing space. Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area or actual drawing area is defined to have the same dimensions as the effective data area (Figure 22(e)) for the display circuit 74.

[0462] After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing content drawn in the virtual drawing space that is included in the drawing area is reflected in the actual drawing area of ​​the frame buffer FBa. Therefore, drawing content that extends beyond the drawing area or that is in the area marked "working area" in Figure 12(c) is not reflected in the frame buffer as is. Note that when a working area is allocated in the virtual drawing space, the non-drawing area of ​​the virtual drawing space is used.

[0463] Next, in this operation cycle, the drawing circuit 76 specifies where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, the index space IDX that will be the "write area" for the drawing content based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a texture setting command, specifies (1) that the frame buffer FBa is allocated in an arbitrary area, and (2) that the index space IDX that will be the "write area" N An index number N on an arbitrary region of the image is identified.

[0464] When N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically the index space IDX in the frame buffer FBa of the double buffer structure. 255 It is thus defined as:

[0465] In this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 12(a)), and either one is designated by toggling (L13). Note that this index number is the index number of the display area other than (0) / (1) designated in step ST6 of the main control processing. For example, in the processing of step ST6, if display area (0) is designated for the display circuit 74, display area (1) becomes the "write area" for the drawing circuit 76.

[0466] As described above, the correspondence between the actual drawing area (logical space of W×H) and the drawing area (virtual space of W×H) is generally defined by instruction command L11 and instruction command L12, and then the W×H virtual space is associated with the W×H logical space in a specific index space IDX by instruction command L13 (SETINDEX), which specifically specifies the index space IDX.

[0467] In other words, from now on, the content that will be virtually drawn in the W x H virtual space based on a series of instruction commands will become image data in the built-in VRAM 71 (frame buffer) based on a conversion table inside the VDP that defines the correspondence between the virtual space and the actual addresses of the built-in VRAM 71.

[0468] Next, an instruction command to execute a frame buffer clear process is written (L14, L15) to fill the specified index space IDX as the "write area" with, for example, black. This is nothing more than a process to erase the image data written to the frame buffer FBa two operation periods ago.

[0469] Specifically, the SETFCOLOR command, which is a type of environment setting command, is used to select, for example, black, and the RECTANGLE command, which is a primitive drawing command, is used to specify that a rectangular area should be filled in. The RECTANGLE command specifies the X and Y coordinates of the upper left and lower right corners of the drawing area set in the virtual drawing space (the virtual space corresponding to the frame buffer FBa) (see Figure 12(c)).

[0470] With the above processing, the rendering preparation processing is completed, and next, instruction commands are listed for rendering an appropriate texture, such as a still image or a single frame of video, in the virtual rendering space. Typically, the index space IDX into which the texture will be deployed is first specified with a texture setting command, a SETINDEX command, and then a texture load command, a TXLOAD command, is written and a specified texture read from CGROM 55 is written in the display list DL to be deployed in the specified index space IDX.

[0471] As explained above, in this embodiment, the background video is composed of IP stream video. Therefore, for example, the index space IDX into which the background video should be loaded is specified as index space IDX0 in page area (b) using the texture setting command SETINDEX, and then the texture loading command TXLOAD is written. The TXLOAD command must specify the starting address of the CGROM 55 (texture source address) and the data size (horizontal x vertical) after loading for the video frame to be loaded.

[0472] When the VDP circuit 52 executes the TXLOAD command, one video frame (texture) of the background video is first acquired in the AAC area (a), and then the GDEC 75, which starts automatically, expands it into the index space IDX0 of the page area (b). This one video frame is then drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "index space IDX0 of the page area (b) is the texture to be processed thereafter," but if processing is to be performed immediately following the TXLOAD command, the SETINDEX command can be omitted.

[0473] In either case, once it has been determined that "index space IDX0 of page area (b) is the texture to be processed next," appropriate inter-drawing calculation command instructions are then entered, such as setting parameters for alpha blending. Alpha blending is a process that involves making the image already written in the drawing area (frame buffer FBa) transparent or semi-transparent with the image to be overwritten. Therefore, for the first drawing operation, such as for a video frame of a background video, there is no need to use inter-drawing calculation command instructions.

[0474] Next, the SPRITE command, which is a primitive rendering instruction command, is written to draw the "texture (one video frame of the background video) in index space IDX0 of page area (b)" in the appropriate location (rectangular Destination area) in the virtual rendering space. Note that the SPRITE command requires that the upper left and lower right corners of the Destination area in the virtual rendering space be specified.

[0475] This destination area is the entire drawing area (virtual space defined on the virtual drawing space) that has been previously associated with the actual drawing area (FBa) by the instruction commands L11 and L12, or a part thereof. However, since the background moving image is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or larger. An example of a destination area larger than the entire drawing area is when the background moving image is zoomed in.

[0476] With the above processing, the drawing of the video frames of the background video is completed, and then instruction commands such as texture load, texture setting, inter-drawing calculation, and primitive drawing commands are listed in an appropriate order and overlaid on the background video to form a display list DL for drawing various textures. As explained above, a large number of videos are required for variable effects, and in that case, an index table control instruction command (NEWPIX) is written to increase the index space IDX for page area (b) of the built-in VRAM 71.

[0477] For example, for the second IP stream video, an additional index space IDX1 is allocated in page area (b) using the NEWPIX command, and then this index space IDX1 is specified (SETINDEX), a command is issued to render one frame of the second video (TXLOAD), and the rendered texture is placed in the appropriate location in the drawing area (SPRITE). Normally, the destination area in this case is part of the drawing area.

[0478] The same applies below. The NEWPIX command creates the index space IDX one after another. k After securing this, if multiple IP streams are drawn in the drawing area while performing appropriate alpha blending, the contents drawn in the drawing area will be sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When multiple N IP stream videos are drawn, multiple N index spaces are functioning in the page area (b).

[0479] Then, when a series of variable effects has ended, the multiple index spaces IDX1 to IDX2 secured in the page area (b) are k In order to free up the index space IDX that is deemed unnecessary, the unnecessary index space IDX can be deleted using the DELPIX command.

[0480] When drawing still images or I-stream video, use the SETINDEX command to specify that the decoding destination for these textures is AAC area (a), then execute the TXLOAD command. The texture acquired in AAC area (a) will then be expanded into ACC area (a) by GDEC75, which starts automatically. The expanded texture can then be drawn in the appropriate location in the drawing area using the SPRITE command. Depending on whether or not the cache hit function is used, either the first AAC area (a1) or the second AAC area (a2) will be used.

[0481] In the explanation so far, each texture is drawn directly in the drawing area of ​​the main display device DS1, but this operation is not necessarily limited to this. For example, if an appropriate drawing area is set up so as not to overlap with the drawing area already reserved for the display device DS1 (FIG. 12(c)), and this drawing area is associated with the working area of ​​the built-in VRAM 71, an intermediate drawing area can be constructed and an appropriate rendering image can be completed. Here, the reason for not overlapping with the drawing area for the display device DS1 is that for overlapping areas, later association settings take priority, and the drawing contents in that area are not reflected in the frame buffer FBa.

[0482] As shown in Figure 12(c), the working area in this embodiment is the index space IDX0 in the arbitrary area (c). Then, at the timing of the performance using this working area, an instruction command sequence (SETDAVR, SETDAVF, SETINDEX) is written in advance to associate the drawing area for the performance image (see Figure 12(c)) with the working area (the actual drawing area of ​​the index space IDX0). As shown in Figure 12(c), the drawing area for the performance image is secured in an area that is not included in the drawing area for the main display device DS1.

[0483] Then, by listing instruction commands similar to the instruction command sequence L16 for frame buffer FBa, an appropriate effect image can be completed in index space IDX0. In this embodiment, since the effect image is composed of a still image, an instruction command (SETINDEX) is written to expand the decoded data into the first AAC area (a1), and then a primitive drawing instruction command (SPRITE) is used with the appropriate location in the drawing area of ​​index space IDX0 as the destination. Note that this operation is repeated once or multiple times depending on the effect content.

[0484] Then, after positioning the index space IDX0 with the completed effect image as a texture (SETINDEX), the effect image (texture) of the index space IDX0 can be drawn in the appropriate location in the drawing area of ​​the main display device DS1 using the SPRITE command. In such a case, it is possible to break down the effect image of the index space IDX0 into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. The rotation angle of the texture can be associated with, for example, the reliability of the preview effect.

[0485] The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, but the instruction command sequence (L17 to L12) for completing one frame of the sub-display device DS2 is similar. That is, the starting X and Y coordinates of the frame buffer FBb are specified (L17) and defined (usually X=0, Y=0), and a drawing area for the sub-display device DS2 is defined (L18) in the virtual drawing space shown in Figure 12(c).

[0486] In this embodiment, after generating image data for the main display device DS1, the process moves to generation processing for the sub-display device DS2, so there is no problem even if the drawing area for the sub-display device DS2 overlaps with the drawing area for the main display device DS1, and the drawing area can be set freely. Therefore, when developing a program to generate a display list DL, for example, if an appropriate texture is to be pasted into a newly set drawing area using a SPRITE command, the setting of the operation parameters (Destination area) of the SPRITE command and other settings can be standardized to a certain extent.

[0487] Once the definition of such an arbitrary drawing area is completed (L18), the index space IDX that will be the "write area" for the drawing content based on the current display list DL is identified for the frame buffer FBb of the double-buffered display device DS2 (L19). The index number of this index space IDX is the index number for the frame buffer FBb that does not correspond to the display area (0) / (1) specified in step ST6 of the main control process.

[0488] Then, the instruction command sequence L20 to L22 for the sub-display device DS2 is listed in the same manner as the instruction command sequence L14 to L16 for the main display device DS1. It is also possible to use the completed performance image in the index space IDX0.

[0489] As described above, in this embodiment, the command lengths of all of the instruction commands L11 to L22 that make up the display list DL are limited to integer multiples of 32 bits. As explained above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and after adding the required number of NOP commands (L23) as dummy commands, it is terminated with an EODL command (L24). In other words, the embodiment of Figure 23 employs the standard method (B) described above.

[0490] However, even when standard method (B) is adopted, it is not necessarily required to fix the total data size of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total data size of the display list DL excluding NOP commands exceeds 256 bytes (for example, during a special performance period), the total data size of the display list DL is adjusted to 512 bytes or more, i.e., N x 256 bytes, by adding NOP commands. Note that, as explained above, when standard method (B) is adopted, the end of the N x 256 bytes is terminated with an EODL command.

[0491] The configuration of the display list DL has been explained in detail above, and the performance control CPU 63 issues the completed display list DL of fixed byte length to the VDP circuit (ST7 to ST8). Figure 24 is a flowchart explaining the DL issuing process (ST8 in Figure 22) in which the performance control CPU 63 directly WRITE accesses the transfer port register TR_PORT of the transfer circuit 72 and issues the display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that specifies the operation content of the data transfer circuit 72.

[0492] To implement the DL issuance process, first, necessary setting values ​​must be set in a plurality of data transfer registers RGij that define the operation details of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are specified in a predetermined data transfer register RGij. Although the setting contents are not particularly limited, in this example, it is set that data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the CPU bus control unit 72d executes the data transfer operation while checking the remaining capacity of its FIFO buffer (ST20). In the following description, the ChB control circuit 72b may be abbreviated as the "transfer circuit ChB" for convenience.

[0493] Next, the total transfer size is set in a predetermined data transfer register RGij. As explained above, in this embodiment, the total data amount of the display list DL is adjusted to an integer multiple of 256 bytes, so that value is set. Note that the total data amount = 256 x N is also an integer multiple N of the minimum data amount Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following explanation, N = 1 will be used.

[0494] Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit register, the performance control CPU 63 executes a register WRITE operation for the transfer port TR_PORT every 32 bits. Therefore, the value of the management counter CN, which manages the number of register WRITEs, is initialized to 64 (ST21). Note that if the non-adjustment method (C) is adopted, the data transfer amount that is an integer multiple of the minimum data amount Dmin is determined at this timing, and the management counter CN is set.

[0495] The above process completes the initial setting, and next, the data transfer operation via the transfer circuit ChB is set to a start state (ST22), and the drawing operation is started based on the set value of the predetermined drawing register RGij that defines the operation of the drawing circuit 76 (ST23). As a result, the performance control CPU 63 subsequently ensures quick and smooth analysis processing by the drawing circuit 76 (display list analyzer) for the instruction command sequence that performs the register WRITE operation on the transfer port TR_PORT.

[0496] Furthermore, the fact that the instruction commands listed in the display list DL are limited to those whose command length is an integral multiple of 32 bits also contributes effectively to a fast and smooth analysis process. Timings t1, t2, t3, and t4 in Figure 30(a) indicate the operation timing of step ST23. Note that, because the display list DL issuance process (ST8) is completed quickly, the time required for the issuance process is not shown in Figures 30 to 31.

[0497] Next, it is confirmed whether the setting in step ST22 has worked (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes longer to process than the register WRITE operation (setting operation) by the performance control CPU 63, so subsequent instructions are not given to the incomplete data transfer circuit 72. If the operation does not start even after waiting for a predetermined time, the serious abnormality flag ABN is set and the DL issuance process is terminated (ST25). As a result, the WDT circuit 58 then functions, and the composite chip 50 is abnormally reset (ST10).

[0498] As mentioned above, in order to avoid resetting the CPU circuit 51, the performance control CPU 63 may output a predetermined keyword string to the pattern check circuit CHK and abnormally reset only the VDP circuit 52 based on the reset signal RST.

[0499] However, since the setting in step ST22 is usually completed quickly, next, after confirming that the FIFO buffer (32 bits x 130 stages) of the CPU bus control unit 72d is not full (ST26), instruction commands are written to the transfer port TR_PORT for each line in the display list DL, starting from the first line (ST28).

[0500] Then, while decrementing the management counter CN (ST29), the processing of steps ST26 to ST29 is repeated until the management counter CN becomes zero (ST30). In this embodiment, since a minimum data amount Dmin is defined for the data transfer circuit 72, a data transfer operation is executed when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in an intermittent transfer operation.

[0501] In any case, in this embodiment, the DL issuance process (ST28) is completed quickly, but in the unlikely event that the settings in the VDP registers RGij become inconsistent due to the effects of noise or the like, the FIFO buffer full state may not be resolved even after waiting for a predetermined time in the determination of step ST26. In such a case, initialization data is set in the predetermined VDP registers RGij, the drawing circuit 76 and data transfer circuit 72 are initialized, and the serious abnormality flag ABN is set, and the DL issuance process is terminated (ST27).

[0502] At this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and completed a certain amount of processing. Therefore, the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area, while maintaining the contents of the drawing register RGij. Similarly, the initialization process of the data transfer circuit 72 includes initialization of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

[0503] In the initialization process of step ST27 described above, the contents of the drawing register RGij are maintained, but the contents of certain drawing registers may be initialized. The certain drawing registers that are cleared to their initial values ​​include (a) an execution control register (see ST23 in FIG. 24) that sets the start of drawing execution, (b) a status register that indicates the execution status of the drawing circuit 76, and (c) a status register that specifies the position of the display list currently being processed.

[0504] In any case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and the performance control CPU 63 then function and the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a), so it is not necessarily necessary to initialize the drawing circuit 76 and the data transfer circuit 72. On the other hand, if the drawing circuit 76 and the data transfer circuit 72 are initialized, recovery from the abnormality can be expected as a result, so it is also preferable to return to the processing of step ST20 and re-execute the DL issuance processing without setting the serious abnormality flag ABN.

[0505] This also applies to the processing of step ST25, and it is preferable to return to the processing of step ST20 without setting the serious abnormality flag ABN after initializing the data transfer circuit 72 and the drawing circuit 76. In such a case, however, the number of retries of the DL issuance processing is counted, and if the number of retries exceeds a limit value, the serious abnormality flag ABN is set and the DL issuance processing is terminated.

[0506] 24(b) is a diagram illustrating a normal operating state for confirmation. As shown in the diagram, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and operations based on each instruction command are executed. This operation is executed in parallel with the display list DL issuance process and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

[0507] For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and stored in the AAC area (a), after which the GDEC 75 is automatically started to perform a decoding operation, and the decoded data is expanded in a predetermined index space. Also, depending on the instruction command, the geometry engine 77 and other functions are activated, but in any case, the various parts of the drawing circuit 76 work together to complete the image data corresponding to the display list DL in the frame buffers FBa and FBb.

[0508] Next, a case where a display list DL is issued via the DMAC circuit 60 will be described with reference to Fig. 25. Although not limited thereto, it is assumed that the third DMA channel is used among the first to fourth DMA channels built into the DMAC circuit 60.

[0509] In the embodiment of Fig. 25, first, a clear value is set in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This processing is the same as the error processing in step ST27 of Fig. 24, and the internal circuitry of the data transfer circuit 72 including the FIFO buffer is initialized, the status bit of the data transfer register indicating the progress of the data transfer is set to an initial value, and the bit indicating that the entire data transfer is being initialized is set to a predetermined value.

[0510] The same applies to the drawing circuit 76, and includes the above-mentioned processes of (1) setting internal parameters to initial values, (2) setting the internal control circuit to an initial state, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area. The predetermined drawing register RGij may also be initialized in the initialization process of the drawing circuit (ST20 in FIG. 25). Note that this initialization process may be executed first in the process of FIG. 24.

[0511] 25, the process next checks whether the initialization process has been completed successfully by reading a predetermined status register RGij that specifies the operating states of the data transfer circuit 72 and the drawing circuit 76 (ST21). If the initialization process is not successful, the process sets a serious abnormality flag ABN and ends the process (ST22). However, this situation almost never actually occurs.

[0512] Next, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are set in a predetermined data transfer register RGij. The setting contents are not particularly limited, but here, it is set that the data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the transfer protocol to the CPU bus control unit 72d follows the setting in the DMAC circuit 60 (ST23).

[0513] Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 24, the total data amount = 256. Note that if the non-adjustment method (C) is adopted, a total transfer size that is an integer multiple of the minimum data amount Dmin is determined and set at this timing. Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). The timings t1, t2, t3, and t4 in FIG. 30(a) are also the operation timings of step ST25. Next, the operation of the DMAC circuit 60 is started (ST26), and then the data transfer operation of the data transfer circuit 72 is started (ST27).

[0514] The process of starting the operation of the DMAC circuit 60 is as shown in Figure 25(b), and first, with DMAC transfer disabled, the process waits for the transfer of one cycle of data transfer unit (one operand) to be completed (ST40). The detailed operation content is the same as the process shown in Figure 26, and is divided into a process of setting DMAC transfer to disabled (ST53) and a subsequent waiting process (ST54).

[0515] The reason for providing such processing is that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (FIG. 22), and (2) in other embodiments that do not provide the processing of step ST5 in FIG. 22, the DMAC circuit 60 that has started issuing a display list DL may not be able to complete the DL issuing operation within its operating period (δ).

[0516] In the exceptional case described above, if new setting values ​​(such as contradictory setting values) are additionally set to the operating DMAC circuit 60, normal DMA operation is not guaranteed at all, and serious trouble is a concern, but by providing the processing of step ST40, normal operation based on the setting values ​​thereafter is guaranteed. In other words, even in a modified embodiment that is a partial modification of this embodiment, normal DMA operation can be achieved thereafter regardless of the preceding trouble.

[0517] After the processing of step ST40 having the above significance is executed, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in Figure 9, the cycle steal transfer mode is selected, and one operand transfer is set to two 32-bit transfers. Also, the source address is an address in the list buffer area (DL buffer BUF) of RAM 59, so it should be recognized as increasing sequentially, while the destination address is the transfer port TR_PORT, so it should be a fixed value.

[0518] Next, the start address of the DL buffer BUF in RAM 59 is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). Furthermore, the total transfer size, that is, the total amount of data in the display list DL, is set to 256 bytes (ST44), and the DMA operation of the DMAC circuit 60 is started (ST45).

[0519] The explanation so far has been based on the assumption that the effective bit length of the instruction commands is an integral multiple of 32 bits. However, the configuration of the display list DL and the instruction commands is not necessarily limited, so the following explanation will be given for such a case.

[0520] For example, even when the non-adjustment method (C) is employed, if the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, the arbitrary value X is adjusted to an appropriate transfer amount MOD in the processing of step ST44, and then the processing for setting the total transfer size is executed. Here, the appropriate transfer amount MOD is determined based on the setting contents for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

[0521] Specifically, if the one-operand transfer setting is N bytes x M times, the transfer amount MOD is adjusted to a value that is an integer multiple of N x M (bytes) and an integer multiple of Dmin (bytes). For example, if N x M = 8 x 4 and Dmin = 256, the arbitrary value X (= 300) bytes is adjusted to the transfer amount MOD (= 512) bytes.

[0522] As explained above, including generalities, the DMA operation of the DMAC circuit 60 starts a cycle steal transfer operation as shown in Figure 9, and the display list DL is transferred to the transfer port TR_PORT in units of 32 bits in this embodiment without interfering with the operation of the CPU. The transferred data is then transferred to the drawing circuit 76 via the transfer circuit ChB.

[0523] To achieve this operation, in this embodiment, following the processing of step ST45, the data transfer circuit 72 starts its transfer operation and ends the processing (ST27). Thereafter, the data transfer circuit 72 receives a series of instruction commands for the display list DL from the DMAC circuit 60, with the minimum data amount Dmin as one unit, and transfers these to the drawing circuit 76. The drawing circuit 76 then executes drawing operations based on the instruction commands in the display list DL. Therefore, after processing of step ST27, the performance control CPU 63 can start processing of step ST11 in FIG. 22, and can control audio performances, lamp performances, and motor performances in parallel with the drawing operation by the VDP circuit 52 (DL issuance processing by the DMAC circuit 60).

[0524] 25(c) illustrates this operation. Prior to the DMA transfer, the drawing circuit 76 starts operating (ST25), the display list analyzer of the drawing circuit 76 quickly and smoothly executes the analysis process, and based on the operations of the GDEC 75, geometry engine 77, etc., one frame's worth of image data is generated in the frame buffers FBa and FBb for each of the display devices DS1 and DS2.

[0525] Incidentally, the configuration of Fig. 25, in which the DL issuance process ends with the process of step ST27, is not necessarily limited. For example, as shown in Figs. 32 and 33, when another CPU controls the audio effects, lamp effects, and motor effects, it is preferable to check the normal operation of the DMAC circuit 60 and data transfer circuit 72 after the process of step ST27. Fig. 26 is a flowchart illustrating the operation following step ST27 in Fig. 25, and explains the process of checking the normal operation.

[0526] First, a predetermined status register is referenced to confirm that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). Also, it is confirmed that the data transfer circuit 72 has completed its transfer operation (ST51). Normally, the DL issuance process of FIG. 25 is completed through this process.

[0527] On the other hand, if the operation of the DMAC circuit 60 is not completed even after waiting for a predetermined time, or if the data transfer circuit 72 has not completed its transfer operation, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72, and the DL issuance process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not ended normally, and specifically, it is the same as the error process in step ST27 in Fig. 24 and the initial process in step ST20 in Fig. 25.

[0528] That is, in this case too, the drawing circuit 76 has already started operating and has completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area.

[0529] Next, new DMA transfer operations are prohibited (ST53), and the process waits for the transfer operation of one operand currently being executed to finish (ST54). As explained above, in this embodiment, two 32-bit transfers are counted as one operand, and this is to avoid abruptly initializing the DMAC circuit 60 while it is in operation.

[0530] Once this preparation work is complete, a clear value is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60, thereby initializing the DMAC circuit 60 (ST52). Then, the serious abnormality flag ABN is set, and the DL issuance process is terminated. In this case, since the abnormality can be expected to be recovered from by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 in FIG. 25 and re-execute the DL issuance process without setting the serious abnormality flag ABN. However, it is necessary to count the number of retries of the DL issuance process (ST23 to ST27), and if the number of retries exceeds a limit, to set the serious abnormality flag ABN and terminate the DL issuance process.

[0531] Next, the main control process when the preloader 73 is used will be described with reference to Fig. 27. The process of Fig. 27 is similar to the process of Fig. 22, but first, the content of the start condition determination (ST5') is different. That is, in an embodiment using a preloader, at the start of each operation cycle, status information of the drawing circuit 76 and the preloader 73 is accessed for reading to confirm that the drawing operation based on the display list DL1 has ended and that the preload operation based on the display list DL2 has ended (ST5').

[0532] 31(a), the preloader 76 should have completed the pre-reading operation (preloading operation) during an operation cycle (T1 to T1+δ) based on the display list DL1 issued during that operation cycle. Also, the drawing circuit 76 should have completed the drawing operation during that operation cycle (T1+δ to T1+2δ) based on the operation start command issued during that operation cycle.

[0533] Therefore, in (ST5'), the status information of the VDP register RGij related to the drawing circuit 76 and the preloader 73 is read and accessed to confirm the normal operation. Figure 31(a) shows that normal operation is confirmed at the determination timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but the preload operation has not ended at the determination timing of the operation cycle T1+3δ.

[0534] In the event of such an abnormality, the abnormality flag ER is incremented (ER=ER+1) and the process proceeds to step ST9. As a result, a frame is dropped, as in the example of FIG. 22. That is, the display area switching process (ST6) is skipped, and the same screen is re...

Claims

1. A gaming machine including a driver that rotates a DC motor, a transmission means that transmits the rotational motion of the DC motor, and a control means that controls the driver, The control means regulates the rotation of the DC motor by specifying the rotation direction and rotation torque of the DC motor to the driver.

2. 2. The gaming machine according to claim 1, wherein the rotational torque is configured to change in accordance with the progress of the operation of the accessory that moves via the transmission means.

3. 3. The gaming machine according to claim 1, wherein the rotation speed of the DC motor is increased in accordance with the progress of the action of the movable device via the transmission means.

4. The gaming machine described in claim 1, wherein the driver is configured so that the built-in transistors are turned on / off appropriately based on motor control signals received from the outside, and the rotation direction is specified to be one direction, thereby realizing appropriate motor effects.

5. 5. The gaming machine according to claim 4, wherein the driver receives the motor control signal as a serial signal.

6. 6. The gaming machine according to claim 5, wherein the driver receives the motor control signal in SPI (Serial Peripheral Interface) format.

7. 2. The gaming machine according to claim 1, wherein the rotational torque changes in level in a manner capable of driving a stepping motor using a two-phase excitation method or a one-two phase excitation method.

8. 9. The gaming machine according to claim 8, wherein the manner of the level change is determined based on the motor control signal.

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