Data transmission system, transmitter, receiver, and data transmission method

Abstract

To perform clock synchronization with a simple configuration while reducing a transmission delay amount of data in a system for transmitting data included in a packet.SOLUTION: The transmission device generates an optical signal including the transmission data using a baseband clock and transmits the optical signal to the reception device, the transmission device transmits relation information indicating a relation between a frequency of the baseband clock and a frequency of a data clock corresponding to the data rate to the reception device, and the reception device reproduces the baseband clock based on the optical signal and reproduces the data clock based on the reproduced baseband clock and the relation information.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a data transmission system, a transmitting device, a receiving device, and a data transmission method. [Background technology]

[0002] Conventionally, techniques for synchronizing clocks between a transmitting device and a receiving device have been proposed. For example, Patent Document 1 (JP 2011-71830 A) discloses the following clock recovery device. That is, the clock recovery device recovers a clock from a timestamp included in a received packet, and includes counter means that counts based on the recovered clock, and recovery means that recovers the clock based on the difference between the timestamp included in the received packet and the count value of the counter means at the time the packet is received, and the packet is a packet for measuring delay. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-71830 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-177913 [Patent Document 3] Japanese Patent Application Laid-Open No. 2012-54847 Summary of the Invention [Problem to be solved by the invention]

[0004] Beyond the techniques described in Patent Documents 1 to 3, there is a demand for a technique that can perform clock synchronization with a simple configuration while reducing the amount of data transmission delay in a system that transmits data contained in packets.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a data transmission system, a transmitting device, a receiving device, and a data transmission method that are capable of performing clock synchronization with a simple configuration while reducing the amount of data transmission delay in a system that transmits data contained in packets. [Means for solving the problem]

[0006] The data transmission system disclosed herein comprises a transmitting device that transmits transmission data at a predetermined data rate, and a receiving device that receives the transmission data from the transmitting device, wherein the transmitting device generates an optical signal including the transmission data using a baseband clock and transmits the generated optical signal to the receiving device, the transmitting device transmits relationship information to the receiving device that indicates the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate, and the receiving device recovers the baseband clock based on the optical signal received from the transmitting device, and recovers the data clock based on the recovered baseband clock and the relationship information received from the transmitting device.

[0007] One aspect of the present disclosure may be realized not only as a transmitting device including such a characteristic processing unit, but also as a transmitting method including steps of such characteristic processing, or as a program for causing a computer to execute such steps. Furthermore, one aspect of the present disclosure may be realized as a semiconductor integrated circuit that realizes part or all of the transmitting device.

[0008] One aspect of the present disclosure may be realized not only as a receiving device including such a characteristic processing unit, but also as a receiving method including steps of such characteristic processing, or as a program for causing a computer to execute such steps. Furthermore, one aspect of the present disclosure may be realized as a semiconductor integrated circuit that realizes part or all of the receiving device. [Effects of the Invention]

[0009] According to the present disclosure, in a system in which data is transmitted in packets, clock synchronization can be performed with a simple configuration while reducing the amount of data transmission delay. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a data transmission system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a transmission device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a receiving device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating an example of a relationship information generating unit in the transmission device according to the embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an example of a relationship information generating unit in a transmission device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating an example of a relationship information generating unit in a transmission device according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an example of a transmission sequence of transmission data in a data transmission system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] First, the contents of the embodiments of the present disclosure will be listed and described. (1) A data transmission system according to an embodiment of the present disclosure includes a transmitting device that transmits transmission data at a predetermined data rate, and a receiving device that receives the transmission data from the transmitting device, wherein the transmitting device generates an optical signal including the transmission data using a baseband clock and transmits the generated optical signal to the receiving device, the transmitting device transmits relationship information to the receiving device that indicates a relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate, and the receiving device recovers the baseband clock based on the optical signal received from the transmitting device and recovers the data clock based on the recovered baseband clock and the relationship information received from the transmitting device.

[0012] In this way, the receiving device regenerates the data clock based on the baseband clock recovered from the optical signal received from the transmitting device and relationship information indicating the relationship between the frequency of the baseband clock and the frequency of the data clock corresponding to the data rate of the transmission data. This allows the data clock to be regenerated using the pulse interval of the baseband clock as a common time interval with the transmitting device, thereby achieving clock synchronization with a simpler configuration than a configuration in which information about the data clock is transmitted via a dedicated line separate from the transmission line for the optical signal. Furthermore, the receiving device regenerates the data clock based on a transmission data read cycle adjusted so that the amount of data stored in a buffer that stores the received transmission data is constant. Therefore, in a system in which data is transmitted in packets, clock synchronization can be achieved with a simpler configuration while reducing the amount of data transmission delay.

[0013] (2) In the above (1), the transmitting device may transmit the relationship information indicating a result of comparison between the frequency of the baseband clock and the frequency of the data clock to the receiving device.

[0014] With this configuration, the data clock can be accurately recovered using the frequency of the baseband clock as a reference.

[0015] (3) In the above (1) or (2), the receiving device may include a PLL circuit that regenerates the data clock, and a signal based on the regenerated baseband clock may be provided as a reference signal to a phase comparator in the PLL circuit, and the division number of a divider between the output of a voltage-controlled oscillator in the PLL circuit and the input of the phase comparator may be set to a value based on the relationship information.

[0016] With this configuration, the signal based on the baseband clock and the relationship between the frequency of the baseband clock and the frequency of the data clock corresponding to the data rate of the transmission data are reflected in the operation of the PLL circuit, making it possible to reproduce the data clock with a simple configuration.

[0017] (4) A transmitting device according to an embodiment of the present disclosure is a transmitting device that transmits transmission data at a predetermined data rate to a receiving device, and includes: a first generating unit that generates an optical signal including the transmission data using a baseband clock; a first transmitting unit that transmits the optical signal generated by the first generating unit to the receiving device; a second generating unit that generates relationship information indicating the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate; and a second transmitting unit that transmits the relationship information generated by the second generating unit to the receiving device.

[0018] In this manner, by transmitting an optical signal generated using a baseband clock to a receiving device and transmitting relationship information indicating the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate of the transmitted data to the receiving device, the receiving device can regenerate a data clock, for example, by using the pulse interval of the baseband clock regenerated based on the optical signal as a common time interval with the transmitting device. Therefore, clock synchronization can be achieved with a simpler configuration than a configuration in which information about the data clock is transmitted using a dedicated line separate from the transmission line for the optical signal. Furthermore, data transmission delay can be reduced compared to a configuration in which the receiving device regenerates a data clock based on a transmission data read cycle adjusted so that the amount of data stored in a buffer that stores the received transmission data is constant. Therefore, in a system in which data is transmitted in packets, clock synchronization can be achieved with a simple configuration while reducing data transmission delay.

[0019] (5) A receiving device according to an embodiment of the present disclosure is a receiving device that receives transmission data at a predetermined data rate from a transmitting device that transmits the transmission data, and includes: a first receiving unit that receives an optical signal that is generated using a baseband clock and includes the transmission data; a second receiving unit that receives relationship information that indicates the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate; a first regenerating unit that regenerates the baseband clock based on the optical signal received by the first receiving unit; and a second regenerating unit that regenerates the data clock based on the baseband clock regenerated by the first regenerating unit and the relationship information received by the second receiving unit.

[0020] In this way, the data clock is regenerated based on the baseband clock regenerated based on the optical signal received from the transmitting device and on relationship information indicating the relationship between the frequency of the baseband clock and the frequency of the data clock corresponding to the data rate of the transmission data. This allows the data clock to be regenerated using the pulse interval of the baseband clock as a common time interval with the transmitting device. This allows clock synchronization to be achieved with a simpler configuration than a configuration in which information about the data clock is transmitted using a dedicated line separate from the transmission line for the optical signal. Furthermore, data transmission delays can be reduced compared to a configuration in which the data clock is regenerated based on a transmission data read cycle adjusted so that the amount of data stored in a buffer that stores the received transmission data is constant. Therefore, in a system in which data is transmitted in packets, clock synchronization can be achieved with a simpler configuration while reducing data transmission delays.

[0021] (6) A data transmission method according to an embodiment of the present disclosure is a data transmission method comprising a transmitting device that transmits transmission data at a predetermined data rate and a receiving device that receives the transmission data from the transmitting device, and includes the steps of: the transmitting device generating an optical signal including the transmission data using a baseband clock and transmitting the generated optical signal to the receiving device; the transmitting device transmitting relationship information indicating the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate to the receiving device; and the receiving device recovering the baseband clock based on the optical signal received from the transmitting device, and recovering the data clock based on the recovered baseband clock and the relationship information received from the transmitting device.

[0022] In this way, in a receiving device, a method for recovering a data clock based on a baseband clock recovered from an optical signal received from a transmitting device and relationship information indicating the relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate of the transmission data allows the data clock to be recovered using the pulse interval of the baseband clock as a common time interval with the transmitting device. This allows clock synchronization to be achieved with a simpler configuration than a configuration in which information about the data clock is transmitted via a dedicated line separate from the transmission line for the optical signal. Furthermore, in a receiving device, data transmission delay can be reduced compared to a configuration in which the data clock is recovered based on a transmission data read cycle adjusted so that the amount of data stored in a buffer that accumulates the received transmission data is constant. Therefore, in a system in which data is transmitted in packets, clock synchronization can be achieved with a simple configuration while reducing the amount of data transmission delay.

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, identical or corresponding parts are designated by the same reference numerals, and their description will not be repeated. Furthermore, at least some of the embodiments described below may be combined in any manner.

[0024] [Configuration and basic operation] 1 is a diagram illustrating a configuration of a data transmission system according to an embodiment of the present disclosure. Referring to FIG. 1, a data transmission system 301 includes a transmitting device 101 and a receiving device 201.

[0025] The transmitting device 101 transmits transmission data Dt at a predetermined data rate Rt to the receiving device 201. More specifically, the transmitting device 101 receives a stream of transmission data Dt, for example, having a nominal data rate Rt of 8 Gbps (Giga bit per second), from a data generating device 111 that generates the transmission data Dt. For example, the stream of transmission data Dt is a stream in which the end of the data is not determined and is transmitted continuously over a long period of time. The transmission data Dt may be video data, audio data, or data other than video data and audio data. The transmitting device 101 generates a fixed-length packet Pt that stores the received transmission data Dt, and transmits a frame Fr1 including the generated packet Pt to the receiving device 201 via the network 151. The data transfer rate between the transmitting device 101 and the receiving device 201 is, for example, 100 Gbps.

[0026] The network 151 is, for example, an all-photonics network conforming to IOWN (Innovative Optical and Wireless Network). An optical signal including a frame Fr1 is transmitted through the network 151. The network 151 may include optical components such as an optical switch, an optical demultiplexer, and an optical multiplexer in addition to optical fibers. For example, the network 151 does not include a repeater that acquires and stores packets Pt from the optical signal.

[0027] The receiving device 201 receives transmission data Dt from the transmitting device 101. More specifically, the receiving device 201 receives a frame Fr1 from the transmitting device 101 via the network 151, and acquires the transmission data Dt from a packet Pt included in the received frame Fr1. The receiving device 201 recovers a bit clock CL1 corresponding to a data rate Rt of the transmission data Dt, and transmits the transmission data Dt to the data processing device 211 using the recovered bit clock CL1. The bit clock CL1 is an example of a data clock.

[0028] The data transmission system 301 transmits the transmission data Dt with low delay between the data generating device 111 and the data processing device 211. The transmission delay of the transmission data Dt between the data generating device 111 and the data processing device 211 is, for example, 5 milliseconds or less.

[0029] [assignment] In the data transmission system 301, a technique is desired that can perform clock synchronization with a simple configuration while reducing the amount of transmission delay of the transmission data Dt.

[0030] For example, in a system that transmits transmission data Dt without packetizing it, it is possible to provide clock information related to the bit clock CL1 to the transmission destination by encoding or scrambling. On the other hand, since the transmitting device 101 is configured to transmit the transmission data Dt to the receiving device 201 by including it in a packet Pt, it is not easy to provide information related to the bit clock CL1 to the receiving device 201. Furthermore, if the clock information is transmitted using a dedicated line for transmitting clock information separate from the network 151, the configuration of the data transmission system 301 becomes complicated.

[0031] Furthermore, in the receiving device 201, when the amount of transmission data Dt stored in the buffer is monitored and the bit clock CL1 is regenerated based on the read cycle of the transmission data Dt adjusted so that the amount of packets stored in the buffer is constant, it is necessary to store the amount of transmission data Dt required for regeneration in the buffer, which results in a large transmission delay of the transmission data Dt between the data generating device 111 and the data processing device 211.

[0032] Therefore, the data transmission system 301 according to the embodiment of the present disclosure solves the above problem by adopting the following configuration.

[0033] (Transmitting device) FIG. 2 is a diagram illustrating a configuration of a transmitting device according to an embodiment of the present disclosure. Referring to FIG. 2, the transmitting device 101 includes a receiving buffer 11, a bit clock recovery unit 12, a counter 13, a related information generating unit 14, a BB clock generating unit 15, a frame generating unit 17, a transmitting unit 18, and a transmitting buffer 19. The transmitting unit 18 is an example of a first generating unit, an example of a first transmitting unit, and an example of a second transmitting unit. The related information generating unit 14 is an example of a second generating unit. Some or all of the bit clock recovery unit 12, the counter 13, the related information generating unit 14, the BB clock generating unit 15, the frame generating unit 17, and the transmitting unit 18 are implemented by, for example, a processing circuit including one or more processors. The receiving buffer 11 and the transmitting buffer 19 are, for example, FIFO (First-In First-Out) buffers.

[0034] The transmitting device 101 generates an optical signal including transmission data Dt using a baseband clock CL2, and transmits the generated optical signal to the receiving device 201. The transmitting device 101 also transmits relationship information Sf1 indicating the relationship between the frequency of the baseband clock CL2 and the frequency of a bit clock CL1 corresponding to the data rate Rt of the transmission data Dt to the receiving device 201. Details of the processing in the transmitting device 101 will be described below.

[0035] The receiving buffer 11 receives the transmission data Dt having a nominal data rate Rt of 8 Gbps from the data generating device 111, and stores the received transmission data Dt.

[0036] The bit clock recovery unit 12 recovers a bit clock CL1 corresponding to the data rate Rt of the transmission data Dt. More specifically, the bit clock recovery unit 12 uses a CDR (Clock Data Recovery) function to extract the bit clock CL1 from the transmission data Dt transmitted from the data generating device 111 to the transmitting device 101. The bit clock recovery unit 12 outputs the extracted bit clock CL1 to the counter 13 and the relationship information generating unit 14. Here, the frequency of the bit clock CL1 is 8000 MHz when the data rate Rt is 8 Gbps.

[0037] Counter 13 counts the pulses of bit clock CL1 received from bit clock recovery unit 12 and holds the count value.

[0038] The BB clock generation unit 15 generates a baseband clock CL2. For example, the BB clock generation unit 15 generates the baseband clock CL2 having a frequency fs based on a clock output from a high-precision crystal oscillator (not shown). The BB clock generation unit 15 outputs the generated baseband clock CL2 to the relationship information generation unit 14 and the transmission unit 18.

[0039] The relationship information generation unit 14 generates relationship information Sf1 indicating the relationship between the frequency of the baseband clock CL2 and the frequency of the bit clock CL1. More specifically, the relationship information generation unit 14 generates the relationship information Sf1 indicating the relationship between the frequency of the baseband clock CL2 received from the BB clock generation unit 15 and the frequency of the bit clock CL1 received from the bit clock recovery unit 12 at timing according to a predetermined cycle. Note that the relationship information generation unit 14 may also generate the relationship information Sf1 irregularly. The relationship information generation unit 14 outputs the generated relationship information Sf1 to the frame generation unit 17. Details of the relationship information Sf1 will be described later.

[0040] The frame generation unit 17 receives the relationship information Sf1 from the relationship information generation unit 14 and holds the received relationship information Sf1.

[0041] For example, the frame generation unit 17 stores the transmission data Dt in the packet Pt using the bit clock CL1. More specifically, every time the count value of the counter 13 increases by "8", the frame generation unit 17 obtains one byte of the transmission data Dt from the receive buffer 11 and stores the obtained transmission data Dt in the packet Pt.

[0042] The frame generation unit 17 generates a frame Fr1 at a timing according to a predetermined period, in which the packet Pt is stored in the payload and the held relationship information Sf1 is stored in the header, and stores the generated frame Fr1 in the transmission buffer 19. The frame generation unit 17 may store a packet Pt including dummy data in the frame Fr1. The frame generation unit 17 may also generate a frame Fr1 and store it in the transmission buffer 19 at irregular intervals.

[0043] The transmitter 18 generates an optical signal including transmission data Dt using the baseband clock CL2. The transmitter 18 transmits the generated optical signal to the receiver 201. The transmitter 18 further transmits relationship information Sf1 generated by the relationship information generator 14 to the receiver 201.

[0044] More specifically, the transmitter 18 acquires a bit string corresponding to one frame Fr1 from the transmission buffer 19, one bit at a time, at an acquisition timing according to the baseband clock CL2 received from the BB clock generator 15. The transmitter 18 generates an optical signal including the frame Fr1 by converting the acquired bit string into an optical signal at a timing according to a predetermined cycle. The transmitter 18 transmits the generated optical signal to the receiver 201 via the network 151. Note that the transmitter 18 may also generate and transmit an optical signal to the receiver 201 at irregular intervals.

[0045] (receiving device) FIG. 3 is a diagram illustrating a configuration of a receiving device according to an embodiment of the present disclosure. Referring to FIG. 3, the receiving device 201 includes a receiving unit 21, a data acquiring unit 22, a BB clock regenerating unit 23, a bit clock regenerating unit 24, a transmitting unit 25, and a buffer 26. The receiving unit 21 is an example of a first receiving unit and an example of a second receiving unit. The BB clock regenerating unit 23 is an example of a first regenerating unit. The bit clock regenerating unit 24 is an example of a second regenerating unit. Some or all of the receiving unit 21, the data acquiring unit 22, the BB clock regenerating unit 23, the bit clock regenerating unit 24, and the transmitting unit 25 are implemented by, for example, a processing circuit including one or more processors. The buffer 26 is, for example, a FIFO.

[0046] The receiving device 201 recovers the baseband clock CL2 based on the optical signal received from the transmitting device 101, and recovers the bit clock CL1 based on the recovered baseband clock CL2 and the relationship information Sf1 received from the transmitting device 101. Details of the processing in the receiving device 201 will be described below.

[0047] The receiving unit 21 receives an optical signal including the transmission data Dt and the related information Sf1. More specifically, the receiving unit 21 receives the optical signal from the transmitting device 101 via the network 151. The receiving unit 21 converts the received optical signal into an electrical signal and outputs the converted electrical signal to the data acquiring unit 22 and the BB clock recovering unit 23.

[0048] The BB clock recovery unit 23 recovers the baseband clock CL2 based on the optical signal received by the receiving unit 21. More specifically, the BB clock recovery unit 23 uses the function of a CDR to recover the baseband clock CL2 from the electrical signal received from the receiving unit 21. The BB clock recovery unit 23 outputs the baseband clock CL2R, which is a recovered clock of the baseband clock CL2, to the data acquiring unit 22 and the bit clock recovery unit 24.

[0049] The data acquisition unit 22 samples the electrical signal received from the receiving unit 21 in accordance with the timing of the baseband clock CL2R received from the BB clock recovery unit 23, thereby reconstructing a frame Fr1 included in the electrical signal. The data acquisition unit 22 acquires a packet Pt and related information Sf1 from the reconstructed frame Fr1. The data acquisition unit 22 acquires transmission data Dt from the acquired packet Pt and stores the data in the buffer 26. For example, if the packet Pt includes dummy data, the data acquisition unit 22 further stores the dummy data in the buffer 26. The data acquisition unit 22 also outputs the acquired related information Sf1 to the bit clock recovery unit 24. If packet length information Sf2, which will be described later, is included in the frame Fr1, the data acquisition unit 22 further acquires the packet length information Sf2 and outputs the packet length information Sf2 to the clock recovery unit 24.

[0050] The bit clock recovery unit 24 recovers the bit clock CL1 based on the baseband clock CL2 recovered by the BB clock recovery unit 23 and the relationship information Sf1 received by the receiving unit 21. More specifically, the bit clock recovery unit 24 recovers the bit clock CL1 based on the baseband clock CL2R received from the BB clock recovery unit 23 and the relationship information Sf1 received from the data acquiring unit 22. The bit clock recovery unit 24 outputs the bit clock CL1R, which is a recovered clock of the bit clock CL1, to the transmitting unit 25.

[0051] The transmitter 25 obtains the transmission data Dt bit by bit from the buffer 26 in accordance with the bit clock CL1R received from the bit clock regenerator 24, and transmits the obtained transmission data Dt to the data processor 211.

[0052] (Example 1 of relationship information Sf1) 4 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to an embodiment of the present disclosure. Referring to FIG. 4, relationship information generation unit 14A, which is relationship information generation unit 14, includes a frequency divider 31A, a counter 31B, a frequency divider 31C, and a generation unit 31D. Relationship information generation unit 14A generates relationship information Sf1 indicating a comparison result between the frequency of baseband clock CL2 and the frequency of bit clock CL1.

[0053] The frequency division number of the frequency divider 31A is set to, for example, "10." The frequency division number of the frequency divider 31C is set to, for example, "fs / (1 megabit)."

[0054] The frequency divider 31A receives a bit clock CL1 of approximately 8000 MHz from the bit clock recovery unit 12, and divides the received bit clock CL1 by 10 to generate a measurement clock Cm1 of approximately 800 MHz and outputs it to the counter 31B.

[0055] The counter 31B counts the pulses of the measurement clock Cm1 received from the frequency divider 31A and holds the count value.

[0056] The frequency divider 31C receives the baseband clock CL2 of frequency fs from the BB clock generation unit 15, and divides the received baseband clock CL2 by (fs / 1 megabit) to generate a 1 MHz measured clock Cm2 and output it to the generation unit 31D.

[0057] The generation unit 31D obtains a measurement value Δc1 of the number of pulses of the measurement clock Cm1 in one cycle of the measurement target clock Cm2 received from the frequency divider 31C by referring to the count value of the counter 31B. Here, the measurement value Δc1 is "800" when the frequency of the bit clock CL1 is 8000 MHz, and "799" when the frequency of the bit clock CL1 is, for example, 7990 MHz. The generation unit 31D generates relationship information Sf1 indicative of the measurement value Δc1 and outputs the generated relationship information Sf1 to the frame generation unit 17.

[0058] 5 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. Referring to FIG. 5, bit clock recovery unit 24A, which is part of bit clock recovery unit 24, includes a PLL circuit 32, a setting unit 33, a frequency divider 34, and a pulse conversion unit 35. PLL circuit 32 includes a phase comparator 32A, a loop filter 32B, a voltage-controlled oscillator 32C, and frequency dividers 32D and 32E. Frequency dividers 32D and 32E are provided between the output of voltage-controlled oscillator 32C and the input of phase comparator 32A. PLL circuit 32 recovers bit clock CL1. PLL circuit 32 outputs bit clock CL1R, which is a recovered clock of bit clock CL1, to transmitter 25.

[0059] The frequency division number of the frequency divider 34 is set to, for example, "fs / (1 MHz)." The frequency division number of the frequency divider 32D in the PLL circuit 32 is set to, for example, "10" when the transmission data Dt is transmitted in 10-bit units in accordance with the DisplayPort (registered trademark) standard.

[0060] The frequency division number of frequency divider 32E in PLL circuit 32 is set to a value based on the relationship information Sf1. More specifically, setting unit 33 sets the frequency division number of frequency divider 32E to the measured value Δc1 indicated by the relationship information Sf1 received from data acquiring unit 22. Every time setting unit 33 receives relationship information Sf1 from data acquiring unit 22, it sets the frequency division number of frequency divider 32E to the measured value Δc1 indicated by the relationship information Sf1.

[0061] The frequency divider 32D divides the output signal of the voltage-controlled oscillator 32C by 10, and outputs the resultant signal to the frequency divider 32E. The frequency divider 32E divides the output signal of the frequency divider 32D by the division number set by the setting unit 33, and outputs the resultant signal to the phase comparator 32A.

[0062] The frequency divider 34 receives the baseband clock CL2R of frequency fs from the BB clock recovery unit 23, and divides the frequency of the received baseband clock CL2R by (fs / 1 MHz) to generate a 1 MHz clock signal, which is output to the pulse conversion unit 35. The pulse conversion unit 35 provides a signal based on the baseband clock CL2 to the phase comparator 32A as a reference signal. More specifically, the pulse conversion unit 35 generates a reference signal, which is a 1 MHz pulse signal, based on the clock signal received from the frequency divider 34, and outputs the reference signal to the phase comparator 32A.

[0063] Phase comparator 32A compares the phase of the reference signal received from pulse conversion unit 35 with the phase of the signal received from frequency divider 32E, and outputs a phase comparison signal indicating the comparison result to loop filter 32B.

[0064] Loop filter 32B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 32A, and outputs the signal as a control voltage for voltage controlled oscillator 32C.

[0065] Voltage controlled oscillator 32C generates a bit clock CL1R, which is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 32B, for example, and outputs the generated bit clock CL1R to transmitter 25 and frequency divider 32D.

[0066] (Specific example 2 of relationship information Sf1) 6 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to an embodiment of the present disclosure. Referring to FIG. 6, relationship information generation unit 14B, which is part of relationship information generation unit 14, includes a frequency divider 41A, a counter 41B, a frequency divider 41C, and a generation unit 41D. Relationship information generation unit 14B generates relationship information Sf1 indicating a comparison result between the frequency of baseband clock CL2 and the frequency of bit clock CL1.

[0067] The frequency division number of frequency divider 41A is set to, for example, "8000." The frequency division number of frequency divider 41C is set to, for example, "fs / (900 megabits)."

[0068] The frequency divider 41C receives the baseband clock CL2 of frequency fs from the BB clock generation unit 15, and divides the received baseband clock CL2 by (fs / 900 MHz) to generate a measurement clock Cm1 of 900 MHz and output it to the counter 41B.

[0069] The counter 41B counts the pulses of the measurement clock Cm1 received from the frequency divider 41C and holds the count value.

[0070] The frequency divider 41A receives a bit clock CL1 of approximately 8000 MHz from the bit clock recovery unit 12, divides the received bit clock CL1 by 8000, and generates a clock Cm2 to be measured of approximately 1 MHz, which is output to the generation unit 41D.

[0071] The generation unit 41D obtains a measured value Δc2 of the number of pulses of the measurement clock Cm1 in one cycle of the measurement target clock Cm2 received from the frequency divider 41A by referring to the count value of the counter 41B. Here, when the frequency of the bit clock CL1 is 8000 MHz, the measured value Δc2 is "900." The generation unit 41D generates relationship information Sf1 indicating the measured value Δc2 and outputs the generated relationship information Sf1 to the frame generation unit 17.

[0072] 7 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. Referring to FIG. 7, bit clock recovery unit 24B, which is part of bit clock recovery unit 24, includes a PLL circuit 42, a setting unit 43, a down counter 44, and frequency dividers 45 and 46. PLL circuit 42 includes a phase comparator 42A, a loop filter 42B, a voltage-controlled oscillator 42C, and frequency dividers 42D and 42E.

[0073] The frequency division number of frequency divider 45 is set to, for example, "fs / (900 MHz)". The frequency division number of frequency divider 46 is set to, for example, "2". The frequency division number of frequency divider 42D in PLL circuit 42 is set to, for example, "8000". The frequency division number of frequency divider 42E in PLL circuit 42 is set to, for example, "2".

[0074] The preset value of the down counter 44 is set to a value based on the relationship information Sf1. More specifically, the setting unit 43 sets the count value of the down counter 44 to the measured value Δc2 indicated by the relationship information Sf1 received from the data acquiring unit 22. Every time the setting unit 43 receives relationship information Sf1 from the data acquiring unit 22, it sets the count value of the down counter 44 to the measured value Δc2 indicated by the relationship information Sf1.

[0075] Frequency divider 42D divides the output signal of voltage controlled oscillator 42C by 8000, and outputs the resultant signal to frequency divider 42E. Frequency divider 42E divides the output signal of frequency divider 42D by 2, and outputs the resultant signal to phase comparator 42A.

[0076] The frequency divider 45 receives the baseband clock CL2R of frequency fs from the BB clock recovery unit 23, and divides the received baseband clock CL2R by (fs / 900 MHz) to generate a 900 MHz signal and outputs it to the down counter 44.

[0077] The down counter 44 decrements the count value by "1" each time it detects a pulse in the signal received from the frequency divider 45, and resets the count value to the measured value Δc2 when the count value reaches zero. The down counter 44 outputs a 1 MHz borrow signal to the frequency divider 46, which goes high each time the count value reaches zero.

[0078] The frequency divider 46 receives a 1 MHz borrow signal from the down counter 44, and divides the frequency of the received borrow signal by two to generate a 500 kHz reference signal with a duty ratio of 50%, which is output to the phase comparator 42A.

[0079] Phase comparator 42A compares the phase of the reference signal received from frequency divider 46 with the phase of the signal received from frequency divider 42E, and outputs a phase comparison signal indicating the comparison result to loop filter 42B.

[0080] Loop filter 42B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 42A, and outputs the signal as a control voltage for voltage controlled oscillator 42C.

[0081] Voltage controlled oscillator 42C generates bit clock CL1R, which is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 42B, for example, and outputs generated bit clock CL1R to transmitter 25 and frequency divider 42D.

[0082] (Example 3 of relationship information Sf1) 8 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to an embodiment of the present disclosure. Referring to FIG. 8, relationship information generation unit 14C, which is part of relationship information generation unit 14, includes counter 51B and generation unit 51D. Relationship information generation unit 14C generates relationship information Sf1 indicating the number of pulses of baseband clock CL2 during the time required to collect transmission data Dt to be stored in packet Pt from receive buffer 11.

[0083] The counter 51B receives the baseband clock CL2 having the frequency fs from the BB clock generating unit 15. The counter 51B counts the pulses of the baseband clock CL2 and holds the count value.

[0084] The generation unit 51D monitors the frame generation unit 17 to obtain the number of bytes of the transmission data Dt stored in the packet Pt by the frame generation unit 17. Furthermore, by referring to the count value of the counter 51B, the generation unit 51D obtains a measured value Δc3 of the number of pulses of the baseband clock CL2 during the period from when the frame generation unit 17 starts storing the transmission data Dt in the packet Pt to when the frame generation unit 17 finishes storing the transmission data Dt in the packet Pt. The generation unit 51D generates packet length information Sf2 indicating the number of bytes of the transmission data Dt stored in the packet Pt and relationship information Sf1 indicating the measured value Δc3, and outputs the generated packet length information Sf2 and relationship information Sf1 to the frame generation unit 17.

[0085] 9 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to an embodiment of the present disclosure. Referring to FIG. 9, bit clock recovery unit 24C, which is part of bit clock recovery unit 24, includes setting units 90A and 90B, a measurement value FIFO 91, a data FIFO 92, a readout unit 93, latch units 94A and 94B, an up-counter 95, a comparator 96, a loop filter 97, a voltage-controlled oscillator 98, a frequency divider 99, and a down-counter 100. The readout unit 93 may be shared with the transmitting unit 25. The data FIFO 92 may be shared with the buffer 26.

[0086] The bit clock recovery unit 24C generates a bit clock CL1R based on the result of comparing the number of pulses of the baseband clock CL2 during the time required for the transmitting device 101 to store the transmission data Dt in the packet Pt with the number of pulses of the baseband clock CLR2 during the time required for the receiving device 201 to read the transmission data Dt from the data FIFO 92.

[0087] More specifically, the setting unit 90A receives a packet Pt from the data acquiring unit 22 and stores the transmission data Dt included in the received packet Pt in the data FIFO 92. The setting unit 90A assigns a predetermined identifier Id to the first byte of the transmission data Dt in the packet Pt.

[0088] Furthermore, the setting unit 90A receives the relationship information Sf1 from the data acquiring unit 22 and stores the measured value Δc3 indicated by the received relationship information Sf1 in the measured value FIFO 91.

[0089] The frequency divider 99 receives the bit clock CL1R from the voltage controlled oscillator 98, divides the frequency of the received bit clock CL1R by eight to generate a byte clock CL3, and outputs the byte clock CL3 to the readout unit 93 and the down counter 100.

[0090] The read unit 93 receives a byte clock CL3 from the frequency divider 99, and each time it detects a pulse of the byte clock CL3, it reads one byte of transmission data Dt from the data FIFO 92. If the read transmission data Dt has an identifier Id assigned to it, the read unit 93 resets the count value of the up-counter 95 to zero, outputs a latch instruction to the latch unit 94A, and outputs a set instruction to the setting unit 90B.

[0091] The up-counter 95 receives the baseband clock CL2R from the BB clock recovery unit 23. The up-counter 95 counts pulses of the baseband clock CL2R and holds the count value.

[0092] When receiving a latch instruction from the reading unit 93, the latch unit 94A acquires and holds the measurement value Δc3 from the measurement value FIFO 91. The measurement value Δc3 latched by the latch unit 94A corresponds to the number of pulses of the baseband clock CL2 in the time required for the transmitting device 101 to collect, from the receiving buffer 11, the transmission data Dt to be stored in the packet Pt.

[0093] The setting unit 90B receives packet length information Sf2 from the data acquiring unit 22. When the setting unit 90B receives a set instruction from the reading unit 93, it sets the preset value of the down counter 100 to the number of bytes indicated by the received packet length information Sf2. That is, the setting unit 90B sets the count value of the down counter 100 to the number of bytes of the transmission data Dt included in the packet Pt.

[0094] The down counter 100 receives the byte clock CL3 from the frequency divider 99. The down counter 100 decrements the count value by "1" each time it detects a pulse of the byte clock CL3. When the count value reaches zero, the down counter 100 outputs a latch instruction to the latch unit 94B.

[0095] When receiving a latch instruction from the down counter 100, the latch unit 94B acquires and holds the count value of the up counter 95. The count value latched by the latch unit 94B corresponds to the number of pulses of the baseband clock CL2R during the time required for the receiving device 201 to read out the transmission data Dt included in the packet Pt from the data FIFO 92.

[0096] The comparator 96 compares the measurement value Δc3 latched by the latch section 94A with the count value latched by the latch section 94B, and outputs to the loop filter 97 a count comparison signal indicating the comparison result.

[0097] Loop filter 97 attenuates components of a predetermined frequency or higher out of the frequency components of the count comparison signal received from comparator 96 and outputs the signal as a control voltage for voltage controlled oscillator 98 .

[0098] Voltage controlled oscillator 98 generates a bit clock CL1R, which is an oscillation signal having a frequency corresponding to the level of the control voltage received from loop filter 97, for example, and outputs the generated bit clock CL1R to transmitter 25 and frequency divider 99.

[0099] [Operation flow] FIG. 10 is a diagram illustrating an example of a transmission sequence of transmission data in a data transmission system according to an embodiment of the present disclosure.

[0100] Referring to FIG. 10, first, the data generating device 111 transmits a stream of transmission data Dt having a nominal value of a data rate Rt of 8 Gbps to the transmitting device 101 (step S11).

[0101] Next, the transmitting device 101 extracts the bit clock CL1 from the transmission data Dt received from the data generating device 111 (step S12).

[0102] Next, the transmitting device 101 generates a baseband clock CL2 having a frequency fs based on a clock output from a high-precision crystal oscillator (not shown) (step S13).

[0103] Next, the transmitting device 101 starts generating a packet Pt. For example, every time the count value of the pulses of the bit clock CL1 increases by "8", the transmitting device 101 obtains one byte of transmission data Dt from the receiving buffer 11 and stores it in the packet Pt (step S14).

[0104] Next, the transmitting device 101 generates an optical signal including transmission data Dt using the baseband clock CL2 at a transmission timing according to a predetermined transmission period, and transmits the generated optical signal to the receiving device 201 via the network 151. More specifically, the transmitting device 101 generates a frame Fr1 including the packet Pt and related information Sf1, converts a bit string corresponding to the frame Fr1 into an optical signal, thereby generating an optical signal including the frame Fr1, and transmits the generated optical signal to the receiving device 201 via the network 151 (step S15).

[0105] Next, the receiving device 201 converts the optical signal received from the transmitting device 101 into an electrical signal, and recovers the baseband clock CL2 from the electrical signal (step S16).

[0106] Next, the receiving device 201 reconstructs the frame Fr1 by sampling the electrical signal, and acquires the related information Sf1 from the frame Fr1 (step S17).

[0107] Next, the receiving device 201 generates a bit clock CL1R, which is a recovered clock of the bit clock CL1, based on the recovered baseband clock CL2 and the acquired relationship information Sf1 (step S18).

[0108] Next, the receiving device 201 transmits the transmission data Dt to the data processing device 211 in accordance with the bit clock CL1R (step S19).

[0109] Note that, although the transmitting device 101 according to the embodiment of the present disclosure is configured to receive one stream of transmission data Dt from the data generating device 111, this is not limiting. The transmitting device 101 may be configured to receive multiple streams from the data generating device 111. For example, the transmitting device 101 receives a stream of transmission data DtA, which is the transmission data Dt, a stream of transmission data DtB, which is the transmission data Dt, and a stream of transmission data DtC, which is the transmission data Dt.

[0110] In this case, the transmitting device 101 includes receiving buffers 11A, 11B, and 11C that are receiving buffer 11, bit clock regenerators 12A, 12B, and 12C that are bit clock regenerator 12, counters 13A, 13B, and 13C that are counter 13, and relationship information generators 14A, 14B, and 14C that are relationship information generator 14. The receiving device 201 also includes bit clock regenerators 24A, 24B, and 24C that are bit clock regenerator 24, transmitters 25A, 25B, and 25C that are transmitting unit 25, and buffers 26A, 26B, and 26C that are buffer 26.

[0111] In the transmitting device 101, receive buffers 11A, 11B, and 11C store transmit data DtA, DtB, and DtC, respectively. Bit clock recovery units 12A, 12B, and 12C extract bit clocks CL1A, CL1B, and CL1C, which are the bit clock CL1, from the transmit data DtA, DtB, and DtC, respectively, and output the bit clocks to counters 13A, 13B, and 13C. The counters 13A, 13B, and 13C count pulses of the bit clocks CL1A, CL1B, and CL1C, respectively, and store the count values. Each time the count value of counter 13A increases by "8," the frame generation unit 17 retrieves one byte of transmit data DtA from the receive buffer 11A and stores it in packet PtA. Each time the count value of counter 13B increases by "8," the frame generation unit 17 retrieves one byte of transmit data DtB from the receive buffer 11B and stores it in packet PtB. Furthermore, the frame generation unit 17 obtains one byte of transmission data DtC from the receive buffer 11C and stores it in a packet PtC every time the count value of the counter 13C is incremented by "8." The relationship information generation units 14A, 14B, and 14C generate relationship information Sf1A, Sf1B, and Sf1C, respectively, which is relationship information Sf1 indicating the relationship between the frequency of the baseband clock CL2 and the frequencies of the bit clocks CL1A, CL1B, and CL1C. The frame generation unit 17 generates a frame Fr1 in which the packets PtA, PtB, and PtC are stored in the payload and the relationship information Sf1A, Sf1B, and Sf1C are stored in the header, and accumulates the generated frame Fr1 in the transmit buffer 19.

[0112] In the receiving device 201, the data acquiring unit 22 acquires packets PtA, PtB, and PtC from the frame Fr1, acquires transmission data DtA, DtB, and DtC from the acquired packets PtA, PtB, and PtC, and stores them in buffers 26A, 26B, and 26C, respectively. The bit clock regenerator 24A generates a bit clock CL1RA based on the baseband clock CL2R and the data amount of the relationship information Sf1A, and outputs it to the transmitting unit 25A. The bit clock regenerator 24B generates a bit clock CL1RB based on the baseband clock CL2R and the data amount of the relationship information Sf1B, and outputs it to the transmitting unit 25B. The bit clock regenerator 24C generates a bit clock CL1RC based on the baseband clock CL2R and the data amount of the relationship information Sf1C, and outputs it to the transmitting unit 25C. The transmitter 25A obtains transmission data DtA from the buffer 26A in accordance with the bit clock CL1RA and transmits it to the data processing device 211. The transmitter 25B obtains transmission data DtB from the buffer 26B in accordance with the bit clock CL1RB and transmits it to the data processing device 211. The transmitter 25C obtains transmission data DtC from the buffer 26C in accordance with the bit clock CL1RC and transmits it to the data processing device 211.

[0113] Furthermore, in the transmitting device 101 according to the embodiment of the present disclosure, the frame generation unit 17 is configured to obtain one byte of transmission data Dt from the receiving buffer 11 and store the obtained transmission data Dt in the packet Pt each time the count value of the counter 13 increases by "8," but this is not limited to this. If the transmitting device 101 includes the relationship information generation unit 14A or 14B, the frame generation unit 17 may be configured to obtain a predetermined amount of data, for example, 10 bytes of transmission data Dt, all at once from the receiving buffer 11 and store it in the packet Pt without using the count value of the counter 13. In other words, if the transmitting device 101 includes the relationship information generation unit 14A or 14B, the frame generation unit 17 may be configured to store the transmission data Dt in the packet Pt without using the bit clock CL1.

[0114] Furthermore, in transmitting device 101 according to the embodiment of the present disclosure, frame generating unit 17 is configured to store relationship information Sf1 in the header of frame Fr1, but this is not limited to this. Frame generating unit 17 may also be configured to store relationship information Sf1 in a frame other than frame Fr1.

[0115] The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0116] Each process (each function) in the above-described embodiments is realized by a processing circuit including one or more processors. The processing circuit may be configured as an integrated circuit or the like that combines one or more memories, various analog circuits, and various digital circuits in addition to the one or more processors. The one or more memories store programs (instructions) that cause the one or more processors to execute each of the processes. The one or more processors may execute each of the processes according to the program read from the one or more memories, or according to a logic circuit pre-designed to execute each of the processes. The processor may be various processors suitable for computer control, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), and an application-specific integrated circuit (ASIC). Note that the physically separate processors may cooperate with each other to execute each of the processes. For example, the processors mounted on a plurality of physically separated computers may cooperate with each other to execute the above processes via a network such as a LAN (Local Area Network), a WAN (Wide Area Network), the Internet, etc. The program may be installed into the memory from an external server device or the like via the network, or may be distributed in a state stored on a recording medium such as a CD-ROM (Compact Disc Read Only Memory), a DVD-ROM (Digital Versatile Disc Read Only Memory), or a semiconductor memory, and installed into the memory from the recording medium.

[0117] The above description includes the following additional features. [Appendix 1] a transmitting device that transmits transmission data at a predetermined data rate; a receiving device that receives the transmission data from the transmitting device, the transmitting device generates an optical signal including the transmission data using a baseband clock, and transmits the generated optical signal to the receiving device; the transmitting device transmits to the receiving device relationship information indicating a relationship between a frequency of the baseband clock and a frequency of a data clock corresponding to the data rate; the receiving device recovers the baseband clock based on the optical signal received from the transmitting device, and recovers the data clock based on the recovered baseband clock and the related information received from the transmitting device; The transmitting device generates a frame including the transmission data and the related information, and transmits the optical signal including the frame to the receiving device. [Explanation of symbols]

[0118] 11 Receive Buffer 12-bit clock recovery section 13 Counter 14, 14A, 14B, 14C Relationship information generation unit 15 BB clock generation unit 17 Frame Generation Unit 18 Transmitter 19 Send Buffer 21 Receiving unit 22 Data Acquisition Section 23 BB clock recovery section 24, 24A, 24B, 24C Bit clock recovery section 25 Transmitter 26 buffers 31A,41A frequency divider 31B, 41B, 51B counters 31C,41C frequency divider 31D, 41D, 51D generation part 32,42 PLL circuit 32A,42A phase comparator 32B, 42B loop filter 32C, 42C Voltage Controlled Oscillator 32D,42D frequency divider 32E,42E frequency divider 33,43 Setting section 34 frequency divider 35 Pulse conversion unit 44 Down Counter 45 divider 46 Frequency divider 90A Setting section 90B Setting section 91 Measurement Value FIFO 92 Data FIFOs 93 Readout section 94A Latch 94B Latch part 95 Up Counter 96 Comparator 97 Loop Filter 98 Voltage Controlled Oscillator 99 frequency divider 100 Down Counter 101 Transmitting device 111 Data generation device 151 Network 201 Receiver 211 Data processing device 301 Data Transmission System

Claims

1. a transmitting device that transmits transmission data at a predetermined data rate; a receiving device that receives the transmission data from the transmitting device, the transmitting device generates an optical signal including the transmission data using a baseband clock, and transmits the generated optical signal to the receiving device; the transmitting device transmits to the receiving device relationship information indicating a relationship between a frequency of the baseband clock and a frequency of a data clock corresponding to the data rate; a receiving device that recovers the baseband clock based on the optical signal received from the transmitting device, and recovers the data clock based on the recovered baseband clock and the related information received from the transmitting device.

2. 2. The data transmission system according to claim 1, wherein the transmitting device transmits the relationship information indicating a result of a comparison between the frequency of the baseband clock and the frequency of the data clock to the receiving device.

3. the receiving device includes a PLL circuit that regenerates the data clock, and provides a signal based on the regenerated baseband clock to a phase comparator in the PLL circuit as a reference signal; 3. The data transmission system according to claim 1, wherein a frequency division number of a frequency divider between the output of a voltage-controlled oscillator and the input of said phase comparator in said PLL circuit is set to a value based on said relationship information.

4. A transmitting device that transmits transmission data at a predetermined data rate to a receiving device, a first generator that generates an optical signal including the transmission data using a baseband clock; a first transmitting unit that transmits the optical signal generated by the first generating unit to the receiving device; a second generating unit that generates relationship information indicating a relationship between a frequency of the baseband clock and a frequency of a data clock corresponding to the data rate; a second transmitting unit configured to transmit the relationship information generated by the second generating unit to the receiving device.

5. A receiving device that receives transmission data at a predetermined data rate from a transmitting device that transmits the transmission data, a first receiving unit that receives an optical signal including the transmission data, the optical signal being generated using a baseband clock; a second receiving unit that receives relationship information indicating a relationship between the frequency of the baseband clock and the frequency of a data clock corresponding to the data rate; a first regenerator configured to regenerate the baseband clock based on the optical signal received by the first receiver; a second regenerating unit configured to regenerate the data clock based on the baseband clock regenerated by the first regenerating unit and the related information received by the second receiving unit.

6. A data transmission method including a transmitting device that transmits transmission data at a predetermined data rate and a receiving device that receives the transmission data from the transmitting device, The transmitting device generates an optical signal including the transmission data using a baseband clock and transmits the generated optical signal to the receiving device; a step of transmitting, from the transmitting device, relationship information indicating a relationship between a frequency of the baseband clock and a frequency of a data clock corresponding to the data rate to the receiving device; a step by the receiving device of recovering the baseband clock based on the optical signal received from the transmitting device, and recovering the data clock based on the recovered baseband clock and the related information received from the transmitting device.

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