Display device

Abstract

To provide a display device capable of improving yield.SOLUTION: In general, according to one embodiment, a display device includes a substrate having a display region for displaying an image, a plurality of pixels each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, the plurality of pixels being arranged in the display region, a dummy pixel region including a plurality of dummy pixels not displaying an image, the dummy pixel region surrounding the display region, and a partition wall including a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion, the partition wall being provided in the display region, the dummy pixel region, and an outer peripheral region surrounding the dummy pixel region. Further, the partition wall has a plurality of slits provided in the display region and the dummy pixel region, and the slits are not provided at a boundary between the dummy pixel region and the outer peripheral region.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a substrate having a display area for displaying an image, a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light in response to application of a voltage, a plurality of pixels arranged in the display area, a dummy pixel area including a plurality of dummy pixels that do not display an image and surrounding the display area, and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall having a plurality of slits formed in the display area and the dummy pixel area, and the slits are not formed at the boundary between the dummy pixel area and the outer periphery area.

[0006] According to an embodiment, a display device includes a substrate having a display area for displaying an image, a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light in response to application of a voltage, the display area including a plurality of pixels and a plurality of dummy pixels that do not display an image, a dummy pixel region surrounding the display area, a conductive lower portion, and an upper portion having an end portion protruding from a side surface of the lower portion, a partition wall provided in the display area, the dummy pixel region, and a peripheral region surrounding the dummy pixel region, a first sealing layer formed of an inorganic insulating material and covering the plurality of pixels and the plurality of dummy pixels, and a second sealing layer formed of an inorganic insulating material and covering the peripheral region. Furthermore, the partition wall has a plurality of slits provided at least in the display area and the dummy pixel region, at least one of the slits being located at a boundary between the dummy pixel region and the peripheral region, and the second sealing layer covering the slit located at the boundary. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the display device according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view of the peripheral region of the display device according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged view of the area enclosed by the frame VI in FIG. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged view of the vicinity of the boundary between the dummy pixel region and the outer peripheral region according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of the dummy pixel region and the outer peripheral region taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic plan view of the motherboard according to the first embodiment. [Figure 10] FIG. 10 is a schematic plan view of the panel unit according to the first embodiment. [Figure 11] FIG. 11 is a flowchart showing an example of the manufacturing method according to the first embodiment. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing a step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a schematic cross-sectional view showing a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a schematic cross-sectional view showing a step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a schematic cross-sectional view showing a step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a schematic cross-sectional view showing a step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a schematic cross-sectional view showing a step subsequent to FIG. 12F. [Figure 13] FIG. 13 is a schematic plan view showing a configuration according to a comparative example. [Figure 14] FIG. 14 is a schematic cross-sectional view of the dummy pixel region and the peripheral region taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a schematic plan view showing the configuration according to the second embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the dummy pixel region and the peripheral region taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a schematic plan view showing the configuration according to the third embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the dummy pixel region and the outer peripheral region taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a schematic plan view showing the configuration according to the fourth embodiment. [Figure 20] FIG. 20 is a schematic plan view showing the configuration according to the fifth embodiment. [Figure 21] FIG. 21 is a schematic plan view showing the configuration according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not limiting.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1, AP2, and AP3 are all rectangular. The area of ​​the pixel opening AP1 is larger than the area of ​​the pixel opening AP3. The area of ​​the pixel opening AP2 is also larger than the area of ​​the pixel opening AP1. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The lower electrode LE1, upper electrode UE1, and organic layer OR1 form the display element DE1 of subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 form the display element DE2 of subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 form the display element DE3 of subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6 is disposed above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. The partition wall 6 surrounds the subpixels SP1, SP2, and SP3.

[0025] The partition wall 6 has a plurality of slits SLa extending in the Y direction. In the example of FIG. 2, the sub-pixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two slits SLa in the X direction. Furthermore, the partition wall 6 has connecting portions CT that connect the portions separated by the slits SLa. Note that the arrangement of the slits SLa and the connecting portions CT is not limited to the example of FIG. 2. For example, there may be slits SLa that are continuous between both ends of the display area DA in the Y direction.

[0026] Sealing layers SE11, SE12, and SE13 (first sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0027] 2, the sealing layers SE11, SE12, and SE13 do not overlap with the slit SLa. As another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SLa.

[0028] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The peripheral edges of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0030] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0031] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0032] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0034] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers to improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the stacked film FL1 and the surrounding partition wall 6. The sealing layer SE12 continuously covers the stacked film FL2 and the surrounding partition wall 6. The sealing layer SE13 continuously covers the stacked film FL3 and the surrounding partition wall 6.

[0037] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] 3, a touch panel electrode TP for detecting a touch operation by a user is disposed on the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material, and has the same shape as the partition wall 6 in a plan view.

[0039] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0040] 3, ends of the sealing layers SE11 and SE12 overlap each other in the Z direction above the partition wall 6 between the subpixels SP1 and SP2. Furthermore, ends of the sealing layers SE11 and SE13 overlap each other in the Z direction above the partition wall 6 between the subpixels SP1 and SP3.

[0041] For example, a gap is formed between the sealing layer SE11 and the upper portion 62 of the partition wall 6. Gaps are also formed between the sealing layer SE12 and the upper portion 62, and between the end of the sealing layer SE11 and the end of the sealing layer SE12. These gaps are generated by the disappearance of the stacked films FL1 and FL2 during the manufacturing process. At least a portion of these gaps may be filled with the resin layer RS1.

[0042] Meanwhile, a stacked film FL3a is disposed between the sealing layer SE13 and the partition wall 6 and between the end of the sealing layer SE11 and the end of the sealing layer SE13. The stacked film FL3a is formed by, for example, altering the stacked film FL3 during the manufacturing process. Note that the stacked film FL3a may be lost during the manufacturing process. In this case, gaps are generated between the sealing layer SE13 and the partition wall 6 and between the ends of the sealing layers SE11 and SE13.

[0043] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0044] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0045] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0046] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0047] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0048] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0049] The first top layer 65 of the partition wall 6 is formed of, for example, a metal material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0050] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal of the signal line S is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0051] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0052] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0053] 4 is a schematic plan view of the display device DSP. In the example of this figure, a dummy pixel region DMY surrounding the display region DA is arranged in the peripheral region SA. The partition wall 6 is also arranged in the dummy pixel region DMY.

[0054] Furthermore, the partition wall 6 is also disposed in an outer peripheral region OP surrounding the dummy pixel region DMY. In the outer peripheral region OP, the partition wall 6 is covered with a sealing layer SE1x (second sealing layer). The sealing layer SE1x is made of the same inorganic insulating material as the sealing layers SE11, SE12, and SE13.

[0055] A dam structure DS1 is disposed outside the sealing layer SE1x. The terminal portion T is located outside the dam structure DS1. For example, the dummy pixel region DMY, the peripheral region OP, the sealing layer SE1x, and the dam structure DS1 are all circular and concentric with the display region DA.

[0056] In the outer peripheral region OP, the partition wall 6 is connected to the lower relay layer RL and the power supply line PW (see FIG. 5) via a plurality of contact portions CN1. The power supply line PW is connected to the terminal portion T and receives a common voltage from the terminal portion T. The common voltage of the partition wall 6 is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the partition wall 6. In the example of FIG. 4, the plurality of contact portions CN1 are arranged in an arc shape on the terminal portion T side.

[0057] 5 is a schematic cross-sectional view of the peripheral area SA of the display device DSP. The structure of the partition walls 6 in the outer peripheral area OP is the same as the structure of the partition walls 6 in the display area DA shown in FIG.

[0058] The circuit layer 11 shown in FIG. 3 includes inorganic insulating layers 31, 32, and 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0059] For example, the dam structure DS1 includes a dam portion DM1, a dam portion DM2 surrounding the dam portion DM1, and a dam portion DM3 surrounding the dam portion DM2. For example, the dam portions DM1, DM2, and DM3 are circular and surround the display area DA. The number of dam portions included in the dam structure DS1 is not limited to three.

[0060] Dam portions DM1, DM2, and DM3 all protrude above the substrate 10. In the example of FIG. 5, dam portion DM1 is formed from organic insulating layers 12 and 34. Dam portions DM2 and DM3 are also formed from organic insulating layers 12 and 34. That is, in this embodiment, dam portions DM1, DM2, and DM3 are formed from the same material as organic insulating layers 12 and 34 and in the same layer as organic insulating layers 12 and 34.

[0061] A power supply line PW to which a common voltage is applied is disposed below the dam portions DM1 and DM2. The power supply line PW has a first wiring W1 formed by the metal layer 42 and a second wiring W2 formed by the metal layer 43.

[0062] 5, the first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN0 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring W2 is located between the organic insulating layers 12 and 34.

[0063] The peripheral area SA is further provided with a conductive relay layer RL that connects the partition wall 6 to the power supply line PW, and a rib layer 5. The relay layer RL is formed, for example, from the same material and by the same process as the above-described lower electrodes LE1, LE2, and LE3.

[0064] The relay layer RL is located closer to the display area DA side (left side in the drawing) than the dam portion DM1, and covers the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1, DM2, and DM3.

[0065] In the outer peripheral region OP, the partition wall 6 is disposed on the rib layer 5. The partition wall 6 is in contact with the relay layer RL at the contact portion CN1 also shown in FIG. 4. Specifically, the rib layer 5 has an opening at the contact portion CN1, and a lower portion 61 (specifically, a bottom layer 63) of the partition wall 6 is in contact with the relay layer RL through this opening. The contact portion CN1 is located above the organic insulating layer 12.

[0066] The relay layer RL is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2, which is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 in plan view.

[0067] In the peripheral region OP, a stacked film FLx is disposed on the partition wall 6. The partition wall 6 and the stacked film FLx are covered with a sealing layer SE1x. The stacked film FLx is formed by the same process and from the same material as any one of the stacked films FL1, FL2, and FL3 shown in FIG. 3. The sealing layer SE1x is formed by the same process and from the same material as any one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3. In this embodiment, it is assumed that the stacked film FLx and the sealing layer SE1x are formed by the same process and from the same material as the stacked film FL3 and the sealing layer SE13, respectively. That is, the stacked film FLx includes an upper electrode UE3, an organic layer OR3, and a cap layer CP3.

[0068] Above the sealing layer SE1x, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are arranged. Also, above the sealing layer SE2, the touch panel wiring TPL connected to the touch panel electrodes TP shown in Fig. 3 is arranged. For example, the touch panel wiring TPL is made of the same material as the touch panel electrodes TP.

[0069] The resin layer RS1 covers the sealing layer SE1x and the rib layer 5. The dam portions DM1, DM2, and DM3 serve to block the resin layer RS1 before hardening during the manufacturing of the display device DSP. In the example of FIG. 5, the end portion Er1 of the resin layer RS1 is located above the dam portion DM2. That is, the resin layer RS1 covers the dam portion DM1 and a part of the dam portion DM2. However, the position of the end portion Er1 is not limited to this example.

[0070] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in an area outside the end portion Er1 (to the right in the figure). In the example of FIG. 5, the sealing layer SE2 is removed near the dam portion DM3. The resin layer RS1 is surrounded by the sealing layer SE1x, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating the resin layer RS1.

[0071] 5, the organic insulating layer 12 may have a first portion PN1 and a second portion PN2 that is thinner than the first portion PN1. The second portion PN2 is formed on the periphery of the first portion PN1. That is, the second portion PN2 surrounds the first portion PN1 in a plan view. The partition wall 6, the stacked film FLx, and the sealing layer SE1x in the peripheral region OP are all located above the first portion PN1.

[0072] 5, the organic insulating layer 34 is disposed below the first portion PN1, and the organic insulating layer 34 is not disposed below the second portion PN2. A step portion 12a is formed in the organic insulating layer 12 near the end of the organic insulating layer 34. For example, the portion of the organic insulating layer 12 closer to the dam portion DM1 than the step portion 12a corresponds to the second portion PN2.

[0073] The relay layer RL covers the first portion PN1, the second portion PN2, and the step portion 12a. If the organic insulating layer 12 did not have the second portion PN2, the step portion 12a would be steeper. If the relay layer RL were formed to cover such a steep step portion 12a, an abnormal shape of the relay layer RL could occur. In contrast, if the second portion PN2 is provided, the step portion 12a can be reduced, and the relay layer RL can be formed well.

[0074] The cross-sectional structure shown in FIG. 5 can be applied to any position in the peripheral area SA except for the vicinity of the terminal portion T. However, the structure of the peripheral area SA is not necessarily limited to that shown in FIG. 5. For example, the organic insulating layer 12 does not necessarily have to have the second portion PN2. Furthermore, the structure for connecting the partition wall 6 and the power supply line PW can be modified as appropriate based on the position of the power supply line PW, the layer configuration of the circuit layer 11, etc.

[0075] 6 is a schematic plan view showing an enlarged view of the area enclosed by the frame VI in FIG. 4. A plurality of dummy pixels DPX are arranged in the dummy pixel area DMY. For example, the dummy pixel DPX includes dummy subpixels DP1, DP2, and DP3. The dummy subpixels DP1, DP2, and DP3 have structures similar to those of the subpixels SP1, SP2, and SP3 shown in FIG. 2, respectively.

[0076] That is, the dummy subpixel DP1 includes a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. The dummy subpixel DP2 includes a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. The dummy subpixel DP3 includes a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0077] However, the dummy subpixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy subpixels DP1, DP2, and DP3. Alternatively, the pixel openings AP1, AP2, and AP3 may be omitted from each of the dummy subpixels DP1, DP2, and DP3. This intervenes between the organic layers OR1, OR2, and OR3 and the lower electrodes LE1, LE2, and LE3, and prevents the application of a voltage to the organic layers OR1, OR2, and OR3 to cause them to emit light.

[0078] A part of the partition wall 6 is located in the dummy pixel region DMY and surrounds each of the dummy pixels DPX. More specifically, the partition wall 6 surrounds each of the dummy sub-pixels DP1, DP2, and DP3.

[0079] The peripheral region OP is formed continuously with the partition wall 6 in the dummy pixel region DMY. For example, the peripheral region OP corresponds to a portion of the partition wall 6 that overlaps with the sealing layer SE1x. Lower electrodes LE1, LE2, LE3 and pixel circuits PC are arranged in the display region DA and the dummy pixel region DMY, but these are not arranged in the peripheral region OP.

[0080] For example, the partitions 6 in the display region DA and the dummy pixel region DMY have the same opening pattern. That is, the partitions 6 have openings 71, 72, and 73 (first openings) in the subpixels SP1, SP2, and SP3, respectively, and openings 81, 82, and 83 (second openings) in the dummy subpixels DP1, DP2, and DP3, respectively. The openings 71, 72, and 73 have the same shapes as the openings 81, 82, and 83, respectively. The arrangement of the openings 71, 72, and 73 is also the same as the arrangement of the openings 81, 82, and 83.

[0081] The partition wall 6 has a plurality of openings 91 (third openings) provided in the outer peripheral region OP. These openings 91 are arranged at regular intervals in the X and Y directions. Each opening 91 has, for example, a rectangular shape that is elongated in the Y direction, but may have other shapes.

[0082] The display area DA is provided with the slits SLa and connection portions CT. The dummy pixel area DMY is also provided with the slits SLa and connection portions CT. On the other hand, in this embodiment, the slits SLa and connection portions CT are not provided in the outer peripheral area OP.

[0083] In this embodiment, the display area DA, the dummy pixel area DMY, and the outer peripheral area OP all have circular outer shapes. Such outer shapes can be realized by forming a stepped boundary between the display area DA and the dummy pixel area DMY, and a stepped boundary between the dummy pixel area DMY and the outer peripheral area OP, as shown in FIG.

[0084] In this way, when the boundary between the dummy pixel region DMY and the outer peripheral region OP is stepped, there is a location where the opening 82 in the dummy pixel region DMY and the opening 91 in the outer peripheral region OP are aligned in the X direction, as surrounded by a frame A. In this embodiment, no slit SLa is provided in such a location, i.e., between the openings 82 and 91 aligned in the X direction.

[0085] 7 is a schematic plan view showing an enlarged view of the boundary between the dummy pixel region DMY and the peripheral region OP. Similar to the subpixels SP1, SP2, and SP3, sealing layers SE11, SE12, and SE13 are disposed in the dummy subpixels DP1, DP2, and DP3, respectively. The sealing layer SE13 is continuous across a plurality of openings 82 aligned in the Y direction, for example.

[0086] 7, the sealing layers SE11, SE12, and SE13 do not overlap with the slit SLa. As another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SLa.

[0087] Each opening 91 in the peripheral region OP overlaps with the sealing layer SE1x. The sealing layer SE1x is separated from each of the sealing layers SE11, SE12, and SE13 at the boundary between the dummy pixel region DMY and the peripheral region OP. However, the sealing layer SE1x may overlap with at least one of the sealing layers SE11, SE12, and SE13 at the boundary.

[0088] Figure 8 is a schematic cross-sectional view of the dummy pixel region DMY and the peripheral region OP taken along line VIII-VIII in Figure 7. The substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layer RS2 are not shown in this figure. In the following description, the partition 6 disposed in the dummy pixel region DMY will be referred to as partition 6A, the partition 6 disposed in the peripheral region OP as partition 6B, and the partition 6 disposed at the boundary between the dummy pixel region DMY and the peripheral region OP as partition 6C.

[0089] The dummy subpixel DP1 includes a lower electrode LE1, a laminated film FL1, and a sealing layer SE11. The dummy subpixel DP2 includes a lower electrode LE2, a laminated film FL2, and a sealing layer SE12. In the example of FIG. 8, the rib layer 5 does not have a pixel opening in the dummy subpixels DP1 and DP2. Therefore, the lower electrode LE1 and the laminated film FL1 face each other via the rib layer 5. The lower electrode LE2 and the laminated film FL2 face each other via the rib layer 5.

[0090] The sealing layer SE11 continuously covers the stacked film FL1 and the surrounding partition wall 6A. The sealing layer SE12 continuously covers the stacked film FL2 and the surrounding partition walls 6A and 6C. In the example of FIG. 8, the ends of the sealing layers SE11 and SE12 overlap in the Z direction above the partition wall 6A. For example, a gap is formed between the sealing layer SE11 and the upper part 62 of the partition wall 6A. Gaps are also formed between the sealing layer SE12 and the upper parts 62 of the partition walls 6A and 6C, and between the end of the sealing layer SE11 and the end of the sealing layer SE12. At least a portion of these gaps may be filled with the resin layer RS1.

[0091] In the outer peripheral region OP, a stacked film FLx is disposed on the upper portion 62 of the partition wall 6B and in the opening 91. The sealing layer SE1x continuously covers the stacked film FLx, the partition wall 6B, and part of the partition wall 6C.

[0092] A laminated film FLxa is disposed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C. The laminated film FLxa is formed by, for example, deforming the laminated film FLx during the manufacturing process. Note that the laminated film FLxa may be lost during the manufacturing process. In this case, a gap is generated between the sealing layer SE1x and the partition wall 6C.

[0093] In this embodiment, the end Es of the sealing layer SE12 and the end Ex of the sealing layer SE1x are spaced apart on the partition wall 6C. The resin layer RS1 covers the sealing layers SE11, SE12, and SE1x. In addition, the resin layer RS1 covers the upper portion 62 of the partition wall 6C exposed from the sealing layers SE12 and SE1x in the region between the ends Es and Ex.

[0094] Next, an example of a method for manufacturing the display device DSP will be described. When manufacturing the display device DSP, a large mother substrate is fabricated on which a plurality of regions (panel portions) each including a portion corresponding to the display device DSP is formed.

[0095] 9 is a schematic plan view of a mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have another shape such as a circle.

[0096] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA surrounding the panel portions PP. In the example of Fig. 9, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, the arrangement of the plurality of panel portions PP on the mother substrate MB is not limited to this example. As another example, some panel portions PP may be lined up without blank areas BA between them.

[0097] 10 is a schematic plan view of the panel portion PP. The outer shape of the panel portion PP corresponds to the cutting lines CL1 for cutting out each panel portion PP from the motherboard MB.

[0098] The panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA in the panel unit PP corresponds to the area between the display area DA and the cut line CL1.

[0099] The peripheral area SA further has a cut line CL2 that defines the outline of the substrate 10 of the display device DSP. When manufacturing the display device DSP, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0100] The panel portion PP includes a dam structure DS2 in addition to the dam structure DS1 described above. The dam structure DS2 serves to block the resin layer RS2 before curing. For example, the dam structure DS2 includes multiple dam portions formed of the organic insulating layers 12 and 34, similar to the dam portions DM1, DM2, and DM3.

[0101] Dam structure DS1 is located between cut line CL2 and display area DA and surrounds display area DA. Dam structure DS2 is located between cut lines CL1 and CL2 and surrounds cut line CL2. In the example of Fig. 10, dam structures DS1 and DS2 join near terminal portion T, and this joined portion passes between terminal portion T and display area DA.

[0102] The majority of the cut line CL2 is located between the dam structures DS1 and DS2. However, in the example of Fig. 10, the cut line CL2 is located outside the dam structures DS1 and DS2 near the terminal portion T. In other words, the cut line CL2 crosses the dam structure DS2 near the terminal portion T.

[0103] Fig. 11 is a flowchart showing an example of a manufacturing method of the display device DSP. Fig. 12A to Fig. 12G are schematic cross-sectional views showing the manufacturing process of the display device DSP. Fig. 12A to Fig. 12G mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0104] In forming the panel portion PP, first, a circuit layer 11 including the inorganic insulating layers 31, 32, and 33, the organic insulating layer 34, and the metal layers 41, 42, and 43 is formed above the substrate 10 of the motherboard MB (step PR1 in FIG. 11). Further, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in FIG. 11). At this time, dam structures DS1 and DS2 are also formed.

[0105] After step PR2, as shown in FIG. 12A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in FIG. 11). Furthermore, as shown in FIG. 12A, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR4 in FIG. 11). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0106] After the rib layer 5 is formed, as shown in FIG. 12B, the partition walls 6 are formed on the rib layer 5 (step PR5 in FIG. 11). For example, to form the partition walls 6, layers of material for the bottom layer 63, the axis layer 64, the first top layer 65, and the second top layer 66 are formed over the entire mother substrate MB. Furthermore, a resist in the shape of the partition walls 6 is placed on these layers. The partition walls 6 can be formed by etching each layer using this resist as a mask.

[0107] 12C, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in FIG. 11). The pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6 are formed.

[0108] After step PR6, a step for forming display element DE1 is performed (step PR7 in FIG. 11). To form display element DE1, first, as shown in FIG. 12D, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0109] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including not only the display area DA of each panel unit PP but also the peripheral area SA and marginal area BA. The laminated film FL1 is divided by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided portion of the laminated film FL1 and the partition walls 6.

[0110] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist RT is disposed on the sealing layer SE11, as shown in Fig. 12D. The resist RT covers the subpixel SP1 and part of the partition wall 6 around it.

[0111] Then, an etching process is performed using the resist RT as a mask. As a result, as shown in FIG. 12E, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist RT are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist RT is removed (peeled off).

[0112] After step PR7, a step for forming display element DE2 is performed (step PR8 in FIG. 11). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0113] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 12F. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0114] After step PR8, a step for forming display element DE3 is performed (step PR9 in FIG. 11). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0115] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning such a laminated film FL3 and sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 12G. In FIG. 12G, a gap is formed under the sealing layer SE13 on the partition wall 6 between the subpixels SP1 and SP3. The laminated film FL3a shown in FIG. 3 may remain in this gap.

[0116] For example, in most of the peripheral area SA and the marginal area BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning. However, the portions of the stacked film FL3 and the sealing layer SE13 that cover the outer peripheral area OP are left. These remaining portions correspond to the stacked film FLx and the sealing layer SE1x described above.

[0117] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0118] After step PR9, a resin layer RS1 is formed (step PR10 in FIG. 11). The resin layer RS1 can be formed inside the dam structure DS1 by, for example, an inkjet method. After step PR10, a sealing layer SE2 is formed by, for example, CVD (step PR11 in FIG. 11).

[0119] After step PR11, etching is performed to remove the rib layer 5 and the sealing layer SE2 that cover the terminal portions T (step PR12 in FIG. 11). The etching is, for example, dry etching.

[0120] After step PR12, touch panel electrodes TP and touch panel wiring TPL are formed on the sealing layer SE2 (step PR13 in FIG. 11). Furthermore, a resin layer RS2 is formed (step PR14 in FIG. 11). The resin layer RS2 can be formed inside the dam structure DS2 by, for example, an inkjet method. The dam structure DS2 serves to block the resin layer RS2 before it hardens.

[0121] After step PR14, the mother substrate MB is cut along the cut lines CL1 (step PR15 in FIG. 11). Furthermore, the panel portion PP is cut along the cut lines CL2 (step PR16 in FIG. 11). This completes the display device DSP. For cutting in steps PR15 and PR16, for example, laser cutting, in which an infrared laser is irradiated along the cut lines CL1 and CL2, can be used. However, cutting in steps PR15 and PR16 may also be performed by other methods, such as scribe cutting.

[0122] According to the above-described embodiment, it is possible to improve the yield of the display device DSP. That is, the laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the base. Therefore, there is a possibility that the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel off from the base during the manufacturing of the display device DSP.

[0123] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are divided into small pieces by the partition walls 6. This prevents the peeling.

[0124] In this embodiment, the partition wall 6 having a plurality of openings 91 is also arranged in the outer peripheral region OP. This allows the stacked films FL1, FL2, FL3 to be finely divided also in the outer peripheral region OP, thereby suppressing the peeling.

[0125] Furthermore, with the configuration of the display device DSP according to this embodiment, it is possible to obtain the effects described below, for example. 13 is a schematic plan view showing a configuration according to a comparative example of this embodiment, which focuses on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in FIG.

[0126] In this comparative example, the slits SLa are also provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP. That is, there are locations where the slits SLa are located between the openings 82 and 91 aligned in the X direction.

[0127] Fig. 14 is a schematic cross-sectional view of the dummy pixel region DMY and the peripheral region OP taken along line XIV-XIV in Fig. 7. In this comparative example, the portion corresponding to the partition wall 6C in Fig. 7 is divided into partition walls 6C1 and 6C2 by a slit SLa. Furthermore, the end Es of the sealing layer SE12 is located on the partition wall 6C1, and the end Ex of the sealing layer SE1x is located on the partition wall 6C2.

[0128] When the resin layer RS1 is formed by the inkjet method, droplets of a resin material are ejected onto the display area DA, the dummy pixel area DMY, and the peripheral area OP. Typically, these droplets wet and spread on the sealing layers SE11, SE12, SE13, and SE1x, covering the entire inside of the dam structure DS1.

[0129] However, the opening patterns of the partition walls 6 are different between the dummy pixel region DMY and the peripheral region OP. As a result, the unevenness appearing on the upper surfaces of the sealing layers SE11, SE12, and SE13 in the dummy pixel region DMY differs from the unevenness appearing on the upper surface of the sealing layer SE1x in the peripheral region OP. If the shape of the base of the resin layer RS1 differs in this way, it may affect the way droplets spread near the boundary between the dummy pixel region DMY and the peripheral region OP.

[0130] 14, a steep step formed by the partition wall 6C1 and the end Es of the sealing layer SE12 and a steep step formed by the partition wall 6C2 and the end Ex of the sealing layer SE1x occur on both sides of the slit SLa. If such a step is formed at the boundary between the dummy pixel region DMY and the outer peripheral region OP, where the droplet spreading pattern changes, the droplet may not spread beyond the slit SLa. In this case, as shown in FIG. 14, a coating gap where the resin layer RS1 is partially missing occurs near the slit SLa.

[0131] The missing coating portion may cause the touch panel wiring TPL formed above the resin layer RS1 to have a defective shape or to be broken. The missing coating portion may also cause unevenness in the appearance of the display device DSP or create a path for moisture penetration.

[0132] In contrast, in this embodiment, no slit SLa is provided at the boundary between the dummy pixel region DMY and the peripheral region OP. Therefore, a steep step as shown in the comparative example does not occur. This makes it easier for droplets of the resin layer RS1 to spread beyond the boundary when applied, thereby suppressing the occurrence of coating gaps.

[0133] In addition, by suppressing the occurrence of coating voids, it is possible to suppress poor coating of liquid resins such as various resists that are applied after the formation of the resin layer RS1. Examples of such liquid resins include resists for processing the rib layer 5 and the sealing layer SE2 in step PR12, and resists for processing the touch panel electrodes TP and the touch panel wiring TPL in step PR13.

[0134] The display device DSP may include a plurality of color filters corresponding to the colors of the subpixels SP1, SP2, and SP3, and a black matrix located at the boundaries of the subpixels SP1, SP2, and SP3. For example, these color filters and black matrix may be disposed above the sealing layer SE2. By suppressing the occurrence of coating voids in the resin layer RS1, it is possible to suppress poor coating of the resin that is the material for these color filters and black matrix.

[0135] [Second embodiment] Fig. 15 is a schematic plan view showing a configuration according to the second embodiment. Fig. 16 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP taken along line XVI-XVI in Fig. 15. In these figures, attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in Figs. 7 and 8.

[0136] In this embodiment, as in the comparative example described above, a slit SLa is also provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP. That is, there is a portion where the slit SLa extends in the Y direction through between the openings 82 and 91 aligned in the X direction. However, in this embodiment, this slit SLa is covered with the sealing layer SE1x.

[0137] 16, partition walls 6C1 and 6C2 separated by a slit SLa are arranged near the boundary between the dummy pixel region DMY and the outer peripheral region OP. A stacked film FLx is arranged in the slit SLa. A sealing layer SE1x fills the slit SLa.

[0138] The end portion Ex of the sealing layer SE1x is located above the partition wall 6C1. In the example of FIG. 16, the end portion Ex overlaps the end portion Es of the sealing layer SE12 in the Z direction. A stacked film FLxa is disposed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C1. As another example, a gap may be formed between the sealing layer SE1x and the upper portion 62 of the partition wall 6C1. Furthermore, at least a portion of this gap may be filled with a resin layer RS1.

[0139] The configurations shown in FIGS. 15 and 16 can be applied to each position where the openings 82 and 91 are aligned in the X direction on the boundary between the dummy pixel region DMY and the outer peripheral region OP (for example, the area surrounded by frame A in FIG. 6).

[0140] Even when a slit SLa is provided at the boundary between the dummy pixel region DMY and the outer peripheral region OP as in this embodiment, the slit SLa is covered with the sealing layer SE1x, thereby suppressing the steep step as shown in the comparative example of Fig. 14. Therefore, it is possible to suppress the occurrence of coating voids in the resin layer RS1.

[0141] [Third embodiment] Fig. 17 is a schematic plan view showing a configuration according to a third embodiment. Fig. 18 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP taken along line XVIII-XVIII in Fig. 17. In these figures, attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in Figs. 7 and 8.

[0142] In this embodiment, as in the first embodiment, no slit SLa is provided between the dummy pixel region DMY and the outer peripheral region OP. On the other hand, as in the second embodiment, the end Ex of the sealing layer SE1x overlaps the end Es of the sealing layer SE12 in the Z direction. Even with this configuration, as in the above-mentioned embodiments, it is possible to suppress the occurrence of coating voids in the resin layer RS1.

[0143] [Fourth embodiment] 19 is a schematic plan view showing a configuration according to the fourth embodiment, in which attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in FIG.

[0144] In this embodiment, the slits SLa extend across the dummy pixel region DMY and the outer peripheral region OP. Each slit SLa passes between the openings 91 adjacent to each other in the X direction in the outer peripheral region OP. At least one of the multiple slits SLa may reach an end of the outer peripheral region OP.

[0145] Each slit SLa in the outer peripheral region OP is covered with the sealing layer SE1x. As in the third embodiment, the slits SLa located at the boundary between the dummy pixel region DMY and the outer peripheral region OP (the slits SLa located between the openings 82 and 91 in the X direction) are also covered with the sealing layer SE1x. Even with this configuration, as in the above-described embodiments, it is possible to suppress the occurrence of coating voids in the resin layer RS1.

[0146] [Fifth embodiment] 20 is a schematic plan view showing a configuration according to the fifth embodiment, in which attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in FIG.

[0147] In this embodiment, the slits SLa extend across the dummy pixel region DMY and the outer peripheral region OP, as in the fourth embodiment. Furthermore, in this embodiment, the openings 91 and the slits SLa are connected by slits SLx extending in the X direction.

[0148] In the example of Fig. 20, the slit SLx intersects with the slit SLa and is connected to two openings 91. However, the slit SLx near the center of Fig. 20 is connected to the slit SLa in a T-shape.

[0149] In the outer peripheral region OP, the slits SLa, the slits SLx, and the opening 91 are covered with the sealing layer SE1x. As a result, recesses are formed on the upper surface of the sealing layer SE1x according to the shapes of the slits SLa, the slits SLx, and the opening 91. Droplets ejected during the formation of the resin layer RS1 flow along these recesses and are therefore more likely to spread over the entire outer peripheral region OP.

[0150] [Sixth embodiment] 21 is a schematic plan view showing a configuration according to the sixth embodiment, in which attention is focused on the vicinity of the boundary between the dummy pixel region DMY and the outer peripheral region OP, as in FIG.

[0151] In this embodiment, as in the fifth embodiment, the slits SLa extend across the dummy pixel region DMY and the outer peripheral region OP, and the openings 91 and the slits SLa are connected by the slits SLx extending in the X direction.

[0152] Furthermore, in this embodiment, connection portions CT that connect the portions of the partition walls 6 separated by the slits SLa are also provided in the outer peripheral region OP. For example, the arrangement intervals of the connection portions CT in the Y direction are the same in each of the display region DA, the dummy pixel region DMY, and the outer peripheral region OP. At least one opening 91 is connected to the slits SLa separated by the connection portions CT. However, there may be slits SLa in the outer peripheral region OP that are not connected to an opening 91.

[0153] The configurations disclosed in the first to sixth embodiments can be combined as appropriate. For example, the configuration of one of the embodiments may be applied to a part of the outer peripheral region OP, and the configuration of another embodiment may be applied to another part.

[0154] In each embodiment, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a shape different from the partition wall disclosed in each embodiment, the part that protrudes to the side corresponds to the "upper part," and the part that recedes below the part that protrudes to the side corresponds to the "lower part."

[0155] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices disclosed in each embodiment also fall within the scope of the present invention as long as they include the gist of the present invention.

[0156] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0157] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0158] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE1x, SE2...sealing layer, RS1, RS2...resin layer, MB...motherboard, PP...panel portion, 5...rib layer, 6...partition wall, 61...lower portion, 62...upper portion, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a substrate having a display area for displaying an image; a plurality of pixels arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a dummy pixel area including a plurality of dummy pixels that do not display an image and surrounding the display area; a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall being provided in the display region, the dummy pixel region, and an outer peripheral region surrounding the dummy pixel region; Equipped with the partition wall has a plurality of slits provided in the display region and the dummy pixel region, the slit is not provided at the boundary between the dummy pixel region and the outer peripheral region; Display device.

2. The partition wall is a plurality of first openings provided in the display region, each of the plurality of pixels; a plurality of second openings provided in the plurality of dummy pixels in the dummy pixel region; a plurality of third openings provided in the outer peripheral region; It has The display device according to claim 1 .

3. the boundary between the dummy pixel region and the outer peripheral region is stepped; the second opening and the third opening are aligned in a first direction in a part of the boundary; the plurality of slits extend in a second direction intersecting the first direction, and are not provided between the second opening and the third opening aligned in the first direction; The display device according to claim 2 .

4. a first sealing layer formed of an inorganic insulating material and covering the plurality of pixels and the plurality of dummy pixels; a second sealing layer formed of an inorganic insulating material and covering the outer peripheral region; a resin layer covering the first sealing layer and the second sealing layer; It further comprises: The display device according to claim 1 .

5. the first sealing layer and the second sealing layer are spaced apart from each other at the boundary between the dummy pixel region and the outer peripheral region; The display device according to claim 4 .

6. the resin layer covers the partition wall exposed from the first sealing layer and the second sealing layer at the boundary between the dummy pixel region and the outer peripheral region. The display device according to claim 5 .

7. the first sealing layer and the second sealing layer overlap each other at the boundary between the dummy pixel region and the outer peripheral region; The display device according to claim 4 .

8. the partition wall has a connection portion that connects the portions separated by the slits in the display region and the dummy pixel region. The display device according to claim 1 .

9. the display region, the dummy pixel region, and the outer peripheral region are circular; 9. The display device according to claim 1.

10. a substrate having a display area for displaying an image; a plurality of pixels arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a dummy pixel area including a plurality of dummy pixels that do not display an image and surrounding the display area; a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall being provided in the display region, the dummy pixel region, and an outer peripheral region surrounding the dummy pixel region; a first sealing layer formed of an inorganic insulating material and covering the plurality of pixels and the plurality of dummy pixels; a second sealing layer formed of an inorganic insulating material and covering the outer peripheral region; Equipped with the partition wall has a plurality of slits provided at least in the display region and the dummy pixel region; at least one of the plurality of slits is located at a boundary between the dummy pixel region and the outer peripheral region; The second sealing layer covers the slit located at the boundary. Display device.

11. the first sealing layer and the second sealing layer overlap each other at the boundary between the dummy pixel region and the outer peripheral region; The display device according to claim 10.

12. At least one of the plurality of slits extends to the outer circumferential region. The display device according to claim 10.

13. the second sealing layer covers the slit located in the outer peripheral region. The display device according to claim 12.

14. The partition wall is a plurality of first openings provided in the display region, each of the plurality of pixels; a plurality of second openings provided in the plurality of dummy pixels in the dummy pixel region; a plurality of third openings provided in the outer peripheral region; It has The display device according to claim 12.

15. the boundary between the dummy pixel region and the outer peripheral region is stepped; the second opening and the third opening are aligned in a first direction in a part of the boundary; At least one of the plurality of slits passes between the second opening and the third opening which are aligned in the first direction and extends in a second direction intersecting the first direction. The display device according to claim 14.

16. At least one of the plurality of slits extends between the third openings adjacent to each other in the first direction in the outer peripheral region. The display device according to claim 15.

17. At least one of the plurality of third openings is connected to the slit located in the outer circumferential region. The display device according to claim 16.

18. the partition wall has a connecting portion that connects the portions separated by the slit located in the outer peripheral region. The display device according to claim 16.

19. Further comprising a resin layer covering the first sealing layer and the second sealing layer. The display device according to claim 10.

20. the display region, the dummy pixel region, and the outer peripheral region are circular; 20. A display device according to any one of claims 10 to 19.

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