Semiconductor Devices

Abstract

A semiconductor device is provided that reduces variations in luminance of light-emitting elements between pixels due to variations in threshold voltage of transistors. [Solution] In a pixel 10, a plurality of switches control their conduction states independently of one another. Switches SW1, SW4, and SW3 are electrically connected in series between a wiring SL and a wiring PLb. Switch SW5 controls the conduction state between a light-emitting element EL1 and a wiring PLc. A transistor M2 has a gate electrically connected to a node N2 electrically connected to switches SW4 and SW5, one of its source and drain electrically connected to the wiring PLa, and the other electrically connected to the light-emitting element. A capacitor C1 has a first electrode and a second electrode, the first electrode electrically connected to a node N3 electrically connected to switches SW1 and SW4, and the second electrode electrically connected to the light-emitting element.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a driving method thereof, a manufacturing method thereof, and the like.

[0002] It should be noted that one embodiment of the present invention is not limited to the above technical fields. One aspect of the technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter Therefore, the technical field of one embodiment of the present invention disclosed in this specification is Examples of such devices include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, and memory devices. Examples include devices, driving methods thereof, and manufacturing methods thereof. [Background technology]

[0003] Regarding the pixels of active matrix display devices that use light-emitting elements, each manufacturer has different Generally, a pixel has a light emitting element, a video signal input to the pixel, and a circuit configuration. a transistor (switching transistor) that controls the At least a transistor (driving transistor) for controlling the current is provided. The source-drain current (hereinafter sometimes referred to as drain current) that flows through a transistor By supplying the light emitting element with this, the light emitting element emits light at a brightness according to the value of the drain current. The drain current value of the driving transistor is controlled by the potential of the video signal.

[0004] Therefore, in a plurality of pixels that constitute the screen of the display device, the threshold voltage of the driving transistor is If there is a variation in the value voltage, even if a video signal with the same potential is supplied to these pixels, the light-emitting elements The threshold voltage of the driving transistors among multiple pixels varies. Variations in pressure are one of the causes of a decrease in the display quality of a display device. Active matrix display devices are being promoted to have more pixels in order to achieve higher resolution, and A display device has hundreds of thousands to tens of millions of pixels. For ll-HD, it is 1366 x 768 x 3 (RGB) = 1,049,088, and 8 For k4k (Super Hi-Vision), it is 7,680 x 4,320 x 3 (RGB) = 3 The number of pixels is 3,177,600. It is very difficult to perfectly match the threshold voltages. In order to suppress the effect of the pixel, a pixel capable of correcting the threshold voltage of the driving transistor is proposed. It has been proposed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256032 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-137498 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel driving method thereof, or a novel For example, an object of one embodiment of the present invention is to improve display quality. To provide a semiconductor device or a driving method thereof that can improve the To provide a device or a driving method thereof, or to suppress variations in luminance of each pixel To provide a semiconductor device or a driving method thereof that can reduce the number of terminals. and to provide a semiconductor device capable of achieving this and a method for driving the same.

[0007] It should be noted that the description of multiple problems does not preclude the existence of each other's problems. The form does not necessarily solve all of the problems exemplified. From the description of the above, problems other than those exemplified will become clear, and these problems are also within the scope of the present invention. This can be a form of challenge. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device including a first transistor and a first capacitor having first and second electrodes. a semiconductor device having a pixel electrode, first to fourth switches, and first to fourth wirings; The first to fourth switches are capable of controlling the conduction states independently of each other. The first switch, the third switch, and the second switch are The first switch is electrically connected in series between the first wiring and the third wiring, and the third switch is electrically connected in series between the first wiring and the third wiring. a first electrode electrically connected to a first node electrically connected to the switch; The fourth switch has a function of controlling the conduction state between the pixel electrode and the fourth wiring. The second electrode is electrically connected to the pixel electrode, and the third switch and the second switch are electrically connected to each other. The gate of the first transistor is electrically connected to a second node connected to the One of the source and the drain of the first transistor is electrically connected to the second wiring. The other of the source and drain of the first transistor is electrically connected to the pixel electrode. A semiconductor device characterized by:

[0009] In the above embodiment, the second to fifth transistors functioning as the first to fourth switches are In this case, the first to fifth transistors may have a region where a channel is formed. Alternatively, in the above embodiment, the pixel electrode may include an oxide semiconductor layer containing the oxide semiconductor layer. The light emitting element may be included.

[0010] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. This refers to semiconductor elements such as transistors and diodes, as well as semiconductor circuits and arithmetic units. A memory device, an imaging device, a display device, a light-emitting device, and the like are all embodiments of the semiconductor device. Image devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (thin-film solar cells, (including organic thin-film solar cells, etc.), electronic devices, electrical devices, and mechanical devices, etc. There are cases where they have.

[0011] In this specification, a display device or a light-emitting device includes a panel having pixels in which display elements are formed. A panel in which an IC including a driver circuit or controller is mounted on the panel. In the case of a light-emitting device, the display element is composed of a light-emitting element. In addition, in the display device or light-emitting device, the panel An element substrate corresponding to a form before the display element is completed, and a display element corresponding to a form before the display element is completed For example, the element substrate includes a transistor and a substrate a semiconductor device in which a pixel electrode to which a potential or current is supplied is fabricated on the same substrate as the pixel electrode; The pixel electrodes correspond to the electrodes that constitute the display elements.

[0012] In this specification, ordinal numbers such as first, second, third, etc., do not only indicate order but also indicate composition. In some cases, ordinal numbers are used to avoid confusion between elements. In this case, the use of ordinal numbers indicates the individuality of the components. It does not limit the number. For example, "first" can be changed to "second" or "third" as appropriate. The above can be substituted to describe one aspect of the invention.

[0013] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. , including cases where the angle is between 85° and 95°.

[0014] In addition, in this specification and the like, when a crystal is a trigonal or rhombohedral crystal, the crystal is referred to as a hexagonal crystal. Express it as a system.

[0015] In this specification, when it is explicitly stated that X and Y are connected, are electrically connected, X and Y are functionally connected, and X and Y are Here, X and Y are the object (for example, (device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). The specific connection relationships, for example, are not limited to the connection relationships shown in the drawings or text, but are not limited to the connection relationships shown in the drawings or text. Connections other than those shown are also included.

[0016] In a circuit, components are electrically connected if a current, voltage, or potential flows through them. This includes being configured to be able to transmit or make it possible to transmit. In a circuit, two components are said to be connected if they are directly connected to each other. It is possible to supply or transmit, but is not limited to, a current, a voltage, or a potential. In this way, they are electrically connected through elements such as wiring, resistors, diodes, and transistors. A connected configuration is also included in this category.

[0017] Also, even if components that are independent on the circuit diagram are connected, For example, when a part of the wiring also functions as an electrode, one conductive film is connected to a plurality of components. In this specification, connection means a connection between two conductive members. A membrane that combines the functions of multiple components is also included in this category.

[0018] For example, if the source (or first terminal, etc.) of the transistor is connected to the (without an intervening resistor), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z2 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0019] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. It can be expressed as "electrically connected to the source of the transistor." (or first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor is connected to X. The transistor drain (or second terminal, etc.) and Y are electrically connected in this order. "X is connected to the source ( or the first terminal) and the drain (or the second terminal) X is the source (or first terminal, etc.) of the transistor, and the drain The terminal (or second terminal, etc.), Y, can be expressed as "provided in this connection order." Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal. The expression methods are only examples, and the present invention is not limited to these. Z2 is the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) Let's say there is.

[0020] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. It refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or Voltage may be read as potential.

[0021] A transistor has three terminals called the gate, source, and drain. The two terminals that function as the source and drain are determined by the transistor channel type and the Depending on the level of the potential applied to the Generally, in an n-channel transistor, the source is given a low potential. The terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In a p-channel transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the drain. The terminal to which the potential is given is called the source. Therefore, we will limit the explanation to one of the two terminals of a transistor being the source and the other being the drain. Of course, depending on the driving method, the voltage applied to each terminal of the transistor may The pressure relationship may change, and the source and drain may be swapped.

[0022] In the following, to make it easier to understand the circuit configuration and its operation, one of the two terminals of the transistor is In some cases, the explanation will be limited to the source and the drain. In this case, the terminal (electrode) to which high-level (H-level) signals and power supply potential are mainly input. is called the drain, and low-level (L-level) signals and power supply potentials are mainly input. The terminal (electrode) is called the source. In the case of a p-channel transistor, the opposite is true. Of course, depending on the driving method, the magnitude of the voltage applied to each terminal of the transistor may change. The relationship between the source and drain may change, and the source and drain may be interchanged. In this case, the distinction between the source and drain of a transistor is not limited to the description in the specification. There is no.

[0023] In one embodiment of the present invention, various types of switches can be used. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. For example, it allows current to flow through path 1, It has the function of selecting and switching whether to allow current to flow through path 2. As an example of the switch, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current. An example of a switch is a transistor (e.g., a bipolar transistor, a MOS (Metal Oxide Semiconductor) transistors, diodes diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM ( Metal Insulator Metal Diode, MIS (Metal In sulator semiconductor diode, diode-connected transistor Examples of mechanical switches include: For example, MEMS (microelectromechanical systems) such as digital micromirror devices (DMDs) There are switches that use electro-mechanical system (ELECTRO-MECHANICAL) technology. The electrode can be moved automatically, and the movement of the electrode controls conduction and non-conduction. It operates under control.

[0024] In one aspect of the present invention, the device structure of a capacitor that is intentionally provided as an element is There is no restriction on the number of stages. For example, MIM type capacitors can be used, and MOS type capacitors can also be used. can also be used. [Effects of the Invention]

[0025] According to one embodiment of the present invention, a novel semiconductor device, a novel driving method thereof, or a novel semiconductor device For example, one embodiment of the present invention can improve the display quality. To provide a semiconductor device or a driving method thereof with improved performance, It is possible to provide a driving method for the same, or to suppress variations in brightness between pixels. To provide a semiconductor device capable of reducing the number of terminals or a driving method thereof It is possible to provide a semiconductor device capable of driving the same, and the like.

[0026] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of the effects exemplified. Problems, advantages, and novel features other than those mentioned above will be described in the description and drawings of this specification. This will become clear from the above. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel. [Figure 3] 10 is a timing chart showing an example of a method for driving a pixel. [Figure 4] A and B: Circuit diagram showing an example of pixel operation. [Figure 5] A and B: Circuit diagram showing an example of pixel operation. [Figure 6] FIG. 1 is a circuit diagram showing an example of the operation of a pixel. [Figure 7] FIG. 1 is a block diagram showing an example of the configuration of a display device. [Figure 8] FIG. 1 is an exploded perspective view showing an example of the configuration of a display device. [Figure 9] 1A-1D are plan views showing an example of the configuration of a display panel. [Figure 10] FIG. 2 is a diagram showing an example of the configuration of a display panel (element substrate). [Figure 11] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel. [Figure 12] FIG. 2 is a circuit diagram showing an example of the configuration of a gate driver circuit (GDL, GDR). [Figure 13] A: A block diagram showing an example of the configuration of a basic circuit (GSR) of GDL and GDR. B: A block diagram showing an example of the configuration of a dummy basic circuit (dumGSR) of the same. [Figure 14] FIG. 1 is a circuit diagram showing an example of the configuration of a GSR. [Figure 15] FIG. 1 is a circuit diagram showing an example of the configuration of dumGSR. [Figure 16] A: Block diagram showing an example of the configuration of the basic circuit (GdINV) of GDL and GDR. B: Circuit diagram showing an example of the configuration of GdINV. [Figure 17] 10 is a timing chart showing an example of a method for driving the GDL and GDR. [Figure 18] FIG. 2 is a block diagram showing an example of the configuration of a circuit SSDC1_O. [Figure 19] FIG. 2 is a block diagram showing an example of the configuration of a circuit SSDC1_E. [Figure 20] A: Block diagram showing an example of the configuration of the basic circuit (SSD) of SSDC1_O and SSDC1_E. B: Circuit diagram showing an example of the configuration of the SSD. [Figure 21] 4 is a timing chart showing an example of a method for driving an SSD and a display panel. [Figure 22] 4 is a timing chart showing an example of a method for driving an SSD and a display panel. [Figure 23] FIG. 2 is a block diagram showing an example of the configuration of a display panel (element substrate). [Figure 24] A: Block diagram showing an example of the configuration of a basic circuit (SSD). B: Circuit diagram showing an example of the configuration of an SSD. [Figure 25] FIG. 1 is a cross-sectional view showing an example of the configuration of a display panel. [Figure 26] 1A and 1B are plan views showing an example of a pixel configuration. [Figure 27] AE: Plan views showing an example of a method for manufacturing an element substrate. [Figure 28] AE: Plan views showing an example of a method for manufacturing an element substrate. [Figure 29] 1A and 1B are plan views showing an example of the structure of a transistor, and 1C and 1D are cross-sectional views showing an example of the structure of a transistor. [Figure 30] 1A and 1B are plan views showing an example of a transistor configuration. [Figure 31] 1A and 1B are cross-sectional views showing an example of the structure of a transistor. [Figure 32] FIG. 1 is a cross-sectional view illustrating an example of the structure of a transistor. [Figure 33] 1A to 1D are cross-sectional views showing an example of a method for manufacturing a display panel. [Figure 34] 1A and 1B are cross-sectional views showing an example of a method for manufacturing a display panel. [Figure 35] 1A to 1D are cross-sectional views showing an example of a method for manufacturing a display panel. [Figure 36] 1A and 1B are diagrams illustrating an example of the configuration of a display device. [Figure 37] FIG. 2 illustrates an example of the configuration of a circuit board of a display device. [Figure 38] AE: A diagram for explaining an example of the configuration of an information processing device. [Figure 39] AF: A diagram illustrating an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and does not deviate from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the form and details thereof. Therefore, one embodiment of the present invention should be construed as being limited to the description of the following embodiment. isn't it.

[0029] In addition, several embodiments of the present invention will be described below, and the embodiments may be combined appropriately. In addition, when several configuration examples are shown in one embodiment, The configuration examples can be combined as appropriate.

[0030] In the drawings used to explain the embodiments of the present invention in this specification, the same parts or Parts having similar functions are given the same reference numerals, and repeated explanations may be omitted. do.

[0031] In this specification, the clock signal CLK is abbreviated to simply the signal CLK, CLK, etc. This also applies to other signals, voltages, potentials, circuits, elements, etc. It seems that

[0032] (Embodiment 1) In this embodiment, a light-emitting device having a light-emitting element will be described as an example of a semiconductor device. The light-emitting device of this embodiment mode can function as a display device.

[0033] <<Pixel configuration example 1>> An example of the pixel configuration of a light-emitting device is shown in Fig. 1. As shown in Fig. 1, a pixel 10 includes a switch SW1, switch SW3, switch SW4, switch SW5, transistor M2, capacitor The pixel 10 includes a wiring SL, a wiring PLa, a wiring P The pixel portion of the light emitting device is arranged in an array. It comprises a plurality of pixels 10 arranged in a row.

[0034] The conduction state of SW1 is controlled by a signal Sa. The conduction state of SW3 is controlled by a signal Sb. The conductive state of SW4 is controlled by a signal Sd. The conductive state of switch SW5 is controlled by a signal Sd. In the example of Figure 1, four switches (SW1, SW3, SW4, S W5) have their conduction states controlled by different signals.

[0035] The data signal DATA is a signal that represents a gray scale, and the wiring SL transmits the data signal DATA to the pixel. 10. and the wiring PLc supply the potential VA, the potential V0, and the potential V1 to the pixel 10, respectively. The wiring (PLa, PLb, PLc) can function as wiring for connecting the pixels. It is also possible to make it function as a wiring for supplying signals to 10.

[0036] As shown in FIG. 1, node N1 is an input node for a signal DATA. The node N3 and the node N4 are the gate of the transistor M2. The light-emitting element EL1 has a pair of terminals (anode and cathode). The node N4 corresponds to one terminal of the light-emitting element EL. The terminal is supplied with a potential VC.

[0037] The light-emitting element EL1 is an element whose luminance can be controlled by current or voltage. The light emitting element EL1 can be a light emitting diode (LED). Diode) and OLED (Organic Light Emitting Diode) For example, in the case of an OLED, the light-emitting element EL1 is an EL (electro The device has at least an EL layer, an anode, and a cathode. The EL layer is a layer containing a light-emitting substance ( The light-emitting layer is at least

[0038] One of the source and drain of the transistor M2 is connected to the wiring PLa, and the other is connected to the node SW1, SW4 and SW3 are connected in series. The junction between the switches SW3 and SW4 is the gate of the transistor M2. The connection between the switch SW1 and the switch SW4 is connected to the capacitor (node ​​N2). This is connected to the terminal (node ​​N3) of the capacitor C1.

[0039] SW1 functions as a switch that controls the conduction state between the wiring SL and the node N3. 1 controls the supply of the signal DATA to the pixel 10. SW3 is connected to the node N2 via a wiring SW3 controls the conduction state between PLb and PLb. SW3 resets the potential of node N2 to a constant potential V0. SW4 controls the conduction state between node N3 and node N2. It also functions as a switch that controls the output of the power supply. The reset circuit functions as a reset circuit that resets the potential of node N3 to a constant potential (V0). SW5 controls the conduction state between node N4 and wiring PLc. SW5 functions as a reset circuit that resets the potential of node N4 to a fixed potential (V1). The capacitor C1 is a storage capacitor for holding the potential of the node N4. It is possible to function as

[0040] The drain current of transistor M2 (hereinafter sometimes referred to as "drain current Id2") As a result, the potential of the node N4 changes. When the potential difference changes and becomes equal to or greater than the threshold voltage VthEL of the light-emitting element EL1, The photo element EL1 emits light. The drain current Id2 is controlled by the potential of the node N2. The potential of the node N2 is controlled to a value corresponding to the potential of the signal DATA supplied from the line SL. The transistor M2 is a transistor corresponding to the driving transistor. The variation in the threshold voltage of transistor M2 between these pixels 10 Therefore, the pixel 10 corrects the threshold voltage of the transistor M2. Specifically, it is composed of switches SW3-SW5 and a capacitor C1. This threshold voltage is corrected by the circuitry in the switches SW3-SW5 and the capacitors The circuit consisting of transistor C1 controls the conduction state of switches SW3-SW5. The function of charging and discharging the charge held at the gate of transistor M2 (node ​​N2) is A specific circuit configuration of the pixel 10 will be shown below, and the functions of the pixel 10 will be described.

[0041] <Pixel circuit configuration example> 2 shows an example of a more specific circuit configuration of the pixel 10. The pixel 20 in FIG. Four switches (SW1, SW3, SW4, SW5) are connected to transistors (M1, M3, M4 , M5). As shown in FIG. 2, the pixel 20 corresponds to a circuit configured with five transistors. (M1, M2, M3, M4, M5), a capacitor C1, and a light-emitting element EL1. In the example of Figure 2, the transistors M1-M5 are n-channel transistors. The anode of the light-emitting element EL1 corresponds to the node N4. A potential VC is supplied to the cathode of the light-emitting element EL1. As will be described later, the light emitting device has a pixel section in which a plurality of pixels 20 are arranged in an array. In the pixel section, the cathode of each light-emitting element EL1 can be configured as one common electrode. In this case, the circuit configuration is such that a potential VC is supplied to the common electrode.

[0042] The gate of the transistor M1 is connected to the wiring GLa, and the gate of the transistor M3 is connected to the wiring G The gate of the transistor M4 is connected to the wiring GLd, and the gate of the transistor M5 The gates of the transistors (M1, M3, M4, M 5) The conduction state is input from the wiring (GLa, GLb, GLd, GLc) respectively. In this example, the wiring GLa, the wiring GLb, the wiring GLc, and the wiring GLd are input with the signals Sa, Sb, Sc, and Sd, respectively.

[0043] <Example of pixel driving method> An example of a method for driving the pixel 20 will be described with reference to FIGS.

[0044] 3 shows an example of a method for driving the pixel 20. In FIG. 3, the pixel 20[k , j] (k, j are integers equal to or greater than 1). , the signal (Sa , Sb, Sc), and the signal DATA input to the wiring SL[j] in the j-th column. .

[0045] In the following description, the lines, pixels, signals, etc. will be identified using row numbers and / or column numbers. Therefore, we will use identification symbols such as [k] and [k, j].

[0046] As shown in FIG. 3, the operation of the pixel 20 is performed in periods T1, T2, T3, and T4. These operations are explained with reference to Figs. 4 to 6. 4-6, in order to facilitate understanding of the operation of pixel 20, four transistors are shown as in FIG. The transistors (M1, M3, M4, M5) are represented by the circuit symbol of the switch. We distinguish between the source (S) and drain (D) of transistor M2. In the transistor M2, the terminal connected to the wiring PLa is the drain, and the light-emitting element EL The terminal connected to the anode of 1 (node ​​N4) is the source.

[0047] [Period T1: Initialization operation] The period T1 is an initial period in which the potentials of the nodes N1, N3, and N4 of the pixel 20 are initialized. FIG. 4A shows the operation of the pixel 20 during the initialization period T1. T1 corresponds to the period when the signal Sc is at a high level. T2 corresponds to the period when the signal Sa is at a low level. At any timing of T1, the signals Sb, Sc, and Sd are at high level. In this case, the signal Sb is required to transition from a low level to a high level. In the initialization operation, the transistor M1 is in a non-conductive state. The transistors M3, M5, and M4 are in a conducting state. When the transistor M4 is turned on, the potential Vn2 of the node N2 and the potential Vn3 of the node N3 n3 is reset to V0. Transistor M5 is turned on, and node N4 The potential Vn4 is reset to V1.

[0048] The potentials V0, V1, and VC are set to values ​​that satisfy the following formulas (1) and (2). In 2), Vth2 is the threshold voltage of transistor M2, and VthEL is the light-emitting diode (LED). The threshold voltage of the element EL1 is the threshold voltage at which the light emitting element is in the light emitting state. The potential difference between the cathode and anode of the light-emitting element EL1 is V When the voltage reaches thEL or higher, the light emitting element EL1 is in a light emitting state.

[0049] (V0-Vth2)-VC<VthEL ···(1) V0-Vth2> V1 (2)

[0050] By satisfying the formula (1), the light-emitting element EL is in a non-emitting state at T1, T2, and T3. Furthermore, by satisfying the formula (2), the The gate-source voltage Vgs2 of transistor M2 is greater than Vth2, so The second power supply M2 can be brought into a conducting state.

[0051] [Period T2: Threshold voltage correction operation] T2 is the period during which the threshold voltage of the transistor M2 is corrected. 10 is a diagram illustrating the operation of the pixel 20 in the low-value voltage correction period T2. The potential levels of other signals (Sa, Sb, Sd) change. The transistor M5 goes from a conducting state to a non-conducting state. In T2, the state of transistors M3 and M4 is the same as in T1. Since the conduction state of the transistor M4 is maintained, Vn2 and Vn3 do not change and remain at V0. Since gs2 is higher than Vth2, transistor M2 is in a conducting state and the drain current I This drain current Id2 charges the capacitor C1, The potential Vn4 of the source (node ​​N4) of transistor M2 rises. Vgs2=Vn2-Vn4 of transistor M2 drops. Vgs2 drops to Vth2. Then, the drain current Id2 of the transistor M2 does not flow. The potential Vn4 of the source (node ​​N4) becomes V0-Vth2.

[0052] The threshold voltage correction operation is performed by adjusting the drain current supplied to the light emitting element EL1 during the light emitting period (FIG. 6). This is an operation to make Id2 a value that is not affected by Vth2. This causes the potential (Vn4) of the source of the transistor M2 to be set to a potential corresponding to Vth2. More specifically, the source potential Vn4 is changed from a certain constant potential (V0) to a This is an operation to set the potential to a value obtained by dividing the threshold voltage Vth2 of the transistor M2.

[0053] At T2, the voltage between the anode and cathode of the light-emitting element EL1 does not exceed VthEL according to equation (1). Therefore, the light-emitting element EL1 is in a non-emitting state.

[0054] [Period T3: Data write operation] The period T3 is a period during which the data signal DATA[k] is written to the pixel 20. Specifically, the potential Vn3 of the node N3 is set to the potential Vdata corresponding to the signal DATA[k]. 3 and 5, the operation of pixel 20 during this period is as follows: explain.

[0055] In the example of FIG. 3, the start of T3 is the rising edge of the signal Sa, and the end of T3 is the rising edge of the signal Sd. The period TH corresponds to one horizontal period of the corresponding row, and in the period TH, the signal S a is always at a high level. FIG. 5A shows the state of pixel 20 during period TH. In this example, before the period VH ends, the signal Sb is changed from high level to low level. After the period TH ends, the signal Sd is changed from low level to high level. As a result, at the end of the period T3 (FIG. 5B), the potential written to the node N3 Fluctuations in Vn3 (=Vdata) can be suppressed.

[0056] At T3, first, the signal Sa goes high and the signal Sd goes low. This causes transistor M1 to be conductive, transistor M4 to be non-conductive, and node The data signal DATA[k] is written to N3, and its potential Vn3 is the signal DATA[k]. The potential Vn3 of the node N3 is held by the capacitor C1. The state of transistors M3 and M5 is the same as T2, so Vn2 = V0 , Vn4=V0-Vth2. Therefore, Vgs2 (=Vn2-Vn4) is Vth2. Since it does not exceed this limit, transistor M2 remains non-conductive.

[0057] After writing the signal DATA[k] to the node N3, first, the signal Sb is set to a low level, Then, the signal Sa is set to a low level to turn on the transistor M3. 5B shows the state of pixel 20 at the end of period T3. As shown in FIG. 5B, at the end of the period T3, the transistors (M1, M2, M4, M 5) is non-conductive, transistor M3 is conductive, and node N3 is electrically floating. The timing when the signal Sa changes from high to low and the timing when the signal S The timing at which d changes from low level to high level can be made the same.

[0058] [Period T4: Light Emitting Operation] The period T4 is a light emitting period in which the light emitting element EL1 emits light at a luminance corresponding to the potential Vdata. The operation of pixel 20 during this period will be described with reference to Figures 3 and 6.

[0059] At T4, of the input signals (Sa-Sd) to the pixel 20, only the signal Sd becomes high level. Since the transistor M4 is in a conducting state, the potential Vn2 of the gate of the transistor M2 becomes V The gate-source voltage Vgs2 of the transistor M2 is The value is Vdata-(V0-Vth2). As shown in Equation (4), the drain current Id2 of the transistor M2 is independent of Vth2. As shown in the figure, β is determined by the size of the transistor M2 (channel length L, channel width W), Capacity C OX、 and the electron mobility μ. In the case of a channel type, the hole mobility is used for μ.

[0060] Id2=0.5β(Vgs-Vth2) 2 =0.5β(Vdata-V0+Vth2-Vth2) 2 =0.5β(Vdata-V0) 2 ···(3) β=μC OX (W / L) (4)

[0061] As shown in the formula (3), when the light emitting element EL1 is in a light emitting operation, Vth2 Even if the drain current Id2 flowing through transistor M2 is different, it is not affected by the This value does not depend on the threshold voltage Vth2 of the transistor M2. This shows that the light emitting element EL1 can emit light at a luminance of 1000 . This embodiment makes it possible to provide a light emitting device (display device) with excellent display quality.

[0062] In the driving method example of FIG. 3, during the period T2 in which the threshold voltage correction is being performed on the pixels 20 in the k-th row, indicates that the signal DATA[k-1] is written to the pixel 20 in the k-1th row. In this way, in the pixel 20 (pixel 10), the threshold voltage correction operation and the data writing operation Since it is possible to perform the above in different periods, the pixel 20 (pixel 10) is provided in the pixel portion, and the light emitting In this device (display device), dot sequential driving is possible. This will be explained below.

[0063] (Embodiment 2) In this embodiment, an active matrix display device is used as an example of a semiconductor device. Specifically, the structure of an active matrix display device having pixels 10 in the pixel portion will be described. Examples of the configuration and driving method will be described.

[0064] <<Example of display device configuration>> FIG. 7 is a block diagram showing an example of the configuration of the display device.

[0065] As shown in FIG. 7, the display device 50 includes a controller 51, a power management unit (PMU) 52, The device includes a power supply circuit 53, a pixel section 60, a gate driver circuit 61, a source driver circuit 62, etc. Here, the gate driver circuit 61 and the source driver circuit 62 are collectively referred to as the peripheral circuit 6 It may be called 3.

[0066] The pixel section 60 includes a plurality of pixels 65 arranged in an array, a plurality of wirings arranged in the vertical direction, and a plurality of wirings. 66, and a plurality of wirings 67 arranged in the horizontal direction. Pixels 65 in the same column are connected to wiring 66 of the same column, and pixels 65 in the same column are connected to wiring 67 of the same column.

[0067] The controller 51 controls the display device 50. The controller 51 receives a video signal, The sync signal for controlling the rewriting of the screen is input. For example, there are horizontal sync signals, vertical sync signals, and reference clock signals. generates control signals for the peripheral circuit 63 from these signals. It controls the PMU 52 based on the control signal from the controller 51 or an external device. U52 controls the power supply circuit 53.

[0068] The wiring 66 is connected to the gate driver circuit 61. The gate driver circuit 61 The control signal from the controller 51 controls the conductive state of the switch provided in the pixel section 60. The wiring 66 has a function of outputting a control signal for controlling the pixel 10 to the wiring 66. The wiring 67 is connected to the source driver circuit 62. The source driver circuit 62 receives the video signal D input from the controller 51. ATA to the wiring 67. The wiring 67 corresponds to the wiring SL of the pixel 10. It's wiring.

[0069] A more specific structure of the display device 50 will be described with reference to FIG. 8. FIG. 2 is an exploded perspective view showing a configuration example.

[0070] As shown in FIG. 8, the display device 50 is provided between an upper cover 5001 and a lower cover 5002. , FPC5003 is connected to touch panel unit 5004, FPC5005 is connected A display panel 5006, a frame 5009, a printed circuit board 5010, and a backplane 5014 are connected to the display panel 5006. The battery 5011 and the touch panel unit 5 004, etc. may not be provided. The upper cover 5001 and the lower cover 5002 , the shape and size can be adjusted to fit the size of the touch panel unit 5004 and the display panel 5006. The dimensions can be changed as appropriate.

[0071] The touch panel unit 5004 displays a resistive or capacitive touch panel. The display panel 5006 can be used by overlapping it with the opposing substrate ( It is also possible to provide the sealing substrate with a touch panel function. It is also possible to provide an optical sensor in each pixel of the panel 5006 to make it an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 5006, and a capacitance type It is also possible to use a touch panel.

[0072] The frame 5009 protects the display panel 5006 and also prevents the operation of the printed circuit board 5010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The printed circuit board 5010 may have a function as a heat sink. The power supply circuit has a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying the power may be an external commercial power source or a separately provided battery 50 The battery 5011 may be a power source of the commercial power supply. The display device 50 may include components such as a polarizing plate, a retardation plate, and a prism sheet. may be additionally provided.

[0073] <<Display panel configuration example>> Hereinafter, with reference to FIG. 9, an example of the configuration of a display panel that constitutes a display device will be described.

[0074] FIG. 9A shows a display panel having a structure in which a pixel section 60 and a peripheral circuit 63 are integrated on the same substrate. The display panel 71 has a substrate 81 and a substrate 82. The substrate 81 has a pixel portion 8A, a gate driver 60, a peripheral circuit 63, and a terminal section 85 are fabricated. The driver circuit 61 is divided into two circuits, a gate driver circuit 61L and a gate driver circuit 61R. For example, the gate driver circuit 61L is connected to the odd-numbered wiring 66, The other gate driver circuit 61R supplies signals to the wirings 66 of the even rows. are connected to supply signals to those wires 66.

[0075] The terminal section 85 has a plurality of terminals for connecting the pixel section 60 and the peripheral circuit 63 to an external circuit. The terminal portion 85 is provided with a flexible printed circuit (FPC). In this example, the FPC 86 is connected to the terminal portion 85. Devices with a structure in which the display panel is not connected are also included in the display panel.

[0076] The substrate 81 and the substrate 82 are opposed to each other with a gap (cell gap) maintained by the sealing member 83. 9A, the sealing member 83 is placed so as to overlap the peripheral circuit 63. By providing this, the display panel 71 can have a narrow frame.

[0077] A part of the peripheral circuit 63 is incorporated into an IC chip, and the IC chip is mounted on a substrate 81 or F It is also possible to mount it on a PC86. An example of a display panel with such a configuration is shown in FIG. Shown in 9D.

[0078] As shown in FIG. 9B, the display panel 72 includes a source driver circuit 62. An IC chip 91 is mounted on the substrate 81 .

[0079] 9C and 9D show a circuit diagram of a source driver circuit 62 assembled on an IC chip 92. A part of the circuit 95 is mounted on the substrate together with the pixel section 60 and the gate drivers (61L, 61R). 81 shows an integrated display panel. In the display panel 73 of FIG. 9C, the IC chip 92 is The chip is mounted on the substrate 81 by the OG (Chip on Glass) method. In the display panel 74, the IC chip is mounted on the FPC using the COF (Chip on Film) method. The mounting method of the IC chip 91 and the IC chip 92 is not particularly limited. Also, instead of TCP, an IC chip is incorporated into the SOF (System on Film). The SOF may be attached to the substrate 81 by embedding the SOF therein.

[0080] The display panel 71 (FIG. 9A) has circuits (60, 61L, 61R, 62) formed on a substrate 81. This reduces the number of external components such as IC chips, resulting in cost reduction. Due to limitations on the performance of semiconductor elements that can be fabricated on the substrate 81, There are cases where it is not possible to fabricate all of the peripheral circuits 63 together with the pixel section 60. In this case, As with panels 72 to 74, some of the peripheral circuits 63 are incorporated into an IC chip. This IC chip is connected to the peripheral circuit 63 and / or the pixel section 60 on the substrate 81. In order to do this, it is necessary to provide terminals on the substrate 81. The number of terminals on the substrate 81 is greater than that on the panel 71. The increase in the number of terminals is a problem in the display device. This hinders the edge processing and increases manufacturing costs due to the process of connecting the terminals to the FPC.

[0081] Therefore, an example of the configuration of a display panel that can reduce the number of terminals will be described below. .

[0082] <<Display panel configuration example 1>> FIG. 10 shows an example of the configuration of a display panel. Specifically, FIG. 10 shows the elements that make up the display panel. 1 is a diagram illustrating an example of the configuration of a sub-substrate. On the top, there are a pixel unit 121, a gate driver circuit GDL, a gate driver circuit GDR, and a circuit SS. The circuit includes a DC1_E, a circuit SSDC1_O, a terminal portion 112E, and a terminal portion 112O. In the element substrate 101, circuits other than the pixel section 121 may be collectively called peripheral circuits. do.

[0083] The pixel section 121 has a plurality of pixels 21 arranged in an array. The terminal section 112O has a plurality of terminals 111 connected to the circuit SSDC1_E. The terminal section 112E has a plurality of terminals 111 connected to the source terminal SDC1_0. One or more IC chips that configure the driver circuit are connected to the terminal section 112O. is.

[0084] <<Pixel section, pixel>> An example of the configuration of the pixel section 121 and the pixel 21 will be described with reference to FIGS. 11 is a circuit diagram showing an example of the configuration of the pixel 21. As shown in FIG. , pixel 20 (FIG. 2) has the same circuit configuration, and transistors (M1-M3, M5) The pixel 20 differs from the pixel 10 in that it has a back gate connected to the gate. The pixel 21 can be driven in accordance with the timing chart of FIG. 3, similarly to the pixel 20. do.

[0085] By providing a back gate connected to the gate of the transistor, the on-state voltage of the transistor can be increased. It is possible to increase the current and improve the field effect mobility of the transistor. In addition, fluctuations in electrical characteristics such as the threshold voltage of the transistor can be suppressed. Furthermore, by providing a back gate, the strength of the transistor can be improved. In other words, the back gate acts as a reinforcing member against deformation such as bending of the transistor support substrate. This makes the transistor less likely to break.

[0086] The pixel section 121 has a plurality of wirings (GLa, GLb, GL c, GLd) and multiple wirings (PLa, PLb, PLc). For clarity, in Fig. 10, the wiring (GLa, GLb, GLc, GLd) is grouped into a wiring group GLS. The wiring (PLa, PLb, PLc) is omitted.

[0087] In the example of FIG. 10, pixel 21 is a sub-pixel that emits red (R), green (G), and blue (B) light. The three pixels 21 form a unit pixel 31 (hereinafter, sometimes referred to as a pixel 31). The pixel section 121 is provided with pixels 21 arranged in n rows and 2m columns. (n and m are integers of 1 or more). In the same column of the pixel section 121, pixels 21 of the same luminescent color are arranged. are arranged in a vertical (column) RGB stripe arrangement.

[0088] In this specification, when components are distinguished by the color displayed by a pixel, _R, [R], R For example, pixel 21_R represents the red pixel 21. The wiring SL_G[2] is the wiring SL_G[3] in the second column to which the green data signal DATA_G is input. In addition, when the luminous colors are not distinguished among the 3n wirings SL, the wirings SL_ R[k] (k is an integer equal to or greater than 1) is the wiring SL[3k-2] in the 3k-2 column, and the wiring S L_G[k] is the wiring SL of the (3k-1)th column, and wiring SL_B[k] is the wiring of the (3k)th column. In addition, three wirings with a common column number (SL_R[k], SL_G[k], S L_B[k]) may be collectively referred to as the wiring group SLS[k].

[0089] In the example of FIG. 10, the wiring group GLS[k] (k is an integer satisfying 1≦k≦n) is Other configuration examples include a GDL and a GDR. For example, the odd-numbered line group GLS can be connected to the GDL, The wiring group GLS of the even rows can also be connected to GDR. It is connected to the line group SLS[2h-1] (h is an integer satisfying 1≦h≦m), and SSDC1_E are connected to the wiring group SLS[2h] of the even-numbered columns.

[0090] <<Peripheral circuits>> Next, an example of the configuration of the peripheral circuit of the element substrate 101 and an example of a driving method will be described.

[0091] <<Gate driver circuits GDL, GDR>> 11 to 17, examples of the configuration and driving method of the GDL and GDR will be described. 2 is a circuit diagram showing an example of the configuration of the GDL and GDR. The following describes the GDL, but the GDR has the same circuit configuration. be.

[0092] GDL consists of an n-stage basic circuit (GSR) 131 and a two-stage dummy basic circuit (dumGSR) 1 32, and n+2 basic circuits (GdINV) 131. In this case, the GSR 131 in the hth stage may be written as GSR[h]. The same is true for .

[0093] The shift register 130 includes an n-stage GSR 131 and a two-stage dumGSR 132. The GDL has the following control signals: signal GSP, signal INIRES, signal (GPWC1A, GPWC1B, GPWC1C, GPWC1D), signal (GPWC3A, GPWC3B, G PWC3C, GPWC3D), signal (GPWC4A, GPWC4B, GPWC4C, GP WC4D), and signals (GCLK1, GCLK2, GCLK3, GCLK4) are input. The GDL generates multiple pulse signals according to these signals and sends them to the wiring group GLS [1]-GLS[n] has the function to output.

[0094] GSR[1] contains dummy wiring (GLa[dum1], GLd[dum1]) and wiring The lines (GLb[1], GLc[1]) are electrically connected. GSR[k] (k is 2 or more) The upper integer (n or less) has wiring (GLa[k-1], GLd[k-1], GLb[k], G Lc[k]) is electrically connected. The first stage dummy circuit (dumGSR[1]) has , wiring (GLa[n], GLd[n]), and dummy wiring (GLb[dum1], GL c[dum1]) is electrically connected to dumGSR[2]. La[dum2], GLd[dum2], GLb[dum2], GLc[dum2]) is connected.

[0095] GSR131 and dumGSR132 are connected to the wiring GLd via GdINV133. GdINV133 is electrically connected to GSR131 or dumGSR132. It has the function of generating an inverted signal of the signal input from the

[0096] <Basic circuit GSR, dummy basic circuit dumGSR> FIG. 13A is a block diagram showing an example of the configuration of the GSR 131, and FIG. 13B is a block diagram showing an example of the configuration of the dumGSR 131. FIG. 14 is a circuit diagram showing an example of the configuration of GSR131. FIG. 15 is a circuit diagram showing an example of the configuration of the dumGSR 132.

[0097] The GSR131 receives GVDD as the high power supply potential and GVSS and GSR131 is connected to the input nodes (LIN, RES, RI N, CK1, CK2, CK3, PWC1, PWC3, PWC4), output node (SROU T, GOUT2, GOUT3, GOUT4), transistors (Mg1-Mg23) and The transistors (Mg1-Mg23) are n-channel These transistors (Mg 1-Mg23) one or more transistors do not have a back gate A transistor may also be applied.

[0098] As shown in Figure 12, the input node RIN of the GSR131 is connected to the output node RIN of the GSR131 two stages later. The two dumbGSR132s are connected to the output node SGOUT. [n-1], and GSR[n] are provided to output signals to the input nodes RIN. Therefore, the input node RIN is not required for the dumGSR132 itself, and the dumGSR1 32 corresponds to the circuit of GSR131 excluding the input terminal RIN and transistor Mg7. do.

[0099] The signal INIRES is input to the RES terminal of GSR131 and dumGSR132. The signal INIRES is output from the output nodes (SROUT, GOUT2, GOUT3, GOUT 4) can function as a reset signal to reset the potential level of The signal GSP is input to the input node LIN of the first stage GSR131. can function as a start pulse signal. The node LIN is connected to the output node SGOUT of the preceding GSR.

[0100] <Basic circuit GdINV> FIG. 16A is a block diagram showing an example of the configuration of GdINV 133, and FIG. 16B is a circuit diagram of the same. be.

[0101] GdINV133 receives GVDD as the high power supply potential and GVE as the low power supply potential. E2 is input. GdINV133 has input nodes (IN, RIN4), output node O UT, transistors (Mg31 - Mg35) and capacitor Cg31. Here the transistors (Mg31 - Mg35) are n-channel transistors. Also back gates are provided for these. One or a plurality of these transistors can be transistors without back gates as well.

[0102] <<Example of Driving Method for GDL and GDR>> FIG. 17 is a timing chart showing an example of the driving method for GDL and GDR. In FIG. 17 the waveforms of various signals input to GDL and GDR are shown. Further, the waveforms of the output signals to the wirings electrically connected to GSR[1] - GSR[4] are shown. Specifically, the signals (Sa[dum1], Sd[dum1]) output to the dummy wirings (GLa[dum1], GLd[dum1]), and the signals output to the wiring group GLS[1] - [4] (Sa[1] - Sa[3], Sb[1] - Sb[4], Sc[1] - Sc[4 ) are shown.

[0103] In the example of the driving method in FIG. 17, the signals (GPWC4A, GPWC4B, GPWC4C, GPWC 4D) respectively use signals with the same waveforms as the signals (GPWC1A, GPWC1B, GPWC1C, GPWC1D ). Also, in FIG. 17, GdINV133 generates the inverted signal of the signal Sa[h] input to the wiring G La[h] and outputs it as the signal Sd[h] to the wiring GLd[h].

[0104] <<Circuit SSDC1_E, circuit SSDC1_O>> The configuration of SSDC1_E and SSDC1_O will be explained below with reference to Figures 10, 18 to 22. Examples of the driving method and the like will be described.

[0105] As shown in FIG. 10, the SSDC1_E and SSDC1_O circuits each have m basic circuits. The SSD 141 is a circuit that has the function of a demultiplexer. In the example of FIG. 10, the SSD 141 has one input node and three output nodes. The signal input to the input node can be output to one of the three output nodes. The SSD 141 is provided in accordance with the arrangement of the pixels 21. Since one SSD141 is provided for each of the three rows (RGB), SSDC1_E and S Each of the SDC1_0 has m stages of SSDs 141. In the example of FIG. 01 has 2m SSD141s in two circuits (SSDC1_E, SSDC1_O). Although it is provided separately, it may be provided as one circuit or may be provided as two or more separate circuits. It can also be done as follows.

[0106] The input node of SSD141 is connected to the wiring DTL, and the wiring DTL is connected to the terminal 111. The terminal 111 is connected to a source driver circuit built into the IC chip. The three output nodes of SSD141 are connected to the wiring (SL_R, SL_G, SL With this connection structure, the data signal DATA is transmitted to the terminal 11 1 and the wiring DTL, and is input to the SSD 141. The SSD 141 is connected to the wiring (SL_ The data signal DATA can be output to one of the wirings (SL_R, SL_G, SL_B). It is possible.

[0107] Although only the terminal 111 connected to the wiring DTL is shown in FIG. 10, In addition to the terminals 111, the element substrate 101 may also include GDL, GDR, , supplying signals or potentials to the pixel unit 121, SDDC1_E, and SSDC1_O. A plurality of terminals are provided for this purpose.

[0108] FIG. 18 shows an example of the configuration of SSDC1_E, and FIG. 19 shows an example of the configuration of SSDC1_O. As shown in Figures 18 and 19, SSDC1_E and SSDC1_O are controlled by The difference is whether the line group SLS is an odd-numbered row or an even-numbered row, but they have the same circuit configuration. Therefore, common components (such as signals and wiring) between SSDC1_O and SSDC1_E are ) etc., the identification symbol "_E" or "_O" should be added.

[0109] As shown in Figure 18, SSDC1_O is connected to the wiring (SML_R_O, SML_G_O, SM L_B_O), wiring (PRL_R_O, PRL_G_O, PRL_B_O) and m-stage As shown in FIG. 19, SSDC1_E includes a wiring (SML_R_E , SML_G_E, SML_B_E), wiring (PRL_R_E, PRL_G_E, PRL _B_E) and m stages of SSD 141.

[0110] In SSDC1_O, the wiring (SML_R_O, SML_G_O, SML_B_O) are input signals (SMP_R_O, SMP_G_O, SMP_B_O), respectively. The signals (SMP_R_O, SMP_G_O, SMP_B_O) are connected to the wiring (SL_R, SL SL_G, SL_B) to be connected to the wiring DTL. It can also be used as wiring (PRL_R_O, PRL_G_O, PRL _B_O) respectively have signals (PRE_R_O, PRE_G_O, PRE_B_O) The signals (PRE_R_O, PRE_G_O, PRE_B_O) are input via the wiring (S It can be used as a control signal to precharge the As shown in Figure 19, the wiring and signals for SSDC1_E are Since this is similar, the explanation of FIG. 18 is also applicable.

[0111] <Basic circuit SSD> FIG. 20A is a block diagram showing an example of the configuration of the SSD 141, and FIG. 20B is a block diagram showing an example of the configuration of the SSD 141. 1 shows a circuit diagram illustrating an example of the configuration of the device shown in FIG.

[0112] The SSD141 has one input node DIN to which a data signal DATA is input, Three output nodes (DOUT1, DOUT2, DOUT3) where DATA is output, signal (SMP_R, SMP_G, SMP_B, PRE_R, PRE_G, PRE_B) are input The six input nodes, wires (SML_R, SML_G, SML_B), and wires ( PRL_R, PRL_G, PRL_B) and wiring (SML_R, SML_G, SM Signals (SMP_R, SMP_G, SMP_B) are input to the wiring (PRL _R, PRL_G, PRL_B) have signals (PRE_R, PRE_G, PRE_B) The node DIN is connected to a wiring DTL, and the data signal DATA is input. The output nodes (DOUT1, DOUT2, DOUT3) are connected to the wiring (SL_ The SSD 141 is connected to the signals (SMP_R, SMP_ A circuit (SMPC) 41 controlled by signals (PRE_R, P The circuit (PREC) 42 is controlled by the PRE_G and PRE_B.

[0113] The SMPC 41 can function as a demultiplexer. The input signal (DATA) is output from three nodes (DOUT1, DOUT2, DOUT3). The SMPC41 is a circuit that can select the node to which the signal is input. 1, Ms2, Ms3), and the transistors (Ms1, Ms2, Ms3) are , respectively, the conduction between the nodes (DOUT1, DOUT2, DOUT3) and the node DIN The transistors (Ms1, Ms2, Ms3, Ms4, Ms5, Ms6, Ms7, Ms8, Ms9, Ms10, Ms11, Ms12, Ms13, Ms14, Ms15, Ms16, Ms17, Ms18, Ms19, Ms20, Ms21, Ms22, Ms23, Ms24, Ms25, Ms26, Ms The gates of Ms2 and Ms3 are electrically connected to the wiring (SML_R, SML_G, SML_B). The conduction state of the transistors (Ms1, Ms2, Ms3) is determined by the signal (SMP_R , SMP_G, SMP_B).

[0114] PREC42 controls the potential of the nodes (DOUT1, DOUT2, DOUT3). For example, it can function as a precharge circuit. REC42 has transistors (Mr1, Mr2, Mr3). The gates of the PRLs (Mr1, Mr2, Mr3) are electrically connected to the wiring (PRL_R, PRL_G, PRL_B). The conduction state of the transistors (Mr1, Mr2, Mr3) is determined by the signal (PR Transistor Mr1 is controlled by node D It is used as a switch to control the conduction state between OUT1 and the wiring to which the potential VPR_R is applied. The transistor Mr2 can function as a voltage source between the node DOUT2 and the potential VPR_G It can function as a switch that controls the conduction state between the wiring to which the voltage is applied. The transistor Mr3 is a conductor between the node DOUT3 and the wiring to which the potential VPR_B is applied. It can function as a switch that controls the on / off state.

[0115] In the example of FIG. 20B, transistors (Ms1, Ms2, Ms3) and transistor (Mr Mr1, Mr2, Mr3) are n-channel transistors, but p-channel transistors These transistors can also be connected to the gates of the buffers. These transistors (Ms1, Ms2, Ms3, Mr1) , Mr2, Mr3) is provided with a back gate. It is also possible to use a smaller transistor.

[0116] <<Display panel driving method example 1>> 21 and 22, examples of a method for driving the SSD 141 and a table An example of a method for driving the display panel 100 will be described. A, SMP_R, SMP_G, SMP_B, PRE_R, PRE_G, PRE_B), and the wiring in rows h-1, h, and h+1 (GLa, GLb, GLc, GLd) The waveform of the input signal to is shown in the period TH[h-1], TH[h], TH[h+1]. are one horizontal period of the (h-1)th row, the hth row, and the (h+1)th row of the pixel section 121, respectively. 22 corresponds to a timing chart that is a partial enlargement of FIG. 21. FIG. 21 further includes , the waveforms of the signals (GCLK1, GCLK2, GCLK3, GCLK4) input to the gate driver circuit (GDL, GDR) are also shown.

[0117] <Example of driving method of SSD141> During one horizontal period TH, any one of the signals SMP_R, SMP_G, and SMP_B becomes high level. Here, SMPC41 is controlled so that a plurality of transistors (Ms1, Ms2, Ms3) do not become conductive simultaneously due to the signals (SMP_R, SMP_G, SMP_B). is controlled.

[0118] To the wirings (SL_R, SL_G, SL_B), the signal DATA input to the wiring DTL is input during the period when the signals (SMP_R, SMP_G , SMP_B) are at high level, respectively. Therefore, the format of the data signal DATA is a dot sequential format divided (RGB divided) for each display color. Specifically, the data signal DATA is divided into DATA_R, DATA_G, and DATA_B in this order so that the signals (DATA_R, DATA_G, DATA_B) corresponding to the display colors are written to the pixels (21_R, 21_G, 21_B), respectively, and input to the wiring DTL. <In the circuit configuration of pixel 21, the threshold voltage correction operation and the data writing operation can be performed in different periods. That is, with the combination of SSD141 (SSDC1_E and SSDC1_O) and

[0119] the pixel 21, dot sequential driving is possible, and a display panel 100 with excellent display quality can be provided.

[0120] As shown in FIG. 10, in the display panel 100, the wirings (SL_R, SL_G, SL_B The number of SSDC1_O and SSDC1_E is 2m each. During the period VH, as the wiring to write the signal DATA, first, 2m SL_R are simultaneously Then, 2m lines of SL_G are simultaneously selected and the signal DATA_R is written. , signal DATA_G is written, and finally, 2m SL_B are selected simultaneously, and signal D ATA_B is written. In other words, in the display panel 100, SSDC1_O and SS DC1_E makes it possible to simultaneously sample 2m SLs.

[0121] As shown in FIG. 10, the display panel 100 has 2m×3 (RGB) lines SL. The number of terminals 111 for inputting data signals DATA to these wirings SL is one third of that. In other words, by providing the SSD 141, the number of terminals 111 is increased by 2m times the number of wirings SL. Therefore, the number of samples that can be sampled with SSD141 can be reduced to one third. If the number of lines SL is N (N is an integer of 2 or more), the number of terminals 111 is 1 / 2 the total number of lines SL. It can be set to 1 / N.

[0122] In addition, in PREC42 of SSD141, the signal wiring (SL_R, SL_G, SL_B) Before data is written, the potential of the lines (SL_R, SL_G, SL_B) is set to a predetermined voltage. Precharge is performed to boost the voltage to the VPR_R, VPR_G, and VPR_B levels.

[0123] In PREC42, the trigger is triggered by signals (PRE_R_E, PRE_G_E, PRE_B_E). When the transistors (Mr1, Mr2, Mr3) are in a conductive state, the wiring (SL_R, SL_G , SL_B) are applied with potentials (VPR_R, VPR_G, VPR_B), respectively. By performing such a precharge operation, the signals (SMP_R, SMP_G, SMP _B) is high level (SSD141 selects wiring (SL_R, SL_G, SL_B) During the period when the line is selected, the potential of the wiring (SL_R, SL_G, SL_B) is measured as data. The potentials corresponding to the data signals (DATA_R, DATA_G, DATA_B) ensure It is possible.

[0124] The potential of the wiring (SL_R, SL_G, SL_B) is set to a potential corresponding to the data signal DATA. The routing (SL_R, SL_G, SL_B) is selected for the time required to If the period is long enough, the SSD 141 does not need to be provided with the PREC 42. (SL_R, SL_G, SL_B) For example, the signal PRE_R may be used to operate the display panel 100. In this case, the transistor Mr1 (see FIG. 19) can be kept at a low level even during the period when the ) is in a non-conductive state, and precharging of the wiring SL_R is not performed.

[0125] <<Display panel configuration example 2>> In FIG. 10, one unit pixel 31 is composed of three (RGB) pixels 21 (sub-pixels). However, the unit pixel is not limited to this. The number of sub-pixels and the number of sub-pixels may be changed. The emission color and the arrangement of sub-pixels within a unit pixel can be set as appropriate. For example, four sub-pixels that emit red (R), green (G), blue (B), and yellow (Y) light are used. A display having such a unit pixel can be constructed as shown in FIG. 1 shows an example of the configuration of the panel 102. Of course, the display colors of the sub-pixels that make up the unit pixel are Not limited to this, for example, red (R), green (G), blue (B), and white (W) It is also possible.

[0126] FIG. 23 is a block diagram showing an example of the configuration of the element substrate 103 that constitutes the display panel 102. The element substrate 103 has the same structure as the element substrate 101. It can be driven in the same way as panel 100. The differences are as follows.

[0127] The pixel section 122 of the element substrate 103 has a unit pixel 32 that is composed of four pixels 21 of RGBY. The element substrate 103 is provided with SSD2_E and SSD2_O. D2_E and SSD2_O each have m basic circuits SSD142.

[0128] <Basic circuit SSD> FIG. 24A is a block diagram showing an example of the configuration of the SSD 142, and FIG. 24B is a circuit diagram of the same. As shown in FIG. 24B, the SSD 142 includes a circuit (SMPC) 43 and a circuit (PR SMPC44 has the same function as SMPC41, and This corresponds to a circuit in which a wiring SML_Y and a transistor Ms4 are added to C41. Circuit P REC44 has the same function as the circuit PREC42, and PREC42 is connected to the wiring PR This corresponds to a circuit with L_Y and transistor Mr4 added.

[0129] As shown in FIG. 23, the display panel 102 has two more wirings SL than the display panel 100. Although the number of terminals 111 has increased by 2m, by providing 2m SSDs 142, the number of terminals 111 is It is possible to make it 2m in length, the same as module 100.

[0130] As described above, by applying this embodiment, a threshold voltage correction function for a pixel transistor can be realized. It is possible to provide a display device that has the above-mentioned functions and is capable of point sequential driving. By applying this embodiment, it is possible to provide a display device with a reduced number of terminals.

[0131] As described above, in the display panel according to the present embodiment, the pixel section and other peripheral circuits are Therefore, it is possible to configure the element substrate with transistors of the same conductivity type (unipolarity). Since the number of manufacturing steps can be reduced, the manufacturing cost of the display panel can be reduced.

[0132] (Embodiment 3) In this embodiment, an active matrix display device is used as an example of a semiconductor device. As an example, the device structure of a display panel according to the second embodiment and its manufacturing method will be described. More specifically, the display panel 10 to which the element substrate 101 is applied will be described. 10 (FIG. 10) and its manufacturing method will be described.

[0133] (Regarding the device structure of semiconductor elements) Regarding the device structure of the semiconductor elements such as transistors that constitute the element substrate 101, There are no restrictions. As long as a transistor suitable for the characteristics of the circuit formed on the element substrate 101 is selected, The device structure of the transistor can be, for example, a top gate type or a bottom gate type. , and dual gate type with both gate (front gate) and bottom gate, one A multi-gate type having multiple gate electrodes for the same semiconductor layer is also available. There are no particular restrictions on the semiconductor layer in which the transistor channel is formed. Semiconductor films are roughly classified into single crystal semiconductor films and non-single crystal semiconductor films. Examples of the semiconductor layer include a polycrystalline semiconductor film, a microcrystalline semiconductor film, and an amorphous semiconductor film. Semiconductor materials include Group 4 semiconductors containing one or more Group 4 elements such as Si, Ge, and C. (e.g., silicon, silicon carbide, etc.), oxide semiconductor film (e.g., In-Ga-Zn oxides, compound semiconductor films, etc.

[0134] <<Display panel configuration example>> 25 is a cross-sectional view showing an example of the configuration of a display panel. 25 is a layout diagram showing an example of the configuration of the display panel 100. As shown in FIG. It has an element substrate 101 and an opposing substrate 171. In this specification, The substrate facing the element substrate is called the opposing substrate. It is also called a filter substrate or a sealing substrate.

[0135] Here, as an example of the display panel 100, transistors of the same conductivity type (single polarity) are used as elements. An example of the structure of the sub-substrate 101 will be described. In addition, the transistors of the element substrate 101 are as follows: A transistor including an oxide semiconductor layer including a channel (hereinafter referred to as an OS transistor) ) will be explained as an example.

[0136] In the example of FIG. 25, the display panel 100 reflects the light 180 emitted from the light emitting element EL1 onto the counter substrate. The pixel section 121 has a top emission structure where light is extracted from the plate 171 side. The optical elements EL1 are provided with a common EL layer that emits white light, and the opposing substrate 1 71 is provided with an RGB color filter, so that color display can be performed on the display panel 100. The device structure of the display panel capable of color display is shown in Figure 25. For example, a color filter may be provided on the element substrate. In addition, the pixel 21_R, the pixel 21_G, and the pixel 21_B are provided with EL layers that emit light of different colors. In this case, a color display is possible by forming a color film on the element substrate or the opposing substrate. A filter may or may not be provided.

[0137] <Configuration example of element substrate> (Pixel layout example) An example of the configuration of the pixel 21 will be described with reference to Fig. 25 and Fig. 26. Fig. 26A shows the configuration of the pixel 21. An example layout of transistors M1-M5 and capacitor C1 is shown in FIG. 26B. 10 shows an example of the layout of the pixel electrode (conductive layer 251) of the light-emitting element EL1 stacked on the element from the above. Figure 25 corresponds to a cross-sectional view taken along the cutting line a1-a2 in Figure 26A, and is shown in the figure for clarity. 26A and 26B, some of the openings are marked with symbols for clarity. Therefore, the description of some layers and the symbols of the openings are omitted, and some layers are given hatching patterns. is doing.

[0138] In the layout example in Figure 26, the diagonal size of the display area is 13.3 inches and the resolution is It is possible to provide a display panel 100 with a resolution of 8k4k (7,680 x RGB x 4,320) In this specification, the size of the pixel 21 is 12.75 μm (H 21 )×8.25μm( V 21 )

[0139] The element substrate 101 includes a substrate 110 having an oxide semiconductor (OS) layer, a plurality of insulating layers, a plurality of conductive layers, and a plurality of insulating layers. The pixel 21 is configured by laminating an organic layer, an oxide semiconductor (OS) layer, etc. 201-205, first conductive layers 211-216, second conductive layers 221-227, The third layer includes conductive layers 231-235 and insulating layers 271-273. The transistors M1-M5 and the capacitor C1 are configured as a result. The fourth layer includes conductive layers 241-243, conductive layers 251-253, an EL layer 260, and an insulating layer 274-277. Conductor layers 251-253 and an EL layer 260 are stacked. The portion functions as the light-emitting element EL1.

[0140] (peripheral circuits) The element substrate 101 also includes peripheral circuits such as gate driver circuits (GDL, GDR) and These circuits include the pixel 21 and the circuit (SSDO1, SSDE1). Transistors and capacitors having similar device structures are formed.

[0141] The conductive layers (211-216, 221-227, 231-235) constituting the element substrate 101 , 241-243, 251-253, etc.) are single-layer conductive films or two or more layers of conductive films. Such a conductive film can be formed using aluminum, chromium, copper, silver, gold, or the like. , platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Uses metal films such as niobium, manganese, magnesium, zirconium, and beryllium In addition, alloy films and compound films containing these metals, and films containing impurities such as phosphorus, can be formed. A polycrystalline silicon film containing silicon, a silicide film, or the like can be used. A light-transmitting conductive film can be used as the conductive film that constitutes the plate 101. Examples of suitable indium oxides include tungsten oxide-containing indium oxides and tungsten oxide-containing indium oxides. Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium tin oxide (called ITO), indium zinc oxide, silicon oxide Examples of the film include a film containing a metal oxide such as indium tin oxide doped with .

[0142] The insulating layer (271-278) can be formed of a single insulating layer or two or more insulating layers. Inorganic insulating films include aluminum oxide, magnesium oxide, silicon oxide, Silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide Examples of resin films include films made of acrylic resin, polycarbonate, and the like. Polyimide resin, benzocyclobutene resin, siloxane resin, polyamide resin, epoxy In this specification, the term "oxynitride" refers to a film containing an oxide rather than nitrogen. Nitrogen oxides are compounds that contain more nitrogen than oxygen. This refers to

[0143] The insulating film, conductive film, semiconductor film, etc. that constitute the display panel 100 can be formed by a sputtering method. Typical methods are the CVD method and the plasma CVD method. Other methods, such as the coating method and nanoimprint method, Examples include linting, evaporation, thermal CVD, and molecular beam epitaxy (MBE). As a thermal CVD method, for example, MOCVD (Metal Organic Chemical Vapor Deposition) Chemical Vapor Deposition (ALD) and Atomic Lay The er Deposition method can be used.

[0144] <Configuration example of opposing substrate> As shown in FIGS. 25 and 28, the counter substrate 171 includes a substrate 170, a light-shielding layer 280, a color filter, and a color filter. Each color filter layer (281 _R, 281_B, 281G) convert the light (white light) 180 emitted from the EL layer 260 into different The light-shielding layer 280 is an optical filter layer for converting light of different colors. The light-shielding layer 280 has a single-layer structure and functions to block light from entering the display panel 100. The light-shielding layer 280 may have a structure of two or more layers or a laminated structure of two or more layers. For example, a film made of a polymer in which chromium, titanium, nickel, or carbon black is dispersed is used. The overcoat layer 282 serves to flatten the surface of the opposing substrate 171 and remove impurities (typically The overcoat layer 282 has a function of preventing the diffusion of oxygen and / or water. For example, it can be made of polyimide resin, epoxy resin, acrylic resin, or the like.

[0145] Similar to the display panels 71-74 (FIG. 9), the display panel 100 also has an element substrate 101 and an opposing substrate. The plate 171 is fixed by a sealing member. By providing an optical film or the like on 171, the extraction efficiency of light 180 can be improved. In addition, a desiccant may be attached to the counter substrate 171 to prevent deterioration of the light-emitting element EL1. For the same reason, nitrogen gas or argon is not used in the space 181 between the substrate 110 and the substrate 170. It is preferable to fill the cavity with an inert gas such as gon gas, or a solid substance such as a resin material. In addition, by filling the space 181 with a substance with a high refractive index (such as resin), it is possible to extract the light 180. Efficiency can be improved.

[0146] <Example of element substrate manufacturing method> An example of a method for manufacturing the element substrate 101 will be described below with reference to FIGS. 28 is a plan view for explaining an example of a method for manufacturing the pixels (21_R, 21_G, 21_B). In addition, the element substrate 101 is provided with a peripheral circuit section (G DL, GDR, SSDO1, SSDE1) and terminal parts (112O, 112E) is formed.

[0147] (First conductive layer) A single-layer or multi-layer conductive film is formed on the substrate 110. Here, the conductive film is a thin film having a thickness of 1000 .mu.m or less. A copper film of 170 nm to 230 nm and a nitrogen film of 5 nm to 15 nm thick as an underlayer for the copper film. A tantalum chloride film is formed. A resist mask RM1 (not shown) is formed on the copper film. Using resist mask RM1, the laminated film of tantalum nitride film and copper film is etched to form the first layer. The conductive layers 211-216 are formed (FIG. 27A). The conductive layer 211 constitutes the wiring GLa. The conductive layer 212 has a region that functions as the gate electrode of the transistor M1. The wiring GLb has a region that functions as the gate electrode of the transistor M3. The layer 213 forms the wiring GLc and is a region that functions as the gate electrode of the transistor M5. The conductive layer 214 forms the wiring GLd and serves as the gate electrode of the transistor M4. The conductive layer 215 functions as the gate electrode of the transistor M2. The conductive layer 216 has a region that functions as a terminal (electrode) of the capacitor C1. It has a region.

[0148] An insulating layer 271 is formed over the conductive layers 211-216. The area that functions as the gate insulating layer for the transistors M1-M5 and the dielectric layer for the capacitor C1. Here, an insulating film having a two-layer structure is formed as the insulating layer 271. For example, the first layer is a silicon nitride film having a thickness of 300 nm to 500 nm, and the second layer is a silicon nitride film having a thickness of 300 nm to 500 nm. Silicon oxynitride films are formed to a thickness of 20 nm to 100 nm. These films are PE(p It can be formed by the laser-enhanced CVD method.

[0149] (OS layer) An oxide semiconductor film is formed over the insulating layer 271. The oxide semiconductor film is an In—Ga oxide film. In-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, L It is possible to form a semiconductor film made of a metal oxide such as Ce, Nd, or Hf. Here, an In-Ga-Zn oxide film with a thickness of 30 nm to 50 nm is formed by sputtering. The In-Ga-Zn oxide film is etched using a resist mask RM2 (not shown). The OS layers 201-205 are then formed (FIG. 27B). Each of these constitutes a semiconductor layer having a channel forming region for the transistors M1 to M5.

[0150] (Second conductive layer) In order to form openings 301 and 302 in the insulating layer 271, a resist mask RM3 ( 2. Using a etch mask (not shown), the insulating layer 271 is etched to form an opening 30 reaching the conductive layer 215. 1, and an opening 302 reaching the conductive layer 216 is formed (FIG. 27C).

[0151] A conductive film is formed over insulating layer 271 and OS layers 201-205. A conductive film is formed. A tungsten film having a thickness of 30 nm to 80 nm is formed as a first layer, and a second layer is formed as a second layer. An aluminum film having a thickness of 200 nm to 500 nm is formed on the first layer, and a thickness of 70 nm or less is formed on the third layer. A titanium film of up to 150 nm is formed. These films can be formed by sputtering. The three-layer conductive film is etched using a resist mask RM4 (not shown). Conductive layers 221-226 are formed (FIG. 27C).

[0152] The conductive layer 221 forms the wiring PLb and is connected to the source electrode or the drain electrode of the transistor M3. The conductive layer 222 has a region that functions as a source electrode or a gate electrode of the transistor M1. The conductive layer 223 has a region that functions as a drain electrode. 4, which has an area that functions as a source electrode or a drain electrode, and The conductive layer 224 is in contact with the source electrodes of the transistors M4 and M5. has a region that functions as a drain electrode, and is in contact with the conductive layer 215 at the opening 301. The conductive layer 225 serves as the source electrode or drain electrode of the transistors M2 and M5. The conductive layer 2 has a region that functions as a capacitor C1 and a region that functions as an electrode of the capacitor C1. 26 constitutes the wiring PLc, which functions as the source electrode or drain electrode of the transistor M5. The conductive layer 227 has a region that functions as a source electrode or a drain electrode of the transistor M2. It has a region that functions as an electrode.

[0153] (Third conductive layer) An insulating layer 272 is formed covering the OS layers 201-205 and the conductive layers 221-227. The insulating layer 272 is formed by, for example, a 300 nm to 500 nm thick nitride film by the PECVD method. A resist mask RM5 (not shown) is used to form an insulating layer 272. Etching is performed to form openings 305 that reach the conductive layer 225 (FIG. 27D). This etching step removes the insulating layer 272 (oxynitride) in the areas where the openings 311-313 will be formed. The second layer (silicon film) of the insulating layer 271 and the second layer (silicon oxynitride film) of the insulating layer 271 are removed.

[0154] An insulating layer 273 is formed to cover the insulating layer 272. The insulating layer 273 may be, for example, a 7 mm thick film. A silicon nitride film is formed to a thickness of 5 nm to 125 nm. A resist mask RM6 (not shown) is formed. etch the insulating layers 271-273 to form openings 311-313, opening 321, and forming opening 322 (FIG. 27D). Openings 311-313 are formed in conductive layers 211-21. The opening 321 reaches the conductive layer 223, and the opening 322 is an opening that reaches the conductive layer 224.

[0155] A conductive film is formed over the insulating layer 273. Here, a single-layer light-transmitting conductive film is formed. The silicon oxide (SiOx) layer is deposited by sputtering to a thickness of 75 nm to 125 nm. Then, an indium tin oxide (ITO) film is formed. A resist mask RM is formed on the transparent conductive film. 7 (not shown), and the transparent conductive film is etched to form conductive layers 231-235. (Figure 27D).

[0156] The conductive layer 231 has a region that functions as a back gate electrode of the transistor M1. The conductive layer 232 is in contact with the conductive layer 211 at the gate 311. It has a region that functions as a back gate electrode and is in contact with the conductive layer 212 at the opening 312. The conductive layer 233 has a region that functions as the back gate electrode of the transistor M5. The conductive layer 234 is in contact with the conductive layer 213 at the opening 313. The conductive layer 215 has an area that functions as a back gate electrode of the transistor M2. The conductive layer 235 has an area that functions as an electrode of the capacitor C1, and The opening 321 contacts the conductive layer 223 .

[0157] Through the above steps, the transistors M1 to M5 and the capacitor C1 are fabricated. As shown, the capacitor C1 has conductors (216, 224, 225, 235) as electrodes and an insulator The pixel 21_R and the pixel 21_G include an edge layer 271 and an insulating layer 272 as dielectrics. , pixel 21_B, the size of one or more of transistors M1-M5 (Channel length L, channel width W) may be different. For example, W (the ratio of the channel length to the channel width) is pixel 21_G>pixel 21_G>pixel 21_B. As a result, the gate-source voltage V Even if gs2 is the same, Id2 flowing through transistor M2 can be made different (see the previous example). See equations (3) and (4) in embodiment 1).

[0158] (Fourth conductive layer) An insulating layer 274 is formed covering the insulating layer 273 and the conductive layers 231-235. 74 is a diagram showing the structure of the pixel 21, which is formed by the transistors M1-M5 and the capacitor C1. It is preferable to form the insulating layer 274 as a planarizing film for planarization. Here, a polyimide film having a thickness of 1.5 μm to 2.5 μm is formed by a coating method. Here, an exposure process is performed using a mask MK8 (not shown), and opening 3 is formed. 27E, an insulating layer 274 having the conductive layers 31-333 is formed. 22, opening 332 is an opening that reaches conductive layer 227, and opening 33 3 are openings that reach the conductive layer 225. These openings allow the second conductive layer and the first conductive layer to be separated. The four conductive layers are electrically connected.

[0159] A conductive film is formed on the insulating layer 274. Here, a conductive film having a three-layer structure is formed. The first and third layers are titanium films with a thickness of 75 nm to 125 nm, and the second layer is a 350 nm thick film. The titanium film and aluminum film are formed by sputtering or the like. A resist mask RM9 (not shown) is used to form a three-layered conductive film. Conductive layers 241-243 are formed by etching (FIG. 27E). The wiring SL is formed and is in contact with the conductive layer 222 at the opening 331. The conductive layer 227 has an area that functions as the wiring PLa and is in contact with the conductive layer 227 at the opening 332. The conductive layer 243 connects the pixel electrode (conductive layer 251) of the light-emitting element EL1 to the transistor. The conductive layer 243 has an area that functions as an electrode for electrically connecting to the photoconductor M2. contacts the conductive layer 225 at the opening 333 .

[0160] (Light-emitting element EL1) An insulating layer 275 is formed over the insulating layer 274 and the conductive layers 241-243. The insulating layer 275 can be formed in the same manner as the insulating layer 274. A polyimide film of up to 2.5 μm is formed. An exposure process using a mask MK10 (not shown) is performed. By performing the above, an insulating layer 275 having an opening 341 is formed (FIG. 28A). A light-reflective conductive film capable of reflecting light 180 is formed on the substrate. The first layer is a titanium film with a thickness of 30 nm to 70 nm, and the second layer is a titanium film with a thickness of 100 nm to 200 nm. The third layer is an aluminum film having a thickness of 5 nm to 10 nm. A resist mask RM10 (not shown) is used to form a three-layer conductive film. The conductive layer 251 is formed by etching the conductive layer 251 (FIG. 28A). The conductive layer 251 functions as an electrode of the light-emitting element EL1 and also functions as an anode of the light-emitting element EL1. At 41 it contacts the conductive layer 243 .

[0161] A conductive layer 252 is formed on the conductive layer 251 (FIG. 28B). The conductive layer 252 is formed of a light-transmitting conductive film. The conductive layer 252 is provided to form a structure between the conductive layer 251 and the conductive layer 253. The thickness of the conductive layer 252, which functions as an adjustment layer for adjusting the optical path length, is determined by taking out the pixel 21. The thickness of the conductive layer 252 is adjusted according to the wavelength (color) of the light. The thickness of the conductive layer 252 may be adjusted in the range of 100 nm to 100 nm. Indium tin oxide film (herein referred to as "SiO x The resulting film is called a "containing ITO film." ) The longer the wavelength of the light 180, the thicker the conductive layer 252 is. In the example, the thickness of the conductive layer 252 is adjusted by the number of layers of the transparent conductive film.

[0162] First, the first layer of SiO x A resist mask RM11 (not shown) is formed on the ITO film. Using this SiO x The ITO film is etched to form the pixels (21R, 21G, 21 _B), a first transparent conductive layer is formed on the pixel 21_B. 52 is completed. Next, the second layer of SiO x Form an ITO film containing resist mask RM12 (not shown) to this SiO x The ITO film is etched to form the pixel 21_R and In this step, the second transparent conductive layer of the pixel 21_G is formed. Finally, the third layer of SiO x Forming an ITO film containing resist mask This is etched using RM13 (not shown) to form a third layer of transparent conductive film on pixel 21_R. In this step, the conductive layer 252 of the pixel 21_R is completed.

[0163] An insulating layer 276 is formed on the insulating layer 275. The insulating layer 276 has a thickness of 0.8 μm to 1.2 μm by a coating method. A polyimide film with a thickness of 1 μm is formed by performing an exposure process using a mask MK14 (not shown). Thus, an insulating layer 276 having an opening 351 is formed (FIG. 28C, FIG. 25). In this step, the surface of the conductive layer 252 is exposed.

[0164] An insulating layer 277 that functions as a spacer is formed on the insulating layer 276 (FIG. 25, FIG. 28D The insulating layer 277 may be formed in the same manner as the insulating layer 276. An exposure process is performed using a mask MK15 (not shown), and an insulating layer 277 having a thickness of 1. A polyimide film having a thickness of 5 μm to 2.2 μm is formed. As shown in FIG. 28D, an insulating layer 277 The conductive layer 251 (pixel electrode) is formed as a strip-shaped structure along the wiring SL so as to overlap with the conductive layer 251 (pixel electrode). It is formed by

[0165] The insulating layer 277, the insulating layer 276 and the conductive layer 252 are covered, and the entire pixel portion 121 is covered with an EL The EL layer 260 includes one or more light-emitting layers containing at least a light-emitting material. It is sufficient that the light-emitting layer has a laminated structure with a layer other than the light-emitting layer. For example, a material having a high hole injection property, a material having a high hole transport property, a material having a poor hole transport property (a material having a high hole transport property) hole-blocking materials), materials with high electron transport properties, materials with high electron injection properties, and barrier materials. Examples of the layer include a layer containing a bipolar substance (a substance with high electron and hole transport properties). In this example, two or more light-emitting layers are provided in the EL layer 260, and the light-emitting element EL1 emits white light 180. I try to express it.

[0166] A conductive layer 253 is formed over the entire pixel portion 121, covering the EL layer 260. 3 functions as a common electrode of the pixel section 121 and also functions as a cathode of the light-emitting element EL1. In the opening 351 of the insulating layer 276, the conductive layers 251-253 and the EL layer 260 are The laminated region functions as a light-emitting region (light-emitting element EL1). The conductive layer 253 is formed of a transparent conductive film that transmits light 180 (visible light). Forming a semi-transparent electrode (semi-reflective electrode) that has both reflective and optically transparent properties In this case, a thin metal film (preferably 20 nm or less in thickness, more preferably 10 nm or less) is used. The conductive layer 253 can be formed by a stacked film of the transparent conductive film and the transparent conductive film. The thin metal film may be a single layer of silver, magnesium, or an alloy containing these metal materials. A film having a structure or a laminated structure can be used.

[0167] Through the above steps, the element substrate 101 can be fabricated.

[0168] <<Example of how to fabricate an opposing substrate>> An example of a method for manufacturing the counter substrate 171 will be described with reference to FIGS. 25 and 28. First, a light-shielding layer 280 that functions as a black matrix is ​​formed on the color substrate. Form the filter layers (281_R, 281_G, 281_B) as shown in FIG. 28E. , along the wiring SL (conductive layer 241), color filter layers (281, R, 281_G, 281_B) are formed in a band shape.

[0169] Here, the sizes of the pixels 21_R, 21_G, and 21_B (H 21 , V 21 ) (Fig. 26B) are set equal to each other, but they may be different for each luminescent color. For example, V 21 is a painting The pixel 21_R, pixel 21_G, and pixel 21_B are all the same size, and H 21 is pixel 21_B can be made the longest, and pixel 21_G and pixel 21_B can be made the same length.

[0170] <<Display panel assembly>> Through the above steps, the counter substrate 171 is completed. In this state, a sealing material is provided around the periphery of the element substrate 10. Then, an optical member is attached to the opposing substrate 171. The necessary assembly processes such as attaching the switch panel and FPC are then carried out, and the display panel is Complete the 100.

[0171] (substrate) Substrates applicable to the substrate 110 and the substrate 170 include, for example, glass substrates and quartz substrates. , plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, flexible substrate, adhesive Examples include laminated films, paper containing fibrous materials, and substrate films. Examples of the substrate include barium borosilicate glass, aluminoborosilicate glass, or silicon dioxide. Examples of flexible substrates include polyethylene terephthalate ( PET), polyethylene naphthalate (PEN), polyethersulfone (PES) Typical examples include plastics, and flexible synthetic resins such as acrylic. Examples of laminating films include polypropylene, polyester, polyvinyl fluoride, or Examples of base films include polyester, polyamide, Examples include polyimide, aramid, epoxy, inorganic vapor deposition film, and paper. In the fifth example, the substrate 170 is a substrate that transmits light 180 (visible light).

[0172] The substrate 110 is a support substrate (such as a glass substrate) used to fabricate the element substrate 101. After the pixels 21 and the like are formed, the support substrate is peeled off and the flexible substrate is attached by the adhesive layer. Similarly, the substrate 170 may also have a color filter layer (281_R, 281 It does not have to be a support substrate (glass substrate, etc.) used in the manufacture of the substrate (B, 281G, etc.), After the bar coat layer 282 is formed, the support substrate is peeled off and the flexible substrate is attached by the adhesive layer. An example of such a manufacturing method will be described later in Embodiment 5.

[0173] (Fourth embodiment) In this embodiment, several structural examples of transistors included in a semiconductor device will be described.

[0174] <<Configuration Example 1>> Here, an example of the structure of an OS transistor is described. The top view (layout diagram) of transistors (TA1 and TA2) with different structures is shown in Figure 29. 29C and 29D are cross-sectional views of the transistors (TA1 and TA2). sectional views taken along lines x1-x2 and y1-y2 of the transistor TA1, and x3-x The cross-sectional views taken along lines y4 and y3-y4 are shown in Figs. 29C and 29D. The cross-sectional structure of the TA1 and TA2 in the channel length direction is shown in FIG. 29C. The cross-sectional structure in the width direction is shown in FIG. 29D.

[0175] As shown in Figures 29C and 29D, the transistors (TA1, TA2) are connected to the same insulating surface ( These transistors are integrated on a substrate 600, and are fabricated in the same fabrication process. In order to clarify the device structure, the gate of each transistor is shown here. The wiring for supplying signals and potentials to the gate (G), source (S), and drain (D) Electrical connections are omitted. In this example, the channel length of the OS transistor is , the distance between the source electrode and the drain electrode. The channel width of the OS transistor is The width of the source electrode or drain electrode in the region where the oxide semiconductor layer and the gate electrode overlap is defined as For example, as shown in FIGS. 29A and 29B, the channel lengths of the transistors TA1 and TA2 are is La1 and the channel width is Wa1.

[0176] The transistor TA1 (FIG. 29A) and the transistor TA2 (FIG. 29B) have a gate (G) and The transistor TA1 has a back gate (BG). The transistor TA2 has a structure in which the back gate is connected to the gate. 1. It is possible to eliminate the need for BG in the transistor TA2.

[0177] <Transistor TA1> The transistor TA1 is formed on a substrate 600 and has a gate electrode GE1, a source electrode S E1, a drain electrode DE1, a back gate electrode BGE1, and an oxide semiconductor layer OS1. Has.

[0178] The layer OS1 overlaps the electrode GE1 via an insulating layer 621. A pair of electrodes (SE1, DE1) is formed in contact with the surface. The OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The layer OS1 has a length in the channel length direction longer than the channel length La1 and a channel width The length in the direction is longer than the channel width Wa1.

[0179] An insulating layer 622 and an insulating layer 623 are formed over the layer OS1, the electrode GE1, the electrode SE1, and the electrode DE1. The insulating layer 623 is formed on the insulating layer 623. The electrode BGE1 is formed on the insulating layer 623. E1 is provided so as to overlap the layer OS1 and the electrode GE1. In the layout diagram, the electrode GE1 is arranged to have the same shape and be placed in the same position as the electrode GE1. The electrode BGE1 is formed by an opening penetrating the insulating layer 621-23 and the insulating film. The gate electrode CG1 is in contact with the electrode GE1. The gate (G) and back gate (BG) are electrically connected.

[0180] As shown in the cross-sectional view in the channel width direction of FIG. 29D, the transistor TA1 has a channel forming The region (channel) has a device structure surrounded by electrodes GE1 and BGE1. Therefore, in the channel forming region of TA1, not only the electrode GE1 but also the electrode BGE1 Therefore, the back gate electrode BGE1 is affected by the electric field formed by the gate electrode. By connecting it to the gate electrode GE1, the on-current of the transistor TA1 can be increased. In addition, the field effect mobility of the transistor TA1 can be improved. Fluctuations in the electrical characteristics such as the threshold voltage of the transistor TA1 can be suppressed.

[0181] In addition, the back gate electrode BGE1 is provided to improve the strength of the transistor TA1. The electrode BGE1 acts as a reinforcing member against deformation such as bending of the substrate 600. This makes it possible to make the transistor TA1 less likely to break down.

[0182] The layer OS1 including the channel forming region has a multi-layer structure. Here, as an example, three oxides are used. The semiconductor film (631, 632, 633) has a three-layer structure. The compound semiconductor film is preferably a metal oxide film containing at least one of the same metal elements. It is particularly preferable that the semiconductor layer of the transistor contains In. Examples of metal oxides containing In include In-Ga oxide films, In-M-Zn oxide films (where M is Al, Typical examples are Ga, Y, Zr, La, Ce, or Nd. It is also possible to use a film in which other elements or materials are added to the solid film.

[0183] The oxide semiconductor film 632 is a film that forms a channel formation region of the transistor TA1. The oxide semiconductor film 633 serves as a channel formation region in the transistor TA2 described later. Therefore, in the transistor TA1, the oxide semiconductor film 632 is a film constituting the transistor. In the transistor TA2, the oxide semiconductor film 633 is formed so that a channel is formed in the oxide semiconductor film 633. It is preferable to adjust the atomic ratio of the metal elements that are the main components of 631-633.

[0184] In the transistor TA1, a channel is formed in the oxide semiconductor film 632. This prevents the channel formation region from being in contact with the insulating layers 621 and 622. In addition, the oxide semiconductor films 631 to 633 can be formed by using a metal oxide film containing at least one of the same metal element. By using an oxide semiconductor film as the oxide semiconductor film, the interface between the oxide semiconductor film 632 and the oxide semiconductor film 631 and the oxide semiconductor film The interface between the compound semiconductor film 632 and the oxide semiconductor film 633 is made less susceptible to interface scattering. This allows the field effect mobility of the transistor TA1 to be increased by and transistor TB1, and the drain current ( The on-state current can be increased.

[0185] <Transistor TA2> The transistor TA2 has a gate electrode GE2, a source electrode SE2, a drain electrode DE2, and a The gate electrode BGE2 has an insulating layer. The transistor T is in contact with the electrode GE2 at an opening GC2 that penetrates the layer 621-23. A2 is a modification of the transistor TA1, in which the layer OS2 is a single layer made of an oxide semiconductor film 633. It differs from the transistor TA1 in that it has a layered structure, but is otherwise similar. , the channel length La2 and channel width Wa2 of the transistor TA2 are The channel length La1 and the channel width Wa1 are set to be equal.

[0186] [Insulating layer] The insulating layer 621, the insulating layer 622 and the insulating layer 623 are formed with transistors (TA1, TA2). The insulating layers 621, 622 and 623 are films formed on the entire area where the insulating layer 621 is formed. The insulating layer 621 is formed of multiple insulating layers. The insulating layer 622 and the insulating layer 623 are films that form the gate insulating layer. This film constitutes the gate insulating layer on the back channel side of the gate electrodes (TA1, TA2). The insulating layer 623 on the top surface functions as a protective film for the transistors formed on the substrate 600. It is preferable to form the third electrode B from such a material. The insulating layer 623 may be provided as appropriate. To insulate GE1 from the second layer electrodes (SE1, DE1), there must be at least 1 It is sufficient that a layer insulating film exists.

[0187] [Oxide semiconductor film] Here, the oxide semiconductor film constituting the semiconductor layer of the transistors TA1 and TA2 will be described. When the semiconductor layer has a multi-layer structure like the layer OS1, the oxide semiconductors that make up the layer The metal oxide film is preferably a metal oxide film containing at least one of the same metal elements, and In is It is preferred that it contains

[0188] For example, when the oxide semiconductor film 631 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. In the case of an In-M-Zn oxide film, the atomic ratio of In is set to be smaller than the atomic ratio of M. In this case, the atomic ratio of Zn can be maximized. do.

[0189] For example, when the oxide semiconductor film 632 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. The ratio of the number of electrons is larger than that of the number of electrons in the In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the atomic ratio of In is made larger than the atomic ratio of M. In the Zn oxide film, the atomic ratio of In is larger than the atomic ratios of M and Zn. preferable.

[0190] For example, when the oxide semiconductor film 633 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. In the case of In-M-Zn oxide films, the atomic ratio of In is set to the same as or smaller than the atomic ratio of In. The atomic ratio of Zn is set to the same as the atomic ratio of M. In this case, the atomic ratio of Zn is set to be larger than that of In and M. Here, the oxide semiconductor film 633 is a transistor TA2 , and is also a film that constitutes the channel forming region of the transistor TB1.

[0191] The atomic ratio of the oxide semiconductor films 631 and 633 is This is possible by adjusting the atomic ratio of the constituent materials of the target. In this case, it is possible to adjust the flow rate ratio of the source gases. 1-633, an example of forming an In-M-Zn oxide film by sputtering. The target used for film formation will be described.

[0192] The atomic ratio of the metal elements in the target of the oxide semiconductor film 631 is In:M:Zn=x1:y1 :z1 、It is preferable that x1 / y1 is equal to or greater than 1 / 6 and less than 1. y1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

[0193] Typical examples of the atomic ratio of the metal elements in the target are In:M:Zn=1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4: 6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1: 5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn= Examples include In:M:Zn=1:5:8, In:M:Zn=1:6:8, etc.

[0194] The atomic ratio of the metal elements in the target of the oxide semiconductor film 632 is In:M:Zn=x2:y2 If you set it to :z2 、 It is preferable that x2 / y2 is greater than 1 and not greater than 6. It is preferable that / y2 is greater than 1 and not greater than 6. Typical examples are In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1: 3, In:M:Zn=3:1:4, etc.

[0195] The atomic ratio of the metal elements in the target of the oxide semiconductor film 633 is In:M:Zn=x3:y3 If you set it to :z3 、 It is preferable that x3 / y3 is 1 / 6 or more and 1 or less. It is preferable that y3 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Typical examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Zn= 1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M :Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In :M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5: 6, In:M:Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1: Examples include 6:8.

[0196] In the target for forming the In-M-Zn oxide film, the atomic ratio of the metal elements is In:M: When Zn=x:y:z, by setting 1≦z / y≦6, an In-M-Zn oxide film can be obtained. This is preferable because it makes it easier to form a CAAC-OS film. More details will be given later.

[0197] As the oxide semiconductor films 631 to 633, oxide semiconductor films with low carrier density are used. For example, the oxide semiconductor films 631 to 633 may have a carrier density of 1×10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following oxide semiconductor film is used.

[0198] The oxide semiconductor films 631 to 633 are formed of oxide semiconductors having low impurity concentrations and low density of defect states. By using a conductive film, it is possible to fabricate a transistor with even better electrical characteristics. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are highly High purity authentic or substantially high purity authentic High purity authentic or substantially high purity authentic Oxide semiconductors have few carrier generation sources, so the carrier density can be reduced in some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may The threshold voltage rarely becomes negative (also known as normally-on) In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Since the concentration is low, the trap level density may also be low. The intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 μ Even if the device has a channel length L of 10 μm, the voltage between the source and drain electrodes ( The off-state current was measured by the semiconductor parameter analyzer in the range of 1V to 10V. below the measurement limit of the -13 A or less can be obtained. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has little fluctuation in electrical characteristics. The transistors are small and highly reliable. Impurities include hydrogen, nitrogen, and alkali metals. , or alkaline earth metals, etc.

[0199] The hydrogen contained in the oxide semiconductor film reacts with the oxygen that is bonded to the metal atoms to form water, and the hydrogen Oxygen vacancies are formed in the lattice from which the atoms are desorbed (or in the areas from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. By bonding with oxygen, which bonds with metal atoms, electrons, which act as carriers, may be generated. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It's easy to become.

[0200] Therefore, in the oxide semiconductor films 631 to 633, oxygen vacancies and hydrogen are reduced as much as possible. Specifically, in the oxide semiconductor films 631 to 633, secondary ions are preferably Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration obtained by 19 atoms / cm 3 The following is more preferred: 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than preferred Or 1 x 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following applies.

[0201] When the oxide semiconductor films 631-633 contain silicon or carbon, which is one of the group 14 elements, As a result, oxygen vacancies in the film increase, and the film becomes n-type. The concentrations of silicon and carbon in 631-633 (concentrations obtained by secondary ion mass spectrometry) degrees) to 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / c m 3 The following applies.

[0202] In addition, in the oxide semiconductor films 631 to 633, The concentration of alkaline metals or alkaline earth metals is 1×10 18 atoms / cm 3 Below is good Preferably 2 x 10 16 atoms / cm 3 Alkali metals and alkaline earths When a metal bonds with an oxide semiconductor, it can generate carriers, which can cause the transistor to turn off. Therefore, the alkali metal oxide semiconductor films 631 to 633 may be used. It is preferred to reduce the concentration of metals or alkaline earth metals.

[0203] When nitrogen is contained in the oxide semiconductor films 631 to 633, electrons serving as carriers are generated, and The carrier density increases and it is easy to make it n-type. Since the transistor tends to be normally on, the oxide semiconductor films 631-633 It is preferable that the nitrogen content of the above is reduced as much as possible. For example, the nitrogen content of the above is determined by secondary ion mass spectrometry. The nitrogen concentration obtained by the method is 5 x 10 18 atoms / cm 3 It is preferable to do the following: .

[0204] Although the oxide semiconductor films 631 to 633 have been described above, the present invention is not limited to these. Depending on the semiconductor characteristics and electrical characteristics of the transistor (field effect mobility, threshold voltage, etc.) An oxide semiconductor film having an appropriate composition may be used. In order to obtain the desired properties and electrical characteristics, the carrier density and impurity concentration of the oxide semiconductor films 631 to 633 are controlled. By appropriately adjusting the concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable that:

[0205] The transistor TA1 is a Ga or M (M is Al, Ga, Y, Zr, La, Ce, or A channel is formed in the oxide semiconductor film 632 in which the atomic ratio of In is larger than the atomic ratio of Nd. Therefore, the field effect mobility can be increased. is 10cm 2 / Vs is larger than 60cm 2 / Vs less than 15cm 2 / Vs or later Upper 50cm 2 / Vs. Therefore, it is suitable for the circuit of an active matrix display device. When the transistor TA1 is used, it is suitable for a drive circuit that requires high speed operation.

[0206] The transistor TA2, whose channel formation region is formed using the oxide semiconductor film 633, Its field-effect mobility is lower than that of the TA1, and its size is 3 cm. 2 / Vs or more 10cm 2 The transistor TA2 does not include the oxide semiconductor film 632. Therefore, it is less susceptible to degradation by light than the transistor TA1, and the increase in off-state current due to light irradiation is Therefore, the transistor in which the channel formation region is formed using the oxide semiconductor film 633 The TA2 is suitable for pixel areas that are irradiated with light. 2 / Vs or less To achieve a field effect mobility of about 1000 MHz, the channel length of the transistor must be 2.5 μm or longer. This can be done.

[0207] The transistor TA1 has a higher efficiency than the transistor TA2 that does not include the oxide semiconductor film 632. When exposed to light, the current in the off state tends to increase. The peripheral circuits of the pixel area (e.g. This is one of the reasons why it is suitable for applications such as driver circuits. A transistor with such a structure can also be provided in a circuit other than the pixel portion, such as a driver circuit. be.

[0208] Although the transistors (TA1, TA2) have been described above, the present invention is not limited to these and may be applied to any other transistors as required. By changing the transistor configuration according to the semiconductor and electrical characteristics of the transistor, For example, the presence or absence of a back gate electrode, the stacked structure of the oxide semiconductor layer, the oxide semiconductor layer gate The shapes and arrangements of the gate electrode, source electrode and drain electrode can be changed as appropriate.

[0209] <<Transistor configuration example 2>> 30 and 31 show examples of the structure of a top-gate OS transistor. FIG. 30B shows a top view (layer diagram) of transistors (TA3, TA4) having different device structures. FIG. 31 shows a cross-sectional view of the transistors (TA3 and TA4). Cross-sectional view of transistor TA3 taken along lines x5-x6 and y5-y6, and x7 of transistor TA2 Cross-sectional views taken along lines -x8 and y7-y8 are shown in Figures 29C and 29D. The cross-sectional structures of TA3 and TA4 in the channel length direction are shown in FIG. 31B. The cross-sectional structure is shown in Figure 31C.

[0210] The transistors TA3 and TA4 are formed on a substrate 650. The transistor TA3 , a back gate electrode BGE3, an oxide semiconductor layer OS3 on the insulating layer 651, a source electrode SE 3, a drain electrode DE3, an insulating layer 652, and a gate electrode GE3. The electrode TA4 includes an oxide semiconductor layer OS4, a source electrode SE4, a drain electrode DE4, and an insulating layer 6 53, and a gate electrode GE4. The transistors TA3 and TA4 have an insulating layer 6 The insulating layer 653 and the insulating layer 652 function as a gate insulating film. The oxide semiconductor layer OS3 and the oxide semiconductor layer OS4 are each a single-layer oxide semiconductor film or an oxide semiconductor film. It is formed of a laminated film of a compound semiconductor film.

[0211] The gate electrode GE3 is in contact with the back gate electrode BGE3 at the opening CG3. The electrode GE3 and the back gate electrode BGE3 are not connected to each other, and different potentials are applied to them. 31B, the threshold voltage of the transistor TA3 can be controlled. As shown in the figure, the gate electrode GE3 and the back gate electrode BGE3 are connected and the same potential is applied. This increases the on-current, reduces variations in initial characteristics, and reduces degradation in GBT stress tests. and suppression of fluctuations in the on-current rise voltage at different drain voltages. is.

[0212] In the transistor TA4 and the transistor TA3, the gate electrode GE4 and the source The gate electrode GE4 and the source electrode DE4 do not overlap each other. It is possible to reduce the parasitic capacitance between the electrode SE4 and the drain electrode DE4. In addition, the gate electrode GE3 does not overlap with the source electrode SE3 and the drain electrode DE3. As a result, the parasitic capacitance between the gate electrode GE3 and the source electrode SE3 and the drain electrode DE3 is As a result, when a large-area substrate is used as the substrate 650, The source electrode SE4, the drain electrode DE4, the gate electrode GE4, and the source electrode SE 3, and the signal delay in the drain electrode DE3 and the gate electrode GE3 can be reduced. It is possible.

[0213] In the transistor TA3, a source electrode SE3, a drain electrode DE3, and a gate electrode By using GE3 as a mask, impurity elements are added to the oxide semiconductor layer OS3, and oxygen vacancies are formed. In the transistor TA4, a region having a source electrode SE4, a drain electrode SE5, and a Using the electrode DE4 and the gate electrode GE4 as a mask, a rare gas element is introduced into the oxide semiconductor layer OS4 By adding the insulating layer 654 to the insulating layer 654 containing hydrogen, a region having oxygen vacancies is formed. When the transistors TA3 and TA4 are formed of a film, the region having oxygen vacancies is Since the insulating layer 654 is in contact with the insulating layer 654 containing hydrogen, the hydrogen contained in the insulating layer 654 has oxygen vacancies. By diffusing the GaN layer into the region, a low resistance region is formed. A region can be formed.

[0214] <About oxide semiconductor films> The structure of the oxide semiconductor film will be described below.

[0215] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor (OS) films, etc. The semiconductor layer may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CAAC-OS film. It may be a laminated film having two or more of the above.

[0216] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not contain a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in the microscopic areas, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0217] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher order of molecular arrangement than the amorphous oxide semiconductor film. The defect level density is also low.

[0218] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0219] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0220] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0221] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0222] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0223] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0224] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0225] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0226] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0227] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0228] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0229] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0230] <<Transistor configuration example 3>> A transistor used in a semiconductor device according to one embodiment of the present invention may be an amorphous, microcrystalline, or polycrystalline transistor. A semiconductor film or semiconductor substrate such as silicon or germanium, which is crystalline or single crystal, The transistor may have a channel forming region. In this case, the semiconductor layer including the channel formation region is formed of a silicon film. The following describes an example of the structure of a silicon film transistor. Amorphous silicon produced by vapor phase growth or sputtering, Polycrystalline silicon and single crystal silicon wafers crystallized by laser annealing or other processes It is possible to use single crystal silicon or the like in which hydrogen ions or the like are implanted to peel off the surface layer.

[0231] FIG. 32 shows an example of the configuration of a top-gate structure transistor (TA5, TA6). The transistor TA is an n-channel transistor, and the transistor TA6 is a p-channel transistor. The transistors TA5 and TA6 are transistors of the same type. It is formed on 1.

[0232] The transistor TA5 is made up of a conductive layer 660, a conductive layer 662, a conductive layer 664, and a conductive layer 666. 66, a conductive layer 667, an insulating layer 671, an insulating layer 672, an insulating layer 673, an insulating layer 674, and and a semiconductor layer 680. The transistor TA6 has a conductive layer 661, a conductive layer 663, and a , conductive layer 665, conductive layer 668, conductive layer 669, insulating layer 671, insulating layer 672, insulating It has an edge layer 673 , an insulating layer 674 , and a semiconducting layer 681 .

[0233] The insulating layer 672 serves as an insulating layer for the transistors TA5 and TA6. The semiconductor layer 680 includes a channel forming region 682, a pair of LDDs (Light Diodes). The doped drain region 683 and a pair of impurity regions 684 are also included. The channel formation region 682 is a region of the semiconductor layer 680 that overlaps with the conductive layer 664. The pair of impurity regions 684 function as a source region and a drain region. 3, and the impurity region 684 is an impurity element that imparts n-type conductivity to the semiconductor layer 680. For example, boron (B), aluminum (Al), gallium (Ga), etc. are added. The semiconductor layer 681 has a channel formation region 685 and a pair of impurity regions 686 . The channel formation region 685 is a region of the semiconductor layer 681 that overlaps with the conductive layer 665. The impurity region 686 functions as a source region and a drain region. is an impurity element that imparts p-type conductivity to the semiconductor layer 681, such as phosphorus (P), arsenic ( As) etc. are added.

[0234] The semiconductor layer 680 or the semiconductor layer 681 may be crystallized by various techniques. Examples of the crystallization method include a laser crystallization method using a laser beam and a crystallization method using a catalytic element. Alternatively, the crystallization method using a catalyst element and the laser crystallization method can be used in combination. In addition, when a substrate having excellent heat resistance such as quartz is used as the substrate 671, Thermal crystallization using a furnace, lamp annealing crystallization using infrared light, and catalytic element crystallization A crystallization method that combines a crystallization method with high-temperature annealing at about 950° C. may also be used.

[0235] The conductive layer 660 and the conductive layer 661 are the first conductive layers. The conductive layer 661 includes a region that functions as a back gate electrode of the transistor TA5. The conductive layer 662 includes a region that functions as a back gate electrode of the transistor TA6. The layer 663 is a second conductive layer, and the conductive layers 664 and 665 are third conductive layers. The width of the conductive layer 664 in the channel length direction is shorter than that of the conductive layer 662. The width of the conductive layer 665 in the channel length direction is shorter than that of the conductive layer 663. In the conductive layer 662 and the conductive layer 664, the region overlapping with the semiconductor layer 680 via the insulating layer 672 is The region serves as the gate electrode of transistor TA5.

[0236] The conductive layers 666-669 are the fourth conductive layer. 68 includes the regions that function as the source and drain electrodes of transistor TA5. The insulating layer 673 and the insulating layer 674 are in contact with the semiconductor layer 680 through openings formed therein. The conductive layer 668 and the conductive layer 669 are the source electrode and the drain electrode of the transistor TA6. The insulating layer 673 and the insulating layer 674 include an area that functions as a drain electrode. The opening is in contact with the semiconductor layer 681 .

[0237] For example, the conductive layer 662 and the conductive layer 663 may be integrally formed, and the conductive layer 664 may be integrally formed. The conductive layer 665 is integrally formed, and the conductive layer 667 and the conductive layer 668 are integrally formed. This allows a CMOS inverter to be configured.

[0238] (Embodiment 5) As described in the third embodiment, after a semiconductor device is partially or entirely completed, It is possible to separate the substrate from which it was fabricated and transfer it to another substrate. By using this manufacturing method, transistors can be transferred to substrates with poor heat resistance or flexible substrates. do.

[0239] An example of a transfer substrate on which a transistor is transferred is a substrate for forming the above-described transistor. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide Film substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon) lon, polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon These substrates include leather substrates, and rubber substrates. By using a plate, it is possible to form transistors with good characteristics and low power consumption. It is possible to form a device that is less likely to break, to provide heat resistance, and to reduce weight or thickness. .

[0240] The transfer substrate is preferably a substrate that can be deformed when the semiconductor device is in use, such as a flexible substrate. The transfer substrate may be a substrate that does not deform during use. The substrate is not limited to a flat plate, but may also have a curved portion.

[0241] A method for manufacturing such a semiconductor device will be described below with reference to the drawings. An example of manufacturing a display panel 400 as a semiconductor device will be described.

[0242] <<Production method example 1>> An example of a method for manufacturing the display panel 400 will be described with reference to FIGS.

[0243] An insulating layer 420 is formed on a substrate 462, and an element layer 410 is formed on the insulating layer 420 (FIG. 3 3A). Semiconductor elements such as transistors are formed on the element layer 410. The sub-layer 410 includes a semiconductor element, a display element, or a part of a display element such as a pixel electrode. Here, the element layer 410 may include a pixel portion, a peripheral circuit, and a terminal portion. is formed.

[0244] The substrate 462 must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 4. It may also be used as 62.

[0245] When a glass substrate is used as the substrate 462, a silicon oxide film is formed between the substrate 462 and the insulating layer 420. When an insulating film such as a silicon oxide nitride film, a silicon nitride film, or a silicon nitride oxide film is formed, the glass This is preferable because it can prevent contamination from the substrate.

[0246] The insulating layer 420 may be made of, for example, epoxy resin, aramid resin, acrylic resin, or polyimide resin. An organic resin film such as a polyamide resin or a polyamide-imide resin can be used. It is preferable to use polyimide resin because it has high heat resistance. When a polyimide resin is used, the thickness of the polyimide resin is preferably 3 nm or more and 20 μm or less. The thickness is preferably 500 nm or more and 2 μm or less. In this case, the coating method may be a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when a polyimide resin is used as the insulating layer 420, a doctor blade By using a method, a part of the film using the polyimide resin is removed to obtain a film having a desired thickness. An insulating layer 420 can be obtained.

[0247] The element layer 410 is preferably formed at a temperature in the range of room temperature to 300° C. inclusive. For example, the insulating film or conductive film using an inorganic material included in the element layer 410 is formed at a temperature It is preferable that the film is formed at a temperature of 150°C or higher and 300°C or lower, and more preferably 200°C or higher and 270°C or lower. In addition, the insulating film and the like made of organic resin material included in the element layer 410 are formed at room temperature. It is preferable that the film is formed at a temperature of 100°C or higher.

[0248] When the transistor included in the element layer 410 is an OS transistor, the oxide semiconductor The layer is preferably the CAAC-OS film. For example, when the display panel 400 is bent, cracks or the like are less likely to occur in the channel forming region. The conductive film included in the element layer 410 can be made of a material such as silicon dioxide, which is easily resistant to bending. Therefore, when indium tin oxide with added silicon oxide is used, the display panel 400 can be folded. This is preferable because cracks and the like are less likely to occur in the conductive film when the conductive film is removed.

[0249] The element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464, and the substrate 46 The insulating layer 420 and the element layer 410 are peeled off from the substrate 2. The temporary support substrate 466 is made of glass. A glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, etc. can be used. In addition, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment is used. Alternatively, a flexible substrate such as a film may be used. Some are soluble in water or solvents, and others can be plasticized by exposure to ultraviolet light, etc. In this way, the temporary support substrate 466 and the element layer 410 can be chemically or physically separated as needed. Use an adhesive that can be used.

[0250] The transfer step onto the temporary support substrate 466 can be carried out by various methods. 33B, the insulating layer 420 is formed on the side of the insulating layer 462 on which the insulating layer 420 is not formed. By irradiating the insulating layer 420 with laser light 468, the insulating layer 420 is weakened, and the substrate 46 2 and the insulating layer 420. By adjusting the density, it is possible to obtain a region where the substrate 462 and the insulating layer 420 have high adhesion and a region where the substrate 462 and the insulating layer 420 have high adhesion. It is also possible to separate the insulating layer 420 into areas with low adhesion and then peel it off.

[0251] In this embodiment, a method of peeling at the interface between the substrate 462 and the insulating layer 420 is exemplified. However, the peeling method is not limited to this. Alternatively, a liquid may be allowed to penetrate into the interface between the substrate 462 and the insulating layer 420 to separate the substrate 462. Alternatively, the insulating layer 420 may be peeled off from the interface between the insulating layer 420 and the element layer 410. The element layer 410 may be peeled off from the insulating layer 420 by allowing a liquid to penetrate into the insulating layer 420. For example, water, a polar solvent, etc. can be used. In this case, the liquid is present at the interface between the substrate 462 and the insulating layer 420 or at the interface between the insulating layer 420 and the element layer 410. By penetrating the body, static electricity and the like generated by peeling given to the element layer 410 can be prevented. The impact can be reduced.

[0252] Adhesion layer 418 is used to attach substrate 401 to insulating layer 420 (FIG. 33C). The release adhesive 464 is dissolved or plasticized to remove the release adhesive 464 and the adhesive from the device layer 410. The temporary support substrate 466 is then removed (FIG. 33D). It is preferable to remove the adhesive 464 with water or a solvent. A device substrate 400a can be fabricated having a layer 410.

[0253] 33, an adhesive layer 412 and an adhesive layer 412 An upper insulating layer 440 and an element layer 411 are formed (FIG. 34A). The edge layer 440 is formed using the same material as the insulating layer 420, which is an organic resin in this case. For example, a color filter layer and a light-shielding layer may be provided as the element layer 411. In this process, the element substrate (counter substrate) 400b can be fabricated.

[0254] Next, a sealing layer 432 is filled between the element layer 410 and the element layer 411, and the element layer 410 and the element layer 411 are sealed. The layer 411 is bonded to the substrate 410 (FIG. 34B). The sealing layer 432 provides, for example, solid sealing. However, it is preferable that the sealing layer 432 has flexibility. 432 is, for example, a glass material such as glass frit or a two-component mixed resin. Use resin materials such as room temperature curing resin, photocuring resin, and thermosetting resin. As a result, a device having the element substrate 400a and the element substrate (opposite substrate) 400b can be obtained. A display panel 400 can be fabricated.

[0255] <<Production method example 2>> Next, another method for manufacturing the display panel 400 according to one embodiment of the present invention will be described with reference to FIG. In FIG. 35, inorganic insulating films are used as the insulating layers 420 and 440. The configuration used will be explained.

[0256] First, a separation layer 463 is formed over a substrate 462. Next, an insulating layer 420 is formed over the separation layer 463. Then, the element layer 410 is formed on the insulating layer 420 (FIG. 35A).

[0257] The peeling layer 463 may be made of, for example, tungsten, molybdenum, titanium, tantalum, or niobium. , Nickel, Cobalt, Zirconium, Zinc, Ruthenium, Rhodium, Palladium, Os An element selected from the group consisting of tungsten, iridium, and silicon, an alloy material containing the element, or The material may be a compound material containing silicon, and may have a single layer or a laminated structure. In the case of a layer containing silicon, the crystalline structure of the layer containing silicon may be amorphous, microcrystalline, polycrystalline, or the like. The peeling layer 463 may be formed by sputtering or PECVD. The coating method may be a spin coating method, a droplet ejection method, or the like. Includes dispensing and dispensing methods.

[0258] When the release layer 463 has a single layer structure, it is made of tungsten, molybdenum, or tungsten and molybdenum. It is preferable to form a layer containing a mixture of tungsten and tungsten oxide. a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of stainless steel and molybdenum may also be formed. The mixture of tungsten and molybdenum is, for example, an alloy of tungsten and molybdenum. is equivalent to

[0259] The peeling layer 463 may be a stack of a layer containing tungsten and a layer containing tungsten oxide. When forming a layer structure, a layer containing tungsten is formed, and an upper layer made of oxide is formed. By forming an insulating layer, tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Alternatively, the surface of the layer containing tungsten may be treated with a thermal acid. The oxidizing power of chemical treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, ozone water, etc. A layer containing tungsten oxide may be formed by treatment with a strong solution. The smearing and heating processes may be carried out using oxygen, nitrogen, or nitrous oxide alone, or in combination with other gases. The above plasma treatment or heat treatment may be performed under a mixed gas atmosphere. By changing the surface condition of the peeling layer 463, the adhesiveness between the peeling layer 463 and the insulating layer 420 to be formed later can be improved. It is possible to control the

[0260] The insulating layer 420 may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. An inorganic insulating film with low moisture permeability, such as a silicon film or an aluminum oxide film, can be used. The inorganic insulating film can be formed by using, for example, a sputtering method, a PECVD method, or the like. Cut.

[0261] Next, the element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464, and then peeled off. The insulating layer 420 and the element layer 410 are peeled off from the release layer 463. The sub-layer 410 is provided on the temporary support substrate 466 side (FIG. 35B).

[0262] The transfer step onto the temporary support substrate 466 can be carried out by various methods as appropriate. For example, When a layer containing a metal oxide film is formed at the interface between the peeling layer 463 and the insulating layer 420, the metal The oxide film is weakened by crystallization, and the insulating layer 420 can be peeled off from the peeling layer 463. In addition, when the peeling layer 463 is formed using a tungsten film, ammonia water and hydrogen peroxide are used. The tungsten film may be removed while being etched with a mixed solution of water.

[0263] In addition, a liquid is allowed to penetrate into the interface between the release layer 463 and the insulating layer 420 to separate the insulating layer 420 from the release layer 463. The liquid may be, for example, water, a polar solvent, or the like. At the interface where the insulating layer 420 is peeled off, specifically at the interface between the peeling layer 463 and the insulating layer 420, By allowing the liquid to penetrate, static electricity and the like that are generated due to peeling that is given to the element layer 410 can be eliminated. The influence of the above can be suppressed.

[0264] Next, the substrate 401 is bonded to the insulating layer 420 using the adhesive layer 418 (FIG. 35C). The release adhesive 464 is dissolved or plasticized to remove the release adhesive 464 from the device layer 410. The temporary support substrate 466 is removed (FIG. 35D). It is preferable to remove the peeling adhesive 464 with water or a solvent. A device substrate 400a having a device layer 410 can be fabricated.

[0265] Next, by the same manufacturing method as the process shown in FIG. 35, a substrate 405 and an adhesive layer on the substrate 405 are 412, an insulating layer 440 on the adhesive layer 412, and an element substrate (counter substrate) having an element layer 411. Then, as shown in FIG. 31D, element layer 410 and element layer 411 are formed. The sealing layer 432 is filled between the element layers 410 and 411, and the element layers 410 and 411 are bonded together. In this process, the display panel 400 can be fabricated.

[0266] The display panel 400 shown in FIG. 31D has an FP formed by an anisotropic conductive film at the terminal portion of the element layer 410. C. Also, if necessary, an IC chip or the like can be mounted.

[0267] (Sixth embodiment) In this embodiment, a display device and a semiconductor device including a display unit (display device) are used as an example of the semiconductor device. The display device (or display) described in the first embodiment will be described. The display panel can be applied to the display unit of an electronic device.

[0268] <<Display device>> FIG. 36A is a perspective view showing an example of the appearance of a display device. The device 1610 includes a panel 1601, a circuit board 1602, and a connection portion 1603. The panel 1601 includes a pixel section 1604 having a plurality of pixels and a display section 1605 for selecting the plurality of pixels for each row. a driver circuit 1605 for controlling the input of an image signal Sig to the pixels in the selected row; The circuit board 1602 includes a controller, a power supply circuit, an image processing circuit, and , image memory, CPU, etc.

[0269] Various signals and power supply potentials are transmitted from the circuit board 1602 to the panel via the connection part 1603. The signal is input to 1601. An FPC or the like can be used for the connection part 1603. FPC When a chip is mounted on a board, it is called COF tape. In addition, COF tape is used for the connection part 1603. In this case, a part of the circuit in the circuit board 1602 or the driving circuit 1601 of the panel 1601 may be 1605 and part of the driver circuit 1606 are formed on a separately prepared chip, and then the COF method is used. The chip may be connected to the COF tape.

[0270] FIG. 36B is a perspective view showing an example of the appearance of a display device using the COF tape 1607. As shown in FIG. 36B, in the display device 1611, the chip 1608 is It is a semiconductor bare chip (IC, LSI, etc.) with terminals on the surface. CR components can also be mounted on the flexible substrate 1607, and the area of ​​the circuit board 1602 can be reduced. The wiring patterns on the cable board are formed in multiple patterns corresponding to the terminals of the chip to be mounted. 608 is positioned on a flexible substrate having a wiring pattern by a bonder device or the like. The components are then soldered together and mounted by thermocompression.

[0271] FIG. 36B shows an example of one COF tape 1607 on which one chip 1608 is mounted. However, this is not particularly limited. Multiple rows of chips can be mounted on one or both sides of one COF tape 1607. However, to reduce costs, it is necessary to reduce the number of chips to be implemented. It is preferable to have one row, and more preferably one.

[0272] <Example of circuit board configuration> 37 shows an external view of the circuit board 2003. The circuit board 2003 has a slit 2211. On the FPC2201, which has Bluetooth (registered trademark) IEEE802.15.1 ) standard communication device 2101, microcomputer 2102, storage device 2103, FPGA 2 104, a DA converter 2105, a charge control IC 2106, and a level shifter 2107 are provided. The circuit board 2003 also has a configuration in which the input / output connector 2108 is connected to the The FPC 2201 is electrically connected to the display device according to one embodiment of the present invention. By providing this, the flexibility of the circuit board 2003 using the FPC 2201 is increased.

[0273] By using a flexible substrate for the display device, the display device can be bent along with the circuit board 2003. Therefore, the display device using the flexible substrate and the circuit board 200 3. It can be repeatedly deformed to fit the shape of the part of the body where it is worn, so it can be worn on the arms, legs, etc. It is suitable for use in electronic devices that can be worn on the body.

[0274] <<Configuration example of information processing device>> FIG. 38A is a schematic diagram illustrating the appearance of the information processing device 1000, and FIG. 38B is a schematic diagram illustrating the appearance of the information processing device 1000. 38C and 38D are schematic diagrams illustrating the structure of a cross section taken along the line z1-z2 of FIG. 38C and 38D are schematic diagrams illustrating the external appearance of the information processing device 1000. FIG. 38C is a schematic diagram illustrating the structure of a cross section taken along line z3-z4 of the information processing device. 38A is a schematic diagram illustrating the front of the information processing device 1000, and FIG. 38B is a schematic diagram illustrating the rear of the information processing device 1000. This is a schematic diagram.

[0275] As shown in FIGS. 38C and 38D, the position input unit 1001 or the display unit 1002 is an information processing unit. The positioning device 1000 may be provided not only on the front surface but also on the side surface or rear surface. The input unit 1001 or the display unit 1002 may be provided on the top surface of the information processing device 1000. The position input unit 1001 or the display unit 1002 may be mounted on the bottom surface of the information processing device 1000. It may be provided in.

[0276] In addition to the position input unit 1001, the surface of the housing 1003 is provided with hardware buttons and external connectors. It may also have a connection terminal or the like.

[0277] By adopting such a configuration, it is possible to prevent the display device from being parallel to the front of the housing 1003 as in the case of a conventional information processing device. It is possible to display not only on the front surface but also on the side surface of the housing 1003. In addition, providing display areas along two or more sides of the housing 1003 increases the variety of displays. This is preferable.

[0278] A display area arranged along the front of the information processing device and each display area arranged along the side Each of the two may be used as an independent display area to display different images, etc. For example, an image may be displayed across two or more display areas of an information processing device. The image to be displayed in the display area arranged along the side of the information processing device is displayed on the display area arranged along the side of the information processing device. The images may be displayed continuously in a display area.

[0279] The arithmetic unit 1005 is provided inside the housing 1003. In FIG. The device 1005 is provided at a position separated from the display unit 1002. A display unit 1005 is provided at a position overlapping the display unit 1002 .

[0280] The position input unit 1001 includes, for example, a first area 1001(1) and a second area 100(2). a second region 1001(2) facing the first region 1001(1) and ... the second region 1001(2) facing the second region 1001(1) The third region 1001(3) is formed between the first region 1001(2) and the second region 1001(3). As another example, the first region 1 has flexibility that allows the first region 1 to be 001(1), a third region 1001(3), and a third region 1001(4) facing the third region 1001(3). The area 1001(4) has flexibility so that it can be bent to form the area 1001(4). (See Figure 38E).

[0281] As another example, a third region 1001(3), a fifth region 1001(5), and a third region 1001(6) are provided. The third region 1001(3) is folded to form a fourth region 1001(4) facing the third region 1001(3). The substrate may have flexibility so that it can be bent.

[0282] The second region 1001(2) facing the first region 1001(1) is arranged in the same manner as the first region 1001(1). The arrangement is not limited to facing the area 1001(1), but may be tilted toward the first area 1001(1). Also, a fourth area facing the third area 1001(3) is included. The arrangement of the area 1001(4) is not limited to being directly opposite the third area 1001(3), but may be This also includes an arrangement in which the area faces the area 1001(3) at an angle.

[0283] The display unit 1002 includes at least a first area 1001(1), a second area 1001(2), Arranged so as to overlap a part of the third area 1001(3) or the fourth area 1001(4). will be done.

[0284] The information processing device 1000 includes a flexible position input unit 100 that detects an object in proximity or in contact with the object. 1. The position input unit 1001 is configured to include, for example, a first area 1001( 1), a second region 1001(2) facing the first region, and a first region 1001(1). A third area 1001(3) overlapping the display unit 1002 is formed between the second area 1001(2). ) and can be folded to form a palm or hand. Either of the fingers is in the first area 1001(1) or the second area 1001(2), etc. As a result, it is possible to realize a human interface with excellent operability. Alternatively, a novel information processing device with excellent operability can be provided.

[0285] The substrate used for the display unit 1002 can be made of a resin having a thickness that is flexible. Examples of resins include polyester, polyolefin, polyamide, polyimide, and Examples of the resin include acrylate, epoxy, polycarbonate, and acrylic resin. In addition, typical substrates that do not have flexibility include glass substrates, quartz substrates, semiconductor substrates, etc. etc. can be used.

[0286] <<Examples of electronic device configurations>> The semiconductor device according to one embodiment of the present invention is used in a display device, a notebook personal computer (PC), ), image playback devices equipped with recording media (typically DVD: Digital Versatile Media) A device having a display that can play back recording media such as a DVD disc and display the images. In addition, the semiconductor device according to one embodiment of the present invention can be used in Electronic devices that can be used include mobile phones, portable game consoles, personal digital assistants, e-book readers, video Cameras such as digital cameras and digital still cameras, goggle-type displays (head-mounted display), navigation system, sound reproduction equipment (car audio, digital audio players, copiers, fax machines, printers, multi-function printers, Examples of such electronic devices include automated teller machines (ATMs) and vending machines. An example is shown in Figure 39.

[0287] 39A shows an example of the configuration of a display device. The display device 5200 includes a housing 5201, a display unit 5 202, a support stand 5203, etc. There is no particular restriction on the use of the display device 5200. For example, all information displays for personal computers, TV broadcast reception, advertisement display, etc. A display device is included.

[0288] 39B shows an example of the configuration of a mobile information terminal. The mobile information terminal 5100 includes a housing 5101, The device has a display unit 5102, operation keys 5103, and the like.

[0289] FIG. 39C shows an example of the configuration of a display device. A display device 5700 includes a housing 5701 and a display The display unit 5702 is supported by a curved housing 5701. The display portion 5702 is provided with a display panel using a flexible substrate. It is possible to provide a display device 5700 that is flexible, lightweight, and easy to use.

[0290] FIG. 39D shows an example of the configuration of a portable game machine. The portable game machine 5300 has a housing 530 1, housing 5302, display unit 5303, display unit 5304, microphone 5305, speaker The portable game machine has a display 5306, operation keys 5307, and a stylus 5308. The display 5300 has two display units, 5303 and 5304. The number is not limited to this, and may be one, or three or more.

[0291] An example of the configuration of an electronic book terminal is shown in FIG. 39E. The electronic book terminal 5600 includes a housing 5601, and a display portion 5602. The display portion 5602 is a display panel using a flexible substrate. This allows us to create a flexible, lightweight and user-friendly e-book reader 5600. can be provided.

[0292] FIG. 39F shows an example of the configuration of an information terminal 5900. The information terminal 5900 is housed in a housing 5901. , display unit 5902, microphone 5907, speaker 5904, camera 5903, external The display unit 5902 has a connection unit 5906, an operation button 5905, etc. The information terminal 5900 is, for example, a smartphone. It can be used as a mobile phone, tablet information terminal, tablet PC, e-book terminal, etc. This can be done. [Explanation of symbols]

[0293] 10, 20, 21 pixels M1, M2, M3, M4, M5 transistors C1 capacitor EL1 light-emitting element

[0294] This application is Japanese Patent Application No. 2014-037 filed with the Japan Patent Office on February 27, 2014. 156 and by reference to all the contents of the Japanese application. and is incorporated herein by reference.

Claims

1. It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a data line, a first initialization line, a second initialization line, a potential supply line, and a light-emitting element. Either the source or the drain of the first transistor is in conductivity with the data line. The source or drain of the first transistor is electrically connected to the source or drain of the fourth transistor. Either the source or the drain of the fourth transistor is in electrical contact with the capacitor. The capacitor has the function of maintaining the potential of either the source or the drain of the fourth transistor. The source or drain of the fourth transistor, the other of which is in conductivity with the gate of the second transistor, The gate of the second transistor is electrically connected to either the source or the drain of the third transistor. The source or drain of the third transistor, the other of which is in conductivity with the first initialization line, The source or drain of the fifth transistor is in electrical contact with the light-emitting element. The source or drain of the fifth transistor, the other of which is in conductivity with the second initialization line, A first conductive layer having the function of a potential supply line and a second conductive layer having the function of a data line are arranged in the same layer. The first conductive layer is electrically connected to either the source or the drain of the second transistor via the third conductive layer. The third conductive layer is arranged in the same layer as the fourth conductive layer. The fourth conductive layer is electrically connected to the other of the source or drain of the second transistor. The fourth conductive layer is electrically connected to either the source or the drain of the fifth transistor. A fifth conductive layer having the function of the second initialization line is provided, The sixth conductive layer functions as the gate electrode of the first transistor. The seventh conductive layer functions as the gate electrode of the second transistor. The eighth conductive layer functions as the gate electrode of the third transistor. The ninth conductive layer functions as the gate electrode of the fifth transistor. The sixth conductive layer, the seventh conductive layer, the eighth conductive layer, and the ninth conductive layer are arranged in the same layer. The sixth conductive layer is positioned above the channel formation region of the first transistor. The seventh conductive layer is positioned above the channel formation region of the second transistor. The eighth conductive layer is positioned above the channel formation region of the third transistor. The ninth conductive layer is positioned above the channel formation region of the fifth transistor. The tenth conductive layer, which functions as the first initialization line, is arranged in the same layer as the fifth conductive layer. In a top view, the semiconductor layer of the second transistor has a region that overlaps with the first conductive layer. The semiconductor layer has a channel formation region for the second transistor, The fourth conductive layer is in electrical contact with the pixel electrodes of the light-emitting element, in a semiconductor device.

2. It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a data line, a first initialization line, a second initialization line, a potential supply line, and a light-emitting element. Either the source or the drain of the first transistor is in conductivity with the data line. The source or drain of the first transistor is electrically connected to the source or drain of the fourth transistor. Either the source or the drain of the fourth transistor is in electrical contact with the capacitor. The capacitor has the function of maintaining the potential of either the source or the drain of the fourth transistor. The source or drain of the fourth transistor, the other of which is in conductivity with the gate of the second transistor, The gate of the second transistor is electrically connected to either the source or the drain of the third transistor. The source or drain of the third transistor, the other of which is in conductivity with the first initialization line, The source or drain of the fifth transistor is in electrical contact with the light-emitting element. The source or drain of the fifth transistor, the other of which is in conductivity with the second initialization line, A first conductive layer having the function of a potential supply line and a second conductive layer having the function of a data line are arranged in the same layer. The first conductive layer is electrically connected to either the source or the drain of the second transistor via the third conductive layer. The third conductive layer is arranged in the same layer as the fourth conductive layer. The fourth conductive layer is electrically connected to the other of the source or drain of the second transistor. The fourth conductive layer is electrically connected to either the source or the drain of the fifth transistor. A fifth conductive layer having the function of the second initialization line is provided, The sixth conductive layer functions as the gate electrode of the first transistor. The seventh conductive layer functions as the gate electrode of the second transistor. The eighth conductive layer functions as the gate electrode of the third transistor. The ninth conductive layer functions as the gate electrode of the fifth transistor. The sixth conductive layer, the seventh conductive layer, the eighth conductive layer, and the ninth conductive layer are arranged in the same layer. The sixth conductive layer is positioned above the channel formation region of the first transistor. The seventh conductive layer is positioned above the channel formation region of the second transistor. The eighth conductive layer is positioned above the channel formation region of the third transistor. The ninth conductive layer is positioned above the channel formation region of the fifth transistor. The tenth conductive layer, which functions as the first initialization line, is arranged in the same layer as the fifth conductive layer. In a top view, the semiconductor layer of the second transistor has a region that overlaps with the first conductive layer. The semiconductor layer has a channel formation region for the second transistor, The fourth conductive layer is electrically connected to the pixel electrode of the light-emitting element, In a top view, the first conductive layer has a region extending in a first direction, In a top view, the second conductive layer has a region extending in the first direction, In a top view, the fifth conductive layer has a region that extends in a second direction different from the first direction, In a top view, the fifth conductive layer has a region that intersects with the first conductive layer and a region that intersects with the second conductive layer, In a top view, the tenth conductive layer has a region extending in the second direction, A semiconductor device in which, in a top view, the tenth conductive layer has a region that intersects with the first conductive layer and a region that intersects with the second conductive layer.

3. In claim 1 or 2, The first conductive layer is provided in contact with the upper surface of the insulating layer. The first conductive layer is electrically connected to the third conductive layer through an opening provided in the insulating layer. The insulating layer is disposed between the third conductive layer and the first conductive layer. The insulating layer is disposed between the fourth conductive layer and the first conductive layer. The insulating layer is disposed between the fifth conductive layer and the first conductive layer. The insulating layer is disposed between the sixth conductive layer and the first conductive layer. The insulating layer is disposed between the seventh conductive layer and the first conductive layer. The insulating layer is disposed between the eighth conductive layer and the first conductive layer. The insulating layer is disposed between the ninth conductive layer and the first conductive layer. A semiconductor device wherein the insulating layer is disposed between the tenth conductive layer and the first conductive layer.

4. In any one of claims 1 to 3, When the first transistor is ON, a data signal is supplied from the data line to either the source or drain of the fourth transistor and to the capacitor. When the second transistor is in the ON state, a period is provided during which potential is supplied to the light-emitting element from the potential supply line through the source and drain of the second transistor. When the third transistor is ON, a first initialization signal is supplied from the first initialization line through the third transistor to the gate of the second transistor. When the fourth transistor is in the ON state, the charge of the capacitor is supplied to the gate of the second transistor. A semiconductor device wherein, when the fifth transistor is in the ON state, a second initialization signal is supplied to the light-emitting element from the second initialization line via the fifth transistor.

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