Solar cell and its manufacturing method

Abstract

The present application provides a solar cell and a method for manufacturing the same. [Solution] A solar cell includes a silicon substrate having opposing first and second surfaces, a first doping layer on the first surface, a second doping layer on the second surface having a doping type opposite to that of the first doping layer, a first electrode connected to the first doping layer, a second electrode connected to the second doping layer, and an isolation groove that penetrates the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode. The solar cell of this application avoids leakage of the solar cell due to a short circuit by separating the electrode from the edge of the cell using the isolation groove that penetrates the first doping layer.

Description

[Technical Field]

[0001] This application relates primarily to the field of photovoltaics, and more particularly to solar cells and methods for their manufacture. [Background technology]

[0002] Among the many solar energy technologies, solar cells have attracted attention for their ability to convert solar energy into electrical energy. When exposed to light, solar cells generate electron-hole pairs, which are separated inside the cell and migrate to the two poles of the cell. With the advancement of solar cell technology, an increasing number of solar cell types have been developed. Currently, solar cell types mainly include passivated emitter and rear contact (PERC), tunnel oxide passivated contact (TOPCON), heterojunction solar cells (HIT), and interdigitated back contact (IBC). During solar cell manufacturing, factors such as the manufacturing process and production environment can cause short-circuit currents in solar cells during operation, such as undesired contact between electrodes and some functional layers of the solar cell. Short-circuit currents reduce the efficiency of solar cells, and internal short-circuit currents should be avoided. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical problem to be solved by the present application is to provide a solar cell that can prevent leakage of the solar cell due to a short circuit, and a method for manufacturing the same. [Means for solving the problem]

[0004] The technology used in the present application to solve the above-mentioned technical problem is a solar cell comprising: a silicon substrate having a first surface and a second surface opposite to each other; a first doping layer provided on the first surface; a second doping layer provided on the second surface and having a doping type opposite to that of the first doping layer; a first electrode connected to the first doping layer; a second electrode connected to the second doping layer; and a separation groove that penetrates the first doping layer along the thickness direction of the silicon substrate and surrounds the first electrode.

[0005] In one embodiment of the present application, the distance between the isolation groove and the edge of the first doping layer is less than a predetermined distance, and the predetermined distance is between 10 μm and 2000 μm.

[0006] In one embodiment of the present application, the semiconductor device further comprises a tunnel layer, the tunnel layer being disposed on the second surface, and the second doped layer being disposed on a surface of the tunnel layer away from the silicon substrate.

[0007] In one embodiment of the present application, the tunnel layer extends to a side surface of the silicon substrate and covers at least a portion of the side surface of the silicon substrate, the second doping layer covers a surface of the tunnel layer that faces away from the silicon substrate, and the height of the tunnel layer located on the side surface of the silicon substrate is 0.1 μm or more and less than the thickness of the silicon substrate.

[0008] In one embodiment of the present application, the semiconductor device further comprises a first passivation layer disposed on a surface of the first doped layer away from the silicon substrate.

[0009] In one embodiment of the present application, the first passivation layer covers the bottom and sidewalls of the isolation trench.

[0010] In one embodiment of the present application, the semiconductor device further comprises a second passivation layer disposed on a surface of the second doped layer away from the silicon substrate.

[0011] To solve the above-mentioned technical problems, the present application further proposes a method for manufacturing a solar cell, including the steps of: providing a silicon substrate having first and second surfaces opposite to each other; forming a first doping layer on the first surface of the silicon substrate; sequentially forming a tunnel layer and a second doping layer on the second surface of the silicon substrate, wherein the doping type of the first doping layer is opposite to that of the second doping layer; forming a first electrode connected to the first doping layer; forming a second electrode connected to the second doping layer; and forming an isolation groove that penetrates the first doping layer along a thickness direction of the silicon substrate and surrounds the first electrode.

[0012] In one embodiment of the present application, the method for forming the tunnel layer and the second doped layer includes: forming an initial tunnel layer on the second surface, a side surface of the silicon substrate, and a surface of at least a portion of the first doped layer that is away from the silicon substrate; forming an initial second doped layer on the surface of the initial tunnel layer that is away from the silicon substrate; and removing the initial tunnel layer and the initial second doped layer on the first doped layer to form the tunnel layer and the second doped layer.

[0013] In one embodiment of the present application, the isolation groove is formed after the step of forming the initial tunnel layer and the initial second doping layer and before the step of removing the initial tunnel layer and the initial second doping layer in the first doping layer.

[0014] In one embodiment of the present application, a portion of the initial tunnel layer and the initial second doping layer on the side of the silicon substrate is further removed so that the height of the tunnel layer and the second doping layer located on the side of the silicon substrate is greater than or equal to 0.1 μm and less than or equal to the thickness of the silicon substrate.

[0015] In one embodiment of the present application, the distance between the isolation groove and the edge of the first doping layer is less than a predetermined distance, and the predetermined distance is between 10 μm and 2000 μm.

[0016] In one embodiment of the present application, a first passivation layer is formed on a surface of the first doped layer facing away from the silicon substrate.

[0017] In one embodiment of the present application, the first passivation layer is formed after the step of forming the isolation groove.

[0018] In one embodiment of the present application, a second passivation layer is formed on a surface of the second doped layer that faces away from the silicon substrate.

[0019] In one embodiment of the present application, the isolation groove is formed after the step of forming the second passivation layer.

[0020] The solar cell and its manufacturing method of the present application avoids leakage of the solar cell due to short circuits by isolating the electrode and the edge of the cell using an isolation groove that penetrates the first doping layer.

[0021] In order to make the above objects, features, and advantages of the present application more clearly understandable, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a schematic plan view of a solar cell according to an embodiment of the present application; [Figure 2] 2 is a cross-sectional view of the solar cell of the embodiment taken along line AA in FIG. 1. [Figure 3] FIG. 2 is a cross-sectional view taken along line AA of the solar cell in FIG. 1 according to another embodiment. [Figure 4] 1 is an exemplary flowchart of a method for manufacturing a solar cell according to an embodiment of the present application. [Figure 5] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 6] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 7] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 8] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 9] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 10] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 11] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 12] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 13] 1A-1C are cross-sectional schematic diagrams of intermediate products of a solar cell manufacturing process in one embodiment. [Figure 14] 10 is an exemplary flow chart for forming isolation trenches in different embodiments. [Figure 15] 10 is an exemplary flow chart for forming isolation trenches in different embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0023] In order to make the above objects, features, and advantages of the present application more clearly understandable, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application; however, the present application may also be practiced in other ways than those described herein, and therefore the present application is not limited to the specific examples disclosed below.

[0025] As set forth in this application and the claims, unless the context clearly indicates otherwise, terms such as "a," "one," "one," "a kind," and / or "the" do not specifically refer to the singular but may also include the plural. Generally, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, and do not constitute an exclusive list of these steps and elements; a method or apparatus may include other steps or elements.

[0026] It should also be explained that the use of terms such as "first" and "second" to define components is merely to facilitate distinguishing between corresponding components, and that unless otherwise stated, the above terms have no special meaning and should not be understood as limitations on the scope of protection of the present application. Furthermore, although the terms used in the present application are selected from well-known terms, some terms described in the specification of the present application have been selected by the applicant at his / her own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. It is also required to understand the present application not only based on the actual terms used but also on the meanings contained in each term.

[0027] Flowcharts are used herein to describe the operations performed by the system according to the embodiments of the present application. It will be understood that the operations described above or below are not necessarily intended to be performed in exact order. Instead, various steps may be processed in reverse order or simultaneously. Concurrently, other operations may be added to these processes, or operations of certain steps or steps may be deleted from these processes.

[0028] Next, the solar cell and the manufacturing method thereof according to the present invention will be described with reference to specific examples.

[0029] Fig. 1 is a schematic plan view of a solar cell according to one embodiment, and Fig. 2 is a schematic cross-sectional view of the solar cell according to one embodiment taken along line AA in Fig. 1, with part of the first electrode simply omitted in Fig. 2. As shown in Figs. 1 and 2, the solar cell includes a silicon substrate 110, a first doping layer 120, a second doping layer 130, a first electrode 140, a second electrode 150, and an isolation groove 160.

[0030] 2, the silicon substrate 110 has a first surface 111 and a second surface 112 that face each other in a thickness direction D3, and two side surfaces 113 that face each other in a first direction D1. It is understood that the silicon substrate 110 also has two side surfaces that face each other in a second direction D2. The first surface 111 and the second surface 112 may have a pyramidal pile shape that helps reduce the reflection of incident light from the solar cell.

[0031] The silicon substrate 110 may be a doped monocrystalline silicon wafer or a doped polycrystalline silicon wafer, and the doping type may be N-type doping or P-type doping. If the silicon substrate 110 is N-type doped, the dopant may be one or more selected from phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). If the silicon substrate 110 is P-type doped, the dopant may be one or more selected from boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0032] The first doped layer 120 is provided on the first surface 111. The term "provided" means that the first doped layer 120 is in direct contact with the first surface 111, and other functional layers are provided between the first doped layer 120 and the first surface 111. This description also applies to subsequent documents, and will not be expanded upon in subsequent documents. In FIG. 2 , the first doped layer 120 is in direct contact with the first surface 111. A method for forming the first doped layer 120 includes doping the silicon substrate 110 to convert a portion of the silicon substrate 110 into the first doped layer 120. In addition to the above method, the first doped layer 120 can also be deposited on the first surface 111 by a deposition process. The first doped layer 120 may be doped monocrystalline silicon or doped polycrystalline silicon.

[0033] A second doped layer 130 is provided on the second surface 112. The second doped layer 130 may be doped polycrystalline silicon. When the second doped layer 130 is doped polycrystalline silicon, a method of forming the second doped layer 130 comprises depositing amorphous silicon on the second surface 112, doping the amorphous silicon in the layer, and heat treating the doped amorphous silicon to convert the amorphous silicon to polycrystalline silicon.

[0034] The doping type of the second doped layer 130 is opposite to the doping type of the first doped layer 120, and one of the doped layers has the same doping type as the silicon substrate 110. For example, there are the following cases:

[0035] The silicon substrate 110 is N-type doped, the first doped layer 120 is P-type doped, and the second doped layer 130 is N-type doped, and the first doped layer 120 forms a PN junction with the silicon substrate 110 .

[0036] The silicon substrate 110 is N-type doped, the first doped layer 120 is N-type doped, and the second doped layer 130 is P-type doped, and the second doped layer 130 forms a PN junction with the silicon substrate 110 .

[0037] The silicon substrate 110 is P-type doped, the first doped layer 120 is N-type doped, and the second doped layer 130 is P-type doped, and the first doped layer 120 forms a PN junction with the silicon substrate 110 .

[0038] The silicon substrate 110 is P-type doped, the first doped layer 120 is P-type doped, and the second doped layer 130 is N-type doped, and the second doped layer 130 forms a PN junction with the silicon substrate 110 .

[0039] In the above case, the doping concentration of the first doped layer 120 may be greater than the doping concentration of the silicon substrate 110 , and the doping concentration of the second doped layer 130 may be greater than the doping concentration of the silicon substrate 110 .

[0040] For convenience of explanation, a solar cell will be described using an example of an N-type doped silicon substrate 110, a P-type doped first doped layer 120, and an N-type doped second doped layer 130. Here, the doping concentration of the second doped layer 130 is greater than the doping concentration of the silicon substrate 110.

[0041] As shown in FIG. 2, the first electrode 140 is in contact with and connected to the first doping layer 120, and the second electrode 150 is in contact with and connected to the second doping layer 130. The first electrode 140 and the second electrode 150 may be used to extract electrical energy generated in the solar cell. As shown in FIG. 1, the first electrode 140 includes a plurality of first gate lines 141 and a plurality of second gate lines 142. The plurality of first gate lines 141 are arranged at intervals along a first direction D1, and the plurality of second gate lines 142 are arranged at intervals along a second direction D2. Each second gate line 142 is connected to a plurality of first gate lines 141. The first gate lines 141 may be used to collect current generated in the solar cell, and the second gate lines 142 may be used to collect the current collected by the plurality of second gate lines 141. The second electrode 150 may have an electrode structure similar to that of the first gate line 141 and the second gate line 142 of the first electrode 140, and the description thereof will be omitted.

[0042] As shown in FIG. 2, the separation groove 160 penetrates the first doping layer 120 in the thickness direction D3. As shown in FIG. 1, when viewed from a plan view of the solar cell, the separation groove 160 is a closed rectangle that surrounds all of the first electrodes 140. As shown in FIGS. 1 and 2, the first doping layer 120 is divided into two by the separation groove 160. One part is surrounded by the separation groove 160, and the other part is not surrounded by the separation groove 160 and is located between the edge 170 of the solar cell and the separation groove 160. For convenience of explanation, the part of the first doping layer 120 surrounded by the separation groove 160 will be referred to as the internal doping layer 121, and the part of the first doping layer not surrounded by the separation groove 160 will be referred to as the peripheral doping layer 122. The internal doping layer 121 is in contact with and connected to the first electrode 140, and carriers (e.g., holes or electrons) in the internal doping layer 121 can be transmitted to the outside of the solar cell via the first electrode 140. Due to the division of the separation groove 160, the internal doping layer 121 does not contact the peripheral doping layer 122, so there is no electrical connection between the internal doping layer 121 and the peripheral doping layer 122 (and, naturally, there is no electrical connection between the peripheral doping layer 122 and the first electrode). If there is a connection between the peripheral doping layer 122 and the second doping layer 130, the separation effect of the separation groove 160 prevents a connection between the internal doping layer 121 and the second doping layer 130, thereby avoiding leakage current in the solar cell due to a short circuit.

[0043] The shape of the separation groove 160 is not limited to the rectangular shape shown in Figure 1. The separation groove 160 may have other shapes surrounding the first electrode 140, such as a circle, an ellipse, or another polygon.

[0044] 1 and 2, in one embodiment, the first doping layer 120 has an edge 123 that points outward from the first doping layer 120 in the first direction D1. The edge 123 is a rectangle that surrounds the separation groove 160, and the distance between the separation groove 160 and the edge 123 is smaller than a predetermined distance, and the predetermined distance is any one of values ​​between 10 μm and 2000 μm, for example, 10 μm, 50 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 1000 μm, 1500 μm, or 2000 μm. Specifically, as shown in FIG. 1, edge 123 may be divided into four parts: first edge 123a located on the right side, second edge 123b located below, third edge 123c located on the left side, and fourth edge 123d located above, and separation groove 160 may be divided into four parts: first separation groove 160a located on the right side, second separation groove 160b located below, third separation groove 160c located on the left side, and fourth separation groove 160d located above. 1, first separation groove 160a and first edge 123a are spaced apart by a distance D1 in the second direction D2, second separation groove 160b and second edge 123b are spaced apart by a distance d2 in the first direction D1, and similarly, third separation groove 160c and third edge 123c are spaced apart by a distance d3 in the second direction D2, and fourth separation groove 160d and fourth edge 123d are spaced apart by a distance d4 in the first direction D1 (distances d3 and d4 are not shown). Distances d1, d2, d3, and d4 are all smaller than a predetermined distance, and distances d1, d2, d3, and d4 may be the same or different.

[0045] As shown in FIGS. 1 and 2 , the first doped layer 120 forms a PN junction with the silicon substrate 110. When the solar cell is in operation, carriers in the internal doped layer 121 are output through the first electrode 140 connected to the internal doped layer 121. Due to the isolation effect of the isolation groove 160, carriers in the peripheral doped layer 122 are not output through the first electrode 140. Simply put, when the solar cell is in operation, the internal doped layer 121 is involved in the output of electrical energy, while the peripheral doped layer 122 is not. To increase the electrical energy output of the solar cell, the area of ​​the internal doped layer 121 should be as large as possible. Making the distance between the isolation groove 160 and the edge of the first doped layer 120 smaller than a predetermined distance helps increase the area of ​​the internal doped layer 121.

[0046] In FIG. 1, both the separation groove 160 and the edge 123 are rectangular. The separation groove 160 may be divided into multiple segments, for example, by dividing the second separation groove 160b and the fourth separation groove 160d into multiple segments in the first direction D1 and dividing the first separation groove 160a and the third separation groove 160c into multiple segments in the second direction D2. In this case, the minimum distance between each segment and the edge 123 is smaller than a predetermined distance. In this way, the area of ​​the internal doped layer 121 can be maximized. That is, the distance between the separation groove 160 and the edge 123 is set to maximize the area of ​​the internal doped layer 121, contributing to maximizing the electrical energy generated by the solar cell.

[0047] 2, the cross section of the isolation trench 160 is U-shaped, but in other embodiments, the cross section of the isolation trench 160 may be V-shaped. In the present application, the depth and width of the isolation trench 160 are not limited, but the depth and width must be filled to electrically isolate the inner doped layer 121 from the peripheral doped layer 122. The depth may be any value between 2 μm and 50 μm, and the width may be any value between 5 μm and 60 μm.

[0048] As shown in FIG. 2 , in one embodiment, the solar cell further includes a tunnel layer 180. The tunnel layer 180 is disposed on the second surface 112, and the second doped layer 130 is disposed on the surface of the tunnel layer 180 away from the silicon substrate 110 in the thickness direction D3. The tunnel layer 180 has a tunneling effect. The tunnel layer 180 allows the passage of multi-electrons (e.g., electrons) and prevents the passage of minor-electrons (e.g., holes), which helps reduce carrier recombination. In one embodiment, the tunnel layer 180 is a silicon oxide (SiOx) layer that can form doped polycrystalline silicon as the second doped layer 130 on the surface away from the silicon substrate 110. The silicon oxide layer and the doped polycrystalline silicon layer together can form a passivation structure. Even if minor electrons pass through the silicon oxide layer, they are blocked by the internal electric field due to the doping concentration difference between the doped polycrystalline silicon layer and the silicon substrate, making it difficult for them to reach the interface where the second electrode and the doped polycrystalline silicon layer contact, thereby preventing recombination of major and minor electrons at the interface.

[0049] FIG. 3 is a cross-sectional schematic diagram of the solar cell of FIG. 1 according to another embodiment, taken along line AA. The difference between FIG. 3 and FIG. 2 is that the tunnel layer 180 in FIG. 3 extends to the side surface 113 of the silicon substrate 110 and covers a portion of the side surface 113. That is, the tunnel layer 180 is formed on the second surface 112 and a portion of the side surface 113, and the tunnel layer located on the second surface 112 and the tunnel layer located on the side surface 113 are continuous. For ease of explanation, in FIG. 3, the tunnel layer located on the second surface 112 is referred to as a main body portion 181, and the tunnel layer located on the side surface 113 is referred to as an extension portion 182. To make it easier to understand what the main body portion 181 and the extension portion 182 specifically refer to, the boundary between them is indicated by a dotted line B in FIG. 3.

[0050] 3 and 2 is that the second doping layer 130 extends from the main body portion 181 to the extension portion 182, the second doping layer 130 covers the surface of the main body portion 181 that is away from the silicon substrate 110 in the thickness direction D3, and the extension portion 182 covers the surface that is away from the silicon substrate 110 in the first direction D1. For convenience of explanation, the second doping layer located on the main body portion 181 will be referred to as the main body portion 131, and the second doping layer located on the extension portion 182 will be referred to as the extension portion 132. To make it easier to understand what the main body portion 131 and the extension portion 132 specifically refer to, the boundary between them is indicated by a dotted line B in FIG. 3.

[0051] As shown in FIG. 3 , the extension portion 182 and the extension portion 132 have the same or substantially the same height. The height h1 of both extension portions is greater than or equal to 0.1 μm and less than the thickness of the silicon substrate. Note that the height h1 refers to the dimension in the thickness direction D3. In FIG. 3 , the extension portion 182 and the extension portion 132 are formed on a portion of the side surface 113. In some other embodiments, the extension portion 182 and the extension portion 132 may be formed over the entire side surface 113, with the height h1 being equal to the thickness of the silicon substrate. By extending the tunnel layer 180 and the second doping layer 130 to the side surface 113, the carrier collection area can be increased. Meanwhile, the passivation contact area between the passivation structure and the silicon substrate 110 can be increased, reducing carrier recombination at the edge of the solar cell.

[0052] 1 and 2, the solar cell further includes a first passivation layer 190. The first passivation layer 190 is provided so as to be spaced apart from the surface of the silicon substrate 110 in the thickness direction D3 of the first doping layer 120. In FIG. 2, the first passivation layer 190 covers the bottom and sidewalls of the isolation trench 160. In FIG. 3, the first passivation layer 190 does not cover the bottom and sidewalls of the isolation trench 160. This difference is due to the fact that the process step of forming the first passivation layer 190 in FIG. 2 is after the process step of forming the isolation trench 160, while the process step of forming the first passivation layer 190 in FIG. 3 is before the process step of forming the isolation trench 160.

[0053] The first passivation layer 190 has a passivation effect on the solar cell, reducing carrier recombination and helping to improve cell efficiency. The first passivation layer 190 may be an electric field passivation layer having a field effect passivation effect, a chemical passivation layer having a chemical passivation effect, or a laminated passivation structure having a common composition of an electric field passivation layer and a chemical passivation layer. In some embodiments, the solar cell further includes a first reflection reduction layer disposed on a surface of the first passivation layer 190 that faces away from the silicon substrate 110. The first reflection reduction layer can reduce reflection of incident light by the solar cell and increase the utilization efficiency of the incident light.

[0054] As shown in FIG. 3, the first passivation layer 190 extends to the side surface 113 of the silicon substrate 110 and contacts the extension portion 132 and the extension portion 182, and a portion (or the entire surface) of the extension portion 132 that faces away from the silicon substrate 110 in the first direction D1 is covered by the first passivation layer 190.

[0055] As shown in FIG. 2 , in one embodiment, the solar cell further includes a second passivation layer 210. The second passivation layer 210 is disposed on a surface of the second doping layer 130 that faces away from the silicon substrate 110. The second passivation layer 210 has a passivation effect on the solar cell, reducing carrier recombination and improving cell efficiency. The second passivation layer 210 may be an electric field passivation layer that has a field effect passivation effect, a chemical passivation layer that has a chemical passivation effect, or a laminated passivation structure that includes a field effect passivation layer and a chemical passivation layer. In some embodiments, the solar cell further includes a second reflection reduction layer disposed on a surface of the second passivation layer 210 that faces away from the silicon substrate 110. The second reflection reduction layer can reduce reflection of incident light by the solar cell and improve the utilization efficiency of the incident light.

[0056] Another aspect of the present application further proposes a method for manufacturing a solar cell. Figure 4 is an exemplary flowchart of a method for manufacturing a solar cell according to one embodiment. As shown in Figure 4, the manufacturing method according to this embodiment includes the following steps:

[0057] Step S110: providing a silicon substrate having a first surface and a second surface opposite to each other; Step S120: forming a first doping layer on a first surface of a silicon substrate; Step S130: sequentially forming a tunnel layer and a second doping layer on a second surface of the silicon substrate, where the doping type of the first doping layer is opposite to the doping type of the second doping layer; Step S140: Form a first electrode connected to the first doping layer; Step S150: forming a second electrode connected to the second doping layer; Step S160: A separation trench is formed that penetrates the first doping layer in the thickness direction of the silicon substrate and surrounds the first electrode.

[0058] 5 to 13 are schematic cross-sectional views of intermediate products in a solar cell manufacturing process according to one embodiment. Steps S110 to S160 described above will now be described in detail with reference to FIGS.

[0059] 5, in step S110, a silicon substrate 110 is provided, having a first surface 111 and a second surface 112 facing each other in a thickness direction D3. The silicon substrate 110 may be a doped single crystal silicon wafer or a doped polycrystalline silicon wafer, and the doping type may be N-type doping or P-type doping. Next, a silicon substrate 110 made of N-type doped single crystal silicon will be described as an example.

[0060] 5 and 7, in step S120, a first doped layer 120 is formed on the first surface 111. The first doped layer 120 may be P-type doped single crystalline silicon, N-type doped single crystalline silicon, P-type doped polycrystalline silicon, or N-type doped polycrystalline silicon. Hereinafter, the P-type doped single crystalline silicon will be used for the description. The first doped layer 120 of P-type doped single crystalline silicon forms a PN junction with the silicon substrate 110 of N-type doped single crystalline silicon.

[0061] In one embodiment, a method for forming the first doped layer 120 includes performing a doping process on the silicon substrate 110 and then retaining the doped layer on the first surface 111. For example, referring to FIGS. 5, 6, and 7, a boron diffusion process is performed on the silicon substrate 110 to penetrate boron elements into the silicon substrate 110 to a certain depth, thereby forming the initial first doped layer 120a. The initial first doped layer 120a may also be formed on a surface of the silicon substrate 110 other than the first surface 111, and the first doped layer 120 is formed by removing the initial first doped layer 120a on the surface other than the first surface 111. The initial first doped layer 120a on the surface other than the first surface 111 may be removed by wet etching.

[0062] 5 and 9, in step S130, a tunnel layer 180 and a second doping layer 130 are sequentially formed on the second surface 112. The doping type of the second doping layer 130 is opposite to that of the first doping layer 120, and the following description will be given taking the second doping layer 130 with an N-type doping type as an example. The doping concentration of the second doping layer 130 may be greater than the doping concentration of the silicon substrate 110.

[0063] In some embodiments, the method of forming the tunnel layer 180 and the second doped layer 130 comprises the following steps.

[0064] Step S131: forming an initial tunnel layer on the second surface, the side surface of the silicon substrate, and the surface of at least a part of the first doping layer away from the silicon substrate; Step S132: forming an initial second doping layer on the surface of the initial tunnel layer away from the silicon substrate; Step S133: The initial tunnel layer and the initial second doping layer in the first doping layer are removed to form a tunnel layer and a second doping layer.

[0065] The following is a specific description of steps S131 to S133.

[0066] 7 and 8, the surface 123 of the first doping layer 120 is separated from the silicon substrate 110 in the thickness direction D3. In step S131, an initial tunnel layer 180a is formed on the second surface 112, the side surface 113, and a portion of the surface 123. Due to the process of forming the initial tunnel layer 180a, the initial tunnel layer 180a also covers areas other than the second surface 112. In a more detailed explanation, the process for forming the initial tunnel layer 180a may be selected from atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. When forming the initial tunnel layer 180a using the above process, ideally, the initial tunnel layer 180a should be formed on the target area, the second surface 112, or at least a portion of the second surface 112 and the side surface 113. However, due to the process itself, the initial tunnel layer 180a also deposits on other non-target areas (eg, surface 123).

[0067] 7, the initial tunnel layer 180a is formed on the second surface 112, the side surface 113, and part of the surface 123. In step S132, an initial second doped layer 130a is formed on the initial tunnel layer 180a. Ideally, the initial second doped layer 130a should be formed on the initial tunnel layer located on the second surface 112 and the side surface 113, but not on the initial tunnel layer located on the surface 123.

[0068] 7 and 9, in step S133, the initial tunnel layer and the initial second doping layer on the first doping layer 120 are removed, and portions of the initial tunnel layer and the initial second doping layer located on the side surface 113 are also removed, forming the tunnel layer 180 and the second doping layer 130 shown in FIG. 9. As shown in FIGS. 8, 9, and 3, the upper portions of the initial tunnel layer and the initial second doping layer located on the side surface 113 are removed, and the extension portions 182 and 132 located on the side surface 113 are retained so that the height h1 of the extension portions 182 and 132 is 0.1 μm or more and less than the thickness of the silicon substrate 110. In another embodiment, the initial tunnel layer and the initial second doping layer on the first doping layer 120 are removed, but the initial tunnel layer and the initial second doping layer on the side surface 113 are not removed. In this case, the height h1 of the extension portions 182 and 132 is equal to the thickness of the silicon substrate 110. The method for removing the initial tunnel layer and the initial second doping layer comprises a wet etching process.

[0069] 10 and the flowcharts shown in FIG. 14, in one embodiment, after the step of forming the initial tunnel layer 180a and the initial second doping layer 130a (i.e., step S132), the isolation trench 160 is formed (i.e., step S160) before the step of removing the initial tunnel layer and the initial second doping layer on the first doping layer 120 (i.e., step S133), and step S133 is performed after the isolation trench 160 is formed. FIG. 10 shows the isolation trench 160 formed using the steps of FIG. 14, where the isolation trench 160 penetrates the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120.

[0070] The method for forming the separation groove 160 includes etching the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120 with a laser to form the separation groove 160 penetrating the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120. In the process of forming the separation groove 160 using a laser beam, the laser beam may damage the silicon substrate 110, the initial tunnel layer 180a, the initial second doping layer 130a, and the first doping layer 120 exposed in the separation groove 160. By providing the step of forming the separation groove 160 between step S132 and step S133, laser damage can be removed using step S133. Specifically, step S133 can remove the initial tunnel layer and the initial second doping layer while simultaneously removing laser damage.

[0071] 15, in another embodiment, the isolation groove 160 can be formed (i.e., step S160) after the step of removing the initial tunnel layer and the initial second doping layer on the first doping layer 120 (i.e., step S133). FIG. 11 shows an isolation groove formed using the steps of FIG. 15. Comparing FIG. 11 with FIG. 10, it can be seen that the isolation groove 160 in FIG. 11 does not penetrate the initial tunnel layer and the initial second doping layer because the initial tunnel layer and the initial second doping layer on the first doping layer 120 were removed before step S160.

[0072] As shown in FIGS. 5, 6, and 7, in the step of removing the initial first doped layer 120a to form the first doped layer 120, ideally, only the initial doped layer located on the first surface 111 should remain. However, due to process limitations, the initial first doped layer may remain on other surfaces. For example, the initial first doped layer may remain on the side surface 113 and / or the second surface 112. As shown in FIG. 9, these remaining initial first doped layers may connect the first doped layer 120 and the second doped layer 130, thereby causing a short circuit between the first doped layer 120 and the second doped layer 130, which may reduce the efficiency of the solar cell.

[0073] 1 and 2 , the separation groove 160 penetrates the first doping layer 120 in the thickness direction D3 and is a closed rectangle surrounding all of the first electrodes 140. The first doping layer 120 is divided into two parts by the separation groove 160. One part is surrounded by the separation groove 160 (this part is referred to as the internal doping layer 121), and the other part is not surrounded by the separation groove 160 and is located between the edge 170 of the solar cell and the separation groove 160 (this part is referred to as the peripheral doping layer 122). The internal doping layer 121 is in contact with and connected to the first electrode 140, and carriers (e.g., holes or electrons) in the internal doping layer 121 can be transmitted to the outside of the solar cell via the first electrode 140. Due to the division of the separation groove 160, the internal doping layer 121 does not contact the peripheral doping layer 122, and there is no electrical connection between the internal doping layer 121 and the peripheral doping layer 122. Therefore, even if the remaining initial first doping layer 120a connects the first doping layer 120 and the second doping layer 130, the internal doping layer 121 connected to the first electrode 140 does not contact the second doping layer 130 due to the existence of the separation groove 160. This prevents a short circuit from occurring between the first doping layer 120 and the second doping layer 130, more precisely, prevents a short circuit from occurring between the internal doping layer 121 and the second doping layer 130.

[0074] As shown in FIG. 1, the distance between the isolation groove 160 and the edge 123 of the first doped layer 120 is smaller than a predetermined distance, which may be any value between 10 μm and 2000 μm. As described above, due to the isolation effect of the isolation groove 160, when the solar cell is operating, the internal doped layer 121 is involved in the output of electrical energy, while the peripheral doped layer 122 is not involved in the output of electrical energy. To increase the electrical energy output of the solar cell, the area of ​​the internal doped layer 121 should be as large as possible. Limiting the distance between the isolation groove 160 and the edge of the first doped layer 120 increases the area of ​​the internal doped layer 121, which helps increase the area available for power generation by the solar cell.

[0075] 11 and 12 , the surface 124 of the first doping layer 120 is separated from the silicon substrate 110 in the thickness direction D3. A first passivation layer 190 is formed on the surface 124, and also on the side surface 113 of the silicon substrate 110. The first passivation layer 190 further covers the bottom and side surfaces of the isolation trench 160. By forming the first passivation layer 190 after forming the isolation trench 160, the bottom and side surfaces of the isolation trench 160 can be covered with the first passivation layer 190, which allows the first passivation layer 190 to contact the silicon substrate 110 and first doping layer 120 exposed in the isolation trench 160, thereby achieving good passivation of the isolation trench 160. In another embodiment, the first passivation layer 190 may be formed only on the surface 124.

[0076] In one embodiment, the isolation groove 160 may be formed after the first passivation layer 190 is formed, and Figure 3 shows a solar cell sequentially fabricated using the above steps, with the isolation groove 160 sequentially penetrating the first passivation layer 190 and the first doping layer 120. Because the isolation groove 160 is formed after the first passivation layer 190 is formed, the first passivation layer 190 does not cover the bottom and side surfaces of the isolation groove 160. Details of the first passivation layer 190 are described above and will not be described here.

[0077] 12 and 13 , in one embodiment, the surface 133 of the second doping layer 130 is separated from the silicon substrate 110 in the thickness direction D3, and the second passivation layer 210 is formed on the surface 133. In some embodiments, the isolation groove 160 can be formed after the step of forming the second passivation layer 210. In other embodiments, the first electrode 140 and the second electrode 150 are formed after the second passivation layer 210 is formed, and then the isolation groove 160 is formed.

[0078] Although the basic concepts have been described above, it will be apparent to those skilled in the art that the above disclosure is merely illustrative and does not limit the scope of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed in the present application and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0079] At the same time, the present application uses specific terms to describe embodiments of the present application. For example, "one embodiment," "one embodiment," and / or "some embodiments" refer to features, configurations, or characteristics associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment," "one embodiment," or "one alternative embodiment" mentioned more than once in different places in this specification do not necessarily refer to the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application may be combined as appropriate.

[0080] In some examples, numbers are used to describe the number of components or attributes. It should be understood that the numbers describing such examples are, in some instances, modified using the modifiers "about," "approximately," or "approximately." Unless otherwise specified, "about," "approximately," or "approximately" means that the numerical value can vary by ±20%. Accordingly, in some examples, the numerical parameters used in the specification and claims are approximations, and these approximations may vary depending on the characteristics required for a particular example. In some examples, the numerical parameters should be calculated using a given number of significant digits and ordinary methods of conserving digits. In some examples, the numerical fields and parameters used to determine the breadth of ranges are approximations; however, in certain examples, such numerical values ​​are set as precisely as possible within the ranges possible. [Explanation of symbols]

[0081] Silicon substrate 110 1st surface 111 2nd surface 112 Side 113 First doping layer 120 Inner doping layer 121 Peripheral doping layer 122 Edge 123 surface 124 First Edge 123a 2nd Edge 123b 3rd Edge 123c 4th Edge 123d Initial first doping layer 120a Second doping layer 130 Main body 131 Extension part 132 surface 133 Initial second doping layer 130a 1st electrode 140 1st Gate Line 141 Second gate line 142 2nd electrode 150 Separation groove 160 1st separation groove 160a 2nd separation groove 160b Third separation groove 160c 4th separation groove 160d Solar Cell Edge 170 Tunnel layer 180 Main body 181 Extension 182 Initial tunnel layer 180a First passivation layer 190 Second passivation layer 210

Claims

1. a silicon substrate having opposing first and second surfaces; a first doping layer disposed on the first surface; a second doped layer disposed on the second surface and having a doping type opposite to that of the first doped layer; a first electrode connected to the first doping layer; a second electrode connected to the second doping layer; an isolation trench that penetrates the first doped layer along a thickness direction of the silicon substrate and surrounds the first electrode.

2. 2. The solar cell of claim 1, wherein the distance between the isolation groove and the edge of the first doping layer is smaller than a predetermined distance, and the predetermined distance is between 10 μm and 2000 μm.

3. 2. The solar cell according to claim 1, further comprising a tunnel layer, the tunnel layer being provided on the second surface, and the second doped layer being provided on a surface of the tunnel layer away from the silicon substrate.

4. 4. The solar cell according to claim 3, wherein the tunnel layer extends to a side surface of the silicon substrate and covers at least a portion of the side surface of the silicon substrate, the second doping layer covers a surface of the tunnel layer that faces away from the silicon substrate, and the height of the tunnel layer located on the side surface of the silicon substrate is 0.1 μm or more and is equal to or less than the thickness of the silicon substrate.

5. 2. The solar cell of claim 1, further comprising a first passivation layer disposed on a surface of the first doped layer away from the silicon substrate.

6. The solar cell according to claim 5 , wherein the first passivation layer covers the bottom and sidewalls of the isolation groove.

7. 2. The solar cell of claim 1, further comprising a second passivation layer disposed on a surface of the second doped layer away from the silicon substrate.

8. providing a silicon substrate having opposing first and second surfaces; forming a first doped layer on a first surface of the silicon substrate; sequentially forming a tunnel layer and a second doped layer on the second surface of the silicon substrate, the doping type of the first doped layer being opposite to the doping type of the second doped layer; forming a first electrode connected to the first doped layer; forming a second electrode connected to the second doped layer; forming an isolation trench that penetrates the first doped layer along a thickness direction of the silicon substrate and surrounds the first electrode.

9. The method for forming the tunnel layer and the second doping layer includes: forming an initial tunnel layer on the second surface, a side surface of the silicon substrate, and a surface of at least a portion of the first doping layer that is away from the silicon substrate; forming an initial second doped layer on a surface of the initial tunneling layer away from the silicon substrate; and forming the tunnel layer and the second doped layer by removing the initial tunnel layer and the initial second doped layer in the first doped layer.

10. 10. The manufacturing method according to claim 9, wherein the isolation groove is formed after the step of forming the initial tunnel layer and the initial second doping layer and before the step of removing the initial tunnel layer and the initial second doping layer in the first doping layer.

11. 10. The method of claim 9, further removing a portion of the initial tunnel layer and the initial second doping layer on the side of the silicon substrate so that the height of the tunnel layer and the second doping layer located on the side of the silicon substrate is 0.1 μm or more and less than the thickness of the silicon substrate.

12. 9. The method of claim 8, wherein a distance between the isolation groove and an edge of the first doping layer is less than a predetermined distance, and the predetermined distance is between 10 μm and 2000 μm.

13. 9. The method of claim 8, further comprising forming a first passivation layer on a surface of the first doped layer facing away from the silicon substrate.

14. The manufacturing method according to claim 13 , wherein the first passivation layer is formed after the step of forming the isolation trench.

15. 9. The method of claim 8, further comprising forming a second passivation layer on a surface of the second doped layer facing away from the silicon substrate.

16. 16. The method of claim 15, wherein the isolation trench is formed after the step of forming the second passivation layer.

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