System for simplifying executable instructions for optimized verifiable computations

Abstract

The present invention provides a distributed ledger technology, such as a consensus-based blockchain.SOLUTION: A computer-implemented method for reducing an arithmetic circuit derived from a smart contract is described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a set of program of conditions encoded in a second programming language. The set of conditions is pre-compiled into pre-compiled program code. The pre-compiled program code is transformed into an arithmetic circuit. An arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates generally to blockchain technology, and more specifically to optimizing and obfuscating smart contracts by converting them into arithmetic circuits and minimizing the arithmetic circuits. The present invention further utilizes cryptographic and mathematical techniques to enforce security in connection with electronic transfers made on a blockchain network. The present invention is particularly suited for, but not limited to, use in creating and executing smart contracts. [Background technology]

[0002] As used herein, the term "blockchain" may refer to any of several types of electronic, computer-based distributed ledgers. These include consensus-based blockchain and transaction chain technologies, permissioned and permissionless ledgers, shared ledgers, and variations thereof. While the most widely known application of blockchain technology is the Bitcoin ledger, other blockchain implementations have been proposed and developed. For convenience and illustrative purposes, the example of Bitcoin may be referenced as a beneficial application of the technology described in this disclosure, but Bitcoin is only one of many applications to which the technology described in this disclosure may be applied. However, it should be noted that the present invention is not limited to use with the Bitcoin blockchain, and alternative blockchain implementations and protocols, including non-commercial applications, are also within the scope of the present invention. For example, the technology described in this disclosure may provide advantages over utilizing other blockchain implementations that have similar restrictions as Bitcoin regarding the constraints that may be encoded within transactions, regardless of whether a cryptocurrency exchange occurs.

[0003] A blockchain is a peer-to-peer electronic ledger implemented as a computer-based, decentralized system composed of blocks, which may consist of transactions and other information. In some examples, a "blockchain transaction" refers to an input message that encodes a structured collection of field values ​​containing data and a set of conditions, where satisfying the set of conditions is a prerequisite for the set of fields to be written to the blockchain data structure. For example, in Bitcoin, each transaction is a data structure that encodes the transfer of control of a digital asset between participants in the blockchain system and includes at least one input and at least one output. In some embodiments, a "digital asset" refers to binary data associated with usage rights. Examples of digital assets include Bitcoin, Ether, and Litecoin. In some implementations, transferring control of a digital asset can be performed by reassociating at least a portion of the digital asset from a first entity to a second entity. Each block in a blockchain may include a hash of the previous block, such that blocks are chained together to create a permanent, immutable record of all transactions written to the blockchain since its inception.

[0004] In some examples, a "stack-based scripting language" refers to a programming language that supports various stack-based or stack-oriented execution models and operations. That is, a stack-based scripting language may utilize a stack. A stack allows values ​​to be pushed onto the top of the stack or popped from the top of the stack. Various operations performed on the stack may result in one or more values ​​being pushed onto or popped from the top of the stack. For example, the OP_EQUAL operation pops the top two items from the stack, compares them, and pushes the result (e.g., 1 if equal, 0 if not equal) onto the top of the stack. Other operations performed on the stack, such as OP_PICK, may allow an item to be selected from a position other than the top of the stack. In some scripting languages ​​used in some of the embodiments, there may be at least two stacks: a main stack and an alternate stack. Some operations in the scripting language can move an item from the top of one stack to the top of another stack. For example, OP_TOALTSTACK moves a value from the top of the main stack to the top of the alternate stack. Note that stack-based scripting languages ​​may in some cases not be limited to strictly last-in-first-out (LIFO) operations. For example, a stack-based scripting language may support an operation that copies or moves the nth item in the stack to the top (e.g., OP_PICK and OP_ROLL in Bitcoin, respectively). Scripts written in stack-based scripting languages ​​may be pushed onto a logical stack, which may be implemented using any suitable data structure, such as a vector, list, or stack.

[0005] Transactions must be "validated" before they can be written to the blockchain. Network nodes (mining nodes) perform work to ensure each transaction is valid, and invalid transactions are rejected by the network. Nodes can have different standards for validity than other nodes. Because blockchain validity is consensus-based, a transaction is considered valid if a majority of nodes agree that it is valid. A software client installed on a node performs this validation work for transactions that reference partially unspent transactions (UTXOs) by executing the UTXO locking and unlocking scripts. A transaction is validated by a node if the execution of the locking and unlocking scripts evaluates to TRUE and other validation conditions, if applicable, are met. Validated transactions are propagated to other network nodes, where mining nodes can choose to include the transaction in the blockchain. Thus, for a transaction to be written to the blockchain, i) it must be verified by the first node that receives it, which, if verified, relays the transaction to other nodes in the network; ii) it must be added to a new block constructed by mining nodes; and iii) it must be mined, i.e., added to the public ledger of past transactions. A transaction is considered confirmed once enough blocks have been added to the blockchain to make it effectively irreversible.

[0006] While blockchain technology is most widely known for its use in implementing cryptocurrencies, digital entrepreneurs are beginning to explore the use of both the cryptographic security system on which Bitcoin is based and the data that can be stored on the blockchain to implement new systems. It would be highly advantageous to be able to use blockchain to automate tasks and processes that are not limited to the cryptocurrency realm. Such solutions, while more versatile in their uses, would be able to take advantage of the benefits of blockchain (e.g., persistence, tamper-proof record of events, distributed processing, etc.).

[0007] This disclosure describes technical aspects of one or more blockchain-based computer programs. A blockchain-based computer program may be a machine-readable, executable program recorded in a blockchain transaction. A blockchain-based computer program may include rules that can process inputs to generate results and then cause actions to be performed depending on those results. One area of ​​current research is the use of blockchain-based computer programs for the implementation of "smart contracts." Unlike traditional contracts that are written in natural language, smart contracts may be computer programs designed to automate the execution of the terms of a machine-readable contract or agreement.

[0008] In embodiments, interactions with specific entities can be encoded in specific steps of a smart contract, but the smart contract may otherwise be automatically executed and self-enforcing. It is machine-readable and executable. In some examples, automatic execution refers to the execution of a smart contract that successfully executes to enable the transfer of a UTXO. Note that in such examples, the “entity” that enables the transfer of a UTXO refers to an entity that can create the unlocking script without being required to prove knowledge of any secret. In other words, the unlocking transaction can be validated without verifying that the source of the data (e.g., the entity that created the unlocking transaction) has access to cryptographic secrets (e.g., private asymmetric keys, symmetric keys, etc.). Additionally, in such examples, self-enforcing refers to validating nodes in a blockchain network enforcing the unlocking transaction in accordance with constraints. In some examples, “unlocking” a UTXO (also known as “spending” a UTXO) is used in a technical sense to refer to creating an unlocking transaction that executes as valid, with reference to the UTXO.

[0009] The output of a blockchain transaction includes a locking script and information about the ownership of a digital asset, such as Bitcoin. A locking script, sometimes called an encumbrance, "locks" a digital asset by specifying conditions that must be satisfied in order for a UTXO to be transferred. For example, a locking script may require that specific data be provided in an unlocking script to unlock the associated digital asset. In Bitcoin, a locking script is also known as a "scriptPubKey." A technique for requiring a party to provide data to unlock a digital asset involves embedding a hash of the data within the locking script. However, this presents a problem when the data is unspecified (e.g., unknown and unfixed) at the time the locking script is created.

[0010] The present invention may be described as a verification method / system and / or a control method / system for controlling the verification of blockchain transactions. In some embodiments, a verified blockchain transaction results in the recording of a transaction on the blockchain, which, in some applications, may result in the exchange or transfer of digital assets via the blockchain. Digital assets may be units of resources managed by the blockchain. In some embodiments, digital assets may be used as cryptocurrency, although it is contemplated that in some embodiments, digital assets may additionally or alternatively be usable in other contexts. It should be noted that while the present invention is applicable to the control of digital assets, it is technical in nature and may be used in other contexts utilizing blockchain data structures that do not necessarily involve the transfer of digital assets. Summary of the Invention [Problem to be solved by the invention]

[0011] It would therefore be desirable to provide a method and system that improves blockchain technology in one or more of these aspects. Such an improved solution has now been devised. Thus, in accordance with the present invention, there is provided a method as defined in the accompanying claims. [Means for solving the problem]

[0012] It is therefore desirable to provide a computer-implemented method, the computer-implemented method comprising: converting the set of conditions encoded in the first programming language into a programmatic set of conditions encoded in a second programming language; precompiling a program set of conditions into precompiled program code; transforming the precompiled program code into an arithmetic circuit; reducing the arithmetic circuit to form a reduced arithmetic circuit; Includes:

[0013] The method may include obtaining a set of conditions encoded in a first programming language, which may be performed before the converting step.

[0014] The method may include storing the reduced arithmetic circuit.

[0015] Reducing the arithmetic circuit may include minimizing the arithmetic circuit to generate a reduced arithmetic circuit.

[0016] An arithmetic circuit may be a directed acyclical graph. Alternatively, the directed acyclical graph may include a set of nodes representing logic gates and inputs. Alternatively, the directed acyclical graph may include a set of nodes and edges representing wires between the logic gates and inputs.

[0017] The arithmetic circuit may include a logical sub-module that includes a proper subset of the set of nodes. Alternatively, reducing the arithmetic circuit may include reducing the logical sub-module separately from the remainder of the arithmetic circuit.

[0018] The wires between the logic gates within a logic submodule may be 1 bit wide.

[0019] The arithmetic circuit may further include another logical sub-module including another subset of the set of nodes. In addition, the subset of nodes and the other subset of nodes may be nonintersecting. In addition, reducing the arithmetic circuit may further include reducing the logical sub-module using the first processor core in parallel with reducing the other logical sub-module using the second processor core.

[0020] The computer-implemented method may further include allocating logical sub-modules to a first processor core and other logical sub-modules to a second processor core according to heuristics for optimizing computing resource usage.

[0021] The heuristic may be a longest processing time greedy algorithm.

[0022] Reducing the arithmetic circuit may include determining a set of prime implicants of the arithmetic circuit. Additionally, reducing the arithmetic circuit may include expressing the set of prime implicants as a product of sums including a first product term and a second product term. Additionally, reducing the arithmetic circuit may include simplifying the first product term and the second product term.

[0023] Simplifying the first and second product terms may be performed by applying a Boolean minimisation rule to the first and second product terms.

[0024] The second programming language may be C++.

[0025] The first programming language may be a computer programming language designed for constructing machine-readable financial contracts.

[0026] The computer-implemented method may further include generating a quadratic program including a set of polynomials that describe the reduced arithmetic circuit. Additionally, the computer-implemented method may further include generating a set of parameters for use by nodes in the blockchain network in executing the quadratic program.

[0027] It is also desirable to provide a system that includes a processor and a memory that includes executable instructions that, when executed by the processor, cause the system to perform any of the claimed methods.

[0028] It is also desirable to provide a non-transitory computer-readable storage medium storing executable instructions that, when executed by one or more processors of a computer system, cause the computer system to perform at least any of the claimed methods.

[0029] The present invention can be described as a verification method / system and / or a control method / system for controlling the exchange or transfer of digital assets over a blockchain. In some embodiments, the digital assets are tokens or portions of cryptocurrencies. As described below, the present invention can also be described as a secure method / system for new, improved, and advantageous ways of performing operations over a blockchain network or platform. Alternatively, the present invention can provide improved blockchain programming tools or aids, which can provide improved, efficient, and optimized configurations that facilitate or enable distributed, verifiable computation. [Brief explanation of the drawings]

[0030] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0031] [Figure 1] FIG. 1 illustrates a blockchain environment in which various embodiments may be implemented. [Figure 2] FIG. 1 is a diagram of an example of logical reduction according to one embodiment. [Figure 3] FIG. 1 is a swim diagram illustrating an example of verifiable calculations and involved parties, according to one embodiment. [Figure 4] FIG. 1 illustrates an example workflow from a domain-specific language contract to a second-order arithmetic program, according to one embodiment. [Figure 5] FIG. 2 illustrates an example of an arithmetic circuit including logic sub-modules, according to one embodiment. [Figure 6] FIG. 10 illustrates an example of processing logical sub-modules in parallel, according to one embodiment. [Figure 7] FIG. 10 illustrates an example of prime implicant reduction, according to one embodiment. [Figure 8]1 is a flowchart illustrating an example of transforming a domain-specific language contract into a reduced arithmetic circuit, according to one embodiment. [Figure 9] 1 is a flowchart illustrating an example of arithmetic circuit reduction, according to one embodiment. [Figure 10] FIG. 1 illustrates a computing environment in which various embodiments may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0032] Reference is first made to Figure 1, which illustrates an example blockchain network 100 associated with a blockchain according to one embodiment of the present disclosure. In this embodiment, the example blockchain network 100 includes blockchain nodes implemented as peer-to-peer distributed electronic devices, each of which executes instances of software and / or hardware that perform operations according to a blockchain protocol agreed upon at least in part among operators of the nodes 102. In some examples, a "node" refers to a peer-to-peer electronic device distributed across the blockchain network. One example of a blockchain protocol is the Bitcoin protocol.

[0033] In some embodiments, node 102 may comprise any suitable computing device (e.g., by a server in a data center, by a client computing device (e.g., a desktop computer, laptop computer, tablet computer, smartphone, etc.), by multiple computing devices in a distributed system of a computing resource service provider, or by any suitable electronic client device such as computing device 1000 of FIG. 10). In some embodiments, node 102 has an input for receiving data messages or objects representing proposed transactions, such as transaction 104. The node, in some embodiments, is queriable for information it maintains, such as information about the state of transaction 104.

[0034] As shown in Figure 1, some of the nodes 102 are communicatively coupled to one or more other of the nodes 102. Such communicative coupling may include one or more of wired or wireless communication. In an embodiment, the nodes 102 each maintain at least a portion of a "ledger" of all transactions in the blockchain. In this manner, the ledger is a distributed ledger. Transactions processed by a node that affect the ledger are verifiable by one or more of the other nodes so that the integrity of the ledger is maintained.

[0035] With regard to which nodes 102 can communicate with which other nodes, it is sufficient that each of the nodes in the example blockchain network 100 can communicate with one or more other of the nodes 102 such that messages passed between nodes can propagate throughout the entire example blockchain network 100 (or any significant portion thereof), assuming the messages are messages that the blockchain protocol indicates should be forwarded. One such message may be the publication of a proposed transaction by one of the nodes 102, e.g., node 102A, which would then propagate along a path such as path 106. Another such message may be the publication of a proposed new block for inclusion in the blockchain.

[0036] In one embodiment, at least some of the nodes 102 are mining nodes that perform complex computations, such as solving cryptographic problems. Mining nodes that solve cryptographic problems create new blocks for the blockchain and broadcast the new blocks to other nodes 102. The other nodes 102 verify the mining node's work and, upon verification, accept the block into the blockchain (e.g., by adding the block to the blockchain's distributed ledger). In some examples, a block is a group of transactions, often marked with a timestamp and a "fingerprint" (e.g., a hash) of the previous block. In this manner, each block may become linked to the previous block, thereby creating a "chain" that links the blocks in the blockchain. In embodiments, valid blocks are added to the blockchain by consensus of the nodes 102. Also, in some examples, the blockchain includes a list of validated blocks.

[0037] In one embodiment, at least some of the nodes 102 operate as validating nodes that validate transactions as described in this disclosure. In some examples, a transaction includes proof of ownership of a digital asset (e.g., multiple bitcoins) and data providing conditions for accepting or transferring ownership / control of the digital asset. In some examples, an "unlocking transaction" refers to a blockchain transaction that reassociates (e.g., transfers ownership or control of) at least a portion of the digital asset represented by a UTXO of a previous transaction to an entity associated with a blockchain address. In some examples, a "previous transaction" refers to a blockchain transaction that includes the UTXO referenced by the unlocking transaction. In some embodiments, a transaction includes a "locking script" that blocks the transaction with conditions that must be met before ownership or control can be transferred ("unlocked").

[0038] In some embodiments, a blockchain address is an alphanumeric string associated with an entity to which control of at least a portion of a digital asset is being transferred / reassociated. In some blockchain protocols implemented in some embodiments, there is a one-to-one correspondence between a public key associated with an entity and a blockchain address. In some embodiments, validating a transaction includes verifying one or more conditions specified in a locking script and / or an unlocking script. If a transaction 104 is successfully validated, the validating node adds the transaction 104 to the blockchain and distributes it to nodes 102.

[0039] Figure 2 illustrates an example 200 of one embodiment of the present disclosure. Specifically, Figure 2 illustrates a smart contract 202 that has been converted into an arithmetic circuit 214, which is then shrunk by an arithmetic circuit optimization module to reduce the resources required by a worker node 250 in the blockchain to determine the outcome of the smart contract 202.

[0040] In one embodiment, smart contract 202 is a contract or agreement written in a format that allows a computing device to execute the terms of the contract and / or determine whether the terms of the contract are met. Smart contract 202 may include a set of rules and / or conditions that, when evaluated against a set of input values, allow a computing device to determine an outcome of smart contract 202, which can then cause further actions to be performed depending on the outcome.

[0041] The purpose of this disclosure is to describe a protocol that allows an entity to compose a set of rules and / or a set of conditions, such as those of smart contract 202, using a domain-specific programming language. In some examples, a domain-specific programming language or "domain-specific language" (DSL) refers to a computer programming language designed for use in a particular field of use. Examples of DSLs include Hypertext Markup Language (HTML), Acturus Modeling Language (AML), Digital Asset Modeling Language (DAML), Financial Instruments Markup Language (EpML), and Emacs Lisp.

[0042] In some instances, general-purpose programming languages ​​or "general-purpose languages ​​(GPLs)" are widely applicable, as opposed to DSLs. Examples of general-purpose programming languages ​​include Ada, ALGOL, assembly language, BASIC, Boo, C, C++, C#, Clojure, COBOL, Crystal, D, Dart, Elixir, Erlang, F#, Fortran, Go, Harbour, Haskell, Idris, Java, JavaScript, Julia, Lisp, Lua, Modula-2, NPL, Oberon, Objective-C, Pascal, Perl, PHP, Pike, PL / I, Python, Ring, RPG, Ruby, Rust, Scala, Simula, Swift, and Tcl. C++, which may be referenced in embodiments of the present disclosure, is a general-purpose programming language with imperative, object-oriented, and general programming features, and also provides capabilities for low-level memory manipulation.

[0043] In one embodiment, the arithmetic circuit 214 is a directed acyclic graph (DAG) that represents the smart contract 202. That is, the edges ("wires") of the DAG may represent inputs or values ​​between nodes in the graph, and the nodes may represent arithmetic operations (e.g., sum, product, etc.). Thus, input values ​​to the arithmetic circuit 214 are associated with input values ​​to the smart contract, and in embodiments, the result of the smart contract matches the result of the arithmetic circuit 214. Note that in various embodiments, match does not necessarily require equality. For example, two values ​​may match if they are unequal but mathematically equivalent. As another example, two values ​​may match if they correspond to a common object (e.g., a value) or are complementary in some predetermined way, and / or they satisfy one or more match criteria. In general, any method of determining whether a match exists may be used.

[0044] In one embodiment, the reduced arithmetic circuit 216 is the result of an arithmetic circuit that has been reduced by the arithmetic circuit reduction module 220 according to Boolean minimization rules or other mathematical equivalence rules. For example, in Boolean algebra, the expression u+uv can be simply minimized to u, similarly resulting in the arithmetic circuit: [Table 1] of: [Table 2] can be simply minimized to

[0045] Thus, the arithmetic circuit reduction module 220 can reduce / simplify the arithmetic circuit 214 by evaluating the arithmetic circuit 214 for ways to reduce or minimize the circuit, thereby generating a reduced arithmetic circuit 216, which is output by the arithmetic circuit reduction module 220.

[0046] In one embodiment, arithmetic circuit reduction module 220 is hardware or software that, as a result of its execution, generates reduced arithmetic circuit 216 by performing operations that compare product terms in arithmetic circuit 214 using Boolean minimization rules or other mathematical equality rules to determine where and how arithmetic circuit 214 can be reduced. Further details of the operations performed by arithmetic circuit reduction module 220 can be found in the description of Figures 7-9.

[0047] In one embodiment, worker node 250 is a node in a blockchain network, similar to node 102 in Figure 1 and worker node 350 in Figure 3. That is, worker node 250 may be a computing device configured to process and / or verify blockchain transactions that is communicatively coupled with one or more other nodes in the blockchain network. Worker node 250, in some embodiments, may be designed to determine the output of an arithmetic circuit, such as reduced arithmetic circuit 216, given a set of input values.

[0048] In embodiments, contract execution can be outsourced to untrusted parties, but the correctness of the contract execution can be publicly verified. In embodiments, the protocol uses cryptographic primitives that ensure completeness, soundness, and zero-knowledge. In some examples, "completeness" refers to the ability of a verifier to determine the validity of an output if the prover correctly follows the protocol. In some examples, "soundness" refers to the inability of a prover to deceive a verifier about the authenticity of the output. In some examples, "zero-knowledge" refers to the ability of a verifier to verify an output without being able to derive the inputs used to generate the output.

[0049] In this way, smart contracts can be generated using a DSL designed to make smart contracts easy for humans to write and read, without requiring non-expert programmers to implement the cryptography themselves. In embodiments of the present disclosure, a compiler / interpreter automatically compiles the DSL source code from the user into a cryptographic protocol usable on the blockchain. In this disclosure, embodiments provide a highly optimized solution for the expression of complex contracts in terms of simple arithmetic gates. This expression can be viewed as a solution or tool for the construction of comprehensive pipelines that can provide distributed, verifiable computation.

[0050] 3 is a diagram illustrating an example of a verifiable computation process 300 and the parties involved in an embodiment of the present disclosure. As illustrated in FIG. 3, the verifiable computation process 300 may include a client node 340, a worker node 350, and a verifier node 360, which are involved in performing steps in a verifiable computation protocol in an embodiment of the present disclosure. In an embodiment, one or more of the client node 340, the worker node 350, or the verifier node 360 ​​is a node in a blockchain network, such as node 102 in the example blockchain network 100 of FIG. 1.

[0051] In one embodiment, the setup phase involves writing a contract in a DSL. The interpreter, which may be a client node 340, takes source code as input and

number

[0052] From the circuit C, embodiments of the present disclosure can generate a quadratic program Q that includes a set of polynomials that provides a complete description of the original circuit C. Public parameters may then be generated that are used by the worker node 350 and the verifier node 360 ​​in executing and verifying the quadratic program.

[0053] At 304, worker node 350 executes circuit C or quadratic program Q on input x and claims that the output is y. In some embodiments, worker node 350 (i.e., the prover) is expected to obtain a valid transcript for {C, x, y}; therefore, at 306 of process 300, worker node 350 encodes the transcript. In some examples, a valid transcript for {C, x, y} is to assign values ​​to circuit wires such that the values ​​assigned to the input wires are those of x, the intermediate values ​​correspond to the correct operation of each gate in C, and the value assigned to the output wire is y; if the claimed output is incorrect (i.e., y≠P(x)), then there is no valid transcript for {C, x, y}.

[0054] At 308, the worker node 350 provides the output y to the client node 340. In an embodiment, a public evaluation key EK and a public verification key VK are derived using a secret value s selected by or from the client node 340. In an embodiment, the worker node 350 uses these public keys to evaluate a calculation for a particular input x. In an embodiment, the output y, the values ​​of the internal circuit wires, and EK are used to generate a proof-of-correctness π. The proof π can be stored on the blockchain and can be verified by multiple parties (e.g., the verifier node 360) without requiring the worker node 350 to interact with the multiple parties separately. In this way, the verifier node 360 ​​can verify the transaction, thereby validating the contract, at 310 using the public verification key VK and the proof π.

[0055] Figure 4 illustrates an example workflow 400 from a smart contract encoded in a DSL to a quadratic arithmetic program (QAP), according to an embodiment of the present disclosure. Specifically, Figure 4 illustrates a DSL smart contract 402 being converted by a converter 404 into a GPL contract 406. A GPL precompiler 408 (also known as a preprocessor) incorporates external libraries 410 referenced by the GPL contract 406 and generates a GPL preprocessing contract 412. The GPL preprocessing contract 412 is transformed into an arithmetic circuit 414 that is optimized to generate a reduced arithmetic circuit 416 from which a QAP polynomial 418 is derived.

[0056] In embodiments, DSL smart contract 402 is a contract written in a formal language with precise semantics. In embodiments, DSL smart contract 402 includes a set of conditions, and the outcome of DSL smart contract 402 depends on the fulfillment of the set of conditions. An example of a smart contract is an insurance contract that takes as input the insured's premium and a potential distribution to the insurer by the insurer. If the insured suffers a loss during the term of the smart contract (e.g., fulfillment of the first condition), execution of the smart contract distributes the premium to the insurer and distributes the loss distribution to the insured. On the other hand, if the insured does not suffer a loss during the term of the smart contract, execution of the smart contract distributes the premium to the insurer and returns the potential distribution to the insurer.

[0057] In one embodiment, converter 404 is a software program that takes a set of conditions written in a DSL, such as DSL smart contract 402, and translates the DSL code into GPL source code, such as GPL contract 406, as a result of execution. In an embodiment, GPL contract 406 is a GPL program, such as a C++ program, that includes the contract defined in DSL smart contract 402.

[0058] In one embodiment, GPL precompiler 408 is a computer-executable program that processes GPL contract 406 and required external libraries 410 to generate standalone GPL precompiler contract 412. In an embodiment, GPL precompiler 408 evaluates constant expressions and registers symbols found in GPL contract 406.

[0059] In one embodiment, external library 410 is a collection of pre-written subroutines, functions, classes, containers, values, and / or mutable types that are utilized by GPL contract 406 through calls. For example, by calling external library 410, GPL contract 406 obtains the functionality of that library without having to implement the functionality itself.

[0060] In one embodiment, GPL preprocessing contract 412 includes a set of expressions and operators. Operators can be arithmetic operators (e.g., addition (+), multiplication (*), etc.), comparison operators (e.g., less than (<), equal (=), greater than or equal (≧), etc.), conditional statements (e.g., if-then (?, :)), or logical operators (e.g., AND (&&), OR (||), NOT (!), XOR (XOR), etc.). (outside 1) TIFF2026035866000005.tif6153), etc. In some embodiments, the main function is generated to have a predetermined name and format.

[0061] In one embodiment, the arithmetic circuit 414 is a DAG for a set of variables. In one embodiment, each node of the DAG with an indegree of zero has an input gate (e.g., x i ), and every other node in the DAG is a sum gate (+) or a product gate (×). In embodiments, every gate (node) has an outdegree of 1, and therefore the underlying graph is a directed tree. In embodiments, arithmetic circuit 414 has two measures of complexity: size and depth. In some examples, the "size" of an arithmetic circuit is based on the number of gates in arithmetic circuit 414. In some examples, the "depth" of an arithmetic circuit is based on the length of the longest directed path in the arithmetic circuit.

[0062] After the arithmetic circuit 414 is generated, it may be reduced. In Boolean algebra, any Boolean function can be expressed in minterm normal form. A function f(x1,...,x n), a product term in which each of the variables appears once, either in its natural or complemented form, is sometimes called a minterm. That is, in some instances, a "minterm" is a logical expression of n variables that uses only the complement operator (') and the conjunction operator (). For example, abcd and abc'cd' are two minterms of f(a,b,c,d). In this way, a 2-term expression of n variables is n f will exist.

[0063] In some instances, "implicant" refers to a product that covers a group of minterms of f (i.e., a product term P of a sum of products is an implicant of f whenever P is equal to 1 when f takes the value 1). For example, the following function: f(a,b,c,d)=ab+bc'+d In the above example, ab, bc', abc', abc'd, and d are examples of implicants for f. In some examples, a "prime implicant" refers to an implicant that cannot be covered by a more general (e.g., with fewer literals) implicant. That is, a prime implicant is a product term P that becomes a non-implicant for f if any literal is removed from P. Using the above example, abc'd is not a prime implicant because a literal can be removed to make it prime (for abc'd to be a prime implicant, f(a,b,c,d) must equal 1 if and only if a=1 and b=1 and C=0 and d=1).

[0064] However, as will be appreciated, if a, b, and c' are eliminated (i.e., if d = 1), then f(a,b,c,d) can equal 1. Similarly, if c' and d are eliminated (i.e., if ab = 1), then f(a,b,c,d) can equal 1. Similarly, if a and d are eliminated (i.e., if bc' = 1), then f(a,b,c,d) can equal 1. The process of eliminating literals from a Boolean term is sometimes called "expansion." Expanding one literal doubles the number of input combinations for which the term is true. For example, abc' can be expanded to ab or bc' without changing the cover of f.

[0065] The sum of all prime implicants of a Boolean function is sometimes called the "Blake canonical form." Prime implicants that cover outputs of the function that cannot be covered by combinations of other prime implicants are sometimes called "essential prime implicants." The number of prime implicants of a Boolean function with n input variables is 3 n / n. Extracting the minimum prime implicants is known to belong to the class of nondeterministic polynomial-time complete (NP-complete) problems. The following method shows an example of constructing a chart of prime implicants using the Quine-McCluskey algorithm.

[0066] The Quine-McCluskey method, found in McCluskey's Minimization of Boolean Functions (1956), returns a complete list of prime implicants for a Boolean function. In one embodiment, the returned prime implicants are used to construct a prime implicant table, which can be used as input to one or more algorithms for the extraction of the essential prime implicants of a function. The Boolean function f(x1,...,xn) to be reduced can be expressed as:

number

[0067] The M minterms m used to represent f that give the output 1 i is contained in the index vector v. Each index v i represents the binary encoding of a given input sequence:

number

[0068] Therefore, each minterm of v is expressed as x i It can be expressed as a product of natural or complementary inputs depending on their values. Pairs of minterms can be combined if their representation changes by a single digit changing. Terms that cannot be further combined are prime implicants. The essential prime implicant table is constructed using a list of irreducible prime implicants.

[0069] In one example, n=4, M=6, and v={4, 8, 10, 11, 12, 15}, xxf(x1,...,x n ), the Quine-McCluskey method for extracting prime implicants and generating a prime implicant table appears as follows:

number

[0070] Therefore, f can be expressed as a sum of the following minterms: m4=f(0,1,0,0)=a'bc'd' ·m8=f(1,0,0,0)=ab'c'd' m 10 =f(1,0,1,0)=ab'cd' m 11=f(1,0,1,1)=ab'cd m 12 =f(1,1,0,0)=abc'd' m 15 =f(1,1,1,1)=abcd

[0071] For four inputs, the minterm is [m0,m 15 ], where m0=f(0,0,0,0) and m 15 =(1,1,1,1). The normal sum of the product expression for f is: f(a,b,c,d)=a'bc'd'+ab'c'd'+ab'cd'+ab'cd+abc'd'+abcd

[0072] Minterms are combined when a single digit changes and the corresponding input is set to "-". This results in size-2 implicants: m 4,12 =f(-,1,0,0) [irreducible] m _ (8,9)=f(1,0,0,-) m 8,10 =f(1,0,-,0) m 8,12 =f(1,-,0,0) m 9,11 =f(1,0,-,1) m 10,11 =f(1,0,1,-) m 10,14 =f(1,-,1,0) m 12,14 =f(1,1,-,0) m 11,15 =f(1,-,1,1) m 14,15 =f(1,1,1,-)

[0073] Some of the size-2 implicants may not be irreducible, but may be recombined, resulting in size-4 implicants: m 8,9,10,11 =f(1,0,-,-) [irreducible] m8,10,12,14 =f(1,-,-,0) [irreducible] m 10,11,14,15 =f(1,-,1,-) [irreducible]

[0074] This time, all of the size-4 implicants are irreducible. The list of irreducible implicants corresponds to the prime implicants of the Boolean function. As a final step, a required prime implicant table may be constructed using the list of prime implicants. An example prime implicant table is shown in Table 1 below: [Table 3]

[0075] A "tick" in the table corresponds to a prime implicant that requires a given index vector, i.e., a given input sequence, to be true. If a column of v has only one tick, then the corresponding minterm can be covered by only one prime implicant. Such a prime implicant is essential for f.

[0076] In one embodiment, reduced arithmetic circuit 416 is a reduced or minimized directed acyclic graph (DAG) that can be used to determine the outcome of a set of conditions, such as those specified in DSL smart contract 402, given a set of inputs. In some implementations, reduced arithmetic circuit 416 is a minimized (i.e., reduced to a minimum degree) arithmetic circuit. In some embodiments, the most optimal arithmetic circuit may not necessarily be the smallest arithmetic circuit (e.g., a certain larger arithmetic circuit may be evaluated more quickly than a larger arithmetic circuit, depending on the number and types of arithmetic operations in the circuit); in such embodiments, reduced arithmetic circuit 416 is an arithmetic circuit that is optimized (e.g., for maximum speed, less memory usage, most efficient processor utilization, etc.), but not necessarily minimized.

[0077] In one embodiment, the QAP polynomial 418 is one or more expressions including variables and coefficients expressed in a mathematical formula that provides a complete description of an original arithmetic circuit (e.g., arithmetic circuit 414 of FIG. 4). In an embodiment, the polynomials of the QAP polynomial are defined in terms of their evaluation at the root of the arithmetic circuit, as described, for example, in Quadratic Span Programs and Succint NIZKs without PCPs by Gennaro, R. et al. (2013). In an embodiment, the QAP polynomial is encoded into the locking script of a blockchain transaction as a representation of the smart contract. In an embodiment, the locking script, upon execution, receives a set of parameter values ​​(e.g., as a result of the execution of the locking script), and these parameter values ​​are input as variables into the QAP polynomial to determine the outcome of the smart contract.

[0078] In an embodiment, GPL precompiler 408 generates GPL preprocessing contracts 412. GPL preprocessing contracts 412 may be arithmetic circuits composed of arithmetic gates. Note, however, that complex arithmetic circuits also embed logic submodules due to conditional and flow control statements. In an embodiment, these submodules are also converted into arithmetic circuits, but characterized by 1-bit wide gate connections, as seen in FIG. 5.

[0079] FIG. 5 illustrates an exemplary model of an arithmetic circuit 500 including logic submodules according to an embodiment of the present disclosure. As illustrated in FIG. 5, the arithmetic circuit 500 may include a 1-bit input 502 and a group of inputs 504, which are passed to logic submodules 508A-508B and / or ungrouped arithmetic gates 506A-506D to generate an output 510. The thick lines in FIG. 5 represent groups of 1-bit wide wires (e.g., buses), and the thin lines represent 1-bit-wide wires. Because logic and arithmetic 1-bit wide circuits are dual (e.g., can be expressed in at least two ways, i.e., as a product of sums or a sum of products), logic circuit reductions can be applied to the logic submodules 508A-508B within the arithmetic circuit 500.

[0080] Each of the logical submodules *508A-508B may include a proper (strict) subset of the set of nodes in the arithmetic circuit. In other words, the logical submodules may not encompass the entire arithmetic circuit. Furthermore, in some embodiments, the logical submodules *508A-508B are disjoint, i.e., in such embodiments, the logical submodules *508A-508B will not share any internal gates. Furthermore, in such embodiments, because the logical submodules 508A-508B do not share any internal gates, the reduction procedure can be parallelized (e.g., each of the logical submodules 508A-508B can be reduced in parallel) to reduce the time complexity of the operation.

[0081] In one embodiment, 1-bit input 502 is a wire capable of carrying a value representing either a 1 or a 0, while group of inputs 504 represents multiple 1-bit wires. Complex arithmetic circuits may embed logic sub-modules derived from conditional and flow control statements. In embodiments, these logic sub-modules may also be converted into arithmetic circuits, but may be characterized by 1-bit wide gate connections, such as the illustrated logic sub-modules 508A-508B. In some embodiments, the wires within logic sub-modules 508A-508B are only 1-bit wide.

[0082] Because the logic and arithmetic 1-bit-wide circuits are dual, logic reduction may also be applied to the logic submodules 508A-B. Furthermore, because the logic submodules 508A-B do not share internal gates, the reduction procedure may be parallelized to reduce the time complexity of the arithmetic circuit 500; for example, separate processor cores may be assigned to perform logic reduction on each of the logic submodules 508A-B. In one embodiment, computationally optimized heuristics may be utilized to assign the logic submodules 508A-B to different processing cores for logic reduction. The computationally optimized heuristic may be a heuristic designed to optimize the use of computational resources. One example of a computationally optimized heuristic that may be used is the longest processing time (LPT) greedy method. In such a heuristic, the scheduler attempts to balance the computational load of each transaction if the logic submodules 508A-B are sorted by processing time and assigned to the machine with the earliest finish time so far. Further details can be found below in the description of Figure 7. In contrast, in an embodiment, ungrouped arithmetic gates 506A-506D cannot be reduced in parallel because the ungrouped arithmetic gates 506A-506D are shared by groups of 1-bit wires, such as group of inputs 504. Note that in an embodiment, the reduction is applied to the number of gates, but the number of inputs (e.g., 1-bit input 502 and group of inputs 504) remains the same.

[0083] In one embodiment, output 510 is the result of an operation performed on inputs 502 and 504 according to arithmetic circuit 500. In some implementations, the result is a true or false value. In other embodiments, the result is a set of one or more 1-bit values. In other embodiments, the result may be any other value or values ​​supported by the arithmetic circuit.

[0084] As mentioned above, in an embodiment, the Quine-McCluskey method can return a complete list of prime implicants for a Boolean function f. Furthermore, using the method described in Petrick's A Direct Determination of the Irredundant Forms of a Boolean Function from the Set of Prime Implicants (1956), the number of prime implicants can be reduced to represent f as a composition of essential prime implicants as described below.

[0085] Let f be a Boolean function represented by a prime implicant table (e.g., prime implicant table 1), and let f be an auxiliary Boolean function. * The auxiliary Boolean function f * is true when all of the columns in the prime implicant table are covered. * for each index vector v i The sum of prime implicants σ that contribute to (i.e., contribute to each output of f) i can be expressed as a product of:

number

[0086] For example, the prime implicant σ in Table 1 i The list of terms is as follows: σ0=σ(v0=4)=bc'd' σ1=σ(v1=8)=ab'+ad' σ2=σ(v2=10)=ab'+ad'+ac σ3=σ(v3=11)=ab'+ac σ4=σ(v4=12)=bc'd'+ad' σ5=σ(v5=15)=ac

[0087] Therefore, the dual function f * teeth: f * =(bc'd')(ab'+ad')(ab'+ad'+ac)(ab'+ac)(bc'd'+ad')(ac) This becomes:

[0088] z i f * When expressed in terms of individual minterms, the function is: f * =z0(z1+z2)(z1+z2+z3)(z1+z3)(z0+z2)z3 can be rewritten as:

[0089] Boolean functions can be further simplified using specific Boolean rules, such as the rules shown below: 1.u+uv=u 2.u+u'v=u+v 3.(u+v)(u+w)=u+vw

[0090] It should be noted that other Boolean simplification rules exist, and it is considered within the scope of this disclosure that fewer, more, or different Boolean simplification rules may be used in embodiments of the present disclosure. However, using the above rules, f * The following simplifications can be performed on: (z1+z2)(z1+z3)=z1+z2z3 (Rule 3) z0(z0+z2)=z0 (Rule 1)

[0091] Some further simplifications *By applying to f * can undergo the following reductions: f * =z0z3(z1+z2z3)(z1+z2+z3) f * =z0z3(z1z1+z1z2+z1z3+z1z2z3+z2z2z3+z2z3z3) f * =z0z3(z1+z1z2+z1z3+z1z2z3+z2z3+z2z3) f * =z0z3(z1+z2z3) f * =z0z1z3+z0z2z3

[0092] Therefore, the function * can be covered by z0z1z3 and z0z2z3, both of which contain the minterm minterm (different dual functions f * (If we consider =z0z1z3+z0z2, the term z0z2 will be used to represent f because it is the smallest number of smallest terms.) Therefore, we can write f as f=z0+z1+z3=bc'd'+ab'+ac or, f=z0+z2+z3=bc'd'+ad'+ac can be simplified as follows.

[0093] In this way, the auxiliary Boolean function f * Let σ be the sum of the prime implicants that contribute to each output of f. i can be expressed as a product of:

number

number

[0094] Therefore, z ik is the sum σ iDenote the kth prime implicant that contributes to: σ1=z 11 +z 12 +···+z1|z1| σ2=z 21 +z 22 +···+z2|z2| ... σ M =z M1 +z M2 +···+z M |z M |

[0095] FIG. 6 illustrates an example 600 of a reduced logic submodule in accordance with an embodiment of the present disclosure. Specifically, FIG. 6 illustrates an illustrative example of a system using four processor cores 622 to process eight logic submodules 608A-608H. In example 600, an LPT greedy algorithm is used, and the goal is for all of the processor cores to finish processing as nearly at the same time as possible to optimize the system's processor usage. Initially, the logic submodules 608A-608H may be ordered by complexity (e.g., the number of logic gates in the logic submodules 608A-608H) as an estimate of the processing time of the logic submodules 608A-608H relative to one another. However, it is contemplated that other methods of estimating the processing time of the logic submodules 608A-608H may be used.

[0096] In example 600, the first four logical submodules 608A-608D with the longest estimated processing times may be distributed among processor cores 622 in a round-robin or pseudo-random manner. As can be seen, logical submodule 608D, being processed by core 4, has the smallest estimated processing time of the four and finishes first. As a result, core 4 is assigned the unprocessed logical submodule with the fifth longest estimated processing time, which is logical submodule 608E. Core 3 next finishes processing logical submodule 608C and is assigned to logical submodule 608F, the logical submodule with the sixth longest estimated processing time. Core 2 finishes processing logical submodule 608B and receives logical submodule 608G. Finally, core 1 finishes processing the logical submodule with the longest estimated processing time and receives logical submodule 608H, the logical submodule with the shortest estimated processing time of the eight logical submodules 608A-608H. As can be seen in example 600, all four processor cores 622 finish processing the eight logical sub-modules 608A-608H at approximately the same time, resulting in reduced processor idle time.

[0097] 7 illustrates an example 700 of prime implicants reduction according to one embodiment of the present disclosure. Specifically, FIG. 7 illustrates a set of prime implicants σ1 through σ5 that have been simplified according to the steps described above, for example, by the arithmetic circuit reduction module 220 of FIG. 2. For example, the product term σ i list {σ1,...,σ M In an embodiment, at each step, two members of the list are compared (called the "left" and "right" members), and simplified if possible. In example 700, at time t1, left member 702A (σ1) is paired with right member 704A (σ2), and f * The product term of is simplified using Boolean simplification rules such as those listed above. If the left member 702A and the right member 704A can be simplified, the left member becomes a new term σ 12However, in example 700, it can be seen that the left member 702A and the right member 704A cannot be further simplified.

[0098] Then, at time t2, the left member 702B (σ1) is concatenated with the right member 704B (σ3) and processed according to Boolean simplification rules. In this case, in example 700, the left member 702B and the right member 704B are concatenated with σ 13 Therefore, at time t3, the left member 702C (σ 13 ) is compared to right member 704C (σ4). In example 700, left member 702C and right member 704C cannot be further simplified.

[0099] Similarly, at time t4, left member 702D and right member 704D (σ5) likewise cannot be further simplified. After all right members have been checked, the left member is set to the next member in the list, which in example 700 is σ2. Thus, at time t5, left member 702E (σ2) is concatenated with right member 704E (σ4), and according to Boolean simplification rules, they are σ 24 and becomes the value of the left member. Therefore, at time t6, the left member 702F(σ 24 ) is concatenated with the right member (σ5) and processed to obtain σ 245 This process ends when no further checks are available, as seen at time t7.

[0100] In an embodiment, the number of simplification steps is upper bounded by M(M-1) / 2. In an embodiment, each simplification step of a pair (left, right) consists of performing the following operations: 1. Try to simplify (left, right) according to rule 1, 2. Try to simplify (left, right) according to rule 2, 3. Attempt to simplify (left, right) according to rule 3.

[0101] In embodiments, the u terms in Rules 1, 2, and 3 represent the intersection of a (left, right) pair. The cross-check (intersection) between the addends of the left and right members in embodiments may have time complexity of, for example, o(n 2 ) or o(nlogn).

[0102] In an embodiment, after the simplification process is complete, the remaining product term σ i into a p-term σ * Therefore, the function f * can be covered by the following terms:

number

[0103] Note that the value of p depends on the number of successful simplification operations.

number

number

number

number

number

number

number

[0104] In embodiments, it is contemplated that individual logical sub-modules, such as logical sub-modules 508A-508B in FIG. 5, may be parsed in parallel by different processing cores for faster processing. In such embodiments, a computationally optimized heuristic is performed by the scheduler to assign individual logical sub-modules to different processing cores for the logical reduction phase, called the LPT greedy method. The scheduler attempts to balance the computational load for each logical sub-module being processed, where jobs are sorted by processing time and then assigned to the machine (processing core) with the earliest finish time to date.

[0105] In an embodiment, a logical submodule (S i ) initial gate g i The number of i is presumed to be a good indicator of the expected time required to reduce (e.g., the more gates there are, the longer the expected processing time). Thus, given a machine with N cores and n submodules to reduce, the number of submodules S i are those g i The aggregates G are sorted by value (1≦i≦n) and then the lowest aggregate G at a given time t′ is j (t') metric for the list of core j j} is assigned to:

number

[0106] Alternatively, submodule S i is g iFor example, when i(modulo N)=j, S i can be assigned to core j.

[0107] 8 is a flowchart illustrating an example of a process 800 for transforming a DSL contract into a reduced arithmetic circuit, according to various embodiments. Some or all of process 800 (or any other processes described, or variations and / or combinations of these processes) may be performed under the control of one or more computer systems comprised of executable instructions and / or other data, and may be implemented as executable instructions collectively executing on one or more processors. The executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash medium).

[0108] For example, some or all of process 800 can be performed by one or more computing devices (e.g., by a server in a data center, by a client computing device, by multiple computing devices in a distributed system of a computing resource service provider, or by any suitable electronic client device such as computing device 1000 of FIG. 10). Process 800 includes a series of operations in which a smart contract written in a DSL is converted to GPL, pre-compiled, and transformed into an arithmetic circuit. The arithmetic circuit is reduced according to techniques described in this disclosure and output.

[0109] At 802, a system executing process 800 obtains a smart contract written in a DSL. As mentioned above, a DSL may be a computer programming language designed for use in a particular field. In embodiments, a DSL devised for constructing financial instruments such as smart contracts may be used. Such a DSL may make smart contracts easier to write and read for the average user and may enable non-expert programmers to write smart contracts without implementing any cryptography.

[0110] At 804, the system executing process 800 converts the smart contract to GPL. In this way, the DSL smart contract is converted into a generic form that can be compiled / interpreted into a cryptographic protocol for use on a blockchain. In an embodiment, the GPL is C++ source code, although it is contemplated that other GPL languages ​​may be used.

[0111] At 806, the GPL source code is pre-compiled, which may incorporate library files and / or other dependencies into the pre-compiled source code. The pre-compiling process may also obfuscate variable names, which may have the advantage of hiding the nature of the smart contract from the public after it is committed to the blockchain.

[0112] At 808, the system executing process 800 converts the pre-compiled source code into an arithmetic circuit, for example, by transforming various commands, conditionals, variables, and arithmetic operations into an arithmetic algorithm, which may be represented as a directed cyclic graph, similar to that shown in FIG.

[0113] At 810, the system executing process 800 performs a reduction process on the arithmetic algorithm generated at 808. The reduction process may be similar to process 900 of Figure 9. This reduction process results in a smaller, simplified arithmetic algorithm that can be more efficiently processed by a blockchain node, such as node 102 of Figure 1.

[0114] At 812, the system performing process 800 outputs the reduced arithmetic circuit. In some embodiments, the system provides the reduced circuit to another process that transforms the reduced circuit into a QAP polynomial, such as QAP polynomial 418 in FIG. 4. In other embodiments, the system provides the reduced circuit to a data store or other storage resource for future use. In still other embodiments, the system provides the reduced circuit to one or more entities of the original DSL contract (e.g., entities created or affected by it) via a user interface, for example, through a display in the user interface. It should be noted that one or more of the operations performed at 802-812 may be performed in various orders and combinations, including in parallel.

[0115] 9 is a flowchart illustrating an example process 900 for arithmetic circuit reduction of a pre-compiled GPL smart contract, according to various embodiments. Some or all of process 900 (or any other process described, or variations and / or combinations of these processes) may be performed under the control of one or more computer systems comprised of executable instructions and / or other data, and may be implemented as executable instructions collectively executing on one or more processors. The executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash medium).

[0116] For example, some or all of process 900 may be performed by one or more computing devices (e.g., by a server in a data center, by a client computing device, by multiple computing devices in a distributed system of a computing resource service provider, or by any suitable electronic client device, such as computing device 1000 of FIG. 10). For example, process 900 may be performed as a result of executing arithmetic circuit reduction module 220 of FIG. 2. Process 900 includes a series of operations that determine prime implicants of an arithmetic logic circuit, express them as a product of sums, compare each pair of product terms against logic rules to determine whether the product terms can be simplified, and output the arithmetic circuit in reduced form after all pairs have been simplified. The operations of process 900 extend those of 810 of FIG. 8.

[0117] At 902, a system executing process 900 obtains an arithmetic circuit. The arithmetic circuit may be composed of a set of minterms. In embodiments, the obtained arithmetic circuit may be transformed from pre-compiled GPL source code, such as GPL preprocessing contract 412 of FIG. 4. In embodiments, the obtained arithmetic circuit represents a smart contract. In some implementations, the smart contract was previously written in a DSL format and converted to the GPL format.

[0118] At 904, the system performing the process isolates prime implicants of the arithmetic logic circuit, as in the manner described above in connection with Figure 4. That is, the system may determine a set of implicants from the set of minterms of the arithmetic logic circuit. The system may determine which members of the set of implicants constitute the set of prime implicants of the arithmetic logic circuit (i.e., product terms that become non-implicants if any literals are removed).

[0119] At 906, the set of prime implicants is determined by the sum of prime implicants σ, e.g., as described above with respect to FIG. i At 908, the system performing the process 900 calculates the first pair of product terms σ L and σR を The comparison determines at 910 whether the pair can be simplified according to Boolean logic rules, as described with respect to Figure 7. If not, the system proceeds to 914. Otherwise, if simplification is possible, the system combines and simplifies the pair at 912, and then the system proceeds to 914.

[0120] At 914, the system executing process 900 determines whether all pairs of product terms have been compared and found to be irreducible. If not, the system then returns to 908 to compare the next pair of product terms. Otherwise, at 916, the system outputs the reduced product terms as a sum of products, which is a reduced arithmetic circuit. As described above in connection with 812 of FIG. 8, the system may output the reduced arithmetic circuit to another process for further processing, to a data store, to a data file, or to a user interface. Note that one or more of the operations performed at 902-916 may be performed in various orders and combinations, including in parallel.

[0121] In the context of describing the disclosed embodiments, unless otherwise specified, use of language relating to executable instructions (also called code, applications, agents, etc.) that perform actions that the "instructions" do not normally perform alone (e.g., transmitting data, performing calculations, etc.) means that the instructions are being executed by a machine, thereby causing the machine to perform the specified actions.

[0122] FIG. 10 is an exemplary simplified block diagram of a computing device 1000 that can be used to implement at least one embodiment of the present disclosure. In various embodiments, the computing device 1000 can be used to implement any of the systems illustrated and described above. For example, the computing device 1000 can be configured for use as a data server, a web server, a portable computing device, a personal computer, or any electronic computing device. As illustrated in FIG. 10 , the computing device 1000, in embodiments, can include one or more processors 1002 that communicate with and are operably coupled to multiple peripheral subsystems via a bus subsystem 1004. In some embodiments, these peripheral subsystems include a storage subsystem 1006, including a memory subsystem 1008 and a file / disk storage subsystem 1010, one or more user interface input devices 1012, one or more user interface output devices 1014, and a network interface subsystem 1016. Such a storage subsystem 1006 can be used for temporary or long-term storage of information.

[0123] In some embodiments, bus subsystem 1004 provides a mechanism that allows various components and subsystems of computing device 1000 to communicate with each other as intended. While bus subsystem 1004 is shown schematically as a single bus, alternative embodiments of the bus subsystem utilize multiple buses. In some embodiments, network interface subsystem 1016 provides an interface to other computing devices and networks. Network interface subsystem 1016, in some embodiments, serves as an interface for receiving data from computing device 1000 and transmitting data to other systems. In some implementations, bus subsystem 1004 is utilized to communicate data such as details, search terms, etc.

[0124] In some embodiments, the user interface input devices 1012 include one or more user input devices, such as a keyboard; a pointing device, such as an integrated mouse, trackball, touchpad, or graphics tablet; a scanner; a barcode scanner; a touchscreen integrated into a display; an audio input device, such as a voice recognition system or a microphone; and other types of input devices. In general, the use of the term "input device" is intended to include all possible types of devices and mechanisms for inputting information into the computing device 1000. In some embodiments, the one or more user interface output devices 1014 include a display subsystem, a non-visual display, such as a printer or an audio output device, or the like. In some embodiments, the display subsystem includes a cathode ray tube (CRT), a liquid crystal display (LCD) or light emitting diode (LED) display, a flat panel device, such as a projection device, or other display device. In general, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computing device 1000. One or more user interface output devices 1014 may be used, for example, to present a user interface and to facilitate user interaction with applications that perform the described processes and variations thereof, when such interaction may be appropriate.

[0125] In some embodiments, storage subsystem 1006 provides a computer-readable storage medium for storing basic programming and data constructs that provide the functionality of at least one embodiment of the present disclosure. Applications (programs, code modules, instructions), which, when executed by one or more processors in some embodiments, provide the functionality of one or more embodiments of the present disclosure, are, in embodiments, stored in storage subsystem 1006. These application modules or instructions can be executed by one or more processors 1002. In various embodiments, storage subsystem 1006 also provides a repository for storing data used in accordance with the present disclosure. In some embodiments, storage subsystem 1006 includes memory subsystem 1008 and file / disk storage subsystem 1010.

[0126] In embodiments, memory subsystem 1008 includes multiple memories, such as a main random access memory (RAM) 1018 for storing instructions and data during program execution and / or a read-only memory (ROM) 1020 that may store fixed instructions. In some embodiments, file / disk storage subsystem 1010 provides non-transitory, persistent (non-volatile) storage for program files and data files and may include a hard disk drive, a floppy disk drive with associated removable media, a compact disk read-only memory (CD-ROM) drive, an optical drive, a removable media cartridge, or other similar storage media.

[0127] In some embodiments, computing device 1000 includes at least one local clock 1024. The at least one local clock 1024, in some embodiments, is a counter that represents the number of ticks that have occurred since a particular start date and, in some embodiments, is integrally located within computing device 1000. In various embodiments, at least one local clock 1024 is used to synchronize data transfers within processors and subsystems included therein for computing device 1000 at particular clock pulses and may be used to coordinate synchronization operations between computing device 1000 and other systems in a data center. In another embodiment, the local clock is a timer with a programmable interval.

[0128] Computing device 1000 can be any of a variety of types, including a portable computing device, a tablet computer, a workstation, or any other device described below. Additionally, computing device 1000, in some embodiments, can include another device that can connect to computing device 1000 through one or more ports (e.g., USB, headphone jack, Lightning connector, etc.). In embodiments, such a device includes a port that accepts a fiber optic connector. Thus, in some embodiments, the device converts optical signals into electrical signals that are transmitted through the port that connects the device to computing device 1000 for processing. Due to the ever-changing nature of computers and networks, the description of computing device 1000 shown in FIG. 8 is intended only as a specific example for purposes of describing a preferred embodiment of the device. Many other configurations are possible, having more or fewer components than the system shown in FIG. 10.

[0129] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. However, it will be apparent that various modifications and changes can be made thereto without departing from the scope of the invention as set forth in the appended claims. Likewise, other variations are within the scope of this disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, specific illustrated embodiments thereof have been shown in the drawings and have been described above in detail. It is to be understood, however, that there is no intention to limit the invention to the particular form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the scope of the invention as defined by the appended claims.

[0130] In the context of describing the disclosed embodiments (particularly in the context of the claims that follow), the use of "a" and "an" and "the" and similar referents should be construed to include both the singular and the plural unless otherwise indicated or clearly contradicted. The terms "comprise," "have," "include," and "comprise" should be construed as open-ended terms (i.e., meaning, but not limited to, "comprise") unless otherwise indicated. The term "connected," when referring to an unmodified physical connection, should be construed as being partially or wholly contained within, attached to, or joined together, even if there is some intervening space. The recitation of ranges of values ​​in this disclosure is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise indicated, and each individual value is incorporated herein as if set forth individually. The use of the term "set" (e.g., "set of items") or "subset") should be construed as a non-empty set containing one or more members, unless otherwise noted or contradicted by context. Furthermore, unless otherwise noted or contradicted by context, the term "subset" of a corresponding set does not necessarily indicate a proper subset of the corresponding set, but a subset and a corresponding set may be equivalent.

[0131] Conjunctions, for example, phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C," are understood in the context as commonly used to indicate that an item, term, etc. can be either A or B or C, or any non-empty subset of the set A, B, and C, unless otherwise specifically stated or clearly contradicted by context. For example, in the specific example of a set having three members, the conjunctive phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A,B}, {A,C}, {B,C}, {A,B,C}. Thus, such conjunctives are not generally intended to suggest that a particular embodiment requires that at least one of A, at least one of B, and at least one of C each be present.

[0132] The operations of the processes described may be performed in any suitable order unless otherwise indicated or clearly contradicted by context. The processes described (or variations and / or combinations thereof) may be performed under the control of one or more computer systems comprised of executable instructions, may be implemented by hardware, or a combination thereof, as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively operating on one or more processors. In some embodiments, the code may be stored on a computer-readable storage medium, e.g., in the form of a computer program including a plurality of instructions executable by one or more processors. In some embodiments, the computer-readable storage medium is non-transitory.

[0133] The use of any and all examples or exemplary language (e.g., "such as") provided is intended only to better illuminate embodiments of the invention and does not impose limitations on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

[0134] Embodiments of the present disclosure are described, including the best mode known to the inventors for carrying out the invention. Variations of these embodiments will become apparent to those skilled in the art upon reading the foregoing description. The inventors expect skilled artisans to adopt such variations as necessary, and the inventors intend to practice the embodiments of the present disclosure otherwise than as specifically described. Accordingly, the scope of the present disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Furthermore, any combination of the above-described elements in all possible variations thereof is encompassed within the scope of the present disclosure unless otherwise indicated or clearly contradicted by context.

[0135] All references, including publications, patent applications, and patents, cited in this specification are hereby incorporated by reference to the same extent as if each reference was individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0136] It should be noted that the above-described embodiments are illustrative rather than limiting of the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the present invention as defined by the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of terms such as "comprising" and "comprises" does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. In this specification, "comprising" means "comprises or comprises" and "comprises" or "comprises or comprises." A singular reference to an element does not exclude a plural reference to such elements, and vice versa. The present invention can be implemented by means of hardware comprising several distinct elements and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain means are recited in mutually different dependent claims does not indicate that a combination of these means cannot be used to advantage.

[0137] summary The novel techniques described and suggested in this disclosure extend the functionality of blockchains without interfering with their ability to ensure the integrity of data stored within blockchain data structures. For example, the techniques can improve computational areas, particularly in the area of ​​digital record validation, where conditions for validation are defined within blockchain transactions embedded in the records. The techniques described and suggested in this disclosure can further improve computational areas in the area of ​​smart contract creation and execution by simplifying smart contracts being validated on the blockchain, thereby enabling blockchain nodes to optimize the use of processing resources. Additionally, the techniques described and suggested in this disclosure can improve the efficiency of blockchain nodes by transforming smart contracts into reduced arithmetic circuits from which quadratic arithmetic programs can be derived, thereby enabling blockchain nodes to execute smart contracts more efficiently.

[0138] Furthermore, the techniques described and suggested in this disclosure may be necessarily rooted in computer technology by converting the smart contract from DSL to GPL and then to reduced arithmetic after it has been committed to the blockchain, thereby obfuscating some of the smart contract details, in order to overcome the particular problem that arises of the smart contract details being publicly viewable.

Claims

1. obtaining a set of conditions encoded in a first programming language; converting the set of conditions into a program set of conditions encoded in a second programming language; precompiling the program set of conditions into precompiled program code, wherein precompiling the program set of conditions includes obfuscating variable names; transforming the precompiled program code into an arithmetic circuit; reducing the arithmetic circuit to form a reduced arithmetic circuit; storing the reduced arithmetic circuit; A computer-implemented method comprising:

2. The set of conditions is contained in a smart contract. The computer-implemented method of claim 1 .

3. Reducing the arithmetic circuit includes minimizing the arithmetic circuit to generate the reduced arithmetic circuit.

3. A computer-implemented method according to claim 1 or 2.

4. The arithmetic circuit comprises: a set of nodes representing logic gates and inputs, and a set of edges connecting said nodes representing wires between said logic gates and said inputs; is a directed acyclic graph containing A computer-implemented method according to any one of claims 1 to 3.

5. the arithmetic circuit includes a logic sub-module that includes a proper subset of the set of nodes; reducing the arithmetic circuit includes reducing the logic sub-module separately from the remainder of the arithmetic circuit.

5. The computer-implemented method of claim 4.

6. the wires between the logic gates within the logic submodule are 1 bit wide; 6. The computer-implemented method of claim 5.

7. the arithmetic circuit further includes another logic sub-module including another subset of the set of nodes, the subset of nodes and the other subset of nodes being disjoint; and reducing the arithmetic circuit further comprises reducing the logic sub-module using a first processor core in parallel with reducing the other logic sub-module using a second processor core.

7. A computer-implemented method according to claim 5 or 6.

8. further comprising the step of assigning the logical sub-modules to the first processor core and the other logical sub-modules to the second processor core according to heuristics for optimizing computational resource usage.

8. The computer-implemented method of claim 7.

9. The heuristic is a longest processing time greedy algorithm.

9. The computer-implemented method of claim 8.

10. Reducing the arithmetic circuit includes: determining a set of prime implicants for said arithmetic circuit; expressing the set of prime implicants as a product of sums including a first product term and a second product term; simplifying the first product term and the second product term; 10. A computer-implemented method according to any preceding claim, comprising:

11. simplifying the first product term and the second product term is performed by applying a Boolean minimization rule to the first product term and the second product term.

11. The computer-implemented method of claim 10.

12. the second programming language is a general-purpose programming language; A computer-implemented method according to any preceding claim.

13. the first programming language is a domain-specific programming language; A computer-implemented method according to any preceding claim.

14. generating a quadratic program including a set of polynomials that describe the reduced arithmetic circuit; generating a set of parameters to be used by nodes in a blockchain network in executing the secondary program; 14. The computer-implemented method of claim 1, further comprising:

15. In the system, a processor; a memory containing executable instructions that, when executed by the processor, cause the system to perform the computer-implemented method of any one of claims 1 to 14; A system including:

16. A non-transitory computer-readable storage medium storing executable instructions that, when executed by a processor of a computer system, cause the computer system to perform at least the computer-implemented method of any one of claims 1 to 14.

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