Communication device, communication system, reception processing method, and reception processing program

Abstract

To provide a communication device, a communication system, a reception processing method, and a reception processing program capable of shortening a transmission delay time of data transmission using an LDPC code.SOLUTION: The communication device includes a detection unit that detects an uplink signal including LDPC encoded data transmitted from each of a first external device and a second external device, a first reception processing unit that decodes the LDPC encoded data transmitted from the first external device, and a second reception processing unit that decodes the LDPC encoded data transmitted from the second external device in parallel with the first reception processing unit, and the first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times corresponding to a degree of deterioration of the received uplink signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a communication device, a communication system, a reception processing method, and a reception processing program for performing data transmission using LDPC codes. [Background technology]

[0002] Fiber To The Home (FTTH) is a wiring method that uses optical fiber for the transmission path from base stations to individual homes, and is becoming popular for the purpose of providing high-speed, wideband broadband services to ordinary residential homes. An optical access network called a Passive Optical Network (PON) is often used to provide FTTH broadband services. A PON is configured by connecting one optical line terminal (OLT) and multiple optical network units (ONUs) in a one-to-multiple configuration. A PON allows multiple subscribers to share optical fiber and OLTs, making it possible to provide FTTH services economically.

[0003] Development of 25GS-PON, a next-generation PON with a transmission rate of 25 Gbps, is progressing as a next-generation PON to meet the increasing communication demand in future optical access networks. In PON systems, FEC (Forward Error Correction) is applied to compensate for transmission path errors that occur between the optical transceiver (OTL) and optical network unit (ONU). 25GS-PON employs a low-density parity check (LDPC) code as the FEC code. LDPC codes are a type of error-correcting code used when repeatedly performing error correction processing. LDPC codes have the advantage of having extremely high error correction capabilities. Patent Document 1 discloses that LDPC codes can be used in a communication system including an ONU that encodes data to be transmitted to an optical line terminal (OLT) and an OLT that decodes the encoded data. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2015 / 178315 Summary of the Invention [Problem to be solved by the invention]

[0005] In LDPC decoding, error correction is performed on input data. If all errors cannot be corrected in one error correction, the error correction process is repeated. The number of required iterations varies depending on the degree of degradation of the input data. Conventional PON systems are generally configured to perform pipeline processing, with a fixed processing time for each data process. Considering pipeline processing, the number of iterations in the LDPC decoding circuit must be set to the maximum number of processes corresponding to the maximum expected degree of degradation of the input data, with a constant processing delay, and the data must be output to the subsequent stage. For this reason, even if the degree of degradation of the input data is small and error correction is completed in one error correction process, the data will be output to the subsequent stage with the maximum transmission delay. This results in unnecessary delay being added to data that should be transmitted with little delay.

[0006] The present invention has been made to solve the above-mentioned problems, and aims to provide a communication device, a communication system, a reception processing method, and a reception processing program that can reduce the transmission delay time of data transmission using LDPC codes. [Means for solving the problem]

[0007] A communication device according to the present invention comprises a detection unit that detects an uplink signal containing LDPC-encoded data transmitted from each of a first external device and a second external device, a first reception processing unit that decodes the LDPC-encoded data transmitted from the first external device, and a second reception processing unit that operates in parallel with the first reception processing unit and decodes the LDPC-encoded data transmitted from the second external device, and the first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal.

[0008] A communication system according to the present invention includes a communication device, a first external device, and a second external device, and the first external device and the second external device repeatedly perform error correction processing a number of times corresponding to the expected maximum degree of degradation of LDPC encoded data received from the communication device.

[0009] A reception processing method according to the present invention comprises a detection step of detecting an uplink signal containing LDPC-encoded data transmitted from each of a first external device and a second external device; a first decoding step of decoding the LDPC-encoded data transmitted from the first external device in a first reception processing unit; and a second decoding step, which is performed in parallel with the first decoding step, of decoding the LDPC-encoded data transmitted from the second external device in a second reception processing unit, wherein the first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal.

[0010] A reception processing program according to the present invention causes a processor to execute a detection step of detecting an uplink signal containing LDPC-encoded data transmitted from each of a first external device and a second external device, a first decoding step of decoding the LDPC-encoded data transmitted from the first external device in a first reception processing unit, and a second decoding step, which is performed in parallel with the first decoding step and in parallel with the first decoding step, of decoding the LDPC-encoded data transmitted from the second external device in a second reception processing unit, and the first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal. [Effects of the Invention]

[0011] According to the present invention, the first reception processing unit decodes data transmitted from a first external device, and the second reception processing unit decodes data transmitted from a second external device, in parallel. Furthermore, the first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal. Therefore, the first reception processing unit and the second reception processing unit do not need to perform unnecessary repeated processing on the transmitted data. Therefore, the transmission delay time of data transmission using LDPC codes can be reduced. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic configuration diagram showing a communication system according to a first embodiment. [Figure 2] FIG. 2 is a functional block diagram showing an OLT according to the first embodiment. [Figure 3] FIG. 2 is a functional block diagram showing a reception processing unit according to the first embodiment. [Figure 4] 1 is a functional block diagram showing an ONU according to a first embodiment. [Figure 5] 2 is a hardware configuration diagram showing a control unit of an OLT according to the first embodiment. FIG. [Figure 6] 4 is a flowchart showing a reception processing method according to the first embodiment. [Figure 7] 3 is a diagram showing a state in which a burst signal is transmitted in an ONU according to the first embodiment. FIG. [Figure 8] FIG. 4 is a diagram for explaining a transmission delay time caused by a reception processing unit according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and various modifications are possible without departing from the spirit of the present invention. Furthermore, the present invention includes all possible combinations of the configurations shown in the following embodiments. In addition, in each drawing, components with the same reference numerals are the same or equivalent, and this is common throughout the entire specification.

[0014] Embodiment 1 FIG. 1 is a schematic diagram showing a communication system 1 according to a first embodiment. As shown in FIG. 1, the communication system 1 is a PON system configured by connecting an OLT 2 (corresponding to the "communication device" of the present invention) with a first ONU 3a, a second ONU 3b, and a third ONU 3c via an optical fiber 4. The optical fiber 4 is branched by an optical splitter 5 corresponding to the first ONU 3a, the second ONU 3b, and the third ONU 3c. In the following, when there is no need to distinguish between the three ONUs, the first ONU 3a, the second ONU 3b, and the third ONU 3c, they will be referred to as ONUs 3 (corresponding to the "first external device" or the "second external device" of the present invention). Furthermore, FIG. 1 shows only three ONUs 3 out of a plurality of ONUs 3 included in the communication system 1, but the number of ONUs 3 included in the communication system 1 is not particularly limited.

[0015] The communication system 1 is, for example, a 25GS-PON, and employs an LDPC code as the FEC code. Time Division Multiple Access (TDMA) technology is used for communication (upstream communication) from the ONU 3 to the OLT 2, to avoid collision of signals from multiple ONUs 3. A PON that uses this TDMA technology is also called a TDM-PON.

[0016] The OLT 2 is, for example, a central office terminal device managed by a telecommunications carrier. The OLT 2 combines optical signals to be transmitted to the ONUs 3 and sends them to the optical fiber 4. The OLT 2 also relays signals received from the optical fiber 4 to lines and devices on the network NW side.

[0017] The ONU3 is a subscriber-side terminating device installed in, for example, a private home. The ONU3 is connected to a router or a user terminal (not shown) such as a PC (Personal Computer), a smartphone, or a tablet. The user terminal can access a network NW such as the Internet via the OLT2 and the ONU3.

[0018] (OLT2) Fig. 2 is a functional block diagram showing an OLT 2 according to the first embodiment. As shown in Fig. 2, the OLT 2 has a control unit 21, an SNI (Service Node Interface) 22, and a PON interface 23. The control unit 21 processes data transmitted and received between the ONU 3. The SNI 22 is an interface for communication between the network NW and the OLT 2. The PON interface 23 is an interface for communication with the ONU 3 via an optical fiber 4.

[0019] The control unit 21 includes a data input unit 61, a GEM frame transmitter 62, an FS frame transmitter 63, an LDPC coding unit 64, a downstream signal output unit 65, an OLT optical transceiver 66, an upstream signal detector 67 (corresponding to the "detector" of the present invention), a first reception processor 68a, a second reception processor 68b, a third reception processor 68c, a data multiplexer 69, and a data output unit 70. Note that, hereinafter, when there is no need to distinguish between the three units, the first reception processor 68a, the second reception processor 68b, and the third reception processor 68c, they will be referred to as the reception processor 68. The OLT 2 of the first embodiment is characterized by the data reception processing method performed by the upstream signal detector 67, the reception processor 68, and the data multiplexer 69.

[0020] The data input unit 61 receives data (for example, an Ethernet frame) input from the SNI 22 and outputs it to the GEM frame transmission unit 62.

[0021] The GEM frame transmitting unit 62 encapsulates data (for example, an Ethernet frame) input from the data input unit 61 into a packet called a GEM (G-PON Encapsulation Method) frame. The GEM frame transmitting unit 62 outputs the GEM frame to the FS frame transmitting unit 63.

[0022] The FS frame transmitting unit 63 forms a frame called an FS (Framing Sublayer) frame by combining the multiple GEM frames input from the GEM frame transmitting unit 62. The FS frame transmitting unit 63 outputs the FS frame to the LDPC coding unit 64.

[0023] The LDPC coding unit 64 performs an LDPC coding process to encode the FS frame input from the FS frame transmitting unit 63 with an LDPC code. The LDPC coding unit 64 outputs the LDPC-encoded LDPC-encoded data to the downstream signal output unit 65.

[0024] The downstream signal output unit 65 constructs a PHY (Physical Layer) frame with the LDPC-encoded data input from the LDPC encoding unit 64 as a payload, and scrambles the PHY frame. The downstream signal output unit 65 outputs the scrambled data to the OLT optical transceiver 66.

[0025] The OLT optical transceiver 66 converts the electrical signal input from the downstream signal output unit 65 into an optical signal and outputs it to the PON interface 23, thereby transmitting it to the ONU 3. The OLT optical transceiver 66 also converts the optical signal input from the PON interface 23 into an electrical signal and outputs it to the upstream signal detection unit 67.

[0026] The upstream signal detector 67 detects, for each ONU 3, an upstream burst signal (corresponding to the "upstream signal" of the present invention) indicating a PHY frame configured in the ONU 3 from the signal input from the OLT optical transceiver 66. The upstream signal detector 67 descrambles the PHY frame for each ONU 3. Here, the upstream signal detector 67 is provided with three ports (not shown). Each port is connected to one of the first reception processing unit 68a, the second reception processing unit 68b, and the third reception processing unit 68c. The upstream signal detector 67 outputs the payload (LDPC encoded data) of the burst signal corresponding to each ONU 3 to one of the ports.

[0027] The reception processing unit 68 performs LDPC decoding processing, GEM extraction processing, and decapsulation processing on the LDPC-encoded data input from the upstream signal detection unit 67. The first reception processing unit 68a, the second reception processing unit 68b, and the third reception processing unit 68c perform processing in response to burst signals transmitted from the first ONU 3a, the second ONU 3b, and the third ONU 3c, respectively. The reception processing units 68 perform processing independently of and in parallel with the other reception processing units 68. Although FIG. 2 shows only three reception processing units 68 out of the multiple reception processing units 68 possessed by the control unit 21, the number of reception processing units 68 provided is the same as the number of ONUs 3 that communicate with the OLT 2. In other words, a reception processing unit 68 is provided corresponding to each ONU 3.

[0028] 3 is a functional block diagram showing the reception processing unit 68 according to Embodiment 1. As shown in FIG. 3, the reception processing unit 68 has an LDPC decoding unit 71, an FS frame receiving unit 72, and a GEM frame receiving unit 73.

[0029] The LDPC decoding unit 71 performs LDPC decoding processing. Specifically, the LDPC decoding unit 71 repeatedly performs error correction processing on the payload input from the upstream signal detection unit 67 (hereinafter, the error correction processing may be referred to as iterative processing). When all errors are eliminated during the iterative processing, the LDPC decoding unit 71 considers the LDPC-encoded data to be decoded, and outputs the decoded LDPC-decoded data to the FS frame receiving unit 72. Furthermore, if the iterative processing has been performed the maximum number of times without eliminating errors, the LDPC decoding unit 71 either outputs the input data as is to the FS frame receiving unit 72, or discards the data.

[0030] The FS frame receiver 72 detects FS frames from the LDPC decoded data input from the LDPC decoder 71. The FS frame receiver 72 performs GEM extraction processing to extract GEM frames from the detected FS frames. The FS frame receiver 72 outputs the extracted GEM frames to a GEM frame receiver 73.

[0031] The GEM frame receiving unit 73 performs decapsulation processing on the GEM frame input from the FS frame receiving unit 72. The GEM frame receiving unit 73 outputs the decapsulated data (for example, an Ethernet frame) to the data multiplexing unit 69.

[0032] The data multiplexing unit 69 multiplexes the data (for example, Ethernet frames) output from the GEM frame receiving units 73 of the multiple reception processing units 68, and outputs the multiplexed data to the data output unit .

[0033] The data output unit 70 outputs the input data (for example, an Ethernet frame) to the SNI 22.

[0034] (ONU3) Fig. 4 is a functional block diagram showing an ONU 3 according to the first embodiment. As shown in Fig. 4, the ONU 3 has a control unit 31, a UNI (User Network Interface) 32, and a PON interface 33. The control unit 31 processes data transmitted and received between the ONU 3 and the OLT 2. The UNI 32 is an interface for communication between the ONU 3 and a router or a user terminal, etc. The PON interface 33 is an interface for communication with the OLT 2 via an optical fiber 4.

[0035] The ONU 3 has a data input unit 81, a GEM frame transmitting unit 82, an FS frame transmitting unit 83, an LDPC coding unit 84, an upstream signal output unit 85, an ONU optical transceiver 86, a downstream signal detecting unit 87, an LDPC decoding unit 88, an FS frame receiving unit 89, a GEM frame receiving unit 90, and a data output unit 91.

[0036] The data input unit 81 receives data (for example, an Ethernet frame) input from the UNI 32 and outputs it to the GEM frame transmission unit 82.

[0037] The GEM frame transmitting unit 82 encapsulates data (for example, an Ethernet frame) input from the data input unit 81 into a packet called a GEM frame. The GEM frame transmitting unit 82 outputs the GEM frame to the FS frame transmitting unit 83.

[0038] The FS frame transmitting unit 83 forms a frame called an FS frame by combining a plurality of GEM frames input from the GEM frame transmitting unit 82. The FS frame transmitting unit 83 outputs the FS frame to the LDPC coding unit 84.

[0039] The LDPC coding unit 84 performs LDPC coding processing on the FS frame input from the FS frame transmitting unit 83. The LDPC coding unit 84 outputs the LDPC-coded LDPC-coded data to the upstream signal output unit 85.

[0040] The upstream signal output unit 85 constructs a PHY frame with the input LDPC encoded data as a payload and scrambles the PHY frame. The scrambling is performed upon receiving an instruction from the OLT 2. The upstream signal output unit 85 outputs the scrambled data to the ONU optical transceiver 86.

[0041] The ONU optical transceiver 86 converts the electrical signal input from the upstream signal output unit 85 into an optical signal, and outputs it to the PON interface 33, thereby transmitting it to the OLT 2. The ONU optical transceiver 86 also converts the optical signal input from the PON interface 33 into an electrical signal, and outputs it to the downstream signal detection unit 87.

[0042] The downstream signal detector 87 detects downstream PHY frames from the signal input from the ONU optical transceiver 86. The downstream signal detector 87 performs descrambling processing on the PHY frames. Then, the downstream signal detector 87 outputs the payload (LDPC-encoded data) to the LDPC decoder 88.

[0043] The LDPC decoder 88 repeatedly performs error correction processing on the payload input from the downstream signal detector 87 a number of times corresponding to the maximum expected degree of degradation of the downstream input data. The number of times corresponding to the degree of degradation is the number of times error correction processing can be repeated to complete the error correction for that degree of degradation. After completing the iterations, the LDPC decoder 88 outputs the decoded LDPC-decoded data to the FS frame receiver 89. Furthermore, if errors remain after completing the iterations, the LDPC decoder 88 outputs the input data to the FS frame receiver 89 as is or discards it. The LDPC decoder 88 of each ONU 3 individually sets the number of iterations to perform for each ONU 3. In other words, if the maximum expected degree of degradation of the downstream signal received from the OLT 2 differs for each LDPC decoder 88 of each ONU 3, the LDPC decoder 88 of each ONU 3 performs error correction processing a different number of times.

[0044] The FS frame receiver 89 detects FS frames from the LDPC decoded data input from the LDPC decoder 88. The FS frame receiver 89 performs GEM extraction processing to extract GEM frames from the detected FS frames. The FS frame receiver 89 outputs the extracted GEM frames to a GEM frame receiver 90.

[0045] The GEM frame receiving unit 90 performs decapsulation processing on the GEM frame input from the FS frame receiving unit 89. The GEM frame receiving unit 90 outputs the decapsulated data (for example, an Ethernet frame) to the data output unit 91.

[0046] The data output unit 91 outputs the input data (for example, an Ethernet frame) to the UNI.

[0047] Next, the hardware configuration of the control unit 21 of the OLT 2 will be described. The hardware configuration of the control unit 21 of the ONU 3 is the same as that of the OLT 2, so the description will be omitted. Fig. 5 is a hardware configuration diagram showing the control unit 21 of the OLT 2 according to the first embodiment. As shown in Fig. 5, the control unit 21 of the OLT 2 includes a processor 101, a main storage device 102, and an auxiliary storage device 103. The processor 101, the main storage device 102, and the auxiliary storage device 103 are connected to each other by, for example, a bus 104.

[0048] The processor 101 controls the overall operation of the control unit 21 of the OLT 2. The processor 101 is, for example, a CPU that executes a program stored in the main memory device 102. The processor 101 reads out a program stored in the auxiliary memory device 103 and loads it into the main memory device 102. The processor 101 executes the loaded program to realize each function of the OLT 2.

[0049] The main memory device 102 temporarily stores the program read by the processor 101 from the auxiliary memory device 103, thereby providing a working area for the processor 101. The main memory device 102 is a volatile semiconductor memory such as a RAM. However, the main memory device 102 may also be a non-volatile semiconductor memory such as a ROM, flash memory, EPROM, or EEPROM.

[0050] The auxiliary storage device 103 stores various data related to the operation of the OLT 2. The auxiliary storage device 103 stores programs for implementing the various functions of the OLT 2. In particular, the auxiliary storage device 103 stores a reception processing program for causing the upstream signal detection unit 67, reception processing unit 68, and data multiplexing unit 69 to execute a data reception processing method. The auxiliary storage device 103 is, for example, a magnetic disk, an optical disk, or a flash memory.

[0051] The processor 101 may be a dedicated logic circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array), or may include such a circuit.

[0052] Next, a reception processing method in the OLT 2 will be described with reference to Fig. 6. Fig. 6 is a flowchart showing the reception processing method according to the first embodiment. First, as shown in Fig. 6, the upstream signal detector 67 detects, for each ONU 3, a burst signal including LDPC encoded data from the signal transmitted from the ONU 3 via the PON interface 23 and the OLT optical transceiver 66 (step S1).

[0053] Here, the degree of degradation of the burst signal received by the upstream signal detector 67 will be explained further with reference to FIG. 7. FIG. 7 is a diagram showing how burst signals are transmitted in the ONU 3 according to the first embodiment. FIG. 7 illustrates an example in which a first ONU 3a, a second ONU 3b, and a third ONU 3c are connected to the OLT 2. It is also assumed that the second ONU 3b is located closest to the OLT 2, the first ONU 3a is located farthest from the OLT 2, and the third ONU 3c is located midway between the first ONU 3a and the second ONU 3b. The burst signal received by the upstream signal detector 67 degrades more the further the ONU 3 that transmitted the burst signal is from the OLT 2. Therefore, based on the distance from the OLT 2, the degree of degradation of the burst signal P#1 received from the first ONU 3a is considered to be relatively large, and the degree of degradation of the burst signal P#2 received from the second ONU 3b is considered to be relatively small. Furthermore, the degree of degradation of the burst signal P#3 received from the third ONU3c can be considered to be intermediate between the degree of degradation of the burst signal P#1 received from the first ONU3a and the degree of degradation of the burst signal P#2 received from the second ONU3b.

[0054] The burst signal from ONU 3 is transmitted from ONU 3 upon receiving an instruction from OLT 2. In the example of Fig. 7, based on the instruction from OLT 2, burst signals are output from each ONU 3 so that, as viewed from the receiving end of OLT 2, the burst signal P#1 from the first ONU 3a, the burst signal P#2 from the second ONU 3b, and the burst signal P#3 from the third ONU 3c are output in this order.

[0055] Next, the upstream signal detector 67 outputs the payload (LDPC-encoded data) of the burst signal to the port of the reception processor 68 corresponding to each ONU 3 (step S2). At this time, the transmission delay time of the upstream signal detector 67 is the same for each port. The transmission delay time here refers to the time from when an input signal is processed until it is output to a subsequent stage. In other words, in the upstream signal detector 67, the time from when data is input until it is output is the same for each port. The LDPC decoder 71 of the first reception processor 68a performs LDPC decoding processing on the burst signal P#1 transmitted from the first ONU 3a (step S3). Then, the FS frame receiver 72 and GEM frame receiver 73 of the first reception processor 68a perform GEM extraction processing and decapsulation processing on the decoded LDPC-decoded data, and output the processing results to the data multiplexer 69 (step S4).

[0056] Similarly, the LDPC decoder 71 of the second reception processor 68b performs LDPC decoding processing on the burst signal P#2 transmitted from the second ONU 3b (step S5).Then, the FS frame receiver 72 and GEM frame receiver 73 of the second reception processor 68b perform GEM extraction processing and decapsulation processing on the decoded LDPC decoded data, and output the processing results to the data multiplexer 69 (step S6).

[0057] Similarly, the LDPC decoder 71 of the third reception processor 68c performs LDPC decoding processing on the burst signal P#3 transmitted from the third ONU 3c (step S7).Then, the FS frame receiver 72 and GEM frame receiver 73 of the third reception processor 68c perform GEM extraction processing and decapsulation processing on the decoded LDPC decoded data, and output the processing results to the data multiplexer 69 (step S8).

[0058] Here, the setting of the number of iterations of the error correction process in the LDPC decoding process in each reception processing unit 68 will be described. The number of iterations of the error correction process is set, for example, as follows. First, each reception processing unit 68 of the OLT 2 determines the degree of degradation of the signal input from each ONU 3 when each ONU 3 connects (links up) to the OLT 2, that is, during the PON link-up sequence. Next, the OLT 2 determines the number of iterations according to the determined degree of degradation. The number of iterations according to the degree of degradation is the number of times that error correction can be completed by repeating the error correction process at that degree of degradation. The OLT 2 stores the determined number of iterations in the auxiliary storage device 103, and after link-up, performs the error correction process for the stored number of iterations.

[0059] FIG. 8 is a diagram illustrating a transmission delay time by the reception processing unit 68 according to the first embodiment. Burst signals P#1 to P#3 surrounded by a solid line in FIG. 8 indicate burst signals that are actually transmitted. On the other hand, burst signals P#1 to P#3 surrounded by a dashed line indicate burst signals that would be generated if the transmission delay time in the reception processing unit 68 were zero. As shown in FIG. 8, each reception processing unit 68 requires a different length of transmission delay time depending on the degree of degradation of the burst signal. Specifically, the greater the degree of degradation of the burst signal, the longer the transmission delay time required by the LDPC decoding unit 71 of the reception processing unit 68 before outputting LDPC-decoded data. This is because the greater the degree of signal degradation, the more times error correction is repeated.

[0060] It is expected that a greater number of error correction iterations will be required for burst signal P#3, which corresponds to the third ONU 3c and has a relatively moderate degree of degradation, compared to burst signal P#2, which corresponds to the second ONU 3b and has a relatively low degree of degradation. In the example of FIG. 8, the number of iterations for the second ONU 3b is set to 3, and the number of iterations for the third ONU 3c is set to 6. For this reason, if the transmission delay time of the second reception processing unit 68b, which receives burst signal P#2 and has a relatively low degree of degradation, is T, the transmission delay time of the third reception processing unit 68c, which receives burst signal P#3 and has a relatively low degree of degradation, is twice the transmission delay time (2T) of the second reception processing unit 68b.

[0061] Similarly, a burst signal P#1 corresponding to the first ONU 3a and having a relatively high degree of degradation is expected to require more repeated error corrections than a burst signal P#2 corresponding to the second ONU 3b and having a relatively low degree of degradation. In particular, a burst signal P#1 having a relatively high degree of degradation is expected to require more repeated error corrections than a burst signal P#3 having a relatively medium degree of degradation. In the example of FIG. 8, the number of repeated processes corresponding to the first ONU 3a is set to 9. Therefore, the transmission delay time of the first reception processing unit 68a, which receives the burst signal P#1 and has a relatively high degree of degradation, is three times longer (3T) than the transmission delay time of the second reception processing unit 68b.

[0062] Here, consider a comparative example in which multiple reception processors 68 corresponding to each ONU 3 are not provided, and a single reception processor 68 processes burst signals from each ONU 3. In this case, the number of error correction repetition processes M is determined according to the maximum degree of degradation of input burst signals expected in the communication system 1, and error correction processes are always repeated M times for burst signals received from all ONUs 3. If M is set to 12, the transmission delay time for all ONUs 3 is 4T. The number of repetition processes M in this case is the maximum number of processes according to the maximum degree of degradation expected, regardless of the degree of degradation of signals sent from ONUs 3 connected to the OLT 2.

[0063] Therefore, in the first embodiment, compared to the comparative example described above, the transmission delay time of the burst signal P#1 received from the first ONU 3a can be reduced by T. Also, the transmission delay time of the burst signal P#2 received from the second ONU 3b can be reduced by 3T. Also, the transmission delay time of the burst signal P#3 received from the third ONU 3c can be reduced by 2T. However, the number of iterations of the error correction process and the transmission delay times described above are merely examples.

[0064] As a result, the data is input to the data multiplexing unit 69 in the order of data from the second ONU 3b, data from the first ONU 3a, and data from the third ONU 3c.

[0065] Then, the data multiplexing unit 69 multiplexes the data output from each reception processing unit 68 (step S9). The multiplexed data is output to the SNI 22 by the data output unit 70. The output order of the data at this time is the same as the input order to the data multiplexing unit 69, that is, data from the second ONU 3b, data from the first ONU 3a, and data from the third ONU 3c.

[0066] As described above, according to the first embodiment, the first receiving processor 68a decodes data transmitted from the first ONU 3a, the second receiving processor 68b decodes data transmitted from the second ONU 3b, and the third receiving processor 68c decodes data transmitted from the third ONU 3c in parallel. Furthermore, the first receiving processor 68a, the second receiving processor 68b, and the third receiving processor 68c repeatedly perform error correction processing a number of times according to the degree of degradation of the received upstream signal. Therefore, the first receiving processor 68a, the second receiving processor 68b, and the third receiving processor 68c do not need to perform unnecessary repeated processing on the data transmitted from each ONU 3. This reduces the transmission delay time of data transmission using LDPC codes.

[0067] Furthermore, the first ONU 3a, the second ONU 3b, and the third ONU 3c each repeatedly perform error correction processing a number of times according to the expected maximum degree of degradation of the LDPC-coded data they receive from the OLT 2. In other words, the number of times to perform the repeat processing is set individually for each ONU 3 according to the degree of degradation of the downstream signal between the OLT 2 and each ONU 3. Therefore, even in data transmission using LDPC codes from the OLT 2 to the ONU 3, the transmission delay time can be reduced compared to when each ONU 3 performs the repeat processing the same number of times.

[0068] Although the above is a description of the embodiments of the present disclosure, the present disclosure is not limited to the configurations of the above embodiments, and various modifications and combinations are possible within the scope of the technical concept. For example, although an example has been shown in which a configuration having multiple reception processing units 68 corresponding to multiple ONUs 3 is applied to a 25GS-PON system, the same is applicable to all communication systems that use LDPC codes as FEC codes.

[0069] In the embodiment, the number of iterations of the error correction process is set and stored according to the degree of degradation of the signal received during the PON link-up sequence, and the error correction process is performed using the stored number of iterations after link-up. However, the number of iterations of the error correction process may be dynamically changed according to changes in the degree of degradation of the upstream signal received by the OLT 2 after link-up. For example, if an error is corrected using an error correction process performed fewer times than the stored number of iterations, the OLT 2 may update the stored number of iterations to a smaller number. Conversely, if an error is not corrected even after repeating the error correction process the stored number of iterations, the OLT 2 may update the stored number of iterations to a larger number. In this case, the transmission delay time of data transmission using LDPC codes can be further reduced. [Explanation of symbols]

[0070] 1 Communication system, 2 OLT, 3 ONU, 3a First ONU, 3b Second ONU, 3c Third ONU, 4 Optical fiber, 5 Optical splitter, 21 Control unit, 22 SNI, 23 PON interface, 31 Control unit, 32 UNI, 33 PON interface, 61 Data input unit, 62 GEM frame transmitter, 63 FS frame transmitter, 64 LDPC coding unit, 65 Downstream signal output unit, 66 OLT optical transceiver, 67 Upstream signal detection unit, 68 Reception processing unit, 68a First reception processing unit, 68b Second reception processing unit, 68c Third reception processing unit, 69 Data multiplexing unit, 70 Data output unit, 71 LDPC decoding unit, 72 FS frame receiver, 73 GEM frame receiver, 81 Data input unit, 82 GEM frame transmitter, 83 FS frame transmitter, 84 LDPC coding unit, 85 Upstream signal output unit, 86 ONU optical transceiver, 87 downstream signal detection unit, 88 LDPC decoding unit, 89 FS frame receiving unit, 90 GEM frame receiving unit, 91 data output unit, 101 processor, 102 main memory device, 103 auxiliary memory device, 104 bus.

Claims

1. a detection unit that detects upstream signals including LDPC encoded data transmitted from each of a first external device and a second external device; a first receiving processor that decodes LDPC encoded data transmitted from the first external device; a second receiving processing unit that is in parallel with the first receiving processing unit and that decodes the LDPC encoded data transmitted from the second external device; The first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal. Communication equipment.

2. a data multiplexing unit that multiplexes and outputs the processing results of the first reception processing unit and the second reception processing unit; The communication device according to claim 1 .

3. The first reception processing unit setting the number of times the error correction process is to be repeated during link-up with the first external device; changing the number of times the error correction process is repeated in accordance with a change in the degree of degradation of the upstream signal received after link-up with the first external device; The second reception processing unit setting the number of times the error correction process is to be repeated during link-up with the second external device; The number of times the error correction process is repeated is changed in accordance with a change in the degree of degradation of the upstream signal received after link-up with the second external device.

3. The communication device according to claim 1 or 2.

4. A communication device according to claim 1 or 2; the first external device; the second external device, The first external device and the second external device each repeatedly perform error correction processing a number of times corresponding to the expected maximum degree of degradation of the LDPC encoded data received from the communication device. Communication system.

5. a detection step of detecting upstream signals including LDPC encoded data transmitted from each of the first external device and the second external device; a first decoding step in a first receiving processing unit of decoding LDPC encoded data transmitted from the first external device; a second decoding step, which is performed in parallel with the first decoding step, of decoding, in a second reception processing unit, the LDPC-encoded data transmitted from the second external device; The first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal. Incoming processing method.

6. a detection step of detecting upstream signals including LDPC encoded data transmitted from each of the first external device and the second external device; a first decoding step in a first receiving processing unit of decoding LDPC encoded data transmitted from the first external device; a second decoding step, which is performed in parallel with the first decoding step, in a second reception processing unit, of decoding the LDPC-encoded data transmitted from the second external device in parallel with the first decoding step; The first reception processing unit and the second reception processing unit repeatedly perform error correction processing a number of times according to the degree of degradation of the received uplink signal. Reception processing program.

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