Indication device

Abstract

To reduce display unevenness in a display device. [Solution] The display device includes a light-emitting element, a first transistor and a second transistor connected in series between the light-emitting element and a driving power line, a third transistor electrically connected to the gate electrode of the first transistor, and a fourth transistor connected in parallel between the drain of the first transistor and the light-emitting element, wherein the ratio of the channel width W1 to the channel length L1 of the first transistor (W1 / L1 ratio) and the ratio of the channel width W2 to the channel length L2 of the second transistor (W2 / L2 ratio) are greater than the ratio of the channel width W3 to the channel length L3 of the third transistor (W3 / L3 ratio) and the ratio of the channel width W4 to the channel length L4 of the fourth transistor (W4 / L4 ratio).

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a display device, and more particularly to a pixel configuration of a display device. [Background technology]

[0002] Organic electroluminescence (hereinafter referred to as organic EL) display devices are the subject of active research due to their advantages, such as a wide viewing angle, fast response, and the ability to be used as a sheet display. In organic EL display devices, each pixel is provided with a light-emitting element, and images are displayed by individually controlling light emission. The light-emitting element has a structure in which a layer containing an organic EL material (hereinafter also referred to as the "light-emitting layer") is sandwiched between a pair of electrodes, one of which is distinguished as the anode and the other as the cathode. When electrons are injected into the light-emitting layer from the cathode and holes are injected from the anode, the electrons and holes recombine. The excess energy released as a result excites the light-emitting molecules in the light-emitting layer, which then emit light by de-excitation.

[0003] In recent years, oxide semiconductors (OS) have been attracting attention as semiconductor layers that constitute organic electroluminescence (EL) display devices. Transistors using oxide semiconductor layers have low off-leakage current and can be driven at low frequencies, so they are expected to be applied to low-power display devices. In particular, applying transistors using oxide semiconductor layers to self-emitting organic EL display devices can significantly reduce power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-254950 Summary of the Invention [Problem to be solved by the invention]

[0005] A transistor using an oxide semiconductor layer has a problem of low reliability, such as a change in threshold voltage over time. For example, a transistor using an oxide semiconductor layer tends to have larger fluctuations in characteristics due to voltage stress than a transistor using low-temperature polysilicon. Therefore, compared to a liquid crystal display device using one transistor per pixel, an organic EL display device using multiple transistors per pixel is more likely to have display unevenness due to fluctuations in the characteristics of each transistor.

[0006] In view of the above problems, one object of one embodiment of the present invention is to improve the reliability of a display device. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first transistor and a second transistor connected in series between a light-emitting element and a driving power line, a third transistor electrically connected to the gate electrode of the first transistor, and a fourth transistor connected in parallel between the drain of the first transistor and the light-emitting element, wherein the ratio of the channel width W1 to the channel length L1 of the first transistor (W1 / L1 ratio) and the ratio of the channel width W2 to the channel length L2 of the second transistor (W2 / L2 ratio) are greater than the ratio of the channel width W3 to the channel length L3 of the third transistor (W3 / L3 ratio) and the ratio of the channel width W4 to the channel length L4 of the fourth transistor (W4 / L4 ratio). [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view illustrating a configuration of a display device according to an embodiment of the present invention. [Figure 2] 1 is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention. [Figure 3] 1 is a planar layout diagram of pixels included in a display device according to one embodiment of the present invention. [Figure 4] 1 is a diagram illustrating a cross-sectional structure of a pixel of a display device according to one embodiment of the present invention. [Figure 5] 1 is an equivalent circuit diagram of a pixel included in a display device according to one embodiment of the present invention. [Figure 6] 1 is a planar layout diagram of pixels included in a display device according to one embodiment of the present invention. [Figure 7] 1 is a graph showing the Id-Vg characteristics of a transistor IST. [Figure 8] 1 is a graph showing the Id-Vg characteristics of a transistor BCT. [Figure 9A] 1 is a graph showing the results of a PBTS test. [Figure 9B] 1 is a graph showing the results of a PBTS test. [Figure 9C] 1 is a graph showing the results of a PBTS test. [Figure 9D] 1 is a graph showing the results of a PBTS test. [Figure 9E] 1 is a graph showing the results of a PBTS test. [Figure 9F] 1 is a graph showing the results of a PBTS test. [Figure 9G] 1 is a graph showing the results of a PBTS test. [Figure 9H] 1 is a graph showing the results of a PBTS test. [Figure 9I] 1 is a graph showing the results of a PBTS test. [Figure 9J] 1 is a graph showing the results of a PBTS test. [Figure 9K] 1 is a graph showing the results of a PBTS test. [Figure 9L] 1 is a graph showing the results of a PBTS test. [Figure 10] The graph shows the relationship between the threshold voltage Vth [V] and the drive transistor DRT, the write transistor SST, and the output transistor BCT that each of the display devices A to C and the display device INI has. [Figure 11] 10 is a graph summarizing the amount of current decrease after driving display devices A to C. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in the drawings, the width, thickness, shape, etc. of each part may be shown schematically compared to the actual form to make the explanation clearer. However, these schematic diagrams are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements that are the same or similar to those described in the previous drawings may be given the same reference numerals, and redundant explanations may be omitted.

[0010] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

[0011] In this specification, expressions such as "above" and "below" when describing the drawings express the relative positional relationship between a structure of interest and other structures. In this specification, the direction from the first substrate (described later) toward the pixel electrode in a side view is defined as "above," and the opposite direction is defined as "below." In this specification and claims, when describing an aspect in which another structure is disposed on top of another structure, the term "above" is used to refer to both a case in which another structure is disposed directly above the structure so as to be in contact with the structure, and a case in which another structure is disposed above the structure via another structure, unless otherwise specified.

[0012] In this specification, bottom gate driving refers to on / off control by a gate electrode arranged below the semiconductor layer. In this specification, top gate driving refers to on / off control by a gate electrode arranged above the semiconductor layer. In this specification, dual gate driving refers to on / off control by inputting the same control signal to gate electrodes arranged above and below the semiconductor layer.

[0013] (First embodiment) A display device 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0014] 1 is a plan view illustrating the configuration of a display device 100 according to one embodiment of the present invention. As shown in FIG. 1, the display device 100 includes a display region 102 and a peripheral region 109 provided on a substrate 101.

[0015] The display region 102 has a plurality of pixels 103 arranged in a matrix. Each of the plurality of pixels 103 has a plurality of transistors and a light-emitting element.

[0016] The peripheral region 109 is provided to surround the display region 102. The peripheral region 109 refers to the region of the substrate 101 from the display region 102 to the edge of the substrate 101. In other words, the peripheral region 109 refers to the region on the substrate 101 other than where the display region 102 is provided (i.e., the region outside the display region 102). The peripheral region 109 has gate drive circuits 104_1 and 104_2 and a terminal unit 107 including a plurality of terminals 106. The gate drive circuits 104_1 and 104_2 are provided to sandwich the display region 102. The driver IC 105 is provided on a flexible printed circuit 108 in the form of an IC chip. The flexible printed circuit 108 is connected to the plurality of terminals 106. 1 shows an example in which a source driving circuit is incorporated into the driver IC 105, but this is not limiting and the source driving circuit may be provided on the substrate 101 separately from the driver IC 105. Also, this shows an example in which the driver IC 105 is disposed on the flexible printed circuit 108, but this is not limiting and the driver IC 105 may be disposed on the substrate 101.

[0017] The driver IC 105 is connected to the gate drive circuits 104_1 and 104_2 and a plurality of video signal lines VL. The gate drive circuit 104_1 or the gate drive circuit 104_2 is connected to the pixels 103 via write control scan lines Sgb. Of the plurality of write control scan lines Sgb, for example, the write control scan lines Sgb of odd rows are connected to the gate drive circuit 104_1, and the write control scan lines Sgb of even rows are connected to the gate drive circuit 104_2. The video signal lines VL are connected to the pixels 103. A control signal SG for selecting each pixel 103 is provided to the display region 102 from the driver IC 105 via the gate drive circuits 104_1 and 104_2 and the write control scan lines Sgb. A video signal Vsig is also provided to the display region 102 from the driver IC 105 via the video signal line VL. These signals drive the transistors of the pixels 103, thereby enabling an image to be displayed in accordance with the video signal Vsig in the display area 102. The high potential power supply SLa and the low potential power supply SLb connected to the pixels 103 are connected to different terminals 106, respectively.

[0018] A glass substrate or a flexible plastic substrate is used as the substrate 101. When a flexible plastic substrate is used as the substrate 101, the region between the display region 102 and the terminal portion 107 can be bent. This allows the frame of the display device 100 to be narrowed.

[0019] <Equivalent circuit diagram> 2 is an equivalent circuit diagram of a pixel 103 included in a display device 100 according to one embodiment of the present invention. The pixel 103 of the display device 100 includes a high potential power supply SLa, a low potential power supply electrode SLb, a light emitting The pixel electrode 104 has a control scanning line Sga, a write control scanning line Sgb, a video signal line VL, and a reset power line SLc. The high potential power supply SLa is supplied with a high potential power supply Pvdd, and the low potential power supply electrode SLb is supplied with a low potential power supply Pvss. The write control scanning line Sgb is connected to gate drive circuits 104_1 and 104_2, and the video signal line VL and the reset power line SLc are connected to a driver IC 105.

[0020] The pixel 103 includes at least a drive transistor DRT (also referred to as a first transistor), an output transistor BCT (also referred to as a second transistor), a write transistor SST (also referred to as a third transistor), a reset transistor RST (also referred to as a fourth transistor), a storage capacitor Cs, and a light-emitting element OLED. The write transistor SST, the drive transistor DRT, the output transistor BCT, and the reset transistor RST each have a first terminal, a second terminal, and a control terminal. In this specification, the first terminal is referred to as a source electrode, the second terminal is referred to as a drain electrode, and the control terminal is referred to as a gate electrode.

[0021] A high potential power supply Pvdd is applied to the anode (also called pixel electrode) of the light emitting element OLED via the output transistor BCT and the drive transistor DRT, and a low potential power supply Pvss is applied to the cathode (also called common electrode).

[0022] In the output transistor BCT, the source electrode is connected to a high-potential power supply SLa, the drain electrode is connected to the source electrode of the drive transistor DRT, and the gate electrode is connected to the light-emission control scan line Sga. In the output transistor BCT, the on state (conductive state) or off state (non-conductive state) is controlled by a control signal BG from the light-emission control scan line Sga. The output transistor BCT controls the light-emission time of the light-emitting element OLED in response to the control signal BG.

[0023] The write transistor SST has a gate electrode connected to the write control scan line Sgb, a source electrode connected to the video signal line VL, and a drain electrode connected to the gate electrode of the drive transistor DRT. The write transistor SST functions as a switching element that selects conduction or non-conduction between the two nodes, and writes a voltage corresponding to the emission brightness of the light-emitting element OLED.

[0024] In the drive transistor DRT, the drain electrode is connected to the anode of the light-emitting element OLED, the source electrode is connected to the drain electrode of the output transistor BCT, and the gate electrode is connected to the drain electrode of the write transistor SST and one electrode of the storage capacitor Cs. In other words, the drive transistor DRT is connected in series with the light-emitting element OLED and the output transistor BCT between the high-potential power supply SLa and the low-potential power supply electrode SLb. The drive transistor DRT functions as a current control element that controls the value of the current flowing through the light-emitting element OLED in accordance with the gate-source voltage. As a result, the drive transistor DRT outputs a drive current to the light-emitting element OLED in an amount corresponding to the video signal Vsig.

[0025] In the reset transistor RST, the source electrode is connected to a reset power line SLc connected to a reset power supply, the drain electrode is connected to the other electrode of the storage capacitor Cs and the light-emitting element OLED, and the gate electrode is connected to a reset control scan line Sgc that functions as a reset control gate wiring. In other words, the drain electrode of the reset transistor RST is connected to the gate electrode of the drive transistor DRT via the storage capacitor Cs. The reset power line SLc is connected to the reset power supply and is fixed to a reset potential Vrst, which is a constant potential.

[0026] The reset transistor RST switches between the reset power line SLc and the reset control scan line Sgr to an ON state or an OFF state in response to a control signal RG given through the reset control scan line Sgc. When the reset transistor RST is switched to the ON state, the potential of the drain electrode of the drive transistor DRT is initialized.

[0027] A storage capacitor Cs may be provided between the gate and drain of the driving transistor DRT. The storage capacitor Cs holds the gate-drain voltage of the driving transistor DRT for a certain period of time.

[0028] For example, amorphous silicon, low-temperature polysilicon, or oxide semiconductor is used as the semiconductor layer of the transistor constituting the display device 100. Here, a transistor using an oxide semiconductor layer has a low off-leakage current and can be driven at a low frequency, thereby realizing a display device 100 with low power consumption. Furthermore, compared to a transistor having a low-temperature polysilicon layer, a transistor using an oxide semiconductor layer does not exhibit a kink effect and therefore has good saturation characteristics. In this embodiment, a case where an oxide semiconductor layer is used as the semiconductor layer of the transistor constituting the display device 100 will be described.

[0029] Transistors using an oxide semiconductor layer have a problem of low reliability, such as a change in threshold voltage over time. For example, transistors using an oxide semiconductor tend to have larger fluctuations in characteristics due to voltage stress than transistors using low-temperature polysilicon. Therefore, compared to liquid crystal display devices using one transistor per pixel, organic EL display devices using multiple transistors per pixel are more likely to have display unevenness due to fluctuations in the characteristics of each transistor.

[0030] For example, in a pixel using four transistors as shown in Figure 2, a negative bias is applied for a long time to the write transistor SST and reset transistor RST, which are used to hold and reset the signal potential, in order to drive at a low frequency. On the other hand, a positive bias is applied for a long time to the output transistor BCT and drive transistor DRT, which control the current flowing through the light-emitting element OLED. When such a pixel is used as a display device and driven for a long time, it has been found that the degradation rates of the output transistor BCT and drive transistor DRT are significantly different from those of the write transistor SST and reset transistor RST within the same pixel. In particular, it has been found that the threshold voltages of transistors such as the output transistor BCT and drive transistor DRT, which control the current flowing through the light-emitting element OLED, tend to drift to the positive side. However, it is difficult to improve such variations in transistor characteristics by adjusting the semiconductor manufacturing process (so-called process tuning).

[0031] Transistors using an oxide semiconductor layer have different characteristics depending on the ratio of their channel width W to their channel length L (also referred to as the W / L ratio), even when fabricated using the same process and on the same substrate. This is because the larger the channel width W and the shorter the channel length L of a transistor, the more likely oxygen vacancies are to occur in the oxide semiconductor, resulting in a change in the Fermi level of the active layer. Essentially, the closer the Fermi level is to a conductor, the less likely carrier traps are formed in the gate insulating film, reducing the amount of positive drift in the threshold voltage caused by stress due to a positive bias applied to the gate. On the other hand, the shorter the channel length L, the more likely negative drift in the threshold voltage, known as photodegradation, occurs. Therefore, simply increasing the W / L ratio of a transistor gradually leads to a negative drift in the threshold voltage. In this specification, the channel region refers to the region where the oxide semiconductor layer overlaps with the gate electrode. The channel length L refers to the length in the direction connecting the source electrode and the drain electrode in the region where the oxide semiconductor layer overlaps with the gate electrode. The channel width W refers to the length in a direction perpendicular to the channel length L in a region where the oxide semiconductor layer overlaps with the gate electrode.

[0032] Therefore, in the display device 100 according to one embodiment of the present invention, the W / L ratio of the transistor used for emitting light from the light-emitting element OLED is set to be larger than the W / L ratio of the transistor used for retaining or resetting the charge of the capacitance where a negative bias is dominant. That is, in the pixel 103 shown in FIG. 2, the W / L ratios of the write transistor SST and the reset transistor RST are set to be small, and the W / L ratios of the output transistor BCT and the drive transistor DRT are set to be large. Specifically, the W / L ratios of the write transistor SST and the reset transistor RST are set to be less than 1.5, and the W / L ratios of the output transistor BCT and the drive transistor DRT are set to be 1.5 or more. Preferably, the W / L ratios of the write transistor SST and the reset transistor RST are set to be 1.0 or less, and the W / L ratios of the output transistor BCT and the drive transistor DRT are set to be 2.0 or more.

[0033] This configuration suppresses negative drift of the threshold voltages of the transistors SST and RST used for holding and resetting the charge in the capacitor, and also reduces the amount of positive drift of the threshold voltage of the transistor used for emitting light from the light-emitting element OLED, which is caused by stress due to a positive bias applied to the gate. Therefore, deterioration of the transistors in the pixels 103 of the display device 100 can be suppressed. This improves the reliability of the display device 100.

[0034] <Plane layout and cross section of pixel> Next, a planar layout and a cross section of pixel 103 of display device 100 according to one embodiment of the present invention will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a planar layout diagram of pixel 103 of display device 100 according to one embodiment of the present invention. Fig. 4 is a cross-sectional view of pixel 103 shown in Fig. 3 taken along line A1-A2.

[0035] As shown in FIG. 3, the pixel 103 has transistors 310, 320, 330, and 340, and a storage capacitor 360. The transistor 310 corresponds to the drive transistor DRT. The transistor 320 corresponds to the output transistor BCT. The transistor 330 corresponds to the write transistor SST. The transistor 340 corresponds to the reset transistor RST. The storage capacitor 360 corresponds to the storage capacitor Cs. Although the transistors 310 to 340 will all be described as top-gate drive transistors, they may also be bottom-gate drive transistors or dual-gate drive transistors.

[0036] 3 illustrates oxide semiconductor layers 208-1 to 208-4, conductive layers 214-1 to 214-4, conductive layers 218-1 to 218-6, conductive layer 219-1, and contact holes 211-1 to 211-8, 217-1, and 221-1. Insulating films such as a base film, a gate insulating film, an interlayer insulating film, and a planarizing film are not shown in FIG. 3. Furthermore, layers above conductive layer 219-1 are also not shown in FIG.

[0037] The transistor 310 includes an oxide semiconductor layer 208-1, conductive layers 214-1, 218-2, and 218-3, and a gate insulating film. The conductive layer 214-1 functions as a gate electrode in a region overlapping with the oxide semiconductor layer 208-1. The oxide semiconductor layer 208-1 is connected to conductive layers 218-2 and 218-3 through contact holes 211-1 and 211-2 formed in the gate insulating film and the interlayer insulating film. Although not shown in FIG. 3 , the oxide semiconductor layer 208-1 is electrically connected to a pixel electrode of the light-emitting element OLED through the conductive layers 218-3 and 219-1.

[0038] The transistor 320 includes an oxide semiconductor layer 208-2, a conductive layer 214-2, conductive layers 218-2 and 218-4, and a gate insulating film. The conductive layer 214-2 functions as a gate electrode in a region overlapping with the oxide semiconductor layer 208-2. The oxide semiconductor layer 208-2 is connected to the conductive layers 218-2 and 218-4 through contact holes 211-3 and 211-4 provided in the gate insulating film and the interlayer insulating film. The transistor 320 is connected to the transistor 310 through the conductive layer 218-2.

[0039] The transistor 330 includes an oxide semiconductor layer 208-3, a conductive layer 214-3, conductive layers 218-1 and 218-5, and a gate insulating film. The conductive layer 214-3 functions as a gate electrode in a region overlapping with the oxide semiconductor layer 208-3. The oxide semiconductor layer 208-3 is connected to the conductive layers 218-1 and 218-5 through contact holes 211-5 and 211-6 provided in the gate insulating film and the interlayer insulating film.

[0040] The transistor 340 includes an oxide semiconductor layer 208-4, a conductive layer 214-4, conductive layers 218-1 and 218-6, and a gate insulating film. The conductive layer 214-4 functions as a gate electrode in a region overlapping with the oxide semiconductor layer 208-4. The oxide semiconductor layer 208-4 is connected to the conductive layers 218-1 and 218-6 through contact holes 211-7 and 211-8 provided in the gate insulating film and the interlayer insulating film. The transistor 340 is connected to the transistor 330 through the conductive layer 218-1.

[0041] The storage capacitor 360 is composed of a conductive layer 218-1, a conductive layer 219-1, and an interlayer insulating film.

[0042] The transistor 310 has a channel width W1 and a channel length L1. Although not shown in FIG. 3, the transistor 320 also has a channel width W2 and a channel length L2. Furthermore, the transistor 330 has a channel width W3 and a channel length L3. Although not shown in FIG. 3, the transistor 340 also has a channel width W4 and a channel length L4. Furthermore, in this specification and the like, the ratio of the channel width W to the channel length L of a transistor is referred to as the W / L ratio. For example, the ratio of the channel width W1 to the channel length L1 of the transistor 310 is referred to as the W1 / L1 ratio. The W / L ratios of the transistors 320 to 340 are also described in the same manner as for the transistor 310.

[0043] Comparing transistor 310 and transistor 330, the W1 / L1 ratio of transistor 310 is greater than the W3 / L3 ratio of transistor 330. For example, the W1 / L1 ratio of transistor 310 is 1.5 or greater, while the W3 / L3 ratio of transistor 330 is less than 1.5. Comparing transistor 320 and transistor 330, the W2 / L2 ratio of transistor 320 is greater than the W3 / L3 ratio of transistor 330. For example, the W2 / L2 ratio of transistor 320 is 1.5 or greater, while the W3 / L3 ratio of transistor 330 is less than 1.5. The W1 / L1 ratio of transistor 310 and the W2 / L2 ratio of transistor 320 may be the same or different.

[0044] In this way, the W1 / L1 ratio of transistor 310 and the W2 / L2 ratio of transistor 320 are made larger than the W3 / L3 ratio of transistor 330 and the W4 / L4 ratio of transistor 340. This suppresses negative drift of the threshold voltages of transistors SST and RST, which are used to retain and reset the charge of the capacitors, and also reduces the amount of positive drift of the threshold voltage of the transistor used to emit light from the light-emitting element OLED due to gate positive bias stress. This suppresses transistor degradation in the pixels of the display device, thereby improving the reliability of the display device.

[0045] As described above, the W1 / L1 ratio of transistor 310 and the W2 / L2 ratio of transistor 320 may be 1.5 or greater. Therefore, the W1 / L1 ratio of transistor 310 and the W2 / L2 ratio of transistor 320 may be the same or different.

[0046] Furthermore, the W3 / L3 ratio of transistor 330 and the W4 / L4 ratio of transistor 340 need only be less than 1.5. Therefore, the W3 / L3 ratio of transistor 330 and the W4 / L4 ratio of transistor 340 may be the same or different. However, since the stress applied to transistor 330 and transistor 340 is almost the same, it is preferable that the W3 / L3 ratio of transistor 330 and the W4 / L4 ratio of transistor 340 are the same.

[0047] In addition, in this embodiment, the channel length L1 of the transistor 310 and the channel length L2 of the transistor 320 are illustrated as being the same as the channel length L3 of the transistor 330 and the channel length L4 of the transistor 340, but this embodiment of the present invention is not limited to this. For example, the channel length L1 of the transistor 310 may be different from the channel length L3 of the transistor 330 and the channel length L4 of the transistor 340. Specifically, the channel length L1 of the transistor 310 may be longer than the channel length L3 of the transistor 330 and the channel length L4 of the transistor 340. Increasing the channel length L1 of the transistor 310 can increase the S value.

[0048] <Cross-sectional structure of pixel> 4 is a diagram illustrating a cross-sectional structure of a pixel 103 of a display device 100 according to one embodiment of the present invention. As shown in FIG. 4, a transistor 310 and a transistor 330 are provided on a substrate 101 with an insulating film 202 interposed therebetween. The transistor 310 is connected to a light-emitting element 230. Here, the transistor 310 corresponds to the drive transistor DRT, the transistor 330 corresponds to the write transistor SST, and the light-emitting element 230 corresponds to the light-emitting element OLED.

[0049] The transistor 310 includes at least an oxide semiconductor layer 208-1 provided over an insulating film 202, an insulating film 212 provided over the oxide semiconductor layer 208-1, a conductive layer 214-1 provided over the insulating film 212, and conductive layers 218-2 and 218-3 provided over an insulating film 216. The oxide semiconductor layer 208-1 includes a channel region 208a and impurity regions 208b and 208c. The impurity regions 208b and 208c are provided with the channel region 208a sandwiched therebetween. In the oxide semiconductor layer 208-1, the channel region 208a overlaps with the conductive layer 214-1. The insulating film 212 functions as a gate insulating film of the transistor 310. An insulating film 216 is provided over the conductive layer 214-1. The insulating film 216 functions as an interlayer insulating film. The conductive layers 218-2 and 218-3 function as a source electrode and a drain electrode. The conductive layer 218-2 is connected to the impurity region 208c through a contact hole 211-2 provided in the insulating films 212 and 216. The conductive layer 218-3 is connected to the impurity region 208b through a contact hole 211-1 provided in the insulating films 212 and 216. The conductive layer 218-3 is connected to the conductive layer 219-1 through a contact hole 217-1 provided in the insulating film 223.

[0050] The transistor 330 includes at least an oxide semiconductor layer 208-3 provided over the insulating film 202, an insulating film 212 provided over the oxide semiconductor layer 208-3, a conductive layer 214-3 provided over the insulating film 212, and conductive layers 218-1 and 218-5 provided over the insulating film 216. The insulating film 212 functions as a gate insulating film. The oxide semiconductor layer 208-3 includes a channel region 208d and impurity regions 208e and 208f. The impurity regions 208e and 208f sandwich the channel region 208d. The channel region 208d is a region in the oxide semiconductor layer 208-3 that overlaps with the conductive layer 214-3. An insulating film 216 is provided over the conductive layer 214-3. The insulating film 216 functions as an interlayer insulating film. The conductive layers 218-1 and 218-5 function as source and drain electrodes. The conductive layer 218-1 is connected to the impurity region 208f through a contact hole 211-5 provided in the insulating films 212 and 216. The conductive layer 218-5 is connected to the impurity region 208e through a contact hole 211-6 provided in the insulating films 212 and 216.

[0051] 4, in this embodiment, the transistors 320 and 340 have a top-gate structure similar to the transistor 310. However, in one embodiment of the present invention, the present invention is not limited to this and may have a structure different from that of the transistor 310.

[0052] A storage capacitor 360 is configured by the conductive layer 218-1 provided on the insulating film 212, the insulating film 223, and the conductive layer 219-1.

[0053] A planarization film 222 is provided on the conductive layer 219-1. The planarization film 222 is provided to reduce unevenness caused by the transistors 310 and 320 and the storage capacitor 360. A pixel electrode 226 is provided on the planarization film 222. The pixel electrode 226 is provided for each pixel 103. The pixel electrode 226 is connected to the conductive layer 219-1 through a contact hole 221-1 provided in the planarization film 222. That is, the transistor 310 is connected to the pixel electrode 226 through the conductive layers 218-3 and 219-1.

[0054] The light-emitting element 230 has a pixel electrode 226, an organic layer 232, and a common electrode 234. In one embodiment of the present invention, the display device 100 may be a top-emission type or a bottom-emission type. In this embodiment, the display device 100 will be described as having a top-emission structure. In the case of a top-emission structure, the pixel electrode 226 serves as an anode, and the common electrode 234 serves as a cathode.

[0055] An insulating layer 228 is provided so as to cover the edges of the pixel electrodes 226. The insulating layer 228 is also called a partition wall or a bank. The insulating layer 228 has an opening so that the pixel electrodes 226 are exposed, and the edges of the opening preferably have a gently tapered shape. If the edges of the opening have a steep shape, poor coverage of the organic layer 232 to be formed later will occur.

[0056] A plurality of organic materials constituting the organic layer 232 are stacked on the pixel electrode 226 and the insulating layer 228. The organic layer 232 is provided by stacking, in order from the pixel electrode 226 side, a hole transport layer, a light-emitting layer, an electron transport layer, and the like. These layers may be formed by vapor deposition or by coating on a solvent dispersion. The hole transport layer, electron transport layer, and the like may be selectively formed for each subpixel, or may be formed over the entire display region 102.

[0057] A common electrode 234 is provided on the organic layer 232. In this embodiment, since a top emission structure is employed, the common electrode 234 needs to be light-transmitting. When MgAg is used as the common electrode 234, it is formed as a thin film that allows light emitted from the organic layer 232 to pass through. The common electrode 234 is connected to a wiring layer at a cathode contact portion provided in the peripheral region 109, and is electrically connected to the terminal 106.

[0058] A sealing film 240 is provided on the common electrode 234. The sealing film 240 is provided to prevent moisture from entering from the outside from penetrating into the organic layer 232. In this embodiment, the sealing film 240 is formed as a three-layer structure including an inorganic insulating layer 236, an organic insulating layer 238, and an inorganic insulating layer 242. It is preferable to use silicon nitride, which has high gas barrier properties, for the inorganic insulating layers 236 and 233, and an organic resin material, which has high flexibility, for the organic insulating layer 238. A silicon oxide film or an amorphous silicon film may be provided between the silicon nitride and the organic resin material. This improves the adhesion between the silicon nitride and the organic resin material. An overcoat layer, for example, may be provided on the inorganic insulating layer 242 to also serve as a planarization layer.

[0059] The touch sensor 110 is provided on the sealing film 240. The touch sensor 110 may be formed directly on the sealing film 240. Alternatively, a cover glass on which the touch sensor 110 is formed may be provided on the sealing film 240.

[0060] <Materials of Components of Display Device 100> The substrate 101 can be a rigid substrate that is light-transmitting and not flexible, such as a glass substrate, a quartz substrate, or a sapphire substrate. On the other hand, if the substrate 101 needs to be flexible, a flexible substrate that contains a resin and has flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate 101. In order to improve the heat resistance of the substrate 101, impurities may be introduced into the above resin.

[0061] Common metal materials can be used for the conductive layers 214-1 to 214-4 and the conductive layers 218-1 to 218-6. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used for these components. The above materials can be used as a single layer or as a multilayer.

[0062] A general insulating material can be used for the insulating films 202, 212, 216, and 223. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), Aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers As these insulating layers, insulating layers with few defects can be used. As the planarizing film 222 and the insulating layer 228, an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin is used. Note that the above organic insulating materials may also be used as the insulating films 202, 212, 216, and 223. As the above members, the above materials may be used in a single layer or a stacked layer.

[0063] The above SiO x N y and AlO x N yare silicon and aluminum compounds containing a smaller ratio (x>y) of nitrogen (N) than oxygen (O). x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0064] The oxide semiconductor layers 208-1 to 208-4 may be made of a metal oxide having semiconductor properties. The oxide semiconductor layers 208-1 to 208-4 are light-transmitting. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 may be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and oxide semiconductors with compositions different from the above may also be used. For example, the ratio of In may be increased to improve mobility. Furthermore, the ratio of Ga may be increased to increase the band gap and reduce the influence of light irradiation.

[0065] Other elements may be added to the oxide semiconductor containing In, Ga, Zn, and O. For example, metal elements such as Al and Sn may be added to the oxide semiconductor. In addition to the above oxide semiconductors, oxide semiconductors containing In and Ga (IGO), oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), and oxide semiconductors containing In and W may be used as the oxide semiconductor layers 208-1 to 208-4. Furthermore, when IGO or IZO is used as the oxide semiconductor, metal elements such as Al or An may be added. The oxide semiconductor layers 208-1 to 208-4 may be amorphous or crystalline. The oxide semiconductor layers 208-1 to 208-4 may be a mixed phase of amorphous and crystalline.

[0066] A transparent conductive layer is used as the pixel electrode 226 and the common electrode 234. The transparent conductive layer may be made of a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO). Materials other than those mentioned above may also be used for the transparent conductive layer.

[0067] (Second embodiment) In this embodiment, another example of the pixel 103 included in the display device 100 will be described with reference to Fig. 5 and Fig. 6. Note that in this embodiment, only the parts different from the first embodiment will be described, and detailed descriptions of the other parts will be omitted.

[0068] <Equivalent circuit diagram> Fig. 5 is an equivalent circuit diagram of the pixel circuit of pixel 103A. In this embodiment, an example in which a transistor IST (also referred to as a fifth transistor) is added to the pixel circuit shown in Fig. 2 will be described. The configurations of the write transistor SST, drive transistor DRT, output transistor BCT, and reset transistor RST may be referred to in the first embodiment.

[0069] The pixel 103A includes at least a write transistor SST, a drive transistor DRT, an output transistor BCT, a reset transistor RST, an initialization transistor IST, a storage capacitor Cs, and a light-emitting element OLED. The initialization transistor IST has a first terminal, a second terminal, and a control terminal.

[0070] The initialization transistor IST has a source electrode connected to an initialization signal line SLd, a drain electrode connected to the gate electrode of the drive transistor DRT, the drain electrode of the write transistor SST, and one electrode of the storage capacitor Cs, and a gate electrode connected to an initialization scan line Sgd. The initialization transistor IST is controlled to be in an on or off state by a control signal IG from the initialization scan line Sgd. When the initialization transistor IST is turned on, the gate electrode of the drive transistor DRT is fixed to an initialization potential Vini via the initialization transistor IST.

[0071] FIG. 6 is a planar layout diagram of a pixel 103A of a display device 100 according to one embodiment of the present invention.

[0072] As shown in FIG. 6, the pixel 103A has transistors 310, 320, 330, 340, and 350, and a storage capacitor 360. Compared to the layout diagram shown in FIG. 3, the layout diagram shown in FIG. 5 further includes a transistor 350. The transistor 350 corresponds to the initialization transistor IST. The transistor 350 will be described as a top-gate driven transistor, but may also be a bottom-gate driven transistor or a dual-gate driven transistor. In this embodiment, the transistors 310, 320, 330, 340, and 350 are described as top-gate driven transistors.

[0073] 6 shows oxide semiconductor layers 208-1 to 208-5, conductive layers 214-1 to 214-5, conductive layers 218-1 to 218-7, and contact holes 211-1 to 211-10, 217-1, and 221-1. Compared to the layout diagram shown in FIG. 3, an oxide semiconductor layer 208-5, a conductive layer 214-5, and a conductive layer 218-7 are further provided.

[0074] The transistor 350 includes an oxide semiconductor layer 208-5, a conductive layer 214-5, conductive layers 218-1 and 218-7, and a gate insulating film. The conductive layer 214-5 functions as a gate electrode in a region overlapping with the oxide semiconductor layer 208-5. The oxide semiconductor layer 208-5 is connected to the conductive layers 218-1 and 218-7 through contact holes 211-9 and 211-10 provided in the gate insulating film and the interlayer insulating film.

[0075] Transistor 350 has a channel width W5 and a channel length L5. Comparing transistor 310 and transistor 350, the W1 / L1 ratio of transistor 310 is greater than the W5 / L5 ratio of transistor 350. For example, the W1 / L1 ratio of transistor 310 is 1.5 or greater, while the W5 / L5 ratio of transistor 350 is less than 1.5.

[0076] Since the transistor 350 is the initialization transistor IST, a negative bias is dominant. Furthermore, the transistor 350 is not directly connected to the light-emitting element OLED. Therefore, the W5 / L5 ratio of the transistor 350 only needs to be less than 1.5.

[0077] The W5 / L5 ratio of transistor 350 may be the same as or different from the W3 / L3 ratio of transistor 330 and the W4 / L4 ratio of transistor 340.

[0078] In addition, in this embodiment, the channel length L1 of the transistor 310 and the channel length L2 of the transistor 320 are illustrated as being the same as the channel length L3 of the transistor 330, the channel length L4 of the transistor 340, and the channel length L5 of the transistor 350, but this embodiment is not limited to this. The channel length L1 of the transistor 310 may be different from the channel length L3 of the transistor 330, the channel length L4 of the transistor 340, and the channel length L5 of the transistor 350. Specifically, the channel length L1 of the transistor 310 may be longer than the channel length L3 of the transistor 330, the channel length L4 of the transistor 340, and the channel length L5 of the transistor 350. Increasing the channel length L1 of the transistor 310 can increase the S value. [Example]

[0079] In this example, the Id-Vg characteristics of a display device having a display area configured with pixels shown in FIG. 5 after being driven at 70° C. for 500 hours will be described.

[0080] In this example, a display device having a display region composed of the pixels shown in Figure 5 was fabricated. The display device was then driven at 70°C for 500 hours. The drive transistor DRT, output transistor BCT, write transistor SST, reset transistor RST, and initialization transistor IST were all top-gate transistors. The transistor sizes of the drive transistor DRT, output transistor BCT, write transistor SST, reset transistor RST, and initialization transistor IST were: channel length L = 3 μm, channel width W = 3 μm. The W / L ratios of each transistor are described as the W1 / L1 ratio of the drive transistor DRT, the W2 / L2 ratio of the output transistor BCT, the W3 / L3 ratio of the write transistor SST, the W4 / L4 ratio of the reset transistor RST, and the W5 / L5 ratio of the initialization transistor IST.

[0081] Of the pixel 103 shown in Figure 5, the Id-Vg characteristics of the transistor IST and the transistor BCT were measured before and after driving. The Id-Vg characteristics were measured by applying a gate voltage (Vg) to the gate electrode of each transistor ranging from -5V to +10V in 0.1V steps. The source voltage (Vs) applied to the source electrode was set to 0V, and the drain voltage (Vd) applied to the drain electrode was set to 0.1V and 10V.

[0082] FIG. 7 is a graph of the Id-Vg characteristics of transistor IST. FIG. 8 is a graph of the Id-Vg characteristics of transistor BCT. In FIGS. 7 and 8, the vertical axis represents drain current Id [A] and the horizontal axis represents gate voltage Vg [V]. In FIGS. 7 and 8, the dotted line represents the Id-Vg characteristics in the initial state, and the solid line represents the Id-Vg characteristics after driving.

[0083] As shown in Figure 7, no change in the Id-Vg characteristics of the transistor IST was observed between the initial state of the display device and after it was driven. On the other hand, as shown in Figure 8, it was confirmed that the Id-Vg characteristics of the transistor BCT drifted to the positive side between the initial state of the display device and after it was driven.

[0084] 7 and 8, it was shown that the Id-Vg characteristics of the transistor BCT connected in series with the light-emitting element OLED drift to the positive side when a positive bias is applied to the transistor BCT. In other words, it was shown that the amount of degradation increases when the W1 / L1 ratio of the transistor BCT connected in series with the light-emitting element OLED is less than 1.5.

[0085] Next, the results of investigating the W / L dependency of the threshold voltage Vth variation due to PBTS stress will be explained.

[0086] First, we fabricated transistors with different W / L ratios (channel length L and channel width W). Transistors TrA to TrL were fabricated with channel widths W of 3 μm, 4.5 μm, 6 μm, and 7.5 μm for channel lengths L of 2 μm, 3 μm, and 4 μm, respectively. Table 1 shows the fabricated transistors TrA to TrL.

[0087] [Table 1]

[0088] The dependence of the threshold voltage (Vth) variation on the W / L ratio was investigated using a PBTS (Positive Bias Temperature Stress) test. The PBTS test conditions were a gate voltage (Vg) of +30V, drain voltage (Vd) and source voltage (Vs) of 0V (COMMON), stress temperature of 60°C, stress application time of 0 sec and 3600 sec, and measurement was performed in a dark environment. That is, the source and drain electrodes of the transistor were at the same potential, and a different potential from the source and drain electrodes was applied to the gate electrode for a certain period of time. The potential applied to the gate electrode was higher than the potentials of the source and drain electrodes.

[0089] The results of the PBTS test are shown in Figures 9A to 9L. The results in Figures 9A to 9L correspond to transistors TrA to TrL, respectively. In Figures 9A to 9L, the vertical axis represents drain current Id [A], and the horizontal axis represents gate voltage Vg [V]. Table 2 shows the W / L ratio, threshold voltage Vth [V], and threshold voltage variation ΔVth [V] for transistors TrA to TrL. In Figures 9A to 9L, the dashed lines show the Id-Vg characteristics at drain voltages (Vd) of 0.1 V and 10 V when the stress application time is 0 seconds, and the dashed lines show the Id-Vg characteristics at drain voltages (Vd) of 0.1 V and 10 V when the stress application time is 3600 seconds.

[0090] [Table 2]

[0091] As shown in Table 2, Figures 9E, 9I, and 9J, it was confirmed that when the W / L ratio of the transistor size is less than 1.5, the threshold voltage Vth of the transistor shifts in the positive direction by 2.0 V or more. On the other hand, as shown in Table 2, Figures 9A to 9D, 9F to 9H, 9K, and 9L, when the W / L ratio of the transistor size is 1.5 or more, even if the threshold voltage Vth of the transistor shifts in the positive direction, it is less than 2.0 V.

[0092] As explained above, it was shown that a W / L ratio of 1.5 or more for the transistor size can suppress a positive shift in threshold voltage. Therefore, it was suggested that the reliability of a display device can be improved by using transistors with a W / L ratio of 1.5 or more as the transistors DRT and BCT, to which a positive bias is continuously applied.

[0093] Next, four display devices according to one embodiment of the present invention were fabricated, and after they were driven at 70° C. for 500 hours, the amount of change in the threshold voltage of the transistors was investigated. The results will be described below.

[0094] The manufactured display device has the pixel circuit shown in Fig. 3 in the display area. The drive transistor DRT and output transistor BCT of display device A have a channel width W of 3 μm and a channel length L of 3 μm. The write transistor SST and reset transistor RST also have a channel width W of 3 μm and a channel length L of 3 μm.

[0095] The drive transistor DRT and output transistor BCT of the display device B have a channel width W of 4.5 μm and a channel length L of 3 μm. The write transistor SST and reset transistor RST have a channel width W of 3 μm and a channel length L of 3 μm.

[0096] The channel width W of the drive transistor DRT and the output transistor BCT of the display device C is 6 μm, and the channel length L is 3 μm. The channel width W of the write transistor SST and the reset transistor RST is 3 μm, and the channel length L is 3 μm.

[0097] A driving voltage was applied to the fabricated display devices A to C, a gray test signal was input, and the panels were continuously lit for 500 hours in an environment of 70°C. Next, the Id-Vg characteristics after driving were measured for the driving transistor DRT, the writing transistor SST, and the output transistor BCT of each of the display devices A to C. Figure 10 shows the relationship between the driving transistor DRT, the writing transistor SST, the output transistor BCT, and the threshold voltage Vth [V] of each of the display devices A to C and the display device INI. The horizontal axis represents the driving transistor DRT, the writing transistor SST, and the output transistor BCT of each of the display devices A to C and the display device INI, and the vertical axis represents the threshold voltage Vth [V]. Display device INI was fabricated under the same conditions as display device A and is equivalent to the state of display device A before the 500 hours of continuous lighting.

[0098] Next, the display devices A to C were disassembled, and the Id-Vd characteristics of the transistors were measured to determine the threshold voltages.

[0099] In display device A, where the W / L ratio of each transistor was 1, a tendency for the threshold voltages of the drive transistor DRT and output transistor BCT to drift positively was observed. Furthermore, in display devices B and C, where the W / L ratio of the drive transistor DRT and output transistor BCT was 1.5 or more, it was suggested that the threshold voltages of the drive transistor DRT and output transistor BCT were more inhibited from drifting positively than the threshold voltages of the drive transistor DRT and output transistor BCT of display device A.

[0100] FIG. 11 is a graph summarizing the current reduction amounts after driving display devices A to C. The horizontal axis represents display devices A to C, and the vertical axis represents the current reduction amount [%]. As shown in FIG. 11, in the case of display device A, in which the W / L ratio of the output transistor BCT and the drive transistor DRT connected in series between the light-emitting element OLED and the drive power line is 1, the current reduction amount was found to be 46%. In contrast, in the case of display device B, in which the W / L ratio of the output transistor BCT and the drive transistor DRT is 1.5 or more, the current reduction amount was found to be 15.7%. Furthermore, in the case of display device C, in which the W / L ratio of the output transistor BCT and the drive transistor DRT is 2.0 or more, the current reduction amount was found to be 8.5%. As shown in FIG. 11, display devices B and C were shown to be able to significantly reduce the current reduction amount compared to display device A.

[0101] Therefore, it was shown that when the W / L ratio of the output transistor BCT and the driving transistor DRT connected in series between the light-emitting element OLED and the driving power line is 1.5 or more, a display device that is less likely to deteriorate even when driven for a long period of time can be provided.

[0102] The scope of the present invention also includes any display device in which a person skilled in the art appropriately adds or removes components or modifies the design, or adds or omits processes or modifies conditions, based on the display devices described as embodiments and examples of the present invention, as long as the gist of the present invention is maintained. Furthermore, the above-described embodiments can be combined with each other to the extent that no technical contradiction occurs.

[0103] Furthermore, even if there are other effects and advantages different from those brought about by the above-described embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention.

[0104] It is understood that within the scope of the present invention, those skilled in the art may make various modifications and alterations, and that these modifications and alterations also fall within the scope of the present invention. For example, to the above-described embodiments, those skilled in the art may appropriately add, delete, or modify components, or add, omit, or change conditions of steps, and these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention. [Explanation of symbols]

[0105] 100: display device, 101: substrate, 102: display region, 103: pixel, 103A: pixel, 104: gate drive circuit, 105: driver IC, 106: terminal, 107: terminal portion, 108: flexible printed circuit, 109: peripheral region, 110: touch sensor, 202: insulating film, 206: insulating film, 208-1 to 208-5: oxide semiconductor layer, 208a: channel region, 208b, 208c: impurity regions, 208d: channel region, 208e, 208f: impurities Regions, 211-1 to 211-10: contact holes, 212: insulating film, 214-1 to 214-5: conductive layers, 216: insulating film, 218: conductive layer, 218-1 to 218-6: conductive layers, 222: planarizing film, 226: pixel electrode, 228: insulating layer, 230: light-emitting element, 232: organic layer, 233: inorganic insulating layer, 234: common electrode, 236: inorganic insulating layer, 238: organic insulating layer, 240: sealing film, 242: inorganic insulating layer, 310 to 350: transistors, 360: storage capacitor

Claims

1. A light-emitting element; a first transistor connected in series between the light emitting element and a driving power line; a third transistor electrically connected to the gate of the first transistor; Including, a ratio (W1 / L1 ratio) of a channel width W1 to a channel length L1 of the first transistor is greater than a ratio (W3 / L3 ratio) of a channel width W3 to a channel length L3 of the third transistor.

2. the W1 / L1 ratio of the first transistor is 1.5 or greater; The display device of claim 1 , wherein the third transistor has a W3 / L3 ratio of less than 1.

5.

3. The display device according to claim 1 , further comprising a storage capacitor connected between the gate of the first transistor and the drain of the first transistor.

4. a fourth transistor connected in parallel between the drain of the first transistor and the light-emitting element; 4. The display device according to claim 3, wherein a ratio (W1 / L1 ratio) of a channel width W1 to a channel length L1 of the first transistor is greater than a ratio (W4 / L4 ratio) of a channel width W4 to a channel length L4 of the fourth transistor.

5. The display device of claim 4 , wherein the W3 / L3 ratio of the third transistor is the same as the W4 / L4 ratio of the fourth transistor.

6. 5. The display device according to claim 4, wherein a channel length L1 of the first transistor is different from a channel length L3 of the third transistor and a channel length L4 of the fourth transistor.

7. one terminal of the storage capacitor is connected to the drain of the third transistor; The display device according to claim 4 , wherein the other terminal of the storage capacitor is connected to the drain of the fourth transistor.

8. a second transistor connected in series between the drive power supply line and the first transistor; 8. The display device according to claim 7, wherein a ratio (W2 / L2 ratio) of a channel width W2 to a channel length L2 of the second transistor is greater than a ratio (W3 / L3 ratio) of a channel width W3 to a channel length L3 of the third transistor and a ratio (W4 / L4 ratio) of a channel width W4 to a channel length L4 of the fourth transistor.

9. a W1 / L1 ratio of the first transistor and a W2 / L2 ratio of the second transistor are 1.5 or more; The display device of claim 8 , wherein the W3 / L3 ratio of the third transistor and the W4 / L4 ratio of the fourth transistor are less than 1.

5.

10. a fifth transistor electrically connected to the gate of the first transistor; 9. The display device according to claim 8, wherein a W1 / L1 ratio of the first transistor is greater than a ratio (W5 / L5 ratio) of a channel width W5 to a channel length L5 of the fifth transistor.

11. a W1 / L1 ratio of the first transistor and a W2 / L2 ratio of the second transistor are 1.5 or more; The display device of claim 10 , wherein the fifth transistor has a W5 / L5 ratio of less than 1.5.

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