Video recording system and information processing device

Abstract

This prevents a decrease in the video data recording rate and slows down the operation of the recording device. [Solution] A video recording system (100) includes a storage (3) having a flash memory (33), an information processing device (1), and a configuration unit (5). The configuration unit (5) determines an access size that is an integer multiple of the size of an erase block. The configuration unit (5) assigns a time slot to each of multiple video channels based on the access size. A CPU (11) of the information processing device (1) buffers video data acquired via each video channel in a buffer area assigned to each video channel for the access size. The CPU (11) records the buffered data buffered in each buffer area in the flash memory (33) in the time slot assigned to the video channel corresponding to each buffer area.

Description

[Technical Field]

[0001] The present disclosure relates to a video recording system that stores multiple pieces of video data in a storage device configured with NAND elements, and an information processing device. [Background technology]

[0002] A system is known that inputs video data output by a video output device such as a camera and records the video data in a recording device configured with NAND elements. Recording devices configured with NAND elements are known, for example, as solid-state drives (SSDs). The video data recorded in the recording device is used, for example, for future playback or video editing.

[0003] When recording data such as video data in storage, it is known to reduce the amount of data collected if the total rate of collected data exceeds the throughput parameters of the network infrastructure (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2020-530159 Summary of the Invention [Problem to be solved by the invention]

[0005] Currently, studies are being conducted on recording devices that consist of NAND elements to store multiple pieces of video data output from multiple video output devices. When multiple pieces of video data are recorded on a recording device without any control, the multiple pieces of video data may be recorded on the recording device simultaneously. When attempting to simultaneously record multiple pieces of video data on a recording device, a large amount of video data is transmitted over the data line connected to the recording device, which may result in a decrease in the recording rate of the video data.

[0006] Furthermore, there is a possibility that video data may be recorded without taking into consideration the characteristics of the recording device made up of NAND elements. Specifically, video devices made up of NAND elements need to erase data in units called "erase blocks," but video data may not be recorded in erase block units in the recording device. In other words, video data may only be recorded up to the middle of an erase block.

[0007] When video data that has only been recorded partway through an erase block is erased, other data recorded in that erase block must be moved to another block and then re-recorded (garbage collection processing).If this processing occurs frequently, problems such as slow operation of the recording device may occur.

[0008] An object of the present disclosure is to prevent a decrease in the recording rate of video data and a slowdown in the operation of the recording device when multiple pieces of video data are stored in a storage device configured with NAND elements. [Means for solving the problem]

[0009] The video recording system of the present disclosure includes a storage, an information processing device, and a configuration unit. The storage has a nonvolatile memory unit that writes in page units and erases in erase block units consisting of multiple pages. The information processing device records multiple pieces of video data acquired via multiple video channels in the nonvolatile memory unit. The configuration unit sets time slots. The information processing device includes a temporary storage unit and a control unit. The temporary storage unit has multiple buffer areas allocated to each of the multiple video channels. The control unit controls the recording of the multiple pieces of video data in the nonvolatile memory unit.

[0010] In the above video recording system, the configuration unit determines an access size. The access size is an integer multiple of the size of an erase block. The configuration unit assigns a time slot to each of multiple video channels based on the access size. The control unit buffers video data acquired via each video channel in a buffer area assigned to each video channel for the access size. The control unit also records the buffered data buffered in each buffer area in the nonvolatile memory unit in the time slot assigned to the video channel corresponding to each buffer area. [Effects of the Invention]

[0011] The video recording system disclosed herein does not simultaneously record multiple pieces of video data in storage. In the video recording system, video data from a corresponding video channel is buffered in each of multiple buffer areas by an amount equal to an integer multiple of an erase block, which is the storage's erase unit. In the video recording system, the buffered data buffered in each buffer area is recorded in the storage in a time slot assigned to the video channel corresponding to that buffer area. In other words, multiple pieces of video data (buffered data) are recorded in the storage in individually assigned time slots. This allows the transmission of a single piece of video data (buffered data) to monopolize the data transmission bandwidth of the data line connecting the information processing device and the storage, thereby preventing a decrease in the video data recording rate.

[0012] In addition, in the video recording system of the present disclosure, the size of buffered data recorded in one time slot is set to an integer multiple of the erase block size, which is the unit of data erasure in the storage. This makes it possible to prevent the occurrence of erase blocks in which video data is only partially recorded. As a result, the occurrence of garbage collection processes is reduced, and a decrease in the operating speed of the storage is suppressed. Furthermore, by recording buffered data in one time slot that is an integer multiple of the erase block and larger, fragmentation of video data recorded in the storage can be suppressed. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram showing the configuration of a video recording system. [Figure 2] FIG. 2 is a diagram illustrating a configuration of the information processing device. [Figure 3] FIG. 3 is a diagram illustrating the configuration of storage. [Figure 4] FIG. 4 is a diagram showing the configuration of the recording area. [Figure 5] FIG. 5 is a diagram showing signal transmission and reception in a video recording system. [Figure 6] FIG. 6 is a flowchart showing the operation of the information processing device in the video recording system. [Figure 7] FIG. 7 is a diagram showing a schematic diagram of recording of video data. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of already well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0015] In this disclosure, "video data" refers to data including video data, audio data, and metadata, data including only video data, and data including still image data.

[0016] [1. First embodiment] [1-1.Video Recording System] A video recording system 100 according to the present disclosure will be described below with reference to the drawings. The video recording system 100 is a system that records video data acquired via multiple video channels CH1, CH2, ... CHn in a storage 3 configured with NAND elements. The video data recorded in the storage 3 is used, for example, for future playback and editing. Editing video data includes, for example, generating new video data by inserting a specific portion of other video data into the video data.

[0017] The configuration of the video recording system 100 will be described below with reference to Fig. 1. Fig. 1 is a diagram showing the configuration of the video recording system 100. The video recording system 100 includes an information processing device 1 and a storage 3.

[0018] The information processing device 1 has multiple video channels CH1, CH2, ... CHn. In this embodiment, when there is no need to distinguish between the individual video channels CH1, CH2, ... CHn, they are simply referred to as video channels CH. Each video channel CH is an interface for connecting a video processing device 2. In other words, the information processing device 1 is connected to multiple video processing devices 2 via multiple video channels CH.

[0019] The video processing device 2 is a device that acquires video and audio data, converts it into electrical signals, and outputs it externally as video data. The video processing device 2 is, for example, a video capture device equipped with a camera that captures a predetermined video, a microphone that captures the audio of the predetermined video, and the like. Alternatively, the video processing device 2 may be a media server that records a large number of videos. The video output from the video processing device 2 is, for example, high-quality video such as uncompressed 4K video. As shown in FIG. 2, the video processing device 2 has an output interface 21 that connects the information processing device 1 and the video processing device 2. The output interface 21 can be connected to a video channel CH of the information processing device 1.

[0020] The video channel CH may be connected to a video playback device that acquires video data from the information processing device 1 and displays it on a display device (for example, a display), or a device that performs an operation to edit the video data.

[0021] The information processing device 1 executes various information processes on the video data input from the video processing device 2. Specifically, for example, the information processing device 1 can execute a process of converting video data into compressed data. The information processing device 1 can also output video data in uncompressed format to an external device. The information processing device 1 can edit the video data in accordance with user operations. Furthermore, if the external device connected to the information processing device 1 is a video display device, the information processing device 1 can also function as a video playback device.

[0022] The information processing device 1 is connected to a storage 3. The information processing device 1 records video data input from the video processing device 2, video data converted into a compressed format, edited video data, etc. in the storage 3. The information processing device 1 also outputs video data acquired from the storage 3 to a video playback device or the like.

[0023] The information processing device 1 buffers multiple pieces of video data from multiple video processing devices 2 in buffer areas BF1, BF2, ..., BFn allocated to each video channel CH1, CH2, ..., CHn, for a size that is an integer multiple of the erase block BL of the storage 3. In this embodiment, when the individual buffer areas BF1, BF2, ..., BFn are not distinguished, they are simply referred to as buffer areas BF. The video data buffered in the buffer areas BF are called "buffered data." The information processing device 1 records the buffered data buffered in the buffer areas BF allocated to each video channel CH in the storage 3 in the time slot allocated to that video channel CH.

[0024] Although the video recording system 100 of this embodiment is provided with one information processing device 1, the present invention is not limited to this. The number of information processing devices 1 provided in the video recording system 100 can be any number.

[0025] The storage 3 records the video data received from the information processing device 1 in accordance with a command from the information processing device 1. The storage 3 also reads out designated video data in accordance with a command from the information processing device 1. As will be described later, the storage 3 is a recording device configured with NAND elements. The storage 3 is, for example, a solid state drive (SSD). In the video recording system 100 of this embodiment, one storage 3 is provided, but two or more storages 3 may be provided. The number of storages 3 provided in the video recording system 100 can be any number.

[0026] The video recording system 100 includes a configuration unit 5. The configuration unit 5 is connected to the information processing device 1 and an arbitration unit 6, which will be described later. The configuration unit 5 performs settings related to time slots. Specifically, the configuration unit 5 determines the size of video data that can be recorded or transmitted in one time slot (hereinafter referred to as access size) based on the size of the erase block BL of the storage 3, and notifies the information processing device 1 and the arbitration unit 6 of this size. The configuration unit 5 individually assigns time slots to each of multiple video channels CH. In other words, a time slot means the time allowed to record video data acquired from the assigned video channel CH, or the time allowed to transmit video data to the assigned video channel CH. The configuration unit 5 notifies the information processing device 1 and the arbitration unit 6 of the settings related to time slots.

[0027] The component 5 is, for example, hardware configured by circuits that realize the above functions. The component 5 may be a computer system that includes a CPU, a storage device, various interfaces, etc. and realizes the above functions. The component 5 may realize some or all of the above functions by software. The functions of the component 5 may be realized by the information processing device 1.

[0028] The video recording system 100 includes an arbitration unit 6. The arbitration unit 6 is connected to the information processing device 1 and the configuration unit 5. When there is a request from the information processing device 1 to access the storage 3, the arbitration unit 6 determines whether or not to permit the information processing device 1 to access the storage 3, and notifies the information processing device 1 of the result of the determination.

[0029] The arbitration unit 6 is, for example, hardware configured by circuits that realize the above functions. The arbitration unit 6 may be a computer system that includes a CPU, a storage device, various interfaces, etc. and realizes the above functions. The arbitration unit 6 may realize some or all of the above functions by software. The functions of the arbitration unit 6 may be realized by the information processing device 1.

[0030] [1-2. Information processing device] The configuration of the information processing device 1 will be described with reference to Fig. 2. Fig. 2 is a diagram showing the configuration of the information processing device 1. The information processing device 1 has a CPU (controller) 11, a RAM (temporary storage) 12, a storage device 13, a video interface 14, a storage interface 15, and an interface 16.

[0031] The CPU 11 executes various processes in the information processing device 1. Specifically, the CPU 11 executes information processes such as video data compression, information processing related to video data editing, and video data analysis. The CPU 11 executes the above processes by executing instructions indicated in a program stored in the storage device 13. Note that some of the processes in the information processing device 1 may be realized by hardware implemented separately from the CPU 11 or by an external device. The CPU 11 generates commands for executing various processes.

[0032] The RAM 12 is a storage area that temporarily stores commands, video data, etc. generated by the CPU 11. In the RAM 12, buffer areas BF1, BF2, .... BFn are allocated to each of the video channels CH1, CH2, .... CHn. The buffer areas BF1, BF2, .... BFn are temporary storage areas that buffer the video data acquired via the corresponding video channel CH1, CH2, .... CHn. The size of one buffer area BF is set to a size that provides a certain margin for the access size.

[0033] The storage device 13 is composed of a ROM, a hard disk (HDD), a solid state drive (SSD), etc. The storage device 13 stores programs executed by the CPU 11, settings related to the processing of the information processing device 1, parameters used for the processing, etc.

[0034] The video interface 14 connects the information processing device 1 and the video processing device 2. As shown in FIG. 2, the video interface 14 is provided with a plurality of connection terminals. One of the plurality of connection terminals of the video interface 14 corresponds to one video channel CH. The video processing device 2 can be connected to the connection terminal. One video processing device 2 may be connected to only one connection terminal (i.e., one video channel CH) or to multiple connection terminals (i.e., multiple video channels CH). The video interface 14 is an interface for connecting video-related devices, such as an interface conforming to the Serial Digital Interface (SDI) standard.

[0035] Alternatively, the video interface 14 may be a network interface, in which case transmission according to the ST2110 standard of the SMPTE standardization organization, for example, may be used.

[0036] The storage interface 15 connects the information processing device 1 and the storage 3. The storage interface 15 connects the information processing device 1 and the storage 3 via a direct transfer path. The storage interface 15 is, for example, a PCIe interface that complies with the PCI express standard of the PCI-SIG standard. This allows the information processing device 1 and the storage 3 to send and receive data at high speed using a protocol dedicated to non-volatile memory (NVMe (Non-Volatile Memory Express)) that uses a PCI-Express bus.

[0037] With NVMe, the controller acquires data from the NAND memory using the NAND protocol, converts it to PCIe protocol, and transfers it to the host. In contrast, with conventional SATA (Serial ATA), the DMA controller that transfers data directly to the host converts data from the NAND memory to the SATA protocol, acquires it, and then converts that data to PCIe protocol before transferring it to the host. In other words, NVMe processing directly converts data from the NAND protocol to the PCIe protocol, resulting in fast data transfer speeds.

[0038] The interface 16 is an interface for connecting the information processing device 1 to an external device. The interface 16 is a network interface such as a Gigabit Ethernet (registered trademark) interface that connects the information processing device 1 to an external device via a network such as a WAN or LAN. When the configuration unit 5 and the arbitration unit 6 are configured outside the information processing device 1, the configuration unit 5 and the arbitration unit 6 are connected to the interface 16.

[0039] The storage interface 15 and / or the interface 16 may be configured to enable direct transmission and reception of data between the RAM 12 of the information processing device 1 and a storage device of an external device by remote direct memory access (RDMA), thereby enabling high-speed transmission and reception of data between the information processing device 1 and the external device.

[0040] [1-3.Storage] The configuration of the storage 3 will be described with reference to Fig. 3. Fig. 3 is a diagram showing the configuration of the storage 3. The storage 3 has an access port 31, a flash memory (non-volatile memory unit) 33, a controller 35, and a storage unit 37. The access port 31 is an interface that connects the storage 3 to other devices. The information processing device 1 is connected to the access port 31.

[0041] The flash memory 33 is composed of a plurality of NAND elements. For example, a table is recorded in the flash memory 33, which associates addresses (logical addresses) designated by an external device with addresses (physical addresses) of erase blocks BL corresponding to the logical addresses. As shown in Fig. 4, the flash memory 33 has a recording area RA for recording video. The recording area RA is divided into a plurality of erase blocks BL. Fig. 4 is a diagram showing the configuration of the recording area RA.

[0042] An erase block BL is a unit of data erasure in the flash memory 33. An erase block BL is further divided into a plurality of pages PA. A page PA is a unit of data recording. When data in an erase block BL is erased in the flash memory 33, a process (garbage collection) is executed in which the data contained in this erase block BL is moved to another erase block BL and then erased. As a result, the erase block BL from which the data has been erased becomes a "free block" to which data can be written.

[0043] The controller 35 executes control related to the storage 3. In particular, the controller 35 controls the recording of data to the flash memory 33 and the reading of data from the flash memory 33. The controller 35 also executes other processes required for a solid state drive, such as garbage collection and wear leveling. The controller 35 executes the above processes by executing a program stored in the storage unit 37. The controller 35 may also implement the above processes using its own hardware.

[0044] The storage unit 37 is provided as a memory separate from the flash memory 33, or is part of the recording area RA. The storage unit 37 stores various parameters and the like related to the control of the storage 3. The storage unit 37 stores, for example, information related to the life of the flash memory 33, the size of the page PA, the size of the erase block BL, the number of times data is recorded in each erase block BL, parameters for executing various processes, and the like.

[0045] [1-4. Operation of the video recording system] 5 and 6, the operation of the video recording system 100 will be described. Fig. 5 is a diagram showing signal transmission and reception in the video recording system 100. Fig. 6 is a flowchart showing the operation of the information processing device 1 in the video recording system 100.

[0046] First, the user instructs the configuration unit 5 on the mode (recording mode, playback mode) to be used when recording / playing back video data in the video recording system 100. The recording mode includes the recording rate of the video data (the amount of video data recorded per unit time), and the playback mode includes the playback rate of the video data (the amount of video data read out per unit time). The recording mode may also include the video characteristics of the video data (compressed, uncompressed, etc.). These modes may be set individually for each video channel CH, or the same mode may be set for all video channels CH. In this embodiment, for the sake of convenience, it is assumed that a recording mode is set for all video channels CH1, CH2, ..., CHn.

[0047] Next, the configuration unit 5 requests information about the size of pages PA and the size of erase blocks BL stored in the flash memory 33 of the storage 3 from the storage 3 (step S101 in FIG. 5). Upon receiving this request, the controller 35 of the storage 3 reads information about the size of pages PA and the size of erase blocks BL from the memory unit 37 and transmits this information to the configuration unit 5 (step S102 in FIG. 5).

[0048] Thereafter, the configuration unit 5 determines the access size based on the size of the page PA, the size of the erase block BL, etc. received from the storage 3. The access size can be determined to be an integer multiple of the size of the erase block BL, and to a size that suppresses fragmentation of the video data. The configuration unit 5 may determine the access size for each video channel CH based on the recording rate of the video data, or may determine one access size that is applied to all video channels CH.

[0049] The configuration unit 5 also sets the time slots to be allocated to each video channel CH. Based on the determined access size, the recording mode designated by the user, etc., the configuration unit 5 sets the time length of the time slots and the cycle for allocating the time slots to each video channel CH.

[0050] Specifically, the configuration unit 5 calculates the processing time for processing video data acquired from a specific video channel CHk based on the data transfer rate between the information processing device 1 and the storage 3 and the access size of the video channel CHk, and determines the length of the time slot to be allocated to the video channel CHk. The configuration unit 5 may calculate the processing time by subtracting a predetermined margin from the data transfer rate between the information processing device 1 and the storage 3. Furthermore, the configuration unit 5 calculates the processing cycle required for the video data based on the recording rate of the video data acquired from the specific video channel CHk and the access size of the video channel CHk, and determines the cycle to allocate the time slot.

[0051] For example, if the data transfer rate between the information processing device 1 and the storage 3 is a Mbps and the access size of a particular video channel CHk is determined to be b MB (8*b Mbit), the duration of the time slot to be allocated to that video channel CHk can be determined to be 8*b / a seconds. Also, if the recording rate of video data acquired from a particular video channel CHk is c Mbps, it can be determined that c / (8*b) time slots should be allocated to that video channel CHk per second.

[0052] After completing the time slot setting, the configuration unit 5 transmits the time slot setting information to the arbitration unit 6 (step S103 in FIG. 5). The arbitration unit 6, which has received the time slot setting information, determines, based on the time slot setting, when each video channel CH should be permitted to access the storage 3 (record video data in the storage 3).

[0053] Furthermore, configuration unit 5 transmits time slot setting information to information processing device 1 (step S104 in FIG. 5). CPU 11 of information processing device 1 executes a process of receiving the time slot setting information transmitted from configuration unit 5 (step S1 in FIG. 6).

[0054] Thereafter, the CPU 11 configures the information processing device 1 based on the received time slot configuration. Specifically, the CPU 11 determines the reservation sizes of buffer areas BF1, BF2, ..., BFn to be allocated to each of the video channels CH1, CH2, ..., CHn based on the time slot configuration, and reserves the buffer areas BF1, BF2, ..., BFn in the RAM 12 (step S2 in FIG. 6). The reservation size of each buffer area BF can be determined as the access size determined for the video channel CH to which the buffer area BF is allocated, plus a predetermined margin.

[0055] After the buffer area BF is secured, when a user issues a command to output video data from the plurality of video processing devices 2, the plurality of video data are output from the plurality of video processing devices 2 (step S105 in FIG. 5). The plurality of video data output from the plurality of video processing devices 2 are recorded in the storage 3. The operation of recording the plurality of video data in the storage 3 will be described in detail below.

[0056] The following describes the operation when recording multiple pieces of video data in the storage 3 within a predetermined time. The video recording system 100 repeatedly executes the operation described below as long as there is video data to be recorded in the storage 3.

[0057] The CPU 11 acquires a plurality of pieces of video data output from a plurality of video processing devices 2 via a plurality of video channels CH (step S3 in FIG. 6). The CPU 11 buffers the video data acquired via each video channel CH in a buffer area BF allocated to the video channel CH (step S4 in FIG. 6).

[0058] While buffering each of the multiple video data in the corresponding buffer area BF, CPU 11 determines whether a sufficient amount of video data has been buffered in each buffer area BF (step S5 in FIG. 6). For example, when recording video data acquired via video channel CHk, CPU 11 determines whether a sufficient amount of video data has been buffered in buffer area BFk allocated to that video channel CHk. Note that k starts from 1 and is increased by 1 up to n by repeating the following steps S5 to S10.

[0059] "The amount of video data buffered in the buffer area BF is sufficient" means that the buffered video data (buffered data) has the access size determined for the video channel CH assigned to the buffer area BF.

[0060] If a sufficient amount of video data is not buffered in the buffer area BFk allocated to the video channel CHk ("No" in step S5 of Figure 6), the video data recording operation returns to step S4 above, and the buffering of video data in the buffer area BFk continues.

[0061] On the other hand, if a sufficient amount of video data has been buffered in the buffer area BFk allocated to the video channel CHk ("Yes" in step S5 of FIG. 6), the CPU 11 requests the arbitration unit 6 to access the storage 3 for the video channel CHk in order to record the buffered data buffered in the buffer area BFk in the storage 3 (step S106 of FIG. 5, step S6 of FIG. 6).

[0062] Upon receiving the access request, the arbitration unit 6 determines, based on the time slot setting information, whether or not to allocate a time slot for accessing the storage 3 to the video channel CHk. Based on the time slot setting information, the arbitration unit 6 determines whether or not the current time (the time when the access request is received) is a time when a time slot can be allocated to the video channel CHk. Specifically, based on the time slot setting information, the arbitration unit 6 determines whether or not the current time (the time when the access request is received) is the start time of the time slot allocated to the video channel CHk. If it is determined that the time is a time when a time slot can be allocated, the arbitration unit 6 transmits an access permission to the information processing device 1 in response to the access request of step S6 (step S107 in FIG. 5).

[0063] If no access permission is received from the arbitration unit 6 (“No” in step S7 in FIG. 6), the CPU 11 of the information processing device 1 waits until access permission is received.

[0064] On the other hand, if access permission is received from the arbitration unit 6 ("Yes" in step S7 of FIG. 6), the CPU 11 determines that a time slot for accessing the storage 3 and recording video data has been allocated to the video channel CHk. In this case, the CPU 11 transmits the buffered data buffered in the buffer area BFk to the storage 3 in the time slot allocated to the video channel CHk (step S108 of FIG. 5, step S8 of FIG. 6).

[0065] The controller 35 of the storage 3, which has received the buffered data, records the received buffered data in consecutive pages PA of the flash memory 33. At this time, the controller 35 determines the erase blocks BL in which to record the buffered data based on the number of times data has been recorded for each erase block in the flash memory 33. For example, the controller 35 determines multiple erase blocks BL with similar numbers of times data has been recorded as the erase blocks BL in which to record the buffered data. As described above, the buffered data has a size that is an integer multiple of the size of the erase blocks BL. Therefore, the buffered data is recorded across a predetermined number of consecutive erase blocks BL in the flash memory 33. In other words, the number of erase blocks BL in which data is only partially recorded can be reduced. As a result, the occurrence of garbage collection processing in the storage 3 can be suppressed. Furthermore, by recording relatively large buffered data (video data) in consecutive pages PA (consecutive erase blocks BL), fragmentation of the video data can be suppressed.

[0066] After recording the video data (buffering data) of one video channel CHk in the storage 3 in the time slot assigned to that video channel CHk, the CPU 11 of the information processing device 1 determines whether there is a video channel CH for which video data has not been recorded, i.e., whether the video data of all video channels CH has been recorded (whether k has increased from 1 to n) (step S9 of Figure 6).

[0067] If there is a video channel CH on which video data has not been recorded, i.e., if k is a value smaller than n ("No" in step S9 of FIG. 6), k is incremented by 1 (step S10 of FIG. 6), and steps S106 to S108 of FIG. 5 and steps S5 to S10 of FIG. 6 are executed for the next video channel CHk+1.

[0068] On the other hand, if there is no video channel CH on which video data has not been recorded, that is, if k becomes n (k=n) ("Yes" in step S9 of FIG. 6), it is determined that the video data acquired via all video channels CH has been recorded in the storage 3. Thereafter, as long as video data is being output from a plurality of video processing devices 2, steps S105 to S108 of FIG. 5 and steps S3 to S10 of FIG. 6 are repeatedly executed.

[0069] As a result, in the video recording system 100, as shown in Fig. 7, the video data (buffered data) of the video channels CH is recorded in the storage 3 in sequence in the time slots allocated to each video channel CH. In this way, the video data of all the video channels CH is recorded in the storage 3 within a predetermined time period consisting of multiple time slots. In the video recording system 100, this operation is repeated at a predetermined cycle as long as video data is output from the video processing device 2. This cycle is determined based on, for example, the total time length of the multiple time slots, the time at which the information processing device 1 is permitted to access the storage 3, and so on. Fig. 7 is a diagram schematically showing the recording of video data.

[0070] 2. Other Embodiments Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible within the scope of the gist of the invention. In particular, the multiple embodiments and modifications described in this specification can be arbitrarily combined as necessary.

[0071] (A) The order and content of each process in the diagrams and flowcharts showing signal transmission and reception described above may be changed as appropriate without departing from the spirit of the present invention. Furthermore, the entities that execute each process (information processing device 1, video processing device 2, configuration unit 5, arbitration unit 6, storage 3) may also be changed as appropriate without departing from the spirit of the present invention.

[0072] (B) The information processing device 1 may include the configuration and / or functions of the component 5 and / or arbitration unit 6 described above.

[0073] (C) The configuration unit 5 calculates the processing time for processing video data acquired from a specific video channel CH based on the data transfer rate between the information processing device 1 and the storage 3 and the access size of the specific video channel CH, and determines this as the time length of the time slot. However, the configuration unit 5 may calculate the length by adding a predetermined time to the above-mentioned processing time, and determine this as the time length of the time slot. In other words, the time length of the time slot may include a margin.

[0074] (D) The arbitration unit 6 determines whether a time slot can be allocated by determining whether the current time (the timing at which the access request is received) is the start time of the time slot allocated to video channel CHk based on the time slot setting information. However, the arbitration unit 6 may also determine whether a time slot can be allocated to video channel CHk based on the time slot setting information, by determining whether buffered data corresponding to video channel CHk-1, to which the previous time slot is allocated, has already been transmitted to the storage 3. This makes it possible to aggregate free time slots in the latter half of a predetermined period of time consisting of multiple time slots. As a result, free time can be used efficiently.

[0075] (E) The video recording system 100 may have multiple flash memories 33. In this case, the controller 35 may determine the flash memory 33 in which to record the buffered data based on the lifespan of the flash memories 33. For example, the controller 35 may determine multiple flash memories 33 that are close to reaching the end of their lifespan as the flash memories 33 in which to record the buffered data. This allows the flash memories 33 to be used efficiently.

[0076] (F) An external device may be connected to the information processing device 1 via the interface 16. When an external device requests access to the storage 3, the configuration unit 5 may determine whether there is available time in the time slot. In the example shown in FIG. 6, if there is no video channel CH on which video data is not recorded ("Yes" in step S9 in FIG. 6), the configuration unit 5 may compare the current time with the start time of the next time slot to determine whether there is available time in the time slot. If the configuration unit 5 determines that there is available time, it may allocate the available time to access from the external device.

[0077] (G) The configuration unit 5 may determine the access size for each video channel CH based on the size of the erase block BL of the storage 3, the recording rate of the video data, and the video characteristics of the video data. For example, if the video data to be recorded is in a compressed format, the access size may be calculated based on the size of the video data after compression.

[0078] (H) The configuration unit 5 may calculate the processing cycle required for the video data based on the recording rate, video characteristics, and access size of the video data, and determine the cycle for allocating time slots. For example, if the video data to be recorded is in a compressed format, the cycle for allocating time slots may be calculated based on the size of the compressed video data.

[0079] 3. Features of the Disclosure (1) A video recording system 100 according to the present disclosure includes a storage 3, an information processing device 1, and a configuration unit 5. The storage 3 includes a flash memory 33 that writes data in units of pages PA and erases data in units of erase blocks BL each consisting of a plurality of pages PA. The information processing device 1 records a plurality of pieces of video data acquired through a plurality of video channels CH in the flash memory 33. The configuration unit 5 sets time slots. The information processing device 1 includes a RAM 12 and a CPU 11. The RAM 12 includes a plurality of buffer areas BF1, BF2, ..., BFn that are allocated to the plurality of video channels CH1, CH2, ..., CHn, respectively. The CPU 11 controls the recording of the plurality of pieces of video data in the flash memory 33.

[0080] In the above-described video recording system 100, the configuration unit 5 determines an access size. The access size is an integer multiple of the size of the erase block BL. The configuration unit 5 allocates a time slot to each of the multiple video channels CH based on the access size. The CPU 11 buffers the video data acquired via each video channel CH in buffer areas BF1, BF2, ..., BFn allocated to each video channel CH1, CH2, ..., CHn, by the access size. The CPU 11 also records the buffered data buffered in each buffer area BF1, BF2, ..., BFn in the flash memory 33 in the time slot allocated to the video channel CH1, CH2, ..., CHn corresponding to each buffer area BF1, BF2, ..., BFn.

[0081] In the video recording system 100 described above, multiple pieces of video data are not simultaneously recorded in the storage 3. In the video recording system 100, video data from a corresponding video channel CH is buffered in each of multiple buffer areas BF by an amount equal to an integer multiple of an erase block BL, which is an erasure unit in the storage 3. In the video recording system 100, the buffered data buffered in each buffer area BF is recorded in the storage 3 in a time slot assigned to the video channel CH corresponding to that buffer area BF. In other words, multiple pieces of video data (buffered data) are recorded in the storage 3 in individually assigned time slots. This allows the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3 to be monopolized by the transmission of one piece of video data (buffered data), thereby preventing a decrease in the recording rate of the video data.

[0082] Furthermore, in the video recording system 100, the size of the buffered data recorded in one time slot is set to an integer multiple of the erase block size, which is the unit of data erasure in the storage 3. This makes it possible to prevent the occurrence of erase blocks BL in which video data is only partially recorded. As a result, the occurrence of garbage collection processes is reduced, and a decrease in the operating speed of the storage 3 is suppressed. Furthermore, by recording buffered data that is an integer multiple of the erase block BL and is large in size in the storage 3 in one time slot, it is possible to prevent fragmentation of the video data recorded in the storage 3.

[0083] (2) In the video recording system 100 described above in (1), the configuration unit 5 may further allocate time slots to the video channels CH corresponding to the video data based on the recording rate of the video data. This allows for efficient use of the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3.

[0084] (3) In the video recording system 100 described in (2) above, the configuration unit 5 may further allocate time slots to video channels CH corresponding to video data based on the video characteristics of the video data. This allows for efficient use of the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3.

[0085] (4) In the video recording system 100 of any one of (1) to (3) above, the configuration unit 5 may set the time length of a time slot to a predetermined time added to the processing time based on the data transfer rate and the access size between the information processing device 1 and the storage 3. By adding a margin to the time of the time slot, it is possible to absorb fluctuations in the transmission of video data due to garbage collection processing, changes in the transmission environment, etc.

[0086] (5) The video recording system 100 of any one of (1) to (4) above may further include an arbitration unit 6 that arbitrates access from the CPU 11 to the flash memory 33. The arbitration unit 6 may determine whether to permit access from the CPU 11 to the flash memory 33 based on the time slot setting set by the configuration unit 5. This makes it possible to arbitrate the transmission of video data (buffered data).

[0087] (6) In the video recording system 100 of any one of (1) to (5) above, when an external device requests access to the storage 3, the configuration unit 5 may determine whether there is available time in the time slot. If the configuration unit 5 determines that there is available time, it may allocate the available time to access from the external device. This makes it possible to respond to the access request from the external device.

[0088] (7) In the video recording system 100 of any one of (1) to (6) above, the storage 3 may have a plurality of flash memories 33 and a controller 35 that executes control related to the storage 3. The controller 35 may determine the flash memory 33 in which to record the buffered data based on information about the lifespan of the flash memories 33. By selecting a flash memory 33 that is close to reaching the end of its lifespan and recording the buffered data therein, the storage 3 can be used efficiently.

[0089] (8) The information processing device 1 of the present disclosure includes a RAM 12, a CPU 11, and a configuration unit 5. The RAM 12 includes multiple buffer areas BF1, BF2, ..., BFn allocated to multiple video channels CH1, CH2, ..., CHn, respectively. The CPU 11 controls recording of multiple video data into the flash memory 33. The configuration unit 5 sets time slots.

[0090] In the information processing device 1, the configuration unit 5 determines an access size. The access size is an integer multiple of the size of the erase block BL. The configuration unit 5 allocates a time slot to each of the multiple video channels CH based on the access size. The CPU 11 buffers the video data acquired via each of the video channels CH1, CH2, ..., CHn in buffer areas BF1, BF2, ..., BFn allocated to each of the video channels CH1, CH2, ..., CHn by the access size. The CPU 11 also records the buffered data buffered in each of the buffer areas BF1, BF2, ..., BFn in the flash memory 33 in the time slot allocated to the video channel CH1, CH2, ..., CHn corresponding to each of the buffer areas BF1, BF2, ..., BFn.

[0091] In the information processing device 1, video data from the corresponding video channel CH is buffered in each of the multiple buffer areas BF by an amount equal to an integer multiple of the erase block BL, which is the erase unit of the storage 3. In the information processing device 1, the buffered data buffered in each buffer area BF is recorded in the storage 3 in a time slot assigned to the video channel CH corresponding to that buffer area BF. In other words, multiple pieces of video data (buffered data) are recorded in the storage 3 in individually assigned time slots. This allows the data transmission bandwidth of the data line connecting the information processing device 1 and the storage 3 to be monopolized by the transmission of one piece of video data (buffered data), thereby preventing a decrease in the recording rate of the video data.

[0092] Furthermore, the size of the buffering data recorded in one time slot is set to an integer multiple of the erase block size, which is the unit of data erasure in the storage 3. This makes it possible to prevent the occurrence of erase blocks BL in which video data is only partially recorded. As a result, the occurrence of garbage collection processes is suppressed, and a decrease in the operating speed of the storage 3 is suppressed. Furthermore, by recording buffering data that is an integer multiple of the erase block BL and is large in size in the storage 3 in one time slot, it is possible to prevent fragmentation of the video data recorded in the storage 3.

[0093] (9) The information processing device 1 of (8) above may further include an arbitration unit 6 that arbitrates access from the CPU 11 to the flash memory 33. The arbitration unit 6 may determine whether to permit access from the CPU 11 to the flash memory 33 based on the time slot setting set by the configuration unit 5. This makes it possible to arbitrate the transmission of video data (buffered data). [Industrial Applicability]

[0094] The present disclosure can be widely applied to a recording method for recording video data in a predetermined recording area and a video recording system. [Explanation of symbols]

[0095] 100:Video recording system 11: CPU, control unit 12:RAM, temporary storage 13:Storage device 14: Video interface 15: Storage interface 16: Interface 1: Information processing equipment 2: Video processing device 21: Input / output interface 3: Storage 31: Access port 33: Flash memory, non-volatile memory section 35: Controller 37: Storage section 5: Component 6: Mediation Department BF1 to BFn: Buffer area CH1~CHn: Video channels RA: Recording area BL: Erase Block PA:Page

Claims

1. a storage device having a nonvolatile memory unit that writes data in units of pages and erases data in units of erase blocks each consisting of a plurality of pages; an information processing device that records a plurality of pieces of video data acquired through a plurality of video channels in the nonvolatile memory unit; a component for setting time slots; Equipped with the information processing device includes a temporary storage unit having a plurality of buffer areas allocated to the plurality of video channels, respectively, and a control unit that controls recording of the plurality of video data in the non-volatile memory unit; The component comprises: determining an access size that is an integer multiple of the size of the erase block; assigning a time slot to each of the plurality of video channels based on the access size; The control unit buffering the video data acquired via each video channel in a buffer area allocated to each video channel by the access size; recording the buffered data buffered in each buffer area in the nonvolatile memory unit in a time slot assigned to the video channel corresponding to each buffer area; Video recording system.

2. the configuration unit further allocates time slots to the video channels corresponding to the video data based on the recording rate of the video data. The video recording system according to claim 1 .

3. The configuration unit further allocates a time slot to the video channel corresponding to the video data based on video characteristics of the video data. The video recording system according to claim 2 .

4. the configuration unit sets the time length of a time slot to a time obtained by adding a predetermined time to a processing time based on the data transfer rate between the information processing device and the storage and the access size.

3. A video recording system according to claim 1 or 2.

5. an arbitration unit that arbitrates access from the control unit to the nonvolatile memory unit, the arbitration unit determines whether to permit access from the control unit to the nonvolatile memory unit based on a time slot setting set by the configuration unit.

3. A video recording system according to claim 1 or 2.

6. The component comprises: When an external device requests access to the storage, it determines whether there is an available time slot; When it is determined that there is free time, the free time is allocated to an access from the external device.

3. A video recording system according to claim 1 or 2.

7. the storage includes a plurality of the nonvolatile memory units and a controller that executes control related to the storage; the controller determines the nonvolatile memory unit in which to record the buffered data based on information about the lifespan of the nonvolatile memory unit; 3. A video recording system according to claim 1 or 2.

8. a temporary storage unit having a plurality of buffer areas allocated to each of a plurality of video channels; a control unit that controls recording of a plurality of pieces of video data acquired through the plurality of video channels into a nonvolatile memory unit, the nonvolatile memory unit being written in units of pages and erased in units of erase blocks each consisting of a plurality of pages; a component for setting time slots; Equipped with The component comprises: determining an access size that is an integer multiple of the size of the erase block; assigning a time slot to each of the plurality of video channels based on the access size; The control unit buffering the video data acquired via each video channel in a buffer area allocated to each video channel by the access size; recording the buffered data buffered in each buffer area in the nonvolatile memory unit in a time slot assigned to the video channel corresponding to each buffer area; Information processing device.

9. an arbitration unit that arbitrates access from the control unit to the nonvolatile memory unit; Furthermore, the arbitration unit determines whether to permit access from the control unit to the nonvolatile memory unit based on a time slot setting set by the configuration unit. The information processing device according to claim 8 .

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