Semiconductor Devices

Abstract

A semiconductor device having a display pixel circuit and an imaging pixel circuit is provided. [Solution] A semiconductor device includes first and second circuits, where the first circuit includes a light-emitting device, and the second circuit includes a light-receiving device, first to fifth transistors, and a first capacitor. The light-receiving device has first and second terminals, and the light-emitting device has third and fourth terminals. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the gate of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the first capacitor. The second terminal of the first capacitor is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to the first terminal of the light-receiving device, the second terminal of the light-receiving device is electrically connected to the third terminal of the light-emitting device, and the fourth terminal of the light-emitting device is electrically connected to a wiring.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, the technical field of one embodiment of the present invention disclosed in this specification can include, for example, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] In recent years, improvements have been made in various aspects of display devices for electronic devices for XR (Extended Reality or Cross Reality) such as VR (Virtual Reality) and AR (Augmented Reality), mobile phones such as smartphones, tablet information terminals, notebook PCs (personal computers), etc. For example, display devices are being developed to increase pixel density, improve color reproducibility (NTSC ratio), reduce the size of driving circuits, reduce power consumption, etc.

[0004] The above-mentioned display devices may include an organic EL device. Non-Patent Document 1 discloses a method for manufacturing an organic optoelectronic device using standard UV (Ultraviolet) photolithography, which is one of the organic EL devices.

[0005] Furthermore, display devices that have new functions added by providing circuits other than display pixel circuits in the display area of ​​the display device are also being developed. For example, Patent Document 1 discloses a method for detecting an eye or the area around the eye as an image by a display device that includes an imaging pixel circuit in addition to a display pixel circuit in the display area. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2019 / 243955 [Non-patent literature]

[0007] [Non-Patent Document 1] B. Lamprecht et al., “Organic optoelectronic device fabrication using standard UV photolithography” phys.stat.sol.(RRL)2, No.1, p.16-18 (2008) Summary of the Invention [Problem to be solved by the invention]

[0008] When a display device has a display pixel circuit for outputting an image in its display area, as well as an imaging pixel circuit for detecting an image of a subject approaching or touching the display area, the size of the display area (for example, if the display area is rectangular, the length of the diagonal of the rectangle) tends to increase, and as a result, the pixel density (sometimes called resolution) of the display area tends to decrease.

[0009] One way to prevent the size of the display area from increasing is to use a common power supply wiring electrically connected to the display pixel circuit and the imaging pixel circuit. Specifically, to use a common power supply wiring, it is necessary to equalize the input voltages required for the display pixel circuit and the imaging pixel circuit. However, the input voltage ranges required for the display pixel circuit and the imaging pixel circuit to operate normally may differ. In this case, it is necessary to adjust the input voltage range of one of the display pixel circuit and the imaging pixel circuit to match the input voltage range of the other.

[0010] Furthermore, one method for reducing the size of the display area is to reduce the area of ​​the display pixel circuit and the imaging pixel circuit. However, reducing the area of ​​the light-receiving device included in the imaging pixel circuit reduces the S / N ratio (signal-to-noise ratio), making it more likely that noise will appear in the imaging data. For this reason, the imaging pixel circuit provided in the display area is required to be configured so that the S / N ratio does not decrease even if the area of ​​the imaging pixel circuit (light-receiving device) is reduced.

[0011] Furthermore, if the area of ​​the light-receiving device included in the imaging pixel circuit is reduced, the amount of current generated when the light-receiving device receives light is reduced, and more time is required to obtain imaging data. Therefore, the driving speed (shutter speed) of the imaging pixel circuit during imaging must be slowed. Therefore, when performing high-speed imaging in an imaging pixel circuit with a small area of ​​the light-receiving device, the imaging pixel circuit is required to be configured to shorten the time required to obtain imaging data.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device including a display pixel circuit and an imaging pixel circuit that are driven by a common input voltage.An object of one embodiment of the present invention is to provide a semiconductor device in which the S / N ratio does not decrease even when the imaging pixel circuit is downsized.An object of one embodiment of the present invention is to provide a semiconductor device that is capable of high-speed imaging even when the imaging pixel circuit is downsized.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a display device including the above-described semiconductor device.An object of one embodiment of the present invention is to provide a display device with high pixel density.An object of one embodiment of the present invention is to provide an electronic device including the above-described display device.

[0013] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0014] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit. The first circuit includes a light-emitting device, and the second circuit includes a light-receiving device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The light-receiving device has a first terminal and a second terminal, and the light-emitting device has a third terminal and a fourth terminal. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, and the gate of the second transistor is electrically connected to one of the source or drain of the third transistor and one of a pair of terminals of the first capacitor. The other of the pair of terminals of the first capacitor is electrically connected to one of the source or drain of the fourth transistor and one of the source or drain of the fifth transistor, and the other of the source or drain of the fifth transistor is electrically connected to the first terminal of the light-receiving device. The second terminal of the light-receiving device is electrically connected to the third terminal of the light-emitting device, and the fourth terminal of the light-emitting device is electrically connected to the first wiring, which functions as a wiring that applies a potential to the fourth terminal of the light-emitting device.

[0015] (2) Alternatively, in one embodiment of the present invention, in the above-described (1), a gate of the third transistor may be electrically connected to a gate of the fourth transistor.

[0016] (3) Alternatively, in one aspect of the present invention, in the above (1) or (2), the first circuit may include a sixth transistor and a seventh transistor. In particular, it is preferable that one of the source or drain of the seventh transistor is directly electrically connected to the fourth terminal of the light-emitting device, the other of the source or drain of the seventh transistor is directly electrically connected to the first wiring, and one of the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor.

[0017] (4) Another embodiment of the present invention is a display device including the semiconductor device of (3), a first driver circuit, a second driver circuit, a second wiring, and a third wiring. The first driver circuit is electrically connected to the gate of the sixth transistor via the second wiring, and the second driver circuit is electrically connected to the other of the source and drain of the seventh transistor via the third wiring. The first driver circuit has a function of transmitting a selection signal to the second wiring, and the second driver circuit has a function of transmitting an image data signal to the third wiring.

[0018] (5) Another embodiment of the present invention is an electronic device including the display device described above in (4) and a housing.

[0019] (6) Another embodiment of the present invention is a semiconductor device including a second circuit and a third circuit. The second circuit includes a first light-receiving device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, an eighth transistor, and a first capacitor. The third circuit includes a second light-receiving device, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor. The first light-receiving device has a first terminal and a second terminal, and the second light-receiving device has a fifth terminal and a sixth terminal. One of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, and a gate of the second transistor is electrically connected to one of a source or a drain of the third transistor and one of a pair of terminals of the first capacitor. The other of the pair of terminals of the first capacitor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one of the source or drain of the eighth transistor, and one of the source or drain of the fourteenth transistor, and the other of the source or drain of the fifth transistor is electrically connected to the other of the source or drain of the eighth transistor and a first terminal of the first light-receiving device. One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor, and the gate of the tenth transistor is electrically connected to one of the source or drain of the eleventh transistor and one of the pair of terminals of the second capacitor. The other of the pair of terminals of the second capacitor is electrically connected to one of the source or drain of the twelfth transistor and one of the source or drain of the thirteenth transistor, and the other of the source or drain of the thirteenth transistor is electrically connected to the other of the source or drain of the fourteenth transistor and a fifth terminal of the second light-receiving device. Furthermore, the second terminal of the first light receiving device is electrically connected to the sixth terminal of the second light receiving device.

[0020] (7) Alternatively, in one embodiment of the present invention, in the above (6), the gate of the third transistor may be electrically connected to the gate of the eleventh transistor, the gate of the fourth transistor may be electrically connected to the gate of the twelfth transistor, the gate of the fifth transistor may be electrically connected to the gate of the thirteenth transistor, and the gate of the eighth transistor may be electrically connected to the gate of the fourteenth transistor.

[0021] (8) Alternatively, according to one embodiment of the present invention, in the above-described (7), the other of the source and the drain of the first transistor may be electrically connected to the other of the source and the drain of the ninth transistor.

[0022] (9) Alternatively, one aspect of the present invention may have a configuration in (8) above, which includes a first circuit. In particular, the first circuit preferably includes a light-emitting device. Furthermore, the light-emitting device preferably includes a third terminal and a fourth terminal. Preferably, the third terminal of the light-emitting device is electrically connected to the second terminal of the first light-receiving device and the sixth terminal of the second light-receiving device, and the fourth terminal of the light-emitting device is electrically connected to the first wiring. Furthermore, it is preferable that the first wiring functions as a wiring that applies a potential to the fourth terminal of the light-emitting device.

[0023] (10) Alternatively, one aspect of the present invention may have a configuration in (8) above, including a first circuit including a light-emitting device, a sixth transistor, and a seventh transistor. Preferably, the light-emitting device has a third terminal and a fourth terminal. Preferably, the third terminal of the light-emitting device is electrically connected to the second terminal of the first light-receiving device and the sixth terminal of the second light-receiving device, one of the source or drain of the seventh transistor is electrically connected to the fourth terminal of the light-emitting device, the other of the source or drain of the seventh transistor is electrically connected to the first wiring, and one of the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor. Preferably, the first wiring functions as a wiring that applies a potential to the other of the source or drain of the seventh transistor.

[0024] (11) Alternatively, one embodiment of the present invention is a semiconductor device having a second circuit and a third circuit, but having a configuration different from that of the semiconductor device (6) above. The second circuit includes a first light-receiving device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, an eighth transistor, a fifteenth transistor, and a first capacitor. The third circuit includes a second light-receiving device, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor. The first light-receiving device has a first terminal and a second terminal, and the second light-receiving device has a fifth terminal and a sixth terminal. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, and the gate of the second transistor is electrically connected to one of the source or drain of the third transistor and one of a pair of terminals of the first capacitor. The other of the pair of terminals of the first capacitor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the fifth transistor, one of the source or drain of the eighth transistor, and one of the source or drain of the fifteenth transistor. The other of the source or drain of the fifteenth transistor is electrically connected to one of the source or drain of the fourteenth transistor, and the gate of the fifteenth transistor is electrically connected to the gate of the eighth transistor. The other of the source or drain of the fifth transistor is electrically connected to the other of the source or drain of the eighth transistor and a first terminal of the first light receiving device, and one of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor. The gate of the tenth transistor is electrically connected to one of the source or drain of the eleventh transistor and one of the pair of terminals of the second capacitor. In addition, the other of the pair of terminals of the second capacitor is electrically connected to one of the source or drain of the 12th transistor and one of the source or drain of the 13th transistor, and the other of the source or drain of the 13th transistor is electrically connected to the other of the source or drain of the 14th transistor and the fifth terminal of the second light-receiving device.Furthermore, the second terminal of the first light receiving device is electrically connected to the sixth terminal of the second light receiving device.

[0025] (12) Alternatively, in one aspect of the present invention, in the above (11), the gate of the third transistor may be electrically connected to the gate of the eleventh transistor, the gate of the fourth transistor may be electrically connected to the gate of the twelfth transistor, the gate of the fifth transistor may be electrically connected to the gate of the thirteenth transistor, and the gate of the eighth transistor may be electrically connected to the gate of the fourteenth transistor.

[0026] (13) Alternatively, according to one embodiment of the present invention, in the above-described (12), the other of the source and the drain of the first transistor may be electrically connected to the other of the source and the drain of the ninth transistor.

[0027] (14) Alternatively, one aspect of the present invention may have a configuration in (13) above, which includes a first circuit. The first circuit preferably includes a light-emitting device. The light-emitting device preferably includes a third terminal and a fourth terminal. The third terminal of the light-emitting device is preferably electrically connected to the second terminal of the first light-receiving device and the sixth terminal of the second light-receiving device, and the sixth terminal of the light-emitting device is preferably electrically connected to the first wiring. The first wiring preferably functions as a wiring that applies a potential to the fourth terminal of the light-emitting device.

[0028] (15) Alternatively, one aspect of the present invention may have a configuration according to (13) above, including a first circuit including a light-emitting device, a sixth transistor, and a seventh transistor. The light-emitting device preferably has a third terminal and a fourth terminal. Preferably, the third terminal of the light-emitting device is electrically connected to the second terminal of the first light-receiving device and the sixth terminal of the second light-receiving device, one of the source or drain of the seventh transistor is electrically connected to the fourth terminal of the light-emitting device, the other of the source or drain of the seventh transistor is electrically connected to the first wiring, and one of the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor. Preferably, the first wiring functions as a wiring that applies a potential to the other of the source or drain of the seventh transistor.

[0029] (16) Alternatively, another embodiment of the present invention is a display device including the semiconductor device according to (10) or (15), a first driver circuit, a second driver circuit, a second wiring, and a third wiring. The first driver circuit is electrically connected to the gate of the sixth transistor via the second wiring, and the second driver circuit is electrically connected to the other of the source and drain of the sixth transistor via the third wiring. The first driver circuit has a function of transmitting a selection signal to the second wiring, and the second driver circuit has a function of transmitting an image data signal to the third wiring.

[0030] (17) Another embodiment of the present invention is an electronic device including the display device described above in (16) and a housing.

[0031] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are all examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may themselves be a semiconductor device or may include a semiconductor device.

[0032] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer).

[0033] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0034] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (e.g., inverters, NAND circuits, and NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0035] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., when X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., when X and Y are connected without another element or circuit between them).

[0036] This specification also deals with a circuit configuration in which multiple elements are electrically connected to wiring (a wiring that supplies a constant potential or a wiring that transmits a signal). For example, if X and a wiring are directly connected and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0037] For example, it can be expressed as follows: "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By specifying the order of connections in the circuit configuration using expressions similar to these examples, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0038] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such a case where one conductive film has the functions of multiple components.

[0039] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0040] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of a wiring having a capacitance value higher than 0 F, a parasitic capacitance, or the gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0041] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, or a third gate.

[0042] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0043] Furthermore, in this specification, circuit elements such as "light-emitting devices" and "light-receiving devices" may have polarities referred to as "anodes" and "cathodes." In the case of "light-emitting devices," applying a forward bias (applying a positive potential relative to the "cathode" to the "anode") may cause the "light-emitting device" to emit light. In the case of "light-receiving devices," applying a zero bias or a reverse bias (applying a negative potential relative to the "cathode" to the "anode") and irradiating the "light-receiving device" with light may generate a current between the "anode" and the "cathode." As mentioned above, "anodes" and "cathodes" may be treated as input / output terminals in circuit elements such as "light-emitting devices" and "light-receiving devices." In this specification, the "anodes" and "cathodes" of circuit elements such as "light-emitting devices" and "light-receiving devices" may be referred to as terminals (first terminal, second terminal, etc.), respectively. For example, one of the "anode" or the "cathode" may be referred to as a first terminal, and the other of the "anode" or the "cathode" may be referred to as a second terminal.

[0044] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0045] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal or a wiring can also be referred to as a node.

[0046] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0047] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0048] Furthermore, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0049] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0050] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0051] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0052] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0053] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator."

[0054] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0055] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0056] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0057] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0058] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0059] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0060] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0061] In this specification, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0062] Light-emitting devices can be broadly divided into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, the light-emitting layers can be selected so that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light can be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to produce a configuration in which the entire light-emitting device emits white light.

[0063] A tandem-structured device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structured device. In a tandem-structured device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0064] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0065] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0066] According to one embodiment of the present invention, a semiconductor device including a display pixel circuit and an imaging pixel circuit driven by a common input voltage can be provided. According to one embodiment of the present invention, a semiconductor device in which the S / N ratio does not decrease even when the imaging pixel circuit is downsized can be provided. According to one embodiment of the present invention, a semiconductor device capable of high-speed imaging even when the imaging pixel circuit is downsized can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a display device including the above-described semiconductor device can be provided. According to one embodiment of the present invention, a display device with high pixel density can be provided. According to one embodiment of the present invention, an electronic device including the above-described display device can be provided.

[0067] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0068] [Figure 1] 1A and 1B are block diagrams showing configuration examples of a semiconductor device. [Figure 2] FIG. 2A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIG. 2B is a timing chart showing an example of the operation of the semiconductor device. [Figure 3] FIG. 3A is a circuit diagram showing an example of the configuration of the semiconductor device, and FIG. 3B is a timing chart showing an example of the operation of the semiconductor device. [Figure 4] 4A to 4C are circuit diagrams showing configuration examples of a semiconductor device. [Figure 5]5A to 5C are circuit diagrams showing configuration examples of a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 7] FIG. 7 is a block diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a plan view showing an example of a pixel. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a timing chart showing an example of the operation of the semiconductor device. [Figure 13] FIG. 13 is a timing chart showing an example of the operation of the semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a plan view showing an example of a pixel. [Figure 17] FIG. 17 is a plan view showing an example of a pixel. [Figure 18] FIG. 18 is a cross-sectional view showing a configuration example of a display device. [Figure 19] FIG. 19 is a block diagram showing an example of the configuration of a display device. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of an imaging device. [Figure 21] FIG. 21 is a block diagram showing an example of the configuration of a display device. [Figure 22] FIG. 22 is a cross-sectional view showing a configuration example of a display device. [Figure 23] 23A to 23D are schematic diagrams showing configuration examples of light-emitting devices. [Figure 24] FIG. 24 is a cross-sectional view showing a configuration example of a display device. [Figure 25] 25A and 25B are cross-sectional views showing examples of the configuration of a display device. [Figure 26] 26A and 26B are cross-sectional views showing examples of the configuration of a display device. [Figure 27] 27A and 27B are cross-sectional views showing examples of the configuration of a display device. [Figure 28] 28A and 28B are cross-sectional views showing examples of the configuration of a display device. [Figure 29] 29A to 29F are cross-sectional views showing an example of a method for manufacturing a display device. [Figure 30] FIG. 30A is a circuit diagram showing an example of the configuration of a pixel circuit included in the display device, and FIG. 30B is a schematic perspective view showing an example of the configuration of a pixel circuit included in the display device. [Figure 31] 31A to 31D are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 32] 32A to 32D are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 33] 33A and 33B are schematic plan views showing examples of the arrangement of light-emitting devices and light-receiving devices included in a display device. [Figure 34] 34A to 34D are cross-sectional views showing examples of the configuration of a light-emitting device, a light-receiving device, and connection electrodes included in a display device. [Figure 35] 35A to 35G are plan views showing examples of pixels. [Figure 36] 36A to 36F are plan views showing examples of pixels. [Figure 37] 37A to 37H are plan views showing examples of pixels. [Figure 38] 38A to 38D are plan views showing examples of pixels. [Figure 39] 39A to 39D are plan views showing an example of a pixel, and FIG. 39E is a cross-sectional view showing an example of a display device. [Figure 40]40A and 40B are diagrams showing configuration examples of a display module. [Figure 41] 41A to 41F are diagrams showing configuration examples of electronic devices. [Figure 42] 42A to 42D are diagrams showing configuration examples of electronic devices. [Figure 43] 43A to 43C are diagrams showing configuration examples of electronic devices. [Figure 44] 44A to 44H are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0069] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0070] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0071] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0072] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0073] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0074] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0075] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0076] In addition, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view, for example, is a diagram showing the appearance of a surface (cut surface) obtained by cutting a configuration horizontally. Also, hidden lines (e.g., dashed lines) may be included in the plan view to show the positional relationship of multiple elements included in the configuration or the overlapping relationship of the multiple elements. Note that in this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Depending on the situation, a plan view may refer to a surface (cut surface) obtained by cutting a configuration in a direction other than the horizontal direction, rather than a surface (cut surface) obtained by cutting the configuration horizontally.

[0077] In addition, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a view showing the appearance of a surface (cut surface) of a configuration cut in a vertical direction. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Depending on the situation, a cross-sectional view may refer to a surface (cut surface) of a configuration cut in a direction other than the vertical direction, rather than a surface (cut surface) cut in a vertical direction.

[0078] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0079] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0080] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0081] <Configuration example 1> 1A is a block diagram illustrating a display pixel circuit and an imaging pixel circuit that can be provided in a display region of a display device, and the circuit AP illustrated in FIG. 1A is an example of a semiconductor device of one embodiment of the present invention. The circuit AP includes a circuit PX and a circuit PV.

[0082] The circuit PX has a function as a display pixel circuit, for example. The display pixel circuit can be, for example, a pixel to which at least one of a liquid crystal display device and a light-emitting device is applied. Examples of the light-emitting device include a light-emitting device containing an organic EL material and an LED (including a micro LED). In this embodiment, the circuit PX is described as being applied with a light-emitting device containing an organic EL material. The brightness of light emitted from a light-emitting device capable of emitting particularly high brightness light is, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 More than 10000cd / m 2 or less, more preferably 2000 cd / m 2 More than 5000cd / m 2 The following can be done: Note that a pixel circuit that can be applied to the circuit PX and the like will be described in detail in the fourth embodiment.

[0083] The circuit PV functions as, for example, an imaging pixel circuit, which includes, for example, a light receiving device that functions as an imaging device.

[0084] The circuit PX is electrically connected to, for example, a wiring SL, a wiring GL, and a wiring CT.

[0085] The wiring SL functions as, for example, a wiring that transmits image data signals to the circuit PX, or may be a wiring that applies, for example, a constant voltage or a variable potential (sometimes called a pulse voltage).

[0086] The wiring GL functions as, for example, a wiring that transmits a selection signal for selecting a circuit PX to which an image data signal is to be supplied, or may function as, for example, a wiring that applies a constant potential.

[0087] The wiring CT functions, for example, as a wiring that applies a constant potential to the circuit PX. Furthermore, as an example, the wiring CT is electrically connected to a terminal of a light-emitting device included in the circuit PX. In this case, the constant potential is preferably, for example, a ground potential or a negative potential. Alternatively, the wiring CT may be, for example, a wiring that applies a variable potential.

[0088] The circuit PV is electrically connected to, for example, a wiring TX, a wiring RS, a wiring SE, a wiring OL, and a wiring CT.

[0089] The wiring TX functions as, for example, a wiring that transmits a trigger signal for causing a light receiving device included in the circuit PV to capture an image, or the wiring TX may function as, for example, a wiring that applies a constant voltage.

[0090] The wiring RS functions, for example, as a wiring for transmitting a trigger signal for erasing imaging data captured by a light receiving device included in the circuit PV. The erasing of imaging data can be rephrased as an initialization operation of a potential corresponding to the imaging data stored in the circuit PV, for example, in order to perform new imaging in the circuit PV. Alternatively, the wiring RS may be, for example, a wiring for applying a constant voltage.

[0091] The wiring SE functions as, for example, a wiring that transmits a trigger signal for reading out image data captured by a light receiving device included in the circuit PV, or may function as, for example, a wiring that applies a constant potential.

[0092] The wiring OL functions as a wiring that transmits, as a signal, image data captured by a light receiving device included in the circuit PV, or may be a wiring that applies, for example, a constant potential or a variable potential.

[0093] The wiring CT also functions as a wiring that applies a constant potential to the circuit PV. The wiring CT is also assumed to be electrically connected to a terminal of a light receiving device included in the circuit PV, for example.

[0094] 1A shows various wirings, wirings other than wirings SL, GL, TX, RS, SE, OL, and CT may be electrically connected to either or both of the circuit PX and the circuit PV. For example, although not shown in FIG. 1A, wirings that provide a power supply voltage for driving either or both of the circuit PX and the circuit PV may be electrically connected to the circuit AP.

[0095] Furthermore, at least one of the various wirings shown in Fig. 1A may be provided in a number of pieces rather than one. For example, the wiring GL shown in Fig. 1A may be provided in a number of pieces rather than one. Furthermore, for example, the wiring RS shown in Fig. 1A may be provided in a number of pieces rather than one.

[0096] 1A shows a configuration in which the circuit AP includes one circuit PX as a display pixel circuit, but the circuit AP may include multiple display pixel circuits. In particular, the multiple display pixel circuits may be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the multiple display pixel circuits may be four or more colors, for example, by adding one or more colors selected from cyan, magenta, yellow, and white to the above-mentioned three colors: red (R), green (G), and blue (B). Each pixel that expresses a different color is called a subpixel, and when white is expressed by multiple subpixels of different colors, the multiple subpixels may be collectively referred to as a pixel in this specification.

[0097] 1B shows, as an example, the configuration of a circuit AP having three display pixel circuits: a circuit PX_R that is a red (R) display pixel circuit, a circuit PX_G that is a green (G) display pixel circuit, and a circuit PX_B that is a blue (B) display pixel circuit. Also shown in FIG. 1B are wirings SL_R, SL_G, and SL_B that correspond to the wirings SL in FIG. 1A, where the wiring SL_R is, as an example, electrically connected to the circuit PX_R, the wiring SL_G is, as an example, electrically connected to the circuit PX_G, and the wiring SL_B is, as an example, electrically connected to the circuit PX_B.

[0098] The arrangement order of the display pixel circuits and imaging pixel circuits is not limited to the order shown in FIG. 1B, and may be changed depending on the situation.

[0099] <Example 1> FIG. 2A shows an example of a circuit configuration that can be applied to the circuit AP of FIG. 1A.

[0100] The circuit PX shown in Fig. 2A includes a transistor Tr1 and a light-emitting device ED. Although only the transistor Tr1 and the light-emitting device ED are shown in the circuit PX in Fig. 2A, the circuit PX may include circuit elements other than the transistor Tr1 and the light-emitting device ED depending on the configuration of the circuit PX.

[0101] The circuit PV also includes transistors M1 to M5, a capacitor CV1, and a light-receiving device PD.

[0102] In FIG. 2A, both the light emitting device ED and the light receiving device PD are illustrated as circuit elements having an anode and a cathode, as an example.

[0103] Furthermore, it is preferable to use, for example, OS transistors as the transistors Tr1 and M1 to M5. In particular, the metal oxide contained in the channel formation region of the OS transistor is preferably, for example, an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). Alternatively, the transistor may be a transistor having silicon in the channel formation region (hereinafter referred to as a Si transistor). The silicon may be, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)). In addition, examples of transistors other than OS transistors and Si transistors that can be used include transistors containing germanium or the like in a channel formation region, transistors containing a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, transistors containing carbon nanotubes in a channel formation region, and transistors containing an organic semiconductor in a channel formation region.

[0104] Furthermore, the semiconductor device of one embodiment of the present invention may include, for example, both an OS transistor and a Si transistor. In particular, by using both an LTPS transistor, which is a Si transistor, and an OS transistor, a semiconductor device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO. Note that, as a more preferred example, it is preferable to use an OS transistor as a transistor that functions as a switch for controlling conduction / non-conduction between wirings and an LTPS transistor as a transistor for controlling current.

[0105] As shown in FIG. 2A, the transistor Tr1 and the transistors M1 to M5 are, for example, n-channel transistors having gates above and below the channel, and each of the transistors Tr1 and M1 to M5 has a first gate and a second gate. However, for convenience, the first gate may be referred to as a gate (sometimes referred to as a front gate) and the second gate may be referred to as a back gate. Furthermore, the first gate and the second gate may be interchangeable in the present specification, and therefore the term "gate" may be interchangeable with the term "back gate." Similarly, the term "back gate" may be interchangeable with the term "gate." As a specific example, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" may be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0106] 2A, the back gates of the transistors Tr1 and M1 to M5 are illustrated. Although the connection configuration of the back gates is not illustrated, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor Tr1 may be electrically connected, or the gate and the back gate of the transistor M1 may be electrically connected. Furthermore, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit, and a potential may be applied to the back gate of the transistor from the external circuit.

[0107] 2A includes a back gate, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistor Tr1 and the transistors M1 to M5 shown in FIG. 2A may have a structure without a back gate, that is, a single-gate transistor. Some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0108] 2A illustrates n-channel transistors for the transistors Tr1 and M1 to M5, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor Tr1 and some or all of the transistors M1 to M5 may be replaced with p-channel transistors.

[0109] The above-described examples of changes in the structure and polarity of the transistors are not limited to the transistor Tr1 and the transistors M1 to M5. For example, the structure and polarity of transistors described elsewhere in the specification or illustrated in other drawings may also be changed in the same way.

[0110] In the circuit PX, for example, a first terminal of a transistor Tr1 is electrically connected to a wiring SL, a gate of the transistor Tr1 is electrically connected to a wiring GL, and a cathode of a light-emitting device ED is electrically connected to a wiring CT.

[0111] Note that the circuit PX may include circuit elements other than the transistor Tr1 and the light-emitting device ED. For example, the circuit configuration of the circuit PX in FIG. 2A may vary depending on the functions that the circuit PX may have. In the circuit PX in FIG. 2A, the electrical connection destination of the anode of the light-emitting device ED and the electrical connection destination of the second terminal of the transistor Tr1 are not limited. Therefore, in the circuit PX in FIG. 2A, the electrical connection destination of the anode of the light-emitting device ED and the electrical connection destination of the second terminal of the transistor Tr1 are not illustrated. In addition, configuration examples of display pixel circuits that can be applied to the circuit PX in FIG. 2A will be described later.

[0112] In the circuit PV, for example, a first terminal of a transistor M1 is electrically connected to a wiring OL, a gate of the transistor M1 is electrically connected to a wiring SE, and a second terminal of the transistor M1 is electrically connected to a first terminal of a transistor M2. The second terminal of the transistor M2 is electrically connected to a wiring VDE, and the gate of the transistor M2 is electrically connected to a first terminal of a transistor M3 and a first terminal of a capacitor CV1. The second terminal of the transistor M3 is electrically connected to a wiring VR2, and the gate of the transistor M3 is electrically connected to a wiring RS2. The second terminal of the capacitor CV1 is electrically connected to a first terminal of a transistor M4 and a first terminal of a transistor M5. The second terminal of the transistor M4 is electrically connected to a wiring VR1, and the gate of the transistor M4 is electrically connected to a wiring RS1. The second terminal of the transistor M5 is electrically connected to an anode of a light-receiving device PD, and the gate of the transistor M5 is electrically connected to a wiring TX. The cathode of the light-receiving device PD is electrically connected to a wiring CT.

[0113] In this specification, the electrical connection point between the gate of transistor M2, the first terminal of transistor M3, and the first terminal of capacitor CV1 is referred to as node N2. Similarly, the electrical connection point between the second terminal of capacitor CV1, the first terminal of transistor M4, and the first terminal of transistor M5 is referred to as node N1.

[0114] For example, the wirings VR1, VR2, and VDE function as wirings that apply a constant potential. In particular, the constant potential applied by the wiring VR1 is preferably equal to the constant potential applied by the wiring CT. The constant potential applied by the wiring VR2 is preferably higher than the constant potential applied by the wiring VR1. The constant potential applied by the wiring VDE is preferably a high-level potential, a potential equal to the constant potential applied by the wiring VR2, or a potential higher than the constant potential applied by the wiring VR2.

[0115] <<Example 1>> Next, an example of the operation of the circuit PV included in the circuit AP of FIG. 2A will be described.

[0116] Fig. 2B is a timing chart showing an example of the operation of the circuit AP in Fig. 2A. The timing chart in Fig. 2B shows, as an example, fluctuations in the potentials of the wirings RS1, RS2, TX, SE, node N1, node N2, and OL from time T01 to time T06 and around those times.

[0117] In this example, the high-level potential provided by the wiring RS1 is V High1 The low level potential given by wiring RS1 is V Low1 Also, the high level potential given by wiring RS2 is V High2 The low-level potential given by wiring RS2 is V Low2 In addition, the high level potential given by the wiring TX is V High3 The low-level potential given by the wiring TX is V Low3 Also, the high level potential given by the wiring SE is V High4 The low level potential given by the wiring SE is V Low4 Let's say.

[0118] In this example, the constant voltage provided by the wiring VR1 is V CATH The constant voltage given by wiring VR2 is V LVSH Also, the constant voltage given by the wiring VDE is V DD Also, the constant voltage given by the wiring CT is set to the same V as the constant voltage given by the wiring VR1. CATH Let's say.

[0119] Also, before time T01, for example, V PRE is precharged. PRE The timing for precharging the potential V to the wiring OL does not have to be before time T01, but may be any time between time T01 and time T05. PRE After precharging, the wiring OL is set to a floating state.

[0120] In this example, V LVSH is V CATH The potential is higher than V LVSH and V PRE and may be at the same potential. DD is V CATH , V LVSH , and V PRE The potential is set to be higher than

[0121] Also, V High4 and V PRE Each of the V High4 and V PRE The difference between V and V is higher than the threshold voltage of transistor M4. Low4 and V PRE Each of the V Low4 and V PRE The potential is set so that the difference between these is equal to or less than the threshold voltage of the transistor M4.

[0122] Also, V High1 and V CATH Each of the V High1 and V CATH The difference between V and V is higher than the threshold voltage of transistor M4. Low1 and V CATH Each of the V Low1 and V CATH The difference between V and V is equal to or less than the threshold voltage of transistor M4. High2 and V LVSH Each of the V High2 and V LVSH The difference between V and V is higher than the threshold voltage of transistor M3. Low2 and V LVSH Each of the V Low2 and V LVSH The difference between V and V is equal to or less than the threshold voltage of transistor M3. High3 and V CATH Each of the V High3 and V CATH The difference between V and V is higher than the threshold voltage of transistor M5. Low3 and VCATH Each of the V Low3 and V CATH The potential is set so that the difference between these is equal to or less than the threshold voltage of the transistor M5.

[0123] From the above, if the threshold voltages of transistors M4 and M5 are equal, V High1 and V High3 and may be at equal potentials, and V Low1 and V Low3 and may be at the same potential.

[0124] [From time T01 to time T02] Between time T01 and time T02, the wiring TX is supplied with a low-level potential (V Low3 ) is input, and the low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is input, and the SE line is at a low level potential (V Low4 ) is entered.

[0125] In addition, the potentials of the nodes N1 and N2 from time T01 to time T02 are V ini1 , V ini2 In addition, V ini1 , and V ini2 Each of these is, for example, V CATH The potential is equal to or greater than V ini1 , and V ini2 can be set to a potential corresponding to the imaging data captured by the circuit PV at a time before time T01, for example.

[0126] The gate of the transistor M4 is connected to a low-level potential (V Low1 ) is applied, and the gate-source voltage of transistor M4 becomes V Low1 -V CATH V Low1 -V CATH is equal to or less than the threshold voltage of transistor M4, so transistor M4 is in the off state.

[0127] The gate of the transistor M5 is connected to a low-level potential (V Low3 ) is applied. At this time, the gate-source voltage of the transistor M5 becomes equal to or lower than the threshold voltage of the transistor M5, and the transistor M5 is turned off.

[0128] The gate of the transistor M3 is connected to a low-level potential (V Low2 ) is applied, and the gate-source voltage of transistor M3 becomes V Low2 -V LVSH V Low2 -V LVSH is equal to or less than the threshold voltage of the transistor M3, so the transistor M3 is in an off state.

[0129] The gate of the transistor M1 is connected to a low-level potential (V Low4 ) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0130] Between time T01 and time T02, the gate of transistor M2 is connected to V ini2 is applied to the second terminal of the transistor M2, and the potential V DD Here, the potential of the first terminal of the transistor M2 is V DD The first terminal of the transistor M2 functions as a source. Note that although the transistor M2 is turned on depending on the gate-source voltage of the transistor M2, the transistor M1 is turned off as described above, and therefore no current flows from the wiring VDE to the wiring OL via the transistors M2 and M1.

[0131] [From time T02 to time T03] Between time T02 and time T03, the wiring RS1 is supplied with a high-level potential (V High1 ) is input, and a high-level potential (VHigh2 ) is input to the wiring TX. High3 ) is entered.

[0132] At this time, the gate of the transistor M4 is supplied with a high-level potential (V High1 ) is applied, and the gate-source voltage of transistor M4 becomes V High1 -V CATH V High1 -V CATH is greater than the threshold voltage of the transistor M4, the transistor M4 is turned on. Therefore, conduction is established between the wiring VR1 and the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1), and the potential of the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1) becomes V CATH This becomes:

[0133] The gate of the transistor M5 is connected to a high-level potential (V High3 ) is applied, and the gate-source voltage of transistor M5 becomes V High3 -V CATH V High3 -V CATH is greater than the threshold voltage of the transistor M5, the transistor M5 is turned on. Therefore, the line VR1 and the anode of the light-receiving device PD are electrically connected, and the potential of the anode of the light-receiving device PD is V CATH This becomes:

[0134] At this time, the voltage between the anode and cathode of the light receiving device PD is 0 V, and therefore no current flows between the anode and cathode of the light receiving device PD.

[0135] The gate of the transistor M3 is connected to a high-level potential (V High2 ) is applied, and the gate-source voltage of transistor M3 becomes V High2 -V LVSH V High2 -V LVSHis greater than the threshold voltage of the transistor M3, the transistor M3 is turned on. Therefore, electrical continuity is established between the wiring VR2 and the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2), and the potential of the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2) becomes V LVSH This becomes:

[0136] From time T02 to time T03, the gate of the transistor M2 is supplied with a potential V LVSH is applied to the second terminal of the transistor M2, and the potential V DD Here, as in the period from time T01 to time T02, the potential of the first terminal of the transistor M2 is V DD and the first terminal of the transistor M2 functions as a source. Note that the transistor M2 may be turned on depending on the gate-source voltage of the transistor M2, but it is preferable that the transistor M2 be turned off between time T02 and time T03. Furthermore, as in the period from time T01 to time T02, the transistor M1 is turned off, and therefore no current flows from the wiring VDE to the wiring OL via the transistors M2 and M1.

[0137] [From time T03 to time T04] Between time T03 and time T04, the wiring RS1 is supplied with a low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is entered.

[0138] The gate of the transistor M4 is connected to a low-level potential (V Low1 ) is applied, and the gate-source voltage of transistor M4 becomes V Low1 -V CATH V Low1 -V CATH is equal to or less than the threshold voltage of transistor M4, so transistor M4 is turned off.

[0139] The gate of the transistor M3 is connected to a low-level potential (V Low2 ) is applied, and the gate-source voltage of transistor M3 becomes V Low2 -V LVSH V Low2 -V LVSH is equal to or lower than the threshold voltage of the transistor M3, the transistor M3 is turned off, and therefore the first terminal (node ​​N2) of the capacitor CV1 is in a floating state.

[0140] The transistor M5 has been in the on state since before time T03.

[0141] When light is irradiated onto the light-receiving device PD, a current flows from the cathode to the anode of the light-receiving device PD. Furthermore, because the transistor M4 is in the off state and the transistor M5 is in the on state, a positive charge due to the current flows to the node N1 and accumulates in the second terminal of the capacitor CV1 for the duration that the transistor M5 is in the on state. If the transistor M5 is turned off at time T04, the potential of the second terminal of the capacitor CV1 (node ​​N1) continues to increase from time T03 to time T04.

[0142] Between time T03 and time T04, the amount of positive charge accumulated in the second terminal (node ​​N1) of the capacitance CV1 is determined depending on the amount of current flowing through the light-receiving device PD, and therefore the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 is determined. Furthermore, the amount of current flowing through the light-receiving device PD is determined by the intensity of light incident on the light-receiving device PD. Here, for example, consider the cases where the intensity of light incident on the light-receiving device PD is a first intensity and a second intensity. If the light of the first intensity is stronger than the light of the second intensity, the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 is greater when light of the first intensity is incident on the light-receiving device than when light of the second intensity is incident on the light-receiving device.

[0143] In this operation example, when light of a first intensity is incident on the light receiving device PD, the potential of the node N1 is V CATH From V CATH +V PDS (The potential change of the node N1 in FIG. 2B is shown by a solid line), and when light of a second intensity is incident on the light receiving device PD, the potential of the node N1 changes to V CATH From V CATH +V PDW (The potential change at node N1 in FIG. 2B is shown by a thick dashed line.) PDS , and V PDW is 0 <V PDS <V PDW and the voltage is determined by the intensity of light incident on the light receiving device PD.

[0144] The change in the potential of the node N1 shown in FIG. 2B is an example, and depending on the intensity of light incident on the light receiving device PD, the potential of the node N1 at time T04 may change from V CATH +V PDS , and V CATH +V PDW The value may be other than .

[0145] Furthermore, between time T03 and time T04, the first terminal (node ​​N2) of the capacitor CV1 is in a floating state, and therefore, due to the capacitive coupling of the capacitor CV1, the potential of the second terminal (node ​​N1) of the capacitor CV1 rises, and the potential of the first terminal (node ​​N2) of the capacitor CV1 also rises. The amount of change in the potential of the first terminal (node ​​N2) of the capacitor CV1 is the potential obtained by multiplying the amount of change in the potential of the second terminal (node ​​N1) of the capacitor CV1 by a capacitive coupling coefficient determined by the configuration around the first terminal (node ​​N2) of the capacitor CV1. The capacitive coupling coefficient is calculated, for example, from the capacitance value of the capacitor CV1, the gate capacitance of the transistor M2, and the parasitic capacitance. Here, when the capacitive coupling coefficient of the capacitor CV1 is p, the potential of the first terminal (node ​​N2) of the capacitor CV1 is V LVSH From V LVSH +pV PDS(The potential change at the node N2 in FIG. 2B is shown by a solid line), and when light of a second intensity is incident on the light receiving device PD, V LVSH From V LVSH +pV PDW (The potential change at node N2 in FIG. 2B is shown by a thick dashed line.)

[0146] [From time T04 to time T05] At time T04, the wiring TX is at a low level potential (V Low3 ) is entered.

[0147] At this time, the gate of the transistor M5 receives a low-level potential (V Low3 ) is applied. At this time, the gate-source voltage of the transistor M5 becomes equal to or lower than the threshold voltage of the transistor M5, and the transistor M5 is turned off.

[0148] This completes the accumulation of positive charges (potential increase) at the first terminal (node ​​N2) of the capacitor CV1 due to the current flowing between the anode and cathode of the light receiving device PD during the operation from time T03 to time T04.

[0149] [From time T05 to time T06] Between time T05 and time T06, the wire SE is supplied with a high-level potential (V High4 ) is entered.

[0150] The gate of the transistor M1 is connected to a high-level potential (V High4 ) is applied. At this time, the gate-source voltage of transistor M1 is V High4 -V PRE V High4 -V PRE is greater than the threshold voltage of transistor M1, so transistor M1 is turned on.

[0151] When light of a first intensity is incident on the light receiving device PD between time T03 and time T04, a voltage V LVSH +pV PDS is applied to the second terminal of the transistor M2, and the potential V DD Furthermore, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL. PRE is applied.

[0152] At this time, the gate-source voltage of transistor M2 is V LVSH +pV PDS -V PRE The gate-source voltage V LVSH +pV PDS -V PRE A current corresponding to the voltage flows. At this time, the wiring OL is in a floating state, so the potential of the wiring OL rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL at this time is V OUTS (The potential change of the wiring OL in FIG. 2B is shown by a solid line.)

[0153] Furthermore, when light of a second intensity is incident on the light receiving device PD between time T03 and time T04, a voltage V LVSH +pV PDW is applied to the second terminal of the transistor M2, and the potential V DD Furthermore, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL. PRE is applied.

[0154] At this time, the gate-source voltage of transistor M2 is V LVSH +pV PDW -V PRE The gate-source voltage V LVSH +pV PDW -V PRE A current corresponding to the voltage flows. At this time, the wiring OL is in a floating state, so the potential of the wiring OL rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL at this time is V OUTW (The potential change of the wiring OL in FIG. 2B is shown by a thick dashed line.)

[0155] The gate-source voltage of transistor M2 is V LVSH +pV PDS -V PRE is V LVSH +pV PDW -V PRE is larger than V OUTS is V OUTW The voltage is greater than

[0156] [After time T06] After time T06, the wire SE is at a low level potential (V Low4 ) is entered.

[0157] The gate of the transistor M1 is connected to a low-level potential (V Low4 ) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0158] At this time, by reading out the potential of the wiring OL, it is possible to obtain, from the circuit PV, image data captured by the light receiving device PD between time T03 and time T04.

[0159] Note that the operation of the semiconductor device of one embodiment of the present invention is not limited to the example of the operation in the timing chart in FIG. 2B and may be modified as appropriate within the scope of solving the problem.

[0160] For example, high-level potentials are simultaneously input to the wirings RS1, RS2, and TX from time T02 to time T03 in the timing chart of FIG. 2B. However, the operation of the semiconductor device of one embodiment of the present invention may be such that high-level potentials are input to the wirings RS1, RS2, and TX in any order from time T02 to time T03. Specifically, for example, a high-level potential may be input to the wiring RS1, then to the wiring RS2, and then to the wiring TX. Alternatively, for example, a high-level potential may be input to the wiring RS1, then to the wiring TX, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS2, and then to the wiring RS1.

[0161] Alternatively, for example, the operation of the semiconductor device of one embodiment of the present invention may be such that, between time T02 and time T03, high-level potentials are simultaneously input to two wirings selected from the wirings RS1, RS2, and TX, and high-level potentials are input to the remaining wirings before or after that. Specifically, for example, high-level potentials may be input to the wirings RS1 and RS2 after a high-level potential is input to the wiring TX.

[0162] Although the above describes an example of changing the operation between time T02 and time T03 in the timing chart of Figure 2B, the operation may also be changed during periods other than the period between time T02 and time T03 in the timing chart of Figure 2B.

[0163] As described above, by applying the circuit AP of Figure 2A to a pixel circuit included in a display device or the like, it is possible to electrically connect wiring CT that applies a common constant voltage to the cathode of the light-emitting device included in circuit PX, which is the display pixel circuit, and the cathode of the light-receiving device included in circuit PV, which is the imaging pixel circuit.

[0164] <Example 2> The circuit configuration applicable to the circuit AP of FIG. 1A or FIG. 1B may be not only the circuit AP of FIG. 2A but also the circuit AP shown in FIG. 3A.

[0165] The circuit AP of Fig. 3A is a modified example of the circuit AP of Fig. 2A, and differs from the circuit AP of Fig. 2A in that the electrical connections of the anode and cathode of the light receiving device PD are swapped. Specifically, for example, in the circuit AP of Fig. 3A, the anode of the light receiving device PD is electrically connected to the wiring CT, and the cathode of the light receiving device PD is electrically connected to the second terminal of the transistor M5.

[0166] <<Example 2>> Next, an example of the operation of the circuit PV included in the circuit AP of FIG. 3A will be described.

[0167] Fig. 3B is a timing chart showing an example of the operation of the circuit AP of Fig. 3A. The timing chart of Fig. 3B shows, as an example, fluctuations in the potentials of the wirings RS1, RS2, TX, SE, node N1, node N2, and OL from time T11 to time T16 and around those times.

[0168] In the description of the operation example of the circuit AP in FIG. 3A, the description of the same parts as those in the timing chart in FIG. 2B may be omitted.

[0169] [From time T11 to time T12] Between time T11 and time T12, similarly to the period from time T01 to time T02 in the timing chart of FIG. 2B, the wiring TX is supplied with a low-level potential (VLow3 ) is input, and the low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is input, and the SE line is at a low level potential (V Low4 ) is input. The potentials applied to the wirings TX, RS1, RS2, and SE are the same as the potentials supplied to the wirings described above from time T01 to time T02 in the timing chart of FIG. 2B. Therefore, the switching operations of the transistors M1 to M5 included in the circuit PV can be performed by referring to the operation example from time T01 to time T02 in the timing chart of FIG. 2B.

[0170] In addition, the potentials of the nodes N1 and N2 from time T11 to time T12 are V ini1 , and V ini2 However, V here ini1 , and V ini2 Each of these differs from the timing chart of FIG. 2B, as an example, CATH The potential is as follows: V ini1 , and V ini2 can be set to a potential corresponding to the imaging data captured by the circuit PV at a time before time T11, for example.

[0171] [From time T12 to time T13] Between time T12 and time T13, similarly to the period from time T02 to time T03 in the timing chart of FIG. 2B, the wiring RS1 is supplied with a high-level potential (V High1 ) is input, and a high-level potential (V High2 ) is input to the wiring TX. High3 ) is entered.

[0172] At this time, the gate of the transistor M4 is supplied with a high-level potential (V High1 ) is applied to the first terminal of the transistor M4. ini1 is the potential V of the second terminal of transistor M4CATH is lower than the gate-source voltage of transistor M4, V High1 -V ini1 V High1 -V ini1 is greater than the threshold voltage of the transistor M4, the transistor M4 is turned on. Therefore, conduction is established between the wiring VR1 and the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1), and the potential of the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1) becomes V CATH This becomes:

[0173] Furthermore, the switching operation of the transistor M5 will be explained with reference to the example of operation from time T02 to time T03 in the timing chart of FIG. 2B.

[0174] In particular, the transistor M5 is turned on, and the cathode of the light receiving device is supplied with the potential V CATH At this time, the voltage between the anode and cathode of the light receiving device PD is 0 V, so no current flows between the anode and cathode of the light receiving device PD.

[0175] The gate of the transistor M3 is connected to a high-level potential (V High2 ) is applied to the first terminal of the transistor M3. ini2 is the potential V of the second terminal of transistor M3 LVSH is lower than the gate-source voltage of transistor M3, V High2 -V ini2 V High2 -V ini2 is greater than the threshold voltage of the transistor M3, the transistor M3 is turned on. Therefore, electrical continuity is established between the wiring VR2 and the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2), and the potential of the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2) becomes V LVSH This becomes:

[0176] From time T12 to time T13, the gate of transistor M2 is connected to V LVSH is applied to the second terminal of the transistor M2, and the potential V DD Here, as in the period from time T01 to time T02, the potential of the first terminal of the transistor M2 is V DD The first terminal of the transistor M2 functions as a source. Note that depending on the gate-source voltage of the transistor M2, the transistor M2 is turned on, but the transistor M1 is turned off, so that no current flows from the wiring VDE to the wiring OL via the transistors M2 and M1.

[0177] [From time T13 to time T14] Between time T13 and time T14, similarly to the period from time T03 to time T04 in the timing chart of FIG. 2B, the wiring RS1 is supplied with a low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is entered.

[0178] The switching operations of transistors M3 to M5 are shown in the timing chart of FIG. 2B, with reference to the example of operation from time T03 to time T04. Specifically, from time T13 to time T14, transistors M3 and M4 are both in the OFF state. At this time, the first terminal (node ​​N2) of capacitor CV1 is in a floating state. Transistor M5 continues to be in the ON state from before time T13.

[0179] When light is irradiated onto the light-receiving device PD, a current flows from the cathode to the anode of the light-receiving device PD. As a result, transistor M4 is in the off state and transistor M5 is in the on state, and a positive charge due to this current flows into the line CT only while transistor M5 is in the on state. Conversely, a negative charge accumulates in the second terminal (node ​​N1) of the capacitor CV1. Assuming that transistor M5 turns off at time T14, the potential of the second terminal (node ​​N1) of the capacitor CV1 continues to drop from time T13 to time T14.

[0180] Between time T13 and time T14, the amount of negative charge accumulated at the second terminal (node ​​N1) of the capacitance CV1 is determined depending on the amount of current flowing through the light-receiving device PD, and therefore the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 is determined. Furthermore, the amount of current flowing through the light-receiving device PD is determined by the intensity of light incident on the light-receiving device PD. Here, for example, similar to the timing chart of FIG. 2B, consider the cases where the intensity of light incident on the light-receiving device PD is a first intensity and a second intensity. If the light of the first intensity is stronger than the light of the second intensity, the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 is greater when light of the first intensity is incident on the light-receiving device than when light of the second intensity is incident on the light-receiving device.

[0181] In this operation example, when light of a first intensity is incident on the light receiving device PD, the potential of the node N1 is V CATH From V CATH -V PDS (The potential change of the node N1 in FIG. 3B is shown by a solid line), and when light of a second intensity is incident on the light receiving device PD, the potential of the node N1 changes to V CATH From V CATH -V PDW (The potential change at node N1 in FIG. 3B is shown by a thick dashed line.) PDS , and V PDW is V PDS <V PDW<0, and can be a voltage determined by the intensity of light incident on the light receiving device PD.

[0182] The change in the potential of the node N1 shown in FIG. 3B is an example, and depending on the intensity of light incident on the light receiving device PD, the potential of the node N1 at time T14 may change from V CATH -V PDS , and V CATH -V PDW The value may be other than .

[0183] Furthermore, between time T13 and time T14, the first terminal (node ​​N2) of the capacitor CV1 is in a floating state. Therefore, due to the capacitive coupling of the capacitor CV1, the potential of the second terminal (node ​​N1) of the capacitor CV1 rises, and the potential of the first terminal (node ​​N2) of the capacitor CV1 also rises. The amount of change in the potential of the first terminal (node ​​N2) of the capacitor CV1 is calculated by multiplying the amount of change in the potential of the second terminal (node ​​N1) of the capacitor CV1 by a capacitive coupling coefficient determined by the configuration around the first terminal (node ​​N2) of the capacitor CV1. The capacitive coupling coefficient is calculated, for example, from the capacitance value of the capacitor CV1, the gate capacitance of the transistor M2, the parasitic capacitance, etc. As in the timing chart of FIG. 2B, when the capacitive coupling coefficient of the capacitor CV1 is p, the potential of the first terminal (node ​​N2) of the capacitor CV1 is V LVSH From V LVSH -pV PDS (The potential change at the node N2 in FIG. 3B is shown by a solid line), and when light of a second intensity is incident on the light receiving device PD, V LVSH From V LVSH -pV PDW (The potential change at node N2 in FIG. 3B is shown by a thick dashed line.)

[0184] [From time T14 to time T15] At time T14, similar to time T04 in the timing chart of FIG. 2B, the wiring TX is supplied with a low-level potential (V Low3 ) is entered.

[0185] The switching operation of the transistor M5 will be described with reference to the example of operation from time T04 to time T05 in the timing chart of Fig. 2B. Specifically, at time T14, the transistor M5 is turned off.

[0186] This completes the accumulation of negative charges (a drop in potential) at the second terminal (node ​​N1) of the capacitor CV1 due to the current flowing between the anode and cathode of the light receiving device PD during the operation from time T13 to time T14.

[0187] [From time T15 to time T16] Between time T15 and time T16, similarly to the period between time T05 and time T06 in the timing chart of FIG. 2B, the wire SE is supplied with a high-level potential (V High4 ) is entered.

[0188] The switching operation of the transistor M1 is shown in the timing chart of Fig. 2B from time T05 to time T06. Specifically, the transistor M1 is turned on from time T15 to time T16.

[0189] When light of a first intensity is incident on the light receiving device PD between time T13 and time T14, a voltage V LVSH +pV PDS is applied to the second terminal of the transistor M2, and the potential V DD Furthermore, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL. PRE is applied.

[0190] At this time, the gate-source voltage of transistor M2 is V LVSH +pV PDS -V PRE The gate-source voltage V LVSH +pV PDS-V PRE A current corresponding to the voltage flows. At this time, the wiring OL is in a floating state, so the potential of the wiring OL rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL at this time is V OUTS (The potential change of the wiring OL in FIG. 3B is shown by a solid line.)

[0191] Furthermore, when light of a second intensity is incident on the light receiving device PD between time T13 and time T14, a voltage V LVSH +pV PDW is applied to the second terminal of the transistor M2, and the potential V DD Furthermore, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL. PRE is applied.

[0192] At this time, the gate-source voltage of transistor M2 is V LVSH +pV PDW -V PRE The gate-source voltage V LVSH +pV PDW -V PRE A current corresponding to the voltage flows. At this time, the wiring OL is in a floating state, so the potential of the wiring OL rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL at this time is V OUTW (The potential change of the wiring OL in FIG. 3B is shown by a thick dashed line.)

[0193] The gate-source voltage of transistor M2 is V LVSH +pV PDS -V PRE is V LVSH +pV PDW -V PRE is smaller than V OUTS is V OUTW The voltage is smaller than

[0194] [After time T16] After time T16, similarly to after time T06 in the timing chart of FIG. 2B, the wire SE is supplied with a low-level potential (V Low4 ) is entered.

[0195] The switching operation of the transistor M1 is shown in the timing chart of Fig. 2B after time T06. Specifically, after time T16, the transistor M1 is turned off.

[0196] At this time, by reading out the potential of the wiring OL, it is possible to obtain, from the circuit PV, image data captured by the light receiving device PD between time T13 and time T14.

[0197] 3A to a pixel circuit included in a display device or the like, a wiring that applies a common constant potential to the cathode of a light-emitting device included in the circuit PX, which is a display pixel circuit, and the cathode or anode of a light-receiving device included in the circuit PV, which is an imaging pixel circuit, can be electrically connected.

[0198] Note that the operation of the semiconductor device of one embodiment of the present invention is not limited to the operation example of the timing chart in FIG. 3B and may be modified as appropriate within the scope of solving the problem.

[0199] For example, high-level potentials are simultaneously input to the wirings RS1, RS2, and TX from time T12 to time T13 in the timing chart of FIG. 3B. However, the operation of the semiconductor device of one embodiment of the present invention may be such that high-level potentials are input to the wirings RS1, RS2, and TX in any order from time T12 to time T13. Specifically, for example, a high-level potential may be input to the wiring RS1, then to the wiring RS2, and then to the wiring TX. Alternatively, for example, a high-level potential may be input to the wiring RS1, then to the wiring TX, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS1, and then to the wiring RS2. Alternatively, for example, a high-level potential may be input to the wiring TX, then to the wiring RS2, and then to the wiring RS1.

[0200] Alternatively, for example, the operation of the semiconductor device of one embodiment of the present invention may be such that, between time T12 and time T13, high-level potentials are simultaneously input to two selected from the wirings RS1, RS2, and TX, and high-level potentials are input to the remaining wirings before or after that. Specifically, for example, high-level potentials may be input to the wirings RS1 and RS2 after a high-level potential is input to the wiring TX.

[0201] Although the above describes an example of changing the operation between time T12 and time T13 in the timing chart of Figure 3B, the operation may also be changed during periods other than the period between time T12 and time T13 in the timing chart of Figure 3B.

[0202] <Example 3> The semiconductor device of one embodiment of the present invention is not limited to the circuit configurations shown in Figures 2A, 3A, etc. The configuration of the semiconductor device of one embodiment of the present invention may be changed as appropriate within the scope of solving the problems.

[0203] The circuit AP shown in Fig. 4A is a modified example of the circuit AP of Fig. 2A, and differs from the circuit AP of Fig. 2A in that the gates of the transistors M3 and M4 are electrically connected to each other. The circuit AP of Fig. 4A also differs from the circuit AP of Fig. 2A in that the gates of the transistors M3 and M4 are electrically connected to the wiring RS.

[0204] The wiring RS shown in the circuit AP of FIG. 4A functions as, for example, a wiring that transmits a trigger signal for resetting the image data captured by the light receiving device, similar to the wiring RS1 or wiring RS2 described in the circuit AP of FIG. 1A. In addition, as for the trigger signal, for example, the high-level potential (V High2 ), or the low-level potential (V Low1 ) can be used.

[0205] In the circuit PV of FIG. 2A and the circuit PV of FIG. 3A, the voltage ranges applied to the source, drain, and gate of transistors M3 and M4 are different. Therefore, when the circuit PV is driven with the gate of transistor M3 electrically connected to the gate of transistor M4 as shown in FIG. 4A, the gate-source voltage and gate-drain voltage of transistors M3 and M4 may be larger than those of the circuit PV of FIG. 2A and the circuit PV of FIG. 3A. Therefore, to stably drive the circuit PV with the circuit configuration of circuit AP of FIG. 4A, it is preferable that transistors M3 and M4 be transistors that can be driven even with large gate-source and gate-drain voltages. In other words, it is preferable that transistors M3 and M4 have high withstand voltages.

[0206] The circuit AP of FIG. 4A has one less wire than the circuit AP of FIG. 2A and the circuit AP of FIG. 3A, and therefore can reduce the area compared to the circuit AP of FIG. 2A and the circuit AP of FIG. 3A. Furthermore, by applying the circuit AP of FIG. 4A to a pixel circuit included in the display area of ​​a display device, the number of wires routed in the display area can be reduced compared to the circuit AP of FIG. 2A and the circuit AP of FIG. 3A. Furthermore, since the area in the display area is surplus due to the reduced wires, providing the circuit AP of FIG. 4A by the surplus area can increase the pixel density in the display area. Furthermore, because the circuit AP of FIG. 4A has fewer wires, it may be possible to reduce the influence of parasitic capacitance compared to the circuit AP of FIG. 2A and the circuit AP of FIG. 3A.

[0207] The circuit AP shown in Figure 4B is a modified example of the circuit AP of Figure 2A, and differs from the circuit AP of Figure 2A in that the anode of the light-emitting device ED is electrically connected to the wiring CT and the cathode of the light-emitting device ED is electrically connected to a circuit element included in the circuit PX.

[0208] In this case, a high-level potential is preferably input to the wiring CT to cause the light-emitting device ED to emit light. In this case, the constant potential applied by the wiring VR1 is preferably equal to the high-level potential applied by the wiring CT. The constant potential applied by the wiring VR2 is preferably equal to or lower than the constant potential applied by the wiring VDE.

[0209] For the operation of the circuit PV included in the circuit AP of FIG. 4B when performing imaging, refer to the operation of the timing chart of FIG. 2B, for example.

[0210] In the circuit AP of Fig. 4B, the anode and cathode of the light receiving device PD included in the circuit PV may be electrically connected to each other (not shown). In this case, the operation of the circuit PV when capturing an image may refer to, for example, the operation of the timing chart of Fig. 3B.

[0211] 4C is a modified example of the circuit AP of FIG. 2A, and differs from the circuit AP of FIG. 2A in that the cathode of the light-emitting device ED and the wiring CT are electrically connected via a switch SW. Specifically, the cathode of the light-emitting device ED is electrically connected to a first terminal of the switch SW, and the second terminal of the switch SW is electrically connected to the wiring CT.

[0212] The cathode of the light-emitting device ED and the first terminal of the switch SW may be electrically connected directly, and the second terminal of the switch SW and the wiring CT may be electrically connected directly.

[0213] The switch SW may be, for example, an analog switch or an electrical switch such as a transistor. When a transistor is used as the switch SW, the transistor may have a structure similar to that of the transistor Tr1 or the transistors M1 to M5. In addition to an electrical switch, a mechanical switch may also be used.

[0214] As shown in FIG. 4C , by providing a switch SW between the cathode of the light-emitting device ED and the wiring CT, the cathode of the light-emitting device ED and the wiring CT can be brought into a conductive or non-conductive state. For example, when the light-emitting device ED is to emit light, the switch SW is turned on to allow current to flow between the cathode of the light-emitting device ED and the wiring CT. Also, for example, when the light-emitting device ED is not to emit light, the switch SW is turned off to stop the current flowing between the cathode of the light-emitting device ED and the wiring CT. As a result, when the light-emitting device ED is not to emit light, turning the switch SW off can prevent current from flowing from the cathode of the light-emitting device ED to the wiring CT, which would otherwise cause the light-emitting device ED to emit light erroneously.

[0215] 4C, the anode and cathode of the light-emitting device included in the circuit PX may be electrically connected to each other (not shown), and the anode and cathode of the light-receiving device included in the circuit PV may be electrically connected to each other (not shown).

[0216] <Example 4> Fig. 5A is a circuit diagram showing an example of a specific circuit configuration of a circuit PX, which is a display pixel circuit, in the circuit AP of Fig. 2A. The circuit PX included in the circuit AP of Fig. 5A includes, for example, a transistor Tr1, a transistor Tr2, a capacitor CX1, and a light-emitting device ED.

[0217] The transistors Tr1 and Tr2 can be, for example, transistors that can be applied to the transistors M1 to M5.

[0218] A first terminal of the transistor Tr1 is electrically connected to the wiring SL, a second terminal of the transistor Tr1 is electrically connected to the first terminal of the capacitor CX1 and the gate of the transistor Tr2, and the gate of the transistor Tr1 is electrically connected to the wiring GL.

[0219] A first terminal of the transistor Tr2 is electrically connected to a second terminal of the capacitor CX1 and the line VA, and a second terminal of the transistor Tr2 is electrically connected to the anode of the light-emitting device ED.

[0220] The wiring VA functions as, for example, a wiring that applies a constant potential. The constant potential is, for example, V CATH It is preferable that the potential is higher than that.

[0221] In the circuit PX, a potential corresponding to image data is written to the first terminal of the capacitor CX1, causing the light-emitting device ED to emit light. Specifically, for example, by writing a potential corresponding to image data to the first terminal of the capacitor CX1, the amount of current flowing between the source and drain of the transistor Tr2 is determined, and this current flows between the anode and cathode of the light-emitting device ED. Furthermore, the brightness of the light emitted by the light-emitting device ED is proportional to the amount of current. In other words, the brightness of the light emitted by the light-emitting device ED is determined by the potential corresponding to the image data written to the first terminal of the capacitor CX1.

[0222] To write image data to the first terminal of the capacitor CX1 of the circuit PX, for example, a high-level potential is applied to the line GL to turn on the transistor Tr1, and then a desired image data signal is sent from the line SL to the first terminal of the capacitor CX1 via the transistor Tr1 (a potential corresponding to the image data is supplied). After the image data is written to the first terminal of the capacitor CX1 of the circuit PX, a low-level potential is applied to the line GL to turn off the transistor Tr1.

[0223] In addition, in the circuit AP of Fig. 2A, the circuit PX, which is a display pixel circuit, may be the circuit PX shown in Fig. 5B. The circuit PX shown in Fig. 5B is a modification of the circuit PX of Fig. 5A, and differs from the circuit PX shown in Fig. 5A in that the cathode of the light-emitting device ED is electrically connected to the wiring CT via the source-drain of the transistor Tr2.

[0224] The circuit PX in Fig. 5B includes a transistor Tr1 and a transistor Tr2, and also includes a capacitor CX4 instead of a capacitor CX1.

[0225] The first terminal of the transistor Tr1 is electrically connected to the line SL, the second terminal of the transistor Tr1 is electrically connected to the first terminal of the capacitor CX4 and the gate of the transistor Tr2, and the gate of the transistor Tr1 is electrically connected to the line GL. The anode of the light-emitting device ED is electrically connected to the line VA, and the cathode of the light-emitting device ED is electrically connected to the first terminal of the transistor Tr2. The second terminal of the transistor Tr2 is electrically connected to the second terminal of the capacitor CX4 and the line CT.

[0226] For the operation of the circuit PX in FIG. 5B, please refer to the explanation of the operation of the circuit PX in FIG. 5A.

[0227] Furthermore, in the circuit AP of Fig. 2A, the circuit PX, which is a display pixel circuit, may be the circuit PX shown in Fig. 5C. The circuit PX shown in Fig. 5C is, as an example, a configuration example of a display pixel circuit capable of duty driving. The circuit PX of Fig. 5C is a modified example of the circuit PX shown in Fig. 5A, and differs from the circuit PX shown in Fig. 5A in that it includes a transistor Tr3, a transistor Tr4, and a capacitor CX2, but does not include a capacitor CX1.

[0228] For example, the transistors Tr3 and Tr4 can be transistors that can be used as the transistors M1 to M5.

[0229] The first terminal of the capacitor CX2 is electrically connected to the second terminal of the transistor Tr1, the gate of the transistor Tr2, and the first terminal of the transistor Tr4. The second terminal of the capacitor CX2 is electrically connected to the second terminal of the transistor Tr2, the first terminal of the transistor Tr3, and the anode of the light-emitting device ED. The second terminal of the transistor Tr3 is electrically connected to the second terminal of the transistor Tr4 and the wiring VC.

[0230] 5C, the gate of transistor Tr1 is electrically connected to wiring GL1 instead of wiring GL, the gate of transistor Tr4 is electrically connected to wiring GL2, and the gate of transistor Tr3 is electrically connected to wiring GL3.

[0231] For example, the wiring VC functions as a wiring that applies a constant potential, which may be, for example, a ground potential.

[0232] In the circuit AP of FIG. 5C, when image data is written to the circuit PX, for example, a high-level potential is applied to the wiring GL1 and the wiring GL3, and a low-level potential is applied to the wiring GL2. This turns on the transistors Tr1 and Tr3, and turns off the transistor Tr4. After that, a desired image data signal is sent from the wiring SL to the first terminal of the capacitor CX2 (a potential corresponding to the image data is supplied). At this time, for example, a ground potential is applied from the wiring VC to the second terminal of the capacitor CX2. After writing the image data to the first terminal of the capacitor CX2 of the circuit PX, a low-level potential is applied to the wiring GL1 and the wiring GL3, turning off the transistors Tr1 and Tr3.

[0233] Furthermore, in the circuit AP of FIG. 5C, to write image data for black display to the circuit PX, for example, a high-level potential is applied to the lines GL2 and GL3 and a low-level potential is applied to the line GL1. This turns on the transistors Tr3 and Tr4 and turns off the transistor Tr1. Therefore, the ground potential is applied from the line VC to the first terminal of the capacitor CX2 and the second terminal of the capacitor CX2. In other words, since the gate-source voltage of the transistor Tr2 becomes 0V, if the threshold voltage of the transistor Tr2 is appropriate, no current flows through the light-emitting device ED, and the circuit PX displays black. After writing the ground potential to the first terminal of the capacitor CX2 of the circuit PX, a low-level potential is applied to the lines GL2 and GL3 to turn off the transistors Tr3 and Tr4.

[0234] 2A, the circuit PX, which is a display pixel circuit, may be the circuit PX shown in FIG. 6. The circuit PX shown in FIG. 6 is, as an example, a configuration example of a display pixel circuit that can correct the threshold voltage of transistor Tr2. The circuit PX in FIG. 6 is a modified example of the circuit PX shown in FIG. 5A, and differs from the circuit PX shown in FIG. 5A in that it includes transistors Tr3, Tr5, Tr6, capacitors CX2 and CX3, and does not include capacitor CX1.

[0235] For example, the transistors Tr5 and Tr6 can be any of the transistors applicable to the transistors M1 to M5.

[0236] The first terminal of the capacitor CX2 is electrically connected to the second terminal of the transistor Tr1 and the gate of the transistor Tr2. The second terminal of the capacitor CX2 is electrically connected to the second terminal of the transistor Tr2, the first terminal of the transistor Tr3, the first terminal of the transistor Tr5, and the first terminal of the capacitor CX3. The second terminal of the transistor Tr3 is electrically connected to the wiring VC. The second terminal of the capacitor CX3 is electrically connected to the back gate of the transistor Tr2 and the first terminal of the transistor Tr6, and the second terminal of the transistor Tr6 is electrically connected to the wiring VB. The second terminal of the transistor Tr5 is electrically connected to the anode of the light-emitting device ED.

[0237] 6, the gate of transistor Tr1 is electrically connected to wiring GL1 instead of wiring GL. The gate of transistor Tr6 is electrically connected to wiring GL2. The gate of transistor Tr3 is electrically connected to wiring GL3. The gate of transistor Tr5 is electrically connected to wiring GL4.

[0238] The wiring VB functions as a wiring that applies a constant voltage, for example. In particular, the constant voltage applied by the wiring VB in FIG. BG Let's say.

[0239] The wiring VC functions as a wiring that applies a constant voltage, for example. In particular, the constant voltage applied by the wiring VC in FIG. 6 is V CST In addition, V CST is V BG The voltage shall be lower than

[0240] In the circuit AP of FIG. 6, when correcting the threshold voltage of the transistor Tr2 of the circuit PX, for example, a high-level potential is first applied to the wirings GL1, GL2, GL3, and GL4. This turns on the transistors Tr1, Tr3, Tr5, and Tr6. At this time, a voltage V, which is equal to the constant voltage applied by the wiring VC, is applied from the wiring SL to the first terminal of the capacitor CX2. CST In addition, the potential from the wiring VB to the second terminal of the capacitor CX3 is V BG The second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 are supplied with a potential V CST However, since the transistor Tr5 is in the on state, the potential of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 is V CST The potential becomes lower than that of

[0241] Next, a low-level potential is applied to the line GL4, which turns off the transistor Tr5. Since the transistor Tr3 is on and the transistor Tr5 is off, the potentials of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 are V CST Strictly speaking, the potential of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 rises to V CST Lower than V CST At this time, the potential of the first terminal of the capacitor CX2 (the gate of the transistor Tr2), the potential of the second terminal of the capacitor CX2, and the potential of the first terminal of the capacitor CX3 (the second terminal of the transistor Tr2) are both approximately V CSTTherefore, the potential between the pair of terminals of the capacitor CX2 is approximately 0V.

[0242] Next, a low-level potential is applied to the wiring GL1 and the wiring GL3, which turns off the transistors Tr1 and Tr3. With the transistor Tr1 turned off, the first terminal of the capacitor CX2 (the gate of the transistor Tr2) is supplied with a potential V CST is maintained.

[0243] Here, the potential V of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 CST and the potential of the line VA, a high bias is applied between the first and second terminals of transistor Tr2. At this time, transistor Tr2 is turned on, and current flows from the first terminal to the second terminal of transistor Tr2. However, because transistors Tr3 and Tr5 are turned off, the potentials of the second terminal of capacitor CX2 and the first terminal of capacitor CX3 (the second terminal of transistor Tr2) are boosted by this current. Note that because the voltage across the pair of terminals of capacitor CX2 is approximately 0 V and transistor Tr1 is turned off (the first terminal of capacitor CX2 is floating), the gate-source voltage of transistor Tr2 remains approximately 0 V despite the boost in the potentials of the second terminal of capacitor CX2 and the first terminal of capacitor CX3 (the second terminal of transistor Tr2).

[0244] The potentials of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 are increased until the transistor Tr2 is turned off. Since the gate-source voltage of the transistor Tr2 is approximately 0V, when the threshold voltage of the transistor Tr2 becomes equal to or exceeds 0V, the transistor Tr2 is turned off. In other words, when the back gate-source voltage of the transistor Tr2 becomes a voltage that makes the threshold voltage of the transistor Tr2 0V, the transistor Tr2 is turned off. When the back gate-source voltage of the transistor Tr2 that makes the threshold voltage of the transistor Tr2 0V is V CRCWhen this is done, the potential at the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 is V BG -V CRC This becomes:

[0245] Since the first terminal of the capacitor CX2 is floating, the potential of the second terminal of the capacitor CX2 and the first terminal of the capacitor CX3 is V CST From V BG -V CRC The voltage boosted at the first terminal of the capacitor CX2 is determined by the capacitive coupling coefficient between the pair of terminals of the capacitor CX2.

[0246] Next, a high-level potential is applied to the wiring GL1 and the wiring GL3, and a low-level potential is applied to the wiring GL2. This turns on the transistor Tr1 and turns off the transistor Tr6. As a result, the second terminal of the capacitor CX3 is in a floating state, and the potential of the back gate of the transistor Tr2 is held by the second terminal of the capacitor CX3. This completes the correction of the threshold voltage of the transistor Tr2.

[0247] By correcting the threshold voltage of the transistor Tr2, it is possible to suppress variations in the current flowing between the source and drain of the transistor Tr2 due to deviations in the threshold voltage of the transistor Tr2, thereby suppressing variations in the brightness of the light emitted by the light-emitting device ED through which the current flows.

[0248] In the circuit PX, after the correction of the threshold voltage of the transistor Tr2 is completed, for example, a high-level potential is applied to the wiring GL1 and the wiring GL4, and a low-level potential is applied to the wiring GL2 and the wiring GL3. As a result, the transistors Tr1 and Tr5 are turned on, and the transistors Tr3 and Tr6 are turned off. After that, a desired image data signal is sent from the wiring SL to the first terminal of the capacitor CX2 (a potential corresponding to the image data is supplied). Furthermore, after the image data is written to the first terminal of the capacitor CX2 of the circuit PX, a low-level potential is applied to the wiring GL1 to turn off the transistor Tr1.

[0249] As described above, the circuit PX included in the circuit AP shown in Figures 2A and 3A can be the circuit PX included in any one of the circuits AP shown in Figures 5A to 5C and 6. Furthermore, a circuit configuration other than the circuit PX shown in Figures 5A to 5C and 6 may be applied to the circuit PX included in the circuit AP shown in Figures 2A and 3A.

[0250] Note that the circuit configurations described in this embodiment mode can be combined with each other as appropriate.

[0251] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0252] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention, which is different from the semiconductor device described in Embodiment 1, will be described.

[0253] <Configuration example 1> 7 is a block diagram showing a part of a display region of a display device including a display pixel circuit and an imaging pixel circuit, and is also an example of a semiconductor device of one embodiment of the present invention. Also shown in FIG. 7 are a circuit AP[i,j] (where i is an integer of 2 or greater and j is an integer of 2 or greater), a circuit AP[i+1,j], a circuit AP[i,j+1], and a circuit AP[i+1,j+1]. In FIG. 7, the circuit AP[i,j], the circuit AP[i+1,j], the circuit AP[i,j+1], and the circuit AP[i+1,j+1] are indicated by short dashed lines.

[0254] Each of the circuits AP[i,j], AP[i+1,j], AP[i,j+1], and AP[i+1,j+1] includes, for example, a circuit PX_R, a circuit PX_G, a circuit PX_B, and a circuit PV. The circuits PX_R, PX_G, and PX_B function as display pixel circuits, and the circuit PV functions as an imaging pixel circuit.

[0255] For the circuits PX_R, PX_G, and PX_B, please refer to the description of the circuit PX explained in the first embodiment. For the circuit PV, please refer to the description of the circuit PV explained in the first embodiment.

[0256] Furthermore, the display pixel circuits of the circuits PX_R, PX_G, and PX_B may each include a light-emitting device that emits light of a different color. In particular, the light-emitting devices included in the circuits PX_R, PX_G, and PX_B may emit light of three colors: red (R), green (G), and blue (B). Alternatively, the light-emitting devices included in the circuits PX_R, PX_G, and PX_B may emit light of three colors selected from red, green, blue, cyan, magenta, yellow, and white. Alternatively, the light-emitting devices included in two of the circuits PX_R, PX_G, and PX_B may emit light of the same color, while the light-emitting device included in the remaining circuit may emit light of a different color from the light-emitting devices included in the two circuits. Alternatively, the light-emitting devices included in the circuits PX_R, PX_G, and PX_B may all emit light of the same color.

[0257] 7, each of the circuits PV of the circuit AP[i,j], the circuit AP[i+1,j], the circuit AP[i,j+1], and the circuit AP[i+1,j+1] is arranged so as to be included in one region DM_V. Specifically, four circuits PV are arranged in a matrix of two rows and two columns in one region DM_V.

[0258] 7, four circuits PX_R are arranged so as to be included in one region DM_R, four circuits PX_G are arranged so as to be included in one region DM_G, and four circuits PX_B are arranged so as to be included in one region DM_B. Specifically, as shown in FIG. 8, four circuits PX_R are arranged in a 2-row, 2-column matrix in one region DM_R, four circuits PX_G are arranged in a 2-row, 2-column matrix in one region DM_G, and four circuits PX_B are arranged in a 2-row, 2-column matrix in one region DM_B. Note that FIG. 8 shows an example of a circuit configuration in which, in the arrangement of circuits AP[i,j], circuit AP[i+1,j], circuit AP[i,j+1], and circuit AP[i+1,j+1] shown in FIG. 7, circuit PV of circuit AP[i+1,j+1] is illustrated in the lower right, and circuit PX_G of circuit AP[i-1,j-1] is illustrated in the upper left. Therefore, Figure 8 shows the entire circuit AP[i,j], as well as portions of circuit AP[i-1,j-1], circuit AP[i-1,j], circuit AP[i-1,j+1], circuit AP[i,j-1], circuit AP[i,j+1], circuit AP[i+1,j-1], circuit AP[i+1,j], and circuit AP[i+1,j+1].

[0259] In FIG. 7, the regions DM_V, DM_R, DM_G, and DM_B are indicated by long dashed lines.

[0260] As shown in Figure 8, by arranging four circuits PX_R, four circuits PX_G, four circuits PX_B, and four circuits PV, one circuit AP can be provided with circuits PX_R, circuits PX_G, circuits PX_B, and circuits PV.

[0261] In addition, in FIG. 8, the light-emitting devices included in the circuit PX_R arranged in a 2-row, 2-column matrix in the region DM_R can be formed using, for example, a photolithography method. Specifically, for example, materials for forming the light-emitting devices are sequentially stacked over the entire region DM_R. Examples of the method for stacking the materials include film formation methods such as CVD (Chemical Vapor Deposition), sputtering, vacuum deposition, spin coating, spray coating, and screen printing. Then, photolithography is used to divide the stacked materials into 2 rows and 2 columns, thereby forming four light-emitting devices. Using this fabrication method, a light-emitting device can be fabricated for each of the four circuits PX_R included in the region DM_R.

[0262] 8, for regions DM_G and DM_B, similarly to region DM_R, the laminate of materials constituting the light-emitting devices can be divided into a matrix of two rows and two columns using photolithography or the like, and four light-emitting devices can be formed in each region. This allows a light-emitting device to be fabricated for each of the four display pixel circuits included in each region.

[0263] 7 and 8, for region DM_V, as with region DM_R, the laminate of materials constituting the light-receiving device can be divided into a matrix of two rows and two columns using photolithography or the like, and four light-receiving devices can be formed in region DM_V. This allows a light-receiving device to be fabricated for each of the four circuits PV, which are imaging pixel circuits included in region DM_V.

[0264] 7 and 8 show an example in which, using photolithography or the like, display pixel circuits of two rows and two columns are formed in regions DM_R, DM_G, and DM_B, and imaging pixel circuits of two rows and two columns are formed in region DM_V. However, the formed display pixel circuits and imaging pixel circuits may be in a matrix other than two rows and two columns. For example, the display pixel circuits may be formed in a matrix of one or more rows and one or more columns in regions DM_R, DM_G, and DM_B. Similarly, the imaging pixel circuits may be formed in a matrix of one or more rows and one or more columns in region DM_V.

[0265] Each of the circuits AP[i,j], AP[i+1,j], AP[i,j+1], and AP[i+1,j+1] shown in FIG. 7 can perform imaging in the same manner as the semiconductor device described in the first embodiment (hereinafter, this operation will be referred to as the first operation). Furthermore, by electrically connecting each of the four circuits PV to each other in the region DM_V, imaging data captured by each of the four circuits PV can be added together, and the added data can be output as a single imaging data (hereinafter, this operation will be referred to as the second operation). The second operation can output imaging data captured by each of the four circuits PV as a single imaging data, thereby reducing the time required for reading the imaging data and shortening the time required for imaging and reading the imaging data. Furthermore, since the imaging data increases in size as a result of the second operation, the voltage handled by the circuit PV also increases. Therefore, the second operation may be able to increase the operating speed of the circuit PV compared to the first operation. Furthermore, the noise component in the imaging data obtained by the second operation is relatively lower than that obtained by the first operation. As a result, by configuring the circuit shown in Fig. 7, it is possible to increase the S / N ratio of the circuit in Fig. 7. Furthermore, the second operation is suitable for imaging in an environment where the amount of current generated in the light receiving device is small, such as a dark place, because imaging data is added together by each of the four circuits PV, for example.

[0266] In addition, in the above configuration, the region DM_V is described as including four circuit PVs as an example, but in a semiconductor device of one embodiment of the present invention, the number of circuit PVs included in the region DM_V may be two, three, or five or more.

[0267] 7, the circuit PX_R is electrically connected to the wiring SL_R[j], the wiring GL[i], and the wiring CT[i], the circuit PX_G is electrically connected to the wiring SL_G[j], the wiring GL[i], and the wiring CT[i], the circuit PX_B is electrically connected to the wiring SL_B[j], the wiring GL[i], and the wiring CT[i], and the circuit PV is electrically connected to the wiring OL[j], the wiring TX[i], the wiring RS[i], the wiring SE[i], and the wiring CT[i].

[0268] 7, the circuit PX_R is electrically connected to the wiring SL_R[j], the wiring GL[i+1], and the wiring CT[i+1], the circuit PX_G is electrically connected to the wiring SL_G[j], the wiring GL[i+1], and the wiring CT[i+1], the circuit PX_B is electrically connected to the wiring SL_B[j], the wiring GL[i+1], and the wiring CT[i+1], and the circuit PV is electrically connected to the wiring OL[j], the wiring TX[i+1], the wiring RS[i+1], the wiring SE[i+1], and the wiring CT[i+1].

[0269] 7, the circuit PX_R is electrically connected to the wiring SL_R[j+1], the wiring GL[i], and the wiring CT[i], the circuit PX_G is electrically connected to the wiring SL_G[j+1], the wiring GL[i], and the wiring CT[i], the circuit PX_B is electrically connected to the wiring SL_B[j+1], the wiring GL[i], and the wiring CT[i], and the circuit PV is electrically connected to the wiring OL[j+1], the wiring TX[i], the wiring RS[i], the wiring SE[i], and the wiring CT[i].

[0270] 7, the circuit PX_R is electrically connected to the wiring SL_R[j+1], the wiring GL[i+1], and the wiring CT[i+1], the circuit PX_G is electrically connected to the wiring SL_G[j+1], the wiring GL[i+1], and the wiring CT[i+1], the circuit PX_B is electrically connected to the wiring SL_B[j+1], the wiring GL[i+1], and the wiring CT[i+1], and the circuit PV is electrically connected to the wiring OL[j+1], the wiring TX[i+1], the wiring RS[i+1], the wiring SE[i+1], and the wiring CT[i+1].

[0271] In the region DM_V in FIGS. 7 and 8, the four circuits PV are electrically connected to one another.

[0272] 8, the wiring SL_G[j-1] is electrically connected to the circuit PX_G of the circuit AP[i-1,j-1] and the circuit PX_G of the circuit AP[i,j-1]. The wiring SL_B[j-1] is electrically connected to the circuit PX_B of the circuit AP[i,j-1] and the circuit PX_B of the circuit AP[i+1,j-1]. The wiring CT[i-1] is electrically connected to the circuit PX_G of the circuit AP[i-1,j-1], the circuit PX_G and the circuit PX_R of the circuit AP[i-1,j+1], and the circuit PX_R of the circuit AP[i-1,j+1]. In addition, the wiring GL[i-1] is electrically connected to the circuit PX_G of the circuit AP[i-1, j-1], the circuit PX_G and the circuit PX_R of the circuit AP[i-1, j], and the circuit PX_R of the circuit AP[i-1, j+1].

[0273] Each of the wirings SL_R shown in Figures 7 and 8 functions, for example, as a wiring that transmits image data signals to a circuit PX_R, which is a display pixel circuit. Each of the wirings SL_G shown in Figures 7 and 8 functions, for example, as a wiring that transmits image data signals to a circuit PX_G, which is a display pixel circuit. Each of the wirings SL_B shown in Figures 7 and 8 functions, for example, as a wiring that transmits image data signals to a circuit PX_B, which is a display pixel circuit. Each of the wirings SL_R, SL_G, and SL_B may be wiring that applies, for example, a constant potential or a variable potential (sometimes referred to as a pulse voltage).

[0274] 7 and 8 function as, for example, a wiring that transmits a selection signal for selecting a row including the circuit PX_R, the circuit PX_G, or the circuit PX_B that is a supply destination of the image data signal. Alternatively, the wiring GL may be, for example, a wiring that applies a constant voltage.

[0275] 7 and 8 function as, for example, a wiring that transmits a trigger signal for causing a light receiving device included in the circuit PV to capture an image. Alternatively, the wiring TX may function as, for example, a wiring that applies a constant voltage.

[0276] 7 and 8 function as wirings that transmit trigger signals for erasing imaging data captured by a light-receiving device included in the circuit PV. The erasing of imaging data can be rephrased as an initialization of a potential corresponding to the imaging data stored in the circuit PV, for example, in order to perform new imaging in the circuit PV. Alternatively, the wirings RS may be wirings that apply a constant voltage.

[0277] 7 and 8 show an example in which a wiring TX is provided for each row including a circuit PV, but if the timing of the trigger signals provided by the wirings TX of each row is the same, the wirings TX of each row may be combined into one wiring. Specifically, for example, in FIG. 7 or 8, the wirings TX[i] and TX[i+1] may be combined into one wiring.

[0278] In particular, by grouping the wirings TX extending to all rows containing circuits PV in the display area into the same wiring, and grouping the wirings RS extending to all rows containing circuits PV into the same wiring, all circuits PV included in the display area can simultaneously erase or acquire imaging data. In other words, the above-mentioned configuration enables imaging using a global shutter system. Furthermore, in the display area shown in Figures 7 and 8, by sequentially transmitting trigger signals to each of the multiple wirings TX extending to all rows containing circuits PV and to one or the other of the multiple wirings RS, imaging using a rolling shutter system can be performed.

[0279] 7 and 8 show an example in which the wiring RS is extended for each row including the circuit PV, but if the timing of the trigger signals provided by the wiring RS of each row is the same, the wiring RS of each row may be combined into one wiring. Specifically, for example, in FIG. 7 or 8, the wiring RS[i] and the wiring RS[i+1] may be combined into one wiring.

[0280] 7 and 8 function as, for example, a wiring for transmitting a trigger signal for reading out imaging data captured by a light receiving device included in the circuit PV. Alternatively, the wiring SE may function as, for example, a wiring for applying a constant potential.

[0281] 7 and 8 function as wirings that transmit, as signals, image data captured by a light-receiving device included in the circuit PV. Alternatively, the wirings OL may be wirings that apply, for example, a constant potential or a variable potential (sometimes called a pulse voltage).

[0282] Each of the wirings CT shown in Figures 7 and 8 functions as a wiring that applies a constant potential to, for example, the circuit PX_R, the circuit PX_G, the circuit PX_B, and the circuit PV. Furthermore, as an example, the wiring CT is electrically connected to a terminal of a light-emitting device included in the circuit PX and to a terminal of a light-receiving device included in the circuit PV. In this case, the constant potential is preferably, for example, a ground potential or a negative potential. Alternatively, the wiring CT may be, for example, a wiring that applies a variable potential (sometimes called a pulse voltage).

[0283] 7 and 8 show examples in which the wiring CT is provided for each row, but if the constant potentials applied by the wiring CT of each row are equal, the wiring CT of each row may be combined into a single wiring. Specifically, for example, in FIG. 7, the wiring CT[i] and the wiring CT[i+1] may be combined into a single wiring. Also, for example, in FIG. 8, the wiring CT[i-1], the wiring CT[i], and the wiring CT[i+1] may be combined into a single wiring.

[0284] 7 and 8, various wirings are shown, but wirings other than wirings SL_R, SL_G, SL_B, wirings GL, wirings TX, RS, wirings SE, wirings OL, and wirings CT may be electrically connected to at least one of circuits PX_R, PX_G, PX_B, and circuits PV. For example, although not shown in FIG. 7, wirings that provide a power supply voltage for driving one or more selected from circuits PX_R, PX_G, PX_B, and PV may be electrically connected to circuit AP.

[0285] Furthermore, at least one of the various wirings shown in Figures 7 and 8 may be provided in multiple numbers instead of one. For example, each of the wirings GL shown in Figures 7 and 8 may be provided in multiple numbers instead of one. For example, each of the wirings RS shown in Figures 7 and 8 may be provided in multiple numbers instead of one. For example, each of the wirings TX shown in Figures 7 and 8 may be provided in multiple numbers instead of one.

[0286] <Example 1> Fig. 9 shows an example of a circuit configuration that can be applied to four circuits PV included in the region DM_V in Fig. 7 and Fig. 8. Note that the region DM_V in Fig. 9 shows the circuits PV included in each of the circuit AP[i,j], circuit AP[i+1,j], circuit AP[i,j+1], and circuit AP[i+1,j+1].

[0287] The four circuits PV included in the region DM_V shown in Figures 7 and 8 are designated as circuit PV1, circuit PV2, circuit PV3, and circuit PV4 in the region DM_V shown in Figure 9. For example, circuit PV1 corresponds to the circuit PV included in circuit AP[i,j], circuit PV2 corresponds to the circuit PV included in circuit AP[i,j+1], circuit PV3 corresponds to the circuit PV included in circuit AP[i+1,j], and circuit PV4 corresponds to the circuit PV included in circuit AP[i+1,j+1].

[0288] The circuit PV1 includes transistors M1 to M6, a capacitor CV1, and a light-receiving device PD.

[0289] Furthermore, each of the circuits PV2 to PV4 includes transistors M1 to M5 and a transistor M7, a capacitor CV1, and a light-receiving device PD.

[0290] As the transistors M1 to M7, for example, the transistors Tr1, Tr2, Tr5, and Tr6 described in Embodiment 1 or transistors applicable to the transistors M1 to M5 can be used.

[0291] In the circuit PV1, for example, the first terminal of the transistor M1 is electrically connected to the wiring OL[j], the gate of the transistor M1 is electrically connected to the wiring SE[i], and the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2. The second terminal of the transistor M2 is electrically connected to the wiring VDE, and the gate of the transistor M2 is electrically connected to the first terminal of the transistor M3 and the first terminal of the capacitor CV1. The second terminal of the transistor M3 is electrically connected to the wiring VR2, and the gate of the transistor M3 is electrically connected to the wiring RS2[i]. The second terminal of the capacitor CV1 is electrically connected to the first terminal of the transistor M4, the first terminal of the transistor M5, and the first terminal of the transistor M6. The second terminal of the transistor M4 is electrically connected to the wiring VR1, and the gate of the transistor M4 is electrically connected to the wiring RS1[i]. The second terminal of the transistor M5 is electrically connected to the second terminal of the transistor M6 and the anode of the light receiving device PD, the gate of the transistor M5 is electrically connected to the wiring TX1[i], the gate of the transistor M6 is electrically connected to the wiring TX2[i], and the cathode of the light receiving device PD is electrically connected to the wiring CT[i].

[0292] In the circuit PV2, for example, the first terminal of the transistor M1 is electrically connected to the wiring OL[j+1], the gate of the transistor M1 is electrically connected to the wiring SE[i], and the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2. The second terminal of the transistor M2 is electrically connected to the wiring VDE, and the gate of the transistor M2 is electrically connected to the first terminal of the transistor M3 and the first terminal of the capacitor CV1. The second terminal of the transistor M3 is electrically connected to the wiring VR2, and the gate of the transistor M3 is electrically connected to the wiring RS2[i]. The second terminal of the capacitor CV1 is electrically connected to the first terminal of the transistor M4 and the first terminal of the transistor M5. The second terminal of the transistor M4 is electrically connected to the wiring VR1, and the gate of the transistor M4 is electrically connected to the wiring RS1[i]. The second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M7 and the anode of the light receiving device PD, the gate of the transistor M5 is electrically connected to the wiring TX1[i], the gate of the transistor M7 is electrically connected to the wiring TX2[i], and the cathode of the light receiving device PD is electrically connected to the wiring CT[i].

[0293] In the circuit PV3, for example, the first terminal of the transistor M1 is electrically connected to the wiring OL[j], the gate of the transistor M1 is electrically connected to the wiring SE[i+1], and the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2. The second terminal of the transistor M2 is electrically connected to the wiring VDE, and the gate of the transistor M2 is electrically connected to the first terminal of the transistor M3 and the first terminal of the capacitor CV1. The second terminal of the transistor M3 is electrically connected to the wiring VR2, and the gate of the transistor M3 is electrically connected to the wiring RS2[i+1]. The second terminal of the capacitor CV1 is electrically connected to the first terminal of the transistor M4 and the first terminal of the transistor M5. The second terminal of the transistor M4 is electrically connected to the wiring VR1, and the gate of the transistor M4 is electrically connected to the wiring RS1[i+1]. The second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M7 and the anode of the light receiving device PD, the gate of the transistor M5 is electrically connected to the wiring TX1[i+1], the gate of the transistor M7 is electrically connected to the wiring TX2[i+1], and the cathode of the light receiving device PD is electrically connected to the wiring CT[i+1].

[0294] In the circuit PV4, for example, the first terminal of the transistor M1 is electrically connected to the wiring OL[j+1], the gate of the transistor M1 is electrically connected to the wiring SE[i+1], and the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2. The second terminal of the transistor M2 is electrically connected to the wiring VDE, and the gate of the transistor M2 is electrically connected to the first terminal of the transistor M3 and the first terminal of the capacitor CV1. The second terminal of the transistor M3 is electrically connected to the wiring VR2, and the gate of the transistor M3 is electrically connected to the wiring RS2[i+1]. The second terminal of the capacitor CV1 is electrically connected to the first terminal of the transistor M4 and the first terminal of the transistor M5. The second terminal of the transistor M4 is electrically connected to the wiring VR1, and the gate of the transistor M4 is electrically connected to the wiring RS1[i+1]. The second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M7 and the anode of the light receiving device PD, the gate of the transistor M5 is electrically connected to the wiring TX1[i+1], the gate of the transistor M7 is electrically connected to the wiring TX2[i+1], and the cathode of the light receiving device PD is electrically connected to the wiring CT[i+1].

[0295] Furthermore, the second terminal of the transistor M7 of the circuit PV2 is electrically connected to the second terminal of the transistor M7 of the circuit PV3 and the second terminal of the transistor M7 of the circuit PV4.

[0296] In this specification, in each of the circuits PV1 to PV4, the electrical connection point between the gate of the transistor M2, the gate of the transistor M3, and the first terminal of the capacitor CV1 is referred to as node N2. In the circuit PV1, the electrical connection point between the second terminal of the capacitor CV1, the first terminal of the transistor M4, the first terminal of the transistor M5, and the first terminal of the transistor M6 is referred to as node N1. Similarly, in the circuits PV2 to PV4, the electrical connection point between the second terminal of the capacitor CV1, the first terminal of the transistor M4, and the first terminal of the transistor M5 is referred to as node N1.

[0297] For the wiring VR1, the wiring VR2, and the wiring VDE, the descriptions of the wiring VR1, the wiring VR2, and the wiring VDE in the first embodiment should be referred to.

[0298] The wiring TX1[i] and the wiring TX2[i] shown in Fig. 9 correspond to the wiring TX[i] shown in Fig. 7 and Fig. 8. Similarly, the wiring TX1[i+1] and the wiring TX2[i+1] shown in Fig. 9 correspond to the wiring TX[i+1] shown in Fig. 7 and Fig. 8.

[0299] 9 correspond to the wiring RS[i] shown in Fig. 7 and 8. Similarly, the wiring RS1[i+1] and wiring RS2[i+1] shown in Fig. 9 correspond to the wiring RS[i+1] shown in Fig. 7 and 8.

[0300] In addition, the wirings TX1[i] and TX1[i+1] shown in Figure 9 may be combined into the same wiring, the wirings TX2[i] and TX2[i+1] may be combined into the same wiring, the wirings RS1[i] and RS1[i+1] may be combined into the same wiring, the wirings RS2[i] and RS2[i+1] may be combined into the same wiring, and the wirings CT[i] and CT[i+1] may be combined into the same wiring.

[0301] Specifically, for example, the configuration of the wiring extending into the region DM_V shown in Fig. 9 may be changed to the configuration of the wiring extending into the region DM_V shown in Fig. 11. In Fig. 11, the wiring TX1[i] and wiring TX1[i+1] of Fig. 9 are combined into wiring TX1(i, i+1), the wiring TX2[i] and wiring TX2[i+1] of Fig. 9 are combined into wiring TX2(i, i+1), the wiring RS1[i] and wiring RS1[i+1] of Fig. 9 are combined into wiring RS1(i, i+1), the wiring RS2[i] and wiring RS2[i+1] of Fig. 9 are combined into wiring RS2(i, i+1), and the wiring CT[i] and wiring CT[i+1] of Fig. 9 are combined into wiring CT(i, i+1).

[0302] 7 and 8, the four circuits PV included in the region DM_V are preferably imaging pixel circuits that receive light of the same color. For example, the color of light that can be received by the four circuits PV included in the region DM_V may be one color selected from red (R), green (G), blue (B), cyan, magenta, yellow, and white.

[0303] Furthermore, when the display device includes a plurality of regions DM_V in the display region, the color of light that can be received by the four circuits PV of the region DM_V may be different for each region DM_V. A specific example of this will be described below.

[0304] The block diagram shown in Fig. 10 is an example of the configuration of a display area having four imaging pixel circuits, circuits PV_Y, PV_R, PV_G, and PV_B, that receive light of different colors. Specifically, the display area of ​​Fig. 10 includes a region DM_V including four circuits PV_Y, a region DM_V including four circuits PV_R, a region DM_V including four circuits PV_G, and a region DM_V including four circuits PV_B. For example, the circuit PV_Y may be an imaging pixel circuit that receives yellow light, the circuit PV_R may be an imaging pixel circuit that receives red light, the circuit PV_G may be an imaging pixel circuit that receives green light, and the circuit PV_B may be an imaging pixel circuit that receives blue light.

[0305] 10. The four imaging pixel circuits included in each region DM_V shown in FIG. 10 correspond to the four circuits PV1 to PV4 included in the region DM_V in FIG. 9 or FIG.

[0306] Focusing on the multiple regions DM_V located in the kth row (k is an integer greater than or equal to 1) and the k+1th row, two circuits PV_Y and two circuits PV_R are arranged side by side from the left. Focusing on the multiple regions DM_V located in the k+2th row and the k+3th row, two circuits PV_B and two circuits PV_G are arranged side by side from the left. Focusing on the circuits included in the region DM_V located in the hth column (h is an integer greater than or equal to 1) and the h+1th column, two circuits PV_Y and two circuits PV_B are arranged side by side from the top. Focusing on the circuits included in the region DM_V located in the h+2th column and the h+3th column, two circuits PV_R and two circuits PV_G are arranged side by side from the top.

[0307] 10, in the plurality of regions DM_V located on the kth and k+1th rows, the imaging pixel circuits may be arranged in a repeated order of two circuits PV_Y, two circuits PV_R, two circuits PV_Y, and two circuits PV_R. Furthermore, in the plurality of regions DM_V located on the k+2th and k+3th rows, the imaging pixel circuits may be arranged in a repeated order of two circuits PV_B, two circuits PV_G, two circuits PV_B, and two circuits PV_G. Furthermore, in the plurality of regions DM_V located on the hth and h+1th columns, the imaging pixel circuits may be arranged in a repeated order of two circuits PV_Y, two circuits PV_B, two circuits PV_Y, and two circuits PV_B. In addition, in multiple regions DM_V located in the h+2th and h+3rd columns, the imaging pixel circuits may be arranged in a repeated sequence of two circuits PV_R, two circuits PV_G, two circuits PV_R, and two circuits PV_G.

[0308] 10 is configured to receive four colors of light, it may be configured to receive three or fewer colors of light, or five or more colors of light. In this case, the colors of the received light may be three or fewer colors, or five or more colors, selected from red (R), green (G), blue (B), cyan, magenta, yellow, and white.

[0309] <<Example 1>> Next, a first example of the operation of the circuits PV1 to PV4 included in the area DM_V in FIG. 11 will be described.

[0310] FIG. 12 is a timing chart showing an example of a first operation of the circuits PV1 to PV4 included in the region DM_V in FIG. The timing chart in FIG. 12 shows, as an example, changes in the potential of the wirings RS1(i, i+1), RS2(i, i+1), TX1(i, i+1), TX2(i, i+1), SE[i], SE[i+1], the nodes N1 and N2 of the circuit PV1 (referred to as N1(PV1) and N2(PV1) in FIG. 12), the nodes N1 and N2 of the circuit PV2 (referred to as N1(PV2) and N2(PV2) in FIG. 12), the nodes N1 and N2 of the circuit PV3 (referred to as N1(PV3) and N2(PV3) in FIG. 12), the nodes N1 and N2 of the circuit PV4 (referred to as N1(PV4) and N2(PV4) in FIG. 12), the wiring OL[j], and the wiring OL[j+1] from time T21 to time T29 and in the vicinity thereof.

[0311] In this example, the high-level potential given by the wiring RS1(i, i+1) is V High1 The low level potential given by the wiring RS1(i,i+1) is V Low1 In addition, the high level potential given by the wiring RS2(i,i+1) is V High2 The low level potential given by wiring RS2(i,i+1) is V Low2 In addition, the high level potential given by the wiring TX1(i, i+1) is V High3 The low level potential given by the wiring TX1(i,i+1) is V Low3 In addition, the high level potential given by the wiring TX2(i,i+1) is V High5 The low level potential given by the wiring TX1(i,i+1) is V Low5 In addition, the high-level potential given by the wiring SE[i] is V High4 The low-level potential given by the wiring SE[i] is V Low4 In addition, the high level potential given by the wiring SE[i+1] is V High6The low level potential given by the wiring SE[i+1] is V Low6 Let's say.

[0312] In this example, the constant potential given by the wiring VR1 is V CATH The constant potential given by the wiring VR2 is V LVSH In addition, the constant potential given by the wiring VDE is V DD Also, the constant potential given by the wiring CT is set to V, the same as the constant potential given by the wiring VR1. CATH Let's say.

[0313] Furthermore, before time T21, the wiring OL[j] and the wiring OL[j+1] are connected to, for example, V PRE is precharged. Note that V is applied to the wiring OL[j] and wiring OL[j+1]. PRE The timing for precharging does not have to be before time T21, but may be any time between time T21 and time T25.

[0314] In this example, V LVSH is V CATH The potential is higher than V LVSH and V PRE and may be at the same potential. DD is V CATH , V LVSH , and V PRE The potential is set to be higher than

[0315] Also, V High4 and V PRE Each of the V High4 and V PRE The difference between V and V is higher than the threshold voltage of transistor M4. Low4 and V PRE Each of the V Low4 and V PRE The potential is set so that the difference between these is equal to or less than the threshold voltage of the transistor M4.

[0316] Also, V High6 is V High4 It may also be a potential equal to V Low6 is VLow4 The potential may be equal to

[0317] Also, V High1 and V CATH Each of the V High1 and V CATH The difference between V and V is higher than the threshold voltage of transistor M4. Low1 and V CATH Each of the V Low1 and V CATH The difference between V and V is equal to or less than the threshold voltage of transistor M4. High2 and V LVSH Each of the V High2 and V LVSH The difference between V and V is higher than the threshold voltage of transistor M3. Low2 and V LVSH Each of the V Low2 and V LVSH The difference between V and V is equal to or less than the threshold voltage of transistor M3. High3 and V CATH Each of the V High3 and V CATH The difference between V and V is higher than the threshold voltage of transistor M5. Low3 and V CATH Each of the V Low3 and V CATH The potential is set so that the difference between these is equal to or less than the threshold voltage of the transistor M5.

[0318] Also, V High5 and V CATH Each of the V High5 and V CATH The difference between these potentials is higher than the threshold voltages of the transistors M6 and M7. Low5 and V CATH Each of the V Low5 and V CATH The potential is set so that the difference between these potentials is equal to or less than the threshold voltages of the transistors M6 and M7.

[0319] From the above, when the threshold voltages of the transistors M4 to M7 are approximately equal, V High1 and V High3 and V High5 and may be at equal potentials, and V Low1 and V Low3 and V Low5 and may be at the same potential.

[0320] [From time T21 to time T22] Between time T21 and time T22, the wiring TX1(i,i+1) is supplied with a low-level potential (V Low3 ) is input, and the low-level potential (V Low5 ) is input, and the low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is input, and the low-level potential (V Low4 ) is input, and the low-level potential (V Low6 ) is entered.

[0321] In addition, the potentials of the nodes N1 and N2 of the circuit PV1 from time T21 to time T22 are V ini11 , V ini12 The potentials of the nodes N1 and N2 of the circuit PV2 are V ini21 , V ini22 The potentials of the nodes N1 and N2 of the circuit PV3 are V ini31 , V ini32 The potentials of the nodes N1 and N2 of the circuit PV4 are V ini41 , V ini42 In addition, V ini11 , V ini12 , V ini21 , V ini22 , V ini31 , V ini32 , V ini41 , and V ini42 As an example, each of CATH The potential is equal to or greater than V ini11 , V ini12 , Vini21 , V ini22 , V ini31 , V ini32 , V ini41 , and V ini42 can be set to potentials corresponding to the imaging data captured by the circuits PV1 to PV4, respectively, at a time before time T21.

[0322] In each of the circuits PV1 to PV4, the gate of the transistor M4 is supplied with a low-level potential (V Low1 ) is applied, and the gate-source voltage of transistor M4 becomes V Low1 -V CATH V Low1 -V CATH is equal to or less than the threshold voltage of transistor M4, so transistor M4 is in the off state.

[0323] In each of the circuits PV1 to PV4, the gate of the transistor M5 receives a low-level potential (V Low3 ) is applied. At this time, the gate-source voltage of the transistor M5 becomes equal to or lower than the threshold voltage of the transistor M5, and the transistor M5 is turned off.

[0324] In each of the circuits PV1 to PV4, the gate of the transistor M3 is supplied with a low-level potential (V Low2 ) is applied, and the gate-source voltage of transistor M3 becomes V Low2 -V LVSH V Low2 -V LVSH is equal to or less than the threshold voltage of the transistor M3, so the transistor M3 is in an off state.

[0325] In each of the circuits PV1 and PV2, the gate of the transistor M1 is supplied with a low-level potential (V Low4) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0326] Similarly, in each of the circuits PV3 and PV4, the gate of the transistor M1 is supplied with a low-level potential (V Low6 ) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0327] In the circuits PV1 to PV4, the potential of the first terminal of the transistor M2 is V DD and the first terminal of the transistor M2 functions as a source. Note that although the transistor M2 is turned on depending on the gate-source voltage of the transistor M2, as described above, the transistor M1 is turned off. Therefore, in the circuits PV1 and PV3, no current flows from the wiring VDE to the wiring OL[j] via the transistors M2 and M1, and in the circuits PV2 and PV4, no current flows from the wiring VDE to the wiring OL[j+1] via the transistors M2 and M1.

[0328] [From time T22 to time T23] Between time T22 and time T23, the wiring RS1(i,i+1) is supplied with a high-level potential (V High1 ) is input, and the high-level potential (V High2 ) is input to the wiring TX1(i,i+1). High3 ) is input, and the low-level potential (V Low5 ) is entered.

[0329] At this time, in each of the circuits PV1 to PV4, the gate of the transistor M4 receives a high-level potential (V High1) is applied, and the gate-source voltage of transistor M4 becomes V High1 -V CATH V High1 -V CATH is greater than the threshold voltage of the transistor M4, the transistor M4 is turned on. Therefore, conduction is established between the wiring VR1 and the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1), and the potential of the first terminal of the transistor M5 (the second terminal of the capacitor CV1 or the node N1) becomes V CATH In the case of the circuit PV1, the potential of the first terminal of the transistor M6 is also V CATH This becomes:

[0330] In each of the circuits PV1 to PV4, the gate of the transistor M5 receives a high-level potential (V High3 ) is applied, and the gate-source voltage of transistor M5 becomes V High3 -V CATH V High3 -V CATH is greater than the threshold voltage of the transistor M5, the transistor M5 is turned on. Therefore, the line VR1 and the anode of the light receiving device PD are electrically connected, and the potential of the anode of the light receiving device PD is V CATH This becomes:

[0331] In the circuit PV1, the gate of the transistor M6 is supplied with a low-level potential (V Low5 ) is applied, and the potentials of the first terminal (node ​​N1) and the second terminal of the transistor M6 are V CATH As a result, the voltage between the gate and the first terminal of the transistor M6 (the voltage between the gate and the second terminal) becomes V Low5 -V CATH As a result, the transistor M6 is turned off.

[0332] In each of the circuits PV2 to PV4, the gate of the transistor M7 is supplied with a low-level potential (V Low5) is applied to the first and second terminals of the transistor M7 (node ​​N1 of the circuit PV1). CATH Therefore, the voltage between the gate and the first terminal of the transistor M7 (the voltage between the gate and the second terminal) is V Low5 -V CATH As a result, the transistor M7 is turned off.

[0333] At this time, in each of the circuits PV1 to PV4, the voltage between the anode and cathode of the light receiving device PD is 0V, and therefore, no current flows between the anode and cathode of the light receiving device PD.

[0334] In each of the circuits PV1 to PV4, the gate of the transistor M3 is supplied with a high-level potential (V High2 ) is applied, and the gate-source voltage of transistor M3 becomes V High2 -V LVSH V High2 -V LVSH is greater than the threshold voltage of the transistor M3, the transistor M3 is turned on. Therefore, electrical continuity is established between the wiring VR2 and the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2), and the potential of the gate of the transistor M2 (the first terminal of the capacitor CV1 or the node N2) becomes V LVSH This becomes:

[0335] In the circuits PV1 to PV4, from time T22 to time T23, as described above, V LVSH is applied to the second terminal of the transistor M2, and the potential V DD Here, as in the period from time T21 to time T22, the potential of the first terminal of the transistor M2 is V DD, and the first terminal of the transistor M2 functions as a source. Note that although the transistor M2 may be turned on depending on the gate-source voltage of the transistor M2, it is preferable that the transistor M2 be in an off state between time T22 and time T23. Furthermore, since the transistor M1 is in an off state as in the period between time T21 and time T22, in the circuits PV1 and PV3, no current flows from the wiring VDE to the wiring OL[j] via the transistors M2 and M1, and in the circuits PV2 and PV4, no current flows from the wiring VDE to the wiring OL[j+1] via the transistors M2 and M1.

[0336] [From time T23 to time T24] Between time T23 and time T24, the wiring RS1(i,i+1) is supplied with a low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is entered.

[0337] In each of the circuits PV1 to PV4, the gate of the transistor M4 is supplied with a low-level potential (V Low1 ) is applied, and the gate-source voltage of transistor M4 becomes V Low1 -V CATH V Low1 -V CATH is equal to or less than the threshold voltage of transistor M4, so transistor M4 is turned off.

[0338] In each of the circuits PV1 to PV4, the gate of the transistor M3 is supplied with a low-level potential (V Low2 ) is applied, and the gate-source voltage of transistor M3 becomes V Low2 -V LVSH V Low2 -V LVSHis equal to or lower than the threshold voltage of the transistor M3, the transistor M3 is turned off, and therefore the first terminal (node ​​N2) of the capacitor CV1 is in a floating state.

[0339] The transistor M5 of each of the circuits PV1 to PV4 continues to be in the on state from before time T23.

[0340] When light is irradiated onto the light-receiving device PD of each of the circuits PV1 to PV4, a current flows from the cathode to the anode of the light-receiving device PD. Furthermore, because transistor M4 is off and transistor M5 is on, a positive charge due to the current flows to node N1 and accumulates in the second terminal of capacitor CV1 for the duration that transistor M5 is on. If transistor M5 is turned off at time T24, the potential of the second terminal of capacitor CV1 (node ​​N1) continues to increase from time T23 to time T24.

[0341] Between time T23 and time T24, the amount of positive charge accumulated in the second terminal (node ​​N1) of the capacitance CV1 is determined depending on the amount of current flowing through the light-receiving device PD, and therefore the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 is determined. Also, the amount of current flowing through the light-receiving device PD is determined by the intensity of light incident on the light-receiving device PD. In this operation example, as an example, when each of the light-receiving devices PD of the circuits PV1 to PV4 receives light, the potential of the node N1 of the circuit PV1 becomes V CATH From V CATH +V PD1 The potential of the node N1 in the circuit PV2 changes to V CATH From V CATH +V PD2 The potential of the node N1 in the circuit PV3 changes to V CATH From V CATH +V PD3 The potential of the node N1 of the circuit PV4 changes to V CATH From V CATH +V PD4 It is assumed that the value changes to

[0342] Furthermore, between time T23 and time T24, the first terminal (node ​​N2) of the capacitor CV1 of each of the circuits PV1 to PV4 is in a floating state. Therefore, due to the capacitive coupling of the capacitor CV1, the potential of the second terminal (node ​​N1) of the capacitor CV1 rises, and the potential of the first terminal (node ​​N2) of the capacitor CV1 also rises. The amount of change in the potential of the first terminal (node ​​N2) of the capacitor CV1 is calculated by multiplying the amount of change in the potential of the second terminal (node ​​N1) of the capacitor CV1 by a capacitive coupling coefficient determined by the peripheral configuration of the first terminal (node ​​N2) of the capacitor CV1. The capacitive coupling coefficient is calculated, for example, from the capacitance value of the capacitor CV1, the gate capacitance of the transistor M2, and the parasitic capacitance. Here, let p be the capacitive coupling coefficient of the capacitor CV1 of each of the circuits PV1 to PV4. When each of the light-receiving devices PD of the circuits PV1 to PV4 receives light, the potential of the first terminal (node ​​N2) of the capacitor CV1 of the circuit PV1 rises to V. LVSH From V LVSH +pV PD1 The potential at the first terminal (node ​​N2) of the capacitor CV1 in the circuit PV2 changes to V LVSH From V LVSH +pV PD2 The potential at the first terminal (node ​​N2) of the capacitor CV1 in the circuit PV3 changes to V LVSH From V LVSH +pV PD3 The potential at the first terminal (node ​​N2) of the capacitor CV1 in the circuit PV4 changes to V LVSH From V LVSH +pV PD4 It is assumed that the value changes to

[0343] [From time T24 to time T25] At time T24, the wiring TX1(i,i+1) is at a low level potential (V Low3 ) is entered.

[0344] At this time, the gate of the transistor M5 in each of the circuits PV1 to PV4 receives a low-level potential (V Low3) is applied. At this time, the gate-source voltage of the transistor M5 becomes equal to or lower than the threshold voltage of the transistor M5, and the transistor M5 is turned off.

[0345] This completes the accumulation of positive charge (potential increase) at the first terminal (node ​​N2) of capacitance CV1 due to the current flowing between the anode and cathode of each light receiving device PD of circuits PV1 to PV4 during the operation from time T23 to time T24.

[0346] [From time T25 to time T26] Between time T25 and time T26, the wiring SE[i] is supplied with a high-level potential (V High4 ) is entered.

[0347] In each of the circuits PV1 and PV2, the gate of the transistor M1 receives a high-level potential (V High4 ) is applied. At this time, the gate-source voltage of transistor M1 is V High4 -V PRE V High4 -V PRE is greater than the threshold voltage of transistor M1, so transistor M1 is turned on.

[0348] In the circuit PV1, between time T25 and time T26, the gate of the transistor M2 is connected to V LVSH +pV PD1 is applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL[j]. PRE is applied.

[0349] At this time, the gate-source voltage of transistor M2 in circuit PV1 is V LVSH +pV PD1 -V PREThe gate-source voltage V LVSH +pV PD1 -V PRE A current corresponding to the voltage flows. At this time, since the wiring OL[j] is in a floating state, the potential of the wiring OL[j] rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL[j] at this time is V OUT1 Let's say.

[0350] In the circuit PV2, between time T25 and time T26, V LVSH +pV PD2 is applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the wiring OL[j+1]. PRE is applied.

[0351] At this time, the gate-source voltage of transistor M2 in circuit PV2 is V LVSH +pV PD2 -V PRE The gate-source voltage V LVSH +pV PD2 -V PRE At this time, since the wiring OL[j+1] is in a floating state, the potential of the wiring OL[j+1] rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL[j+1] at this time is V OUT2 Let's say.

[0352] [From time T26 to time T27] Between time T26 and time T27, the wiring SE[i] is supplied with a low-level potential (V Low4 ) is entered.

[0353] The gates of the transistors M1 in the circuits PV1 and PV2 are connected to a low-level potential (V Low4 ) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0354] At this time, by reading out the potentials of the wiring OL[j] and wiring OL[j+1], it is possible to obtain the imaging data captured by the light receiving devices PD of the circuits PV1 and PV2 between time T23 and time T24.

[0355] [From time T27 to time T28] Between time T27 and time T28, the wiring OL[j] and the wiring OL[j+1] are supplied with a potential V PRE As a result, the potential of the wiring OL[j] read from the circuit PV1 and the potential of the wiring OL[j+1] read from the circuit PV2 are precharged to the initial state potential (V PRE ) can be reset to

[0356] [From time T28 to time T29] Between time T28 and time T29, the wiring SE[i+1] is supplied with a high-level potential (V High6 ) is entered.

[0357] In each of the circuits PV3 and PV4, the gate of the transistor M1 receives a high-level potential (V High6 ) is applied. At this time, the gate-source voltage of transistor M1 is V High6 -VPRE V High6 -V PRE is greater than the threshold voltage of transistor M1, so transistor M1 is turned on.

[0358] In the circuit PV3, between time T28 and time T29, the gate of the transistor M2 is connected to V LVSH +pV PD3 is applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL[j]. PRE is applied.

[0359] At this time, the gate-source voltage of transistor M2 in circuit PV3 is V LVSH +pV PD3 -V PRE The gate-source voltage V LVSH +pV PD3 -V PRE A current corresponding to the voltage flows. At this time, since the wiring OL[j] is in a floating state, the potential of the wiring OL[j] rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL[j] at this time is V OUT3 Let's say.

[0360] In the circuit PV4, between time T28 and time T29, the gate of the transistor M2 is connected to V LVSH +pV PD4 is applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the wiring OL[j+1]. PREis applied.

[0361] At this time, the gate-source voltage of transistor M2 in circuit PV4 is V LVSH +pV PD4 -V PRE The gate-source voltage V LVSH +pV PD4 -V PRE At this time, since the wiring OL[j+1] is in a floating state, the potential of the wiring OL[j+1] rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL[j+1] at this time is V OUT4 Let's say.

[0362] [After time T29] After time T29, the wiring SE[i+1] is supplied with a low-level potential (V Low6 ) is entered.

[0363] The gates of the transistors M1 in the circuits PV3 and PV4 are connected to a low-level potential (V Low6 ) is applied. At this time, the gate-source voltage of the transistor M1 becomes equal to or lower than the threshold voltage of the transistor M1, and the transistor M1 is turned off.

[0364] At this time, by reading out the potentials of the wiring OL[j] and wiring OL[j+1], it is possible to obtain the imaging data captured by the light receiving devices PD of the circuits PV3 and PV4 between time T23 and time T24.

[0365] Note that the operation of the semiconductor device of one embodiment of the present invention is not limited to the operation example of the timing chart in FIG. 12 and may be modified as appropriate within the scope of solving the problem.

[0366] 12, high-level potentials are simultaneously input to the wirings RS1(i,i+1), RS2(i,i+1), and TX1(i,i+1). However, the operation of the semiconductor device of one embodiment of the present invention may be such that high-level potentials are input to the wirings RS1(i,i+1), RS2(i,i+1), and TX1(i,i+1) in any order from time T22 to time T23. Specifically, for example, after inputting a high-level potential to the wiring RS1(i,i+1), a high-level potential may be input to the wiring RS2(i,i+1), and then a high-level potential may be input to the wiring TX1(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring RS1(i,i+1) and then a high-level potential may be input to the wiring TX1(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring TX1(i,i+1), and then a high-level potential may be input to the wiring RS1(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring TX1(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1), and then a high-level potential may be input to the wiring RS1(i,i+1).

[0367] <<Example 2>> Next, a second operation example of the circuits PV1 to PV4 included in the area DM_V in FIG. 11 will be described.

[0368] FIG. 13 is a timing chart showing an example of the second operation of the circuits PV1 to PV4 included in the region DM_V in FIG. The timing chart in FIG. 13 shows, as an example, changes in the potential of the wirings RS1(i, i+1), RS2(i, i+1), TX1(i, i+1), TX2(i, i+1), SE[i], SE[i+1], the nodes N1 and N2 of the circuit PV1 (referred to as N1(PV1) and N2(PV1) in FIG. 13), the nodes N1 and N2 of the circuit PV2 (referred to as N1(PV2) and N2(PV2) in FIG. 13), the nodes N1 and N2 of the circuit PV3 (referred to as N1(PV3) and N2(PV3) in FIG. 13), the nodes N1 and N2 of the circuit PV4 (referred to as N1(PV4) and N2(PV4) in FIG. 13), the wiring OL[j], and the wiring OL[j+1] from time T31 to time T36 and in the vicinity thereof.

[0369] In the description of the operation example of the circuit AP in FIG. 11, the description of the same parts as those in the timing chart in FIG. 12 may be omitted.

[0370] [From time T31 to time T32] Between time T31 and time T32, similarly to the period from time T21 to time T22 in the timing chart of FIG. 12, the wiring TX1(i, i+1) is supplied with a low-level potential (V Low3 ) is input, and the low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is input, and the low-level potential (V Low4 ) is input, and the low-level potential (V Low6) is input. The potentials applied to the wirings TX1(i, i+1), TX2(i, i+1), RS1(i, i+1), RS2(i, i+1), SE[i], and SE[i+1] are the same as the potentials supplied to the wirings described above from time T21 to time T22 in the timing chart of FIG. 12. Therefore, for the switching operations of the transistors M1 to M7 included in the region DM_V, refer to the operation example from time T21 to time T22 in the timing chart of FIG. 12.

[0371] [From time T32 to time T33] Between time T32 and time T33, similarly to the period from time T22 to time T23 in the timing chart of FIG. 12, the wiring RS1(i, i+1) is supplied with a high-level potential (V High1 ) is input, and the high-level potential (V High2 ) is entered.

[0372] Between time T32 and time T33, the wiring TX1(i,i+1) continues to be supplied with a low-level potential (V Low3 ) is input, and the high-level potential (V High5 ) is input. In this respect, this operation example differs from operation example 1 of the present embodiment.

[0373] Regarding the switching operation of the transistor M4 in each of the circuits PV1 to PV4, an example of operation from time T22 to time T23 in the timing chart of Fig. 12 is referred to. Specifically, in each of the circuits PV1 to PV4, the gate of the transistor M4 is supplied with a high-level potential (V High1 ) is applied to transistor M4, turning it on.

[0374] In each of the circuits PV1 to PV4, the gate of the transistor M5 receives a low-level potential (V Low3 ) is applied, and the gate-source voltage of transistor M5 becomes VLow3 -V CATH V Low3 -V CATH is smaller than the threshold voltage of the transistor M5, so the transistor M5 is turned off.

[0375] In the circuit PV1, the gate of the transistor M6 is supplied with a high-level potential (V High5 ) is applied, and the potential of the first terminal (node ​​N1) of the transistor M6 is V CATH As a result, the gate-source voltage of transistor M6 becomes V High5 -V CATH V High5 -V CATH is greater than the threshold voltage of the transistor M6, the transistor M6 is turned on. Therefore, the line VR1 and the anode of the light-receiving device PD are electrically connected, and the potential of the anode of the light-receiving device PD becomes V CATH This becomes:

[0376] In each of the circuits PV2 to PV4, the gate of the transistor M7 receives a high-level potential (V High5 ) is applied to the second terminal of the transistor M7 (node ​​N1 of the circuit PV1). CATH Therefore, the gate-source voltage of transistor M7 is V High5 -V CATH As a result, the wiring VR1 of the circuit PV1 and the anode of each of the light receiving devices PD of the circuits PV2 to PV4 are electrically connected, and the potential of the anode of each of the light receiving devices PD of the circuits PV2 to PV4 becomes V CATH This becomes:

[0377] At this time, in each of the circuits PV1 to PV4, the voltage between the anode and cathode of the light receiving device PD is 0V, and therefore, no current flows between the anode and cathode of the light receiving device PD.

[0378] Regarding the switching operation of the transistor M3 in each of the circuits PV1 to PV4, an example of operation from time T22 to time T23 in the timing chart of Fig. 12 is taken into consideration. Specifically, in each of the circuits PV1 to PV4, the gate of the transistor M3 is supplied with a high-level potential (V High2 ) is applied to transistor M3, turning it on.

[0379] In the circuits PV1 to PV4, from time T32 to time T33, as described above, V LVSH is applied to the second terminal of the transistor M2, and the potential V DD Here, as in the period from time T31 to time T32, the potential of the first terminal of the transistor M2 is V DD , and the first terminal of the transistor M2 functions as a source. Note that although the transistor M2 may be turned on depending on the gate-source voltage of the transistor M2, it is preferable that the transistor M2 be in an off state between time T32 and time T33. Furthermore, since the transistor M1 is in an off state as in the period from time T31 to time T32, in the circuits PV1 and PV3, no current flows from the wiring VDE to the wiring OL[j] via the transistors M2 and M1, and in the circuits PV2 and PV4, no current flows from the wiring VDE to the wiring OL[j+1] via the transistors M2 and M1.

[0380] [From time T33 to time T34] Between time T33 and time T34, the wiring RS1(i,i+1) is supplied with a low-level potential (V Low1 ) is input, and the low-level potential (V Low2 ) is entered.

[0381] Regarding the switching operation of the transistor M4 in each of the circuits PV1 to PV4, an example of operation from time T23 to time T24 in the timing chart of Fig. 12 is referred to. Specifically, in each of the circuits PV1 to PV4, the gate of the transistor M4 is supplied with a low-level potential (V Low1 ) is applied to transistor M4, turning it off.

[0382] For the switching operation of the transistor M3 in each of the circuits PV1 to PV4, refer to the operation example from time T23 to time T24 in the timing chart of Fig. 12. Specifically, in each of the circuits PV1 to PV4, the gate of the transistor M3 receives a low-level potential (V Low2 ) is applied to the transistor M3, turning it off. This also causes the first terminal (node ​​N2) of the capacitor CV1 to be in a floating state.

[0383] The transistor M6 of the circuit PV1 and the transistor M7 of each of the circuits PV2 to PV4 have been in the on state since before time T33.

[0384] When light is irradiated onto the light-receiving device PD of each of circuits PV1 to PV4, a current flows from the cathode to the anode of the light-receiving device PD. Furthermore, because transistor M5 of each of circuits PV1 to PV4 is off and transistor M6 of circuit PV1 and transistor M7 of each of circuits PV2 to PV4 are on, a positive charge due to the current flows to node N1 of circuit PV1 and accumulates in the second terminal of capacitor CV1 of circuit PV1 for the duration that transistor M6 and each transistor M7 are on. If transistor M6 and each transistor M7 are turned off at time T34, the potential of the second terminal (node ​​N1) of capacitor CV1 of circuit PV1 continues to increase from time T33 to time T34.

[0385] That is, the imaging data captured by the light receiving devices PD of the circuits PV2 to PV4 is transmitted to the node N1 of the circuit PV1. As a result, the imaging data captured by the light receiving devices PD of the circuits PV1 to PV4 is added together, and the added imaging data is held in the second terminal (node ​​N1) of the capacitor CV1 of the circuit PV1.

[0386] Between time T33 and time T34, the amount of positive charge accumulated in the second terminal (node ​​N1) of the capacitance CV1 of the circuit PV1 is determined depending on the amount of current flowing through each of the light receiving devices PD of the circuits PV1 to PV4, and therefore the amount of change in potential per unit time at the second terminal (node ​​N1) of the capacitance CV1 of the circuit PV1 is determined. In this operation example, as an example, when each of the light receiving devices PD of the circuits PV1 to PV4 receives light, the potential of the node N1 of the circuit PV1 becomes V CATH From V CATH +V PDA It is assumed that the value changes to

[0387] Furthermore, between time T33 and time T34, the first terminal (node ​​N2) of the capacitance CV1 of the circuit PV1 is in a floating state. Therefore, due to the capacitive coupling of the capacitance CV1, the potential of the second terminal (node ​​N1) of the capacitance CV1 rises, and the potential of the first terminal (node ​​N2) of the capacitance CV1 also rises. The amount of change in the potential of the first terminal (node ​​N2) of the capacitance CV1 is calculated by multiplying the amount of change in the potential of the second terminal (node ​​N1) of the capacitance CV1 by a capacitive coupling coefficient determined by the peripheral configuration of the first terminal (node ​​N2) of the capacitance CV1. The capacitive coupling coefficient is calculated, for example, from the capacitance value of the capacitance CV1, the gate capacitance of the transistor M2, and the parasitic capacitance. Here, assuming that the capacitive coupling coefficient of the capacitance CV1 of the circuit PV1 is p, when each of the light-receiving devices PD of the circuit PV1 receives light, the potential of the first terminal (node ​​N2) of the capacitance CV1 of the circuit PV1 becomes V LVSH From V LVSH +pV PDA It is assumed that the value changes to

[0388] [From time T34 to time T35] At time T34, the wiring TX2(i, i+1) is supplied with a low-level potential (V Low5 ) is entered.

[0389] At this time, the gates of the transistors M6 in the circuit PV1 and M7 in the circuits PV2 to PV4 receive a low-level potential (V Low5 ) is applied. At this time, the gate-source voltage of transistor M6 in circuit PV1 becomes equal to or lower than the threshold voltage of transistor M6, turning transistor M6 off. Also, the gate-source voltage of transistor M7 in each of circuits PV2 to PV4 becomes equal to or lower than the threshold voltage of transistor M7, turning transistor M7 off.

[0390] This completes the accumulation of positive charge (potential increase) at the first terminal (node ​​N2) of capacitance CV1 of circuit PV1 due to the current flowing between the anode and cathode of each light receiving device PD of circuits PV1 to PV4 during the operation from time T33 to time T34.

[0391] [From time T35 to time T36] Between time T35 and time T36, similarly to the period between time T25 and time T26 in the timing chart of FIG. 12, the wiring SE[i] is supplied with a high-level potential (V High6 ) is entered.

[0392] The switching operation of the transistor M1 in each of the circuits PV1 and PV2 will be described with reference to the example of operation from time T25 to time T26 in the timing chart of Fig. 12. Specifically, from time T35 to time T36, the transistor M1 in each of the circuits PV1 and PV2 is in the ON state.

[0393] In the circuit PV1, between time T35 and time T36, V LVSH +pV PDAis applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the line OL[j]. PRE is applied.

[0394] At this time, the gate-source voltage of transistor M2 in circuit PV1 is V LVSH +pV PDA -V PRE The gate-source voltage V LVSH +pV PDA -V PRE A current corresponding to the voltage flows. At this time, since the wiring OL[j] is in a floating state, the potential of the wiring OL[j] rises over time. Therefore, as a current flows between the source and drain of the transistor M2, the gate-source voltage of the transistor M2 decreases, and ideally, when the gate-source voltage of the transistor M2 becomes equal to the threshold voltage of the transistor M2, the transistor M2 turns off. Also, the potential of the wiring OL[j] at this time is V OUTA Let's say.

[0395] In the circuit PV2, between time T35 and time T36, V LVSH is applied to the second terminal of the transistor M2, and the potential V DD Also, since the transistor M1 is in the on state, the first terminal of the transistor M2 is supplied with V, which is precharged to the wiring OL[j+1]. PRE is applied.

[0396] At this time, the gate-source voltage of transistor M2 in circuit PV2 is V LVSH -V PRE At this time, V LVSH -V PREWhen the voltage V t of the transistor M2 is lower than or equal to the threshold voltage of the transistor M2, the transistor M2 is turned off, and no current flows between the source and drain of the transistor M2. PRE Does not change from V LVSH -V PRE is greater than the threshold voltage of transistor M2, the gate-source voltage V LVSH -V PRE At this time, since the wiring OL[j+1] is in a floating state, the potential of the wiring OL[j+1] increases over time. In FIG. 13, the transistor M2 is turned off (the potential of the wiring OL[j+1] is V PRE This figure shows the case where the value of the

[0397] [After time T36] After time T36, the wiring SE[i] is supplied with a low-level potential (V Low6 ) is entered.

[0398] The switching operation of the transistor M1 in each of the circuits PV1 and PV2 will be described with reference to the example of operation from time T26 to time T27 in the timing chart of Fig. 12. Specifically, from time T26 to time T27, the transistor M1 in each of the circuits PV1 and PV2 is in the off state.

[0399] At this time, by reading out the potential of the wiring OL[j], it is possible to obtain image data captured by the light receiving devices PD of the circuits PV1 and PV2 between time T33 and time T34. Note that in this operation example, it is not necessary to read out the potential of the wiring OL[j+1], so the potential of the wiring OL[j+1] is V PRE It may vary from

[0400] 9 to a display portion included in a display device, the display device can perform a second operation suitable for high-speed imaging or imaging in a dark place in addition to a first operation.

[0401] Note that the operation of the semiconductor device of one embodiment of the present invention is not limited to the operation example of the timing chart in FIG. 13 and may be modified as appropriate within the scope of solving the problem.

[0402] 13, high-level potentials are simultaneously input to the wirings RS1(i,i+1), RS2(i,i+1), and TX2(i,i+1). However, the operation of the semiconductor device of one embodiment of the present invention may be such that high-level potentials are input to the wirings RS1(i,i+1), RS2(i,i+1), and TX2(i,i+1) in any order from time T32 to time T33. Specifically, for example, after inputting a high-level potential to the wiring RS1(i,i+1), a high-level potential may be input to the wiring RS2(i,i+1), and then a high-level potential may be input to the wiring TX2(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring RS1(i,i+1) after inputting a high-level potential to the wiring TX2(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring TX2(i,i+1), and then a high-level potential may be input to the wiring RS1(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1). Alternatively, for example, a high-level potential may be input to the wiring TX2(i,i+1), and then a high-level potential may be input to the wiring RS2(i,i+1), and then a high-level potential may be input to the wiring RS1(i,i+1).

[0403] <Example 2> The semiconductor device of one embodiment of the present invention is not limited to the circuit configurations illustrated in Figures 9 and 11. The configuration of the semiconductor device of one embodiment of the present invention may be changed as appropriate within the scope of solving the problems.

[0404] The region DM_V shown in FIG. 14 is a modification of the region DM_V in FIG. 9, and differs from the region DM_V in FIG. 9 in that the circuit PV1 includes a transistor M8.

[0405] The transistor M8 can be, for example, a transistor that can be used as the transistors M1 to M5.

[0406] 14, the circuit PV1 includes a transistor M8. Specifically, the transistor M8 is located between the electrical connection between the second terminal of the capacitor CV1 and the second terminal of each of the transistors M7 in the circuits PV2 to PV4. That is, the transistor M8 has the function of switching between a conductive state and a non-conductive state between the second terminal of the capacitor CV1 and the second terminal of each of the transistors M7 in the circuits PV2 to PV4.

[0407] A first terminal of the transistor M8 is electrically connected to a second terminal of the capacitor CV1, a first terminal of the transistor M4, a first terminal of the transistor M5, and a first terminal of the transistor M6. A second terminal of the transistor M8 is electrically connected to a second terminal of the transistor M7 in each of the circuits PV2 to PV4. A gate of the transistor M8 is electrically connected to a gate of the transistor M6 and a wiring TX2[i].

[0408] As shown in Figure 14, by providing transistor M8 in circuit PV1, the influence of parasitic capacitance associated with the wiring electrically connecting the second terminal of capacitance CV1 of circuit PV1 and the second terminal of each of transistors M7 of circuits PV2 to PV4 can be reduced.

[0409] 9, the second terminal of the capacitance CV1 of the circuit PV1 is directly and electrically connected to the second terminal of each of the transistors M7 of the circuits PV2 to PV4, and therefore the parasitic capacitance of the wiring electrically connecting the second terminal of the capacitance CV1 of the circuit PV1 to the second terminal of each of the transistors M7 of the circuits PV2 to PV4 may become large. Therefore, if the parasitic capacitance of the wiring at the second terminal (node ​​N1) of the capacitance CV1 of the circuit PV1 is large, the time required to acquire imaging data in the imaging operation of the circuit PV1 may become long.

[0410] 14, applying a low-level potential to the wiring TX2[i] can turn off the transistor M6 in the circuit PV1 and the transistor M7 in the circuit PV2, as well as the transistor M8. At this time, a low-level potential may also be applied to the wiring TX2[i+1] at approximately the same time to turn off the transistor M7 in the circuits PV3 and PV4. At this time, a high-level potential is applied to the wiring TX1[i] and the wiring TX1[i+1], and the transistor M5 in each of the circuits PV1 to PV4 is turned on.

[0411] This allows the region DM_V to perform imaging by the first operation described in Operation Example 1. At this time, the transistor M8 is in the off state, so that it is possible to prevent the influence of the parasitic capacitance associated with the wiring electrically connected to the second terminal of each of the transistors M7 in the circuits PV2 to PV4 on the second terminal (node ​​N1) of the capacitor CV1.

[0412] 14, applying a high-level potential to the wiring TX2[i] can turn on the transistor M6 in the circuit PV1 and the transistor M7 in the circuit PV2, as well as the transistor M8. At this time, a high-level potential may also be applied to the wiring TX2[i+1] at approximately the same time to turn on the transistor M7 in the circuits PV3 and PV4. At this time, applying a low-level potential to the wiring TX1[i] and the wiring TX1[i+1] turns off the transistor M5 in each of the circuits PV1 to PV4, allowing the region DM_V to perform imaging using the second operation described in Operation Example 2. Thus, even when the region DM_V has a circuit PV1 provided with the transistor M8, the second operation can be performed in the same way as the region DM_V in FIG. 9.

[0413] <Example 3> The region DM_V shown in Fig. 15 is a circuit diagram showing a modified example of the region DM_V of Fig. 9. The circuits PV1 and PV2 of the region DM_V of Fig. 15 each have the same configuration as the circuit PV1 in the region DM_V of Fig. 9, and the circuits PV3 and PV4 of the region DM_V of Fig. 15 each have the same configuration as the circuit PV2, circuit PV3, or circuit PV4 in the region DM_V of Fig. 9.

[0414] The second terminal of the capacitor CV1 of the circuit PV1 and the first terminals of the transistors M4 to M6 of the circuit PV1 are electrically connected to the second terminal of the transistor M7 of the circuit PV3, and the second terminal of the capacitor CV1 of the circuit PV2 and the first terminals of the transistors M4 to M6 of the circuit PV2 are electrically connected to the second terminal of the transistor M7 of the circuit PV4.

[0415] That is, the area DM_V in FIG. 15 has a circuit configuration in which, when the second operation is performed, the circuits PV1 and PV3 add up the imaging data, and the circuits PV2 and PV4 add up the imaging data.

[0416] 15 , when the circuits PV1 and PV3 add up imaging data and the circuits PV2 and PV4 add up imaging data, the pair of circuits PV1 and PV3 and the pair of circuits PV2 and PV4 may each be a pair of circuits that receive light of different colors. For example, the pair of circuits PV1 and PV3 may be a pair of imaging pixel circuits that receive light of one selected from the three colors red (R), green (G), and blue (B), and the pair of circuits PV2 and PV4 may be a pair of imaging pixel circuits that receive light of one selected from the remaining two colors. Furthermore, the three colors are not limited to red (R), green (G), and blue (B) and may be three colors selected from cyan, magenta, yellow, and white in addition to red (R), green (G), and blue (B).

[0417] Here, we will explain the arrangement of colors of light received by the imaging pixel circuits in the display area when the pair of circuits PV1 and PV3, and the pair of circuits PV2 and PV4 in the area DM_V of Figure 15 are each pairs of imaging pixel circuits that receive light of different colors.

[0418] FIG. 16 is a block diagram showing a portion of a display area of ​​a display device to which the region DM_V of FIG. 15 is applied. The display area of ​​FIG. 16 includes, as an example, a region DM_V having two circuits PV_R and two circuits PV_G, a region DM_V having two circuits PV_G and two circuits PV_B, and a region DM_V having two circuits PV_B and two circuits PV_R. Note that the circuits PV_R, PV_G, and PV_B each have a light-receiving device that receives light of a different color. For example, the circuit PV_R may be an imaging pixel circuit that receives red light, the circuit PV_G may be an imaging pixel circuit that receives green light, and the circuit PV_B may be an imaging pixel circuit that receives blue light.

[0419] Furthermore, the four imaging pixel circuits included in the region DM_V shown in Fig. 16 correspond to the four circuits PV1 to PV4 included in the region DM_V in Fig. 15. Specifically, for example, in the display region of Fig. 16, one two imaging pixel circuits that receive light of the same color in the region DM_V correspond to the circuits PV1 and PV2 included in the region DM_V in Fig. 15, and the other two imaging pixel circuits that receive light of the same color in the region DM_V correspond to the circuits PV3 and PV4 included in the region DM_V in Fig. 15.

[0420] Focusing on the multiple regions DM_V located in the kth row (where k is an integer greater than or equal to 1) and the k+1th row, the circuits PV_R, PV_G, PV_B, and PV_R are arranged in this order from left to right. Focusing on the multiple regions DM_V located in the k+2th and k+3th rows, the circuits PV_G, PV_B, PV_R, and PV_G are arranged in this order from left to right. Focusing on the circuits included in the region DM_V located in the hth column (where h is an integer greater than or equal to 1), the two circuits PV_R and the two circuits PV_G are arranged in this order from the top. Focusing on the circuits included in the region DM_V located in the h+1th column, the two circuits PV_G and the two circuits PV_B are arranged in this order from the top. Focusing on the circuits included in the region DM_V located in the h+2th column, the two circuits PV_B and the two circuits PV_R are arranged in this order from the top. Furthermore, when attention is paid to the circuits included in the region DM_V located in the (h+3)th column, two circuits PV_R and two circuits PV_G are arranged in this order from the top.

[0421] That is, in the display area shown in FIG. 16, the imaging pixel circuits are repeatedly arranged in the row direction in a sequence of circuit PV_R, circuit PV_G, and circuit PV_B, and in the column direction in a sequence of two circuits PV_R, two circuits PV_G, and two circuits PV_B.

[0422] Note that the arrangement of the colors of light received by the imaging pixel circuits in the semiconductor device of one embodiment of the present invention is not limited to the arrangement shown in Fig. 16. For example, the arrangement of the colors of light received by the imaging pixel circuits in the semiconductor device of one embodiment of the present invention may be such that the circuits PV_R, PV_G, and PV_B are repeatedly arranged in the row direction, and imaging pixel circuits that receive light of the same color are arranged in each column, as shown in Fig. 17.

[0423] 16 and 17 are configured to receive three colors of light, but may be configured to receive two, four, or more colors of light. In this case, the colors of light received may be two, four, or more colors selected from red (R), green (G), blue (B), cyan, magenta, yellow, and white.

[0424] Although the semiconductor device described in this embodiment has a configuration in which four imaging pixel circuits are provided in the region DM_V as shown in FIGS. 7, 16, and 17, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the four imaging pixel circuits may be configured to be separated from each other by, for example, extending wirings electrically connecting the four imaging pixel circuits. Therefore, the photodetector PD included in each of the circuits PV1 to PV4 shown in FIGS. 9, 11, 14, and 15 may be applied to the photodetector 160 in each of FIGS. 33A and 33B, which will be described later. Furthermore, the circuits PV1 to PV4 shown in FIGS. 9, 11, 14, and 15 may be applied to the subpixels PS in each of FIGS. 39A to 39D.

[0425] Note that the circuit configurations described in this embodiment mode can be combined with each other as appropriate.

[0426] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0427] (Embodiment 3) In this embodiment, a structural example of a display device in which a semiconductor device of one embodiment of the present invention and a display portion are combined will be described.

[0428] 18 is a cross-sectional view of a display device according to one embodiment of the present invention. The display device 10 includes a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0429] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL.

[0430] The circuit layer SICL has a substrate BS, a drive circuit region DRV, and a functional circuit region MFNC.

[0431] The substrate BS can be, for example, a single-crystal substrate (e.g., a semiconductor substrate made of silicon or germanium). In addition to single-crystal substrates, the substrate BS can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, or base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are examples. Another example is a synthetic resin such as acrylic resin. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 10 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate BS.

[0432] For example, when the substrate BS is a semiconductor substrate made of silicon, the transistors included in the drive circuit region DRV and the functional circuit region MFNC can be Si transistors.

[0433] Furthermore, for example, when the substrate BS is a glass substrate, the transistors included in the driver circuit region DRV and the functional circuit region MFNC can be OS transistors.

[0434] The drive circuit region DRV and the functional circuit region MFNC are provided on a substrate BS.

[0435] The drive circuit region DRV has, as an example, a drive circuit for driving a display pixel circuit included in a pixel layer PXAL, which will be described later. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0436] The functional circuit region MFNC may include, for example, a GPU (Graphics Processing Unit). Furthermore, if the display device 10 includes a touch panel, the functional circuit region MFNC may include a sensor controller that controls a touch sensor included in the touch panel. Furthermore, if a light-emitting device using an EL material is used as the display element of the display device 10, the functional circuit region MFNC may include an EL correction circuit. Furthermore, if a liquid crystal element is used as the display element of the display device 10, the functional circuit region MFNC may include a gamma correction circuit.

[0437] The wiring layer LINL is provided with wiring, for example, and the wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in the drive circuit region DRV provided below and a circuit included in the pixel layer PXAL provided above.

[0438] The pixel layer PXAL has, for example, a plurality of display pixel circuits, which may be arranged in a matrix in the pixel layer PXAL.

[0439] Each of the plurality of display pixel circuits can express one or more colors. In particular, the plurality of colors can be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the plurality of display pixel circuits can express four or more colors by adding one or more colors selected from cyan, magenta, yellow, and white to the three colors of red (R), green (G), and blue (B). Each of the display pixel circuits expressing different colors is referred to as a subpixel, and when white is expressed by multiple subpixels of different colors, the multiple subpixels may be collectively referred to as a pixel. For convenience, in this specification and other descriptions, a subpixel will be referred to as a pixel.

[0440] FIG. 19 is a block diagram showing an example of the configuration of the display device 10 shown in FIG. 18. The display device 10 shown in FIG. 19 has, as an example, a display unit DIS and a circuit unit SIC. Although FIG. 19 also shows a sensor PDA, the sensor PDA may be disposed inside or outside the display device 10. If the sensor PDA is disposed inside the display device 10, the sensor PDA may be disposed inside or outside the display area. Note that the outside of the display area includes, for example, the frame area (the area where the drive circuits for the pixel circuits of the display area are disposed and the area nearby).

[0441] In addition, the wirings indicated by thick solid lines in FIG. 19 are depicted as multiple wirings or bus wirings.

[0442] The display unit DIS shown in FIG. 19 is included in, for example, the pixel layer PXAL in FIG. 18. In FIG. 19, the display unit DIS has a plurality of circuits PX arranged in a matrix, each functioning as a display pixel circuit. The circuit PX can be a pixel to which one or more selected from, for example, a liquid crystal display device, a light-emitting device containing an organic EL material, or a light-emitting device containing a light-emitting diode such as a micro LED is applied. Note that in this embodiment, a light-emitting device containing an organic EL material is applied to the circuit PX of the display unit DIS. Also, the circuit PX can be a circuit PX included in the circuit AP described in the above embodiment. Also, circuits that can be applied to the display unit DIS, the circuit PX, etc. will be described in detail in embodiment 4.

[0443] The pixel density (also referred to as "resolution") of the display unit DIS is preferably 100 ppi or more and 10,000 ppi or less, and more preferably 1,000 ppi or more and 10,000 ppi or less. For example, it may be 2,000 ppi or more and 6,000 ppi or less, or 3,000 ppi or more and 5,000 ppi or less.

[0444] The aspect ratio of the display unit DIS is not particularly limited, and the display unit DIS can accommodate various aspect ratios, such as 1:1 (square), 4:3, 16:9, or 16:10.

[0445] The diagonal size of the display unit DIS may be 0.1 inches or more and 100 inches or less, and may be 100 inches or more.

[0446] The configuration of the transistors included in the display unit DIS may be appropriately selected depending on the diagonal size of the display unit DIS. For example, when single-crystal silicon transistors are used as the transistors in the display unit DIS, the display unit DIS can be applied to a screen size with a diagonal size of 0.1 to 3 inches. When LTPS transistors are used as the transistors in the display unit DIS, the display unit DIS can be applied to a screen size with a diagonal size of 0.1 to 30 inches, preferably 1 to 30 inches. When LTPO transistors (combining LTPS transistors and OS transistors) are used in the display unit DIS, the display unit DIS can be applied to a screen size with a diagonal size of 0.1 to 50 inches, preferably 1 to 50 inches. When OS transistors are used as the transistors in the display panel, the display unit DIS can be applied to a screen size with a diagonal size of 0.1 to 200 inches, preferably 50 to 100 inches.

[0447] It is extremely difficult to increase the screen size of a display unit (DIS) using single-crystal Si transistors beyond the size of a single-crystal Si substrate. Furthermore, because LTPS transistors require a laser crystallization device in the manufacturing process, it is difficult to accommodate larger screen sizes (typically, screen sizes exceeding 30 inches in diagonal size). On the other hand, OS transistors are not restricted by the need for a laser crystallization device in the manufacturing process, and can be manufactured at relatively low process temperatures (typically 450°C or lower), making them suitable for display panels with relatively large areas (typically, diagonal sizes of 50 to 100 inches). Furthermore, LTPO can be applied to display panel sizes between those using LTPS transistors and those using OS transistors (typically, diagonal sizes of 1 to 50 inches).

[0448] Moreover, the circuit unit SIC shown in Fig. 19 is included in, for example, the circuit layer SICL in Fig. 18. Furthermore, in Fig. 19, the circuit unit SIC has a drive circuit area DRV and a functional circuit area MFNC.

[0449] The drive circuit region DRV functions as, for example, a peripheral circuit for driving the display unit DIS. Specifically, the drive circuit region DRV includes, for example, a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14.

[0450] 19, the functional circuit area MFNC may include, for example, a storage device in which image data to be displayed on the display unit DIS is stored, a decoder for restoring encoded image data, a GPU for processing image data, a power supply circuit, a correction circuit, a CPU, etc. In FIG.

[0451] Furthermore, the display device 10 in FIG. 19 is configured such that, as an example, bus wiring BSL is electrically connected to each of the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC.

[0452] The source driver circuit 11 has a function of transmitting image data to, for example, a circuit PX included in the display unit DIS, and therefore, the source driver circuit 11 is electrically connected to the circuit PX via wiring SL.

[0453] The digital-analog conversion circuit 12 has a function of converting image data that has been digitally processed by, for example, a GPU or a correction circuit (to be described later) into analog data. The image data converted into analog data is transmitted to the display unit DIS via the source driver circuit 11. Note that the digital-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the following order: source driver circuit 11, digital-analog conversion circuit 12, and display unit DIS.

[0454] The gate driver circuit 13 has a function of selecting a circuit PX to which image data is to be sent in the display unit DIS, for example, and is therefore electrically connected to the circuit PX via a wiring GL.

[0455] The level shifter 14 has a function of converting signals input to, for example, the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, and the like, to appropriate levels.

[0456] The storage device 21 has a function of storing, for example, image data to be displayed on the display unit DIS. The storage device 21 can be configured to store image data as digital data or analog data.

[0457] Furthermore, when image data is stored in the storage device 21, it is preferable that the storage device 21 is a nonvolatile memory. In this case, for example, a NAND type memory or the like can be used as the nonvolatile memory.

[0458] Furthermore, when temporary data generated by the GPU 22, the EL correction circuit 23, the CPU 25, etc. is stored in the storage device 21, it is preferable that the storage device 21 be a volatile memory. In this case, for example, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) can be used as the volatile memory.

[0459] The GPU 22 has a function of performing processing for drawing image data read from the storage device 21 on the display unit DIS, for example. In particular, the GPU 22 is configured to perform pipeline processing in parallel, so that it can process image data to be displayed on the display unit DIS at high speed. The GPU 22 can also function as a decoder for restoring encoded images.

[0460] The functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display unit DIS. For example, the circuits may be correction circuits (circuits for adjusting color or brightness) that detect color unevenness in an image displayed on the display unit DIS and correct the color unevenness to create an optimal image. Furthermore, when light-emitting devices using organic EL materials are used in the pixels of the display unit DIS, the functional circuit region MFNC may also include an EL correction circuit. The EL correction circuit has the function of, for example, appropriately adjusting the amount of current input to a light-emitting device containing an EL material. Because the luminance of a light-emitting device containing an EL material is proportional to the current, poor performance of a driving transistor electrically connected to the light-emitting device may result in the luminance of light emitted by the light-emitting device being lower than desired. The EL correction circuit, for example, monitors the amount of current flowing through the light-emitting device. When the amount of current is smaller than desired, it increases the amount of current flowing through the light-emitting device, thereby increasing the luminance of light emitted by the light-emitting device. Conversely, when the amount of current is larger than the desired amount of current, the amount of current flowing through the light-emitting device may be adjusted to be smaller. Note that, in the present embodiment, the circuit PX of the display unit DIS is described as being applied with a light-emitting device containing an organic EL material, and therefore the functional circuit region MFNC includes, as an example, an EL correction circuit 23.

[0461] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through (or the voltage applied to) the display device provided in the display pixel circuit may be monitored and acquired, and the image displayed on the display unit DIS may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0462] Furthermore, AI calculations can be applied not only to image correction but also to upconversion (downconversion) of image data. This allows high-quality images to be displayed on the display unit DIS by upconverting (downconverting) low-resolution image data to match the resolution of the display unit DIS.

[0463] The above-mentioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC. That is, the GPU 22 can be used to perform various correction calculations (color unevenness correction, up-conversion (down-conversion), etc.).

[0464] The GPU 22 may also include a correction circuit 22a for correcting images and a converter 22b for performing up-conversion (down-conversion).

[0465] In this specification, a GPU that performs artificial intelligence calculations is referred to as an AI accelerator. That is, in this specification, a GPU provided in the functional circuit area MFNC may be described as an AI accelerator.

[0466] The timing controller 24 has a function of varying the frame rate at which an image is displayed on the display unit DIS, for example. For example, when a still image is displayed on the display unit DIS, the display device 10 can be driven by the timing controller 24 at a lower frame rate. Also, for example, when a moving image is displayed on the display unit DIS, the display device 10 can be driven by the timing controller 24 at an increased frame rate. In other words, by providing the timing controller 24 in the display device 10, the frame rate can be changed depending on whether the image is a still image or a moving image. In particular, when a still image is displayed on the display unit DIS, the display device 10 can be operated at a lower frame rate, thereby reducing the power consumption of the display device 10.

[0467] The CPU 25 has the function of performing general-purpose processing such as, for example, running an operating system, controlling data, performing various calculations, or running programs. In the display device 10, the CPU 25 has the role of issuing commands such as writing or reading image data to or from the storage device 21, correcting image data, or issuing commands to a sensor (described later). Furthermore, the CPU 25 may have the function of transmitting control signals to at least one of the circuits included in the functional circuit area MFNC, such as the storage device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0468] The CPU 25 may also have a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed on the display unit DIS, the CPU 25 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 25 to the backup circuit and then stopping the supply of power supply voltage to the CPU 25, the dynamic power consumption of the CPU 25 can be reduced. In this specification, a CPU having a backup circuit is referred to as a NoffCPU (registered trademark).

[0469] The sensor controller 26 has a function of controlling, for example, the sensor PDA. Also, in Fig. 19, a line SNCL is illustrated as a line for electrically connecting to the sensor PDA.

[0470] The sensor PDA may be, for example, a touch sensor that can be provided above, below, or inside the display unit DIS.

[0471] Alternatively, the sensor PDA may be, for example, an illuminance sensor. In particular, by obtaining the intensity of external light illuminating the display unit DIS using the illuminance sensor, it is possible to change the brightness (luminance) of the image displayed on the display unit DIS in accordance with the external light. For example, when the external light is bright, the luminance of the image displayed on the display unit DIS can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed on the display unit DIS can be decreased to reduce power consumption.

[0472] Alternatively, the sensor PDA may be, for example, an image sensor, which may acquire an image or the like and display the image on the display unit DIS.

[0473] For example, the power supply circuit 27 has a function of generating voltages to be supplied to circuits included in the drive circuit area DRV, circuits included in the functional circuit area MFNC, display pixel circuits included in the display unit DIS, etc. The power supply circuit 27 may also have a function of selecting the circuits to which the voltage is supplied. For example, while a still image is being displayed on the display unit DIS, the power supply circuit 27 can reduce the power consumption of the entire display device 10 by stopping the supply of voltage to one or both of the CPU 25 and the GPU 22.

[0474] <Configuration example of imaging pixel circuit> Next, an image sensor that can be used in the sensor PDA of the display device 10 will be described.

[0475] As an image sensor that can be applied to the sensor PDA, for example, an imaging device IM shown in FIG. 20 can be applied.

[0476] 20 is a block diagram showing an example of the circuit configuration of the imaging device IM. The imaging device IM includes an imaging section 31, a first driving circuit section 33, a second driving circuit section 34, a readout circuit section 35, and a control circuit section 36. The first driving circuit section 33, the second driving circuit section 34, the readout circuit section 35, and the control circuit section 36 may be collectively referred to as a "functional circuit." The functional circuit may be a variety of circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit.

[0477] The transistors used in the imaging unit 31 and functional circuits of the imaging device IM may be n-channel transistors or p-channel transistors. Both n-channel transistors and p-channel transistors may be used. The imaging unit 31 and functional circuits may have a CMOS structure that combines n-channel transistors and p-channel transistors.

[0478] The imaging section 31 includes imaging pixel circuits 32 arranged in a matrix of m rows and n columns (m and n are each an integer of 1 or greater). The imaging section 31 is electrically connected to the first drive circuit section 33 via a plurality of wirings 41. The imaging section 31 is also electrically connected to the readout circuit section 35 via a plurality of wirings 42. The readout circuit section 35 is electrically connected to the second drive circuit section 34 via a plurality of wirings 43. For example, the imaging pixel circuit 32 arranged in the i-th row (where i is an integer of 1 to m) is electrically connected to the first drive circuit section 33 via the i-th wiring 41. The imaging pixel circuit 32 arranged in the j-th column (where j is an integer of 1 to n) is electrically connected to the readout circuit section 35 via the j-th wiring 42.

[0479] As the imaging pixel circuit 32, for example, the circuit PV described in the above embodiment can be used.

[0480] 20, the imaging pixel circuit 32 arranged in the first row and first column is indicated as imaging pixel circuit 32[1,1], the imaging pixel circuit 32 arranged in the mth row and nth column is indicated as imaging pixel circuit 32[m,n], and the imaging pixel circuit 32 arranged in the ith row and jth column is indicated as imaging pixel circuit 32[i,j].

[0481] The wiring 41 may be, for example, the wiring SE described in the above embodiment, and the wiring 42 may be, for example, the wiring OL described in the above embodiment.

[0482] Note that the wirings connected to one imaging pixel circuit 32 are not limited to the wiring 41 and the wiring 42. Wirings other than the wiring 41 and the wiring 42 may be connected to the imaging pixel circuit 32. For example, the wirings other than the wiring 41 and the wiring 42 that are electrically connected to the imaging pixel circuit 32 may be the wiring TX, the wiring RS1, or the wiring RS2 described in the above embodiment.

[0483] Furthermore, for the pixel density, aspect ratio, and diagonal size of the imaging unit 31, the above-mentioned description of the pixel density, aspect ratio, and diagonal size of the display unit DIS should be taken into consideration.

[0484] The control circuit unit 36 ​​has a function of controlling the operation of the circuits included in the imaging device IM. The first drive circuit unit 33 has a function of selecting the imaging pixel circuits 32 for each row. The imaging pixel circuits 32 of the row selected by the first drive circuit unit 33 output imaging data to the readout circuit unit 35 via wiring 42.

[0485] The readout circuit unit 35 holds the imaging data supplied from the imaging pixel circuits 32 for each column and performs noise removal processing, etc. As the noise removal processing, for example, CDS (Correlated Double Sampling) processing, etc. The readout circuit unit 35 may also have, for example, one or both of an amplification function and an AD conversion function for the imaging data.

[0486] The second drive circuit section 34 has a function of sequentially selecting the imaging data held in the readout circuit section 35 and outputting the imaging data from the output terminal OUT to the outside.

[0487] <Configuration example of integrated display device and imaging device> Next, the configuration of the display device 10 in which the above-mentioned display unit DIS and imaging device IM are integrated will be described.

[0488] FIG. 21 shows the configuration of a display device 10 in which a display device including the display unit DIS, source driver circuit 11, and gate driver circuit 13 shown in FIG. 19 is combined with the imaging device IM shown in FIG.

[0489] The display device 10 shown in Fig. 21 has a configuration in which circuits AP[1,1] to AP[m,n] are arranged in a matrix of m rows and n columns in the display unit DIS. When i is an integer between 1 and m, and j is an integer between 1 and n, the circuit AP[i,j] includes, for example, a circuit PX[i,j] and an imaging pixel circuit 32[i,j]. Note that Fig. 21 only illustrates the circuits AP[1,1] and AP[m,n] in the display unit DIS with reference symbols.

[0490] As the circuit AP[1,1], the circuit AP[m,n], etc., for example, the circuit AP shown in FIG. 1A, etc., described in the above embodiment, can be applied.

[0491] In FIG. 21, the multiple wirings 41 are described as wirings 41[1] to 41[m], the multiple wirings 42 are described as wirings 42[1] to 42[n], and the multiple wirings 43 are described as wirings 43[1] to 43[n].

[0492] In FIG. 21, as an example, the second drive circuit section 34 and the source driver circuit 11 are electrically connected by wirings 44[1] to 44[n].

[0493] As an example, the imaging data read out by the readout circuit unit 35 is transmitted to the source driver circuit 11 via wiring 43[1] to wiring 43[n], the second drive circuit unit 34, and wiring 44[1] to wiring 44[n].

[0494] For this reason, the source driver circuit 11 may have the functions of adjusting the voltage, converting the polarity, and amplifying the power of the imaging data supplied from the imaging device IM. In other words, the source driver circuit 11 may have the function of converting the imaging data into a video signal. This allows the source driver circuit 11 to output the video signal converted from the imaging data to the circuit PX of the display unit DIS.

[0495] With this configuration, the imaging data acquired by the imaging unit 31 can be converted into a video signal more suitable for display on the display unit DIS by the source driver circuit 11. For example, a display device that is less susceptible to the effects of noise and has good display quality can be realized.

[0496] 21 , by configuring the display device 10 so that the circuit PX and the imaging pixel circuits 32 are arranged in the same display unit DIS, the entire display unit can be used as a sensor area. For example, the imaging pixel circuits 32[1,1] to 32[m,n] capture images of a user's finger, thereby providing the display device 10 with a function for performing fingerprint authentication. Furthermore, the display device 10 may also have a function for operating the display device 10 or an electronic device including the display device 10 by continuously capturing images of a user's finger using the imaging pixel circuits 32[1,1] to 32[m,n].

[0497] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0498] (Fourth embodiment) In this embodiment, a display device that can be included in an electronic device of one embodiment of the present invention will be described. Note that the display device described in this embodiment can be applied to the display unit DIS described in the above embodiment.

[0499] <Example of display device configuration> 22 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. For example, a display device 1000 illustrated in FIG. 22 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310. The structure of the display device 10 or the like according to the above-described embodiments can be the structure of the display device 1000 illustrated in FIG. 22. The pixel circuit described in this embodiment can be the display pixel circuit described in the above-described embodiments.

[0500] Specifically, for example, the circuit layer SICL, wiring layer LINL, and pixel layer PXAL shown in the display device 10 can be configured as in the display device 1000 of Fig. 22. The circuit layer SICL has, as an example, a substrate 310, on which a transistor 300 is formed. In addition, a wiring layer LINL is provided above the transistor 300, and the wiring layer LINL is provided with wiring that electrically connects the transistor 300, a transistor 200 described later, a light-emitting device 150a, a light-emitting device 150b described later, and the like. In addition, a pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL has, as an example, the transistor 200, a light-emitting device 150 (the light-emitting device 150a and the light-emitting device 150b in Fig. 22), and the like.

[0501] The substrate 310 can be, for example, a single crystal substrate (e.g., a semiconductor substrate made of silicon or germanium). In addition to a semiconductor substrate, the substrate 310 can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, or base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are examples. Another example is a synthetic resin such as acrylic resin. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 1000 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0502] In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0503] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a Si transistor. Note that although FIG. 22 illustrates a structure in which one of the source and drain of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366, which will be described later, through the conductor 328, the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention may have a structure in which the gate of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 through the conductor 328.

[0504] The transistor 300 can be made into a fin type by, for example, configuring the top surface and the side surfaces in the channel width direction of the semiconductor region 313 to be covered with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0505] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0506] The region in the semiconductor region 313 where the channel is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that will become the source or drain region preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed of a material containing, for example, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs, or gallium nitride (GaN)). A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0507] The conductor 316, which functions as the gate electrode, can be a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum, or can be a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0508] Note that the work function is determined by the material of the conductor, and therefore, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as a stacked layer for the conductor. In particular, tungsten is preferable in terms of heat resistance.

[0509] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0510] 22 is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0511] In the transistor 300 shown in FIG. 22, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0512] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0513] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve flatness.

[0514] The insulator 324 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to regions above the insulator 324 (e.g., regions where the transistor 200, the light-emitting device 150a, the light-emitting device 150b, etc. are provided). Therefore, the insulator 324 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., through which the impurities are less likely to permeate). Depending on the situation, the insulator 324 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), copper atoms, etc. (i.e., through which the impurities are less likely to permeate). Alternatively, the insulator 324 preferably has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0515] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method.

[0516] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectrometry (TDS). For example, the amount of desorbed hydrogen from the insulator 324 is calculated by TDS as follows: when the surface temperature of the film is in the range of 50° C. to 500° C., the amount of desorbed hydrogen converted into hydrogen atoms is 10×10 per area of ​​the insulator 324. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0517] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0518] Furthermore, conductors 328 and 330 are embedded in the insulators 320, 322, 324, and 326, respectively, to connect to a light-emitting device or the like disposed above the insulator 326. The conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors functioning as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0519] The materials for each plug and wiring (e.g., conductor 328 and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce the wiring resistance.

[0520] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 22 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0521] Note that, for example, the insulator 350 is preferably an insulator that has barrier properties against hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. The conductor 356 preferably includes a conductor that has barrier properties against hydrogen, oxygen, and water.

[0522] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0523] Furthermore, on the insulator 354 and on the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0524] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0525] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, an insulator having a barrier property against impurities such as water and hydrogen is preferably used, similar to the insulator 324. For this reason, the insulators 362 and 364 can be formed using a material that can be used for the insulator 324.

[0526] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0527] An insulator 370 and an insulator 372 are stacked in this order on the insulator 364 and the conductor 366 .

[0528] The insulator 370 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 370 can be made of, for example, a material that can be used for the insulator 324.

[0529] The insulator 372 functions as an interlayer insulating film and a planarizing film. Similarly to the insulator 324, the insulator 372 is preferably an insulator having a barrier property against impurities such as water and hydrogen. For this reason, the insulator 372 can be made of a material that can be used for the insulator 324.

[0530] Furthermore, openings are formed in the insulators 370 and 372 in regions that overlap with portions of the conductor 366, and the conductor 376 is provided to fill the openings. The conductor 376 is also formed on the insulator 372. Thereafter, the conductor 376 is patterned into a shape such as a wiring, a terminal, or a pad by etching or the like.

[0531] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for the conductor 376. Note that the conductor 376 is preferably made of the same material as the conductor 216 included in the pixel layer PXAL, which will be described later.

[0532] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then planarization is performed using, for example, a chemical mechanical polishing (CMP) method until the conductor 376 is exposed. This allows the conductor 376 to be formed on the substrate 310 as a wiring, terminal, or pad.

[0533] As the insulator 380, it is preferable to use, for example, a film having barrier properties that prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. That is, it is preferable to use, for the insulator 380, a material that can be used for the insulator 324. Alternatively, as the insulator 380, it is possible to use, for example, an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between wirings, similar to the insulator 326. That is, it is possible to use, for the insulator 380, a material that can be used for the insulator 326.

[0534] The pixel layer PXAL is provided with, for example, a substrate 210, a transistor 200, a light-emitting device 150 (light-emitting device 150a and light-emitting device 150b in FIG. 22), and a substrate 102. The pixel layer PXAL is also provided with, for example, an insulator 220, an insulator 222, an insulator 226, an insulator 250, an insulator 111a, an insulator 111b, an insulator 112, an insulator 113, an insulator 162, and a resin layer 163. The pixel layer PXAL is also provided with, for example, a conductor 216, a conductor 228, a conductor 230, a conductor 121 (conductor 121a and conductor 121b in FIG. 22), a conductor 122, and a conductor 123.

[0535] 22, for example, the insulator 202 functions as a bonding layer together with the insulator 380. The insulator 202 is preferably made of the same material as the material used for the insulator 380, for example.

[0536] The substrate 210 is provided above the insulator 202. In other words, the insulator 202 is formed on the lower surface of the substrate 210. As the substrate 210, it is preferable to use, for example, a substrate that can be used as the substrate 310. Note that in the display device 1000 of FIG. 22, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0537] For example, a transistor 200 is formed on the substrate 210. The transistor 200 functions as a Si transistor because it is formed on the substrate 210, which is a semiconductor substrate made of silicon. Note that the description of the transistor 300 is to be referred to for the configuration of the transistor 200.

[0538] An insulator 220 and an insulator 222 are provided above the transistor 200. The insulator 220 functions as an interlayer insulating film and a planarizing film, similar to the insulator 320. The insulator 222 functions as an interlayer insulating film and a planarizing film, similar to the insulator 322.

[0539] A plurality of openings are provided in the insulator 220 and the insulator 222. The plurality of openings are formed in regions overlapping with the source and drain of the transistor 200 and a region overlapping with the conductor 376. Of the plurality of openings, a conductor 228 is formed in the opening formed in the region overlapping with the source and drain of the transistor 200. Of the remaining openings, an insulator 214 is formed on the side surfaces of the opening formed in the region overlapping with the conductor 376, and a conductor 216 is formed in the remaining openings. In particular, the conductor 216 may be called a TSV (Through Silicon Via).

[0540] For one or both of the conductor 216 and the conductor 228, for example, a material applicable to the conductor 328 can be used. In particular, the conductor 216 is preferably formed from the same material as the conductor 376.

[0541] The insulator 214 has a function of insulating the substrate 210 from the conductor 216. Note that the insulator 214 is preferably made of a material that can be used for the insulator 320 or the insulator 324, for example.

[0542] The insulator 380 and the conductor 376 formed on the substrate 310 and the insulator 202 and the conductor 216 formed on the substrate 210 are bonded together by, for example, a bonding process.

[0543] As a pre-process before the bonding process, for example, a planarization process is performed on the substrate 310 side to align the heights of the surfaces of the insulator 380 and the conductor 376. Similarly, a planarization process is performed on the substrate 210 side to align the heights of the insulator 202 and the conductor 216.

[0544] In the bonding process, when bonding insulator 380 and insulator 202, that is, bonding insulating layers together, a hydrophilic bonding method can be used, in which, for example, after polishing to achieve high flatness, surfaces that have been hydrophilically treated with oxygen plasma are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them with heat treatment. Hydrophilic bonding also produces bonds at the atomic level, resulting in mechanically excellent bonds.

[0545] Furthermore, when bonding conductor 376 and conductor 216, that is, bonding conductors together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0546] By carrying out the above-described bonding process, the conductor 376 on the substrate 310 side can be electrically connected to the conductor 216 on the substrate 210 side. Also, a connection with sufficient mechanical strength can be obtained between the insulator 380 on the substrate 310 side and the insulator 202 on the substrate 210 side.

[0547] When bonding substrate 310 and substrate 210, since the bonding surfaces of each substrate contain a mixture of insulating and metal layers, a surface activated bonding method and a hydrophilic bonding method may be combined. For example, a bonding method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment. Alternatively, the surface of the metal layer may be made of a resistant metal (e.g., gold) and then subjected to a hydrophilic treatment.

[0548] Note that bonding methods other than those described above may be used to bond the substrates 310 and 210. For example, flip-chip bonding may be used to bond the substrates 310 and 210. Furthermore, when using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 376 on the substrate 310 side or below the conductor 216 on the substrate 210 side. Examples of flip-chip bonding include a method in which a resin containing anisotropic conductive particles is injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to bond them, and a method in which silver-tin solder is used to bond them. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in addition to the flip-chip bonding method described above, an underfill agent may be injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to reduce physical stress such as impact or thermal stress. Furthermore, for example, the substrate 310 and the substrate 210 may be bonded together using a die bonding film.

[0549] An insulator 224 and an insulator 226 are stacked in this order on the insulator 222, the insulator 214, the conductor 216, and the conductor 228.

[0550] Like the insulator 324, the insulator 224 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into a region above the insulator 224. Therefore, it is preferable to use, for example, a material that can be used for the insulator 324 as the insulator 224.

[0551] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, the insulator 226 is preferably made of a material that can be used for the insulator 326, for example.

[0552] A conductor 230 electrically connected to the transistor 200, the light-emitting device 150, etc. is embedded in the insulator 224 and the insulator 226. The conductor 230 functions as a plug or wiring. For the conductor 230, for example, a material applicable to the conductor 328 or the conductor 330 can be used.

[0553] On the insulators 224 and 226, the insulators 250, 111a, and 111b are stacked in this order.

[0554] The insulator 250 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 250 can be made of, for example, a material that can be used for the insulator 324.

[0555] The insulators 111a and 111b can be formed using various inorganic insulating films such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, and an insulating nitride oxide film. The insulator 111a is preferably formed using an insulating oxide film or an oxynitride insulating film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. The insulator 111b is preferably formed using a nitride insulating film or a nitride oxide insulating film such as a silicon nitride film or a silicon nitride oxide film. More specifically, it is preferable to use a silicon oxide film as the insulator 111a and a silicon nitride film as the insulator 111b. The insulator 111b preferably functions as an etching protective film. Alternatively, the insulator 111a may be formed using a nitride insulating film or a nitride oxide insulating film, and the insulator 111b may be formed using an oxide insulating film or an oxynitride insulating film. While this embodiment illustrates an example in which a recess is provided in the insulator 111b, the insulator 111b does not necessarily have a recess.

[0556] Furthermore, openings are formed in the regions of the insulator 250, the insulator 111a, and the insulator 111b that overlap with part of the conductor 230, and the conductor 121 is provided to fill the openings. Note that in this specification and the like, the conductors 121a and 121b shown in FIG. 22 are collectively referred to as the conductor 121. Note that the conductor 121 can be provided using the same material as the conductor 328 and the conductor 330.

[0557] In addition, the pixel electrode described in this embodiment mode includes, for example, a material that reflects visible light, and the counter electrode includes a material that transmits visible light.

[0558] The display device 1000 is a top-emission type. Light emitted from the light-emitting device is emitted toward the substrate 102. The substrate 102 is preferably made of a material that is highly transparent to visible light.

[0559] Above the conductor 121, a light emitting device 150a and a light emitting device 150b are provided.

[0560] Here, the light emitting device 150a and the light emitting device 150b will be described.

[0561] The light-emitting device described in this embodiment refers to a self-luminous light-emitting device such as an organic light-emitting diode (OLED). The light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0562] The conductor 122a and the conductor 122b can be formed, for example, by forming a conductive film over the insulator 111b, the conductor 121a, and the conductor 121b, and then performing a patterning process and an etching process on the conductive film.

[0563] The conductor 122a and the conductor 122b function as the anodes of the light emitting device 150a and the light emitting device 150b included in the display device 1000, respectively, as an example.

[0564] For example, indium tin oxide (sometimes called ITO) can be used as the conductor 122a and the conductor 122b.

[0565] Furthermore, each of the conductors 122a and 122b may have a laminated structure of two or more layers instead of a single layer. For example, a conductor with high reflectivity to visible light may be used for the first layer of the conductor, and a conductor with high translucency may be used for the top layer of the conductor. Examples of conductors with high reflectivity to visible light include silver, aluminum, and an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high translucency include the above-mentioned indium tin oxide. Examples of the conductors 122a and 122b include a laminated film of aluminum sandwiched between a pair of titanium films (a laminated film of Ti, Al, and Ti in this order), a laminated film of silver sandwiched between a pair of indium tin oxide films (a laminated film of ITO, Ag, and ITO in this order), etc.

[0566] An EL layer 141a is provided on the conductor 122a, and an EL layer 141b is provided on the conductor 122b.

[0567] It is preferable that the EL layer 141a and the EL layer 141b each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits light of one of red (R), green (G), and blue (B), and the EL layer 141b may have a light-emitting layer that emits light of one of the remaining two. Although not shown in FIG. 22, if an EL layer other than the EL layer 141a and the EL layer 141b is provided, the EL layer may have a light-emitting layer that emits light of the remaining one. In this way, the display device 1000 may have a structure (SBS structure) in which different light-emitting layers for each color are formed on multiple pixel electrodes (conductors 121a and 121b).

[0568] The combination of colors emitted by the light-emitting layers included in the EL layer 141a and the EL layer 141b is not limited to the above, and colors such as cyan, magenta, and yellow may also be used. Furthermore, although an example of three colors is shown above, the number of colors emitted by the light-emitting device 150 included in the display device 1000 may be two, three, or four or more.

[0569] The EL layer 141a and the EL layer 141b may each have one or more layers selected from an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0570] In addition, the EL layer 141a and the EL layer 141b can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (e.g., dip coating method, die coating method, bar coating method, spin coating method, or spray coating method), or a printing method (e.g., inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexography (relief printing) method, gravure method, or microcontact method).

[0571] When applying the above-mentioned coating method, printing method, or other film formation method, high molecular weight compounds (e.g., oligomers, dendrimers, and polymers), medium molecular weight compounds (compounds in the intermediate range between low molecular weight and high molecular weight: molecular weight 400 to 4000), or inorganic compounds (quantum dot materials, etc.) can be used. The quantum dot materials can include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0572] For example, light emitting device 150a and light emitting device 150b in FIG. 22 can be configured with multiple layers such as light emitting layer 4411 and layer 4430, like light emitting device 150 shown in FIG. 23A.

[0573] The layer 4420 can have, for example, a layer containing a substance with a high electron-injecting property (electron-injecting layer) and a layer containing a substance with a high electron-transporting property (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole-injecting property (hole-injecting layer) and a layer containing a substance with a high hole-transporting property (hole-transporting layer).

[0574] A structure having a layer 4420, a light-emitting layer 4411, and a layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 23A is called a single structure.

[0575] 23B shows a modified example of the EL layer 141 of the light-emitting device 150 shown in Fig. 23A. Specifically, the light-emitting device 150 shown in Fig. 23B has a layer 4430-1 on the conductor 121, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 122 on the layer 4420-2. For example, when the conductor 121 is the anode and the conductor 122 is the cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductor 121 is used as a cathode and the conductor 122 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0576] Note that a configuration in which a plurality of light-emitting layers (for example, light-emitting layer 4411, light-emitting layer 4412, and light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 23C is also a variation of the single structure.

[0577] A laminate having multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430, may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 23D, multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification and elsewhere, a tandem structure may also be referred to as a stack structure. By forming a light-emitting device in a tandem structure, a light-emitting device capable of emitting light with high brightness may be obtained. By forming a light-emitting device in a tandem structure, the light-emitting efficiency and lifespan of the light-emitting device may be improved. When the light-emitting device 150 of the display device 1000 of FIG. 22 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0578] Furthermore, when displaying white, the SBS structure described above can reduce power consumption compared to the single and tandem structures. Therefore, if you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs and higher manufacturing yields.

[0579] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0580] A light-emitting device that emits white light preferably has a structure in which the light-emitting layer contains two or more light-emitting materials. To obtain white light, it is sufficient to select two or more light-emitting materials whose respective emissions are complementary colors.

[0581] The light-emitting layer preferably contains two or more light-emitting materials having emission colors selected from R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, the light-emitting layer preferably contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials preferably contains spectral components of two or more colors selected from R, G, and B.

[0582] 22, a gap is provided between two EL layers between adjacent light-emitting devices. Specifically, in FIG. 22, a recess is formed between adjacent light-emitting devices, and an insulator 112 is provided to cover the side surfaces (side surfaces of the conductor 121a, the conductor 122a, and the EL layer 141a, and side surfaces of the conductor 121b, the conductor 122b, and the EL layer 141b) and the bottom surface (a portion of the insulator 111b) of the recess. An insulator 162 is also formed on the insulator 112 to fill the recess. In this manner, it is preferable that the EL layer 141a and the EL layer 141b are provided so as not to contact each other. This can suitably prevent unintended light emission (also known as crosstalk) caused by current (also known as lateral leakage current) flowing through the two adjacent EL layers. This can improve contrast and realize a display device with high display quality. Furthermore, for example, by configuring the display device so that the lateral leakage current between the light-emitting devices is extremely low, the black display performed by the display device can be a display with extremely little light leakage (also called true black display).

[0583] The EL layer 141a and the EL layer 141b can be formed, for example, by a method using photolithography. For example, an EL film to become the EL layer 141a and the EL layer 141b is formed on the conductor 122, and then the EL film is patterned by photolithography to form the EL layer 141a and the EL layer 141b. This also makes it possible to provide a gap between the two EL layers between adjacent light-emitting devices.

[0584] However, when an EL film is patterned using photolithography, damage (damage due to processing) may occur in the light-emitting layer, etc., which may significantly impair reliability. Therefore, when manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a method in which a sacrificial layer or the like is formed on a layer located above the light-emitting layer (e.g., a carrier transport layer or a carrier injection layer, more specifically, an electron transport layer or an electron injection layer), and the light-emitting layer is processed into an island shape. By applying this method, a highly reliable semiconductor device can be provided.

[0585] The insulator 112 can be an insulating layer containing an inorganic material. The insulator 112 can be, for example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. The insulator 112 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, an aluminum oxide film is preferable because it has a high etching selectivity with respect to the EL layer and protects the EL layer in the formation of the insulator 162, which will be described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD (Atomic Layer Deposition) method as the insulator 112, it is possible to form an insulator 112 with few pinholes and excellent function of protecting the EL layer.

[0586] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0587] The insulator 112 can be formed by a sputtering method, a CVD method, a PLD (Pulsed Laser Deposition) method, or an ALD method. The insulator 112 is preferably formed by an ALD method, which has good coverage.

[0588] The insulator 162 provided on the insulator 112 has the function of flattening recesses formed in the insulator 112 between adjacent light-emitting devices. In other words, the insulator 162 has the effect of improving the flatness of the surface on which the conductor 123 (described later) is formed. For example, an insulating layer containing an organic material can be suitably used as the insulator 162. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins can be used as the insulator 162. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the insulator 162. Alternatively, for example, a photosensitive resin can be used as the photosensitive resin. For example, a photoresist can be used as the photosensitive resin. The photosensitive resin may be a positive type material or a negative type material.

[0589] The difference in height between the top surface of the insulator 162 and the top surface of the EL layer 141a or 141b is, for example, preferably 0.5 times or less, more preferably 0.3 times or less, the thickness of the insulator 162. Alternatively, for example, the insulator 162 may be provided so that the top surface of the EL layer 141a or 141b is higher than the top surface of the insulator 162. Alternatively, for example, the insulator 162 may be provided so that the top surface of the insulator 162 is higher than the top surface of the light-emitting layer of the EL layer 141a or 141b.

[0590] A conductor 123 is provided on the EL layer 141a, the EL layer 141b, the insulator 112, and the insulator 162. An insulator 113 is provided on each of the light-emitting devices 150a and 150b.

[0591] The conductor 123 functions as, for example, a common electrode for the light-emitting device 150a and the light-emitting device 150b. In order to emit light from the light-emitting device 150 upward from the display device 1000, the conductor 123 preferably includes a light-transmitting conductive material.

[0592] The conductor 123 is preferably a material that is highly conductive and has light-transmitting and light-reflecting properties (sometimes called a semi-transparent / semi-reflective electrode). For example, an alloy of silver and magnesium or indium tin oxide can be used for the conductor 123.

[0593] The insulator 113 is sometimes referred to as a protective layer, and providing the insulator 113 above each of the light-emitting device 150a and the light-emitting device 150b can improve the reliability of the light-emitting devices. In other words, the insulator 113 functions as a passivation film that protects the light-emitting device 150a and the light-emitting device 150b. Therefore, the insulator 113 is preferably made of a material that prevents the intrusion of water, for example. The insulator 113 can be made of a material that can be used for the insulator 111a or the insulator 111b, for example. Specifically, aluminum oxide, silicon nitride, or silicon nitride oxide can be used.

[0594] A resin layer 163 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 163.

[0595] The substrate 102 is preferably, for example, a light-transmitting substrate. By using a light-transmitting substrate for the substrate 102, light emitted from the light-emitting device 150a and the light-emitting device 150b can be emitted upward from the substrate 102.

[0596] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device 1000 illustrated in Fig. 22. The configuration of the display device of one embodiment of the present invention may be changed as appropriate within the scope of solving the problem.

[0597] For example, the transistor 200 included in the pixel layer PXAL of the display device 1000 in Fig. 22 may be a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). The display device 1000 shown in Fig. 24 has a configuration in which a transistor 500 (OS transistor) replacing the transistor 200 and a light-emitting device 150 are provided above the circuit layer SICL and wiring layer LINL of the display device 1000 in Fig. 22.

[0598] 24, the transistor 500 is provided over an insulator 512. The insulator 512 is provided over the insulator 364 and the conductor 366, and a substance that has a barrier property against oxygen and hydrogen is preferably used for the insulator 512. Specifically, the insulator 512 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0599] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, diffusion of hydrogen into a semiconductor element (e.g., the transistor 500) having an oxide semiconductor may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0600] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0601] An insulator 514 is provided over the insulator 512, and the transistor 500 is provided over the insulator 514. An insulator 576 is formed over the insulator 512 to cover the transistor 500. An insulator 581 is formed over the insulator 576.

[0602] The insulator 514 is preferably a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0603] As described above, the transistor 500 illustrated in FIG. 24 is an OS transistor including a metal oxide in a channel formation region. Examples of the metal oxide include an In-M-Zn oxide containing indium, an element M, and zinc (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). Specifically, for example, an oxide containing indium, gallium, and zinc (sometimes referred to as IGZO) may be used. For example, an oxide containing indium, aluminum, and zinc (sometimes referred to as IAZO) may be used. For example, an oxide containing indium, aluminum, gallium, and zinc (sometimes referred to as IAGZO) may be used. In addition to the above, the metal oxide may be an In-Ga oxide, an In-Zn oxide, or an indium oxide.

[0604] In particular, it is preferable to use a metal oxide functioning as a semiconductor having a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide having a wide band gap, the off-state current (sometimes called leakage current) of a transistor can be reduced.

[0605] In particular, it is preferable to use a transistor, such as an OS transistor, whose off-state current is sufficiently small even when the source-drain voltage is large as the driving transistor included in the pixel circuit. By using an OS transistor as the driving transistor, the amount of off-state current flowing in the light-emitting device can be reduced when the driving transistor is in an off-state, thereby sufficiently reducing the luminance of light emitted from the light-emitting device through which the off-state current flows. Therefore, when comparing a driving transistor with a large off-state current with a driving transistor with a small off-state current, when black is displayed in the pixel circuit, the pixel circuit including the driving transistor with a small off-state current can have a lower luminance than the pixel circuit including the driving transistor with a large off-state current. In other words, by using an OS transistor, it is possible to suppress floating black when black is displayed in the pixel circuit.

[0606] The off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 aA (1 × 10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1 x 10 -24 A) or less. Note that the off-state current of a Si transistor per 1 μm of channel width at room temperature is 1 fA (1×10 -15 A) More than 1pA (1×10 -12 Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0607] Furthermore, to increase the emission luminance of a light-emitting device included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. OS transistors have a higher source-drain withstand voltage compared to Si transistors, so a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the drive transistor included in a pixel circuit, a high voltage can be applied between the source and drain of the OS transistor, thereby increasing the amount of cur...

Claims

[Claim 1] a first circuit and a second circuit, the first circuit includes a light emitting device; the second circuit includes a light receiving device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor; the light receiving device has a first terminal and a second terminal; the light emitting device has a third terminal and a fourth terminal; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor; a gate of the second transistor is electrically connected to one of the source or the drain of the third transistor and one of a pair of terminals of the first capacitor; the other of the pair of terminals of the first capacitor is electrically connected to one of the source or the drain of the fourth transistor and one of the source or the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the first terminal of the light-receiving device; the second terminal of the light-receiving device is electrically connected to the third terminal of the light-emitting device; the fourth terminal of the light emitting device is electrically connected to a first wiring; the first wiring functions as a wiring that applies a potential to the fourth terminal of the light-emitting device; Semiconductor device.

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