Solid-state imaging device, driving method for solid-state imaging device, and electronic device

Abstract

Provided are a solid-state imaging device, a driving method for a solid-state imaging device, and electronic equipment that can suppress increases in power consumption and circuit area, achieve a high dynamic range, and ultimately realize a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four transistor pixels at low cost. [Solution] In a dual conversion gain system, a readout unit 70 reads out two readout signals, an HCG signal and an LCG signal, and combines them into a high dynamic range (HDR) signal, and controls the HCG signal response characteristics of the first conversion gain signal readout process and the LCG signal response characteristics of the second conversion gain signal readout process to be different characteristics.

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art CMOS (Complementary Metal Oxide Semiconductor) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0003] CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is a column-parallel output type that selects a row in the pixel array and reads out the pixels simultaneously in the column direction.

[0004] Incidentally, the pixel configuration of a solid-state imaging device (CMOS image sensor) can be exemplified by a basic pixel having a four-transistor (4Tr) configuration in which, for one photodiode (photoelectric conversion element), there is one transfer transistor as a transfer element, one reset transistor as a reset element, one source follower transistor as a source follower element, and one selection transistor as a selection element.

[0005] The transfer transistor is selected and turned on during a predetermined transfer period, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode to the floating diffusion FD serving as a detection node. The reset transistor is selected and turned on during a predetermined reset period, resetting the floating diffusion FD to the potential of the power supply line. The select transistor is selected and turned on during read scanning, which causes the source follower transistor to output the column output read signal converted into a voltage signal by the floating diffusion FD to the vertical signal line.

[0006] For example, during a read scan period, after the floating diffusion FD is reset to, for example, the potential (reference potential) of the power supply line during the reset period, the charge of the floating diffusion FD is converted into a voltage signal with a gain according to the FD capacitance and output to the vertical signal line as a reference level read reset signal (reference level signal) Vrst. Subsequently, during a predetermined transfer period, the charges (electrons) photoelectrically converted and accumulated in the photodiode are transferred to the floating diffusion FD. The charges in the floating diffusion FD are then converted into a voltage signal with a gain according to the FD capacitance, and output to the vertical signal line as a signal level readout signal (signal level signal) Vsig. The output signal of the pixel is processed by CDS (Correlated Double Sampling) as a differential signal (Vsig-Vrst) in the column readout circuit.

[0007] In this way, a normal pixel read signal (hereinafter sometimes referred to as a pixel signal) PS is formed by a read reset signal Vrst of one reference level and a read signal Vsig of one signal level.

[0008] In order to improve the characteristics, various methods have been proposed for realizing a high-quality solid-state imaging device (CMOS image sensor) having a high dynamic range (HDR).

[0009] One approach to achieving a high dynamic range is to use a lateral overflow integration capacitor (LOFIC) (see, for example, Patent Document 1). A pixel with a LOFIC configuration has a storage capacitor and a storage transistor added to the basic configuration described above, and the oversaturated charge that overflows from the photodiode during the same exposure time is stored in the storage capacitor instead of being discarded.

[0010] This LOFIC pixel can have two types of conversion gain: one due to the floating diffusion capacitance Cfd1 (high gain side: proportional to 1 / Cfd1), and the other due to the floating diffusion capacitance Cfd1 + the LOFIC capacitance Clofic of the storage capacitor C2 (low gain side: proportional to 1 / (Cfd1+Clofic)). That is, in the LOFIC pixel, a low conversion gain (LCG) signal and a high conversion gain (HCG) signal are used to achieve full well capacitance and small dark noise, respectively.

[0011] However, LOFIC has a significant problem of SNR degradation at the junction of the high conversion gain (HCG) and low conversion gain (LCG) signals. That is, the LOFIC configuration alone cannot remove the kTC noise of the LCG signal, resulting in a decrease in SNR at the junction of the HCG signal and the LCG signal.

[0012] The signal directions of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal are opposite to each other, and in the readout process using the low conversion gain (LCG), the reset noise of the readout reset signal VRST is different from the reset noise of the readout luminance signal VSIG, making it difficult to remove the reset noise using a subtraction process called differential double sampling (DDS).

[0013] In a CMOS image sensor, photoelectric charges generated and accumulated in a photodiode are read out by sequentially scanning each pixel or each row. When using progressive scanning, i.e., a rolling shutter as an electronic shutter, the start and end times of exposure for accumulating photocharges cannot be made consistent for all pixels, which causes the problem of distortion in captured images when capturing moving subjects.

[0014] Therefore, for applications such as capturing images of fast-moving subjects where image distortion is unacceptable, or sensing applications that require simultaneous capture of captured images, a global shutter is used as the electronic shutter, which starts and ends exposure for all pixels in the pixel array at the same time.

[0015] A CMOS image sensor that employs a global shutter as an electronic shutter is provided with a signal holding section in each pixel, for example, that holds a signal read out from a readout section in a signal holding capacitor. In a CMOS image sensor that uses a global shutter, charges from the photodiodes are simultaneously stored as voltage signals in the signal holding capacitors of the signal holding section using an analog sample-and-hold operation, and then the signals are read out sequentially, ensuring the simultaneity of the entire image (see, for example, Non-Patent Document 1).

[0016] As typical pixel configurations, a four-transistor (4Tr) APS pixel (see, for example, Patent Document 2) or a capacitive feedback transimpedance amplifier (CTIA) pixel (see, for example, Patent Documents 3 and 4) are known.

[0017] Known pixels with a global shutter function for a high-quality CMOS image sensor with a wide dynamic range include VMGS (voltage-mode global shutter) pixels and CMGS (charge-mode global shutter) pixels.

[0018] Of these, VMGS pixels have the advantages of higher shutter efficiency and lower parasitic light sensitivity (PLS) compared to CMGS pixels.

[0019] In recent years, there has been an increasing demand for global shutter (GS) CMOS image sensors (CIS), especially in the fields of machine vision and IoT (Internet of Things). In these fields, there is a strong demand for not only GS functionality but also single exposure high dynamic range (SEHDR) performance. [Prior art documents] [Patent documents]

[0020] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-328493 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-65074 Figure 2 [Patent Document 3] Special Publication No. 2006-505975 [Patent Document 4] Special Publication No. 2002-501718 [Non-patent literature]

[0021] [Non-Patent Document 1] J. Aoki, et al., “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node” ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3. Summary of the Invention [Problem to be solved by the invention]

[0022] As described above, in a CMOS image sensor, a pixel can be configured to achieve a large well capacitance (saturation) and small dark noise by using a low conversion gain (LCG) signal and a high conversion gain (HCG) signal, respectively. This method is called the dual conversion gain (DCG) method.

[0023] FIG. 1 is a diagram illustrating a pixel of a typical DCG CMOS image sensor.

[0024] The pixels of a conventional DCG CMOS image sensor are configured to switch between binning switches BIN1 and BIN2, each consisting of six transistors, as shown in Figure 1. The two readout signals from the binning switches BIN1 and BIN2 are read out and combined into an HDR signal.

[0025] However, conventional DCG CMOS image sensors have the disadvantage that the pixel size increases because components are added to the pixel, which increases the number of driver circuits, resulting in increased power consumption and chip costs. As a result, it is currently difficult to realize a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four transistor pixels at low cost.

[0026] The present invention aims to provide a solid-state imaging device, a method for driving a solid-state imaging device, and electronic equipment that can suppress increases in power consumption and circuit area, achieve a high dynamic range, and ultimately realize a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four-transistor pixels at low cost. [Means for solving the problem]

[0027] A solid-state imaging device according to a first aspect of the present invention includes a pixel section in which readout pixels capable of reading out a first conversion gain signal and a second conversion gain signal as pixel signals are arranged, and a readout section that reads out the pixel signals from the readout pixels of the pixel section, wherein the readout pixels include a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period, a transfer element that can transfer the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period, a floating diffusion as a detection node to which the charges accumulated in the photoelectric conversion element are transferred through the transfer element, a reset element that discharges at least the accumulated charges in the floating diffusion to a reset potential, a source follower element that amplifies and outputs a voltage signal converted using the first conversion gain and the second conversion gain, and a selection element that enables the floating diffusion to output a voltage signal to a signal line during a selection period. wherein no transistor elements other than the four transistor elements of the transfer element, the floating diffusion, the reset element, and the selection element are added as components within the pixel, and the readout unit controls the readout pixel to perform a first conversion gain signal readout process in which a pixel signal is read out at a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process in which a pixel signal is read out at a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, and a dual conversion gain system for small pixels is applied, and in the dual conversion gain system, the readout unit reads out two readout signals, an HCG signal and an LCG signal, and combines them into a high dynamic range (HDR) signal, and controls so that the HCG signal response characteristics of the first conversion gain signal readout process and the LCG signal response characteristics of the second conversion gain signal readout process are different characteristics.

[0028] A second aspect of the present invention provides a solid-state imaging device including: a pixel section in which readout pixels capable of reading out a first conversion gain signal and a second conversion gain signal as pixel signals are arranged; and a readout section that reads out the pixel signals from the readout pixels of the pixel section, wherein the readout pixels include: a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element that is capable of transferring the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period; a floating diffusion as a detection node to which the charges accumulated in the photoelectric conversion element are transferred via the transfer element; a reset element that discharges at least the accumulated charges in the floating diffusion to a reset potential; a source follower element that amplifies and outputs a voltage signal converted with the first conversion gain and the second conversion gain; and a selection element that enables output of a voltage signal by the floating diffusion to a signal line during a selection period. a driving method for a pixel including a transfer element, a floating diffusion, a reset element, and a selection element; wherein no transistor elements other than four transistor elements, i.e., the transfer element, the floating diffusion, the reset element, and the selection element, are added as components within the pixel; and wherein the readout unit controls the readout pixel to perform a first conversion gain signal readout process in which a pixel signal is read out at a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process in which a pixel signal is read out at a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, and a dual conversion gain system for small pixels is applied; and the readout unit controls such that, in the dual conversion gain system, two readout signals, an HCG signal and an LCG signal, are read out and combined into a high dynamic range (HDR) signal, and the HCG signal response characteristics of the first conversion gain signal readout process and the LCG signal response characteristics of the second conversion gain signal readout process are different from each other.

[0029] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, the solid-state imaging device including a pixel section in which readout pixels capable of reading out a first conversion gain signal and a second conversion gain signal as pixel signals are arranged, and a readout section for reading out the pixel signals from the readout pixels of the pixel section, the readout pixels including a photoelectric conversion element for accumulating charges generated by photoelectric conversion during an accumulation period, a transfer element for transferring the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period, a floating diffusion as a detection node to which the charges accumulated in the photoelectric conversion element are transferred via the transfer element, a reset element for discharging at least the accumulated charges in the floating diffusion to a reset potential, a source follower element for amplifying and outputting a voltage signal converted with the first conversion gain and the second conversion gain, and a voltage signal generated by the floating diffusion during a selection period. and a selection element that enables output of a signal to a signal line, wherein no transistor elements other than the four transistor elements of the transfer element, the floating diffusion, the reset element, and the selection element are added as components within the pixel, and the readout unit controls the readout pixel to perform a first conversion gain signal readout process that reads out a pixel signal at a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process that reads out a pixel signal at a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, a dual conversion gain system for small pixels is applied, and in the dual conversion gain system, the readout unit reads out two readout signals, an HCG signal and an LCG signal, and combines them into a high dynamic range (HDR) signal, and controls so that the HCG signal response characteristics of the first conversion gain signal readout process and the LCG signal response characteristics of the second conversion gain signal readout process are different characteristics. [Effects of the Invention]

[0030] According to the present invention, it is possible to suppress increases in power consumption and circuit area, and furthermore to achieve a high dynamic range, thereby enabling a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four-transistor pixels to be realized at low cost. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 is a diagram illustrating a basic pixel having a four-transistor (4Tr) configuration in a CMOS image sensor and a pixel in a conventional DCCMOS image sensor. [Figure 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Figure 3] FIG. 2 is a circuit diagram illustrating an example of a readout pixel according to the first embodiment of the present invention. [Figure 4] 4 is a timing chart showing an example of a readout sequence of a readout pixel in the solid-state imaging device according to the first embodiment of the present invention. [Figure 5] 5A and 5B are diagrams illustrating an operation sequence and potential transitions for explaining an operation in a readout process of an HCG signal and an LCG signal in a conversion gain readout mode of the solid-state imaging device according to the first embodiment of the present invention. [Figure 6] 1 is a flowchart illustrating how deep neural networks (DNNs) can be trained to improve accuracy in machine vision applications. [Figure 7] 10A and 10B are diagrams for explaining the linearity of an LCG signal during a conversion gain signal readout process in which a DCG method for small pixels is adopted, in relation to potential transition. [Figure 8] 4A to 4C are diagrams illustrating an example of multiple conversion gains applied to a readout process of an HCG signal and an LCG signal in a conversion gain readout mode of the solid-state imaging device according to the first embodiment of the present invention. [Figure 9]4A to 4C are diagrams illustrating an operation sequence and potential transitions for explaining shutter processing in a conversion gain readout mode of the solid-state imaging device according to the first embodiment of the present invention, and operations in readout processing of an HCG signal and an LCG signal. [Figure 10] 10A and 10B are diagrams illustrating an operation sequence and potential transitions for explaining the operation in the second overflow charge accumulation process employed in the solid-state imaging device according to the first embodiment of the present invention. [Figure 11] 10A and 10B are diagrams illustrating an operation sequence and potential transitions for explaining the operation in the second overflow charge accumulation process employed in the solid-state imaging device according to the first embodiment of the present invention. [Figure 12] FIG. 10 is a circuit diagram showing an example of the configuration of a readout pixel and a main part of a pixel signal processing unit according to a second embodiment of the present invention. [Figure 13] FIG. 10 is a circuit diagram showing an example of the configuration of a readout pixel and a pixel signal processing unit according to a third embodiment of the present invention. [Figure 14] FIG. 10 is a simplified cross-sectional view showing a main part of a readout pixel having a deep PD structure according to a fourth embodiment of the present invention. [Figure 15] FIG. 10 is a simplified cross-sectional view showing a main part of a readout pixel having a large transfer gate (TG) structure according to a fifth embodiment of the present invention. [Figure 16] FIG. 10 is a simplified cross-sectional view showing a main part of a readout pixel having a large transfer gate (TG) structure and a divided structure of the transfer gate (TG) according to a sixth embodiment of the present invention. [Figure 17] FIG. 13 is a circuit diagram showing an example of the configuration of a readout pixel that employs a DCG system according to a seventh embodiment of the present invention and that can be applied to a pixel sharing structure. [Figure 18] FIG. 13 is a timing chart showing an example of an operation sequence of a readout pixel that employs a DCG system according to a seventh embodiment of the present invention and that is applicable to a pixel sharing structure. [Figure 19]13A and 13B are a circuit diagram showing an example of the configuration of a readout pixel that employs a DCG method according to an eighth embodiment of the present invention and that is applicable to an asymmetric four-pixel sharing structure, and a timing chart showing an example of the operation sequence of the readout pixel that is applicable to the asymmetric pixel sharing structure. [Figure 20] FIG. 13 is a timing chart showing an example of an operation sequence of a readout pixel that employs a DCG system according to an eighth embodiment of the present invention and that is applicable to an asymmetric pixel sharing structure. [Figure 21] FIG. 13 is a diagram for explaining a ninth embodiment of the present invention, and is a diagram for explaining a method for adjusting a conversion gain (CG) in an LCG mode. [Figure 22] FIG. 20 is a diagram illustrating a readout pixel employing a DCG method according to a tenth embodiment of the present invention, for explaining one readout process using high dynamic range imaging. [Figure 23] FIG. 22 is a diagram schematically illustrating a solid-state imaging device employing a DCG method according to an eleventh embodiment of the present invention, which functions as an object detection device. [Figure 24] 1 is a diagram illustrating an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0033] (First embodiment) FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of a four-transistor readout pixel in the solid-state imaging device according to the first embodiment of the present invention. 4A to 4C are timing charts showing an example of a readout sequence of a readout pixel in the solid-state imaging device according to the first embodiment of the present invention.

[0034] In this embodiment, the solid-state imaging device 10 is configured by, for example, a DCGCMOS image sensor. The pixel of the DCGCMOS image sensor of this embodiment can be realized at low cost as a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four transistor pixels.

[0035] As shown in FIG. 2, the solid-state imaging device 10 has, as its main components, a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40 including a pixel signal processing section 400, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout unit 70.

[0036] In the first embodiment, the readout pixels 200 arranged in a matrix in the pixel section 20 basically have a configuration as shown in FIG. That is, the readout pixel 200 is composed of a floating diffusion FD11 as a detection node that holds the transferred charge in order to read it out as a voltage signal, a photodiode PD11 as a photoelectric conversion element that accumulates charge according to the amount of incident light during the exposure period PEXP, a transfer transistor TG11-Tr as a transfer element that is held in a non-conductive state during the exposure period PEXP and held in a conductive state during the transfer period to transfer the charge accumulated in the photodiode PD11 as the photoelectric conversion element to the floating diffusion FD11, and a reset transistor RST11-Tr as a reset element that is capable of performing a reset process to discharge the accumulated charge in the floating diffusion FD11.

[0037] The readout pixel 200 may be formed with an overflow path OVFP that allows the charge overflowing from the photodiode PD11 serving as a photoelectric conversion element to overflow through the transfer transistor TG11-Tr toward the region where the floating diffusion FD11 is formed.

[0038] The readout pixel 200 includes a source follower transistor SF11-Tr as a source follower element that outputs a voltage signal converted by the floating diffusion FD11, and a selection transistor SEL11-Tr as a selection element.

[0039] The readout pixel 200 of this embodiment can, under the control of the readout unit 70, change the capacitance of the floating diffusion FD11 to a first capacitance C1 or a second capacitance C2, and switch the conversion gain to a first conversion gain determined by the first capacitance C1 (e.g., high conversion gain: HCG: High Conversion Gain) or a second conversion gain determined by the second capacitance C2 (e.g., low conversion gain: LCG: Low Conversion Gain).

[0040] In this way, under the control of the readout unit 70, the solid-state imaging device 10 is configured to be able to perform a first conversion gain mode readout in which pixel signals are read out with a first conversion gain (high conversion gain: HCG) corresponding to the first capacitance C1, and a second conversion gain mode readout in which pixel signals are read out with a second conversion gain (low conversion gain: LCG) corresponding to the second capacitance (different from the first capacitance) C2, during a specified dual conversion gain readout mode period, as shown in FIG.

[0041] In this first embodiment, the readout pixel 200 performs dual conversion gain signal readout, which involves first conversion gain signal readout, in which pixel signals are read out with a first conversion gain (e.g., high conversion gain: HCG) corresponding to the first capacitance C1, and second conversion gain signal readout, in which pixel signals are read out with a second conversion gain (e.g., low conversion gain: LCG) corresponding to the second capacitance (different from the first capacitance) C2. In this first embodiment, the readout process for the readout pixel 200 is as follows: first, in the first conversion gain signal readout mode, the first readout reset signal HCGRST (HCGrst) is read out, and then the first readout luminance signal HCGSIG (HCGsig) is read out, as shown in FIG. Subsequently, in the second conversion gain signal readout mode, the second readout luminance signal LCGSIG (LCGsig) is read out, and then the second readout reset signal LCGRST (LCGrst) is read out.

[0042] In this way, the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST) read out as the pixel signal PXLOUT from the readout pixel 200 are formed as signals with opposite signal directions (level transition directions).

[0043] (DCG (dual conversion gain) method for small pixels) In the readout section 70 of the first embodiment, a DCG (dual conversion gain) method for small pixels is applied as the readout method. In the DCG (dual conversion gain) method for small pixels of the first embodiment, no transistor elements other than the four transistor elements of the transfer transistor TG11-Tr as a transfer element, the reset transistor RST11-Tr as a reset element, the source follower transistor SF11-Tr as a source follower element, and the select transistor SEL11-Tr as a select element are added as components within the pixel. The readout unit 70 applies a DCG (dual conversion gain) method for small pixels, which controls the readout pixel 200 to perform a first conversion gain signal readout process in which pixel signals are read out with a first conversion gain (HCG) corresponding to a first capacitance C1, and a second conversion gain signal readout process in which pixel signals are read out with a second conversion gain (LCG) corresponding to a second capacitance (different from the first capacitance) C2.

[0044] In the readout unit 70, two readout signals, an HCG signal and an LCG signal, are read out in accordance with the DCG (dual conversion gain) method and combined into a high dynamic range (HDR) signal, and the HCG signal linearity in the first conversion gain (HCG) signal readout process and the LCG signal linearity in the second conversion gain (LCG) signal readout process are controlled to have different characteristics.

[0045] In the first embodiment, the readout section 70 controls so that the LCG signal linearity in the second conversion gain (LCG) signal readout process is lower than the HCG linearity in the first conversion gain (HCG) signal readout process.

[0046] In addition, in the readout unit 70, as a readout process for a readout pixel, as shown in FIG. 4, first, in the first conversion gain signal readout mode, the first readout reset signal HCGRST is read out, and then the first readout luminance signal HCGSIG is read out. Subsequently, in the second conversion gain signal readout mode, the second readout luminance signal LCGSIG is read out, and then the second readout reset signal LCGRST is read out.

[0047] (Specific circuit configuration of pixel 200) Here, a specific circuit configuration of the readout pixel 200 shown in the figure will be described.

[0048] In the pixel section 20, readout pixels 200, each including a photodiode (photoelectric conversion element) and an in-pixel amplifier, are arranged in a two-dimensional matrix of N rows and M columns.

[0049] As shown in FIG. 3, for example, this readout pixel 200 includes a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a transfer element, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, and a floating diffusion FD11 as a detection node.

[0050] In addition, in the readout pixel 200, the capacitance CFD of the floating diffusion FD11 is formed by a very small capacitance CFD for low noise. The capacitance of the gate capacitance of the transfer transistor TG11-Tr is set to a very large value for a high FWC (Full Well Capacity). The capacitance CFD of the floating diffusion FD11 is used for the high conversion gain (HCG), and the electrostatic capacitance such as the gate capacitance of the transfer transistor TG11-Tr is also used for the low conversion gain (LCG).

[0051] The photodiode PD11 generates and accumulates signal charges (electrons in this case) in an amount corresponding to the amount of incident light. In the following, the case where the signal charges are electrons and each transistor is an n-type transistor will be described, but the signal charges may be holes and each transistor may be a p-type transistor.

[0052] In each readout pixel 200, a buried photodiode (PPD) is used as the photodiode (PD). The surface of the substrate on which the photodiode (PD) is formed has interface states due to defects such as dangling bonds, which can generate a large amount of charge (dark current) due to thermal energy, making it impossible to read out the correct signal. In a buried photodiode (PPD), the charge storage section of the photodiode (PD) is embedded in the substrate, which makes it possible to reduce the dark current from mixing into the signal.

[0053] The transfer transistor TG11-Tr is connected between the photodiode PD11 and the floating diffusion FD11, and is controlled via a control signal ΦTG. The transfer transistor TG11-Tr is selected and turned on while the control signal ΦTG is at high level (H), and transfers the charges (electrons) photoelectrically converted by the photodiode PD11 and stored in the storage node to the floating diffusion FD11.

[0054] In the example of FIG. 3, the reset transistor RST11-Tr is connected between the power supply potential VAAPIX and the floating diffusion FD11, and is controlled via a control signal ΦRST. The reset transistor RST11-Tr is selected and turned on while the control signal ΦRST is at H level, and resets the floating diffusion FD11 to the power supply potential VAAPIX.

[0055] In the first embodiment, the reset transistor RST11-Tr and the transfer transistor TG11-Tr are maintained in a conductive state, and the floating diffusion FD11 and the photodiode PD11 are reset. In the first embodiment, the reset transistor RST11-Tr is maintained in a conductive state to reset the floating diffusion FD11.

[0056] In the first embodiment, the overflow path OVFP is formed as a path that can transfer the overflow charge of the photodiode PD11 to the floating diffusion FD11 (broken arrow) as shown in FIG.

[0057] The source follower transistor SF11-Tr and the selection transistor SEL11-Tr are connected in series between the power supply potential VAAPIX and the vertical signal line LSGN11. A floating diffusion FD11 is connected to the gate of the source follower transistor SF11-Tr, and the selection transistor SEL11-Tr is controlled by a control signal ΦSEL applied to the gate via a control line. The selection transistor SEL11-Tr is selected and turned on during the selection period when the control signal ΦSEL is at level H. As a result, the source follower transistor SF11-Tr outputs the column output readout voltage signals (VRST1, VSIG1) converted into voltage signals by FD11 to the vertical signal line LSGN11.

[0058] In the pixel section 20, the readout pixels 200 are arranged in N rows and M columns, and therefore there are N control lines and M vertical signal lines. In FIG. 1, each control line is represented as one row scan control line.

[0059] The vertical scanning circuit 30 drives pixels in the shutter row and readout row through row scanning control lines under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs, in accordance with the address signal, a row selection signal of a read row for reading out a signal and a row address of a shutter row for resetting the charge accumulated in the photodiode PD11.

[0060] The readout circuit 40 may include a pixel signal processing unit 400 as a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel unit 20, and may be configured to enable column-parallel processing with the plurality of column signal processing circuits. In the readout circuit 40, the pixel signal processing unit 400 has a function of inverting either the first conversion gain signal (HCGRST, HCGSIG) or the second conversion gain signal (LCGSIG, LCGRST), which are formed as signals with the opposite signal direction, in other words, level transition direction, and are read out from the readout pixel 200 as the pixel signal PXLOUT, specifically the first conversion gain signal. Furthermore, the pixel signal processing unit 400 has an analog-digital (AD) conversion function that converts the first conversion gain signal and the second conversion gain signal from analog signals to digital signals after aligning the signal directions (level transition directions).

[0061] The horizontal scanning circuit 50 scans and transfers the signals processed by the plurality of pixel signal processing units 400 of the readout circuit 40 in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0062] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0063] When the dual conversion gain read mode MDCG is specified, the read section 70 performs first conversion gain reset read processing HCGRST, first conversion gain read processing HCGSIG, second conversion gain read processing LCGSIG, and second conversion gain reset read processing LCGRST.

[0064] In the first embodiment, after starting the exposure period PEXP, the readout section 70 performs readout processing in the dual conversion gain readout mode MDCG as the readout mode processing.

[0065] For example, as shown in FIG. 3, the readout unit 70 holds the reset transistor RST11-Tr and the transfer transistor TG11-Tr in a conductive state for a predetermined period of time to reset the photodiode PD11 and the floating diffusion FD11 to perform shutter processing, and then turns the transfer transistor TG11-Tr off to start the exposure period PEXP. After starting the exposure period PEXP, the readout unit 70 sequentially performs the first conversion gain reset readout process HCGRST, the first conversion gain readout process HCGSIG, the second conversion gain readout process LCGSIG, and the second conversion gain reset readout process LCGRST as processing of the dual conversion gain readout mode MDCG.

[0066] The configuration and function of each part of the solid-state imaging device 10 and the readout process of the HCG signal and the LCG signal have been outlined above. Next, we will explain systems to which this DCG (dual conversion gain) method can be applied, such as capacitance CFD related to the conversion gain of characterization parameters (linearization parameters, nonlinearization parameters, linearization parameters) related to the readout process compatible with the DCG method for small pixels.

[0067] In the DCG (dual conversion gain) method for small pixels of the first embodiment, no transistor elements other than the four transistor elements of the transfer transistor TG11-Tr, the reset transistor RST11-Tr, the source follower transistor SF11-Tr, and the selection transistor SEL11-Tr are added as components within the pixel. The readout unit 70 applies a DCG (dual conversion gain) method for small pixels, which controls the readout pixel 200 to perform a first conversion gain signal readout process in which pixel signals are read out with a first conversion gain (HCG) corresponding to a first capacitance C1, and a second conversion gain signal readout process in which pixel signals are read out with a second conversion gain (LCG) corresponding to a second capacitance (different from the first capacitance) C2.

[0068] In the readout unit 70, two readout signals, an HCG signal and an LCG signal, are read out in accordance with the DCG (dual conversion gain) method and combined into a high dynamic range (HDR) signal, and the HCG linearity of the first conversion gain (HCG) signal readout process and the LCG signal linearity of the second conversion gain (LCG) signal readout process are controlled to have different characteristics.

[0069] In the first embodiment, the readout section 70 controls so that the LCG signal linearity in the second conversion gain (LCG) signal readout process is lower than the HCG linearity in the first conversion gain (HCG) signal readout process.

[0070] In addition, in the readout section 70, as a readout process for the readout pixel 200, as shown in FIG. 4, first, in the first conversion gain signal readout mode, the first readout reset signal HCGRST is read out, and then the first readout luminance signal HCGSIG is read out. Subsequently, in the second conversion gain signal readout mode, the second readout luminance signal LCGSIG is read out, and then the second readout reset signal LCGRST is read out.

[0071] A pixel in a typical DCG CMOS image sensor is composed of six transistors to achieve high dynamic range (HDR). The typical DCG method is configured to switch between binning switches (BIN1 and BIN2). Two readout signals are read out and combined into an HDR signal. However, in the normal DCG method, pixel components are added, which increases the pixel size and the number of driver circuits.

[0072] In contrast, the first embodiment employs a DCG method for small pixels consisting of four-transistor pixels. Four-transistor pixels are in high demand as low-cost standard dynamic range (SDR) image sensors, but the first embodiment can realize a low-cost HDR image sensor.

[0073] FIG. 4 is a timing chart showing an example of a readout sequence of a readout pixel in the solid-state imaging device according to the first embodiment of the present invention. FIG. 5 is a diagram showing an operation sequence and potential transitions for explaining the operation in the readout process of the HCG signal and the LCG signal in the conversion gain readout mode of the solid-state imaging device according to the first embodiment. FIG. 6 is a flowchart illustrating how deep neural networks (DNNs) can be trained to improve accuracy for machine vision applications.

[0074] 7A to 7C are diagrams for explaining the linearity of an LCG signal during a conversion gain signal readout process in which a DCG method for small pixels is adopted, in relation to potential transition. FIG. 7(A) shows an ideal case where the linearization parameter Cpd is a constant, and FIG. 7(B) shows a real case where the linearization parameter Cpd is not a constant but a value that depends on the voltage. In these cases, the HCG signal level is given by HCG=q / CFD, and the LCG signal level is given by LCG=q / (CFD+CTG+CPD) or LCG=q / (CFD+CTG). Figure 7(C) shows the reconstructed readout characteristics after linearization. The ratio of the readout signals is given by HCG / LCG = (CFD + CTG + CPD) / CFD.

[0075] FIG. 8 is a diagram showing an example of multiple conversion gains applied to the readout process of the HCG signal and the LCG signal in the conversion gain readout mode of the solid-state imaging device according to the first embodiment.

[0076] (Linearization parameter CPD) Global CPD parameters (CPD) are common to all pixels within a chip. Pixel CPD parameters (each pixel has its own CPD). CPD has PD voltage dependency and varies from pixel to pixel.

[0077] Here, an outline of the conversion gain signal readout process employing the DCG method for small pixels will be described. In this process, complete transfer is not required when transferring LCG charge.

[0078] The photocharge accumulated in the photodiode PD is transferred to the floating diffusion FD11 as a detection node at timing t4 in the timing chart, the HCG signal level is read at timing t5, and the charge is converted into a voltage by a small capacitance CFD. Here, the transfer transistor TG11-Tr is turned on by the control signal ΦTG, and the LCG signal level is read at timing t6 using a large capacitance including CFD. The large capacitance may include the TG gate capacitance of the transfer transistor TG11-Tr and the junction capacitance of the photodiode PD.

[0079] Then, the LCG reset level is read at timing t10 ​​and then turned on. Furthermore, the reset transistor RST11-Tr (RST gate) and the transfer transistor TG11-Tr (TG gate) are turned off to remove the offset signal contained in the LCG signal.

[0080] As shown in FIG. 5(B), as the photocharge accumulated in the photodiode PD increases, the conversion gain in the LCG decreases, and therefore the LCG linearity of the DCG scheme according to the first embodiment decreases compared to that of a normal DCG.

[0081] Furthermore, the nonlinear response of the 4T DCG method according to the first embodiment reduces color reproducibility. For machine vision applications, deep neural networks (DNNs) can be trained to improve accuracy, as shown in Figure 6. The open source raw images are tone mapped (ST41, ST42) and then demosaiced (ST43). Representing 4T DCG footage, the DNN is trained or fine-tuned using the 4T DCG dataset (ST44). This processing flow is expected to enable the realization of a low-cost HDR machine vision system.

[0082] As described above, in the first embodiment, a new DCG method for 4T pixels is formed to achieve HDR with small pixels. The dynamic range of this 4T pixel DCG scheme is comparable to that of a normal DCG scheme that requires an additional transistor in the pixel.

[0083] 9A to 9C are diagrams showing an operation sequence and potential transitions for explaining the shutter process in the conversion gain readout mode of the solid-state imaging device according to the first embodiment and the operation in the readout process of the HCG signal and the LCG signal.

[0084] In the example of FIG. 9, full charge transfer is not required when transferring LCG charges.

[0085] In the HCG signal readout process, after CDS [=reset signal], clock feedthrough is cancelled and reset noise is also cancelled.

[0086] In the LCG signal readout process, after DDS [= reset signal], clock feedthrough is canceled, but reset noise is not canceled. However, these can be ignored and are unlikely to cause any problems in the system.

[0087] Next, two types of overflow charge integration, which is one of the characteristic configurations of the first embodiment, will be described.

[0088] 10A to 10C are diagrams showing an operation sequence and potential transitions for explaining the operation in the second overflow charge accumulation process employed in the solid-state imaging device according to the first embodiment. 11A and 11B are diagrams showing an operation sequence and potential transitions for explaining the operation in the second overflow charge accumulation process employed in the solid-state imaging device according to the first embodiment. This example illustrates the cases of low brightness and high brightness.

[0089] In the first example, as shown in FIG. 10(A), one feature is that the floating diffusion FD is not reset before reading out the HCG signal. In this first example, the overflow charge is accumulated in the floating diffusion FD.

[0090] In the second example, the full well capacitance (FWC) increases due to the overflow charge. Also in the second example, as shown in FIG. 11(B), full charge transfer is not required when transferring LCG charges.

[0091] As described above, according to the first embodiment, it is possible to suppress increases in power consumption and circuit area, and furthermore to achieve a high dynamic range, and ultimately to realize a standard dynamic range (SDR) SDRCMOS image sensor for small pixels consisting of four-transistor pixels at low cost.

[0092] (Second embodiment) 12A to 12C are circuit diagrams showing examples of the configuration of the main parts of a readout pixel and a pixel signal processing unit according to the second embodiment of the present invention.

[0093] The readout pixel 200A and the pixel signal processing unit 400A of the second embodiment differ from the readout pixel 200 and the pixel signal processing unit 400 of the first embodiment in the following respects.

[0094] In the readout pixel 200 and pixel signal processing unit 400 of the first embodiment, one current source IB is connected for the source follower transistor SF11-Tr, and current source switching according to pixel gain is not performed.

[0095] In contrast to this, the readout pixel 200A and the pixel signal processing unit 400A of the second embodiment are configured to be able to switch the current sources IB1 and IB2 for the source follower transistor SF11-Tr according to the pixel gain.

[0096] In such a configuration, the current source IB for SF is switched according to the pixel gain. The high accuracy of the cascode current source ISC current mirror in HCG mode improves linearity and column FPN. The output range is small, but the high gain amplifier used in HCG mode reduces the required range. The non-cascode current source ISC in LCG mode has a high output range, which improves the FWC (full well capacitance) and dynamic range. Although the current accuracy is low, the linearity required for bright signals is low, and the photon shot noise is large, so the required FPN is low.

[0097] Furthermore, according to the second embodiment, similarly to the first embodiment described above, it is possible to read out signals having different conversion gains and different signal directions, and it is also possible to suppress increases in power consumption and circuit area, and furthermore, it is possible to achieve a high dynamic range, and ultimately to achieve high image quality.

[0098] (Third embodiment) 13A to 13C are circuit diagrams showing examples of the configuration of the main parts of a readout pixel and a pixel signal processing unit according to the third embodiment of the present invention.

[0099] The readout pixel 200B and the pixel signal processing unit 400B of the third embodiment differ from the readout pixel 200A and the pixel signal processing unit 400A of the second embodiment in the following respects.

[0100] In the readout pixel 200B and pixel signal processing unit 400B of the third embodiment, a depletion type transistor is used for the source follower transistor SF11-Tr instead of an enhancement type transistor.

[0101] In this way, in the third embodiment, since a depletion transistor is used as the source follower transistor SF11-Tr, the following effects can be obtained. That is, according to the third embodiment, the LCG mode depletion SF transistor reduces Vgs (=Vth+Von), thereby increasing the output range, and improving the full well capacitance and dynamic range.

[0102] Furthermore, according to the third embodiment, similarly to the first embodiment described above, it is possible to read out signals with different conversion gains and different signal directions, and it is also possible to suppress increases in power consumption and circuit area, and furthermore, it is possible to achieve a high dynamic range, and ultimately to achieve high image quality.

[0103] (Fourth embodiment) FIG. 14 is a simplified cross-sectional view showing a main part of a readout pixel having a deep PD structure according to a fourth embodiment of the present invention.

[0104] The readout pixel 200C of the fourth embodiment differs from the readout pixel 200 of the first embodiment in the following respects.

[0105] That is, the readout pixel 400C of the fourth embodiment differs from the first to third embodiments in that the photodiode PD has a deep PD structure. Simply put, the deep PD structure is a structure in which the photoelectric conversion function part of the photodiode PD is formed in a region deeper than, for example, the channel formation region of the semiconductor so that, for example, the maximum accumulated signal amount of the photodiode PD is large and the dark current is small.

[0106] As shown in Figure 14(B), in the conventional method, it is not easy to increase the full well capacitance FWC by using deep PD, because the residual charge due to incomplete transfer cannot be read out. In the proposed scheme shown in Fig. 14(A), the use of deep PD can increase the full well capacitance FWC and dynamic range in the LCG. In HCG mode, the FD signal range required to read out the signal with a high-gain amplifier is narrow, so image lag (residual photocharge in the PD) is not an issue even with deep PDs. LCG mode uses PD+TG+FD as the detection node, so the incomplete charge transfer caused by deep PD is not an issue. The conventional and present HCGs are fully transferable, whereas the conventional and present LCGs require full transfer for the conventional LCGs, but do not require full transfer for the present LCGs.

[0107] (Fifth embodiment) 15(A) to 15(D) are simplified cross-sectional views showing the main part of a readout pixel having a large transfer gate (TG) structure according to a fifth embodiment of the present invention. FIG. 15(A) shows a comparative example, FIG. 15(B) shows a first example of the fifth embodiment, FIG. 15(C) shows a second example, and FIG. 15(D) shows a third example.

[0108] The readout pixel 200D of the fifth embodiment differs from the readout pixel 200 of the first embodiment in the following respects.

[0109] That is, the readout pixel 400D of the fifth embodiment differs from the first to fourth embodiments in that it has a large TG structure and achieves highly linear photoelectric conversion characteristics. The readout pixel 200D according to the fifth embodiment is formed as follows.

[0110] In the readout pixel 200D according to the fifth embodiment, a large transfer gate TG is used to improve linearity in the LCG mode. To prevent driftback when the conventional TG is off, the TG size is optimized. Large TG (option Figure 15(B)) In HCG, the maximum charge transferred to the floating diffusion (FD) is small, so the driftback is suppressed by the electric field generated by the optimally high TG voltage. In LCG mode, the capacitance of the detection node is dominated by the CTG capacitor, which has a smaller voltage dependence of the number of photocharges than the CPD, improving the linearity of the photoresponse. Large TG (optional, Figure 15(C)) The PD can be covered with a TG.

[0111] Thanks to BSI (Back Side Illumination) technology, the TG size does not affect the PD fill factor. Also, the vertical TG allows for a larger TG capacity to be used.

[0112] (Sixth embodiment) 16(A) to 16(C) are simplified cross-sectional views showing the main part of a readout pixel having a large transfer gate (TG) structure and a divided structure of the transfer gate (TG) according to a sixth embodiment of the present invention. FIG. 16(A) shows a comparative example, FIG. 16(B) shows a first example (large TG1) of the sixth embodiment, and FIG. 16(C) shows a second example (divided TG).

[0113] The readout pixel 200E of the sixth embodiment differs from the readout pixel 200 of the first embodiment in the following respects.

[0114] That is, the readout pixel 200E of the sixth embodiment differs from the first to fourth embodiments in that it employs a large photodiode PD, has a large TG structure, and has a separate structure for the large PD and TG. The readout pixel 200E according to the sixth embodiment is formed as follows.

[0115] In the readout pixel 200E according to the sixth embodiment, the TG can be separated in a large TG case, which has the advantage of maintaining a large TG capacitance, averaging out variations in PD capacitance, and enabling the implementation of a PDAF function.

[0116] (Seventh embodiment) FIG. 17 is a circuit diagram showing an example of the configuration of a readout pixel that employs the DCG method according to the seventh embodiment of the present invention and that can be applied to a pixel sharing structure. FIG. 18 is a timing chart showing an example of an operation sequence of a readout pixel that employs the DCG method according to the seventh embodiment of the present invention and that is applicable to a pixel sharing structure.

[0117] In the operation example of FIG. 18, the DCG scheme applied to this embodiment is applicable to a four-pixel shared DCG architecture. In the example of FIG. 17, the RST, DF, and SEL transistors are shared by four pixels. The number of transistors per pixel is given by 1.75. Shared pixel DCG helps to achieve smaller pixelation in HDR CMOS image sensors.

[0118] FIG. 18 shows a timing diagram of a DCG scheme with a 4-pixel shared architecture. FIG. 18 shows the readout timing of the photodiodes PD1 and PD2, but omits the readout timing of the photodiodes PD3 and PD4. By omitting ΦRST at timing t10, it is possible to improve the read speed.

[0119] (Eighth embodiment) FIG. 19 is a circuit diagram showing an example of the configuration of a readout pixel that employs the DCG method according to the eighth embodiment of the present invention and that can be applied to an asymmetric four-pixel sharing structure. FIG. 20 is a timing chart showing an example of an operation sequence of a readout pixel that employs the DCG method according to the eighth embodiment of the present invention and that is applicable to an asymmetric pixel sharing structure.

[0120] The readout pixel 200G of the eighth embodiment differs from the readout pixel 200F of the seventh embodiment in the following respects.

[0121] In the 4-shared readout pixel 200G according to the eighth embodiment, an anti-blooming (AB) gate is connected between the storage node of the photodiode PD and a predetermined fixed potential VAAPIX.

[0122] In the readout pixel 200G, the photodiodes PD1 to PD4 have different PD full well capacitances FWC. The readout sequence by the readout pixel 200G of the eighth embodiment will be described below.

[0123] <1> After reading out the photodiode PD1, the anti-blooming gate AB1 is turned on to keep the photodiode PD1 empty. The capacitance of the transfer transistor TG1 can be used as the LCG capacitor when subsequently reading out the photodiodes PD2 to PD4.

[0124] <2> After reading out the photodiode PD2, the anti-blooming gate AB2 is turned on to keep the photodiode PD2 empty. The capacitance of the subsequent transfer transistors TG1 and TG2 can be used as an LCG capacitor when reading out the photodiodes PD3 to PD4 (similarly for PD3 and PD4).

[0125] In this way, according to the eighth embodiment, for example, when the PD size is asymmetric, it is possible to reuse the gate capacitance of the TG adjacent to the PD that has already been read out as the LCG capacitance for a large PD.

[0126] (Ninth embodiment) 21(A) and 21(B) are diagrams for explaining a ninth embodiment of the present invention, and are diagrams for explaining a method of adjusting the conversion gain (CG) in the LCG mode. FIG. 21(A) shows the ON voltage of a high TG, and FIG. 21(B) shows the ON voltage of a low TG. According to the ninth embodiment, the conversion gain in the LCG mode can be adjusted by the ON voltage of the TG.

[0127] (Tenth embodiment) FIG. 22 is a diagram illustrating one readout process using high dynamic range imaging in a readout pixel that employs the DCG method according to the tenth embodiment of the present invention.

[0128] High dynamic range imaging is achieved with a single "signal & reset" readout. In this example, although a pixel is composed of four transistors (TG, RST, SEL, SF), the readout timing sequence is the same as that of a normal 3T CMOS image sensor. After the shutter is reset, the potential gradient formed by the PD, TG(ON), and floating diffusion FD causes the photocharge generated in the PD to flow into the FD node, resulting in high conversion gain under low illumination conditions. As the generated photocharges increase, charges are accumulated in the coupling capacitance, resulting in a decrease in conversion gain under high illumination.

[0129] (Eleventh embodiment) FIG. 23 is a diagram schematically showing a solid-state imaging device employing the DCG method according to the eleventh embodiment of the present invention, which functions as an object detection device.

[0130] Object detection is performed in DCG mode. When a particular object is detected by the object detection device 250, auto exposure is performed in the area of ​​the detected object and the image sensor is switched to normal SDR mode for observation. In this case, it is realized as an SDR image sensor.

[0131] The solid-state imaging devices 10, 10A to 10G described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, medical endoscope cameras, and even AI circuits and deep neural networks (DNNs).

[0132] FIG. 24 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

[0133] As shown in FIG. 24, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A to 10G according to the present embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (forming an image of a subject). The electronic device 300 includes a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310 .

[0134] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310 . The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer, or can be recorded directly on a recording medium such as a memory card, and various other forms are possible.

[0135] As described above, by incorporating the above-described solid-state imaging devices 10, 10A to 10G as the CMOS image sensor 310, it is possible to provide a high-performance, compact, and low-cost camera system. This technology can be used in applications where camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height, such as surveillance cameras and medical endoscope cameras, as well as electronic devices such as AI circuits and deep neural networks (DNN). [Explanation of symbols]

[0136] 10, 10A to 100G... solid-state imaging device, 20... pixel unit, 200, 200A to 200G... readout pixel, PD11... photodiode, FD11... floating diffusion, TG11-Tr... transfer transistor, RST11-Tr... reset transistor, SF11-Tr... source follower transistor, 30... vertical scanning circuit, 40... readout circuit, 400, 400A to 400G... pixel signal processing unit, 50... horizontal scanning circuit, 60... timing control circuit, 70... readout unit, 300... electronic device, 310... CMOS image sensor, 320... optical system, 330... signal processing circuit (PRC).

Claims

1. a pixel section in which readout pixels capable of reading out the first conversion gain signal and the second conversion gain signal as pixel signals are arranged; a readout unit that reads out the pixel signals from the readout pixels of the pixel unit, The readout pixel is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period; a floating diffusion as a detection node to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a source follower element that amplifies and outputs the voltage signals converted with the first conversion gain and the second conversion gain; a selection element that enables output of a voltage signal to a signal line by the floating diffusion during a selection period; No transistor elements other than the four transistor elements of the transfer element, the floating diffusion, the reset element, and the selection element are added as components within the pixel; In the readout unit, A dual conversion gain system for small pixels is applied, which controls the readout pixel to perform a first conversion gain signal readout process for reading out a pixel signal with a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process for reading out a pixel signal with a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, The readout unit In the dual conversion gain method, The two readout signals, the HCG signal and the LCG signal, are read out and combined into a high dynamic range (HDR) signal; The HCG response characteristic of the first conversion gain signal readout process and the LCG signal response characteristic of the second conversion gain signal readout process are controlled to be different characteristics. Solid-state imaging device.

2. The readout unit The LCG response characteristic of the second conversion gain (LCG) signal readout process is controlled to have lower sensitivity than the HCG response characteristic of the first conversion gain (HCG) signal readout process.

2. The solid-state imaging device according to claim 1.

3. The readout unit As a readout process for the readout pixels, First, in a first conversion gain signal readout mode, a first readout reset signal is readout, and then a first readout luminance signal is readout; Subsequently, in the second conversion gain signal readout mode, the second readout luminance signal is readout, and then the second readout reset signal is readout.

3. The solid-state imaging device according to claim 2.

4. The readout unit The new DCG method for 4T pixels, which allows HDR to be achieved with small pixels, employs an overflow charge accumulation function. The readout unit In the conversion gain signal readout process in which the DCG method for small pixels is adopted, the control is performed assuming that complete transfer is not necessary when transferring the charge of the LCG signal.

4. The solid-state imaging device according to claim 3.

5. The photocharge accumulated in the photoelectric conversion element is transferred to a floating diffusion as a detection node at a predetermined timing, the HCG signal level is read at another timing, and the charge is converted into a voltage by a small capacitance CFD. Here, the control signal turns on the transfer element, and the LCG signal level is read at another time using a large capacitance including the CFD, Then, the LCG reset level is read at another time and then turned on, In addition, the reset element and transfer element are turned off to remove the offset signal contained in the LCG signal.

5. The solid-state imaging device according to claim 4.

6. The readout unit Forming a new DCG method for 4T pixels to achieve HDR with small pixels, The dynamic range of this 4T pixel DCG method is equivalent to the dynamic range of a normal DCG method that requires an additional transistor in the pixel. The machine vision system is based on an open-source raw image dataset and can be realized by training a DNN on a 4T DCG image dataset.

6. The solid-state imaging device according to claim 5.

7. The readout unit The new DCG method for 4T pixels to achieve HDR with small pixels is When transferring LCG charges, control is performed assuming that complete transfer is not required. In the HCG signal readout process, after the CDS [=reset signal], the clock feedthrough is cancelled and the reset noise is also cancelled.

7. The solid-state imaging device according to claim 6.

8. The readout unit Before reading out the HCG signal, the floating diffusion FD is not reset, In the floating diffusion FD, the overflow charge is accumulated.

8. The solid-state imaging device according to claim 7.

9. The full well capacitance (FWC) of the floating diffusion FD increases depending on the maximum number of charges that can be detected in the floating diffusion FD during actual operation.

8. The solid-state imaging device according to claim 7.

10. The readout unit When transferring LCG charges, control is performed assuming that complete transfer is not necessary.

10. The solid-state imaging device according to claim 9.

11. The readout pixel is A variable current source that switches the current source for the source follower element according to pixel gain.

2. The solid-state imaging device according to claim 1.

12. The source follower element is formed by a depletion transistor.

4. The solid-state imaging device according to claim 3.

13. The photoelectric conversion element is It has a deep PD structure, The deep PD structure can increase the PD capacitance and dynamic range.

4. The solid-state imaging device according to claim 3.

14. The photoelectric conversion element is A large PD structure is adopted, and the size of the transfer element TG is optimized to improve linearity in LCG mode and prevent driftback when the transfer element TG is off.

4. The solid-state imaging device according to claim 3.

15. The photoelectric conversion element is In order to increase the capacity of the transfer element TG, a large-sized structure of the TG is adopted.

4. The solid-state imaging device according to claim 3.

16. The photoelectric conversion element is In order to increase the capacitance of the transfer element TG, a buried structure of the TG is adopted.

4. The solid-state imaging device according to claim 3.

17. The photoelectric conversion element is The transfer element is configured so that CG control is possible with the TG voltage.

18. The photoelectric conversion element is The asymmetric PD is formed with a floating diffusion FD shared structure.

4. The solid-state imaging device according to claim 3.

19. The readout unit The new DCG method for 4T pixels to achieve HDR with small pixels is applicable to a shared pixel architecture, where multiple elements of the readout pixel are shared by multiple pixels.

4. The solid-state imaging device according to claim 3.

20. In the readout pixel, An anti-blooming gate is connected between the storage node of the photoelectric conversion element and a fixed potential.

20. The solid-state imaging device according to claim 19.

21. The readout unit The linearity of the LCG signal during the conversion gain signal readout process in which the DCG method for small pixels is adopted is controlled in association with the linearization parameter Cpd and potential transition. The signal level in the control is a value that depends on the voltage, In a given case, the HCG signal level is given by HCG = q / CFD, the LCG signal level is given by LCG = q / (CFD + CTG + CPD), or LCG = q / (CFD + CTG), and the ratio of read signals related to the reconstructed read characteristic after linearization is given by HCG / LCG = (CFD + CTG + CPD) / CFD.

4. The solid-state imaging device according to claim 3.

22. a pixel section in which readout pixels capable of reading out the first conversion gain signal and the second conversion gain signal as pixel signals are arranged; a readout unit that reads out the pixel signals from the readout pixels of the pixel unit, The readout pixel is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period; a floating diffusion as a detection node to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a source follower element that amplifies and outputs the voltage signals converted with the first conversion gain and the second conversion gain; a selection element that enables output of a voltage signal to a signal line by the floating diffusion during a selection period; A method for driving a solid-state imaging device, comprising: No transistor elements other than the four transistor elements of the transfer element, the floating diffusion, the reset element, and the selection element are added as components within the pixel; In the readout unit, A dual conversion gain system for small pixels is applied, which controls the readout pixel to perform a first conversion gain signal readout process for reading out a pixel signal at a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process for reading out a pixel signal at a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, The readout unit In the dual conversion gain method, The two readout signals, the HCG signal and the LCG signal, are read out and combined into a high dynamic range (HDR) signal; The HCG signal response characteristic of the first conversion gain signal readout process and the LCG signal response characteristic of the second conversion gain signal readout process are controlled to be different characteristics. A method for driving a solid-state imaging device.

23. a solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device, the solid-state imaging device, a pixel section in which readout pixels capable of reading out the first conversion gain signal and the second conversion gain signal as pixel signals are arranged; a readout unit that reads out the pixel signals from the readout pixels of the pixel unit, The readout pixel is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charges accumulated in the photoelectric conversion element during a transfer period after the accumulation period; a floating diffusion as a detection node to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a source follower element that amplifies and outputs the voltage signals converted with the first conversion gain and the second conversion gain; a selection element that enables output of a voltage signal to a signal line by the floating diffusion during a selection period; No transistor elements other than the four transistor elements of the transfer element, the floating diffusion, the reset element, and the selection element are added as components within the pixel; In the readout unit, A dual conversion gain system for small pixels is applied, which controls the readout pixel to perform a first conversion gain signal readout process for reading out a pixel signal with a first conversion gain (HCG) corresponding to a first capacitance, and a second conversion gain signal readout process for reading out a pixel signal with a second conversion gain (LCG) corresponding to a second capacitance different from the first capacitance, The readout unit In the dual conversion gain method, The two readout signals, the HCG signal and the LCG signal, are read out and combined into a high dynamic range (HDR) signal; The HCG signal response characteristic of the first conversion gain signal readout process and the LCG signal response characteristic of the second conversion gain signal readout process are controlled to be different characteristics. electronic equipment.

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