Semiconductor Devices

Abstract

A semiconductor device capable of suppressing a decrease in breakdown voltage while shortening a termination region is provided. [Solution] A semiconductor device according to one embodiment includes a semiconductor layer having a cell region and a termination region surrounding the cell region, a first insulating film provided on the semiconductor layer, and a semi-insulating film provided on the first insulating film. The semiconductor layer also includes a first semiconductor portion of a first conductivity type provided in the cell region and the termination region, and a second semiconductor portion of a second conductivity type provided on the first semiconductor portion in the termination region, the second semiconductor portion having a plurality of concentration peak regions with the highest second conductivity type impurity concentration within the second semiconductor portion. Furthermore, an end of the first insulating film on the termination region side is located somewhere between the plurality of concentration peak regions.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, in semiconductor devices used in power control, a termination structure with a semi-insulating film has been proposed to shorten the termination region, but depending on the position of this semi-insulating film, it may not be possible to ensure the required breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6519455 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device that can suppress a decrease in breakdown voltage while shortening the termination region. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a semiconductor layer having a cell region and a termination region surrounding the cell region, a first insulating film provided on the semiconductor layer, and a semi-insulating film provided on the first insulating film. The semiconductor layer also includes a first semiconductor portion of a first conductivity type provided in the cell region and the termination region, and a second semiconductor portion of a second conductivity type provided on the first semiconductor portion in the termination region, the second semiconductor portion having a plurality of concentration peak regions with the highest second conductivity type impurity concentration within the second semiconductor portion. Furthermore, an end of the first insulating film on the termination region side is located somewhere between the plurality of concentration peak regions. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a plan view schematically showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. [Figure 3] FIG. 2 is a cross-sectional view showing the structure of a first simulation model. [Figure 4] FIG. 4 is a cross-sectional view showing the structure of a second simulation model. [Figure 5] FIG. 10 is a cross-sectional view showing the structure of a third simulation model. [Figure 6] FIG. 10 is a cross-sectional view showing the structure of a fourth simulation model. [Figure 7] FIG. 10 is a cross-sectional view showing the structure of a fifth simulation model. [Figure 8] 10 is a graph showing the results of a TCAD simulation of breakdown voltage characteristics using each simulation model. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0008] (First embodiment) Fig. 1 is a plan view schematically showing a semiconductor device according to a first embodiment, and Fig. 2 is a cross-sectional view taken along line AA shown in Fig. 1.

[0009] In the following explanation, the arrangement and configuration of each part of the semiconductor device may be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n +The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be determined by, for example, SIMS.

[0012] 1 can be, for example, an IGBT (Insulated Gate Bipolar Transistor), an IEGT (Injection Enhanced Gate Transistor), or a diode. The semiconductor device 1 according to this embodiment includes a semiconductor layer 10, a first electrode 21, a second electrode 22, and a third electrode 23. If the semiconductor device 1 is a diode, the third electrode 23 is not necessary.

[0013] The semiconductor layer 10 is made of, for example, a silicon substrate. The semiconductor layer 10 has, for example, a back surface on which a first electrode 21 is provided and a front surface opposite thereto. A second electrode 22 and a third electrode 23 are provided on the front surface side of the semiconductor layer 10. The semiconductor layer 10 has a cell region R1 and a termination region R2.

[0014] The cell region R1 switches between an on state and an off state depending on the voltage applied to the third electrode 23. In the on state, a current path is created through which a current flows from the first electrode 21 to the second electrode 22. In the off state, the current path is not created, and therefore no current flows from the first electrode 21 to the second electrode 22.

[0015] The termination region R2 is provided outside the cell region R1. In the termination region R2, the above-mentioned current path is not generated regardless of whether a voltage is applied to the third electrode 23, and therefore, no current flows from the first electrode 21 to the second electrode 22.

[0016] The semiconductor layer 10 has a first semiconductor portion 11, a second semiconductor portion 12, a third semiconductor portion 13, a fourth semiconductor portion 14, a fifth semiconductor portion 15, and a sixth semiconductor portion 16. The conductivity type of the first semiconductor portion 11 and the sixth semiconductor portion 16 is n-type (first conductivity type). On the other hand, the conductivity type of the second semiconductor portion 12, the third semiconductor portion 13, the fourth semiconductor portion 14, and the fifth semiconductor portion 15 is p-type (second conductivity type).

[0017] The first semiconductor portion 11 is n - The first semiconductor portion 11 is provided in each of the cell region R1 and the termination region R2.

[0018] The second semiconductor portion 12 is a p-type diffusion portion. The second semiconductor portion 12 is provided on the first semiconductor portion 11 in the termination region R2. The second semiconductor portion 12 has a plurality of concentration peak regions 121. Each concentration peak region 121 is a region into which p-type impurities are injected, and is a region in the second semiconductor portion 12 where the concentration of the p-type impurities is the highest.

[0019] 1, the planar shape of each concentration peak region 121 is a frame shape that continuously surrounds the cell region R1. In this embodiment, the width (length in the X direction) of each concentration peak region 121 is the same. On the other hand, the distance between the concentration peak regions 121, in other words, the interval between the concentration peak regions 121, becomes shorter as the concentration peak regions 121 move away from the cell region R1.

[0020] The third semiconductor portion 13 is a p + The third semiconductor portion 13 is in contact with the innermost of the plurality of concentration peak regions 121, that is, the concentration peak region 121 closest to the cell region R1.

[0021] The fourth semiconductor portion 14 is provided between the first semiconductor portion 11 and the first electrode 21 in the Z direction, and is in contact with the first electrode 21. The fourth semiconductor portion 14 is p + The termination region R2 is a p - It is a semiconductor part.

[0022] The fifth semiconductor portion 15 is provided on the first semiconductor portion 11 in the cell region R1. + This is the mold base part.

[0023] The sixth semiconductor portion 16 is provided on the fifth semiconductor portion 15. The sixth semiconductor portion 16 has an n + The sixth semiconductor portion 16 is electrically connected to the second electrode 22 through a contact via 19.

[0024] When the semiconductor device 1 is an IGBT or IEGT, a plurality of trench gates 17 are arranged at a predetermined pitch (for example, 2 μm) as shown in Fig. 2. An n-type semiconductor layer 20 is formed on the outermost surface of the termination region R2. When the semiconductor device 1 is a diode, the trench gates 17 and the semiconductor layer 20 are not provided.

[0025] For example, each trench gate 17 is formed by filling polysilicon into a trench that penetrates the fifth semiconductor portion 15 and the sixth semiconductor portion 16 and terminates at the first semiconductor portion 11. Each trench gate 17 is electrically insulated from the first semiconductor portion 11, the fifth semiconductor portion 15, and the sixth semiconductor portion 16 by a gate insulating film 18.

[0026] The first electrode 21 is provided over the entire rear surface of the semiconductor layer 10, including the cell region R1 and the termination region R2. When the semiconductor device 1 is an IGBT or an IEGT, the first electrode 21 is a collector electrode. When the semiconductor device 1 is a diode, the first electrode 21 is an anode electrode.

[0027] The second electrode 22 is provided on the surface of the semiconductor layer 10 via the first insulating film 31. When the semiconductor device 1 is an IGBT or an IEGT, the second electrode 22 is an emitter electrode. When the semiconductor device 1 is a diode, the second electrode 22 is a cathode electrode.

[0028] The third electrode 23 is provided on the surface of the semiconductor layer 10 via the first insulating film 31. When the semiconductor device 1 is an IGBT or an IEGT, the third electrode 23 is a gate electrode.

[0029] The third electrode 23 faces the conductor 24 with the first insulating film 31 interposed therebetween. The third electrode 23 is electrically connected to the conductor 24 through a contact via 25. The conductor 24 is electrically connected to each trench gate 17. Therefore, the potential of each trench gate 17 is controlled by the voltage applied to the third electrode 23. When this applied voltage exceeds the threshold voltage, a channel is formed in the fifth semiconductor portion 15. As a result, a current flows between the first electrode 21 and the second electrode 22, and the semiconductor device 1 is turned on.

[0030] 2, in the semiconductor device 1, the second insulating film 32 is provided contiguously with the first insulating film 31 in the termination region R2. The thickness of the second insulating film 32 is thinner than the thickness of the first insulating film 31. The first insulating film 31 and the second insulating film 32 are, for example, silicon oxide films (SiO2). For example, the second insulating film 32 can be formed by dry etching or wet etching an insulating film having the same thickness as the first insulating film 31.

[0031] In the semiconductor device 1, a semi-insulating film 40 is provided on each of the first insulating film 31, the second insulating film 32, the third electrode 23, and the second electrode 22. The planar shape of the semi-insulating film 40 is a ring shape that continuously surrounds the cell region R1. The resistivity of the semi-insulating film 40 is higher than the resistivity of the semiconductor layer 10 and lower than the resistivities of the first insulating film 31 and the second insulating film 32. The semi-insulating film 40 contains, for example, nitrogen and silicon. The nitrogen composition ratio in the semi-insulating film 40 is preferably 40% or more and 55% or less.

[0032] Furthermore, in the semiconductor device 1, a protective film 50 is provided on the semi-insulating film 40. The protective film 50 is formed using a resin such as polyimide.

[0033] In the semiconductor device 1 configured as described above, the semi-insulating film 40 is in contact with the second electrode 22 and the third electrode 23. The resistivity of the semi-insulating film 40 is not so low as to short-circuit the second electrode 22 and the third electrode 23 during operation of the semiconductor device 1. In other words, during operation of the semiconductor device 1, no current of a magnitude that would affect the operation of the semiconductor device 1 flows from the third electrode 23 to the second electrode 22, which has a lower potential than the third electrode 23, through the semi-insulating film 40.

[0034] On the other hand, when a high electric field is generated in termination region R2 from the outside of protective film 50, electrons flow to third electrode 23 through semi-insulating film 40. Therefore, electrons are less likely to accumulate in semi-insulating film 40.

[0035] Furthermore, in the semiconductor device 1, if the thickness of the second insulating film 32 is large, the probability that electrons will tunnel through the second insulating film 32 decreases, and therefore holes are more likely to be trapped in the semi-insulating film 40 by electrons flowing near the interface between the semiconductor layer 10 and the second insulating film 32. If the number of holes trapped in the semi-insulating film 40 increases, the electric field distribution in the termination region R2 may change, causing fluctuations in the breakdown voltage.

[0036] Therefore, in this embodiment, the thickness of the second insulating film 32 provided between the second semiconductor portion 12 and the semi-insulating film 40 is thinner than the thickness of the first insulating film 31. As a result, a certain amount of electrons are tunneled from the semiconductor layer 10, making it difficult for either electrons or holes to be excessively trapped in the semi-insulating film 40.

[0037] However, the breakdown voltage of the semiconductor device 1 can change depending on the position of the end 33 of the first insulating film 31 that contacts the second insulating film 32, in other words, the position of the step portion of the semi-insulating film 40 that is formed as the thickness changes from the first insulating film 31 to the second insulating film 32. Here, with reference to Figures 3 to 8, the results of a TCAD (Technology Computer Aided Design) simulation of the breakdown voltage characteristics when the position of the end 33 of the first insulating film 31 is changed will be described.

[0038] 3 is a cross-sectional view showing the structure of a first simulation model. The first simulation model M1 shown in FIG. 3 corresponds to the semiconductor device 1 according to this embodiment. In the first simulation model M1, a diffusion region 122 is formed around each concentration peak region 121. The diffusion region 122 is a region where p-type impurities implanted into the concentration peak region 121 are thermally diffused. The p-type impurity concentration in the diffusion region 122 is lower than the p-type impurity concentration in the concentration peak region 121.

[0039] The diffusion region 122 may be formed in the actual semiconductor device 1. In Fig. 3, the end 33 of the first insulating film 31, i.e., the step portion where the height position of the semi-insulating film 40 changes, is located between a first concentration peak region 121a, which is closest to the cell region R1 among the multiple concentration peak regions 121 and contacts the third semiconductor portion 13, and a second concentration peak region 121b located outside the first concentration peak region 121a.

[0040] 4 is a cross-sectional view showing the structure of the second simulation model. In the second simulation model M2 shown in FIG. 4, the position of the end 33 of the first insulating film 31 is shifted in the direction from the cell region R1 toward the termination region R2 (to the right) compared to the first simulation model M1. As a result, the position of the end 33 of the first insulating film 31 moves onto the left half of the second concentration peak region 121b.

[0041] 5 is a cross-sectional view showing the structure of the third simulation model. In the third simulation model M3 shown in FIG. 5, the position of the end 33 of the first insulating film 31 is further shifted to the right compared to the second simulation model M2. As a result, the position of the end 33 of the first insulating film 31 moves above the center of the second concentration peak region 121b.

[0042] 6 is a cross-sectional view showing the structure of a fourth simulation model. In the fourth simulation model M4 shown in FIG. 6, the position of the end 33 of the first insulating film 31 is further shifted to the right compared to the third simulation model M3. As a result, the end 33 of the first insulating film 31 moves above the right half of the second concentration peak region 121b.

[0043] 7 is a cross-sectional view showing the structure of a fifth simulation model. In the fifth simulation model M5 shown in FIG. 7, the position of the end 33 of the first insulating film 31 is shifted further to the right compared to the fourth simulation model M4. As a result, the end 33 of the first insulating film 31 moves between the second concentration peak region 121b and the third concentration peak region 121c located outside the second concentration peak region 121b.

[0044] Figure 8 is a graph showing the results of a TCAD simulation of breakdown voltage characteristics using each simulation model. In Figure 8, the horizontal axis represents the collector-emitter voltage VCE, and the vertical axis represents the collector-emitter current ICE. In this simulation, the gate-emitter voltage is set to an off state lower than the threshold voltage.

[0045] According to the simulation results shown in FIG. 8, the breakdown voltage V1 of the fourth simulation model M4, the breakdown voltage V2 (>V1) of the third simulation model M3, and the breakdown voltage V3 (>V2) of the second simulation model M2 are lower than the breakdown voltage V4 of the first simulation model M1 and the fifth simulation model M5.

[0046] In termination region R2, the electric field strength is high between concentration peak region 121, which has a high p-type impurity concentration, and end portion 33 of first insulating film 31 (step portion of semi-insulating film 40). Therefore, in second simulation model M2, third simulation model M3, and fourth simulation model M4, end portion 33 of first insulating film 31 and concentration peak region 121 overlap, so the electric field strengths reinforce each other. As a result, the breakdown voltage decreases.

[0047] In contrast, in the first simulation model M1 and the fifth simulation model M5, the end 33 of the first insulating film 31 is located between the concentration peak regions 121, and the two do not overlap. That is, the step portion of the semi-insulating film 40 is located outside the concentration peak region 121. This makes it possible to suppress a decrease in breakdown voltage.

[0048] As described above, according to this embodiment, the position of the end 33 of the first insulating film 31, in other words, the step portion of the semi-insulating film 40, is optimized, making it possible to suppress a decrease in breakdown voltage while shortening the termination region R2.

[0049] In this embodiment, the end 33 of the first insulating film 31 has a tapered shape. That is, the end 33 is inclined so that the thickness gradually decreases toward the surface of the semiconductor layer 10. This reduces the electric field strength at the end, thereby further suppressing a decrease in breakdown voltage.

[0050] (Second embodiment) Fig. 9 is a cross-sectional view of the semiconductor device according to the second embodiment. In Fig. 9, the same components as those in the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and redundant explanations will be omitted.

[0051] The semiconductor device 2 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that it does not include the second insulating film 32. In the semiconductor device 2 according to this embodiment, the semi-insulating film 40 contacts the surface of the semiconductor layer 10 at a position opposite to the second semiconductor portion 12.

[0052] On the other hand, in the semiconductor device 2 according to this embodiment, as in the first embodiment, the end 33 of the first insulating film 31 is located between the concentration peak region 121 that contacts the third semiconductor portion 13 and another concentration peak region 121 that is adjacent to this concentration peak region 121 in the X direction. Therefore, the step portion of the semi-insulating film 40 is also located outside the concentration peak region 121. This makes it possible to suppress a decrease in the breakdown voltage.

[0053] Therefore, according to this embodiment, even if the second insulating film 32 is not formed, the position of the end 33 of the first insulating film 31, in other words, the step portion of the semi-insulating film 40, is optimized. Therefore, also in this embodiment, it is possible to suppress a decrease in breakdown voltage while shortening the termination region R2.

[0054] Also in this embodiment, the end 33 of the first insulating film 31 has a tapered shape, so that the electric field strength at the end is reduced, and as a result, the decrease in the breakdown voltage can be further suppressed.

[0055] In the termination region R2 of the semiconductor device 2 according to this embodiment, the diffusion region 122 described in the first embodiment may be provided around the concentration peak region 121. In this case, the end 33 of the first insulating film 31 is located on the diffusion region 122.

[0056] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0057] 1: Semiconductor device 10: Semiconductor layer 11: First semiconductor section 12: Second semiconductor section 13: Third Semiconductor Department 14: 4th Semiconductor Department 15: 5th Semiconductor Department 21: 1st electrode 22:Second electrode 23: Third electrode 31: First insulating film 32: Second insulating film 40: Semi-insulating film 50:Protective film

Claims

1. a semiconductor layer having a cell region and a termination region surrounding the cell region; a first insulating film provided on the semiconductor layer; a semi-insulating film provided on the first insulating film, The semiconductor layer is a first semiconductor portion of a first conductivity type provided in the cell region and the termination region; a second semiconductor portion of a second conductivity type provided on the first semiconductor portion in the termination region, the second semiconductor portion having a plurality of concentration peak regions in which the impurity concentration of the second conductivity type is the highest within the second semiconductor portion; an end portion of the first insulating film on the termination region side is located anywhere among the plurality of concentration peak regions.

2. a second insulating film provided between the semi-insulating film and the second semiconductor portion in the termination region; 2. The semiconductor device according to claim 1, wherein the thickness of said second insulating film is thinner than the thickness of said first insulating film.

3. The semiconductor device according to claim 1 , wherein the semi-insulating film is in contact with the semiconductor layer at a position facing the second semiconductor portion in the termination region.

4. the second semiconductor portion further includes a diffusion region of the second conductivity type impurity provided around the concentration peak region, The semiconductor device according to claim 1 , wherein the end is located on the diffusion region.

5. 4. The semiconductor device according to claim 1, wherein the end portion is located between a first concentration peak region that is closest to the cell region among the plurality of concentration peak regions and a second concentration peak region that is located outside the first concentration peak region.

6. the semi-insulating film contains silicon and nitrogen; 4. The semiconductor device according to claim 1, wherein a composition ratio of nitrogen in said semi-insulating film is 40% or more and 55% or less.

7. the semiconductor layer further includes a third semiconductor portion of a second conductivity type that is in contact with the first concentration peak region in the termination region, The semiconductor device according to claim 5 , wherein the impurity concentration in the third semiconductor portion is higher than the impurity concentration in the first concentration peak region.

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