Power detection circuit, radio frequency integrated circuit, and wireless communication device

Abstract

The objective is to provide a power detection circuit, a radio frequency integrated circuit, and a wireless communication device that can simultaneously achieve early detection of abnormalities in the output power of a power amplifier and accurate and precise measurement of that output power. [Solution] The power detection circuit 70 includes a power detector 70a that detects the output power of a power amplifier and outputs the detection result in two systems: a voltage output VO and a current output IO, and a voltage comparison circuit 70b that compares the voltage output VO of the power detector 70a with a predetermined reference voltage Vr and outputs a power detection signal DT which is at the "H" level if the voltage output VO is higher than the reference voltage Vr, and at the "L" level if the voltage output VO is lower than the reference voltage Vr.

Description

Technical Field

[0001] The present invention relates to a power detection circuit, a radio frequency integrated circuit, and a wireless communication device.

Background Art

[0002] Some wireless communication devices include a power detector (PD) in the path from a power amplifier (PA) to an antenna. In such wireless communication devices, the power of the radio signal transmitted from the antenna is stabilized using the detection result of the power detector. The following Patent Documents 1 to 3 disclose such wireless communication devices.

[0003] For example, the following Patent Document 1 discloses a wireless communication device that stabilizes the power of a radio signal transmitted from an antenna by adjusting the amplification gain of a power amplifier based on the comparison result between the detection result of a power detector and a predetermined reference value. Further, the following Patent Document 2 discloses a wireless communication device that stabilizes the power of a radio signal transmitted from an antenna by performing digital pre-distortion (DPD) processing in the baseband signal processing process based on the detection result of a power detector to compensate for the amplification distortion resulting from the characteristics of the power amplifier.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, in wireless communication equipment, there are cases where it is desirable to simultaneously detect abnormalities in the output power of a power amplifier early and measure that output power accurately and precisely. Furthermore, in detecting abnormalities in output power, there are cases where it is desirable to flexibly respond to various error detection conditions. For example, in a phased array antenna module, one example is when the criteria for determining abnormalities in the output power of a power amplifier are changed according to the settings of a beamtable in which the amplification gain setting value of the power amplifier provided for each of the multiple antenna elements is set.

[0006] In order to detect abnormalities in the output power of a power amplifier at an early stage, it is preferable to compare the detection result of a power detector with a predetermined reference voltage. However, there is a problem that quantitative evaluation of the output power cannot be performed by comparing it only with a predetermined reference voltage. Furthermore, in a configuration such as the wireless communication device disclosed in Patent Document 1, where the comparison result with the reference voltage is used only for feedback control of the amplification gain of the power amplifier, there is a problem that it cannot flexibly respond to various error detection conditions.

[0007] Furthermore, in order to accurately and precisely measure the output power of a power amplifier, it is preferable to input the detection result of a power detector into an analog-to-digital converter (ADC) and convert it into a digital value. However, there is a problem in that it takes a certain amount of time to convert the detection result of a power detector into a digital value, resulting in low real-time capability.

[0008] The present invention has been made in view of the above circumstances, and aims to provide a power detection circuit, a radio frequency integrated circuit, and a wireless communication device that can simultaneously detect abnormalities in the output power of a power amplifier at an early stage and measure that output power accurately and precisely. [Means for solving the problem]

[0009] To solve the above problems, a power detection circuit (70) according to one aspect of the present invention includes a power detector (70a) that detects the output power of a power amplifier (65) and outputs the detection result in two systems: a voltage output (VO) and a current output (IO), and a voltage comparison circuit (70b) that compares the voltage output of the power detector with a predetermined reference voltage (Vr) and outputs a power detection signal (DT) which is a first level if the voltage output is higher than the reference voltage and a second level if the voltage output is lower than the reference voltage.

[0010] In a power detection circuit according to one aspect of the present invention, the detection result of the output power of the power amplifier is output in two systems: a voltage output and a current output. The voltage output, one of the systems, is then compared with a predetermined reference voltage, and a power detection signal, which is a digital signal whose signal level changes according to the comparison result, is output. Thus, in a power detection circuit according to one aspect of the present invention, a power detection signal indicating the comparison result between the voltage output and the reference voltage, and a current output indicating the detection result of the output power of the power amplifier are output. This makes it possible to detect abnormalities in the output power of the power amplifier early and to measure that output power accurately and precisely.

[0011] A radio frequency integrated circuit (10) according to a first aspect of the present invention includes a power detection circuit (70) in one aspect for detecting the output power of the power amplifier; a circuit section (12) that amplifies a high-frequency signal supplied to an antenna element (21) and comprises the power amplifier (65) and a variable gain amplifier (63); and a first abnormality detection circuit (16) that detects whether or not there is an abnormality in the high-frequency signal based on an amplification factor setting value that defines the amplification factor of the circuit section and the power detection signal output from the voltage comparison circuit of the power detection circuit.

[0012] A radio frequency integrated circuit according to a second aspect of the present invention is a radio frequency integrated circuit according to a first aspect of the present invention, wherein the first abnormality detection circuit outputs a first abnormality signal (AL) when the amplification factor setting value is greater than a first setting reference value and the power detection signal is at the second level, and outputs a second abnormality signal (AH) when the amplification factor setting value is less than a second setting reference value which is less than the first setting reference value and the power detection signal is at the first level.

[0013] A radio frequency integrated circuit according to a third aspect of the present invention, in which the radio frequency integrated circuit according to a second aspect of the present invention, does not output the first abnormality signal and the second abnormality signal when the amplification factor setting value is smaller than the first setting reference value and larger than the second setting reference value.

[0014] A fourth aspect of the present invention is a radio frequency integrated circuit, in which the reference voltage is set such that the level of the power detection signal is switched when the amplification factor setting value is between the first setting reference value and the second setting reference value.

[0015] A fifth aspect of the present invention provides a radio frequency integrated circuit comprising: a circuit section (12) equipped with a power amplifier (65) that amplifies a high-frequency signal supplied to an antenna element (21); a power detection circuit (70) in one aspect that detects the output power of the power amplifier; a conversion circuit (71) that converts the current output of the power detector into a digital value; and a second abnormality detection circuit (6c) that detects whether or not there is an abnormality in the high-frequency signal based on the digital value and a predetermined comparison reference value (Qr).

[0016] A radio frequency integrated circuit according to a sixth aspect of the present invention is a radio frequency integrated circuit according to a fifth aspect of the present invention, wherein the comparison reference value is set to a value greater than the digital value converted by the conversion circuit when the amplification factor setting value that defines the amplification factor of the circuit section is at its maximum value, or to a value smaller than the digital value converted by the conversion circuit when the amplification factor setting value is at its minimum value.

[0017] The radio frequency integrated circuit according to the seventh aspect of the present invention is the radio frequency integrated circuit according to the fifth aspect of the present invention, and includes a storage unit (6a) for storing the digital value converted by the conversion circuit, and the second abnormality detection circuit detects the presence or absence of an abnormality in the high-frequency signal based on the digital value stored in the storage unit and the comparison reference value.

[0018] The wireless communication device according to the first aspect of the present invention includes a radio frequency integrated circuit (10) according to any one of the first to fourth aspects, and a control device (50) for acquiring the detection result of the first abnormality detection circuit.

[0019] The wireless communication device according to the second aspect of the present invention includes a radio frequency integrated circuit (10) according to any one of the fifth to seventh aspects, and a control device (50) for acquiring the detection result of the second abnormality detection circuit.

Effect of the Invention

[0020] According to the present invention, there is an effect that it is possible to achieve both early detection of an abnormality in the output power of the power amplifier and accurate and precise measurement of the output power.

Brief Description of the Drawings

[0021] [Figure 1] It is a system configuration diagram showing the configuration of a wireless communication device according to an embodiment of the present invention. [Figure 2] It is a block diagram showing the main configuration of a beamformer integrated circuit according to an embodiment of the present invention. [Figure 3] It is a block diagram showing the configuration of a power detection circuit provided in a wireless communication device according to an embodiment of the present invention. [Figure 4] It is a diagram showing the connection relationship between a digital circuit part and an analog circuit part provided in the RF front end of a beamformer integrated circuit according to an embodiment of the present invention. [Figure 5]FIG. 0 is a diagram showing the configuration of a first abnormality detection system that detects an output power abnormality using a power detection signal output from a power detection circuit according to an embodiment of the present invention. [Figure 6] FIG. 3 is a diagram showing the configuration of a second abnormality detection system that detects an output power abnormality using a current output output from a power detection circuit according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[0022] Hereinafter, a power detection circuit, a radio frequency integrated circuit, and a wireless communication device according to embodiments of the present invention will be described in detail with reference to the drawings.

[0023] FIG. 1 is a system configuration diagram showing the configuration of a wireless communication device according to an embodiment of the present invention. As shown in FIG. 1, the wireless communication device DV of this embodiment includes a phased array antenna module 1 and a control device 50. Such a wireless communication device DV can perform beam forming that can freely change the beam pattern, for example, using the millimeter wave band.

[0024] The phased array antenna module 1 has, for example, a plurality of integrated circuits (ICs) mounted on one surface of a substrate such as a known printed circuit board, and an antenna array mounted on the other surface. The plurality of integrated circuits and the antenna array constituting the phased array antenna module 1 are formed by using known materials and known methods. Further, the electrical connection structure between the plurality of integrated circuits and the electrical connection structure between the integrated circuit and the antenna array are not particularly limited. A known connection structure is adopted as the electrical connection structure.

[0025] The control device 50 communicates with a higher-level device (not shown) installed at the base of a pole or tower or in a station building, for example, via an optical fiber FB, and communicates with a corresponding wireless communication device such as a mobile terminal, fixed wireless access network equipment, or base station equipment using the phased array antenna module 1. The control device 50 includes an optical transceiver (not shown) or a pluggable type optical transceiver with an optical connector. The optical fiber FB is connected to the optical transceiver of the control device 50 via an optical connector CN installed in the housing of the wireless communication device DV.

[0026] <Phased Array Antenna Module> As shown in Figure 1, the phased array antenna module 1 comprises eight beamformer integrated circuits 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer integrated circuits 10A to 10H), an antenna array 20, a frequency conversion integrated circuit 30, and an RF signal coupler / splitter 40.

[0027] The phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. RF signals of the IF (intermediate frequency) signal frequency are transmitted and received between the control device 50 and the phased array antenna module 1 via the signal line 51. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0028] The beamformer integrated circuits 10A to 10H are integrated circuits that control the beam pattern of the antenna array 20. Each of the beamformer integrated circuits 10A to 10H is connected to multiple antenna elements 21 that make up the antenna array 20. For example, each of the beamformer integrated circuits 10A to 10H is connected to eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization. In other words, the antenna array 20 is composed of a total of 128 antenna elements 21: 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. Further details of the beamformer integrated circuits 10A to 10H will be described later.

[0029] The frequency conversion integrated circuit 30 is an integrated circuit that performs frequency conversion between an RF signal at the IF signal frequency and an RF signal at the frequency transmitted and received by the beamformer integrated circuits 10A to 10H and the antenna array 20.

[0030] The RF signal coupler / splitter 40 distributes the RF signal output from the frequency conversion integrated circuit 30 to each of the beamformer integrated circuits 10A to 10H. The RF signal coupler / splitter 40 also combines the RF signals received by each of the beamformer integrated circuits 10A to 10H and inputs them to the frequency conversion integrated circuit 30.

[0031] <Beamformer Integrated Circuit> Figure 2 is a block diagram showing the main components of a beamformer integrated circuit according to one embodiment of the present invention. The eight beamformer integrated circuits 10A to 10H have the same configuration as each other. Therefore, in the following description, one of the beamformer integrated circuits 10A to 10H, i.e., beamformer integrated circuit 10, may be described. The other seven beamformer integrated circuits may be omitted from the description.

[0032] The beamformer integrated circuit 10 (radio frequency integrated circuit) comprises 16 RF front ends (RFFEs) 5A to 5P, a digital circuit 6, an analog circuit 7, an RF signal coupler / splitter 8, and an analog-to-digital converter (ADC) 71 (conversion circuit). The 16 RF front ends 5A to 5P have the same configuration as each other. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., RF front end 5, may be described. The other 15 RF front ends may be omitted from the description.

[0033] In the beamformer integrated circuit 10 shown in Figure 2, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P such that each of the 16 RF front ends 5A to 5P corresponds one-to-one with each of the RF front ends 5. Of the 16 RF front ends 5A to 5P and 16 antenna elements 21A to 21P, 8 RF front ends (e.g., RF front ends 5A to 5H) and 8 antenna elements (e.g., antenna elements 21A to 21H) are for horizontal polarization, and the remaining 8 RF front ends (e.g., RF front ends 5I to 5P) and 8 antenna elements (e.g., antenna elements 21I to 21P) are for vertical polarization.

[0034] The 16 antenna elements 21A to 21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A to 21P, i.e., antenna element 21, may be described. The other 15 antenna elements may be omitted from the description. Antenna elements 21A to 21P may have the same configuration. For each of the configurations of antenna elements 21A to 21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may differ slightly.

[0035] Thus, in one beamformer integrated circuit 10, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P in a one-to-one correspondence. Therefore, in the phased array antenna module 1 having eight beamformer integrated circuits 10A to 10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A to 5P in each of the eight beamformer integrated circuits 10A to 10H.

[0036] The 128 antenna elements 21 constituting the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. Eight beamformer integrated circuits 10A to 10H control the transmission and reception of horizontally polarized radio waves and the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized and vertically polarized radio waves, the beamformer integrated circuits 10A to 10H set the phase and intensity of each of the 64 antenna elements so that the direction of the combined radio wave transmitted or received from the 64 antenna elements 21 is in a predetermined direction.

[0037] As shown in Figure 2, the RF front end 5 comprises a digital circuit section 11 and an analog circuit section 12 (circuit section). The digital circuit section 11 transmits and receives control-related communication messages to and from the control device 50 via the control line 52 shown in Figure 1. The digital circuit section 11 controls the RF front end 5 based on the communication messages transmitted from the control device 50.

[0038] In this embodiment, control-related communication messages are transmitted and received between the phased array antenna module 1 and the control device 50 via parallel communication. In other words, the digital circuit unit 11 transmits and receives control-related communication messages to and from the control device 50 via parallel communication. Note that the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. Serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) may also be used.

[0039] The digital circuit unit 11 is connected to the digital circuit 6 by internal wiring of the beamformer integrated circuit 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 50. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the content of the communication message transmitted from the control device 50.

[0040] A single communication transaction transmitted from the control device 50 to the phased array antenna module 1 includes additional information, commands, and data. The communication transaction has a fixed bit length. The command is a register address if it instructs a write to or read from a register. Alternatively, the command is a numerical value indicating an operation instruction to the beamformer integrated circuit 10 or the RF front-end 5. Both the command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 16 bits.

[0041] The digital circuit unit 11 includes a memory 13, which is a memory area for storing beam tables used for beamforming. The beam table is a lookup table that stores multiple combinations of phase shift amount setting values ​​and intensity setting values, which are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (a beam table with 2048 items) with 2048 combinations of phase shift amount setting values ​​and intensity setting values ​​is stored in the memory 13.

[0042] Memory 13 is implemented using, for example, SRAM (Static Random Access Memory). While it is preferable that memory 13 be implemented using SRAM, it may also be implemented using registers, DRAM (Dynamic Random Access Memory), flash memory, or ROM (Read Only Memory).

[0043] The analog circuit section 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit section 11, the analog circuit section 12 adjusts the phase and intensity of the RF signals transmitted and received by the antenna element 21 connected to the RF front end 5.

[0044] The analog circuit section 12 is connected to the analog circuit 7 via an RF signal coupler / splitter 8. The RF signal coupler / splitter 8 distributes the RF signal output from the analog circuit 7 to the analog circuit sections 12 provided in each of the RF front ends 5A to 5P. The RF signal coupler / splitter 8 also combines the RF signals output from the analog circuit sections 12 provided in each of the RF front ends 5A to 5P and outputs them to the analog circuit 7.

[0045] As shown in Figure 2, the analog circuit section 12 includes a phase shifter (PS) 61, a changeover switch (SW) 62, a variable gain amplifier (VGA) 63, a phase inverter (PI) 64, a power amplifier (PA) 65, a changeover switch (SW) 66, a low-noise amplifier (LNA) 67, a variable gain amplifier (VGA) 68, a phase inverter (PI) 69, and a power detection circuit (PD) 70.

[0046] The variable gain amplifier 63, the phase inverter 64, and the power amplifier 65 are located on the transmission path R1, while the low-noise amplifier 67, the variable gain amplifier 68, and the phase inverter 69 are located on the reception path R2. The transmission path R1 is the path through which the RF signal (high-frequency signal) output to the antenna element 21 passes, and the reception path R2 is the path through which the RF signal (high-frequency signal) input from the antenna element 21 passes. The changeover switches 62 and 66 switch between connecting the transmission path R1 or the reception path R2 between the phase shifter 61 and the antenna element 21 at specified time intervals. This allows the phased array antenna module 1 to transmit and receive high-frequency signals as a time-division multiplexing system.

[0047] The phase shifter 61 adjusts the phase shift amount of the RF signal passing through the transmission path R1 or the RF signal passing through the reception path R2 according to the phase shift amount setting value of the beam table read from the memory 13 of the digital circuit unit 11. In other words, the phase shifter 61 is provided in common to both the transmission path R1 and the reception path R2. Alternatively, the phase shifter 61 common to both the transmission path R1 and the reception path R2 may be omitted, and a separate phase shifter may be provided for each of the transmission path R1 and the reception path R2.

[0048] The variable gain amplifier 63 amplifies the RF signal passing through the transmission path R1 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 64 inverts the phase of the RF signal passing through the transmission path R1 according to the phase shift amount setting value of the beamtable read from the memory 13. The power amplifier 65 amplifies the RF signal passing through the transmission path R1 at a predetermined amplification factor. By adjusting the phase shift amount and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0049] The low-noise amplifier 67 amplifies the RF signal output from the selector switch 66 at a predetermined amplification factor. The variable-gain amplifier 68 amplifies the RF signal passing through the receiving path R2 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 69 inverts the phase of the RF signal passing through the receiving path R2 according to the phase shift amount setting value of the beamtable read from the memory 13. By adjusting the phase shift amount and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0050] The power detection circuit 70 detects the power of the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, and outputs a signal indicating the detection result in two types of signals: an analog signal and a digital signal. Specifically, a branching switch BR is provided in the transmission path R1 between the power amplifier 65 and the switch 66, which branches the RF signal amplified by the power amplifier 65 at a stable branching ratio. One of the RF signals branched by branching switch BR is supplied to the switch 66, and the other of the RF signals branched by branching switch BR is supplied to the power detection circuit 70. The power detection circuit 70 detects the power by inputting the power of the other RF signal branched by branching switch BR, and outputs a signal indicating the detection result in two types of signals: an analog signal and a digital signal.

[0051] Figure 3 is a block diagram showing the configuration of a power detection circuit provided in a wireless communication device according to one embodiment of the present invention. As shown in Figure 3, the power detection circuit 70 includes a power detector 70a and a voltage comparison circuit 70b. The power detector 70a detects the power of the other RF signal SP that has been branched by the brancher BR shown in Figure 2, and outputs the detection result in two systems: a voltage output VO and a current output IO.

[0052] The voltage output VO is an analog signal whose voltage changes according to the detection result of the power of the RF signal SP, and the current output IO is an analog signal whose current changes according to the detection result of the power of the RF signal SP. For example, the voltage output VO may be a signal whose voltage changes in proportion to the magnitude of the detected power, and the current output IO may be a signal whose current changes in proportion to the magnitude of the detected power.

[0053] The voltage comparison circuit 70b compares the voltage output VO of the power detector 70a with a predetermined reference voltage Vr and outputs a power detection signal DT according to the comparison result. This power detection signal DT is a digital signal. Specifically, the voltage comparison circuit 70b outputs a power detection signal DT that is at the "H (high)" level (first level) when the voltage output VO is higher than the reference voltage Vr, and at the "L (low)" level (second level) when the voltage output VO is lower than the reference voltage Vr. The reference voltage Vr will be described later.

[0054] The power detection circuit 70 outputs an analog signal, the current output IO, and a digital signal, the power detection signal DT. The analog signal, the current output IO, is input to a current-voltage conversion circuit 72 (see Figure 6) located outside the RF front-end 5. The digital signal, the power detection signal DT, is input to the digital circuit section 11 within the RF front-end 5. The reason for outputting two types of signals (current output IO and power detection signal DT) from the power detection circuit 70 is to achieve both early detection of abnormalities in the output power of the power amplifier 65 and accurate and precise measurement of that output power.

[0055] One ADC71 is provided for each of the multiple RF front-ends 5. For this reason, the ADC71 is positioned within the beamformer integrated circuit 10 at a location separated from some of the RF front-ends 5. The reason for transmitting the detection result of the power detector 70a to the ADC71 as a current output IO is to ensure that the detection result is correctly input to the ADC71, even if the ADC71 is positioned at a location separated from the power detection circuit 70 within the beamformer integrated circuit 10. If the detection result of the power detector 70a were to be transmitted as a voltage output VO to the ADC71, which is positioned at an isolated location, it is conceivable that information degradation due to voltage drops occurring in the transmission line would occur, preventing the detection result from being correctly input to the ADC71.

[0056] The ADC71 converts one of the multiple current output IOs output from the multiple power detection circuits 70 (more precisely, the voltage converted by the current-voltage conversion circuit 72 shown in Figure 6) into a digital signal. The ADC71 starts the conversion process when a trigger signal instructing the start of the conversion is input. The ADC71 requires a certain number of clock cycles from the start of the conversion process until it is completed. When the conversion process is complete, the ADC71 outputs a signal indicating that the conversion is complete. The signal (digital signal) converted by the ADC71 can be extracted from the ADC71 after the above-mentioned signal indicating the completion of the conversion is output. The frequency of the clock supplied to the ADC71 is lower than the frequency of the clock supplied to the digital circuit 6 of the beamformer IC 10 and the digital circuit sections 11 provided in the multiple RF front ends 5. In addition, the signal (digital signal) converted by the ADC71 may be held in a register when the ADC71 completes the conversion process.

[0057] When the control device 50 requests the acquisition of a digital signal converted by the ADC 71, the digital circuit 6 retrieves the digital signal from the ADC 71. The digital circuit 6 then transmits the acquired digital signal to the control device 50. Note that the digital signal can only be retrieved from the ADC 71 after a signal indicating the completion of the conversion to a digital signal is output from the ADC 71.

[0058] Furthermore, the ADC71 may be provided one per beamformer integrated circuit 10, or multiple ADC71s may be provided per beamformer integrated circuit 10. For example, the ADC71 may be provided two per beamformer integrated circuit 10. In this configuration, for example, the first ADC71 may be connected to eight power detection circuits provided in the RF front ends 5A to 5H, and the second ADC71 may be connected to eight power detection circuits provided in the RF front ends 5I to 5P.

[0059] Figure 4 shows the connection relationship between the digital circuit section and the analog circuit section provided at the RF front end of a beamformer integrated circuit according to one embodiment of the present invention. As shown in Figure 4, the phase shifter 61, variable gain amplifiers 63, 68, and phase inverters 64, 69 provided in the analog circuit section 12 are controlled according to the contents of the beam table stored in the memory 13. In contrast, the changeover switches 62, 66, power amplifier 65, and low-noise amplifier 67 provided in the analog circuit section 12 are controlled by logic circuits such as registers (not shown) provided in the digital circuit section 11. The power detection signal DT output from the power detection circuit 70 is input to the digital circuit section 11.

[0060] The unpacking circuit 14 unpacks the bit sequence of the phase shift amount setting value read from the memory 13 of the beam table into a bit sequence of a control value (phase shift control value) for controlling the phase shifter 61. The phase shift amount setting value stored in the beam table is, for example, 7 bits, and the intensity setting value is, for example, 5 bits. The unpacking circuit 14 unpacks 6 bits of the 7-bit phase shift amount setting value into a 52-bit control value bit sequence. The remaining 1 bit of the phase shift amount setting value is used to control the phase inverters 64 and 69. The number of bits in the phase shift amount setting value is set according to the resolution of the phase shift amount, and the number of bits in the control value is set according to the number of division units constituting the phase shifter 61.

[0061] When the most significant bit of the phase shift amount setting value is "1", a phase inversion is instructed to the phase inverters 64 and 69. This corresponds to setting a phase shift amount of 180 degrees. The lower six bits of the phase shift amount setting value are used to indicate which of the 52 division units constituting the phase shifter 61 will have their state changed. When the value of the lower six bits of the phase shift amount setting value is "0", all 52 division units constituting the phase shifter 61 are in the reference state, and when the value is between "1" and "52", the number of division units corresponding to that value are set to the phase shift state. Furthermore, when the value of the lower six bits of the phase shift amount setting value is "52", all 52 division units constituting the phase shifter 61 are set to the phase shift state. In other words, when the phase shifter 61 is composed of 52 division units, the phase shift state of the phase shifter 61 can be set in 53 steps.

[0062] The phase shifter 61 is designed so that, in the frequency range used by the phased array antenna module 1, the phase shift amount exceeds 180 degrees when all 52 division units are set to the phase shift state. In this embodiment, a configuration in which the phase shift amount of the RF signal passing through the transmission path R1 or the reception path R2 is adjusted by combining phase inverters 64 and 69 with the phase shifter 61 capable of setting a phase shift amount exceeding 180 degrees is used as an example, but the configuration is not limited to this. A configuration using only a phase shifter capable of setting a phase shift amount exceeding 360 degrees is also possible without using phase inverters 64 and 69.

[0063] Furthermore, as mentioned above, the lower 6 bits of the phase shift amount setting value are expanded into a 52-bit bit sequence of a control value (phase shift control value) for controlling the phase shifter 61 by the expansion circuit 14 shown in Figure 4. In other words, the lower 6 bits of the phase shift amount setting value are expanded into a bit sequence with the same number of bits as the number of division units that make up the phase shifter 61. Note that the number of division units that make up the phase shifter 61 is not limited to 52, but can be any number.

[0064] The five bits of the intensity setting value are amplification factor setting values ​​that define the amplification factor of the variable gain amplifiers 63 and 68. By individually setting the five bits of intensity setting value for the variable gain amplifiers 63 and 68, the signal strength of the RF signal passing through the transmission path R1 and the RF signal passing through the reception path R2 are individually adjusted.

[0065] Figure 5 shows the configuration of a first anomaly detection system that detects an output power anomaly using a power detection signal output from a power detection circuit according to one embodiment of the present invention. As shown in Figure 5, the first anomaly detection system includes a memory 13, a register 15, and an anomaly detection circuit 16 (first anomaly detection circuit) provided in the digital circuit section 11.

[0066] As described above, memory 13 stores a beam table containing amplification factor setting values ​​that define the amplification factor of the variable gain amplifier 63. Register 15 holds amplification factor setting values ​​that define the amplification factor of the power amplifier 65. The amplification factor of the RF signal passing through the transmission path R1 of the analog circuit section 12 (the amplification factor of the circuit section) is defined by the amplification factor setting values ​​read from memory 13 and the amplification factor setting values ​​held in register 15. Hereinafter, the amplification factor setting value that defines the amplification factor of the RF signal passing through the transmission path R1 of the analog circuit section 12 will be referred to as the "transmission signal amplification factor setting value".

[0067] The abnormality detection circuit 16 detects whether there is an abnormality in the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, based on the amplification factor setting value read from the memory 13, the amplification factor setting value held in the register 15, and the power detection signal DT output from the power detection circuit 70. In other words, the abnormality detection circuit 16 detects whether there is an abnormality in the output power of the power amplifier 65, based on the transmission signal amplification factor setting value and the power detection signal DT output from the power detection circuit 70.

[0068] The abnormality detection circuit 16 uses the high-power setting reference value RH (first setting reference value) and the low-power setting reference value RL (second setting reference value) to detect whether or not there is an abnormality in the output power of the power amplifier 65. The high-power setting reference value RH and the low-power setting reference value RL are reference values ​​set relative to the transmission signal amplification factor setting value.

[0069] The high-power setting reference value RH is a reference value for determining whether the transmission signal amplification factor setting value will cause the output power of the power amplifier 65 to be greater than a predetermined first power (high output). The low-power setting reference value RL is a reference value for determining whether the transmission signal amplification factor setting value will cause the output power of the power amplifier 65 to be less than a predetermined second power (low output). The high-power setting reference value RH and the low-power setting reference value RL are held in a register (not shown) and can be rewritten based on instructions from the control device 50.

[0070] The high-power setting reference value RH and the low-power setting reference value RL are set such that the high-power setting reference value RH is greater than the low-power setting reference value RL within the range in which the output power of the power amplifier 65 can change. At this time, the reference voltage Vr used in the voltage comparison circuit 70b of the power detection circuit 70 is set so that the level of the power detection signal DT is switched when the amplification factor setting value is between the high-power setting reference value RH and the low-power setting reference value RL.

[0071] The abnormality detection circuit 16 outputs a low-power abnormality detection signal AL (first abnormality signal) if the transmission signal amplification factor setting value is greater than the high-power setting reference value RH and the power detection signal DT is at the "L" level. In other words, if the transmission signal amplification factor setting value is a value that indicates high power, but the power detected by the power detection circuit 70 is low, a low-power abnormality detection signal AL at the "H" level is output.

[0072] The anomaly detection circuit 16 outputs a high-power anomaly detection signal AH (second anomaly signal) if the transmission signal amplification factor setting value is smaller than the low-power setting reference value RL and the power detection signal DT is at the "H" level. In other words, if the power detected by the power detection circuit 70 is high despite the transmission signal amplification factor setting value indicating low power, the high-power anomaly detection signal AH at the "H" level is output.

[0073] Furthermore, if the transmission signal amplification factor setting is smaller than the high-power setting reference value RH and larger than the low-power setting reference value RL, the abnormality detection circuit 16 will not output the low-power abnormality detection signal AL and the high-power abnormality detection signal AH, regardless of the level of the power detection signal DT. In other words, since the transmission signal amplification factor setting is between the value indicating high power and the value indicating low power, abnormality in output power is not detected, and the low-power abnormality detection signal AL and the high-power abnormality detection signal AH are at the "L" level.

[0074] In this way, the anomaly detection circuit 16 can detect output power anomalies using flexible criteria that correspond to the contents of the beam table (amplification factor setting value that defines the amplification factor of the variable gain amplifier 63) and the contents of the register 15 (amplification factor setting value that defines the amplification factor of the power amplifier 65). Moreover, since the power detection signal DT, which is a digital signal output from the power detection circuit 70, is used to detect output power anomalies, output power anomalies can be detected with high real-time accuracy.

[0075] The high-power anomaly detection signal AH and the low-power anomaly detection signal AL output from the anomaly detection circuit 16 are acquired by the control device 50. Alternatively, the high-power anomaly detection signal AH and the low-power anomaly detection signal AL output from the anomaly detection circuit 16 may be stored in a register (not shown) provided in the digital circuit unit 11. The control device 50 may then request acquisition from the digital circuit unit 11 to retrieve the high-power anomaly detection signal AH and the low-power anomaly detection signal AL stored in the register.

[0076] Figure 6 shows the configuration of a second abnormality detection system that detects an abnormality in output power using the current output from a power detection circuit according to one embodiment of the present invention. As shown in Figure 6, the second abnormality detection system comprises an ADC 71, a current-voltage conversion circuit 72, and registers 6a (storage unit), 6b, and an abnormality detection circuit 6c (second abnormality detection circuit) provided in the digital circuit 6.

[0077] The current-voltage conversion circuit 72 converts one of the multiple current outputs IO output from the multiple power detection circuits 70 into a voltage. Since the current output IO is an analog signal, the voltage converted by the current-voltage conversion circuit 72 is also an analog signal. The current-voltage conversion circuit 72 is positioned close to the ADC 71. This is to allow the voltage converted by the current-voltage conversion circuit 72 to be input directly to the ADC 71 (with minimal voltage change).

[0078] As a means of selecting one of the multiple current output IOs output from multiple power detection circuits 70 and inputting it to the current-voltage conversion circuit 72, the following configurations are conceivable. For example, one configuration is conceivable in which one current output IO is selected by enabling only the power detector 70a of one of the multiple power detection circuits 70 connected to the current-voltage conversion circuit 72, and disabling the power detectors 70a of the remaining power detection circuits 70. Alternatively, one configuration is conceivable in which the current output IOs output from multiple power detection circuits 70 connected to the current-voltage conversion circuit 72 via a switch having multiple input ports and one output port are selected by controlling the switch.

[0079] Register 6a, located in the digital circuit 6, temporarily holds the digital value converted by the ADC 71. Register 6b, also located in the digital circuit 6, holds the comparison reference value Qr, which is used when detecting an abnormality in output power using the current output IO output from the power detection circuit 70. The comparison reference value Qr held in register 6b can be rewritten based on instructions from the control device 50.

[0080] An anomaly detection circuit 6c provided in the digital circuit 6 detects whether or not there is an anomaly in the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, based on the digital value held in register 6a and the comparison reference value Qr held in register 6b. If the anomaly detection circuit 6c detects an anomaly in the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, it outputs an anomaly detection signal AS.

[0081] The comparison reference value Qr can be set to any value relative to the digital value converted by the ADC71. For example, to detect a high output abnormality in the output power of the power amplifier 65, the comparison reference value Qr is set to a value greater than the value Q11 of the digital signal converted by the ADC71 when the transmit signal amplification factor setting is at its maximum value. Alternatively, to detect a low output abnormality in the output power of the power amplifier 65, the comparison reference value Qr is set to a value less than the value Q22 of the digital signal converted by the ADC71 when the transmit signal amplification factor setting is at its minimum value.

[0082] Furthermore, it is also possible to set the comparison reference value Qr to a value between the above values ​​Q11 and Q22. When set to such a value, the abnormality detection signal AS output from the abnormality detection circuit 6c is used for purposes other than detecting output abnormalities in the output power of the power amplifier 65. For example, since the digital signal output from the ADC 71 accurately indicates the output power of the power amplifier 65, it can be used to verify how accurately the output power of the power amplifier 65 is output relative to the transmission signal amplification factor setting value.

[0083] In this way, the anomaly detection circuit 6c compares the precise measurement results obtained by the ADC 71 with an arbitrary reference value Qr. This makes it possible to accurately detect whether or not there is an anomaly in the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21.

[0084] The abnormality detection signal AS output from the abnormality detection circuit 6c is acquired by the control device 50. Alternatively, the abnormality detection signal AS output from the abnormality detection circuit 6c may be stored in a register (not shown) provided in the digital circuit 6. The control device 50 may then request acquisition from the digital circuit 6 to acquire the abnormality detection signal AS stored in the register.

[0085] As described above, in this embodiment, the detection result of the output power of the power amplifier 65 is output in two systems: a voltage output VO and a current output IO. Then, the voltage output VO, one of the systems, is compared with a predetermined reference voltage Vr, and a power detection signal DT, which is a digital signal whose signal level changes according to the comparison result, is output. In this way, the power detection circuit 70 in this embodiment outputs a power detection signal DT that shows the comparison result between the voltage output VO and the reference voltage Vr, and a current output IO that shows the detection result of the output power of the power amplifier 65. This makes it possible to detect abnormalities in the output power of the power amplifier 65 at an early stage and to measure that output power accurately and precisely.

[0086] Although the power detection circuit, radio frequency integrated circuit, and wireless communication device according to embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be freely modified within the scope of the present invention. For example, the power detection signal DT described above is a signal that is at the "H" level when the voltage output VO is higher than the reference voltage Vr, and at the "L (low)" level when the voltage output VO is lower than the reference voltage Vr, but the signal levels may be reversed. The same applies to other digital signals.

[0087] Furthermore, the phased array antenna module described in the above embodiment was for a time-division multiplexing system. However, the phased array antenna module of the present invention may also be for a frequency-division multiplexing system.

[0088] Furthermore, in the embodiments described above, an example was described in which one antenna element 21 and one RF front end 5 are connected in a one-to-one correspondence. However, in the present invention, two front ends may be connected to dual-polarization antenna elements, each having a connection terminal for horizontal polarization and a connection terminal for vertical polarization. [Explanation of symbols]

[0089] 6a…Register, 6c…Anomaly detection circuit, 10…Beamformer integrated circuit, 12…Analog circuit section, 16…Anomaly detection circuit, 21…Antenna element, 50…Control device, 63…Variable gain amplifier, 65…Power amplifier, 70…Power detection circuit, 70a…Power detector, 70b…Voltage comparison circuit, 71…Analog-to-digital converter, AH…High-power anomaly detection signal, AL…Low-power anomaly detection signal, DT…Power detection signal, IO…Current output, Qr…Reference value for comparison, VO…Voltage output, Vr…Reference voltage

Claims

1. A power detector that detects the output power of a power amplifier and outputs the detection result in two systems: voltage output and current output, A voltage comparison circuit compares the voltage output of the power detector with a predetermined reference voltage and outputs a power detection signal that is at a first level if the voltage output is higher than the reference voltage, and at a second level if the voltage output is lower than the reference voltage. A power detection circuit equipped with the following features.

2. A power detection circuit according to claim 1, wherein the output power of the power amplifier is detected, A circuit section comprising the aforementioned power amplifier and variable gain amplifier, which amplifies the high-frequency signal supplied to the antenna element, A first abnormality detection circuit detects whether or not there is an abnormality in the high-frequency signal based on an amplification factor setting value that defines the amplification factor of the circuit section and the power detection signal output from the voltage comparison circuit of the power detection circuit, A radio frequency integrated circuit equipped with the following features.

3. The first abnormality detection circuit is, If the amplification factor setting value is greater than the first setting reference value and the power detection signal is at the second level, a first abnormal signal is output. If the amplification factor setting value is smaller than a second setting reference value which is smaller than the first setting reference value, and the power detection signal is at the first level, then a second abnormal signal is output. The radio frequency integrated circuit according to claim 2.

4. The radio frequency integrated circuit according to claim 3, wherein the first abnormality detection circuit does not output the first abnormality signal and the second abnormality signal when the amplification factor setting value is smaller than the first setting reference value and larger than the second setting reference value.

5. The radio frequency integrated circuit according to claim 3, wherein the reference voltage is set such that the level of the power detection signal is switched when the amplification factor setting value is between the first setting reference value and the second setting reference value.

6. A circuit section equipped with a power amplifier that amplifies the high-frequency signal supplied to the antenna element, A power detection circuit according to claim 1, wherein the output power of the power amplifier is detected, A conversion circuit that converts the current output of the power detector into a digital value, A second abnormality detection circuit detects whether or not there is an abnormality in the high-frequency signal based on the digital value and a predetermined comparison reference value, A radio frequency integrated circuit equipped with the following features.

7. The radio frequency integrated circuit according to claim 6, wherein the comparison reference value is set to a value greater than the digital value converted by the conversion circuit when the amplification factor setting value defining the amplification factor of the circuit section is at its maximum value, or to a value smaller than the digital value converted by the conversion circuit when the amplification factor setting value is at its minimum value.

8. The system includes a storage unit that stores the digital value converted by the conversion circuit, The second abnormality detection circuit detects whether or not there is an abnormality in the high-frequency signal based on the digital value stored in the memory unit and the comparison reference value. The radio frequency integrated circuit according to claim 6.

9. A radio frequency integrated circuit according to any one of claims 2 to 5, A control device that acquires the detection result of the first abnormality detection circuit, A wireless communication device equipped with the following features.

10. A radio frequency integrated circuit according to any one of claims 6 to 8, A control device that acquires the detection result of the second abnormality detection circuit, A wireless communication device equipped with the following features.

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