Integrated circuit, wireless communication device, and method for acquiring abnormal conditions

Abstract

The present invention provides an integrated circuit, a wireless communication device, and a method for acquiring abnormal conditions that can detect abnormal conditions early without requiring a dedicated wired communication circuit. [Solution] The beamformer integrated circuit includes an anomaly detection circuit for detecting the presence or absence of an anomaly, and a storage area including a detection result storage area for storing the detection result of the anomaly detection circuit. When it receives a first communication message that specifies an address and instructs the reading of information stored in the storage area, it transmits a second communication message that includes information read from the area of ​​the storage area specified by the address, and an anomaly status information indicating whether or not an anomaly has occurred based on the detection result stored in the detection result storage area.

Description

Technical Field

[0005] ,

[0001] The present invention relates to an integrated circuit, a wireless communication device, and a method for obtaining an abnormal state.

Background Art

[0002] Some integrated circuits can detect abnormal states. For example, a radio frequency integrated circuit used in a wireless communication device includes a power detector (PD) in the path from a power amplifier (PA) to an antenna, and there are those that can detect an abnormality in the power of a radio signal transmitted from the antenna according to the detection result of the power detector. In such an integrated circuit, there is one that stores information indicating the detection result of an abnormal state.

[0003] Patent Document 1 below discloses an abnormality detection data recording device that can detect an abnormality and leave a history thereof. This abnormality detection data recording device includes a first semiconductor integrated circuit device and a second semiconductor integrated circuit device, transmits abnormality detection data indicating an abnormality detected by the first semiconductor integrated circuit device to the second semiconductor integrated circuit device, and stores the abnormality detection data in the second semiconductor integrated circuit device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, in the technology disclosed in Patent Document 1 mentioned above, the anomaly detection data is stored in a second semiconductor integrated circuit device, which is different from the first semiconductor integrated circuit device in which the anomaly was detected. For this reason, a dedicated wired communication circuit is provided to transmit the anomaly detection data, and each time an anomaly is detected in the first semiconductor integrated circuit device, the anomaly detection data is transmitted to the second semiconductor integrated circuit device via the dedicated wired communication circuit.

[0006] The present invention has been made in view of the above circumstances, and aims to provide an integrated circuit, a wireless communication device, and a method for acquiring abnormal conditions that can detect the occurrence of abnormal conditions at an early stage without requiring a dedicated wired communication circuit. [Means for solving the problem]

[0007] To solve the above problems, an integrated circuit (10) according to a first aspect of the present invention includes an abnormality detection circuit (16) for detecting the presence or absence of an abnormality, and a storage area including a detection result storage area for storing the detection result of the abnormality detection circuit. When a first communication message is received that specifies an address and instructs the reading of information stored in the storage area, the integrated circuit (10) transmits a second communication message including first information stored in the area of ​​the storage area specified by the address, and second information indicating whether or not an abnormality has occurred based on the detection result stored in the detection result storage area.

[0008] In an integrated circuit according to a first aspect of the present invention, the detection result of an abnormality detection circuit that detects the presence or absence of an abnormality is stored in a memory area. When a first communication message is received that specifies an address and instructs the reading of information stored in the memory area, a second communication message is transmitted that includes first information stored in the memory area specified by the address and second information indicating whether or not an abnormality has occurred based on the detection result stored in the detection result memory area. This makes it possible to detect the occurrence of an abnormal condition early without requiring a dedicated wired communication circuit.

[0009] An integrated circuit according to a second aspect of the present invention is an integrated circuit according to a first aspect of the present invention, wherein the detection result storage area includes a first storage area for storing third information indicating the latest detection result of the abnormality detection circuit, and a second storage area provided corresponding to the first storage area for storing fourth information indicating the detection history of abnormalities detected by the abnormality detection circuit, and when the fourth information is stored in the second storage area, the second communication message including the second information indicating the occurrence of an abnormality is transmitted.

[0010] An integrated circuit according to a third aspect of the present invention, in an integrated circuit according to a second aspect of the present invention, receives a first communication message that specifies the address of the first storage area and instructs the reading of information stored in the first storage area, and transmits a second communication message in which the third information stored in the first storage area is included as first information.

[0011] An integrated circuit according to a fourth aspect of the present invention is an integrated circuit according to any one of the first to third aspects of the present invention, wherein the detection result storage area includes a third storage area that stores a plurality of fifth pieces of information indicating the abnormal state detected by the abnormality detection circuit as a history, and when a first communication message is received that specifies the address of the third storage area and instructs the reading of information stored in the third storage area, a second communication message is transmitted in which the fifth piece of information stored in the area of ​​the third storage area specified by the address is included as first information.

[0012] A wireless communication device (DV) according to a first aspect of the present invention comprises an integrated circuit (10) according to any of the first to fourth aspects described above, and a control device (50) that transmits the first communication message to the integrated circuit, wherein the control device determines whether or not an abnormality has occurred based on the second information contained in the second communication message transmitted from the integrated circuit.

[0013] A wireless communication device according to a second aspect of the present invention, in which, when the control device determines that an abnormality has occurred, transmits a third communication message to the integrated circuit specifying an address and instructing it to read the information stored in the detection result storage area.

[0014] An abnormal state acquisition method according to a first aspect of the present invention comprises a first step in which a control device (50) transmits the first communication message to an integrated circuit according to any of the first to fourth aspects described above, and a second step in which, upon receiving the first communication message, the integrated circuit transmits the second communication message to the control device.

[0015] A second aspect of the present invention provides a method for acquiring an abnormal state, the first aspect of the present invention, comprising: a third step in which the control device determines whether or not an abnormality has occurred based on the second information contained in the second communication message transmitted from the integrated circuit; and a fourth step in which, if the control device determines that an abnormality has occurred, the control device transmits a third communication message to the integrated circuit specifying an address and instructing it to read the information stored in the detection result storage area. [Effects of the Invention]

[0016] According to the present invention, there is an advantage in that abnormal conditions can be detected early without requiring a dedicated wired communication circuit. [Brief explanation of the drawing]

[0017] [Figure 1] This is a system configuration diagram showing the configuration of a wireless communication device according to the first embodiment of the present invention. [Figure 2] This is a block diagram showing the main components of a beamformer integrated circuit according to a first embodiment of the present invention. [Figure 3] This figure shows the connection relationship between the digital circuit section and the analog circuit section provided at the RF front end of a beamformer integrated circuit according to the first embodiment of the present invention. [Figure 4]It is a diagram showing a configuration example of an abnormality detection system that detects an output power abnormality using a power detection signal output from a power detection circuit in the first embodiment of the present invention. [Figure 5] It is a diagram showing an example of a memory map of registers provided in a beamformer integrated circuit according to the first embodiment of the present invention. [Figure 6] In the first embodiment of the present invention, it is a diagram showing an example of a read instruction communication telegram and a read reply communication telegram transmitted and received between a control device and a beamformer integrated circuit. [Figure 7] In the first embodiment of the present invention, it is a diagram showing an example of a communication telegram when information stored in a register to which address K is assigned is read. [Figure 8] In the first embodiment of the present invention, it is a diagram showing an example of a communication telegram when information stored in a register to which address K + 1 is assigned is read. [Figure 9] In the first embodiment of the present invention, it is a diagram showing an example of a communication telegram when information stored in a register to which address L is assigned is read. [Figure 10] In the first embodiment of the present invention, it is a diagram showing an example of a communication telegram when information stored in a register to which address L + 1 is assigned is read. [Figure 11] It is a diagram showing an example of a write instruction communication telegram transmitted from a control device to a beamformer integrated circuit. [Figure 12] It is a diagram showing an example of an operation instruction communication telegram transmitted from a control device to a beamformer integrated circuit. [Figure 13] It is a diagram showing an example of a memory map of registers provided in a beamformer integrated circuit according to the second embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0018] The following describes in detail, with reference to the drawings, an integrated circuit, a wireless communication device, and a method for acquiring abnormal conditions according to embodiments of the present invention. In the following description, a beamformer integrated circuit will be used as an example of an integrated circuit according to embodiments of the present invention. A phased array antenna module and a wireless communication device equipped with a beamformer integrated circuit will also be described.

[0019] [First Embodiment] <Wireless communication equipment> Figure 1 is a system configuration diagram showing the configuration of a wireless communication device according to a first embodiment of the present invention. As shown in Figure 1, the wireless communication device DV of this embodiment comprises a phased array antenna module 1 and a control device 50. Such a wireless communication device DV can, for example, use the millimeter wave band and perform beamforming, which allows the beam pattern to be freely changed.

[0020] The phased array antenna module 1 comprises, for example, a plurality of integrated circuits (ICs) mounted on one side of a substrate such as a known printed circuit board, and an antenna array mounted on the other side. The plurality of integrated circuits and the antenna array constituting the phased array antenna module 1 are formed by using known materials and known methods. Furthermore, the electrical connection structure between the plurality of integrated circuits and the electrical connection structure between the integrated circuits and the antenna array are not particularly limited. Known connection structures are employed as the electrical connection structures.

[0021] The control device 50 communicates with a higher-level device (not shown) installed at the base of a pole or tower or in a station building, for example, via an optical fiber FB, and communicates with a corresponding wireless communication device such as a mobile terminal, fixed wireless access network equipment, or base station equipment using the phased array antenna module 1. The control device 50 includes an optical transceiver (not shown) or a pluggable type optical transceiver with an optical connector. The optical fiber FB is connected to the optical transceiver of the control device 50 via an optical connector CN installed in the housing of the wireless communication device DV.

[0022] <Phaseed Array Antenna Module> As shown in Figure 1, the phased array antenna module 1 comprises eight beamformer integrated circuits 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer integrated circuits 10A to 10H), an antenna array 20, a frequency conversion integrated circuit 30, and an RF signal coupler / splitter 40.

[0023] The phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. RF signals of the IF (intermediate frequency) signal frequency are transmitted and received between the control device 50 and the phased array antenna module 1 via the signal line 51. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0024] The beamformer integrated circuits 10A to 10H are integrated circuits that control the beam pattern of the antenna array 20. Each of the beamformer integrated circuits 10A to 10H is connected to multiple antenna elements 21 that make up the antenna array 20. For example, each of the beamformer integrated circuits 10A to 10H is connected to eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization. In other words, the antenna array 20 is composed of a total of 128 antenna elements 21: 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. Further details of the beamformer integrated circuits 10A to 10H will be described later.

[0025] The frequency conversion integrated circuit 30 is an integrated circuit that performs frequency conversion between an RF signal at the IF signal frequency and an RF signal at the frequency transmitted and received by the beamformer integrated circuits 10A to 10H and the antenna array 20.

[0026] The RF signal coupler / splitter 40 distributes the RF signal output from the frequency conversion integrated circuit 30 to each of the beamformer integrated circuits 10A to 10H. The RF signal coupler / splitter 40 also combines the RF signals received by each of the beamformer integrated circuits 10A to 10H and inputs them to the frequency conversion integrated circuit 30.

[0027] <Beamformer Integrated Circuit> Figure 2 is a block diagram showing the main components of a beamformer integrated circuit according to a first embodiment of the present invention. The eight beamformer integrated circuits 10A to 10H have the same configuration as each other. Therefore, in the following description, one of the beamformer integrated circuits 10A to 10H, i.e., beamformer integrated circuit 10, may be described. The other seven beamformer integrated circuits may be omitted from the description.

[0028] The beamformer integrated circuit 10 (integrated circuit) comprises 16 RF front ends (RFFEs) 5A to 5P, a digital circuit 6, an analog circuit 7, and an RF signal coupler / splitter 8. The 16 RF front ends 5A to 5P have the same configuration as each other. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., RF front end 5, may be described. The other 15 RF front ends may be omitted from the description.

[0029] In the beamformer integrated circuit 10 shown in Figure 2, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P such that each of the 16 RF front ends 5A to 5P corresponds one-to-one with each of the RF front ends 5. Of the 16 RF front ends 5A to 5P and 16 antenna elements 21A to 21P, 8 RF front ends (e.g., RF front ends 5A to 5H) and 8 antenna elements (e.g., antenna elements 21A to 21H) are for horizontal polarization, and the remaining 8 RF front ends (e.g., RF front ends 5I to 5P) and 8 antenna elements (e.g., antenna elements 21I to 21P) are for vertical polarization.

[0030] The 16 antenna elements 21A to 21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A to 21P, i.e., antenna element 21, may be described. The other 15 antenna elements may be omitted from the description. Antenna elements 21A to 21P may have the same configuration. For each of the configurations of antenna elements 21A to 21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may differ slightly.

[0031] Thus, in one beamformer integrated circuit 10, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P in a one-to-one correspondence. Therefore, in the phased array antenna module 1 having eight beamformer integrated circuits 10A to 10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A to 5P in each of the eight beamformer integrated circuits 10A to 10H.

[0032] The 128 antenna elements 21 constituting the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. Eight beamformer integrated circuits 10A to 10H control the transmission and reception of horizontally polarized radio waves and the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized and vertically polarized radio waves, the beamformer integrated circuits 10A to 10H set the phase and intensity of each of the 64 antenna elements so that the direction of the combined radio wave transmitted or received from the 64 antenna elements 21 is in a predetermined direction.

[0033] As shown in Figure 2, the RF front end 5 comprises a digital circuit section 11 and an analog circuit section 12 (circuit section). The digital circuit section 11 transmits and receives control-related communication messages to and from the control device 50 via the control line 52 shown in Figure 1. The digital circuit section 11 controls the RF front end 5 based on the communication messages transmitted from the control device 50.

[0034] In this embodiment, control-related communication messages are transmitted and received between the phased array antenna module 1 and the control device 50 via parallel communication. In other words, the digital circuit unit 11 transmits and receives control-related communication messages to and from the control device 50 via parallel communication. Note that the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. Serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) may also be used.

[0035] The digital circuit unit 11 is connected to the digital circuit 6 by internal wiring of the beamformer integrated circuit 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 50. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the content of the communication message transmitted from the control device 50.

[0036] A single communication transaction transmitted from the control device 50 to the phased array antenna module 1 includes additional information, commands, and data. The communication transaction has a fixed bit length. The command is a register address if it instructs a write to or read from a register. Alternatively, the command is a numerical value indicating an operation instruction to the beamformer integrated circuit 10 or the RF front-end 5. Both the command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 16 bits.

[0037] The digital circuit unit 11 includes a memory 13, which is a memory area for storing beam tables used for beamforming. The beam table is a lookup table that stores multiple combinations of phase shift amount setting values ​​and intensity setting values, which are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (a beam table with 2048 items) with 2048 combinations of phase shift amount setting values ​​and intensity setting values ​​is stored in the memory 13.

[0038] Memory 13 is implemented using, for example, SRAM (Static Random Access Memory). While it is preferable that memory 13 be implemented using SRAM, it may also be implemented using registers, DRAM (Dynamic Random Access Memory), flash memory, or ROM (Read Only Memory).

[0039] The analog circuit section 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit section 11, the analog circuit section 12 adjusts the phase and intensity of the RF signals transmitted and received by the antenna element 21 connected to the RF front end 5.

[0040] The analog circuit section 12 is connected to the analog circuit 7 via an RF signal coupler / splitter 8. The RF signal coupler / splitter 8 distributes the RF signal output from the analog circuit 7 to the analog circuit sections 12 provided in each of the RF front ends 5A to 5P. The RF signal coupler / splitter 8 also combines the RF signals output from the analog circuit sections 12 provided in each of the RF front ends 5A to 5P and outputs them to the analog circuit 7.

[0041] As shown in Figure 2, the analog circuit section 12 includes a phase shifter (PS) 61, a changeover switch (SW) 62, a variable gain amplifier (VGA) 63, a phase inverter (PI) 64, a power amplifier (PA) 65, a changeover switch (SW) 66, a low-noise amplifier (LNA) 67, a variable gain amplifier (VGA) 68, a phase inverter (PI) 69, and a power detection circuit (PD) 70.

[0042] The variable gain amplifier 63, the phase inverter 64, and the power amplifier 65 are located on the transmission path R1, while the low-noise amplifier 67, the variable gain amplifier 68, and the phase inverter 69 are located on the reception path R2. The transmission path R1 is the path through which the RF signal (high-frequency signal) output to the antenna element 21 passes, and the reception path R2 is the path through which the RF signal (high-frequency signal) input from the antenna element 21 passes. The changeover switches 62 and 66 switch between connecting the transmission path R1 or the reception path R2 between the phase shifter 61 and the antenna element 21 at specified time intervals. This allows the phased array antenna module 1 to transmit and receive high-frequency signals as a time-division multiplexing system.

[0043] The phase shifter 61 adjusts the phase shift amount of the RF signal passing through the transmission path R1 or the RF signal passing through the reception path R2 according to the phase shift amount setting value of the beam table read from the memory 13 of the digital circuit unit 11. In other words, the phase shifter 61 is provided in common to both the transmission path R1 and the reception path R2. Alternatively, the phase shifter 61 common to both the transmission path R1 and the reception path R2 may be omitted, and a separate phase shifter may be provided for each of the transmission path R1 and the reception path R2.

[0044] The variable gain amplifier 63 amplifies the RF signal passing through the transmission path R1 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 64 inverts the phase of the RF signal passing through the transmission path R1 according to the phase shift amount setting value of the beamtable read from the memory 13. The power amplifier 65 amplifies the RF signal passing through the transmission path R1 at a predetermined amplification factor. By adjusting the phase shift amount and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0045] The low-noise amplifier 67 amplifies the RF signal output from the selector switch 66 at a predetermined amplification factor. The variable-gain amplifier 68 amplifies the RF signal passing through the receiving path R2 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 69 inverts the phase of the RF signal passing through the receiving path R2 according to the phase shift amount setting value of the beamtable read from the memory 13. By adjusting the phase shift amount and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0046] The power detection circuit 70 detects the power of the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, and outputs a power detection signal DT (digital signal) indicating the detection result. Specifically, the power detection circuit 70 detects the power of one of the RF signals branched by the brancher BR provided in the transmission path R1, and outputs a power detection signal DT indicating the detection result. The power detection signal DT is a signal that becomes either "H (high)" level or "L (low)" level depending on the magnitude of the detected RF signal power. The power detection signal DT is input to the digital circuit section 11 in the RF front end 5.

[0047] Figure 3 shows the connection relationship between the digital circuit section and the analog circuit section provided at the RF front end of the beamformer integrated circuit according to the first embodiment of the present invention. As shown in Figure 3, the phase shifter 61, variable gain amplifiers 63, 68, and phase inverters 64, 69 provided in the analog circuit section 12 are controlled according to the contents of the beam table stored in the memory 13. In contrast, the changeover switches 62, 66, power amplifier 65, and low-noise amplifier 67 provided in the analog circuit section 12 are controlled by logic circuits such as registers (not shown) provided in the digital circuit section 11. The power detection signal DT output from the power detection circuit 70 is input to the digital circuit section 11.

[0048] The unpacking circuit 14 unpacks the bit sequence of the phase shift amount setting value read from the memory 13 of the beam table into a bit sequence of a control value (phase shift control value) for controlling the phase shifter 61. The phase shift amount setting value stored in the beam table is, for example, 7 bits, and the intensity setting value is, for example, 5 bits. The unpacking circuit 14 unpacks 6 bits of the 7-bit phase shift amount setting value into a 52-bit control value bit sequence. The remaining 1 bit of the phase shift amount setting value is used to control the phase inverters 64 and 69. The number of bits in the phase shift amount setting value is set according to the resolution of the phase shift amount, and the number of bits in the control value is set according to the number of division units constituting the phase shifter 61.

[0049] Figure 4 shows an example of the configuration of an abnormality detection system that detects an abnormality in output power using a power detection signal output from a power detection circuit in the first embodiment of the present invention. The abnormality detection system shown in Figure 4 comprises a memory 13, registers 15 and 17, and an abnormality detection circuit 16 (abnormality detection circuit) provided in the digital circuit section 11.

[0050] As described above, memory 13 stores a beam table containing amplification factor setting values ​​that define the amplification factor of the variable gain amplifier 63. Register 15 holds amplification factor setting values ​​that define the amplification factor of the power amplifier 65. The amplification factor setting values ​​held in register 15 can be rewritten based on instructions from the control device 50. In other words, the anomaly detection system shown in Figure 4 can change the amplification factor of the power amplifier 65 as appropriate, and the amplification factor of the RF signal passing through the transmission path R1 of the analog circuit unit 12 is defined by the amplification factor setting values ​​read from memory 13 and the amplification factor setting values ​​held in register 15. Hereinafter, the amplification factor setting value that defines the amplification factor of the RF signal passing through the transmission path R1 of the analog circuit unit 12 will be referred to as the "transmission signal amplification factor setting value".

[0051] Register 17 stores the high-power setting reference value RH and the low-power setting reference value RL, which are used to detect whether or not there is an abnormality in the output power of the power amplifier 65. The high-power setting reference value RH and the low-power setting reference value RL are reference values ​​set relative to the transmission signal amplification factor setting value. The high-power setting reference value RH and the low-power setting reference value RL held in register 17 can be rewritten based on instructions from the control device 50.

[0052] Specifically, the high-power setting reference value RH is a reference value used to determine whether the transmission signal amplification factor setting value causes the output power of the power amplifier 65 to be greater than a predetermined first power (high output). The low-power setting reference value RL is a reference value used to determine whether the transmission signal amplification factor setting value causes the output power of the power amplifier 65 to be less than a predetermined second power (low output).

[0053] The high-power setting reference value RH and the low-power setting reference value RL are set such that the high-power setting reference value RH is greater than the low-power setting reference value RL within the range in which the output power of the power amplifier 65 can change. At this time, the power detection signal DT is set so that a level switch occurs when the amplification factor setting value is between the high-power setting reference value RH and the low-power setting reference value RL.

[0054] The abnormality detection circuit 16 detects whether there is an abnormality in the RF signal (output power of the power amplifier 65) amplified by the power amplifier 65 and supplied to the antenna element 21, based on the transmission signal amplification factor setting value and the power detection signal DT output from the power detection circuit 70. When detecting whether there is an abnormality in the output power of the power amplifier 65, the abnormality detection circuit 16 uses the high-power setting reference value RH and the low-power setting reference value RL stored in the register 17.

[0055] The abnormality detection circuit 16 outputs a low-power abnormality detection signal AL if the transmission signal amplification factor setting value is greater than the high-power setting reference value RH and the power detection signal DT is at the "L" level. In other words, the abnormality detection circuit 16 detects an abnormality and outputs a low-power abnormality detection signal AL at the "H" level if the power detected by the power detection circuit 70 is low, even though the transmission signal amplification factor setting value indicates a high output.

[0056] The anomaly detection circuit 16 outputs a high-power anomaly detection signal AH if the transmission signal amplification factor setting value is smaller than the low-power setting reference value RL and the power detection signal DT is at the "H" level. In other words, the anomaly detection circuit 16 detects an anomaly if the power detected by the power detection circuit 70 is high, even though the transmission signal amplification factor setting value is a value that indicates low power, and outputs a high-power anomaly detection signal AH at the "H" level.

[0057] Furthermore, if the transmission signal amplification factor setting is smaller than the high-power setting reference value RH and larger than the low-power setting reference value RL, the anomaly detection circuit 16 will not output the low-power anomaly detection signal AL and the high-power anomaly detection signal AH, regardless of the level of the power detection signal DT. In other words, the anomaly detection circuit 16 will not detect an anomaly in output power because the transmission signal amplification factor setting is between the value indicating high power and the value indicating low power. In other words, the low-power anomaly detection signal AL and the high-power anomaly detection signal AH will be at the "L" level.

[0058] The detection results of the anomaly detection circuit 16 (high-power anomaly detection signal AH and low-power anomaly detection signal AL) are stored in a register (not shown) provided in the digital circuit unit 11. The control device 50 sends a communication message to the digital circuit unit 11 requesting acquisition of the results and retrieves the detection results of the anomaly detection circuit 16 stored in the register.

[0059] Furthermore, the beamformer integrated circuit 10 is provided with an abnormality detection system for detecting protocol abnormalities, in addition to the abnormality detection system for detecting output power abnormalities shown in Figure 4. This abnormality detection system includes, for example, a protocol abnormality detection circuit (abnormality detection circuit) not shown, provided in the digital circuit 6 and the digital circuit section 11 of the RF front end 5. The protocol abnormality detection circuit detects communication protocol errors (communication message protocol abnormalities) between the control device 50 and the digital circuit 6, and between the control device 50 and the digital circuit section 11 of the RF front end 5.

[0060] The detection result of the protocol anomaly detection circuit provided in the digital circuit 6 is stored in a register (not shown) provided in the digital circuit 6. The detection result of the protocol anomaly detection circuit provided in the digital circuit section 11 of the RF front end 5 is stored in a register (not shown) provided in the digital circuit section 11 of the RF front end 5. The control device 50 sends a communication message to the digital circuit 6 or the digital circuit section 11 of the RF front end 5 to request acquisition and obtain the detection result of the protocol anomaly detection circuit stored in each register.

[0061] <Memory map of registers> Figure 5 shows an example of a register memory map provided in a beamformer integrated circuit according to the first embodiment of the present invention. In this embodiment, the address of the register memory map is 8 bits, and values ​​from "0" to "255" can be specified. The storage capacity of each register is, for example, up to 16 bits. In this embodiment, the 8-bit address space is shared by the register (storage area) provided in the frequency conversion integrated circuit 30, the register (storage area) provided in the digital circuit 6 of the beamformer integrated circuit 10, and the register (storage area) provided in the digital circuit section 11 of the RF front end 5.

[0062] A register is a memory area that stores information by writing to it by specifying an address, and retrieves the stored information by reading it by specifying an address. Furthermore, information may be stored in or updated in registers by logic circuits provided in the digital circuit 6 of the beamformer integrated circuit 10, or in the digital circuit section 11 of the RF front-end 5.

[0063] In the example shown in Figure 5, the registers to which addresses K and K+1 are assigned are registers located in the digital circuit 6 of the beamformer integrated circuit 10. The registers to which addresses L, L+1, M, M+1, N, and N+1 are assigned are registers located in the digital circuit section 11 of the RF front-end 5.

[0064] In other words, when a write or read operation is instructed by specifying address K or address K+1, the write or read operation is performed on a register provided in the digital circuit 6 of the beamformer integrated circuit 10. Furthermore, when a write or read operation is instructed by specifying address L, address L+1, address M, address M+1, address N, or address N+1, the write or read operation is performed on a register provided in the digital circuit section 11 of the RF front-end 5, which has been selected separately in advance. The RF front-end 5 is selected, for example, using a register (not shown) provided in the digital circuit 6 of the beamformer integrated circuit 10.

[0065] Although not shown in Figure 5, a certain address range is also assigned to the registers provided in the frequency conversion integrated circuit 30. When a write or read operation is instructed by specifying an address within this range, the registers provided in the frequency conversion integrated circuit 30 are written to or read from.

[0066] The register assigned to address K (detection result storage area, first storage area) stores information (third information) indicating the latest detection result, which shows whether or not an anomaly has been detected in the anomaly detection circuit provided in the digital circuit 6 of the beamformer integrated circuit 10. In addition, the register assigned to address K+1 (detection result storage area, second storage area) stores information (fourth information) indicating the detection history of anomalies detected by the anomaly detection circuit provided in the digital circuit 6 of the beamformer integrated circuit 10.

[0067] The register assigned to address L (detection result storage area, first storage area) stores information (third information) indicating the latest detection result, which shows whether or not an anomaly has been detected by the anomaly detection circuit provided in the digital circuit section 11 of the RF front end 5. In addition, the register assigned to address L+1 (detection result storage area, second storage area) stores information (fourth information) indicating the detection history of anomalies detected by the anomaly detection circuit provided in the digital circuit section 11 of the RF front end 5.

[0068] The register assigned to address M stores the amplification factor setting value that defines the amplification factor of the power amplifier 65 provided in the RF front end 5. The register assigned to address M+1 stores the amplification factor setting value that defines the amplification factor of the low-noise amplifier 67 provided in the RF front end 5. The register assigned to address N stores the high-output setting reference value RH. The register assigned to address N+1 stores the low-output setting reference value RL. Note that the register assigned to address M is register 15 shown in Figure 4, and the registers assigned to addresses N and N+1 are register 17 shown in Figure 4.

[0069] The information stored in the register assigned to address K and the register assigned to address K+1 consists of multiple bits. For example, it includes a bit indicating whether or not an abnormality was detected in the RF front end 5 (hereinafter referred to as the "RFFE abnormality detection bit"), a bit indicating whether or not a communication protocol error was detected in the digital circuit 6 (hereinafter referred to as the "first communication error detection bit"), and so on. The information stored in the register assigned to address K and the register assigned to address K+1 is updated bit by bit according to the abnormality detected by the beamformer integrated circuit 10.

[0070] The information stored in the register assigned to address L and the register assigned to address L+1 also consists of multiple bits. For example, these include a bit indicating whether or not an abnormality was detected in the RF front end 5, a bit indicating whether or not a high-power abnormality was detected (hereinafter referred to as the "high-power abnormality detection bit"), a bit indicating whether or not a low-power abnormality was detected (hereinafter referred to as the "low-power abnormality detection bit"), and a bit indicating whether or not a communication protocol error was detected in the digital circuit section 11 of the RF front end 5 (hereinafter referred to as the "second communication error detection bit"). The information stored in the register assigned to address L and the register assigned to address L+1 is updated bit by bit according to the abnormality detected in the RF front end 5.

[0071] When the beamformer integrated circuit 10 receives a communication message (hereinafter referred to as a "read instruction communication message") (first communication message) that specifies an address and instructs it to read the information stored in the register to which that address is assigned, it reads the information (first information) stored in the register to which that address is assigned. For example, when the beamformer integrated circuit 10 receives a read instruction communication message specifying address K, it reads the information stored in the register to which address K is assigned.

[0072] Furthermore, the beamformer integrated circuit 10 sets the value of information indicating whether or not an abnormality has occurred (hereinafter referred to as "abnormal state presence / absence information") (second information) based on the information stored in the register to which address K+1 is assigned. For example, if the value of the information stored in the register to which address K+1 is assigned is not "0", the beamformer integrated circuit 10 sets the value of the abnormal state presence / absence information to "1". In other words, the beamformer integrated circuit 10 sets the value of the abnormal state presence / absence information to "1" when information indicating the history of abnormality detection (fourth information) is stored in the register to which address K+1 is assigned. Note that if the value of the information stored in the register to which address K+1 is assigned is "0", the beamformer integrated circuit 10 sets the value of the abnormal state presence / absence information to "0".

[0073] Alternatively, the beamformer integrated circuit 10 sets the value of abnormal state information (second information) based on the information stored in the register assigned to address K+1 and the register assigned to address L+1. For example, if the value of the information stored in the register assigned to address K+1 is not "0", the beamformer integrated circuit 10 sets the value of abnormal state information in the beamformer integrated circuit 10 (hereinafter referred to as "BFIC abnormal state information") to "1". Also, if the value of the information stored in the register assigned to address L+1 is not "0", the beamformer integrated circuit 10 sets the value of abnormal state information in the RF front end 5 (hereinafter referred to as "RFFE abnormal state information") to "1".

[0074] In other words, the beamformer integrated circuit 10 sets the value of the BFIC abnormal state presence / absence information to "1" if the register assigned to address K+1 stores information indicating the history of abnormality detection (fourth information). Also, the beamformer integrated circuit 10 sets the value of the RFFE abnormal state presence / absence information to "1" if the register assigned to address L+1 stores information indicating the history of abnormality detection (fourth information).

[0075] Furthermore, if the value of the information stored in the register assigned to address K+1 is "0", the beamformer integrated circuit 10 sets the value of the BFIC abnormal state presence / absence information to "0". Also, if the value of the information stored in the register assigned to address L+1 is "0", the beamformer integrated circuit 10 sets the value of the RFFE abnormal state presence / absence information to "0".

[0076] The beamformer integrated circuit 10 then transmits a communication message (hereinafter referred to as the "read reply communication message") (second communication message) that includes the read information (first information) and information on whether or not there is an abnormal state (second information). For example, if a read instruction communication message (first communication message) is transmitted from the control device 50, the beamformer integrated circuit 10 transmits a read reply communication message (second communication message) that includes the read information (first information) and information on whether or not there is an abnormal state (second information) to the control device 50.

[0077] <Actions taken when an anomaly is detected> Next, we will describe the operation when an abnormality is detected in the abnormality detection circuit provided in the digital circuit 6 of the beamformer integrated circuit 10, or in the abnormality detection circuit provided in the digital circuit section 11 of the RF front end 5. Below, we will first describe the operation when an output abnormality of the power amplifier 65 is detected in the abnormality detection circuit provided in the digital circuit section 11 of the RF front end 5 (operation when an output abnormality is detected). Next, we will describe the operation when a communication protocol error is detected in the abnormality detection circuit provided in the digital circuit 6, or in the digital circuit section 11 of the RF front end 5 (operation when a communication error is detected). Following that, we will describe the operation when the contents of the register are erased (reset operation).

[0078] Operation upon detecting an output anomaly In the anomaly detection system shown in Figure 4, when a high-power anomaly in the output power of the power amplifier 65 is detected, a high-power anomaly detection signal AH is output from the anomaly detection circuit 16 of the anomaly detection system. Then, for example, a logic circuit provided in the digital circuit section 11 of the RF front end 5 sets the value of the high-power anomaly detection bit to "1" in the register assigned to address L. Similarly, in the register assigned to address L+1, the value of the high-power anomaly detection bit is also set to "1".

[0079] If no high-power anomaly is detected, only the value of the high-power anomaly detection bit in the register assigned to address L will be set to, for example, "0". The value of the high-power anomaly detection bit in the register assigned to address L+1 will be retained. In other words, the step of setting the value of the high-power anomaly detection bit to "0" in the register assigned to address L+1 will not be performed.

[0080] In the anomaly detection system shown in Figure 4, when a low-power anomaly in the output power of the power amplifier 65 is detected, a low-power anomaly detection signal AL is output from the anomaly detection circuit 16 of the anomaly detection system. Then, for example, a logic circuit provided in the digital circuit section 11 of the RF front end 5 sets the value of the low-power anomaly detection bit to "1" in the register to which address L is assigned. Similarly, in the register to which address L+1 is assigned, the value of the low-power anomaly detection bit is also set to "1".

[0081] If no low-power anomaly is detected, only the value of the low-power anomaly detection bit in the register assigned to address L will be set to, for example, "0". The value of the low-power anomaly detection bit in the register assigned to address L+1 will be retained. In other words, the step of setting the value of the low-power anomaly detection bit to "0" in the register assigned to address L+1 will not be performed.

[0082] Actions taken when a communication error is detected. Suppose a communication protocol error is detected by a protocol anomaly detection circuit (not shown) provided in digital circuit 6. Then, for example, the logic circuit provided in digital circuit 6 sets the value of the first communication error detection bit to "1" in the register to which address K is assigned. Similarly, in the register to which address K+1 is assigned, the value of the first communication error detection bit is also set to "1".

[0083] Furthermore, if no communication protocol error is detected by the protocol anomaly detection circuit (not shown) provided in the digital circuit 6, only the value of the first communication error detection bit in the register assigned to address K will be set to, for example, "0". The value of the first communication error detection bit in the register assigned to address K+1 will be retained. In other words, the step of setting the value of the first communication error detection bit to "0" in the register assigned to address K+1 will not be performed.

[0084] Suppose a communication protocol error is detected by a protocol anomaly detection circuit (not shown) provided in the digital circuit section 11 of the RF front end 5. Then, for example, a logic circuit provided in the digital circuit section 11 of the RF front end 5 sets the value of the second communication error detection bit to "1" in the register to which address L is assigned. Similarly, in the register to which address L+1 is assigned, the value of the second communication error detection bit is also set to "1".

[0085] Furthermore, if no communication protocol error is detected by the protocol anomaly detection circuit (not shown) provided in the digital circuit section 11 of the RF front-end 5, only the value of the second communication error detection bit in the register assigned to address L is set to, for example, "0". The value of the second communication error detection bit in the register assigned to address L+1 is retained. In other words, the step of setting the value of the second communication error detection bit to "0" in the register assigned to address L+1 is not performed.

[0086] Here, if the value of any bit in the register to which address L is assigned is "1", then the value of the RFFE anomaly detection bit in the register to which address K is assigned and the register to which address K+1 is assigned will be set to, for example, "1". Note that the case where the value of any bit in the register to which address L is assigned is "1" means that the value of the information stored in the register to which address L is assigned is not "0".

[0087] In contrast, if the value of all bits in the register to which address L is assigned is "0", then only the value of the RFFE anomaly detection bit in the register to which address K is assigned will be set to "0", for example. The value of the RFFE anomaly detection bit in the register to which address K+1 is assigned will be retained. Note that the case where the value of all bits in the register to which address L is assigned is "0" means that the value of the information stored in the register to which address L is assigned is "0".

[0088] Thus, the register assigned to address K+1 stores information indicating the detection history of anomalies detected by the beamformer integrated circuit 10 using multiple bits, and if there is a detection history, the value of the corresponding bit is, for example, "1". Furthermore, if an anomaly is detected by an anomaly detection circuit provided in the digital circuit section 11 of any RF front end 5, the value of a specific bit in both the register assigned to address L+1 and the register assigned to address K+1 becomes "1". As a result, by referring only to the register assigned to address K+1, it is possible to determine whether or not there is a detection history of an anomaly detected by the beamformer integrated circuit 10.

[0089] Reset operation The value stored in the register assigned to address K+1 is set to "0" (reset) during the register's initialization operation, or when the digital circuit 6 of the beamformer integrated circuit 10 receives a communication message instructing it to erase the contents of address K+1. Similarly, the value stored in the register assigned to address L+1 is set to "0" (reset) during the register's initialization operation, or when the digital circuit 6 of the beamformer integrated circuit 10 receives a communication message instructing it to erase the contents of address L+1.

[0090] When the values ​​stored in the register assigned to address K+1 and the register assigned to address L+1 are set to "0", it means that the registers are set to a state where there is no history of previously detected anomalies. In this way, when the registers are initialized or when a communication message to erase the history is received, the registers are set to a state where there is no history of previously detected anomalies. For example, when the wireless communication device DV is in continuous operation, it is possible to repeatedly acquire and erase the history of anomalies as needed.

[0091] <Method for obtaining abnormal status> Next, a method for acquiring abnormal conditions according to the first embodiment of the present invention will be described. In the method for acquiring abnormal conditions according to this embodiment, for example, the following steps 1 to 5 are repeatedly performed at a predetermined period or irregularly.

[0092] • Step 1: Sending a read instruction message. The control device 50 sends a read instruction communication message (first communication message) to the beamformer integrated circuit 10, specifying an address and instructing it to read the information stored in the register to which that address is assigned.

[0093] Step 2: Sending the read-back reply message. When the beamformer integrated circuit 10 receives a read instruction communication message from the control device 50, it sends a read reply communication message (second communication message) to the control device 50, which includes information stored in the area specified by the address included in the read instruction communication message (first information) and information on whether or not there is an abnormal state (second information).

[0094] • Step 3: Determine whether or not an abnormality has occurred. The control device 50 determines whether or not an abnormality has occurred based on the abnormality status information contained in the read-back communication message transmitted from the beamformer integrated circuit 10.

[0095] • Step 4: Send a read instruction communication message that instructs the system to read information indicating an abnormal condition. If the control device 50 determines that an abnormality has occurred, it sends a read instruction communication message (third communication message) to the beamformer integrated circuit 10, specifying an address and instructing it to read the information indicating the abnormal state stored in the register to which that address is assigned.

[0096] • Step 5: Send a read-back communication message containing the read-out information and information on whether or not there is an abnormal condition. When the beamformer integrated circuit 10 receives a read instruction communication message from the control device 50 in the fourth step, it sends a read reply communication message (second communication message) to the control device 50, which includes information indicating an abnormal state (first information) and information indicating whether or not an abnormal state exists (second information) stored in the area specified by the address included in the read instruction communication message.

[0097] Figure 6 shows an example of a read instruction communication message and a read reply communication message transmitted and received between a control device and a beamformer integrated circuit in a first embodiment of the present invention. Figure 6(a) shows a read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10. Figures 6(b) and (c) show examples of read reply communication messages transmitted from the beamformer integrated circuit 10 to the control device 50.

[0098] As shown in Figure 6(a), the read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10 includes additional information and a command. The additional information includes, for example, a start bit, information indicating that it is a read instruction, and target IC selection information. The target IC selection information is IC address information that selects and specifies the frequency conversion integrated circuit 30 or beamformer integrated circuit 10 to be communicated with by the control device 50 within the phased array antenna module 1. The command in the read instruction communication message specifies the address of the register to be read.

[0099] As shown in Figures 6(b) and 6(c), the read-back communication message transmitted from the beamformer integrated circuit 10 to the control device 50 includes additional information and data. In the example shown in Figure 6(b), the additional information consists only of abnormal condition information, but in the example shown in Figure 6(c), it includes BFIC abnormal condition information and RFFE abnormal condition information. The abnormal condition information, BFIC abnormal condition information, and RFFE abnormal condition information included in the additional information are each 1-bit pieces of information. A value of "1" in this information means that an abnormal condition has occurred, and a value of "0" means that an abnormal condition has not occurred.

[0100] The data is read from the register to which the address included in the read instruction communication message is assigned. Thus, in this embodiment, the read reply communication message includes, in addition to the data read based on the read instruction communication message, additional information such as whether or not there is an abnormal state, or whether or not there is a BFIC abnormal state and whether or not there is an RFFE abnormal state. For this reason, the control device 50 can detect the presence or absence of an abnormal state each time it acquires a read reply communication message.

[0101] The read-back message shown in Figure 6(b) is transmitted, for example, when the address specified in the read-instruction message is the address of a register provided in the digital circuit 6 of the beamformer integrated circuit 10. The read-back message shown in Figure 6(c) is transmitted, for example, when the address specified in the read-instruction message is the address of a register provided in the digital circuit section 11 of the RF front-end 5.

[0102] Furthermore, the abnormal state presence / absence information, which is additional information to the read-reply communication message shown in Figure 6(b), is set to "1" if the value of the information stored in the register assigned to address K+1, shown in Figure 5, is not "0," as previously mentioned. Similarly, the BFIC abnormal state presence / absence information, which is additional information to the read-reply communication message shown in Figure 6(c), is set to "1" if the value of the information stored in the register assigned to address K+1, shown in Figure 5, is not "0," just like the abnormal state presence / absence information. The RFFE abnormal state presence / absence information is set to "1" if the value of the information stored in the register assigned to address L+1, shown in Figure 5, is not "0."

[0103] Figure 7 shows an example of a communication message when information stored in a register to which address K is assigned is read in a first embodiment of the present invention. Figure 7(a) shows a read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10. Figure 7(b) shows an example of a read reply communication message transmitted from the beamformer integrated circuit 10 to the control device 50. The read instruction communication message shown in Figure 7(a) is transmitted, for example, in the fourth step described above if an abnormality is determined in the third step described above. The read reply communication message shown in Figure 7(b) is transmitted, for example, in the fifth step described above.

[0104] When reading information stored in the register to which address K is assigned, the address K of the register to be read is specified as the command in the read instruction communication message, as shown in Figure 7(a). Also, as shown in Figure 7(b), the latest detection result indicating whether or not there is an abnormality in the beamformer integrated circuit 10 (third information) is stored as data in the read reply communication message (see Figure 5). Note that even when reading information stored in the register to which address K is assigned, the read reply communication message also includes information on whether or not there is an abnormal state.

[0105] Figure 8 shows an example of a communication message when information stored in a register assigned address K+1 is read in a first embodiment of the present invention. Figure 8(a) shows a read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10. Figure 8(b) shows an example of a read reply communication message transmitted from the beamformer integrated circuit 10 to the control device 50. The read instruction communication message shown in Figure 8(a) is transmitted, for example, in the fourth step described above if an abnormality is determined in the third step described above. The read reply communication message shown in Figure 8(b) is transmitted, for example, in the fifth step described above.

[0106] When reading information stored in the register assigned to address K+1, the address K+1 of the register to be read is specified as the command in the read instruction communication message, as shown in Figure 8(a). Also, as shown in Figure 8(b), information indicating the detection history of anomalies in the beamformer integrated circuit 10 (fourth information) is stored as data in the read reply communication message (see Figure 5). Note that when reading information stored in the register assigned to address K+1, the read reply communication message also includes information on whether or not an anomaly is present.

[0107] Figure 9 shows an example of a communication message when information stored in a register to which address L is assigned is read out in a first embodiment of the present invention. Figure 9(a) shows a read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10. Figure 9(b) shows an example of a read reply communication message transmitted from the beamformer integrated circuit 10 to the control device 50. The read instruction communication message shown in Figure 9(a) is transmitted, for example, in the fourth step described above if an abnormality is determined in the third step described above. The read reply communication message shown in Figure 9(b) is transmitted, for example, in the fifth step described above.

[0108] When reading information stored in the register assigned to address L, the address L of the register to be read is specified as the command in the read instruction communication message, as shown in Figure 9(a). Also, as shown in Figure 9(b), the latest detection result indicating whether or not there is an abnormality in the RF front end 5 (third information) is stored as data in the read reply communication message (see Figure 5). Note that even when reading information stored in the register assigned to address L, the read reply communication message also includes information on whether or not there is an abnormality in the BFIC and RFFE.

[0109] Figure 10 shows an example of a communication message when information stored in a register assigned address L+1 is read in a first embodiment of the present invention. Figure 10(a) shows a read instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10. Figure 10(b) shows an example of a read reply communication message transmitted from the beamformer integrated circuit 10 to the control device 50. The read instruction communication message shown in Figure 10(a) is transmitted, for example, in the fourth step described above if an abnormality is determined in the third step described above. The read reply communication message shown in Figure 10(b) is transmitted, for example, in the fifth step described above.

[0110] When reading information stored in the register assigned to address L+1, the address L+1 of the register to be read is specified as the command in the read instruction communication message, as shown in Figure 10(a). Also, as shown in Figure 10(b), information indicating the detection history of anomalies in the RF front end 5 (fourth information) is stored as data in the read reply communication message (see Figure 5). Furthermore, when reading information stored in the register assigned to address L+1, the read reply communication message also includes information on whether or not there is a BFIC anomaly and information on whether or not there is an RFFE anomaly.

[0111] Figure 11 shows an example of a write instruction message sent from the control device to the beamformer integrated circuit. A write instruction message is a message that specifies an address and instructs the writing of information to the register to which that address is assigned. As shown in Figure 11, the write instruction message sent from the control device 50 to the beamformer integrated circuit 10 includes data in addition to additional information and commands. Additional information includes, for example, a start bit, information indicating that it is a write instruction, and target IC selection information. The command in the write instruction message specifies the address of the register to be written to. The data is the information to be written to the register.

[0112] The control device 50 sends the write instruction communication message shown in Figure 11 to the beamformer integrated circuit 10, causing it to write the specified data to the register assigned to the specified address. For example, it causes the beamformer integrated circuit 10 to write the amplification factor setting value that defines the amplification factor of the power amplifier 65 to the register assigned to address M, and the beamformer integrated circuit 10 to write the amplification factor setting value that defines the amplification factor of the low-noise amplifier 67 to the register assigned to address M+1.

[0113] When the control device 50 wants to write an amplification factor setting value that defines the amplification factor of the power amplifier 65, it sends a write instruction communication message to the beamformer integrated circuit 10 specifying address M as the command and the amplification factor setting value to be written as data. When the control device 50 wants to write an amplification factor setting value that defines the amplification factor of the low-noise amplifier 67, it sends a write instruction communication message to the beamformer integrated circuit 10 specifying address M+1 as the command and the amplification factor setting value to be written as data. In this way, each element component of the analog circuit section 12 of the RF front end 5 is controlled by setting the values ​​of the registers provided in the digital circuit section 11 of the RF front end 5.

[0114] Figure 12 shows an example of an operation instruction communication message transmitted from the control device to the beamformer integrated circuit. An operation instruction communication message is a communication message that instructs the execution of a specific operation. As shown in Figure 12, the operation instruction communication message transmitted from the control device 50 to the beamformer integrated circuit 10 includes data in addition to additional information and commands, similar to a write instruction communication message. The additional information, like that of a write instruction communication message, includes, for example, a start bit, information indicating that it is a write instruction, and target IC selection information. The command of the operation instruction communication message is the operation instruction command. The data specifies the operation instruction parameters.

[0115] The control device 50 transmits an operation instruction command, for example, when it instructs the control of each element component in the analog circuit section 12 of the RF front end 5 to reflect the information of the operation setting values ​​stored in the registers provided in the digital circuit section 11 of the RF front end 5. Alternatively, the control device 50 transmits an operation instruction command when it gives instructions related to beamforming operation.

[0116] As described above, this embodiment includes an anomaly detection circuit 16 for detecting an anomaly in the output power of the power amplifier 65, and a protocol anomaly detection circuit for detecting communication protocol errors. Information indicating the detection history of anomalies detected by these anomaly detection circuits is stored in a register assigned to address K+1 or a register assigned to address L+1. When the beamformer integrated circuit 10 receives a read instruction communication message transmitted from the control device 50, it transmits a read reply communication message to the control device 50 that includes the information stored in the area specified by the address contained in the read instruction communication message, as well as information on whether or not an anomaly exists. As a result, the control device 50 can detect whether or not an anomaly exists each time it acquires a read reply communication message, and can detect the occurrence of an anomaly early without requiring a dedicated wired communication circuit.

[0117] Furthermore, in this embodiment, when the control device 50 detects the occurrence of an abnormality based on the abnormality status information contained in the read-back communication message, it transmits the read-back instruction communication message shown in Figure 7(a) or Figure 9(a). By receiving the read-back communication message shown in Figure 7(b) or Figure 9(b), the control device 50 can obtain information indicating the latest detection result showing whether or not there is an abnormality in the beamformer integrated circuit 10 or information indicating the latest detection result showing whether or not there is an abnormality in the RF front-end 5. This allows the control device 50 to know whether or not the abnormal condition is continuing.

[0118] Alternatively, in this embodiment, when the control device 50 detects the occurrence of an abnormality based on the abnormality status information contained in the read-back communication message, it transmits the read-back instruction communication message shown in Figure 8(a) or Figure 10(a). By receiving the read-back communication message shown in Figure 8(b) or Figure 10(b), the control device 50 can obtain information indicating the abnormality detection history in the beamformer integrated circuit 10 or information indicating the abnormality detection history in the RF front-end 5. This allows the control device 50 to know what kind of abnormalities have occurred in the past.

[0119] Furthermore, in this embodiment, by comparing the information obtained from the read-back communication message shown in Figure 7(b) or Figure 9(b) with the information obtained from the read-back communication message shown in Figure 8(b) or Figure 10(b), the control device 50 can determine whether an abnormality with a detected history is still in an abnormal state or has been resolved.

[0120] Thus, in this embodiment, even in analog integrated circuits that do not include a processor or the like, such as the beamformer integrated circuit 10, and only include simple logic circuits, it is possible to detect the occurrence of an abnormal state at an early stage.

[0121] [Second Embodiment] Figure 13 shows an example of a memory map of registers provided in a beamformer integrated circuit according to a second embodiment of the present invention. Note that this embodiment differs from the first embodiment only in the configuration of the memory map; the configuration of the wireless communication device DV, including the beamformer integrated circuit 10, is substantially the same as that of the first embodiment. Therefore, the following description will mainly focus on matters related to the register memory map.

[0122] <Memory map of registers> The beamformer integrated circuit 10 of this embodiment differs from the first embodiment in that it allows for the storage of multiple histories of information indicating the abnormal state (abnormal state number) detected by the abnormality detection circuit provided in the digital circuit 6 of the beamformer integrated circuit 10 in a register provided in the digital circuit 6. Furthermore, the beamformer integrated circuit 10 of this embodiment differs from the first embodiment in that it allows for the storage of multiple histories of information indicating the abnormal state (abnormal state number) detected by the abnormality detection circuit provided in the digital circuit section 11 of the RF front end 5 in a register provided in the digital circuit section 11 of the RF front end 5.

[0123] An abnormal state number is a number that indicates the details of the abnormality assigned to each abnormal state. For example, in the case of a communication protocol error, if the additional information specifies read operation but the target IC selection information specifies broadcast operation, abnormal state number 51 is assigned. Also, if the additional information specifies write operation and the target IC selection information is for a single beamformer integrated circuit 10 but the write target register address is for the frequency conversion integrated circuit 30, or if the target IC selection information is for the frequency conversion integrated circuit 30 but the write target register address is for the beamformer integrated circuit 10, abnormal state number 52 is assigned.

[0124] In the first embodiment, a value indicating the presence or absence of an anomaly was set in a specific bit (a bit corresponding to the detected anomaly) of the register assigned to address K and the register assigned to address K+1. The same applies to the register assigned to address L and the register assigned to address L+1. Therefore, in the first embodiment, it is possible to know whether or not an anomaly exists, but it is not possible to know the details of the anomaly state. In this embodiment, by storing a history of anomaly state numbers, it is possible to know the details of the anomaly state.

[0125] Specifically, as shown in Figure 13, the digital circuit 6 has P registers (third memory area) assigned addresses K+2 to K+P+1, where P records of abnormal state numbers (fifth information) related to abnormalities detected by the beamformer integrated circuit 10 can be stored. Similarly, the digital circuit section 11 of the RF front-end 5 has Q registers (third memory area) assigned addresses L+2 to L+Q+1, where Q records of abnormal state numbers (fifth information) related to abnormalities detected by the RF front-end 5 can be stored. P and Q may be the same number or different numbers.

[0126] In this embodiment, if an abnormality is detected in the beamformer integrated circuit 10, the value of a specific bit (a bit corresponding to the detected abnormality) in the register assigned to address K and the register assigned to address K+1 is set to, for example, "1", similar to the first embodiment. In addition, in this embodiment, an abnormality status number is stored in one of the registers assigned to addresses K+2 to K+P+1.

[0127] For example, a counter (not shown) provided in the digital circuit 6 is used to manage which of the P registers assigned addresses K+2 to K+P+1 contain the abnormal state number. Then, the new abnormal state number is stored in the register assigned to the address following the address indicated by the counter. If the abnormal state number has been stored up to the register assigned to address K+P+1, the counter is reset so that the next abnormal state number is stored in the register assigned to address K+2.

[0128] Here, only P abnormal state numbers can be stored. For this reason, the digital circuit 6 of the beamformer integrated circuit 10 may omit storing the abnormal state number information if the abnormal state number to be stored this time is the same as the abnormal state number stored last time.

[0129] Furthermore, in this embodiment, if an abnormality is detected in the RF front end 5, the value of a specific bit (a bit corresponding to the detected abnormality) in the register assigned to address L and the register assigned to address L+1 is set to, for example, "1", similar to the first embodiment. In addition, in this embodiment, an abnormality status number is stored in one of the registers assigned to addresses L+2 through L+Q+1.

[0130] For example, a counter (not shown) provided in the digital circuit section 11 of the RF front end 5 is used to manage which of the Q registers assigned to addresses L+2 to L+Q+1 currently stores an abnormal status number. Then, a new abnormal status number is stored in the register assigned to the address following the address indicated by the counter. If an abnormal status number has been stored up to the register assigned to address L+Q+1, the counter is reset so that the next abnormal status number is stored in the register assigned to address L+2.

[0131] Here, only Q abnormal state numbers can be stored. For this reason, the digital circuit section 11 of the RF front end 5 may omit storing the abnormal state number information if the abnormal state number to be stored this time is the same as the abnormal state number stored last time.

[0132] When the beamformer integrated circuit 10 receives a read instruction communication message (first communication message) specifying the address of a register (third memory area) where an abnormal state number is stored, it sends a read reply communication message containing the abnormal state number (fifth information) stored in the register identified by the address included in the read instruction communication message, and information on whether or not an abnormal state exists.

[0133] <Method for obtaining abnormal status> The method for obtaining the history of abnormal state numbers stored in P registers assigned addresses K+2 to K+P+1 is basically the same as the method for obtaining abnormal states described in the first embodiment. Similarly, the method for obtaining the history of abnormal state numbers stored in Q registers assigned addresses L+2 to L+Q+1 is also basically the same as the method for obtaining abnormal states described in the first embodiment.

[0134] In other words, if the control device 50 determines that an abnormality has occurred in the third step described above, it sends a read instruction communication message in the fourth step described above, specifying one of the addresses of the registers where the abnormality status number is stored. Then, in the fifth step described above, the beamformer integrated circuit 10 sends a read reply communication message containing the abnormality status number to the control device 50. In this way, the control device 50 can obtain the abnormality status number stored in the beamformer integrated circuit 10.

[0135] Here, the control device 50 repeatedly performs the fourth step described above while sequentially changing the specified address, and sequentially sends read instruction communication messages to the beamformer integrated circuit 10. As a result, the control device 50 can sequentially acquire the abnormal status numbers stored in the beamformer integrated circuit 10.

[0136] Specifically, the control device 50 manages which of the P registers assigned to addresses K+2 through K+P+1 have already acquired an abnormal status number, and then reads the register at the next address. When an abnormal status number has been acquired up to the register assigned to address K+P+1, the control device sets the address to be instructed next to address K+2.

[0137] Similarly, the control device 50 manages which of the Q registers assigned from address L+2 to address L+Q+1 have already acquired an abnormal status number, and then reads the register at the next address. When an abnormal status number has been acquired up to the register assigned to address L+Q+1, the control device 50 sets the address to be instructed next to address L+2.

[0138] Furthermore, information indicating which of the P registers assigned addresses K+2 to K+P+1 contain the abnormal state number is stored in a register (not shown) provided in the digital circuit 6. Similarly, information indicating which of the Q registers assigned addresses L+2 to L+Q+1 contain the abnormal state number is stored in a register (not shown) provided in the digital circuit section 11 of the RF front end 5. The control device 50 acquires the information stored in these registers and retrieves the abnormal state number up to the register assigned to the address identified by the acquired information.

[0139] In this way, the control device 50 can detect the details of the abnormal condition that occurred in more detail. Furthermore, by sequentially acquiring multiple abnormal condition numbers, the details of the abnormal condition that occurred can be obtained in chronological order.

[0140] As described above, the wireless communication device of this embodiment has basically the same configuration as the wireless communication device DV of the first embodiment. Therefore, in this embodiment as well as in the first embodiment, it is possible to detect the occurrence of an abnormal condition early without requiring a dedicated wired communication circuit, to know whether the abnormal condition is continuing or not, and to know what kind of abnormalities have occurred in the past.

[0141] In addition, in this embodiment, the history of information indicating the abnormal state (abnormal state number) (fifth information) detected by the beamformer integrated circuit 10 is stored in P registers (third region) assigned from address K+2 to address K+P+1, or Q registers (third region) assigned from address L+2 to address L+Q+1. When a read instruction communication message is received instructing the reading of the information stored in these registers, the beamformer integrated circuit 10 sends a read reply communication message (second communication message) that includes the abnormal state numbers stored in these registers. This makes it possible to detect the content of the abnormal state that has occurred in more detail.

[0142] Although an integrated circuit and an anomaly history management method according to embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be freely modified within the scope of the present invention. The phased array antenna module described in the above embodiments was for a time-division multiplexing system. However, the phased array antenna module of the present invention may also be for a frequency-division multiplexing system.

[0143] Furthermore, in the embodiments described above, an example was described in which one antenna element 21 and one RF front end 5 are connected in a one-to-one correspondence. However, in the present invention, two front ends may be connected to dual-polarization antenna elements, each having a connection terminal for horizontal polarization and a connection terminal for vertical polarization. [Explanation of symbols]

[0144] 10...Beamformer integrated circuit, 16...Anomaly detection circuit, 50...Control device, DV...Wireless communication device

Claims

1. An anomaly detection circuit that detects the presence or absence of an anomaly, A storage area including a detection result storage area for storing the detection result of the abnormality detection circuit, Equipped with, When a first communication message is received that specifies an address and instructs the reading of information stored in the storage area, a second communication message is transmitted that includes first information stored in the area of ​​the storage area specified by the address, and second information indicating whether or not an abnormality has occurred based on the detection result stored in the detection result storage area. Integrated circuit.

2. The aforementioned detection result storage area is A first storage area that stores third information indicating the latest detection result of the abnormality detection circuit, A second storage area is provided corresponding to the first storage area and stores a fourth piece of information indicating the detection history of an anomaly detected by the anomaly detection circuit, Includes, If the fourth information is stored in the second memory area, the second communication message containing the second information indicating an abnormality is transmitted. The integrated circuit according to claim 1.

3. The integrated circuit according to claim 2, which, upon receiving a first communication message that specifies the address of the first storage area and instructs the reading of information stored in the first storage area, transmits a second communication message in which the third information stored in the first storage area is included as first information.

4. The detection result storage area includes a third storage area that stores multiple fifth pieces of information indicating the abnormal state detected by the abnormality detection circuit as a history. The integrated circuit according to claim 1, which, upon receiving a first communication message that specifies the address of the third storage area and instructs the reading of information stored in the third storage area, transmits a second communication message in which the fifth information stored in the area of ​​the third storage area specified by the address is included as the first information.

5. An integrated circuit according to any one of claims 1 to 4, A control device that transmits the first communication message to the integrated circuit, Equipped with, The control device determines whether or not an abnormality has occurred based on the second information contained in the second communication message transmitted from the integrated circuit. Wireless communication device.

6. The wireless communication device according to claim 5, wherein, when the control device determines that an abnormality has occurred, it transmits a third communication message to the integrated circuit specifying an address and instructing it to read the information stored in the detection result storage area.

7. A first step in which the control device transmits the first communication message to the integrated circuit according to any one of claims 1 to 4, The second step is that when the integrated circuit receives the first communication message, it transmits the second communication message to the control device, A method for obtaining an abnormal state.

8. The control device performs a third step of determining whether or not an abnormality has occurred based on the second information contained in the second communication message transmitted from the integrated circuit, If the control device determines that an abnormality has occurred, it sends a third communication message to the integrated circuit specifying an address and instructing it to read the information stored in the detection result storage area, in a fourth step. A method for obtaining an abnormal state according to claim 7, comprising:

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