Integrated circuit and anomaly history management method

Abstract

The present invention provides an integrated circuit and an abnormality history management method that can detect the occurrence of an abnormal condition and determine whether or not the abnormal condition is continuing. [Solution] The integrated circuit includes an abnormality detection circuit that detects the presence or absence of an abnormality, a first storage area that stores first information indicating the latest detection result of the abnormality detection circuit, and a second storage area provided in correspondence with the first storage area that stores second information indicating the detection history of abnormalities detected by the abnormality detection circuit.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and an abnormal history management method.

Background Art

[0002] Some integrated circuits can detect abnormal states. For example, a radio frequency integrated circuit used in a wireless communication device includes a power detector (PD) in the path from a power amplifier (PA) to an antenna, and there are those that can detect an abnormality in the power of a radio signal transmitted from the antenna according to the detection result of the power detector. In such an integrated circuit, there is one that stores information indicating the detection result of an abnormal state.

[0003] The following Patent Document 1 discloses an abnormal detection data recording device that can detect an abnormality and leave a history thereof. This abnormal detection data recording device includes a first semiconductor integrated circuit device and a second semiconductor integrated circuit device, transmits abnormal detection data indicating an abnormality detected by the first semiconductor integrated circuit device to the second semiconductor integrated circuit device, and stores the abnormal detection data in the second semiconductor integrated circuit device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in an integrated circuit that can store information indicating an anomaly, such as the technology disclosed in Patent Document 1 mentioned above, it is possible to know what kind of anomaly has occurred by referring to the recorded information. However, even by referring to the recorded information, it is not possible to know whether the anomaly is still ongoing or whether the anomaly was temporary and has already been resolved.

[0006] The present invention has been made in view of the above circumstances, and aims to provide an integrated circuit and an abnormality history management method that can detect the occurrence of an abnormal condition and determine whether or not the abnormal condition is continuing. [Means for solving the problem]

[0007] To solve the above problems, an integrated circuit (10) according to a first aspect of the present invention includes an abnormality detection circuit (6b, 16, 18a) for detecting the presence or absence of an abnormality, a first storage area for storing first information indicating the latest detection result of the abnormality detection circuit, and a second storage area provided in correspondence with the first storage area for storing second information indicating the detection history of abnormalities detected by the abnormality detection circuit.

[0008] In an integrated circuit according to one aspect of the present invention, first information indicating the latest detection result of an abnormality detection circuit that detects the presence or absence of an abnormality is stored in a first memory area, and second information indicating the detection history of abnormalities detected by the abnormality detection circuit is stored in a second memory area provided in correspondence with the first memory area. This makes it possible to know when an abnormal condition has occurred and whether or not the abnormal condition is continuing.

[0009] An integrated circuit according to a second aspect of the present invention erases the second information stored in the second storage area when an initialization operation of a storage area including the second storage area is performed, or when a communication message is received that instructs to erase the second information by specifying the address of the second storage area.

[0010] An integrated circuit according to a third aspect of the present invention further comprises, in an integrated circuit according to a first or second aspect of the present invention, a circuit section (12) that amplifies a high-frequency signal supplied to an antenna element (21), and a power detection circuit (70) that detects the power of the high-frequency signal amplified by the circuit section and compares a voltage output (VO) obtained from that with a predetermined reference voltage (Vr), and outputs a power detection signal DT which is at a first level if the voltage output is higher than the reference voltage, and at a second level if the voltage output is lower than the reference voltage, wherein the abnormality detection circuit detects whether or not there is an abnormality in the high-frequency signal based on an amplification factor setting value that defines the amplification factor of the circuit section and the power detection signal output from the power detection circuit.

[0011] An integrated circuit according to a fourth aspect of the present invention, in an integrated circuit according to a third aspect of the present invention, detects a first abnormality when the amplification factor setting value is greater than a first setting reference value and the power detection signal is at the second level, and detects a second abnormality when the amplification factor setting value is less than a second setting reference value which is less than the first setting reference value and the power detection signal is at the first level.

[0012] An integrated circuit according to a fifth aspect of the present invention, in an integrated circuit according to a fourth aspect of the present invention, the abnormality detection circuit does not detect the first abnormality and the second abnormality if the amplification factor setting value is smaller than the first setting reference value and larger than the second setting reference value.

[0013] An integrated circuit according to a sixth aspect of the present invention is an integrated circuit according to a fourth or fifth aspect of the present invention, wherein the reference voltage is set such that the level of the power detection signal is switched when the amplification factor setting value is between the first setting reference value and the second setting reference value.

[0014] An integrated circuit according to the seventh aspect of the present invention is an integrated circuit according to any one of the first to sixth aspects of the present invention, wherein the abnormality detection circuit is a circuit that detects a communication message protocol abnormality when the content of the received communication message is an invalid instruction.

[0015] An abnormality history management method according to one aspect of the present invention involves, if the detection result of an abnormality detection circuit (6b, 16, 18a) provided on the integrated circuit indicates an abnormality, performing a first step of storing the detection result of the abnormality detection circuit as first information in a first storage area that stores first information indicating the latest detection result of the abnormality detection circuit, and a second step of storing the detection result of the abnormality detection circuit as second information in a second storage area provided corresponding to the first storage area and that stores second information indicating the detection history of abnormalities detected by the abnormality detection circuit; if the detection result of the abnormality detection circuit does not indicate an abnormality, only the first step is performed and the second step is not performed. [Effects of the Invention]

[0016] According to the present invention, it is possible to know when an abnormal condition has occurred, and whether or not the abnormal condition is continuing. [Brief explanation of the drawing]

[0017] [Figure 1] This is a system configuration diagram showing the configuration of a wireless communication device in one embodiment of the present invention. [Figure 2] This block diagram shows the main components of a beamformer integrated circuit according to one embodiment of the present invention. [Figure 3] This is a block diagram showing the configuration of a power detection circuit provided in a wireless communication device according to one embodiment of the present invention. [Figure 4] This figure shows the connection relationship between the digital circuit section and the analog circuit section provided in the RF front end of a beamformer integrated circuit according to one embodiment of the present invention. [Figure 5] This figure shows an example configuration of an abnormality detection system that detects an abnormality in output power using a power detection signal output from a power detection circuit in one embodiment of the present invention. [Figure 6]It is a diagram showing another configuration example of an abnormality detection system that detects an output power abnormality using a power detection signal output from a power detection circuit in an embodiment of the present invention. [Figure 7] It is a block diagram showing a configuration example of an abnormality detection system that detects a protocol abnormality of a beamformer integrated circuit according to an embodiment of the present invention. [Figure 8] It is a diagram showing an example of a memory map of a register provided in a beamformer integrated circuit according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0018] Hereinafter, with reference to the drawings, an integrated circuit and an abnormality history management method according to an embodiment of the present invention will be described in detail. Hereinafter, as an integrated circuit according to an embodiment of the present invention, a beamformer integrated circuit will be described as an example. In addition, a phased array antenna module and a wireless communication device including the beamformer integrated circuit will also be described.

[0019] FIG. 1 is a system configuration diagram showing the configuration of a wireless communication device in an embodiment of the present invention. As shown in FIG. 1, the wireless communication device DV of the present embodiment includes a phased array antenna module 1 and a control device 50. Such a wireless communication device DV can perform beamforming that can freely change a beam pattern, for example, using a millimeter wave band.

[0020] The phased array antenna module 1 has, for example, a plurality of integrated circuits (ICs) mounted on one surface of a substrate such as a known printed circuit board, and an antenna array mounted on the other surface. The plurality of integrated circuits and the antenna array constituting the phased array antenna module 1 are formed by using known materials and known methods. In addition, the electrical connection structure between the plurality of integrated circuits and the electrical connection structure between the integrated circuit and the antenna array are not particularly limited. A known connection structure is adopted as the electrical connection structure.

[0021] The control device 50 communicates with a higher-level device (not shown) installed at the base of a pole or tower or in a station building, for example, via an optical fiber FB, and communicates with a corresponding wireless communication device such as a mobile terminal, fixed wireless access network equipment, or base station equipment using the phased array antenna module 1. The control device 50 includes an optical transceiver (not shown) or a pluggable type optical transceiver with an optical connector. The optical fiber FB is connected to the optical transceiver of the control device 50 via an optical connector CN installed in the housing of the wireless communication device DV.

[0022] <Phaseed Array Antenna Module> As shown in Figure 1, the phased array antenna module 1 comprises eight beamformer integrated circuits 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer integrated circuits 10A to 10H), an antenna array 20, a frequency conversion integrated circuit 30, and an RF signal coupler / splitter 40.

[0023] The phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. RF signals of the IF (intermediate frequency) signal frequency are transmitted and received between the control device 50 and the phased array antenna module 1 via the signal line 51. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0024] The beamformer integrated circuits 10A to 10H are integrated circuits that control the beam pattern of the antenna array 20. Each of the beamformer integrated circuits 10A to 10H is connected to multiple antenna elements 21 that make up the antenna array 20. For example, each of the beamformer integrated circuits 10A to 10H is connected to eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization. In other words, the antenna array 20 is composed of a total of 128 antenna elements 21: 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. Further details of the beamformer integrated circuits 10A to 10H will be described later.

[0025] The frequency conversion integrated circuit 30 is an integrated circuit that performs frequency conversion between an RF signal at the IF signal frequency and an RF signal at the frequency transmitted and received by the beamformer integrated circuits 10A to 10H and the antenna array 20.

[0026] The RF signal coupler / splitter 40 distributes the RF signal output from the frequency conversion integrated circuit 30 to each of the beamformer integrated circuits 10A to 10H. The RF signal coupler / splitter 40 also combines the RF signals received by each of the beamformer integrated circuits 10A to 10H and inputs them to the frequency conversion integrated circuit 30.

[0027] <Beamformer Integrated Circuit> Figure 2 is a block diagram showing the main components of a beamformer integrated circuit according to one embodiment of the present invention. The eight beamformer integrated circuits 10A to 10H have the same configuration as each other. Therefore, in the following description, one of the beamformer integrated circuits 10A to 10H, i.e., beamformer integrated circuit 10, may be described. The other seven beamformer integrated circuits may be omitted from the description.

[0028] The beamformer integrated circuit 10 (integrated circuit) comprises 16 RF front ends (RFFEs) 5A to 5P, a digital circuit 6, an analog circuit 7, and an RF signal coupler / splitter 8. The 16 RF front ends 5A to 5P have the same configuration as each other. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., RF front end 5, may be described. The other 15 RF front ends may be omitted from the description.

[0029] In the beamformer integrated circuit 10 shown in Figure 2, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P such that each of the 16 RF front ends 5A to 5P corresponds one-to-one with each of the RF front ends 5. Of the 16 RF front ends 5A to 5P and 16 antenna elements 21A to 21P, 8 RF front ends (e.g., RF front ends 5A to 5H) and 8 antenna elements (e.g., antenna elements 21A to 21H) are for horizontal polarization, and the remaining 8 RF front ends (e.g., RF front ends 5I to 5P) and 8 antenna elements (e.g., antenna elements 21I to 21P) are for vertical polarization.

[0030] The 16 antenna elements 21A to 21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A to 21P, i.e., antenna element 21, may be described. The other 15 antenna elements may be omitted from the description. Antenna elements 21A to 21P may have the same configuration. For each of the configurations of antenna elements 21A to 21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may differ slightly.

[0031] Thus, in one beamformer integrated circuit 10, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P in a one-to-one correspondence. Therefore, in the phased array antenna module 1 having eight beamformer integrated circuits 10A to 10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A to 5P in each of the eight beamformer integrated circuits 10A to 10H.

[0032] The 128 antenna elements 21 constituting the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. Eight beamformer integrated circuits 10A to 10H control the transmission and reception of horizontally polarized radio waves and the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized and vertically polarized radio waves, the beamformer integrated circuits 10A to 10H set the phase and intensity of each of the 64 antenna elements so that the direction of the combined radio wave transmitted or received from the 64 antenna elements 21 is in a predetermined direction.

[0033] As shown in Figure 2, the RF front end 5 comprises a digital circuit section 11 and an analog circuit section 12 (circuit section). The digital circuit section 11 transmits and receives control-related communication messages to and from the control device 50 via the control line 52 shown in Figure 1. The digital circuit section 11 controls the RF front end 5 based on the communication messages transmitted from the control device 50.

[0034] In this embodiment, control-related communication messages are transmitted and received between the phased array antenna module 1 and the control device 50 via parallel communication. In other words, the digital circuit unit 11 transmits and receives control-related communication messages to and from the control device 50 via parallel communication. Note that the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. Serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) may also be used.

[0035] The digital circuit unit 11 is connected to the digital circuit 6 by internal wiring of the beamformer integrated circuit 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 50. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the content of the communication message transmitted from the control device 50.

[0036] A single communication transaction transmitted from the control device 50 to the phased array antenna module 1 includes additional information, commands, and data. The communication transaction has a fixed bit length. The command is a register address if it instructs a write to or read from a register. Alternatively, the command is a numerical value indicating an operation instruction to the beamformer integrated circuit 10 or the RF front-end 5. Both the command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 16 bits.

[0037] The digital circuit unit 11 includes a memory 13, which is a memory area for storing beam tables used for beamforming. The beam table is a lookup table that stores multiple combinations of phase shift amount setting values ​​and intensity setting values, which are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (a beam table with 2048 items) with 2048 combinations of phase shift amount setting values ​​and intensity setting values ​​is stored in the memory 13.

[0038] Memory 13 is implemented using, for example, SRAM (Static Random Access Memory). While it is preferable that memory 13 be implemented using SRAM, it may also be implemented using registers, DRAM (Dynamic Random Access Memory), flash memory, or ROM (Read Only Memory).

[0039] The analog circuit section 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit section 11, the analog circuit section 12 adjusts the phase and intensity of the RF signals transmitted and received by the antenna element 21 connected to the RF front end 5.

[0040] The analog circuit section 12 is connected to the analog circuit 7 via an RF signal coupler / splitter 8. The RF signal coupler / splitter 8 distributes the RF signal output from the analog circuit 7 to the analog circuit sections 12 provided in each of the RF front ends 5A to 5P. The RF signal coupler / splitter 8 also combines the RF signals output from the analog circuit sections 12 provided in each of the RF front ends 5A to 5P and outputs them to the analog circuit 7.

[0041] As shown in Figure 2, the analog circuit section 12 includes a phase shifter (PS) 61, a changeover switch (SW) 62, a variable gain amplifier (VGA) 63, a phase inverter (PI) 64, a power amplifier (PA) 65, a changeover switch (SW) 66, a low-noise amplifier (LNA) 67, a variable gain amplifier (VGA) 68, a phase inverter (PI) 69, and a power detection circuit (PD) 70.

[0042] The variable gain amplifier 63, the phase inverter 64, and the power amplifier 65 are located on the transmission path R1, while the low-noise amplifier 67, the variable gain amplifier 68, and the phase inverter 69 are located on the reception path R2. The transmission path R1 is the path through which the RF signal (high-frequency signal) output to the antenna element 21 passes, and the reception path R2 is the path through which the RF signal (high-frequency signal) input from the antenna element 21 passes. The changeover switches 62 and 66 switch between connecting the transmission path R1 or the reception path R2 between the phase shifter 61 and the antenna element 21 at specified time intervals. This allows the phased array antenna module 1 to transmit and receive high-frequency signals as a time-division multiplexing system.

[0043] The phase shifter 61 adjusts the phase shift amount of the RF signal passing through the transmission path R1 or the RF signal passing through the reception path R2 according to the phase shift amount setting value of the beam table read from the memory 13 of the digital circuit unit 11. In other words, the phase shifter 61 is provided in common to both the transmission path R1 and the reception path R2. Alternatively, the phase shifter 61 common to both the transmission path R1 and the reception path R2 may be omitted, and a separate phase shifter may be provided for each of the transmission path R1 and the reception path R2.

[0044] The variable gain amplifier 63 amplifies the RF signal passing through the transmission path R1 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 64 inverts the phase of the RF signal passing through the transmission path R1 according to the phase shift amount setting value of the beamtable read from the memory 13. The power amplifier 65 amplifies the RF signal passing through the transmission path R1 at a predetermined amplification factor. By adjusting the phase shift amount and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0045] The low-noise amplifier 67 amplifies the RF signal output from the selector switch 66 at a predetermined amplification factor. The variable-gain amplifier 68 amplifies the RF signal passing through the receiving path R2 according to the intensity setting value of the beamtable read from the memory 13. The phase inverter 69 inverts the phase of the RF signal passing through the receiving path R2 according to the phase shift amount setting value of the beamtable read from the memory 13. By adjusting the phase shift amount and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0046] The power detection circuit 70 detects the power of the RF signal amplified by the power amplifier 65 and supplied to the antenna element 21, and outputs a signal (digital signal) indicating the detection result. Specifically, a branching switch BR is provided in the transmission path R1 between the power amplifier 65 and the switch 66 to branch the RF signal amplified by the power amplifier 65 at a stable branching ratio. One of the RF signals branched by branching switch BR is supplied to the switch 66, and the other of the RF signals branched by branching switch BR is supplied to the power detection circuit 70. The power detection circuit 70 detects the power by inputting the power of the other RF signal branched by branching switch BR, and outputs a signal (digital signal) indicating the detection result.

[0047] Figure 3 is a block diagram showing the configuration of a power detection circuit provided in a wireless communication device according to one embodiment of the present invention. As shown in Figure 3, the power detection circuit 70 includes a power detector 70a and a voltage comparison circuit 70b. The power detector 70a detects the power of the other RF signal SP branched by the brancher BR shown in Figure 2, and outputs the detection result as a voltage output VO.

[0048] The voltage output VO is an analog signal whose voltage changes according to the power detection result of the RF signal SP. For example, the voltage output VO may be a signal whose voltage changes in proportion to the magnitude of the detected power.

[0049] The voltage comparison circuit 70b compares the voltage output VO of the power detector 70a with a predetermined reference voltage Vr and outputs a power detection signal DT according to the comparison result. This power detection signal DT is a digital signal. Specifically, the voltage comparison circuit 70b outputs a power detection signal DT that is at the "H (high)" level (first level) when the voltage output VO is higher than the reference voltage Vr, and at the "L (low)" level (second level) when the voltage output VO is lower than the reference voltage Vr. The reference voltage Vr will be described later. The digital power detection signal DT is input to the digital circuit section 11 in the RF front end 5.

[0050] Figure 4 shows the connection relationship between the digital circuit section and the analog circuit section provided at the RF front end of a beamformer integrated circuit according to one embodiment of the present invention. As shown in Figure 4, the phase shifter 61, variable gain amplifiers 63, 68, and phase inverters 64, 69 provided in the analog circuit section 12 are controlled according to the contents of the beam table stored in the memory 13. In contrast, the changeover switches 62, 66, power amplifier 65, and low-noise amplifier 67 provided in the analog circuit section 12 are controlled by logic circuits such as registers (not shown) provided in the digital circuit section 11. The power detection signal DT output from the power detection circuit 70 is input to the digital circuit section 11.

[0051] The unpacking circuit 14 unpacks the bit sequence of the phase shift amount setting value read from the memory 13 of the beam table into a bit sequence of a control value (phase shift control value) for controlling the phase shifter 61. The phase shift amount setting value stored in the beam table is, for example, 7 bits, and the intensity setting value is, for example, 5 bits. The unpacking circuit 14 unpacks 6 bits of the 7-bit phase shift amount setting value into a 52-bit control value bit sequence. The remaining 1 bit of the phase shift amount setting value is used to control the phase inverters 64 and 69. The number of bits in the phase shift amount setting value is set according to the resolution of the phase shift amount, and the number of bits in the control value is set according to the number of division units constituting the phase shifter 61.

[0052] When the most significant bit of the phase shift amount setting value is "1", a phase inversion is instructed to the phase inverters 64 and 69. This corresponds to setting a phase shift amount of 180 degrees. The lower six bits of the phase shift amount setting value are used to indicate which of the 52 division units constituting the phase shifter 61 will have their state changed. When the value of the lower six bits of the phase shift amount setting value is "0", all 52 division units constituting the phase shifter 61 are in the reference state, and when the value is between "1" and "52", the number of division units corresponding to that value are set to the phase shift state. Furthermore, when the value of the lower six bits of the phase shift amount setting value is "52", all 52 division units constituting the phase shifter 61 are set to the phase shift state. In other words, when the phase shifter 61 is composed of 52 division units, the phase shift state of the phase shifter 61 can be set in 53 steps.

[0053] The phase shifter 61 is designed so that, in the frequency range used by the phased array antenna module 1, the phase shift amount exceeds 180 degrees when all 52 division units are set to the phase shift state. In this embodiment, a configuration in which the phase shift amount of the RF signal passing through the transmission path R1 or the reception path R2 is adjusted by combining phase inverters 64 and 69 with the phase shifter 61 capable of setting a phase shift amount exceeding 180 degrees is used as an example, but the configuration is not limited to this. A configuration using only a phase shifter capable of setting a phase shift amount exceeding 360 degrees is also possible without using phase inverters 64 and 69.

[0054] Furthermore, as mentioned above, the lower 6 bits of the phase shift amount setting value are expanded into a 52-bit bit sequence of a control value (phase shift control value) for controlling the phase shifter 61 by the expansion circuit 14 shown in Figure 4. In other words, the lower 6 bits of the phase shift amount setting value are expanded into a bit sequence with the same number of bits as the number of division units that make up the phase shifter 61. Note that the number of division units that make up the phase shifter 61 is not limited to 52, but can be any number.

[0055] The five bits of the intensity setting value are amplification factor setting values ​​that define the amplification factor of the variable gain amplifiers 63 and 68. By individually setting the five bits of intensity setting value for the variable gain amplifiers 63 and 68, the signal strength of the RF signal passing through the transmission path R1 and the RF signal passing through the reception path R2 are individually adjusted.

[0056] Figure 5 shows an example of the configuration of an abnormality detection system that detects an output power abnormality using a power detection signal output from a power detection circuit in one embodiment of the present invention. The abnormality detection system shown in Figure 5 includes a memory 13, a register 17, and an abnormality detection circuit 16 (abnormality detection circuit) provided in the digital circuit section 11.

[0057] As described above, memory 13 stores a beam table containing amplification factor setting values ​​that define the amplification factor of the variable gain amplifier 63. The amplification factor of the RF signal passing through the transmission path R1 of the analog circuit section 12 (the amplification factor of the circuit section) is defined by the amplification factor setting value read from memory 13 and the amplification factor setting value set for the power amplifier 65. Hereinafter, the amplification factor setting value that defines the amplification factor of the RF signal passing through the transmission path R1 of the analog circuit section 12 will be referred to as the "transmission signal amplification factor setting value".

[0058] Register 17 stores the high-power setting reference value RH (first setting reference value) and the low-power setting reference value RL (second setting reference value), which are used to detect whether or not there is an abnormality in the output power of the power amplifier 65. The high-power setting reference value RH and the low-power setting reference value RL are reference values ​​set relative to the transmission signal amplification factor setting value. The high-power setting reference value RH and the low-power setting reference value RL held in register 17 can be rewritten based on instructions from the control device 50.

[0059] Specifically, the high-power setting reference value RH is a reference value used to determine whether the transmission signal amplification factor setting value causes the output power of the power amplifier 65 to be greater than a predetermined first power (high output). The low-power setting reference value RL is a reference value used to determine whether the transmission signal amplification factor setting value causes the output power of the power amplifier 65 to be less than a predetermined second power (low output).

[0060] The abnormality detection circuit 16 detects whether there is an abnormality in the RF signal (output power of the power amplifier 65) amplified by the power amplifier 65 and supplied to the antenna element 21, based on the transmission signal amplification factor setting value and the power detection signal DT output from the power detection circuit 70. When detecting whether there is an abnormality in the output power of the power amplifier 65, the abnormality detection circuit 16 uses the high-power setting reference value RH and the low-power setting reference value RL stored in the register 17.

[0061] Figure 6 shows another example of an abnormality detection system that detects an output power abnormality using a power detection signal output from a power detection circuit in one embodiment of the present invention. The abnormality detection system shown in Figure 6 includes a memory 13, a register 17, and an abnormality detection circuit 16 provided in the digital circuit unit 11, as well as a register 15 provided in the digital circuit unit 11.

[0062] Register 15 holds the amplification factor setting value that defines the amplification factor of the power amplifier 65. The amplification factor setting value held in register 15 can be rewritten based on instructions from the control device 50. In other words, the abnormality detection system shown in Figure 6 can change the amplification factor of the power amplifier 65 as appropriate, and differs from the abnormality detection system shown in Figure 5 in that the transmission signal amplification factor setting value is determined by the amplification factor setting value read from memory 13 and the amplification factor setting value held in register 15. However, in the abnormality detection system shown in Figure 6, the abnormality detection circuit 16 detects whether or not there is an abnormality in the output power of the power amplifier 65 based on the transmission signal amplification factor setting value and the power detection signal DT, which is the same as the abnormality detection system shown in Figure 5.

[0063] The high-power setting reference value RH and the low-power setting reference value RL are set such that the high-power setting reference value RH is greater than the low-power setting reference value RL within the range in which the output power of the power amplifier 65 can change. At this time, the reference voltage Vr used in the voltage comparison circuit 70b of the power detection circuit 70 is set so that the level of the power detection signal DT is switched when the amplification factor setting value is between the high-power setting reference value RH and the low-power setting reference value RL.

[0064] The abnormality detection circuit 16 outputs a low-power abnormality detection signal AL if the transmission signal amplification factor setting value is greater than the high-power setting reference value RH and the power detection signal DT is at the "L" level. In other words, if the transmission signal amplification factor setting value is a value that indicates high power, but the power detected by the power detection circuit 70 is low, the abnormality detection circuit 16 detects an abnormality (first abnormality) and outputs a low-power abnormality detection signal AL at the "H" level.

[0065] The anomaly detection circuit 16 outputs a high-power anomaly detection signal AH (second anomaly signal) if the transmission signal amplification factor setting value is smaller than the low-power setting reference value RL and the power detection signal DT is at the "H" level. In other words, the anomaly detection circuit 16 detects an anomaly (second anomaly) and outputs a high-power anomaly detection signal AH at the "H" level if the power detected by the power detection circuit 70 is high, even though the transmission signal amplification factor setting value is a value that indicates low power.

[0066] Furthermore, if the transmission signal amplification factor setting is smaller than the high-power setting reference value RH and larger than the low-power setting reference value RL, the anomaly detection circuit 16 will not output the low-power anomaly detection signal AL and the high-power anomaly detection signal AH, regardless of the level of the power detection signal DT. In other words, the anomaly detection circuit 16 will not detect an anomaly in output power because the transmission signal amplification factor setting is between the value indicating high power and the value indicating low power. In other words, the low-power anomaly detection signal AL and the high-power anomaly detection signal AH will be at the "L" level.

[0067] Thus, the anomaly detection circuit 16 can detect output power anomalies using flexible criteria that correspond to the contents of the beamtable (amplification factor setting value that defines the amplification factor of the variable gain amplifier 63), or to the contents of both the beamtable and the register 15 (amplification factor setting value that defines the amplification factor of the power amplifier 65). Moreover, since the power detection signal DT, which is a digital signal output from the power detection circuit 70, is used to detect output power anomalies, output power anomalies can be detected with high real-time accuracy.

[0068] The high-power anomaly detection signal AH and the low-power anomaly detection signal AL output from the anomaly detection circuit 16 are acquired by the control device 50. Alternatively, the high-power anomaly detection signal AH and the low-power anomaly detection signal AL output from the anomaly detection circuit 16 may be stored in a register (not shown) provided in the digital circuit unit 11. The control device 50 may then request acquisition from the digital circuit unit 11 to retrieve the high-power anomaly detection signal AH and the low-power anomaly detection signal AL stored in the register.

[0069] Figure 7 is a block diagram showing an example configuration of an anomaly detection system for detecting protocol anomalies in a beamformer integrated circuit according to one embodiment of the present invention. As shown in Figure 7, each digital circuit section 11 of the RF front end 5A to 5P is provided with a transmit / receive circuit 18, and the digital circuit 6 is provided with a transmit / receive circuit 6a. In addition, each of the transmit / receive circuits 18 is provided with a protocol anomaly detection circuit 18a (anomaly detection circuit) for detecting communication protocol errors (communication message protocol anomalies), and the transmit / receive circuit 6a is provided with a protocol anomaly detection circuit 6b (anomaly detection circuit) for detecting communication protocol errors.

[0070] The transmit / receive circuit 6a, provided in the digital circuit 6, receives the communication message transmitted from the control device 50 and analyzes its contents. The protocol anomaly detection circuit 6b, provided in the transmit / receive circuit 6a, detects whether or not there is a communication protocol error. The protocol anomaly detection circuit 6b detects a communication protocol error if the content of the communication message received by the transmit / receive circuit 6a is an invalid instruction. The transmit / receive circuits 18, provided in each digital circuit section 11 of the RF front end 5A to 5P, receive the communication message transmitted from the control device 50 and analyze its contents. The protocol anomaly detection circuit 18a, provided in the transmit / receive circuit 18, detects whether or not there is a communication protocol error. The protocol anomaly detection circuit 18a detects a communication protocol error if the content of the communication message received by the transmit / receive circuit 18 is an invalid instruction.

[0071] <Memory map of registers> Figure 8 shows an example of a register memory map provided in a beamformer integrated circuit according to one embodiment of the present invention. In this embodiment, the address of the register memory map is 8 bits, and values ​​from "0" to "255" can be specified. The storage capacity of each register is, for example, up to 16 bits. In this embodiment, the 8-bit address space is shared by the register provided in the frequency conversion integrated circuit 30, the register provided in the digital circuit 6 of the beamformer integrated circuit 10, and the register provided in the digital circuit section 11 of the RF front end 5.

[0072] A register is a memory area that stores information by writing to it by specifying an address, and retrieves the stored information by reading it by specifying an address. Furthermore, information may be stored in or updated in registers by logic circuits provided in the digital circuit 6 of the beamformer integrated circuit 10, or in the digital circuit section 11 of the RF front-end 5.

[0073] In the example shown in Figure 8, the registers to which addresses K and K+1 are assigned are registers located in the digital circuit 6 of the beamformer integrated circuit 10. The registers to which addresses L, L+1, M, M+1, N, and N+1 are assigned are registers located in the digital circuit section 11 of the RF front-end 5.

[0074] In other words, when a write or read operation is instructed by specifying address K or address K+1, the write or read operation is performed on a register provided in the digital circuit 6 of the beamformer integrated circuit 10. Furthermore, when a write or read operation is instructed by specifying address L, address L+1, address M, address M+1, address N, or address N+1, the write or read operation is performed on a register provided in the digital circuit section 11 of the RF front-end 5, which has been selected separately in advance. The RF front-end 5 is selected, for example, using a register (not shown) provided in the digital circuit 6 of the beamformer integrated circuit 10.

[0075] Although not shown in Figure 8, a certain address range is also assigned to the registers provided in the frequency conversion integrated circuit 30. When a write or read operation is instructed by specifying an address within this range, the registers provided in the frequency conversion integrated circuit 30 are written to or read from.

[0076] The register assigned to address K (first memory area) stores information (first information) indicating the latest detection result showing whether or not there is an anomaly in the beamformer integrated circuit 10. The register assigned to address K+1 (second memory area) stores information (second information) indicating the detection history of anomalies detected in the beamformer integrated circuit 10.

[0077] The register assigned to address L (first memory area) stores information (first information) indicating the latest detection results showing whether or not there are any abnormalities in the RF front end 5. The register assigned to address L+1 (second memory area) stores information (second information) indicating the detection history of abnormalities detected in the RF front end 5.

[0078] The register assigned to address M stores the amplification factor setting value that defines the amplification factor of the power amplifier 65 provided in the RF front end 5. The register assigned to address M+1 stores the amplification factor setting value that defines the amplification factor of the low-noise amplifier 67 provided in the RF front end 5. The register assigned to address N stores the high-output setting reference value RH. The register assigned to address N+1 stores the low-output setting reference value RL. Note that the register assigned to address M is register 15 shown in Figure 6, and the registers assigned to addresses N and N+1 are register 17 shown in Figures 5 and 6.

[0079] The information stored in the register assigned to address K and the register assigned to address K+1 consists of multiple bits. For example, it includes a bit indicating whether or not an abnormality was detected in the RF front end 5 (hereinafter referred to as the "RFFE abnormality detection bit"), a bit indicating whether or not a communication protocol error was detected in the digital circuit 6 (hereinafter referred to as the "first communication error detection bit"), and so on. The information stored in the register assigned to address K and the register assigned to address K+1 is updated bit by bit according to the abnormality detected by the beamformer integrated circuit 10.

[0080] The information stored in the register assigned to address L and the register assigned to address L+1 also consists of multiple bits. For example, these include a bit indicating whether or not an abnormality was detected in the RF front end 5, a bit indicating whether or not a high-power abnormality was detected (hereinafter referred to as the "high-power abnormality detection bit"), a bit indicating whether or not a low-power abnormality was detected (hereinafter referred to as the "low-power abnormality detection bit"), and a bit indicating whether or not a communication protocol error was detected in the digital circuit section 11 of the RF front end 5 (hereinafter referred to as the "second communication error detection bit"). The information stored in the register assigned to address L and the register assigned to address L+1 is updated bit by bit according to the abnormality detected in the RF front end 5.

[0081] When the beamformer integrated circuit 10 receives a communication message instructing it to read information stored in a register assigned to a specified address, it reads the information stored in that register. Then, the beamformer integrated circuit 10 transmits a communication message containing the read information. For example, if a communication message instructing it to read is sent from the control device 50, the beamformer integrated circuit 10 transmits a communication message containing the read information to the control device 50.

[0082] <Method for managing abnormal history> Next, we will describe the operation when an abnormality is detected in the digital circuit 6 of the beamformer integrated circuit 10 or the digital circuit section 11 of the RF front end 5. Below, we will first describe the operation when an output abnormality of the power amplifier 65 is detected in the digital circuit section 11 of the RF front end 5 (operation when an output abnormality is detected). Next, we will describe the operation when a communication protocol error is detected in the digital circuit 6 or the digital circuit section 11 of the RF front end 5 (operation when a communication error is detected). Following that, we will describe the operation when the contents of the register are erased (reset operation).

[0083] Operation upon detecting an output anomaly In the anomaly detection system shown in Figure 5 or Figure 6, if a high-power anomaly in the output power of the power amplifier 65 is detected, a high-power anomaly detection signal AH is output from the anomaly detection circuit 16 of the anomaly detection system. Then, for example, a logic circuit provided in the digital circuit section 11 of the RF front end 5 sets the value of the high-power anomaly detection bit to "1" in the register to which address L is assigned (first step). Similarly, in the register to which address L+1 is assigned, the value of the high-power anomaly detection bit is also set to "1" (second step).

[0084] Furthermore, if no high-power anomaly is detected, only the value of the high-power anomaly detection bit in the register assigned to address L is set to, for example, "0" (Step 1). The value of the high-power anomaly detection bit in the register assigned to address L+1 is retained. In other words, the step of setting the value of the high-power anomaly detection bit in the register assigned to address L+1 to "0" (Step 2) is not performed.

[0085] In the anomaly detection system shown in Figure 5 or Figure 6, if a low output anomaly in the output power of the power amplifier 65 is detected, a low output anomaly detection signal AL is output from the anomaly detection circuit 16 of the anomaly detection system. Then, for example, the value of the low output anomaly detection bit in the register assigned to address L is set to "1" by a logic circuit provided in the digital circuit section 11 of the RF front end 5 (first step). Similarly, the value of the low output anomaly detection bit in the register assigned to address L+1 is also set to "1" (second step).

[0086] If no low-power anomaly is detected, only the value of the low-power anomaly detection bit in the register assigned to address L is set to, for example, "0" (Step 1). The value of the low-power anomaly detection bit in the register assigned to address L+1 is retained. In other words, the step of setting the value of the low-power anomaly detection bit in the register assigned to address L+1 to "0" (Step 2) is not performed.

[0087] Actions taken when a communication error is detected. Let's assume that a communication protocol error is detected by the protocol error detection circuit 6b of the anomaly detection system shown in Figure 7. Then, for example, the value of the first communication error detection bit in the register assigned to address K is set to "1" by the logic circuit provided in the digital circuit 6 (first step). Similarly, in the register assigned to address K+1, the value of the first communication error detection bit is also set to "1" (second step).

[0088] Furthermore, if the protocol anomaly detection circuit 6b does not detect a communication protocol error, only the value of the first communication error detection bit in the register assigned to address K is set to, for example, "0" (first step). The value of the first communication error detection bit in the register assigned to address K+1 is retained. In other words, the step of setting the value of the first communication error detection bit in the register assigned to address K+1 to "0" (second step) is not performed.

[0089] Let's assume that a communication protocol error is detected by the protocol error detection circuit 18a of the anomaly detection system shown in Figure 7. Then, for example, the logic circuit provided in the digital circuit section 11 of the RF front end 5 sets the value of the second communication error detection bit to "1" in the register to which address L is assigned (first step). Similarly, in the register to which address L+1 is assigned, the value of the second communication error detection bit is also set to "1" (second step).

[0090] Furthermore, if the protocol anomaly detection circuit 18b does not detect a communication protocol error, only the value of the second communication error detection bit in the register assigned to address L is set to, for example, "0" (first step). The value of the second communication error detection bit in the register assigned to address L+1 is retained. In other words, the step of setting the value of the second communication error detection bit in the register assigned to address L+1 to "0" (second step) is not performed.

[0091] Here, if the value of any bit in the register to which address L is assigned is "1", then the value of the RFFE anomaly detection bit in the register to which address K is assigned and the register to which address K+1 is assigned will be set to, for example, "1". Note that the case where the value of any bit in the register to which address L is assigned is "1" means that the value of the information stored in the register to which address L is assigned is not "0".

[0092] In contrast, if the value of all bits in the register to which address L is assigned is "0", then only the value of the RFFE anomaly detection bit in the register to which address K is assigned will be set to "0", for example. The value of the RFFE anomaly detection bit in the register to which address K+1 is assigned will be retained. Note that the case where the value of all bits in the register to which address L is assigned is "0" means that the value of the information stored in the register to which address L is assigned is "0".

[0093] Thus, the register assigned to address K+1 stores information indicating the detection history of anomalies detected by the beamformer integrated circuit 10 using multiple bits. If there is a detection history, the value of the corresponding bit is, for example, "1". Furthermore, if an anomaly is detected in any of the RF front-ends 5, the value of a specific bit in both the register assigned to address L+1 and the register assigned to address K+1 becomes "1". This makes it possible to determine whether or not there is a detection history of an anomaly detected by the beamformer integrated circuit 10 by referring only to the register assigned to address K+1.

[0094] Reset operation The value stored in the register assigned to address K+1 is set to "0" (reset) during the register's initialization operation, or when the digital circuit 6 of the beamformer integrated circuit 10 receives a communication message instructing it to erase the contents of address K+1. Similarly, the value stored in the register assigned to address L+1 is set to "0" (reset) during the register's initialization operation, or when the digital circuit 6 of the beamformer integrated circuit 10 receives a communication message instructing it to erase the contents of address L+1.

[0095] When the values ​​stored in the register assigned to address K+1 and the register assigned to address L+1 are set to "0", it means that the registers are set to a state where there is no history of previously detected anomalies. In this way, when the registers are initialized or when a communication message to erase the history is received, the registers are set to a state where there is no history of previously detected anomalies. For example, when the wireless communication device DV is in continuous operation, it is possible to repeatedly acquire and erase the history of anomalies as needed.

[0096] As described above, this embodiment includes an abnormality detection circuit 16 for detecting abnormalities in the output power of the power amplifier 65, and protocol abnormality detection circuits 6b and 18a for detecting communication protocol errors. Information indicating the detection history of abnormalities detected by these abnormality detection circuits is stored in a register assigned to address K+1 or a register assigned to address L+1. This makes it possible to know when an abnormal condition occurs and to know the history of abnormal occurrences.

[0097] Furthermore, in this embodiment, if the latest detection result of the abnormality detection circuit indicates an abnormality, the latest detection result of the abnormality detection circuit is stored in the register assigned to address K or the register assigned to address L. Conversely, if the latest detection result of the abnormality detection circuit does not indicate an abnormality, the latest detection result of the abnormality detection circuit is stored in the register assigned to address K or the register assigned to address L. This also makes it possible to know when an abnormal condition has occurred and whether or not the abnormal condition is continuing.

[0098] Although an integrated circuit and an abnormal history management method according to embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be freely modified within the scope of the present invention. For example, the power detection signal DT described above is a signal that is at the "H" level when the voltage output VO is higher than the reference voltage Vr and at the "L (low)" level when the voltage output VO is lower than the reference voltage Vr, but the signal levels may be reversed. The same applies to other digital signals.

[0099] Furthermore, the phased array antenna module described in the above embodiment was for a time-division multiplexing system. However, the phased array antenna module of the present invention may also be for a frequency-division multiplexing system.

[0100] Furthermore, in the embodiments described above, an example was described in which one antenna element 21 and one RF front end 5 are connected in a one-to-one correspondence. However, in the present invention, two front ends may be connected to dual-polarization antenna elements, each having a connection terminal for horizontal polarization and a connection terminal for vertical polarization. [Explanation of symbols]

[0101] 6b…Protocol anomaly detection circuit, 10…Beamformer integrated circuit, 12…Analog circuit section, 16…Anomaly detection circuit, 18a…Protocol anomaly detection circuit, 21…Antenna element, 63…Variable gain amplifier, 65…Power amplifier, 70…Power detection circuit, DT…Power detection signal, VO…Voltage output, Vr…Reference voltage

Claims

1. An anomaly detection circuit that detects the presence or absence of an anomaly, A first storage area that stores first information indicating the latest detection result of the abnormality detection circuit, A second storage area is provided corresponding to the first storage area and stores second information indicating the detection history of an anomaly detected by the anomaly detection circuit, An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, which erases the second information stored in the second storage area when an initialization operation of the storage area including the second storage area is performed, or when a communication message is received that instructs to erase the second information by specifying the address of the second storage area.

3. A circuit section that amplifies the high-frequency signal supplied to the antenna element, A power detection circuit that detects the power of the high-frequency signal amplified by the circuit section and compares the voltage output obtained with a predetermined reference voltage, and outputs a power detection signal which becomes a first level if the voltage output is higher than the reference voltage, and a second level if the voltage output is lower than the reference voltage, Furthermore, The abnormality detection circuit detects whether or not there is an abnormality in the high-frequency signal based on an amplification factor setting value that defines the amplification factor of the circuit section and the power detection signal output from the power detection circuit. The integrated circuit according to claim 1 or claim 2.

4. The abnormality detection circuit is, If the amplification factor setting value is greater than the first setting reference value and the power detection signal is at the second level, then the first abnormality is detected. If the amplification factor setting value is smaller than a second setting reference value which is smaller than the first setting reference value, and the power detection signal is at the first level, then a second abnormality is detected. The integrated circuit according to claim 3.

5. The integrated circuit according to claim 4, wherein the abnormality detection circuit does not detect the first abnormality and the second abnormality if the amplification factor setting value is smaller than the first setting reference value and larger than the second setting reference value.

6. The integrated circuit according to claim 4, wherein the reference voltage is set such that the level of the power detection signal is switched when the amplification factor setting value is between the first setting reference value and the second setting reference value.

7. The integrated circuit according to claim 1, wherein the abnormality detection circuit is a circuit that detects a communication message protocol abnormality when the content of the received communication message is an invalid instruction.

8. If an integrated circuit is found to have an abnormality as detected by an abnormality detection circuit provided on the integrated circuit, the following steps are performed: a first step of storing the detection result of the abnormality detection circuit as first information in a first storage area that stores first information indicating the latest detection result of the abnormality detection circuit; and a second step of storing the detection result as second information in a second storage area provided in correspondence with the first storage area and that stores second information indicating the detection history of abnormalities detected by the abnormality detection circuit. If the detection result of the abnormality detection circuit does not indicate an abnormality in the aforementioned integrated circuit, only the first step is performed, and the second step is not performed. Anomaly history management method.

Images