Semiconductor equipment

Abstract

This invention provides a new semiconductor device with a structure that retains its stored contents even when power is not supplied and has no limit on the number of write cycles, as well as a method for manufacturing the same and a method for driving it. [Solution] A semiconductor device having a non-volatile memory cell including a writing transistor 162 made of an oxide semiconductor, a reading transistor 160 made of a different semiconductor material than the transistor, and a capacitive element 164, wherein writing to the memory cell is performed by turning on the writing transistor to supply a potential to a node FG, which is electrically connected to the source electrode or drain electrode of the writing transistor, one of the electrodes of the capacitive element, and the gate electrode of the reading transistor, and then turning off the writing transistor to hold a predetermined amount of charge in the node. Furthermore, a p-channel type transistor is used as the reading transistor, and the reading potential is set to a positive potential.

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element and a method for manufacturing the same. Furthermore, this relates to a method for driving the semiconductor device. [Background technology]

[0002] Memory devices using semiconductor elements are volatile, meaning that the stored data is lost when the power supply is cut off. They can be broadly classified into two types: physical data and non-volatile data, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in the capacitor, it stores information.

[0004] Based on the principle described above, in DRAM, when information is read, the charge in the capacitor is lost, therefore, Each time the data is read, a write operation is required again. Also, the transistors that make up the memory element In an inverter, the leakage current between the source and drain in the off state (off current), etc. Therefore, even when a transistor is not selected, charge flows out or in, so data The retention period is short. Therefore, a write operation (refresh operation) is performed again at a predetermined interval. It is necessary, and it is difficult to sufficiently reduce power consumption. Also, the power supply will be cut off. Because the memory content is lost, long-term memory retention requires the use of other materials such as magnetic or optical materials. A storage device is required.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). SRAM has memory. SRAM uses circuits such as flip-flops to store information. Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Also, in order to inject charge into the floating gate, or to remove that charge This requires a high voltage, as well as a circuit for that purpose. Furthermore, charge injection... , or removal takes a relatively long time, and speeding up writing or erasing is not easy. There's also the problem that it's not available. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 [Overview of the project] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of its objectives is to achieve this. [Means for solving the problem]

[0011] The disclosed invention provides a material that can sufficiently reduce the off-current of a transistor, for example For example, a semiconductor device is constructed using oxide semiconductor material, which is a wide-bandgap semiconductor. By using semiconductor materials that can sufficiently reduce the off-current of the inverter, long-term operation is possible. It is possible to retain information over time.

[0012] Furthermore, the disclosed invention includes a writing transistor using an oxide semiconductor, and the writing Readout transistors and capacitive elements using semiconductor materials different from those of transistors. A semiconductor device having a volatile memory cell is provided. Information is written to the memory cell and Rewriting is done by turning on the writing transistor. One of the source or drain electrodes of the zista, one of the electrodes of the capacitive element, and readout The gate electrode of the transistor is electrically connected to a node to which a potential is supplied, and then it writes By turning off the charging transistor, a predetermined amount of charge can be retained at the node. This is done using a p-channel transistor as the readout transistor. The readout potential is defined as a positive potential.

[0013] More specifically, the following configuration can be adopted, for example.

[0014] One aspect of the present invention relates to a bit line, a source line, a write word line, and a write and read line. It has an output word line and a memory cell, the memory cell having a first gate electrode and a first saw A p-channel type first including a drain electrode, a first drain electrode, and a first channel forming region The transistor, and a second gate electrode, a second source electrode, a second drain electrode, and The device comprises a second transistor including a second channel formation region, and a capacitive element, and the first channel The channel formation region is composed of a different semiconductor material than the second channel formation region, The gate electrode of device 1, the drain electrode of device 2, and one electrode of the capacitive element are electrically connected. A node is formed in which the charge is held, and the bit line, the first source electrode, and the second source The first drain electrode is electrically connected to the source wire and the first drain electrode. The write word line and the second gate electrode are electrically connected, allowing for writing and reading. The protruding word line and the other electrode of the capacitive element are electrically connected semiconductor devices.

[0015] Furthermore, one aspect of the present invention includes a bit line, a source line, a write word line, and a write and A read word line, a memory cell array containing multiple memory cells, and a potential switching circuit. The memory cell has a first gate electrode, a first source electrode, and a first drain A first p-channel type transistor including electrodes and a first channel formation region, and a second The gate electrode, second source electrode, second drain electrode, and second channel forming region The device comprises a second transistor and a capacitive element, and the first channel formation region is the second The channel formation region is composed of different semiconductor materials and comprises a first gate electrode and a second The drain electrode and one electrode of the capacitive element are electrically connected to hold the charge. The node is formed, and the bit line, the first source electrode, and the second source electrode are electrically connected. The terminals of the potential switching circuit, the source wire, and the first drain electrode are electrically connected. The write word line and the second gate electrode are electrically connected, and the write The readout word line and the other electrode of the capacitive element are electrically connected, and the source line is The multiple rows of memory cells are electrically connected, and the potential switching circuit is used during the write period. This is a semiconductor device equipped with the function of selectively supplying ground potential to the source line.

[0016] Furthermore, in the above-described semiconductor device, the second channel formation region includes an oxide semiconductor. It is desirable that this be done.

[0017] Furthermore, in the semiconductor device described above, the second transistor is less than the first transistor. It is preferable that both are provided overlapping with a portion of the other.

[0018] Furthermore, in the above-described semiconductor device, the first channel formation region is composed of silicon. It's okay if it's not allowed.

[0019] Furthermore, in the above semiconductor device, the second transistor is an n-channel type transistor You may also use "ta".

[0020] Another aspect of the present invention includes a bit line, a source line, a plurality of write word lines, and multiple A number of write and read word lines, and a memory cell array containing multiple memory cells, A method for driving a semiconductor device having a first gate electrode, wherein one of the memory cells is a first gate electrode, a first A p-channel type comprising a source electrode, a first drain electrode, and a first channel-forming region. The first transistor, the second gate electrode, the second source electrode, the second drain electrode, The first has a second transistor including a second channel formation region and a capacitive element, and The gate electrode, the second drain electrode, and one electrode of the capacitive element are electrically connected. A node is formed in which the charge is held, and a bit line, a first source electrode, and a second source electrode The electrode and the first drain electrode are electrically connected, and the source wire and the first drain electrode are electrically connected. One of the write word lines and the second gate electrode are electrically connected, allowing for writing and reading. One of the outgoing word lines and the other electrode of the capacitive element are electrically connected during the writing period. In this configuration, a ground potential is supplied to the source line, and during the readout period, the memory cells that are not selected are... A semiconductor device that supplies power potential to one of the write and read word lines connected to one of the write and read word lines. This is the method of driving the device.

[0021] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. do not have.

[0022] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to that. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes." This also includes cases where "or wiring" is formed as a single unit.

[0023] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0024] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0025] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0026] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, in the event of no power supply (however, Even if the electrical potential is fixed, the memory contents can be retained over a long period of time. It is possible.

[0027] Furthermore, the semiconductor device according to the disclosed invention does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved. Also, to erase information Another advantage is that it requires no action.

[0028] Furthermore, the readout transistors utilize materials other than oxide semiconductors to ensure sufficient high-speed operation. Using a transistor capable of this, the writing transistor uses an oxide semiconductor transistor. By combining it with a stator, the operation of semiconductor devices (for example, information readout operations) can be improved. Sufficient speed can be ensured. In addition, transients using materials other than oxide semiconductors This enables the optimal realization of various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. It is possible.

[0029] Thus, transistors using materials other than oxide semiconductors (in other words, sufficiently high-speed operation) Transistors capable of operation (and transistors using oxide semiconductors (in a broader sense, sufficiently) By integrating a transistor with a low off-current, it possesses unprecedented features. This enables the realization of semiconductor devices. [Brief explanation of the drawing]

[0030] [Figure 1] Circuit diagram of a semiconductor device. [Figure 2] Circuit diagram of a semiconductor device. [Figure 3] Circuit diagram of a semiconductor device. [Figure 4] Timing chart. [Figure 5] Cross-sectional and plan views of a semiconductor device. [Figure 6] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 7] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 8] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 9] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 10] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 11] A diagram illustrating electronic devices using semiconductor devices. [Figure 12] A diagram illustrating the crystal structure of oxide materials. [Figure 13] A diagram illustrating the crystal structure of oxide materials. [Figure 14] A diagram illustrating the crystal structure of oxide materials. [Figure 15] A diagram illustrating the gate voltage dependence of the mobility obtained through calculation. [Figure 16] A diagram illustrating the gate voltage dependence of drain current and mobility obtained through calculations. [Figure 17] A diagram illustrating the gate voltage dependence of drain current and mobility obtained through calculations. [Figure 18] A diagram illustrating the gate voltage dependence of drain current and mobility obtained through calculations. [Figure 19]A diagram illustrating the cross-sectional structure of the transistor used in the calculations. [Figure 20] This figure shows a graph illustrating the transistor characteristics using an oxide semiconductor film. [Figure 21] This figure shows the Vg-Id characteristics of the transistor in sample 1 after the BT test. [Figure 22] This figure shows the Vg-Id characteristics of the transistor in sample 2 after the BT test. [Figure 23] This figure shows the dependence of Id and field-effect mobility on Vg. [Figure 24] A diagram showing the relationship between substrate temperature and threshold voltage, and the relationship between substrate temperature and field-effect mobility. [Figure 25] A figure showing the XRD spectra of sample A and sample B. [Figure 26] A diagram showing the relationship between the transistor's off-current and the substrate temperature during measurement. [Figure 27] Top view and cross-sectional view of a coplanar top-gate, top-contact transistor using an In-Sn-Zn-O film as the oxide semiconductor film. [Figure 28] A top view and a cross-sectional view showing the structure of the transistor fabricated in Example 2. [Modes for carrying out the invention]

[0031] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0032] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0033] Furthermore, in this specification, ordinal numbers such as "1st," "2nd," and "3rd" are used in relation to the constituent elements. This note is added to avoid ambiguity and does not indicate a numerical limitation.

[0034] (Embodiment 1) In this embodiment, the basic circuit configuration of a semiconductor device according to one aspect of the disclosed invention and The operation will be explained with reference to Figures 1 and 2. Note that in the circuit diagram, oxide In some cases, the "OS" designation is added to indicate that it is a transistor made of semiconductor material. ru.

[0035] <Basic circuit 1> First, the most basic circuit configuration and its operation will be explained with reference to Figure 1. In the semiconductor device shown in 1(A-1), the bit line BL and the source power of transistor 160 The electrode (or drain electrode) and the source electrode (or drain electrode) of transistor 162. And are electrically connected, the source wire SL and the drain electrode of transistor 160 (or The source electrode is electrically connected. Also, the writing word line OSG and the transistor It is electrically connected to the gate electrode of transistor 162. And transistor 160 The gate electrode of the transistor and the drain electrode (or source electrode) of transistor 162 are capacitive elements. One of the 164 electrodes is electrically connected to the write and read word line C, and the capacitance element The other electrode of child 164 is electrically connected. Note that the source power of transistor 160 The electrode (or drain electrode) and the source electrode (or drain electrode) of transistor 162. Alternatively, instead of electrically connecting them, each could be electrically connected to a separate wire. .

[0036] Here, for example, a transistor using an oxide semiconductor is applied to transistor 162. Transistors using oxide semiconductors have the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, transistor 160 It is possible to maintain the potential of the gate electrode for an extremely long period of time. And the capacitance element Having child 164 helps retain the charge applied to the gate electrode of transistor 160. This makes it easier to retrieve the stored information.

[0037] The semiconductor material of transistor 160 is not particularly limited. From the perspective of improving performance, for example, transistors using single-crystal silicon, It is preferable to use transistors with high switching speeds. However, transistors For the 160, a p-channel type transistor shall be used.

[0038] Furthermore, as shown in Figure 1(B), it is also possible to omit the capacitive element 164. .

[0039] In the semiconductor device shown in Figure 1(A-1), the potential of the gate electrode of transistor 160 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0040] First, we will explain how to write and retain information. First, the writing word line OSG The potential is set to the potential that turns on transistor 162, and transistor 162 is turned on. This is the state. As a result, the potential of the bit line BL becomes the drain electrode of transistor 162 ( (or source electrode), gate electrode of transistor 160, and one electrode of capacitive element 164 The poles are given to electrically connected nodes (also referred to as node FG). A predetermined charge is applied (written) to code FG. Here, two different potentials are applied. A charge that gives a low potential (hereinafter referred to as charge Q) L Charge Q, which gives a high potential H That One of the following will be given. Furthermore, three or more different potentials will be given. The memory capacity may be improved by applying electric charge. Then, the potential of the write word line OSG is... The potential is set such that transistor 162 is in the off state, and transistor 162 is in the off state. By doing so, the charge applied to node FG is retained (held).

[0041] Because the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0042] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the source line SL. In this state, when an appropriate potential (read potential) is applied to the write and read word line C, Depending on the amount of charge held at node FG, the bit line BL takes on different potentials. That is, The conductance of transistor 160 is the gate electrode (node ​​FG) of transistor 160. It is controlled by the charge held in (or, as it could be said).

[0043] Generally, if transistor 160 is a p-channel type, the gate electrode of transistor 160 Q H The apparent threshold V giventh_H is lower than the apparent threshold value V when Q is applied to the gate electrode of the transistor 160. For example, L in writing, when Q is applied, if the potential of the write and read word line C th_L is at V0 (a potential intermediate between V and V L ), the transistor 160 will be in the "on state". When Q is applied, even if the potential of the write and read word line C is at V0, the transistor 160 remains in the "off state". Therefore, by discriminating the potential of the bit line BL, the stored information can be read out. th_H and V th_L ), the transistor 160 will be in the "on state". When Q is applied, even if the potential of the write and read word line C is at V0, the transistor 160 remains in the "off state". Therefore, by discriminating the potential of the bit line BL, the stored information can be read out. H When Q is applied, even if the potential of the write and read word line C is at V0, the transistor 160 remains in the "off state". Therefore, by discriminating the potential of the bit line BL, the stored information can be read out. Thus, by discriminating the potential of the bit line BL, the stored information can be read out. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the above-described writing and

[0044] holding of information. That is, the potential of the write word line OSG is set to a potential at which the transistor 162 is turned on, turning on the transistor 162. As a result, the potential of the bit line BL (the potential related to the new information) is applied to the node FG. Then, the write word line OSG is set to a potential at which the transistor 162 is turned off, turning off the transistor 1 <00005!4>62, so that the node FG assumes a state in which a charge related to the new information is applied. word line OSG is set to a potential at which the transistor 162 is turned off, turning off the transistor 1 62, so that the node FG assumes a state in which a charge related to the new information is applied. Thus, the semiconductor device according to the disclosed invention can directly rewrite information by rewriting the information again. Therefore, it is not necessary to extract charges from the floating gate using a high voltage required in a flash memory or the like, and an erasing operation

[0045] is not required. is not required. is not required. This can suppress the decrease in operating speed caused by this. In other words, high-speed operation of semiconductor devices is possible. It will be revealed.

[0046] Below is an example of applying either the potential VDD or the ground potential GND to node FG. The methods for writing, holding, and reading in this case will be explained in detail below. When a potential VDD is applied to G, the data retained is data "1", and the ground potential is set to node FG. The data retained when GND is applied will be set to data "0". The relationship between potentials is not limited to this.

[0047] When writing information, set the source line SL to GND, and the write and read word line With C as GND and the write word line OSG as VDD, turn on transistor 162. This is the state. And when writing data "0" to node FG, bit line BL will have G Give ND. Also, when writing data "1" to node FG, the bit line BL is powered. Let the position be VDD. Note that when writing data "1" to node FG, the transistor To prevent a voltage drop equal to the threshold voltage (Vth_OS) of 162, write word line OS The potential of G may also be VDD + Vth_OS.

[0048] To retain information, connect the write word line OSG to GND and transistor 162. Turn it off. Also, via transistor 160, which is a p-channel transistor, In order to suppress the generation of current and power consumption in the bit line BL and source line SL, The bit line BL and the source line SL are at the same potential. In this case, the write and read word line C can be either VDD or GND.

[0049] Furthermore, in the above, "same potential" includes "approximately the same potential." That is, In the above, the potential difference between the bit line BL and the source line SL is sufficiently reduced, and the bit line BL The purpose is to suppress the current generated in the source line SL, therefore the potential of the source line SL Compared to fixing it to GND, the power consumption can be reduced sufficiently (for example, to less than one-hundredth). This includes potentials that can be reduced, and other potentials that are considered "approximately the same potential." Also, for example, wiring resistance... Differences in potential shifts caused by resistors, etc., are perfectly acceptable.

[0050] When reading information, set the write word line OSG to GND, and write and read With the word line C as GND, and the source line SL at VDD or a potential slightly lower than VDD, the word line C is connected to GND. (Hereafter referred to as VR). Here, the data "1" is written to node FG. In this case, transistor 160, which is a p-channel transistor, is in the off state, and the bit The potential of line BL is maintained at the potential at the start of readout, or it increases. Maintaining or raising the potential of line BL depends on the readout circuit connected to bit line BL. Additionally, if the data "0" is written to node FG, transistor 160 turns on. In this state, the potential of the bit line BL is the same as the potential of the source line SL, and VDD or VR is at the same potential. Therefore, by determining the potential of the bit line BL, the data held at node FG can be obtained. You can read either "1" or "0".

[0051] Note that the potential VDD is held in node FG (i.e., data "1" is written). If (this is the case), then when reading, if the potential of the source line SL is VDD, then transistor 16 The voltage between the gate and source of a 0 (hereinafter referred to as Vgsp) is given by Vgsp = VDD - VD D=0V, and Vgsp becomes the threshold voltage of transistor 160 (hereinafter referred to as Vth_p). Because it becomes larger than (as noted), the p-channel transistor transistor 160 It turns off. At this point, if the potential written to node FG is less than VDD, etc. Even if the potential held at node FG is less than VDD, the potential of node FG is If VDD is greater than or equal to |Vth_p|, then Vgsp = (VDD - |Vth_p|) - VDD =-|Vth_p|=Vth_p, so transistor 160 is in the off state, which is normal. Data "1" can be read from there. However, the potential of node FG is VDD-|Vth_p If it is smaller, then Vgsp is smaller than Vth_p, so transistor 160 This will turn on, and instead of reading data "1", data "0" will be read, resulting in a misread. In other words, when data "1" is written, the lower limit of the potential that can be read is, The potential of the wire SL is |Vth_p| lower than VDD, so it becomes VDD-|Vth_p|.

[0052] On the other hand, if the potential of the source line SL is set to VR during readout, then, as mentioned above, data "1 The lower limit of the potential that can be read is |Vth_p |The voltage is lower, so VR-|Vth_p|. Here, VR is at a lower potential than VDD. Therefore, VR-|Vth_p| is smaller than VDD-|Vth_p|. That is, source If the potential of line SL is set to VR, the lower limit of the potential that can be read out will be lower. Using VR instead of VDD for the potential of the source line SL allows for easier reading of data "1". This is preferable because it allows for a wider range of potentials. Regarding the upper limit, see source. When the potential of line SL is VR, Vgsp when VDD is written to node FG VDD-VR>Vth_p (because VDD>VR) and transistor 160 can be used without any problems. It can be put into a state of "F".

[0053] Here, the drain electrode (or source electrode) of transistor 162 and transistor 16 The gate electrode of 0 and one electrode of the capacitive element 164 are electrically connected at node F. G) is a floating gate transistor used as a non-volatile memory element. It performs the same function as a loading gate. When transistor 162 is off, the no Node FG can be seen as embedded in the insulator, and charge is retained at node FG. The off-current of transistor 162, which uses a synthetic semiconductor, is formed by silicon semiconductors, etc. Because it is less than 1 / 100,000th of a transistor, the leakage from transistor 162 is no It is possible to ignore the dissipation of charge accumulated in FG. In other words, using an oxide semiconductor Transistor 162 enables the retention of non-volatile data even without a power supply. It is possible to realize a memory device.

[0054] For example, the off-current of transistor 162 at room temperature (25°C) is 10 Hz (1 Hz (Zepto Amperes are 1 x 10 -21 A) The capacitance value of the capacitive element 164 is approximately 10 fF. In some cases, at least 10 4 Data can be retained for more than a second. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance values.

[0055] Furthermore, in the semiconductor device of the disclosed invention, conventional floating gate type transistor The problem of deterioration of the gate insulating layer (tunnel insulating film) that has been pointed out in the previous report does not exist. In other words, the gate when injecting electrons into a floating gate, which has been a problem in the past This eliminates the problem of deterioration of the insulating layer. This is due to the theoretical limitation of the number of write cycles. This means that it does not exist. Also, conventional floating gate type transients The high voltage required for writing and erasing in the original system is no longer necessary.

[0056] The semiconductor device shown in Figure 1(A-1) consists of elements such as transistors that make up the semiconductor device. It is possible to consider this as including resistance and capacitance, as shown in Figure 1(A-2). In other words, in Figure 1(A-2), transistor 160 and capacitive element 164 are, respectively, It is assumed that it is composed of resistance and capacitance. R1 and C1 are respectively These are the resistance and capacitance values ​​of the capacitive element 164, where the resistance value R1 constitutes the capacitive element 164. This corresponds to the resistance value due to the insulating layer. Also, R2 and C2 are, respectively, transistors. The resistance and capacitance values ​​are 160, and the resistance value R2 is when transistor 160 is ON. This corresponds to the resistance value due to the gate insulating layer, and the capacitance value C2 is the so-called gate capacitance (gate electrode and, Capacitance formed between the source electrode or drain electrode, and the gate electrode and channel type This corresponds to the capacity value of the volume formed between the constituent region and the surrounding region.

[0057] The resistance between the source and drain electrodes when transistor 162 is in the off state (actual) If ROS (also called effective resistance) is defined as the gate leakage current of transistor 162 is sufficiently small. Under the given conditions, if R1 and R2 satisfy R1 ≥ ROS and R2 ≥ ROS, The charge retention period (which can also be called the information retention period) is mainly determined by transistor 162 This will be determined by the off-current.

[0058] Conversely, if the above conditions are not met, the off-current of transistor 162 will be sufficiently small. However, it becomes difficult to ensure a sufficient retention period. Other than the off-current of transistor 162. The leakage current (for example, the leakage current that occurs between the source electrode and the gate electrode) is large. Therefore, the semiconductor device disclosed in this embodiment has R1 ≥ RO It is desirable that the relationship between S and R2 ≥ ROS is satisfied.

[0059] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2. Therefore, when controlling the potential of node FG by the write and read word line C, To efficiently supply the potential of the write and read word line C to node FG. This results in a potential difference between the write and read word lines C (for example, the read potential and This is because it allows the potential difference (non-readout potential) to be kept low.

[0060] Thus, by satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. Yes. Note that R1 and R2 are the gate insulating layer of transistor 160 and the capacitive element 164. It is controlled by the insulating layer. The same applies to C1 and C2. Therefore, gate insulation It is desirable to appropriately set the material and thickness of the layers so as to satisfy the above-mentioned relationship.

[0061] In the semiconductor device shown in this embodiment, node FG is a flow such as flash memory. It functions similarly to the floating gate of a ting-gate transistor, but in this implementation... The node FG in this form has characteristics that are fundamentally different from floating gates such as flash memory. It has.

[0062] In flash memory, the potential applied to the control gate is high, so that potential is To avoid affecting the floating gates of adjacent cells, the spacing between cells is... It becomes necessary to maintain a certain level of integration. This is one of the factors that hinders the high integration of semiconductor devices. And the factor in question is a flash current generated by applying a high electric field. This stems from the fundamental principles of spearfishing.

[0063] On the other hand, the semiconductor device according to this embodiment is a transistor switch using an oxide semiconductor. It operates by tunneling and does not use the principle of charge injection by tunnel current as described above. In other words, it does not require a high electric field for charge injection, as in flash memory. Therefore, there is no need to consider the effect of the high electric field from the control gate on adjacent cells. Therefore, high integration becomes easier.

[0064] Furthermore, the fact that a high electric field is not required and large peripheral circuits (such as boost converters) are not needed is also a plus. This is an advantage over Shmemo. For example, the memory cell according to this embodiment is The maximum voltage (the difference between the maximum and minimum potentials applied simultaneously to each terminal of the memory cell) The maximum value is 5V or less when writing 2-stage (1-bit) information to a single memory cell. Preferably, the voltage can be set to 3V or less.

[0065] Furthermore, the relative permittivity εr1 of the insulating layer constituting the capacitive element 164 and the transistor 160 are If the relative permittivity εr2 of the insulating layer is to be different, the insulating element 164 is to be composed of an insulating The area S1 of the layer and the area S2 of the insulating layer that constitutes the gate capacitance in the transistor 160 However, the goal is to achieve C1 ≥ C2 while satisfying 2·S2 ≥ S1 (preferably S2 ≥ S1). This is easy. That is, while reducing the area of ​​the insulating layer constituting the capacitive element 164, C1 It is easy to achieve ≥C2. Specifically, for example, the insulating element that constitutes the capacitive element 164 In the marginal layer, a film made of high-k material such as hafnium oxide, or hafnium oxide A layered structure is adopted consisting of a film made of high-k materials such as εr and a film made of oxide semiconductors. 1 is set to 10 or more, preferably 15 or more, and in the insulating layer constituting the gate capacitance, oxidation By using silicon, εr² can be set to 3-4.

[0066] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be made even more advanced. Integration is possible.

[0067] <Basic circuit 2> Figure 2 shows a memory where the memory cells shown in Figure 1(A-1) are arranged in a 2x2 matrix. This is a circuit diagram of the cell array. The configuration of memory cell 170 in Figure 2 is the same as in Figure 1(A-1) and The same applies. However, in Figure 2(A), the source line SL is in a memory cell with two rows. It has a common structure. Also, in Figure 2(B), the source line SL is in two rows. It has a common structure in Morissel.

[0068] As shown in Figures 2(A) and 2(B), the source lines SL are common in two columns or two rows. By creating a standardized structure, the number of signal lines connected to the memory cell 170 is not standardized. The number of tubes can be reduced from 4 to 3.5 (3 + 1 / 2).

[0069] Furthermore, the number of columns (or rows) for which source lines SL are shared is limited to 2 columns (2 rows). Rather, in memory cells with three or more columns (or rows), It may also be a continuous structure. The number of columns (or rows) of the source lines SL to be standardized is for standardization. Considering the parasitic resistance and parasitic capacitance, suitable values ​​should be selected as appropriate. The more columns (or rows) there are, the fewer signal lines can be connected to the memory cell 170. This is preferable because it allows for this.

[0070] In Figure 2, source line SL is connected to source line switching circuit 194. The source line switching circuit 194 has a source line switching signal line SLC in addition to the source line SL. It is connected to this.

[0071] In the semiconductor device shown in Figures 2(A) and 2(B), data writing, holding, and The reading process is the same as in Figure 1, and the above description can be taken into consideration. For example, when either the power supply potential VDD or the ground potential GND is applied to node FG. When a power potential VDD is applied to node FG, the data retained is data "1", no When ground potential GND is applied to FG, the data retained is set to data "0". The specific writing operation is as follows: First, the memory cell 170 is connected The potential of the write and read word line C is set to GND, and the write word line OSG is set to VD Select memory cell 170 as D. This will change the potential of bit line BL to the selected It is supplied to node FG of memory cell 170.

[0072] Here, if the ground potential GND is applied to node FG (i.e., data "0" is retained) If this occurs, the gate electrode of transistor 160 will be given a potential that turns it on. In that case, current will be generated in the bit line BL and the source line SL, and node FG To suppress the rise in potential when writing, the potential of the source line SL is set to the ground potential GND. It is necessary to do so.

[0073] Therefore, the signal from the source line switching signal line SLC controls the signal of the source line switching circuit 194. By switching the circuit path, the ground potential (GND) is supplied to the source line SL.

[0074] A key feature of this operation is that, during writing, the potential of the source line SL is set to the ground potential GND. It is located there. This provides node FG with a potential that turns on transistor 160. Even in such cases, it is possible to suppress the generation of current in the bit line BL and source line SL.

[0075] Furthermore, as shown in Figure 2, when the memory cells 170 are arranged in an array, the reading During retrieval, it is necessary to be able to read only the information from the desired memory cell 170. Then, the information of a predetermined memory cell 170 is read, and the information of the other memory cells 170 is read. To prevent this from happening, it is necessary to deselect the memory cell 170 that is not to be read.

[0076] For example, as shown in Basic Circuit 1, the node FG can be connected to the power supply potential VDD or the ground potential GND. If either of the above is given, and the power supply potential VDD is given to node FG, it is retained. The data is designated as "Data 1," and the data is retained when a ground potential GND is applied to node FG. When the data is set to "0", the source line SL is set to GND, and writing and reading are performed. By setting the output word line C to VDD and the write word line OSG to GND, a memory cell is formed. 170 can be deselected.

[0077] By setting the write and read word line C to VDD, the potential of node FG is determined by the capacitive element The capacitance coupling with 164 increases by the amount of VDD. VDD, which has data "1", is at node FG. If it is written there, it rises by VDD, so VDD + VDD = 2VDD, and Vgs Since p is greater than Vth_p, the transistor is a p-channel type transistor. 160 is in the OFF state. Meanwhile, GND, which has data "0", is written to node FG. If present, it rises by VDD, so GND + VDD = VDD, and Vgsp becomes Vth_p Because the size also increases, transistor 160, which is a p-channel type transistor, is in the off state. That is, by making the write and read word line C VDD, node FG Regardless of the data held therein, transistor 160 is turned off, i.e., the memory cell 170 can be deselected.

[0078] Let's assume that an n-channel transistor is used for the readout transistor 160. And, the potential of the gate electrode of the n-channel transistor is higher than the threshold voltage of the transistor. If this happens, even if the write and read word line C is set to 0V, all memory cells will remain. It is not always possible to turn it off. Therefore, in order to deselect the memory cell, It is necessary to supply a negative potential to the word line C for writing and reading the selected row. However, In the semiconductor device shown in this embodiment, a p-channel transistor is used for reading. Because a zista is used, the write and read word line C of the unselected row is set to a high potential. This makes it possible to turn off the memory cell. Therefore, in the memory cell, negative Since there is no need to provide a power supply to generate the electric potential, power consumption is reduced, and semiconductor devices It can be miniaturized.

[0079] As shown above, in the semiconductor device with the circuit configuration shown in Figure 2, multiple source lines SL are arranged in rows (and By standardizing the code (multiple lines), the area of ​​the memory cell array can be reduced. This enables a reduction in die size. Furthermore, by reducing the die size, semiconductor equipment This can reduce manufacturing costs or improve yield.

[0080] <Application Example 1> Next, we will discuss a more specific circuit configuration and operation using the circuit shown in Figure 1, as shown in Figure 3 and Please refer to Figure 4 for explanation. Note that in the following explanation, the writing transistor (transistor) will be referred to as a "transistor". An n-channel transistor is used for the transistor (transistor 162), and a readout transistor (transistor The example will be explained using a p-channel transistor in ZISTA 160). Note that Figure 3 In the circuit diagram, wires with diagonal lines are bus signal lines.

[0081] Figure 3 is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. The configuration of memory cell 170 in 3 is the same as in Figure 1(A-1).

[0082] The semiconductor device shown in Figure 3 has m write word lines OSG (where m is an integer greater than or equal to 2) and m lines The write and read word line C, the n bit lines BL (where n is an integer greater than or equal to 2), and The SL lines and memory cells 170 are arranged in a matrix of m rows x n columns. A memory cell array, a boost circuit 180, and a first drive circuit 1 including an address decoder 82, a second drive circuit 192 including a low driver, and a third drive including a page buffer Circuit 190, a fourth drive circuit 184 including a controller, and a fifth drive circuit including an input / output control circuit. It has a drive circuit 186 and a source line switching circuit 194. The number of drive circuits However, this is not limited to Figure 3; a combination of drive circuits having each function may also be used. Alternatively, the functions included in each drive circuit may be divided and used separately.

[0083] In the semiconductor device shown in Figure 3, the first drive circuit 182 includes an address decoder. The decoder decodes the address selection signal line A and the decoded address selection signal The output is sent to the row selection signal line RADR and the page buffer address selection signal line PBADR. It is a path. Address selection signal line A is connected to the row-direction address selection signal of memory cell 170, This is the terminal to which the address selection signal for the page buffer is input, and the number of rows of memory cell 170, The number of row selection signal lines (RAD) varies depending on the number of columns or the page buffer configuration. R is a signal line that specifies the row address of a memory cell. Page buffer address The selection signal line PBADR is a signal line that specifies the address of the page buffer.

[0084] The second drive circuit 192 includes a low driver. The low driver is connected to the first drive circuit 182. Based on the signal from the row selection signal line RADR output from the address decoder included in the system, Row direction selection signal for memory cell 170, signal to write word line OSG, write and It outputs a signal to the read word line C.

[0085] The boost circuit 180 is connected to the second drive circuit 192 by wiring VH-L, and the boost circuit 1 The constant potential input to 80 (for example, the power supply potential VDD) is boosted, and the second drive circuit 19 2 outputs a potential (VH) higher than the constant potential. Write to node FG of memory cell 170. The potential to be written is set to the threshold voltage (Vt) of transistor 162, which is the writing transistor. To prevent a drop of h_OS, the potential of the write word line OSG is set to a bit The potential of line BL must be higher than +Vth_OS. Therefore, for example, node F When writing the power supply potential VDD to G, VH should be greater than or equal to VDD + Vth_OS. And, if there is no problem even if the potential written to node FG drops by Vth_OS, then It is not necessary to provide the pressure circuit 180.

[0086] The third drive circuit 190 includes a page buffer. The page buffer has a data latch and a It has the function of a signal amplifier. Its function as a data latch is through the internal data input / output signal lines. The data output from INTDIO or bit line BL is temporarily stored, and the storage The generated data is output to the internal data input / output signal line INTDIO or the bit line BL. The function of the sense amplifier is to output data from the memory cell via the bit line during readout. Sense the BL (Blue Line).

[0087] The fourth drive circuit 184 includes a controller and chip enable bar signal line CEB, Signal from the lead enable bar signal line WEB, or the lead enable bar signal line REB. From there, the first drive circuit 182, the second drive circuit 192, the third drive circuit 190, and the fifth drive Generates signals to control the drive circuit 186, the source line switching circuit 194, and the boost circuit 180. It is a circuit.

[0088] The chip enable bar signal line CEB is a signal line that outputs the selection signal for the entire circuit, and Only in active mode does it accept input signals and output output signals. The navel bar signal line WEB latches the page buffer data in the third drive circuit 190. This is a signal line that outputs a signal that allows writing to the memory cell array. Additionally, the read enable bar signal line REB allows data to be read from the memory cell array. This is a signal line that outputs a signal that enables the operation. The fourth drive circuit 184 is a boost circuit control signal. It is connected to the boost circuit 180 by line BCC. The boost circuit control signal line BCC is Wiring that transmits the control signal of the boost circuit output from the controller in the drive circuit 184 of 4. Therefore, the number of wires will range from 0 to multiple depending on the circuit configuration. Also, the fourth drive circuit 184 is p It is connected to the third drive circuit 190 by the dibuffer control signal line PBC. The buffer control signal line PBC is output from the controller in the fourth drive circuit 184. These are the wires that transmit the control signals for the buffer, and the number of wires can range from zero to multiple depending on the circuit configuration. Furthermore, the fourth drive circuit 184 is controlled by the low driver control signal line RDRVC, which controls the second drive It is connected to the drive circuit 192. The fourth drive circuit 184 receives the source line switching signal. It is connected to the source line switching circuit 194 by the line SLC.

[0089] The source line switching circuit 194 is a circuit that switches the potential of the source line SL based on the source line switching signal from the controller in the fourth drive circuit 184. The source line switching circuit 194 only needs to have the function of switching the potential of the source line SL, and a multiplexer, an inverter, etc. may be used. The source line switching signal line SLC is a wiring that transmits a signal for switching the potential of the source line SL output from the controller in the fourth drive circuit 184 There is. Depending on the circuit configuration, the number of signal lines is one to a plurality of lines.

[0090] The fifth drive circuit 186 includes an input / output control circuit. The input / output control circuit outputs the input signal from the data input / output signal line DIO to the internal data input / output signal line INTDIO, or outputs the input signal from the internal data input / output signal line INTDIO to the data input / output signal line DIO. The data input / output signal line DIO terminal is a terminal where external data is input or memory data is output to the outside. Depending on the circuit configuration, the number of signal lines is one to a plurality of lines. The internal data input / output signal line INTDIO is a signal line that inputs the output signal of the input / output control circuit to the page buffer or inputs the output signal of the page buffer to the input / output control circuit. Depending on the circuit configuration, the number of signal lines is one to a plurality of lines. Also, the data input / output signal line DIO may be divided into a data input signal line and a data output signal line.

[0091] In the semiconductor device shown in FIG. 3, the writing, holding, and reading of data are basically the same as in the cases of FIGS. 1 and 2. FIG. 4 shows the writing and reading of the semiconductor device according to FIG. 3 An example of a timing chart related to the output operation is shown. Specifically, the latch operation of the page buffer. The operation of writing data to the memory cell array, and the data written to the memory cell array. This section describes an example of the process of reading data and latching it into the page buffer. The names CEB, WEB, etc. in the chart refer to the wiring to which the potential shown in the timing chart is applied. This indicates that if there are multiple wires with similar functions, the name of the wire will be followed by "1". They are distinguished by the addition of m, n, etc. Note that the disclosed invention is not limited to the arrangement shown below. Furthermore, in the circuit configuration shown in this embodiment, CEB, WEB, and REB are at low potential. It becomes active when a certain input is received, but it becomes active when a High potential is received. You may use a circuit like that.

[0092] Let the number of memory cells be (m × n). The memory cell in the first row and first column contains the data "1", and the memory cell in the first row and nth column... Memory cell contains data "0", memory cell in row m, column 1 contains data "0", memo in row m, column n When writing the data "1" to each recell and then reading all the written data: This shows the potential relationship between each wire.

[0093] During the writing period, first the chip enable bar signal line CEB is set to low potential, and The address of memory cell 170 to be written to is specified via the response selection signal line A. Then, Writing is performed by setting the write enable bar signal line WEB to low potential. The buffer outputs the latch data, which is the data to be written, to the bit line BL. This includes the write word line OSG for selected rows and the write and read word line C for unselected rows. It outputs a high potential to the write word line of the unselected row and the write and read lines of the selected row. Output a low potential to the output word line C.

[0094] During the writing period, data is written to the bit line BL in accordance with the timing of row selection. The output is from the page buffer. When writing data "1", the bit line BL is High. When writing data "0" at h potential, the bit line BL will be at low potential. The signal input period for line BL is the write word line OSG of the selected line, and the write and The signal input period of the read word line C should be longer than the signal input period of the bit line BL. This is because if the interval is too short, incorrect data writing to the memory cell may occur.

[0095] Furthermore, if the ground potential GND is applied to node FG during the writing period, To suppress the generation of current in the bit line BL and source line SL, the potential of the source line SL The ground potential (GND) is set. The drive is controlled by the signal on the source line switching signal line SLC. This is done by switching the signal path of the line switching circuit 194.

[0096] During the readout period, first the chip enable bar signal line CEB is set to low potential, and Specify the address of memory cell 170 from which to read from the response selection signal line A. Then, Readout is performed by setting the read enable bar signal line REB to a low potential. The buffer latches the data read from the memory cell to the bit line BL. The b outputs a low potential to the write and read word line C of the selected line, and to the write line of the unselected line. High potential is output to the write and read word line C. The write word line OSG is Regardless of whether it is selected or not, the potential becomes low. The source line switching circuit 194 is source line Output a high potential to the SL.

[0097] During the read period, in accordance with the timing of row selection, a potential corresponding to the data written as 0 in the memory cell 17 is output to the bit line BL. If the data "1" is written in the memory cell, the bit line BL becomes a low potential, and if the data "0" is written, the bit line BL becomes a high potential. If the data "1" is written in the memory cell, the bit line BL becomes a low potential, and if the data "0" is written, the bit line BL becomes a high potential. If the data "1" is written in the memory cell, the bit line BL becomes a low potential, and if the data "0" is written, the bit line BL becomes a high potential.

[0098] During the standby and data retention periods, the chip enable bar signal line CEB is set to a high potential to make the entire circuit shown in FIG. 3 inactive. In this case, since neither writing nor reading is performed, the control signals such as WEB and REB may be either high potential or low potential. During the standby and data retention periods, the chip enable bar signal line CEB is set to a high potential to make the entire circuit shown in FIG. 3 inactive. In this case, since neither writing nor reading is performed, the control signals such as WEB and REB may be either high potential or low potential. During the standby and data retention periods, the chip enable bar signal line CEB is set to a high potential to make the entire circuit shown in FIG. 3 inactive. In this case, since neither writing nor reading is performed, the control signals such as WEB and REB may be either high potential or low potential. During the standby and data retention periods, the chip enable bar signal line CEB is set to a high potential to make the entire circuit shown in FIG. 3 inactive. In this case, since neither writing nor reading is performed, the control signals such as WEB and REB may be either high potential or low potential.

[0099] Note that the shaded portion in the timing chart of FIG. 4 may be either a high potential or a low potential. Note that the shaded portion in the timing chart of FIG. 4 may be either a high potential or a low potential.

[0100] As described above, in the semiconductor device having the circuit configuration shown in FIG. 3, by sharing the source lines SL in a plurality of columns, the area of the memory cell array can be reduced, so that the die size can be reduced. As described above, in the semiconductor device having the circuit configuration shown in FIG. 3, by sharing the source lines SL in a plurality of columns, the area of the memory cell array can be reduced, so that the die size can be reduced. As described above, in the semiconductor device having the circuit configuration shown in FIG. 3, by sharing the source lines SL in a plurality of columns, the area of the memory cell array can be reduced, so that the die size can be reduced. Also, by reducing the die size, the cost of manufacturing the semiconductor device can be reduced, or the yield can be improved.

[0101] Also, in the semiconductor device shown in FIG. 3, when reading is performed, it is necessary to turn off the memory cells of the unselected rows. Since the semiconductor device shown in this embodiment uses a p-channel type transistor for the read transistor, the write and read word lines C of the unselected rows are set to Hi. Also, in the semiconductor device shown in FIG. 3, when reading is performed, it is necessary to turn off the memory cells of the unselected rows. Since the semiconductor device shown in this embodiment uses a p-channel type transistor for the read transistor, the write and read word lines C of the unselected rows are set to Hi. Also, in the semiconductor device shown in FIG. 3, when reading is performed, it is necessary to turn off the memory cells of the unselected rows. Since the semiconductor device shown in this embodiment uses a p-channel type transistor for the read transistor, the write and read word lines C of the unselected rows are set to Hi. By setting the potential to gh (for example, the power supply potential), it is possible to turn off the memory cell. Therefore, there is no need to provide a power supply that generates a negative potential in the memory cell. This allows for reduced power consumption and miniaturization of semiconductor devices.

[0102] Furthermore, the operating method, operating voltage, etc., of the semiconductor device of the disclosed invention are as described above. The configuration is not limited to this, and can be modified as appropriate in the manner in which the operation of the semiconductor device is realized. be.

[0103] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0104] (Embodiment 2) In this embodiment, the configuration of a semiconductor device and a method for manufacturing the same according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 5 to 10.

[0105] <Cross-sectional and planar configurations of semiconductor devices> Figure 5 shows an example of the configuration of a semiconductor device. Figure 5(A) shows a cross-section of the semiconductor device, and Figure 5( Figure B) shows the planes of the semiconductor device. Figure 5(A) is the same as A1-A2 in Figure 5(B). And this corresponds to the cross-section in B1-B2. The semiconductor equipment shown in Figures 5(A) and 5(B) The device has a transistor 160 made of a first semiconductor material at the bottom and a second semiconductor material at the top. It has a transistor 162 made of materials. The first semiconductor material and the second semiconductor material are different It is desirable to use a material that is such that the first semiconductor material is a semiconductor other than an oxide semiconductor. As a material, the second semiconductor material can be an oxide semiconductor. Examples of conductive materials include silicon, germanium, silicon germanium, and silicon carbide. Cone or gallium arsenide can be used, and it is preferable to use a single-crystal semiconductor. Alternatively, organic semiconductor materials may be used. Transigs using such semiconductor materials Transistors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors have certain characteristics. This enables long-term charge retention. The semiconductor device shown in Figure 5 is used as a memory cell. It is possible.

[0106] Furthermore, the technical essence of the disclosed invention is an off-white semiconductor such as an oxide semiconductor for retaining information. Is the key to its success in using a semiconductor material capable of significantly reducing current in transistor 162? Furthermore, the specific components of a semiconductor device, such as the materials used and the structure of the semiconductor device, are explained. It is not necessary to limit ourselves to what is shown here.

[0107] In Figure 5, transistor 160 is a channel provided in the semiconductor layer on the semiconductor substrate 500. A channel-forming region 134 and an impurity region 13 provided so as to sandwich the channel-forming region 134. 2 (also referred to as the source region and drain region) and provided on the channel formation region 134 A gate insulating layer 122a and a channel forming region 134 superimposed on the gate insulating layer 122a It has a gate electrode 128a provided so as to be. Note that in the figure, it is not explicitly stated that In some cases, there may be no drain or traction electrodes, but for convenience, this condition is included in the description. It is sometimes called a transistor. Also, in this case, to explain the connection relationship of transistors... Sometimes, the source region and drain region are included in the term "source electrode" and "drain electrode." In other words, in this specification, the term "source electrode" may include the source region.

[0108] Furthermore, in the impurity region 126 provided in the semiconductor layer on the semiconductor substrate 500, a conductive layer 12 8b is connected. Here, the conductive layer 128b is connected to the source electrode of transistor 160 and It also functions as a drain electrode. In addition, between the impurity region 132 and the impurity region 126 An impurity region 130 is provided. In addition, an insulating layer 1 covers the transistor 160. 36, an insulating layer 138, and an insulating layer 140 are provided. To achieve this, the transistor 160 has a configuration that does not have a sidewall insulating layer, as shown in Figure 5. It is desirable to do so. On the other hand, if the characteristics of transistor 160 are important, the gate A sidewall insulating layer is provided on the side of electrode 128a, and impurities containing regions with different impurity concentrations are present. A material region 132 may also be provided.

[0109] In Figure 5, transistor 162 is an oxide semiconductor layer provided on top of an insulating layer 140, etc. 144 and the source electrode (or drain) electrically connected to the oxide semiconductor layer 144. Electrode) 142a, drain electrode (or source electrode) 142b, and oxide semiconductor layer 144, a gate insulating layer 146 covering the source electrode 142a and the drain electrode 142b, A gate electrode 1 is provided on the gate insulating layer 146 so as to be superimposed on the oxide semiconductor layer 144. It has 48a and

[0110] Here, the oxide semiconductor layer 144 is sufficiently free of impurities such as hydrogen, and It is desirable that the material be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration of the oxide semiconductor layer 144 is 5 × 10⁻⁶. 19 atoms / cm 3 The following is preferable: 5 x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 a toms / cm 3 The following applies. Note that the hydrogen concentration in the oxide semiconductor layer 144 is secondary. Secondary Ion Mass Spectrometry (SIMS) This is measured by (scopy). In this way, the hydrogen concentration is sufficiently reduced to achieve high purity. The defect levels in the energy gap caused by oxygen deficiency are converted and, with sufficient oxygen supply, In the reduced oxide semiconductor layer 144, the carrier concentration is 1 × 10⁻⁶ 12 / cm 3 Less than desired Or, 1 x 10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 Less than and Yes. For example, the off-current at room temperature (25°C) (here, per unit channel width (1 μm) The value of (1 zA) is 100 zA (1 zA (zeptoampere) is 1 × 10⁻¹⁰ -21 A) The following is preferable This becomes 10 zA or less. Thus, the oxidation is i-type (intrinsic) or substantially i-type. By using a semiconductor material, it is possible to obtain a transistor 162 with extremely excellent off-current characteristics. can.

[0111] Furthermore, in transistor 162 of Figure 5, leakage between elements caused by miniaturization is suppressed. To achieve this, an island-shaped oxide semiconductor layer 144 is used, but the island-shaped processing A configuration without this may be adopted. If the oxide semiconductor layer is not processed into an island shape, the processing will be affected. This prevents contamination of the oxide semiconductor layer 144 due to chipping.

[0112] In Figure 5, the capacitive element 164 consists of a drain electrode 142b, a gate insulating layer 146, and a conductive element. It is composed of the electroplating 148b and the capacitive element 164. One electrode functions as one electrode, and the conductive layer 148b functions as the other electrode of the capacitive element 164. This configuration ensures sufficient capacity. Furthermore, when the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked, the drain electricity Sufficient insulation can be ensured between electrode 142b and conductive layer 148b. Furthermore, capacitance If it is not necessary, the configuration can be made without the capacitive element 164.

[0113] In this embodiment, transistor 162 and capacitive element 164 are connected to transistor 160. They are arranged so that at least a portion of them overlap. This type of planar layout is adopted. This allows for higher integration. For example, if the minimum machining dimension is F, then memory... The area occupied by the floor is 15F 2 ~25F 2 It is possible to do so.

[0114] An insulating layer 150 is provided on the transistor 162 and the capacitive element 164. Wiring 154 is provided in the openings formed in the gate insulating layer 146 and the insulating layer 150. Wiring 154 is a wiring that connects one memory cell to another memory cell. This corresponds to the bit line BL in the circuit diagram of Figure 2. Wiring 154 is connected to source electrode 142a, It is connected to the impurity region 126 via the conductive layer 128b. This allows the transient The source region or drain region in transistor 160, and the source region in transistor 162 Compared to connecting electrode 142a to separate wiring, the number of wires is reduced. This allows for an improvement in the integration density of semiconductor devices.

[0115] Furthermore, by providing the conductive layer 128b, the contact between the impurity region 126 and the source electrode 142a The connection point and the connection point between the source electrode 142a and the wiring 154 are provided in an overlapping manner. This can be achieved. By adopting such a planar layout, the contact area causes This can suppress the increase in element area. In other words, it is possible to increase the integration density of semiconductor devices. can.

[0116] <Method for fabricating SOI substrates> Next, Figure 6 shows an example of a method for fabricating an SOI substrate used in the fabrication of the above semiconductor device. Refer to the explanation.

[0117] First, prepare a semiconductor substrate 500 as the base substrate (see Figure 6(A)). Semiconductor substrate 5 For 00, semiconductor substrates such as single-crystal silicon substrates and single-crystal germanium substrates are used. It is possible to use solar cell-grade silicon (SOG-Si:Sola) as a semiconductor substrate. A substrate such as r-grade silicon may also be used. Alternatively, a polycrystalline semiconductor substrate may be used. It may be used. When using solar cell-grade silicon or polycrystalline semiconductor substrates, single crystals may be used. Compared to using silicon substrates or similar materials, manufacturing costs can be reduced.

[0118] Furthermore, instead of semiconductor substrate 500, aluminosilicate glass and aluminoborosilicate glass can be used. Various glass substrates used in the electronics industry, such as barium borosilicate glass, and quartz substrates. Examples include ceramic substrates and sapphire substrates. Also, silicon nitride and aluminum oxide A ceramic substrate with a thermal expansion coefficient close to that of silicon, primarily composed of um, may also be used.

[0119] It is preferable to clean the surface of the semiconductor substrate 500 beforehand. Specifically, For 500 semiconductor substrates, a hydrochloric acid-hydrogen peroxide solution (HPM) and a sulfuric acid-hydrogen peroxide solution are used. Combined solution (SPM), ammonia-hydrogen peroxide solution (APM), dilute hydrofluoric acid (DHF), etc. It is preferable to use [a specific method / tool] for cleaning.

[0120] Next, prepare the bond substrate. Here, a single-crystal semiconductor substrate 510 is used as the bond substrate. (See Figure 6(B)). Note that a single crystal is used as the bond substrate here. The crystallinity of the bond substrate does not need to be limited to single crystal.

[0121] Examples of single-crystal semiconductor substrates 510 include single-crystal silicon substrates and single-crystal germanium substrates. Using single-crystal semiconductor substrates made of Group 14 elements, such as plates and single-crystal silicon germanium substrates. This can be done by using compound semiconductor substrates such as gallium arsenide or indium phosphide. It is also possible to do this. Commercially available silicon substrates include those with a diameter of 5 inches (125 mm) and 6 inches. (150mm), 8 inches (200mm) in diameter, 12 inches (300mm) in diameter, 1 A typical example is a circular one measuring 6 inches (400 mm). Note that single-crystal semiconductor substrate 5 The shape of 10 is not limited to a circle; for example, it may be processed into a rectangle or other shape. Crystal semiconductor substrate 510 is processed using the CZ (Czochralski) method or the FZ (Floating Zone) method. It can be manufactured using the following method.

[0122] An oxide film 512 is formed on the surface of the single-crystal semiconductor substrate 510 (see Figure 6(C)). From the perspective of contaminant removal, before the formation of the oxide film 512, a hydrochloric acid-hydrogen peroxide mixed solution (HPM) Sulfuric acid hydrogen peroxide solution (SPM), ammonia hydrogen peroxide solution (APM), Single crystals are produced using dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. It is preferable to clean the surface of the semiconductor substrate 510. Dilute hydrofluoric acid and ozonated water are discharged alternately. You can take it out and wash it.

[0123] The oxide film 512 may be a single layer or a multilayer of, for example, a silicon oxide film or a silicon oxide nitride film. It can be formed by the following. The above oxide film 512 can be produced by thermal oxidation, CVD Methods include sputtering and other methods. Also, when forming oxide film 512 using the CVD method... To achieve good bonding, tetraethoxysilane (abbreviation: TEOS: chemistry) is used. It is preferable to form a silicon oxide film using an organosilane such as Si(OC2H5)4). It's nice.

[0124] In this embodiment, a single crystal semiconductor substrate 510 is subjected to thermal oxidation treatment to form an oxide film 512 (Here, SiO x A film is formed. Thermal oxidation treatment involves adding halogens to an oxidizing atmosphere. It is preferable to do so.

[0125] For example, a single-crystal semiconductor substrate 510 is subjected to thermal oxidation treatment in an oxidizing atmosphere with added chlorine (Cl). By performing this process, a chlorinated oxide film 512 can be formed. In this case, The oxide film 512 becomes a film containing chlorine atoms. This chlorine oxidation causes exogenous impurities Pure heavy metals (e.g., Fe, Cr, Ni, Mo, etc.) are collected to form metal chlorides. This can be removed to the outside, thereby reducing contamination of the single-crystal semiconductor substrate 510.

[0126] Furthermore, the halogen atoms to be included in the oxide film 512 are not limited to chlorine atoms. It may contain fluorine atoms. A method for fluorine-oxidizing the surface of a single-crystal semiconductor substrate 510 and For example, methods include immersion in an HF solution followed by thermal oxidation in an oxidizing atmosphere, or using NF3. One method involves adding the substance to an oxidizing atmosphere and performing thermal oxidation treatment.

[0127] Next, ions are accelerated by an electric field and irradiated onto the single-crystal semiconductor substrate 510, and by adding them, single-crystal A brittle region 514 with damaged crystal structure is formed at a predetermined depth in the crystalline semiconductor substrate 510 (Figure 6). (See (D)).

[0128] The depth of the region where the brittle region 514 is formed depends on the kinetic energy of the ions, the mass of the ions, and the electrons. It can be adjusted by the angle of incidence of the charge and ions. Also, the embrittlement region 514 is ion It is formed in a region with a depth approximately the same as the average penetration depth of the ions. Therefore, the depth to which ions are added Therefore, the thickness of the single-crystal semiconductor layer separated from the single-crystal semiconductor substrate 510 can be adjusted. For example, the thickness of the single-crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm. The average penetration depth should be adjusted so that it is between m and approximately 200 nm.

[0129] The irradiation treatment with these ions can be carried out using an ion doping device or an ion implantation device. It is possible. A typical example of an ion doping device is one that generates by plasma excitation of process gases. There is a non-mass separation type device that irradiates the object to be treated with all the ion species. This means that the ionic species in the rasma will be irradiated onto the object to be treated without mass separation. In contrast, Ion implantation devices are mass-separation type devices. In ion implantation devices, ion species in the plasma are processed. The ions are separated by mass, and a specific mass of ion species is irradiated onto the object to be treated.

[0130] In this embodiment, hydrogen is added to the single-crystal semiconductor substrate 510 using an ion doping device. Let's explain an example of adding gas. A gas containing hydrogen is used as the source gas. Ion is irradiated. Regarding n, H3 + It would be good to increase the ratio of H + H2 + H3 + Total H3 in relation to quantity + The proportion of [the specified value] should be 50% or more (more preferably 80% or more). H3 + By increasing the proportion of [this component], the efficiency of ion irradiation can be improved.

[0131] Note that the added ions are not limited to hydrogen. Other ions such as helium may also be added. Furthermore, the added ions are not limited to just one type; multiple types of ions may be added. For example However, when irradiating with hydrogen and helium simultaneously using an ion doping device, different Compared to irradiation during the manufacturing process, the number of steps can be reduced, and the subsequent single-crystal semiconductor... It is possible to suppress surface roughness of the layer.

[0132] Furthermore, when forming the embrittlement region 514 using an ion doping device, heavy metals are also added simultaneously. Although it may be added, ion illumination through the oxide film 512 containing halogen atoms By performing this procedure, contamination of the single-crystal semiconductor substrate 510 by these heavy metals can be prevented. can.

[0133] Next, the semiconductor substrate 500 and the single-crystal semiconductor substrate 510 are placed facing each other, and the oxide film 512 is used to... This causes the semiconductor substrate 500 and the single-crystal semiconductor substrate 510 to bond together. (See Figure 6(E)). Note that the semiconductor substrate 5 to be bonded to the single crystal semiconductor substrate 510 An oxide film or nitride film may be formed on the surface of 00.

[0134] During bonding, 0. 001 N / cm 2 More than 100N / cm 2 For example, 1 N / cm 2 More than 20N / cm 2 It is desirable to apply the following pressure. Applying pressure brings the bonding surfaces closer together and tightly adheres to each other. In the area where they are in close contact, a bond is formed between the semiconductor substrate 500 and the oxide film 512, and in that area Spontaneous point junctions extend across almost the entire surface. These junctions involve van der Waals forces and hydrogen The bonding is active and can be performed at room temperature.

[0135] Before bonding the single-crystal semiconductor substrate 510 and the semiconductor substrate 500, It is preferable to perform surface treatment on the surface related to the single crystal semiconductor. This improves the bonding strength at the interface between the substrate 510 and the semiconductor substrate 500.

[0136] Surface treatments include wet treatment, dry treatment, or a combination of wet and dry treatment. Combining can be used. Also, different wet treatments can be used in combination. You can use one method, or you can combine different dry treatments.

[0137] Furthermore, after bonding, heat treatment may be performed to increase the bonding strength. The processing temperature is set to a temperature at which separation does not occur in the embrittlement region 514 (for example, above room temperature, up to 400°C). (Less than) Also, while heating within this temperature range, the semiconductor substrate 500 and the oxide film 512 The parts may be joined together. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, or RTA (instantaneous). Thermal annealing (Rapid Thermal Annealing) equipment, microwave heating equipment, etc. These can be used. However, the above temperature conditions are merely examples, and the disclosed invention may vary. This interpretation is not intended to be limited to this one aspect.

[0138] Next, by performing a heat treatment, the single-crystal semiconductor substrate 510 is separated in the embrittlement region. A single-crystal semiconductor layer 516 is formed on the semiconductor substrate 500 via an oxide film 512 (Figure 6( See F).

[0139] Furthermore, it is desirable that the heat treatment temperature during the above separation is as low as possible. The lower the temperature at which the process is performed, the more effectively surface roughening of the single-crystal semiconductor layer 516 can be suppressed. For example, the heat treatment temperature during the above separation should be between 300°C and 600°C. A temperature between 400°C and 500°C is more effective.

[0140] Furthermore, after separating the single-crystal semiconductor substrate 510, the single-crystal semiconductor layer 516 is treated with 50 Heat treatment is performed at a temperature of 0°C or higher to reduce the concentration of hydrogen remaining in the single-crystal semiconductor layer 516. You may do so.

[0141] Next, by irradiating the surface of the single-crystal semiconductor layer 516 with laser light, the surface flatness is determined. A single-crystal semiconductor layer 518 is formed with improved performance and reduced defects (see Figure 6(G)). Alternatively, heat treatment may be performed instead of laser irradiation.

[0142] In this embodiment, immediately after the heat treatment related to the separation of the single-crystal semiconductor layer 516, Although laser light irradiation is performed, one aspect of the present invention is not limited to this. After the heat treatment for separating the crystalline semiconductor layer 516, an etching treatment is performed to separate the single-crystal semiconductor layer. Alternatively, the areas with many defects on the 516 surface may be removed before the laser irradiation treatment is performed. It is also possible to improve the flatness of the surface of the single-crystal semiconductor layer 516 before performing the laser irradiation treatment. The etching process described above can be either wet etching or dry etching. This may also be used. In addition, in this embodiment, the laser light is irradiated as described above. Furthermore, a thin-film thinning process may be performed to reduce the thickness of the single-crystal semiconductor layer 516. For thinning layer 516, either dry etching or wet etching, or both, can be used. You can use it.

[0143] Through the above process, an SOI substrate having a single-crystal semiconductor layer 518 with good properties can be obtained. It is possible (see Figure 6(G)).

[0144] <Methods for fabricating semiconductor devices> Next, refer to Figures 7 to 10 for a method of fabricating a semiconductor device using the above-mentioned SOI substrate. I will explain it.

[0145] <Method for fabricating the lower transistor> First, the method for fabricating transistor 160 at the bottom will be explained with reference to Figures 7 and 8. Figures 7 and 8 show a portion of the SOI substrate prepared by the method shown in Figure 6. This is a cross-sectional process diagram corresponding to the lower transistor shown in Figure 5(A).

[0146] First, the single-crystal semiconductor layer 518 is processed into an island shape to form the semiconductor layer 120 (Figure 7(A)). (See reference). Furthermore, before and after this process, in order to control the threshold voltage of the transistor... Impurity elements that impart n-type conductivity and impurity elements that impart p-type conductivity to the semiconductor layer It may be added to the semiconductor. When the semiconductor is silicon, it can be used as an impurity element to impart n-type conductivity. For example, phosphorus or arsenic can be used. Additionally, impurities that impart p-type conductivity can be used. Examples of elemental materials that can be used include boron, aluminum, and gallium.

[0147] Next, an insulating layer 122 is formed to cover the semiconductor layer 120 (see Figure 7(B)). Layer 122 will later become the gate insulating layer. The insulating layer 122 is, for example, the semiconductor layer 12 It can be formed by heat treatment of the surface (such as thermal oxidation or thermal nitriding). Alternatively, high-density plasma treatment may be applied. High-density plasma treatment is, for example, He Among noble gases such as Ar, Kr, and Xe, oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen, This can be done using any of the mixed gases. Of course, CVD and sputtering methods are also available. An insulating layer may be formed using the like. The insulating layer 122 may be silicon oxide, silicon oxidnitride Conc. silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide Um, hafnium silicate (HfSixOy(x>0, y>0)), nitrogen was added. Hafnium silicate (HfSixOyNz(x>0, y>0, z>0)), nitrogen added Hafnium aluminate (HfAlxOyNz(x>0, y>0, z>0)) etc. It is desirable to have a single-layer or multi-layer structure including this. Also, the thickness of the insulating layer 122 is, for example If so, the wavelength can be 1 nm to 100 nm, preferably 10 nm to 50 nm. In this embodiment, a single-layer insulating layer containing silicon oxide is produced using the plasma CVD method. We will form it.

[0148] Next, a mask 124 is formed on the insulating layer 122, and an impurity element that imparts conductivity is added to the semiconductor. It is added to layer 120 to form an impurity region 126 (see Figure 7(C)). After adding the impurity elements, mask 124 is removed.

[0149] Next, a mask is formed on the insulating layer 122, and the region where the insulating layer 122 overlaps with the impurity region 126 By removing a portion of the region, the gate insulating layer 122a is formed (see Figure 7(D)). As a method for removing the insulating layer 122, etching such as wet etching or dry etching is used. Ching treatment can be used.

[0150] Next, the gate electrode (including wiring formed in the same layer) is placed on the gate insulating layer 122a. A conductive layer is formed to create the gate electrode 128a and the conductive This forms layer 128b (see Figure 7(E)).

[0151] The conductive layers used in the gate electrode 128a and conductive layer 128b are made of aluminum, copper, titanium, etc. It can be formed using metallic materials such as tantalum and tungsten. A conductive layer containing semiconductor materials such as ricon may be formed. The formation method is not particularly limited, and vapor Various film deposition methods such as CVD, sputtering, and spin coating can be used. Yes, it is possible. Furthermore, the conductive layer can be processed by etching using a resist mask. can.

[0152] Next, the gate electrode 128a and the conductive layer 128b are used as a mask to impart a single conductivity type. By adding pure elements to the semiconductor layer, channel formation regions 134, impurity regions 132, and impurities are formed. A pure material region 130 is formed (see Figure 8(A)). Here, a p-type transistor is formed. Therefore, impurity elements such as boron (B) and aluminum (Al) are added. The concentration of the impurity elements can be set as appropriate. Furthermore, after adding the impurity elements... Then, heat treatment is performed for activation. Here, the concentration in the impurity region is the impurity region 126, impurity The purity level increases in the order of 132 in the pure substance region and 130 in the impurity region.

[0153] Next, the gate insulating layer 122a, gate electrode 128a, and conductive layer 128b are covered with insulating Layer 136, insulating layer 138, and insulating layer 140 are formed (see Figure 8(B)).

[0154] Insulating layer 136, insulating layer 138, insulating layer 140 are silicon oxide, silicon oxide nitride, and nitride Using materials containing inorganic insulating materials such as silicon oxide, silicon nitride, and aluminum oxide, This can be achieved. In particular, the insulating layer 136, insulating layer 138, and insulating layer 140 have a low dielectric constant. By using (low-k) materials, capacitance caused by overlapping electrodes and wiring can be sufficiently reduced. This is preferable because it makes it possible to reduce the amount. Note that insulating layer 136, insulating layer 138, insulating layer 14 A porous insulating layer made of these materials may be applied to 0. In a porous insulating layer, Compared to a high-density insulating layer, the dielectric constant decreases, further reducing the capacitance caused by electrodes and wiring. It is possible to reduce it. Also, insulating layers 136, 138, and 140 are made of poly It is also possible to form it using organic insulating materials such as imide and acrylic. For insulating layer 136, silicon oxide nitride is used, insulating layer 138 is used, insulating The case where silicon oxide is used as layer 140 will be explained. Note that here, insulating layer 1 36. The invention has a laminated structure of insulating layer 138 and insulating layer 140, but one aspect of the disclosed invention This is not limited to this. It may be one or two layers, or a laminated structure of four or more layers. stomach.

[0155] Next, the insulating layer 138 and insulating layer 140 are subjected to CMP (chemical mechanical polishing) treatment or etching treatment. By performing this process, the insulating layer 138 and the insulating layer 140 are flattened (see Figure 8(C)). Here, CMP treatment is performed until the insulating layer 138 is partially exposed. When silicon oxide is used and silicon oxide is used for the insulating layer 140, the insulating layer 138 is It functions as a ching stopper.

[0156] Next, by performing CMP treatment and etching treatment on the insulating layer 138 and insulating layer 140 This exposes the upper surfaces of the gate electrode 128a and the conductive layer 128b (see Figure 8(D)). Here, etching is performed until the gate electrode 128a and the conductive layer 128b are partially exposed. The process is carried out. Dry etching is preferable for this etching process, but Etching may be used. Part of the gate electrode 128a and conductive layer 128b are exposed. In the process of making this happen, in order to improve the characteristics of the transistor 162 that is formed later, The surfaces of the edge layer 136, insulating layer 138, and insulating layer 140 should preferably be as flat as possible. It's nice.

[0157] Through the above process, the lower transistor 160 can be formed (see Figure 8(D)). ).

[0158] Furthermore, before and after each of the above processes, additional steps are taken to form electrodes, wiring, semiconductor layers, insulating layers, etc. It may include a degree of [something]. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. By employing a multilayer wiring structure, it is also possible to realize highly integrated semiconductor devices.

[0159] <Method for fabricating the upper transistor> Next, the method for fabricating the upper transistor 162 will be explained with reference to Figures 9 and 10. do.

[0160] First, gate electrode 128a, conductive layer 128b, insulating layer 136, insulating layer 138, insulating layer 14 An oxide semiconductor layer is formed on top of 0, and the oxide semiconductor layer is processed to form an oxide semiconductor layer Form 144 (see Figure 9(A)). Note that before forming the oxide semiconductor layer, an insulating layer 1 36. An insulating layer that functions as a base layer may be provided on top of the insulating layer 138 and the insulating layer 140. The insulating layer is produced by PVD methods such as sputtering and plasma CVD. It can be formed using methods such as the D method.

[0161] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable to include In and Zn. Furthermore, using the oxide semiconductor As a stabilizer to reduce variations in the electrical characteristics of transistors, It is preferable to have gallium (Ga). Also, tin (Sn) is used as a stabilizer. It is preferable to have ) as a stabilizer. It is preferable that the stabilizer be made of aluminum (Al). stomach.

[0162] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0163] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. These are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn acids oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides Materials, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Using Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible to be there.

[0164] For example, an In-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. This means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not specified. It is also acceptable for metal elements other than a and Zn to be present.

[0165] Furthermore, as a material used for the oxide semiconductor layer, the quaternary metal oxide In-Sn-Ga -Zn-O-based materials, and ternary metal oxides such as In-Ga-Zn-O-based materials, In- Sn-Zn-O type materials, In-Al-Zn-O type materials, Sn-Ga-Zn-O type materials Materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials, and binary metal oxides These are materials such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-G aO-based materials, as well as monocrystalline metal oxides such as In-O-based materials, Sn-O-based materials, and Zn -O-based materials can be used. Furthermore, SiO2 may be added to the above materials. Here, for example, In-Ga-Zn-O materials are made of indium (In) and gallium (Ga) means an oxide film containing zinc (Zn), and the composition ratio is not particularly specified. Furthermore, it may contain elements other than In, Ga, and Zn.

[0166] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn acid with an atomic ratio of a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use In-Sn-Zn oxides with a specific atomic ratio or oxides with a similar composition.

[0167] However, this is not limited to these, and depends on the required semiconductor characteristics (mobility, threshold, variability, etc.) A suitable composition should be used accordingly. Furthermore, in order to obtain the required semiconductor properties, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to make the following appropriate.

[0168] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0169] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of =1) is such that a, b, and c are (a-A) 2 +(b-B) 2 +(c―C) 2 ≤r 2 This means that the following conditions are met, and r can be set to, for example, 0.05. The same applies to other oxides. .

[0170] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or polycrystalline. But that's fine too. Also, even if the structure contains crystalline parts within the amorphous material, it can be non-amorphous. But that's fine.

[0171] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0172] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a nm or smaller.

[0173] Note that Ra is the centerline average roughness defined in JIS B0601, applied to the surface. This is a three-dimensional extension that allows for "averaging the absolute values ​​of the deviations from the reference plane to the specified plane." It can be expressed as "the value" and is defined by the following formula.

[0174]

number

[0175] In the above, S0 is the measurement surface (coordinates (x1,y1)(x1,y2)(x2,y1 Z0 refers to the area of ​​the rectangle enclosed by the four points represented by (x2, y2), and Z0 is This refers to the average height of the measurement surface. Ra stands for Atomic Force Microscope (AFM). It can be evaluated using a microscope.

[0176] Furthermore, the oxide semiconductor layer has the chemical formula InMO3(ZnO) m Materials represented as (m>0) The thin film used can be a thin film. Here, M is selected from Ga, Al, Mn, and Co. It indicates one or more metallic elements. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co, etc., can be used.

[0177] Furthermore, the thickness of the oxide semiconductor layer should preferably be between 3 nm and 30 nm. If the conductor layer is made too thick (for example, if the film thickness is 50 nm or more), the transistor will normally... This is because there is a risk that it will turn into a n.

[0178] The oxide semiconductor layer is manufactured using a method that minimizes the inclusion of impurities such as hydrogen, water, hydroxyl groups, or hydrides. It is preferable to manufacture it in this way. For example, it can be manufactured using methods such as sputtering.

[0179] Furthermore, when using In-Zn-based oxide materials as oxide semiconductors, the combination of targets used The ratio is an atomic ratio, where In:Zn = 50:1 to 1:2 (which translates to In2O3 in mole ratio). :ZnO=25:1~1:4), preferably In:Zn=20:1~1:1 (in terms of mole ratio) When converted, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 1 5:1 to 1.5:1 (converted to a mole ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn oxide semiconductor has an atomic ratio of In When Zn:O = X:Y:Z, let Z > 1.5X + Y.

[0180] Furthermore, In-Sn-Zn oxides can be called ITZOs, and the combination of targets used The composition ratio is In:Sn:Zn in terms of atomic ratio, such as 1:2:2, 2:1:3, 1:1:1, or For example, use 20:45:35.

[0181] In this embodiment, the oxide semiconductor layer uses an In-Ga-Zn-based oxide target. It is formed by the sputtering method.

[0182] For example, an In-Ga-Zn oxide target can be composed of In2O3: An oxide target can be used with a Ga2O3:ZnO = 1:1:1 [molar ratio]. Furthermore, the target material and composition are not limited to those described above. For example, In2O Using an oxide target with a composition ratio of 3:Ga2O3:ZnO = 1:1:2 [molar ratio] It is also possible to do so.

[0183] The packing density of the oxide target is 90% to 100%, preferably 95% to 99%. The percentage should be less than %. By using a metal oxide target with a high packing density, the oxide film can be formed. This is because it allows for the formation of a dense semiconductor layer.

[0184] The atmosphere for film deposition is either a noble gas atmosphere (typically argon), an oxygen atmosphere, or a noble gas atmosphere. This can be done under a mixed atmosphere of hydrogen and oxygen. Also, hydrogen, water, and hydroxyl groups in the oxide semiconductor layer To prevent contamination with hydrides and other impurities, hydrogen, water, hydroxyl groups, hydrides, and other impurities are sufficiently removed. It is desirable to use an atmosphere with the removed high-purity gas.

[0185] For example, an oxide semiconductor layer can be formed as follows:

[0186] First, the substrate is held in a deposition chamber under reduced pressure, and when the substrate temperature exceeds 200°C, 5 Below 00°C, preferably above 300°C and below 500°C, more preferably above 350°C. Heat to a temperature of 50°C or below.

[0187] Next, while removing residual moisture in the deposition chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. The high-purity gas removed in minutes is introduced, and an oxide semiconductor layer is placed on the substrate using the above target. The film is deposited. To remove residual moisture from the deposition chamber, a cryopump is used as an exhaust means. Adsorption-type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. Desirable. Also, the exhaust method may be a turbopump with a cold trap added. Good. The deposition chamber, which is evacuated using a cryopump, contains, for example, hydrogen, water, hydroxyl groups, or hydrogen Because impurities such as phosphates (more preferably compounds containing carbon atoms) have been removed. , hydrogen, water, hydroxyl groups or hydrides contained in the oxide semiconductor layer deposited in the deposition chamber The concentration of impurities can be reduced.

[0188] When the substrate temperature during film deposition is low (for example, below 100°C), the oxide semiconductor contains hydrogen atoms. Because there is a risk of contamination with harmful substances, it is preferable to heat the substrate at the above temperature. By heating the substrate at the above temperature to form an oxide semiconductor film, the substrate temperature becomes high. Therefore, hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. It is difficult to deposit. Therefore, when the substrate is heated to the above temperature, the oxide semiconductor layer is deposited. By doing so, impurities such as hydrogen, water, hydroxyl groups, or hydrides contained in the oxide semiconductor layer can be eliminated. The concentration of the substance can be significantly reduced. Furthermore, damage caused by sputtering can be reduced. It is possible.

[0189] As an example of film deposition conditions, the distance between the substrate and the target is 60 mm, and the pressure is 0.4 Pa. DC power supply 0.5kW, substrate temperature 400℃, film deposition atmosphere oxygen (oxygen flow rate ratio) The atmosphere should be 100%. Note that if a pulsed DC power supply is used, powdery material will be generated during film formation. This method is preferable because it reduces particles (also called dust) and results in a more uniform film thickness distribution.

[0190] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced. In reverse sputtering, which generates plasma, the powder adhering to the surface of the oxide semiconductor layer is removed. It is preferable to remove granular material (also called particles or debris). Reverse sputtering is a process that removes the base This method involves applying a voltage to a plate, forming plasma near the substrate, and modifying the surface of the substrate. Note that other gases such as nitrogen, helium, or oxygen may be used instead of argon.

[0191] The processing of the oxide semiconductor layer involves forming a mask of the desired shape on the oxide semiconductor layer, and then using the acid. This can be done by etching the semiconductor layer. The mask described above is photo It can be formed using methods such as lithography, or by inkjet printing. The mask may be formed using the method described above. Note that the etching of the oxide semiconductor layer is done dry Either etching or wet etching is acceptable. Of course, you can also use a combination of these methods. good.

[0192] Subsequently, the oxide semiconductor layer 144 may be subjected to a heat treatment (first heat treatment). By performing this process, the hydrogen atom-containing material in the oxide semiconductor layer 144 can be further processed. It can be removed. The heat treatment temperature is 250°C to 700°C under an inert gas atmosphere. Preferably, the temperature should be between 450°C and 600°C, or below the strain point of the substrate. Inert gas The atmosphere is primarily composed of nitrogen or noble gases (helium, neon, argon, etc.). It is desirable to apply an atmosphere that does not contain water, hydrogen, etc. For example, heat The purity of nitrogen and noble gases such as helium, neon, and argon introduced into the processing equipment is set to 6N (9 9.9999% or more, preferably 7N (99.99999% or more) (i.e., impurities) The concentration should be 1 ppm or less, preferably 0.1 ppm or less.

[0193] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be carried out under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere. Prevent leakage and ensure that no water or hydrogen is introduced.

[0194] By the way, since the heat treatment described above has the effect of removing hydrogen and water, this heat treatment is used to remove This can also be called a hydration treatment or a dehydrogenation treatment. This heat treatment is used, for example, for oxide semiconductors. This can also be done at other times, such as before processing the body layers into island shapes or after forming the gate insulation layer. It is possible. Furthermore, such dehydration and dehydrogenation treatments can be performed not just once, but multiple times. good.

[0195] Next, on top of the oxide semiconductor layer 144, etc., source electrodes and drain electrodes (same layer) A conductive layer is formed to form wiring (including that which is formed by), and the conductive layer is processed to form Form the drain electrode 142a and the drain electrode 142b (see Figure 9(B)).

[0196] The conductive layer can be formed using PVD or CVD methods. For example, aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. Selected elements or alloys containing the aforementioned elements can be used. One of the following: magnesium, zirconium, beryllium, neodymium, scandium, or Materials combining multiple of these may also be used.

[0197] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, titanium Single-layer structures of silicon films and titanium nitride films, single-layer structures of silicon-containing aluminum films, aluminum A two-layer structure in which a titanium film is laminated on a titanium film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated. Oh, when the conductive layer is a single-layer structure of titanium film or titanium nitride film, it has a tapered shape. The advantage is that the source electrode 142a and drain electrode 142b are easy to process. There is.

[0198] Furthermore, the conductive layer may be formed using a conductive metal oxide. These include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and oxide Indium tin oxide compounds (In2O3-SnO2, sometimes abbreviated as ITO), acid Indium zinc oxide compounds (In2O3-ZnO), or these metal oxide materials A material containing silicon or silicon oxide can be used.

[0199] Etching of the conductive layer is performed on the edges of the source electrode 142a and drain electrode 142b that are formed. It is preferable that the part be tapered. Here, the taper angle is, for example, It is preferable that the temperature is between 30° and 60°. Source electrode 142a, drain electrode 142 The gate that will be formed later is created by etching the end of b into a tapered shape. This improves the coverage of the insulating layer 146 and prevents breakage in steps.

[0200] The channel length (L) of the upper transistor is measured from source electrode 142a to drain electrode 1 This is determined by the spacing of the lower ends of 42b. Note that if the channel length (L) is less than 25 nm When performing exposure for mask formation used in lampistor formation, use a range of several nanometers to several tens of nanometers. It is preferable to use extremely short-wavelength ultraviolet light. Exposure with ultra-ultraviolet light results in high resolution and a large depth of field. Therefore, the later-formed to The channel length (L) of the transistor should be between 10 nm and 1000 nm (1 μm). This is also possible, and it is possible to increase the operating speed of the circuit. Furthermore, miniaturization allows for semiconductor It is also possible to reduce the power consumption of the device.

[0201] Furthermore, as another example from Figure 9(B), the oxide semiconductor layer 144 and the source electrode and drain An oxide conductive layer can be provided between the electrode and the source and drain regions. The material for the oxide conductive layer is preferably one that contains zinc oxide as a component, and zinc oxide It is preferable that it does not contain zinc. A suitable oxide conductive layer is zinc oxide. By applying zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, etc. It is possible.

[0202] For example, an oxide conductive film is formed on an oxide semiconductor layer 144, and a conductive layer is formed thereon, The conductive film and conductive layer are processed by the same photolithography process, and the source region The oxide conductive layer that forms the drain region, the source electrode 142a, and the drain electrode 142b are formed It is possible.

[0203] Furthermore, a laminate of an oxide semiconductor film and an oxide conductive film is formed, and the oxide semiconductor film and the oxide conductive film The stacked layers are processed into island-shaped oxide semiconductor layers 14 using the same photolithography process. A conductive oxide film may be formed with 4. A source electrode 142a and a drain electrode 142b are formed. After that, using the source electrode 142a and drain electrode 142b as masks, further island oxidation is performed. The material conductive film is etched to form oxide conductive layers that will serve as the source and drain regions. It is also possible.

[0204] Furthermore, during the etching process to shape the oxide conductive layer, the oxide semiconductor layer is excessive. To prevent etching, the etching conditions (type of etching agent, concentration, etching) Adjust the time, etc., as appropriate.

[0205] By providing an oxide conductive layer between the oxide semiconductor layer and the source and drain electrodes, This allows for lower resistance in the drain and drain regions, enabling high-speed operation of the transistor. It can be made that way. Also, the oxide semiconductor layer 144, the oxide conductive layer, and the metal material By using a rain electrode configuration, the transistor's breakdown voltage can be further improved. ru.

[0206] Using oxide conductive layers as source and drain regions allows for peripheral circuits (drive circuits) This is effective in improving the frequency characteristics. (Metal electrodes: molybdenum, tungsten, etc.) Compared to contact between the metal electrode (molybdenum, tungsten, etc.) and the oxide semiconductor layer, Contact with the electrode layer can reduce contact resistance. By interposing an oxide conductive layer between the electrode and the drain electrode, contact resistance can be reduced, and the surrounding area The frequency characteristics of the circuit (drive circuit) can be improved.

[0207] Next, the source electrode 142a and drain electrode 142b are covered, and the oxide semiconductor layer 144 A gate insulating layer 146 is formed so as to be in contact with a portion of it (see Figure 9(C)).

[0208] The gate insulating layer 146 can be formed using methods such as CVD or sputtering. Furthermore, the gate insulating layer 146 is made of silicon oxide, silicon nitride, silicon oxynitride, and gallium oxide. Aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium Musilicate (HfSixOy(x>0, y>0)), hafnium silicate with added nitrogen Kate (HfSixOyNz(x>0, y>0, z>0)), Nitrogen-added Hafniu This includes aluminates such as HfAlxOyNz(x>0, y>0, z>0). It is preferable to form it. The gate insulating layer 146 may be a single layer structure or made of the above material. These can be combined to form a laminated structure. Furthermore, the thickness is not particularly limited, but semiconductor equipment When miniaturizing components, it is desirable to make them thin in order to ensure proper transistor operation. For example, when using silicon oxide, the wavelength should be between 1 nm and 100 nm, preferably 10 nm. It can be between m and 50 nm.

[0209] As mentioned above, thinning the gate insulation layer can lead to gate leakage caused by the tunnel effect, etc. This poses a problem. To resolve the gate leakage problem, the gate insulating layer 146 contains hafny oxide. Mu, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0) , y>0)), nitrogen-added hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-added hafnium aluminate (HfAlxOyNz( It is preferable to use high-dielectric constant (high-k) materials such as x>0, y>0, z>0). By using igh-k material for the gate insulating layer 146, electrical characteristics are ensured while the gate It becomes possible to increase the film thickness to suppress leakage. A film containing silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide, and a It may also be a laminated structure with a film containing luminium or any other material.

[0210] Furthermore, an insulating layer in contact with the oxide semiconductor layer 144 (in this embodiment, the gate insulating layer 1 46) may be an insulating material containing a group 13 element and oxygen. Oxide semiconductor materials include Many of these contain Group 13 elements, and insulating materials containing Group 13 elements are incompatible with oxide semiconductors. Often, this is used as an insulating layer in contact with an oxide semiconductor layer, and the interface with the oxide semiconductor layer It can be kept in good condition.

[0211] An insulating material containing a Group 13 element is an insulating material that contains one or more Group 13 elements. This means that insulating materials containing Group 13 elements include, for example, gallium oxide and aluminum oxide. Examples include aluminum, aluminum gallium oxide, and aluminum gallium oxide. Here, oxidation Aluminum gallium is defined as having a higher aluminum content (atomic %) than gallium content (atomic %). This indicates the highest gallium content (atomic %), and gallium aluminum oxide refers to the gallium content (atomic %). This indicates a content (atomic %) of aluminum that is equal to or greater than this value.

[0212] For example, when forming a gate insulating layer in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide in the gate insulating layer, the boundary between the oxide semiconductor layer and the gate insulating layer is achieved. It is possible to maintain good surface characteristics. In addition, the oxide semiconductor layer and the insulating layer containing gallium oxide By providing them in contact, hydrogen pile-up occurs at the interface between the oxide semiconductor layer and the insulating layer. This can reduce the amount of noise. Furthermore, the insulating layer uses elements from the same group as the constituent elements of the oxide semiconductor. In such cases, it is possible to obtain a similar effect. For example, a material containing aluminum oxide It is also effective to form an insulating layer using [aluminum oxide]. Note that aluminum oxide allows water to pass through. Because it has the characteristic of being difficult to use, using this material means that water will not easily reach the oxide semiconductor layer. It is also preferable in terms of preventing intrusion.

[0213] Furthermore, the insulating layer in contact with the oxide semiconductor layer 144 is subjected to heat treatment in an oxygen atmosphere, or oxygen atmosphere It is preferable to use methods such as prisms to ensure that the insulating material has a higher oxygen content than the stoichiometric composition ratio. Oxygen doping refers to the addition of oxygen to the bulk material. The term "bulk material" in this context refers to oxygen. This is used to clarify that the substance is added not only to the surface of the thin film but also to the interior of the thin film. Plain doping includes oxygen plasma doping, which involves adding plasma-formed oxygen to the bulk material. Oxygen doping may also be performed using ion implantation or ion doping methods.

[0214] For example, when gallium oxide is used as an insulating layer in contact with the oxide semiconductor layer 144, the oxygen atmosphere By performing heat treatment under ambient air or oxygen doping, the composition of gallium oxide can be changed to Ga2O x (X = 3 + α, 0 < α < 1) can be set. Also, the oxide semiconductor layer 144 is in contact with When aluminum oxide is used as the insulating layer, heat treatment in an oxygen atmosphere or oxygen doping By doing this, the composition of aluminum oxide is changed to Al2O X (X=3+α, 0<α<1) Alternatively, gallium oxide can be used as an insulating layer in contact with the oxide semiconductor layer 144. When using luminium (aluminum gallium oxide), heat treatment under an oxygen atmosphere or acid By performing doping, gallium aluminum oxide (gallium aluminum oxide) Composition Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0215] By performing oxygen doping treatment, etc., an insulating material has a region where the oxygen content is higher than the stoichiometric composition ratio. A layer can be formed. When an insulating layer having such a region is in contact with an oxide semiconductor layer As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and in the oxide semiconductor layer, This can reduce oxygen-deficient defects at the interface between the oxide semiconductor layer and the insulating layer.

[0216] Furthermore, in insulating layers having regions with a higher oxygen content than the stoichiometric composition ratio, the gate insulating layer 146 is replaced. Furthermore, it may be applied to an insulating layer formed as a base film for the oxide semiconductor layer 144, and gate insulating It may be applied to both the margin layer 146 and the undercoat.

[0217] After the formation of the gate insulating layer 146, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The heat treatment temperature should be between 200°C and 450°C, preferably 25°C. The temperature range is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour under a nitrogen atmosphere. Yes, that's fine. By performing a second heat treatment, variations in the electrical characteristics of the transistors are reduced. It is possible to dehydrate or dehydrogenate the gate insulating layer 146 if it contains oxygen. Oxygen is supplied to the oxide semiconductor layer 144 after processing to compensate for oxygen deficiencies in the oxide semiconductor layer 144. By filling, it is also possible to form an oxide semiconductor layer that is type i (intrinsic semiconductor) or very close to type i. can.

[0218] In this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Heat treatment may be performed. Alternatively, a second heat treatment may be performed immediately following the first heat treatment, or the second heat treatment may be performed immediately following the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. You can do that.

[0219] Next, a conductive layer is formed to form the gate electrode (including wiring formed in the same layer). The conductive layer is then processed to form the gate electrode 148a and the conductive layer 148b (Figure 9(D)).

[0220] The gate electrode 148a and the conductive layer 148b are made of molybdenum, titanium, tantalum, and tungsten. Metal materials such as tungsten, aluminum, copper, neodymium, scandium, or materials with these as the main components It can be formed using an alloy material. Note that the gate electrode 148a and the conductive layer 1 48b can be a single-layer structure or a laminated structure.

[0221] Next, an insulating layer 1 is placed on the gate insulating layer 146, the gate electrode 148a, and the conductive layer 148b. Form layer 50 (see Figure 10(A)). The insulating layer 150 is formed using methods such as PVD or CVD. It can be formed by silicon oxide, silicon oxynitride, silicon nitride, and silicon oxide. Formed using materials containing inorganic insulating materials such as humium, gallium oxide, and aluminum oxide. This is possible. Furthermore, the insulating layer 150 may contain materials with a low dielectric constant or structures with a low dielectric constant (multiple It is desirable to use a porous structure, etc. By lowering the dielectric constant of the insulating layer 150 This is because it reduces capacitance between wiring and electrodes, thereby enabling faster operation. In this embodiment, the insulating layer 150 has a single-layer structure, but one of the disclosed inventions is... The embodiment is not limited thereto, and a laminated structure of two or more layers is also possible.

[0222] Next, openings are formed in the gate insulating layer 146 and the insulating layer 150 that reach the source electrode 142a. This is done. Subsequently, a wiring 154 that is in contact with the source electrode 142a is formed on the insulating layer 150. See Figure 10(B). Note that the opening is formed by selective etching using a mask or the like. It is carried out by [the specified method].

[0223] Wiring 154 has a conductive layer formed using PVD or CVD, and then the conductive layer is patterned. It is formed by machining. Furthermore, aluminum and chrome are used as materials for the conductive layer. Elements selected from tungsten, copper, tantalum, titanium, molybdenum, and the elements mentioned above Alloys containing manganese, magnesium, zirconium, etc. can be used. Materials consisting of beryllium, neodymium, scandium, or a combination of these. You may also use [this].

[0224] More specifically, for example, a thin titanium film is applied to the region including the opening of the insulating layer 150 by PVD. After forming a (approximately 5 nm) layer and creating a titanium film using the PVD method, it is then embedded into the opening. A method for forming an aluminum film can be applied. Here, the film is formed by the PVD method. The titanium film that is formed reduces the oxide film (such as the native oxide film) on the surface to be formed, and the lower electrode, etc. (here It has the function of reducing contact resistance with the source electrode 142a). Also, aluminum It can prevent hillock formation in the film. Furthermore, barrier films made of titanium or titanium nitride can be used. After formation, a copper film may be formed by a plating method.

[0225] The openings formed in the insulating layer 150 are preferably formed in the region that overlaps with the conductive layer 128b. i. By forming an opening in such a region, the element area caused by the contact region increases It can be suppressed.

[0226] Here, without using the conductive layer 128b, the connection between the impurity region 126 and the source electrode 142a Next, we will explain the case where the connection between the source electrode 142a and the wiring 154 is superimposed. In this case, insulating layer 136, insulating layer 138 and insulating layer 1 formed on the impurity region 126 An opening (referred to as the lower contact) is formed at 40, and the source electrode 142 is placed at the lower contact. After forming a, the gate insulating layer 146 and insulating layer 150 are formed, and the lower contact and An opening (referred to as the upper contact) is formed in the overlapping region, and wiring 154 is formed. Yes. When forming the upper contact in the region that overlaps with the lower contact, etching occurs. This may cause the source electrode 142a formed on the lower contact to break. To avoid this, the lower and upper contacts are formed so that they do not overlap. This leads to the problem of increased element area.

[0227] As shown in this embodiment, by using the conductive layer 128b, the source electrode 142a This allows for the formation of the upper contact without causing a break in the wire. This also allows for the formation of the lower contact Because the contact and the upper contact can be superimposed, the contact area is affected This can suppress the increase in element area. In other words, it is possible to increase the integration density of semiconductor devices. can.

[0228] Next, an insulating layer 156 is formed to cover the wiring 154 (see Figure 10(C)).

[0229] As described above, a transistor 162 using a highly purified oxide semiconductor layer 144, and Capacitive element 164 is completed (see Figure 10(C)).

[0230] In the transistor 162 shown in this embodiment, the oxide semiconductor layer 144 is made highly pure. Because it is contained, its hydrogen concentration is 5 × 10 19 atoms / cm 3 The following is preferable: 5x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 below Furthermore, the carrier density of the oxide semiconductor layer 144 is as follows in a typical silicon wafer. Carrier density (1 × 10⁻⁶) 14 / cm 3 A sufficiently small value (for example, 1) compared to the degree ×10 12 / cm 3 Less than, more preferably 1.45 × 10 10 / cm 3 Take the value less than (). And the off-current also becomes sufficiently small. For example, at room temperature (25°C) for transistor 162 The off-current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA ( Zeptoampere is 1 x 10 -21 A) Preferably, the value should be 10zA or less.

[0231] By using the highly purified and intrinsically purified oxide semiconductor layer 144 in this way, transient It becomes easier to sufficiently reduce the off-current of the transistor. And such a transistor By using this technology, a semiconductor device capable of retaining memory contents for an extremely long period of time can be obtained. ru.

[0232] Furthermore, in the semiconductor device shown in this embodiment, it is also possible to standardize the wiring. This makes it possible to realize semiconductor devices with a sufficiently high degree of integration.

[0233] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0234] (Embodiment 3) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, This will be explained using Figure 11. In this embodiment, a computer and a mobile phone (mobile Telephones (also called mobile phones), personal information terminals (including portable game consoles, audio playback devices, etc.) Cameras such as digital cameras and digital video cameras, e-paper, televisions Electronic devices such as televisions (also called televisions or television receivers) use the aforementioned semiconductors. This section explains when the device will be applied.

[0235] Figure 11(A) shows a notebook-type personal computer, consisting of casing 701, casing 702, It consists of a display unit 703, a keyboard 704, etc., and a casing 701 and a casing 702. At least one of them is provided with the semiconductor device shown in the previous embodiment. It offers high-speed data writing and reading, long-term memory retention, and sufficient power consumption. This will result in a notebook-type personal computer with significantly reduced performance.

[0236] Figure 11(B) shows a personal digital assistant (PDA), and the main body 711 has a display unit 713 and an external A separate interface 715 and operation buttons 714 are provided. It is equipped with a stylus 712 for operating the end. Inside the main body 711, as in the previous embodiment, The semiconductor device shown is provided. Therefore, information can be written to and read at high speed. A portable information terminal capable of long-term memory retention and with significantly reduced power consumption will be realized. .

[0237] Figure 11(C) shows an e-reader 720 with electronic paper installed, consisting of a casing 721 and a casing 72 It consists of two enclosures, 721 and 723, respectively, each containing a display unit 7 25 and a display unit 727 are provided. The housing 721 and housing 723 are connected by the shaft portion 737 It is connected and can open and close using the shaft portion 737 as an axis. Unit 21 includes a power supply 731, operation keys 733, a speaker 735, etc. (Cabinet 721) At least one of the housings 723 is provided with the semiconductor device shown in the previous embodiment. Therefore, it allows for high-speed writing and reading of information, long-term memory retention, and erasure. This will enable the creation of e-books with significantly reduced power consumption.

[0238] Figure 11(D) shows a mobile phone, which is composed of two casings, casing 740 and casing 741. Furthermore, the casings 740 and 741 slide and unfold as shown in Figure 11(D). It can be transformed from a separate state to an overlapping state, and can be miniaturized to suit portability. The enclosure 741 includes a display panel 742, a speaker 743, a microphone 744, and an operating panel. Key 745, pointing device 746, camera lens 747, external connection terminal 74 It is equipped with 8, etc. Also, the housing 740 has a solar cell 749 that charges the mobile phone. It also features an external memory slot 750, etc. Furthermore, the antenna is built into the housing 741. It is provided. At least one of the housings 740 and 741 is equipped with the semiconductor equipment shown in the previous embodiment. A storage space is provided. Therefore, information can be written and read at high speed, and long-term storage is possible. A mobile phone that can be held while consuming significantly reduced power will be realized.

[0239] Figure 11(E) shows a digital camera, consisting of the main body 761, display unit 767, eyepiece unit 763, and control panel. It consists of a power switch 764, a display unit 765, a battery 766, etc. Inside 761, the semiconductor device shown in the previous embodiment is provided. Therefore, the information book It offers high-speed write and read operations, long-term data retention, and significantly reduced power consumption. A digital camera that achieves this will be realized.

[0240] Figure 11(F) shows a television device 770, consisting of a housing 771, a display unit 773, and a stand. It consists of 775 and other components. The television device 770 is operated by the casing 771. This can be done using the switch or the remote control unit 780. The housing 771 and the remote control unit The machine 780 is equipped with the semiconductor device shown in the previous embodiment. Therefore, information It offers high-speed writing and reading, long-term memory retention, and sufficiently low power consumption. A reduced-scale television system will be realized.

[0241] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with reduced power consumption can be realized.

[0242] (Embodiment 4) In this embodiment, an oxide semiconductor is used as the semiconductor material described in Embodiments 1 to 3 above. Let me explain in detail about transistors. Specifically, as oxide semiconductors, the c-axis arrangement A triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface. In the c-axis, metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. , in the ab plane, the orientation of the a axis or b axis is different (a crystal rotated around the c axis) (CA Also known as AC:C Axis Aligned Crystal. (Regarding oxides containing AC:C Axis Aligned Crystal) I will explain.

[0243] CAAC-containing oxides, in a broad sense, are non-single crystals that can be viewed from a direction perpendicular to their ab-plane. And, having an atomic arrangement of triangles, hexagons, equilateral triangles or regular hexagons, and perpendicular to the c-axis direction When viewed from a particular direction, the acid contains a phase in which metal atoms are arranged in layers, or in which metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0244] CAAC is not a single crystal, but it is not formed solely from amorphous material either. AC contains crystalline parts (crystalline portions), but the boundary between one crystalline portion and another is not clearly defined. Sometimes it's impossible to determine for sure.

[0245] If CAAC contains oxygen, some of the oxygen may be replaced with nitrogen. The c-axis of each individual crystal portion that makes up the structure is in a constant direction (for example, the substrate surface supporting CAAC, C They may be aligned in a direction perpendicular to the surface of the AAC, etc. Or, each of the components of the CAAC The normal to the ab plane of the crystal portion is in a certain direction (for example, the substrate surface supporting CAAC, CAAC It may be oriented perpendicular to the surface, etc.

[0246] CAAC can be a conductor, a semiconductor, or an insulator, depending on its composition. Depending on its composition, it may be transparent or opaque to visible light. To do.

[0247] Examples of such CAACs include those formed in a film-like manner, with perpendicularity to the film surface or the supporting substrate surface. When observed from a particular direction, a triangular or hexagonal atomic arrangement is observed, and when the cross-section of the film is observed... Upon examination, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) can be observed. Crystals can also be cited.

[0248] An example of the crystal structure contained in CAAC will be explained in detail using Figures 12 to 14. Unless otherwise specified, Figures 12 through 14 define the upward direction as the c-axis direction, and the direction perpendicular to the c-axis direction. Let the surface be called surface ab. Note that when simply referring to the upper half and the lower half, the boundary is surface ab. It refers to the upper half and the lower half.

[0249] Figure 12(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter referred to as 4 The structure shows a coordinated O) and a nearby oxygen atom. Here, for each metal atom, A structure showing only the children is called a small group. The structure in Figure 12(A) takes the form of an octahedron, but For simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 12(A) are respectively There are 4-coordinate oxygen atoms, 3 in each group. The small group shown in Figure 12(A) has a charge of 0.

[0250] Figure 12(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter referred to as 3 The structure shows a coordinated oxygen atom and two 4-coordinate oxygen atoms adjacent to Ga. The 3-coordinate oxygen atom is All of them are located on the ab plane. There is one in the upper half and one in the lower half of Figure 12(B), for a total of four. There is a coordinate oxygen atom. Also, since In can take on a 5-coordinate state, it can take on the structure shown in Figure 12(B). The small group shown in Figure 12(B) has a charge of 0.

[0251] Figure 12(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to the Zn. The structure is shown. The upper half of Figure 12(C) has one 4-coordinate oxygen atom, and the lower half has three 4-coordinate oxygen atoms. There is an O. Alternatively, there are three 4-coordinate Os in the upper half of Figure 12(C) and one in the lower half There may be oxygen atoms with 4 coordination. The small group shown in Figure 12(C) has a charge of 0.

[0252] Figure 12(D) shows a structure having one 6-coordinate Sn and six 4-coordinate O adjacent to the Sn. The structure is shown. The upper half of Figure 12(D) has 3 four-coordinate oxygen atoms, and the lower half has 3 four-coordinate oxygen atoms. There is an O. The small group shown in Figure 12(D) has a charge of +1.

[0253] Figure 12(E) shows a small group containing two Zn molecules. The upper half of Figure 12(E) shows one There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. The small group shown in Figure 12(E) The charge becomes -1.

[0254] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is This is called a large group (also known as a unit cell).

[0255] Here, we will explain the rules by which these subgroups combine. These rules are shown in Figure 12(A). The three oxygen atoms in the upper half of the 6-coordinate In each have three adjacent In atoms below them, and the lower half The three oxygen atoms each have three adjacent in atoms in the upward direction. One of the upper half of the 5-coordinate Ga O has one neighboring Ga in the downward direction, and the lower half of O has one neighboring Ga in the upward direction It has. One oxygen atom in the upper half of the 4-coordinate Zn has one adjacent Zn atom below it, and three in the lower half Each oxygen atom has three neighboring zinc atoms in the upward direction. In this way, the upward direction of the metal atom The number of 4-coordinate oxygen atoms is equal to the number of nearby metal atoms below that oxygen atom, and similarly, the number of metal atoms The number of oxygen atoms in a downward 4-coordinate state is equal to the number of adjacent metal atoms above that oxygen atom. Therefore, the sum of the number of nearby metal atoms below and the number of nearby metal atoms above is 4. Therefore, the number of 4-coordinate oxygen atoms above the metal atom and the number of oxygen atoms below the other metal atom are considered. When the sum of the number of 4-coordinate oxygen atoms and the number of other 4-coordinate oxygen atoms is 4, the two types of small groups containing metal atoms bond together. This is possible. For example, a 6-coordinate metal atom (In or Sn) can absorb the 4-coordinate oxygen in the lower half. When bonded via a mediated bond, there are three 4-coordinate oxygen atoms, and therefore a 5-coordinate metal atom (Ga or In) It will bond with either a 4-coordinate metal atom (Zn) or a 4-coordinate metal atom.

[0256] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine such that the total charge of the layered structure becomes 0. It forms a middle group.

[0257] Figure 13(A) shows a model diagram of the intermediate groups that constitute the layered structure of the In-Sn-Zn-O system. Figure 13(B) shows the large group, which is composed of three subgroups. C) shows the atomic arrangement when the layer structure of Figure 13(B) is observed from the c-axis direction.

[0258] In Figure 13(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate oxygen atoms (indicated by the circle). This is shown as 3. Similarly, in Figure 13(A), the upper half and lower half of In are Each of these has one 4-coordinate oxygen atoms, which are shown as 1 in the circle. Similarly, Figure 13 In (A), the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. Zn has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. This indicates that.

[0259] In Figure 13(A), the middle group constituting the layered structure of the In-Sn-Zn-O system is from the top In order, Sn has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with In in the half and lower half, and that In has three 4-coordinate O in the upper half. It bonds with n, and through one 4-coordinate oxygen atom in the lower half of the Zn, three 4-coordinate oxygen atoms are bonded to the upper half. And bonded to In in the lower half, that In has one 4-coordinate O in the upper half of Zn2 It combines with a small group consisting of , and through one 4-coordinate O in the lower half of this small group, 4 The coordination is structured so that three oxygen atoms are bonded to the Sn atoms in the upper half and three in the lower half. Multiple loops combine to form a larger group.

[0260] Here, for 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0.6, respectively. 67, -0.5 can be considered. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of (5-coordinate) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore Therefore, the small group containing Sn has a charge of +1. As a result, it forms a layered structure containing Sn. For this to work, a charge of -1 is needed to cancel out the charge of +1. Figure 1 shows a structure that takes on a charge of -1. As shown in 2(E), a small group containing two Zn elements is an example. If there is one small group and one small group containing two Zn atoms, the charges cancel each other out. Therefore, the total charge of the layered structure can be set to 0.

[0261] Specifically, the large groups shown in Figure 13(B) are repeated, resulting in In-Sn-Zn -O-based crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be represented by the following empirical formula:

[0262] In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, and ternary metal oxides. In-Ga-Zn oxides (also written as IGZO), which are oxides of the original metal, Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-C e-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm -Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb- Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides In-Zn oxides, Sn-Zn oxides, and Al oxides are examples of oxides of binary metals. -Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and I The same applies when using n-Ga-based oxides, etc.

[0263] For example, Figure 14(A) shows the intermediate group that constitutes the layered structure of the In-Ga-Zn-O system. A diagram is shown.

[0264] In Figure 14(A), the middle group constituting the layered structure of the In-Ga-Zn-O system is from the top In order, the ion molecule has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with Zn, and through the three 4-coordinate oxygen atoms in the lower half of that Zn, one 4-coordinate oxygen atom is bonded. Each bondes with Ga in the upper and lower halves, and via one 4-coordinate O in the lower half of that Ga Thus, the structure consists of three 4-coordinate oxygen atoms bonded to the in atoms in the upper and lower halves, respectively. Multiple of these smaller groups combine to form larger groups.

[0265] Figure 14(B) shows the large group, which is composed of three medium groups. Figure 14(C) is Figure 14(B) shows the atomic arrangement when the layered structure is observed from the c-axis direction.

[0266] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, small groups containing any of In, Zn, and Ga Therefore, the charge becomes 0. The charge of the sum is always 0.

[0267] Furthermore, the intermediate groups that constitute the layered structure of the In-Ga-Zn-O system are shown in Figure 14(A). Not limited to medium groups, but combining medium groups with different arrangements of In, Ga, and Zn. The group could also be included.

[0268] (Embodiment 5) In this embodiment, the oxide semiconductor described in Embodiments 1 to 4 above is used in the channel formation region. Let's discuss the mobility of the transistors used.

[0269] The field-effect mobility of insulated-gate transistors, which is actually measured, is not limited to oxide semiconductors. For various reasons, mobility may be lower than it would be otherwise. Factors that reduce mobility include This includes defects within the semiconductor and defects at the interface between the semiconductor and the insulating film, but the Levinson model... Using this method, we can theoretically derive the field-effect mobility assuming there are no defects inside the semiconductor. Let it.

[0270] Let μ0 be the intrinsic mobility of the semiconductor, and μ be the measured field-effect mobility. Assuming that a tential barrier (grain boundary, etc.) exists,

[0271]

number

[0272] It can be expressed as follows: Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is This is absolute temperature. Also, assuming that the potential barrier originates from a defect, Levins In the on model,

[0273]

number

[0274] This is expressed as follows: Here, e is the elementary charge, and N is the average defect per unit area within the channel formation region. Vault density, where ε is the dielectric constant of the semiconductor and n is the carrier content per unit area of ​​the channel formation region. A number, C ox V is the volume per unit area. g t is the gate voltage, and t is the thickness of the channel formation region. That is the case. Furthermore, for semiconductor layers with a thickness of 30 nm or less, the thickness of the channel formation region is the same as that of a semiconductor layer. It can be considered the same as the thickness of the layer. Drain current I in the linear region d teeth,

[0275]

number

[0276] Here, L is the channel length and W is the channel width, and in this case, L = W = 10 μm. It is. Also, V d This is the drain voltage. Substitute V g Dividing by and then taking the logarithm of both sides,

[0277]

number

[0278] Therefore, the right-hand side of equation 5 is V g This is a function of . As can be seen from this formula, the vertical axis is ln(I d / V g ), horizontal axis is 1 / V g The slope of the straight line obtained by plotting the measured values ​​is used to determine the missing value. The depression N can be determined. That is, the I of the transistor. d ―V g Defect density can be evaluated based on its characteristics. Yes, it is possible. For oxide semiconductors, the ratio of indium (In), tin (Sn), and zinc (Zn) is... For a ratio of In:Sn:Zn=1:1:1, the defect density N is 1 × 10⁻⁶. 12 / cm 2 degree That is the case.

[0279] Based on the defect density and other factors obtained in this way, we can use equations 2 and 3 to conclude that μ0 = 120 cm². 2 / Vs This is derived. The mobility measured in defective In-Sn-Zn oxide is 40 cm². 2 / V It is approximately s. However, oxide semiconductors without defects inside the semiconductor and at the interface between the semiconductor and the insulating film. The conductor's mobility μ0 is 120 cm. 2 It can be expected that the result will be / Vs.

[0280] However, even if there are no defects inside the semiconductor, dispersion occurs at the interface between the channel formation region and the gate insulating layer. The transport characteristics of a transistor are affected by disturbances. That is, from the gate insulating layer interface to x The mobility μ1 at a distance of 1 is

[0281]

number

[0282] It is expressed as follows: Here, D is the electric field in the gate direction, and B and l are constants. B and l are actually This can be determined from the measurement results, and from the above measurement results, B = 4.75 × 10 7 cm / s and l = 10 nm (depth of interface scattering). D increases (i.e., gate voltage). As (increases), the second term of equation 6 increases, so it can be seen that the mobility μ1 decreases.

[0283] A transistor using an ideal oxide semiconductor with no defects inside the semiconductor as the channel formation region. Figure 15 shows the results of calculating the mobility μ2. Note that the calculation was performed using a Synopsys device. Using the simulation software Sentaurus Device, we simulated the performance of oxide semiconductors. The end gap, electron affinity, relative permittivity, and thickness were 2.8 electron volts and 4.7 electrons, respectively. The values ​​were set to volt, 15, and 15 nm. These values ​​represent thin films formed by the sputtering method. This was obtained by measuring [the relevant parameters].

[0284] Furthermore, the work functions of the gate electrode, source electrode, and drain electrode were set to 5.5 electron volts, respectively. The voltage was set to 4.6 electron volts and 4.6 electron volts. The thickness of the gate insulation layer was 100N. The relative permittivity was set to m and 4.1. Both the channel length and channel width were 10 μm, and the drain was also 10 μm. Voltage V d The voltage is 0.1V.

[0285] As shown in Figure 15, with a gate voltage of slightly over 1V, the mobility is 100cm. 2 / Vs or higher peak However, as the gate voltage increases further, interfacial scattering increases, and mobility decreases. Furthermore, in order to reduce interfacial scattering, the semiconductor layer surface must be made atomically flat (At (Crypto Layer Flatness) is desirable.

[0286] When a miniature transistor is fabricated using an oxide semiconductor with such mobility, The results of the calculations are shown in Figures 16 to 18. Note that the cross-sectional structure of the transistor used in the calculations is shown. The structure is shown in Figure 19. The transistor shown in Figure 19 has an oxide semiconductor layer n + It exhibits the following conductivity type. It has semiconductor region 103a and semiconductor region 103c. The resistivity of body region 103c is 2 × 10⁻⁶. -3 Let it be Ωcm.

[0287] The transistor shown in Figure 19(A) consists of a base insulating film 101 and embedded in the base insulating film 101. Formed on top of an embedded insulator 102 made of aluminum oxide that is formed to be The transistor consists of semiconductor region 103a, semiconductor region 103c, and the channel sandwiched between them. The gate electrode has an intrinsic semiconductor region 103b that forms a region for forming a semiconductor, and a gate electrode 105. The width of 105 is set to 33 nm.

[0288] Between the gate electrode 105 and the semiconductor region 103b, there is a gate insulating layer 104, and also, On both sides of the electrode 105 are side wall insulators 106a and 106b, and the gate electrode An insulator 107 is placed above 105 to prevent short circuits between the gate electrode 105 and other wiring. It has the width of the side wall insulator 5 nm. Also, semiconductor region 103a and semiconductor region It has a source electrode 108a and a drain electrode 108b in contact with 103c. The channel width in the transistor is set to 40 nm.

[0289] The transistor shown in Figure 19(B) consists of a base insulating film 101 and an embedded aluminum oxide layer. It is formed on the embedded insulator 102, and has a semiconductor region 103a, a semiconductor region 103c, and The intrinsic semiconductor region 103b sandwiched between them, and the gate electrode 105 with a width of 33 nm and gate insulation Layer 104 and side wall insulator 106a and side wall insulator 106b and insulator 107 and source electrode 1 It is the same as the transistor shown in Figure 19(A) in that it has 08a and drain electrode 108b. That is the case.

[0290] The difference between the transistor shown in Figure 19(A) and the transistor shown in Figure 19(B) is the side wall insulation. This is the conductivity type of the semiconductor region beneath the edge material 106a and the side wall insulator 106b. Figure 19(A) In the transistor shown, the semiconductor region below the side wall insulators 106a and 106b The domain is n + Semiconductor regions 103a and 103c exhibit the conductivity type shown in Figure 1. In the transistor shown in 9(B), the intrinsic semiconductor region is 103b. That is, Figure 19 In the semiconductor layer shown in (B), semiconductor region 103a (semiconductor region 103c) and gate electric A region is created where pole 105 does not overlap with Loff. This region is called the offset region. The width Loff is called the offset length. As is clear from the diagram, the offset length is the side wall It is the same width as the insulator 106a (side wall insulator 106b).

[0291] Other parameters used in the calculations are as described above. The calculations were performed using a Synopsys device. The simulation software, Sentaurus Device, was used. Figure 16 shows The drain current (I) of the transistor with the structure shown in Figure 19(A) d (Solid line) and mobility (μ, dotted line) gate electrode voltage (V) g It exhibits dependence on the potential difference between the gate electrode and the source. The rain current Id is calculated by setting the drain voltage (potential difference between drain and source) to +1V and the mobility μ This calculation assumes a drain voltage of +0.1V.

[0292] Figure 16(A) shows the gate insulating layer thickness as 15 nm, while Figure 16(B) shows it as 10 nm. This is set to m, and Figure 16(C) is set to 5 nm. The gate insulating layer becomes thinner. The drain current Id (off current), especially in the off state, decreases significantly. On the other hand, mobility The peak value of μ and the drain current I in the ON state. d There is no noticeable change in (on-current). At around 1V of the gate voltage, the drain current was shown to exceed 10 μA, which is required for transistors used in memory cells and the like.

[0293] FIG. 17 shows the gate voltage dependence of the drain current I (solid line) and the mobility μ (dotted line) for a transistor having the structure shown in FIG. 19(B) with an offset length Loff of 5 nm. The drain current I was calculated with the drain voltage set to +1V, and the mobility μ was calculated with the drain voltage set to +0.1V. FIG. 17(A) shows the case where the thickness of the gate insulating layer is 15 nm, FIG. 17(B) shows the case where it is 10 nm, and FIG. 17(C) shows the case where it is 5 nm. d (solid line) and the mobility μ (dotted line). g dependence The drain current I d is calculated with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. FIG. 17(A) shows the case where the thickness of the gate insulating layer is 15 nm, FIG. 17(B) shows the case where it is 1 nm, and FIG. 17(C) shows the case where it is 5 nm.

[0294] Also, FIG. 18 shows the gate voltage dependence of the drain current I (solid line) and the mobility μ (dotted line) for a transistor having the structure shown in FIG. 19(B) with an offset length Loff of 15 nm. The drain current I d (solid line) and the mobility μ (dotted line). The drain current I d is calculated with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. FIG. 18(A) shows the case where the thickness of the gate insulating layer is 1 nm, FIG. 18(B) shows the case where it is 10 nm, and FIG. IS(C) shows the case where it is 5 nm.

[0295] In all cases, as the gate insulating layer becomes thinner, the off-current decreases significantly, while there is no significant change in the peak value of the mobility μ or the on-current.

[0296] The peak of the mobility μ is about 80 cm 2 / Vs in FIG. 16, about 60 cm 2 / Vs in FIG. 17, and about 40 cm / Vs in FIG. 18.2 / Vs is approximately, and the offset length Loff increases. The value decreases as the offset length L increases. Similarly, the off-current also shows a similar trend. On the other hand, the on-current also decreases with an offset length L. It decreases as the off-current increases, but this decrease is much more gradual than the decrease in the off-current. Furthermore, the gate voltage is around 1V in all cases, and the drain current is the same as that used in the transistors in the memory cell. It was shown that the current exceeds the 10 μA required for devices such as ZISTA.

[0297] (Embodiment 6) The oxide semiconductors mainly composed of In, Sn, and Zn, as shown in Embodiments 1 to 5 above, In transistors where the Nellum formation region is formed, the substrate is heated during the formation of the oxide semiconductor to deposit the film. By doing so, or by performing heat treatment after forming an oxide semiconductor film, good properties can be obtained. This can be done. Note that the main component refers to an element present in a composition ratio of 5 atomic percent or more.

[0298] Intentionally heating the substrate after depositing an oxide semiconductor film mainly composed of In, Sn, and Zn. This makes it possible to improve the field-effect mobility of the transistor. This makes it possible to shift the threshold voltage positively and enable normal off mode.

[0299] For example, Figures 20(A) to 20(C) show a channel length with In, Sn, and Zn as the main components. An oxide semiconductor film with L of 3 μm and channel width W of 10 μm, and a gate with a thickness of 100 nm. This describes the characteristics of a transistor using an insulating layer. d The voltage was set to 10V.

[0300] Figure 20(A) shows the process of sputtering In, Sn, and Zn as the main components without intentionally heating the substrate. This is the transistor characteristic when an oxide semiconductor film is formed in this manner. At this time, the field effect transfer... The degree is 18.8 cm 2 / Vsec is obtained. On the other hand, when the substrate is intentionally heated to form an oxide semiconductor film mainly composed of In, S n, Zn, it becomes possible to improve the field-effect mobility. FIG. 20(B) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, Zn is formed by heating the substrate to 200°C. The field-effect mobility is 32.2 cm cm 2 / Vsec is obtained.

[0301] The field-effect mobility can be further increased by performing heat treatment after forming an oxide semiconductor film mainly composed of In, Sn, Zn. FIG. 20(C) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, Zn is sputter-deposited at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm After forming an oxide semiconductor film mainly composed of In, Sn, Zn, heat treatment can further increase the field-effect mobility. FIG. 20(C) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, Zn is sputter-deposited at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm After forming an oxide semiconductor film mainly composed of In, Sn, Zn by sputtering at 200°C, heat treatment is performed at 650°C to show the transistor characteristics. At this time, the field-effect mobility is 34.5 cm / V 2 / V sec is obtained.

[0302] By intentionally heating the substrate, it is expected to have the effect of reducing the incorporation of moisture into the oxide semiconductor film during sputter deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 By intentionally heating the substrate, it can be expected to reduce the incorporation of moisture into the oxide semiconductor film during sputtering deposition. Also, by performing heat treatment after film formation, hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film, and the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is presumably due not only to the removal of impurities by dehydration and dehydrogenation but also to the shortening of the interatomic distance due to densification. Also, by removing impurities from the oxide semiconductor to achieve high purity, crystallization can be achieved. The non-single-crystalline oxide semiconductor thus highly purified is presumably capable of realizing a field-effect mobility exceeding 10 0 cm 2 / Vsec.

[0303] Oxygen ions are implanted into an oxide semiconductor mainly composed of In, Sn, and Zn, and then heat-treated to remove the acid By releasing hydrogen, hydroxyl groups, or water contained in the ion semiconductor, and simultaneously with the heat treatment or The oxide semiconductor may be crystallized by subsequent heat treatment. By performing a crystallization treatment, non-single-crystal oxide semiconductors with good crystallinity can be obtained.

[0304] The effect of intentionally heating the substrate to form a film and / or heat treating it after film formation is due to the electric field. In addition to improving effective mobility, it also contributes to enabling normally-off transistors. It exists. Oxide semiconductors mainly composed of In, Sn, and Zn formed without intentionally heating the substrate. In a transistor where a conductive film is used as the channel formation region, the threshold voltage is shifted to the negative. There is a tendency for this to happen. However, in the case of using an oxide semiconductor film formed by intentionally heating the substrate... In total, this negative shift of the threshold voltage is eliminated. In other words, the threshold voltage is The ZISTA is moving towards being normally off, and this trend is shown in Figures 20(A) and 20(B). This can also be confirmed by the comparison.

[0305] Furthermore, the threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible, and by setting the composition ratio to In:Sn:Zn=2:1:3, the transistor's noise - Mari-off formation can be expected. Also, the target composition ratio is In:Sn:Zn By setting the ratio to 2:1:3, a highly crystalline oxide semiconductor film can be obtained.

[0306] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. More preferably, the temperature is 400°C or higher, and by forming the film or heat treating it at a higher temperature, transient This makes it possible to implement a normal off-season for staff.

[0307] Furthermore, by intentionally heating the substrate during film deposition and / or performing heat treatment after film deposition, gate-by It can improve stability against asthma stress. For example, 2 MV / cm, 150°C. Under the condition of being applied for 1 hour, the drift should be less than ±1.5V, preferably 1.0V. It is possible to obtain less than this.

[0308] In fact, the transistor of sample 1, which has not undergone heat treatment after oxide semiconductor film deposition, and 65 A BT test was performed on the transistor of sample 2, which had been subjected to a heat treatment at 0°C.

[0309] First, set the substrate temperature to 25°C, V d Let the voltage be 10V, and the voltage of the transistor g -I d Measurement of characteristics I went. Also, V d This indicates the drain voltage (potential difference between the drain and source). Next, the substrate temperature Let the temperature be 150°C, V d The voltage was set to 0.1V. Next, the electric field applied to the gate insulating layer 608 V g 20V was applied and held for 1 hour. Next , V g We set the voltage to 0V. Next, we set the substrate temperature to 25°C and V d Let the voltage be 10V, and the voltage of the transistor g -I d Measurements were taken. This is called the Plus BT test.

[0310] Similarly, first set the substrate temperature to 25°C, V d Let the voltage be 10V, and the voltage of the transistor g -I d characteristics The measurement was performed. Next, the substrate temperature was set to 150°C, and V d We set it to 0.1V. Next, the gate The electric field strength applied to the insulating layer 608 is set to -2 MV / cm. g Apply -20V to it. Then, it was held like that for 1 hour. Next, V g We set the voltage to 0V. Next, we set the substrate temperature to 25°C and V d Let the voltage be 10V, and the voltage of the transistor g -I d A measurement was taken. This is called the negative BT test. Bu.

[0311] The results of the positive BT test for sample 1 are shown in Figure 21(A), and the results of the negative BT test are shown in Figure 21(B). The results of the positive BT test for sample 2 are shown in Figure 22(A), and the results of the negative BT test are shown in Figure 22(A). The results are shown in Figure 22(B).

[0312] The threshold voltage fluctuations obtained from the positive BT test and negative BT test of sample 1 are as follows: The values ​​were 1.80V and -0.42V. Also, the positive BT test and negative BT test for sample 2 were performed. The threshold voltage fluctuations observed in the BT test were 0.79V and 0.76V, respectively. Both Sample 1 and Sample 2 showed small fluctuations in threshold voltage before and after the BT test, indicating reliability. It is clear that he is highly reliable.

[0313] Heat treatment can be carried out in an oxygen atmosphere, but first use nitrogen or an inert gas, or reduce the pressure. The heat treatment may be performed below first, followed by heat treatment in an oxygen-containing atmosphere. First, dehydration and dehydration By performing hydrogenation and then adding oxygen to the oxide semiconductor, the effect of the heat treatment is further enhanced. This can be done. Also, to add oxygen later, oxygen ions can be accelerated by an electric field to form an oxide semiconductor film. A method of injection may also be applied.

[0314] Defects due to oxygen vacancies are generated in the oxide semiconductor and at the interface with the film in contact with the oxide semiconductor. Although this is easily done, by introducing an excess of oxygen into the oxide semiconductor through such heat treatment, It becomes possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. This is mainly oxygen present between the lattice, and its oxygen concentration is 1 × 10⁻¹⁶ 16 / cm 3 The above 2 x 10 20 / cm 3 The following method allows the crystal to be incorporated into the oxide semiconductor without causing distortion or other problems. It is possible.

[0315] Furthermore, by heat treatment, the oxide semiconductor can contain at least some crystals. This allows for the creation of more stable oxide semiconductor films. For example, a composition ratio of In:Sn:Zn = 1 Using a 1:1 target, an oxide film was deposited by sputtering without intentionally heating the substrate. The halo pattern of a semiconductor film can be determined by X-ray diffraction (XRD). A crystalline substance is observed. This deposited oxide semiconductor film is then subjected to heat treatment to induce crystallization. This can be done. The heat treatment temperature is arbitrary, but for example, by performing heat treatment at 650°C, X-rays Clear diffraction peaks can be observed through diffraction.

[0316] In fact, we performed XRD analysis on the In-Sn-Zn-O film. For the XRD analysis, we used Bruker Using the AXS D8 ADVANCE X-ray diffractometer, the Out-of-Plane method was used. It was measured.

[0317] Sample A and Sample B were prepared as samples for XRD analysis. Below are the results for Sample A and Sample B. The method for preparing ingredient B will be explained.

[0318] An In-Sn-Zn-O film with a thickness of 100 nm was deposited on a dehydrogenated quartz substrate. .

[0319] The In-Sn-Zn-O film was formed using a sputtering apparatus in an oxygen atmosphere with a power of 100W. The film was deposited as DC. The target was I with an atomic ratio of In:Sn:Zn = 1:1:1. An n-Sn-Zn-O target was used. The substrate heating temperature during film deposition was 200°C. The sample prepared in this manner was designated as Sample A.

[0320] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment involves first heating in a nitrogen atmosphere for 1 hour, and then, without lowering the temperature, in an oxygen atmosphere. The sample prepared in this manner was subjected to a further 1-hour heat treatment.

[0321] Figure 25 shows the XRD spectra of sample A and sample B. In sample A, there is a peak originating from the crystal. Although not observed, in sample B, 2θ was near 35 degrees and 37 degrees to 38 degrees. A peak originating from the crystal was observed at g.

[0322] Thus, oxide semiconductors mainly composed of In, Sn, and Zn are intentionally heated during film deposition. By doing and / or by heat treatment after film formation, the characteristics of the transistor can be improved. Cut.

[0323] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing it from being included or removing it from the film. In other words, oxide semi By removing hydrogen, which acts as a donor impurity in the conductor, higher purity can be achieved, This allows for the normally-off operation of transistors, and the purity of oxide semiconductors can be increased. This makes it possible to reduce the off-current to 1 aA / μm or less. Here, the off-current value The unit indicates the current value per 1 μm of channel width.

[0324] Figure 26 shows the relationship between the transistor's off-current and the reciprocal of the substrate temperature (absolute temperature) during measurement. Here, for simplicity, we multiply the reciprocal of the substrate temperature at the time of measurement by 1000 (1000 / The horizontal axis is T).

[0325] Specifically, as shown in Figure 26, when the substrate temperature is 125°C (398.15K), 1 aA / μm (1 × 10⁻⁶) -18 A / μm or less, substrate temperature 85°C (358.15K) In this case, 100 zA / μm (1 × 10 -19 A / μm or less, substrate temperature room temperature (27℃) In the case of 300.15K, 1 zA / μm (1 × 10⁻¹⁰ -21 Keep it below A / μm. This is possible. Preferably, at a substrate temperature of 125°C, the concentration is 0.1 aA / μm (1 × 10⁻¹⁶). -1 9 (A / μm) or less, at 85°C, 10 zA / μm (1 × 10⁻⁶ A / μm). -20 A / μm) or less At room temperature, 0.1 zA / μm (1 × 10⁻⁶ -22 It can be reduced to less than A / μm.

[0326] However, to prevent hydrogen and moisture from entering the film during the deposition of oxide semiconductor films, the outside of the deposition chamber is used. This aims to sufficiently suppress leaks from outside and degassing from the inner walls of the deposition chamber, thereby increasing the purity of the sputtering gas. Preferably, the sputtering gas has a dew point of -70°C or lower so that moisture is not contained in the film. It is preferable to use the gas shown below. Also, the target itself should contain hydrogen, water, and other impurities. It is preferable to use a highly purified target so that it does not contain any pure substances. Oxide semiconductors, mainly composed of In, Sn, and Zn, can have moisture removed from the film through heat treatment. However, compared to oxide semiconductors mainly composed of In, Ga, and Zn, the moisture release temperature is Because of the high moisture content, it is preferable to form a film that does not contain moisture from the beginning.

[0327] Furthermore, a transistor was produced using sample B, which underwent a heat treatment at 650°C after oxide semiconductor film deposition. In this study, the relationship between substrate temperature and electrical characteristics was evaluated.

[0328] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov The thickness is 0 μm, and dW is 0 μm. Note that V d The voltage was set to 10V. The board temperature was -40°C. The tests were conducted at -25°C, 25°C, 75°C, 125°C, and 150°C. Here, the transistor In this context, the overlapping width between the gate electrode and the pair of electrodes is called Lov, and in relation to the oxide semiconductor film... The overhang of the pair of electrodes is called dW.

[0329] Figure 23 shows I d (Solid line) and field effect mobility (dotted line) V g It shows dependency. Also, Figure 2 Figure 4(A) shows the relationship between substrate temperature and threshold voltage, and Figure 24(B) shows the relationship between substrate temperature and field effect mobility. This shows the relationship.

[0330] Figure 24(A) shows that the threshold voltage decreases as the substrate temperature increases. The voltage range was 1.09V to -0.23V at -40℃ to 150℃.

[0331] Furthermore, Figure 24(B) shows that the field-effect mobility decreases as the substrate temperature increases. The temperature range is -40°C to 150°C and the length is 36 cm. 2 / Vs~32cm 2 It was / Vs. Therefore, it can be seen that the variation in electrical characteristics is small within the temperature range mentioned above.

[0332] The above-mentioned oxide semiconductor, mainly composed of In, Sn, and Zn, is used as the channel formation region. According to Rangista, the off-current is kept below 1 aA / μm while the field-effect mobility is 30c. m 2 / Vsec or greater, preferably 40cm 2 / Vsec or more, more preferably 60cm 2 It can be set to / Vsec or higher, satisfying the on-current value required by the LSI. For example, For a FET with L / W = 33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V It can sometimes supply an on-current of 12 μA or more. Furthermore, it meets the requirements for transistor operation. Sufficient electrical characteristics can be ensured even within the temperature range. For example, transistors made of oxide semiconductors are embedded within integrated circuits made of Si semiconductors. Even so, it is possible to realize integrated circuits with new functions without sacrificing operating speed. Cut. [Examples]

[0333] In this embodiment, an example of a transistor using an In-Sn-Zn-O film as the oxide semiconductor film is presented. This will be explained using Figure 27 and other figures.

[0334] Figure 27 shows the top gate, top contact structure of a coplanar transistor. These are top views and cross-sectional views. Figure 27(A) shows a top view of the transistor. Also, Figure 27( Figure B) shows the cross-section AB corresponding to the dashed line AB in Figure 27(A).

[0335] The transistor shown in Figure 27(B) consists of a substrate 1100 and a base provided on the substrate 1100. The insulating film 1102, the protective insulating film 1104 provided around the base insulating film 1102, and the base High-resistance region 1106a and low-resistance region provided on insulating film 1102 and protective insulating film 1104 An oxide semiconductor film 1106 having a resistive region 1106b, and a structure provided on the oxide semiconductor film 1106 The gate insulating layer 1108 is cut, and the oxide semiconductor film 110 is connected to the gate insulating layer 1108. A gate electrode 1110 is provided superimposed on 6, and is provided in contact with the side surface of the gate electrode 1110. A pair of side wall insulating films 1112 and a pair of films provided in contact with at least the low-resistance region 1106b The electrode 1114, at least an oxide semiconductor film 1106, a gate electrode 1110 and a pair An interlayer insulating film 1116 is provided covering the electrode 1114, and the interlayer insulating film 1116 is provided Wiring 11 provided connected to one of at least one pair of electrodes 1114 through a provided opening It has 18 and.

[0336] Although not shown in the diagram, a protective film is provided covering the interlayer insulating film 1116 and the wiring 1118. It may have the following. By providing the protective film, surface conduction of the interlayer insulating film 1116 occurs This can reduce the small leakage current caused by this, thereby reducing the transistor's off-current. It is possible. [Examples]

[0337] In this example, a different In-Sn-Zn-O film was used as the oxide semiconductor film. Here is another example of ZISTA.

[0338] Figure 28 shows a top view and a cross-sectional view of the structure of the transistor fabricated in this embodiment. Figure 28(A) is a top view of the transistor. Figure 28(B) is a single-point chain view of Figure 28(A). This is a cross-sectional view corresponding to line AB.

[0339] The transistor shown in Figure 28(B) consists of a substrate 600 and an insulating base provided on the substrate 600. A film 602, an oxide semiconductor film 606 provided on the underlying insulating film 602, and an oxide semiconductor film A pair of electrodes 614 in contact with 606, and on the oxide semiconductor film 606 and the pair of electrodes 614 A gate insulating layer 608 is provided, and an oxide semiconductor film 606 is connected via the gate insulating layer 608. The gate electrode 610 is superimposed on the gate insulating layer 608 and the gate electrode 610 The interlayer insulating film 616 that covers the interlayer insulating film 616 and the openings provided in the interlayer insulating film 616 Wiring 618 connected to the pair of electrodes 614, and covering the interlayer insulating film 616 and wiring 618. It has a protective film 620 that has been applied.

[0340] As the substrate 600, a glass substrate is used, and as the underlay insulating film 602, a silicon oxide film is used. As the semiconductor film 606, an In-Sn-Zn-O film is used, and as the pair of electrodes 614, tungsten As the tene film, a silicon oxide film is used as the gate insulating layer 608, and as the gate electrode 610, a silicon oxide film is used. The laminated structure of the tantalum oxide film and the tungsten film is constructed using silica oxide nitride as the interlayer insulating film 616. The laminated structure of the condenser film and the polyimide film is used for the wiring 618, which consists of a titanium film, an aluminum film, The titanium film is formed in this order in a laminated structure, and the protective film 620 is a polyimide film, They used them.

[0341] In the transistor with the structure shown in Figure 28(A), the gate electrode 610 and the pair of electrodes are... The width of the overlap with 614 is called Lov. Similarly, a pair of electrons on the oxide semiconductor film 606 The overhang of the extreme 614 is called dW. [Explanation of symbols]

[0342] 120 Semiconductor Layers 122 Insulating layer 122a Gate Insulation Layer 124 masks 126 Impurity region 128a Grid gate 128b Conductive layer 130 Impurity region 132 Impurity region 134 Channel formation region 136 Insulating layer 138 Insulating layer 140 Insulating layer 142a Source electrode 142b Drain electrode 144 Oxide semiconductor layer 146 Gate Insulation Layer 148a Token 148b Conductive layer 150 Insulating layer 154 Wiring 156 Insulating layer 160 transistors 162 transistors 164 Capacitive elements 170 cell cells 180 Boost Circuit 182 Drive Circuit 184 Drive Circuit 186 Drive Circuit 190 Drive Circuit 192 Drive Circuit 194 Source Line Switching Circuit 500 semiconductor substrates 510 Single-crystal semiconductor substrate 512 Oxide film 514 Embrittlement area 516 Single-crystal semiconductor layer 518 Single-crystal semiconductor layer 701 cabinet 702 cabinet 703 Display section 704 Keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Buttons 715 External Interface 720 eBooks 721 cabinet 723 cabinet 725 Display section 727 Display section 731 Power supply 733 Operation Keys 735 Speakers 737 Shaft 740 cabinets 741 cabinets 742 Display Panel 743 Speakers 744 Microphone 745 Operation Keys 746 Pointing devices 747 Camera Lenses 748 External connection terminal 749 solar cells 750 external memory slots 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television equipment 771 cabinet 773 Display section 775 Stand 780 Remote Control Unit

Claims

1. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the first conductive layer, The second conductive layer is always electrically connected to the first conductive layer. The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer comprises In, Ga, and Zn. The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

2. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the first conductive layer, The second conductive layer has a region in contact with the first conductive layer, The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer comprises In, Ga, and Zn. The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

3. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the channel formation region of the first transistor. The second conductive layer has a region in contact with the first conductive layer, The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer comprises In, Ga, and Zn. The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

4. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the first conductive layer, The second conductive layer is always electrically connected to the first conductive layer. The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

5. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the first conductive layer, The second conductive layer has a region in contact with the first conductive layer, The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

6. A semiconductor device having a first transistor, a second transistor, and a capacitive element, The first insulating layer, A semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region for the first transistor, A second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer for the first transistor, A first conductive layer having a region located above the second insulating layer and functioning as the gate electrode of the first transistor, A third insulating layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the side surface of the first conductive layer, An oxide semiconductor layer having a region located above the third insulating layer and functioning as a channel formation region for the second transistor, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the second transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the second transistor, A fourth insulating layer having a region in contact with the oxide semiconductor layer and functioning as a gate insulating layer for the second transistor, A fourth conductive layer having a region in contact with the fourth insulating layer and functioning as the gate electrode of the second transistor, A fifth conductive layer having a region in contact with the fourth insulating layer and functioning as one of the electrodes of the capacitive element, The second conductive layer has a first region that overlaps with the fifth conductive layer via the fourth insulating layer. The first region has a region that overlaps with the channel formation region of the first transistor. The second conductive layer has a region in contact with the first conductive layer, The third conductive layer is always electrically connected to the semiconductor layer. The semiconductor layer has silicon, The oxide semiconductor layer does not have a region that overlaps with the first conductive layer. The semiconductor device has a laminated structure in which the fourth insulating layer comprises an insulating layer having nitrogen and silicon, and an insulating layer having oxygen and silicon.

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