Memory system and its operating method, memory controller, and memory

Abstract

The object of the present invention is to provide a memory system, a method for operating the same, a memory controller, and a memory. [Solution] Embodiments of the present disclosure disclose a memory system and its operating method, a memory controller, and a memory. The memory system includes a memory. The memory includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The operating method is a step of determining the (n+1)th group of page data according to n groups of received prefix commands and received page data by the peripheral circuits, where n is a positive integer and n+1 is a positive integer less than or equal to m, and placing 2 in the memory cell array n The process includes the step of writing n groups of page data and the (n+1)th group of page data to a memory cell array in order to generate a distinct data state.

Description

[Technical Field]

[0001] Cross-reference of related applications This application is based on Chinese Patent Application No. 202211275605.2, entitled “Memory System and Operation Method Thereof, Memory Controller and Memory,” filed on 18 October 2022, which claims priority to the Chinese Patent Application, incorporated in its entirety by reference herein.

[0002] Embodiments of this disclosure are, but are not limited to, those relating to the semiconductor field, and more particularly to memory systems, methods of operation thereof, memory controllers, and memory. [Background technology]

[0003] NAND memory cells include single-level cells that store 1 bit of data and multi-level cells that store at least 2 bits of data. NAND memory with single-level cells can achieve faster write speeds and higher reliability, but has a smaller storage capacity and is more expensive. NAND memory with multi-level cells has a larger storage capacity and is less expensive, but has a slower write speed and is less reliable.

[0004] However, in some applications, NAND memory needs to achieve not only high write speeds and high reliability with single-level cells, but also large storage capacity and low cost with multi-level cells. Therefore, flexibly configuring NAND memory to realize multiple modes of memory cells has become an urgent technical challenge that needs to be addressed. [Overview of the project] [Means for solving the problem]

[0005] According to a first aspect of the embodiments of the present disclosure, an operating method for a memory system is provided, the memory system includes a memory, the memory includes a memory cell array and peripheral circuits coupled to the memory cell array, the memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1, and the operating method is A step in which peripheral circuits determine the (n+1)th group of page data according to the received prefix command and n groups of received page data, wherein n is a positive integer and n+1 is a positive integer less than or equal to m, 2 n The process includes the step of writing n groups of page data and the (n+1)th group of page data to a memory cell array in order to generate a distinct data state.

[0006] According to a second aspect of the embodiments of the present disclosure, a memory controller is provided, the memory controller is coupled to a memory, the memory includes a memory cell array and peripheral circuits coupled to the memory cell array, the memory cell array includes a memory cell capable of storing m bits of information, where m is a positive integer greater than 1, and the memory controller The peripheral circuit determines the (n+1)th group of page data according to the prefix command and n groups of page data, and places 2 in the memory cell array. n To enable the generation of individual different data states, the system is configured to send a prefix command and n groups of page data to a peripheral circuit, where n is a positive integer and n+1 is a positive integer less than or equal to m.

[0007] According to a third aspect of the embodiments of this disclosure, memory is provided, and the memory is A memory cell array including a memory cell capable of storing m bits of information, Peripheral circuits coupled to the memory cell array and Includes, The peripheral circuit is configured to determine the (n+1)th group of page data according to the received prefix command and n groups of received page data, where n is a positive integer and n+1 is a positive integer less than or equal to m. The peripheral circuitry has two memory cell arrays. n To generate individual distinct data states, the system is further configured to write n groups of page data and the (n+1)th group of page data to the memory cell array.

[0008] According to a fourth aspect of the embodiments of this disclosure, a memory system is provided, and the memory system is A memory according to a third aspect of the embodiments of the present disclosure, A memory controller according to a second aspect of the embodiments of this disclosure, which is coupled to and configured to control the memory, Includes.

[0009] In embodiments of this disclosure, the peripheral circuit determines the (n+1)th group of page data according to the received prefix command and the n groups of received page data, writes the n groups of page data together with the (n+1)th group of page data to the memory cell array, and stores 2 n It is possible to generate multiple different data states. That is, a portion of the memory's storage space can be used as at least one of SLC, MLC, TLC, and QLC. In this way, NAND memory can be flexibly configured to realize multiple modes of memory cells, providing advantages such as fast write speeds, high reliability, large storage capacity, and low cost.

[0010] To more clearly show the detailed description of the present disclosure or the technical solutions in the prior art, the drawings that need to be used in the detailed description or the description of the prior art are briefly introduced below. The accompanying drawings in the following description are some implementation forms of the present disclosure, and it is obvious that other drawings can be obtained for those skilled in the art according to these drawings without creative work. <0******>

Brief Description of the Drawings

Mode for Carrying Out the Invention

[0012] The following examples are provided for a better understanding of the present disclosure and are not limited to the best implementation mode, nor do they limit the content and protection scope of the present disclosure. Any product identical or similar to the present disclosure obtained under the teaching of the present disclosure or by combining the present disclosure with other prior art features falls within the protection scope of the present disclosure.

[0013] In the description of the present disclosure, the directional relationship or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the directional relationship or positional relationship shown in the drawings. For the convenience of explaining the present disclosure and for simplifying the explanation only, it does not imply or suggest that the device or element mentioned must have a specific orientation and be constructed and operate in a specific orientation. Therefore, it should be noted that it should not be construed as limiting the present disclosure. In addition, terms such as "first" and "second" are used only for the purpose of explanation and should not be construed as indicating or suggesting relative importance.

[0014] Figure 1 is a schematic diagram showing different data states of memory according to an exemplary embodiment. Referring to Figure 1, with the development of NAND memory, the number of bits in memory cells increased from 1 bit to 2 bits, 3 bits, and 4 bits, and thus memory cells evolved from single-level cells (SLC) to multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). In response, the number of data states in memory increased from 2 to 4, 8, and 16, so as memory capacity increased and cost decreased.

[0015] Referring to Figure 1(a), the memory cell of an SLC memory stores 1 bit of data. The data state of an SLC memory includes one erase state and one program state. The erase state is marked with E, and the program state is marked with P. The threshold voltage for the program state P is higher than the threshold voltage for the erase state E.

[0016] Referring to Figure 1(b), the memory cells of the MLC memory store 2 bits of data. The data state of the MLC memory includes one erase state and three program states. The erase state is marked with E, and the program states are marked with P1, P2, and P3 in order from the first to the third state. The threshold voltage gradually increases from the P1 state to the P3 state.

[0017] Referring to Figure 1(c), the memory cells of the TLC memory store 3 bits of data. The data state of the TLC memory includes one erase state and seven program states. The erase state is marked with E, and the program states are marked sequentially from the first to the seventh state with P1, P2, P3, P4, P5, P6, and P7. The threshold voltage gradually increases from the P1 state to the P7 state.

[0018] Referring to Figure 1(d), the memory cells of the QLC memory store 4 bits of data. The data states of the QLC memory include one erase state and 15 program states. The erase state is marked with E, and the program states are marked sequentially from the 1st state to the 15th state as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15. The threshold voltage gradually increases from the P1 state to the P15 state.

[0019] With the advancement of 3D NAND technology, the number of stacked layers in memory continues to increase. MLC memory does not exist when the number of stacked layers exceeds 64. Currently, the main 3D NAND product is TLC memory, but when the number of stacked layers exceeds 300, the main 3D NAND product becomes QLC memory.

[0020] Developing new 3D NAND product technologies is costly, especially as the number of stacked layers increases. From a customer demand perspective, low-bit memory is still needed to meet the requirements of better reliability, for example, in the automotive industry. However, the market size for this is not large. From a cost perspective, it is not worthwhile to develop dedicated low-bit memory. For example, if mainstream NAND is TLC memory, there is still some application need for MLC memory. If mainstream NAND is QLC memory, there is still some application need for both TLC and MLC memory. From an application program perspective, this is a mismatch.

[0021] One solution is to develop a general-purpose NAND memory that supports all cell levels (SLC / MLC / TLC / QLC). However, such a solution would place a significant burden on all development teams, including design, verification, validation, and testing. Furthermore, the cost of this work is three times that of SLC memory, especially for the testing and certification teams.

[0022] Figure 2 is a flowchart of a writing method for a memory system shown according to an exemplary embodiment, and Figure 3 is a schematic diagram of the memory system 10 shown according to an exemplary embodiment. As shown in Figures 2 and 3, the writing method consists of at least the following steps: S101: A step in which the controller 11 receives lower page (LP) data and upper page (UP) data, S102: Steps to enable scrambler 13 to randomize LP data and UP data, S103: Steps to enable Error Correction Code (ECC) 14 in order to perform parity checks on randomized LP data and UP data, S104: After performing a parity check, the LP data and UP data are sent to memory, for example, a page buffer. S105: Steps to disable the descrambler 16 and the ECC decoder 15, S106: A step of sending LP data and UP data from memory to the controller 11, S107: A step in which a central processing unit (CPU) on the host side executes firmware (FW) to perform an exclusive OR (NXOR) operation on LP data and UP data in order to generate intermediate page (MP) data, wherein the firmware being executed can be stored in memory. S108: A step of disabling the scrambler 13 and ECC decoder 14 and sending LP / MP / UP data to memory, for example, the page buffer. S109: Send a write command (e.g., 10h) and start the write operation, for example, writing LP / MP / UP data from the page buffer to the memory cell array 12. Includes.

[0023] Figure 4 is a schematic diagram of the memory write state shown according to an exemplary embodiment. Referring to Figure 4, LP / MP / UP data can be written to the memory cell array 12 by a normal writing method, and 3 bits of data can be written into the memory cells of the TLC memory to generate eight different data states, namely the erase state E and the program states P1 to P7. LP / MP / UP data is written to the memory cell array 12 by performing the method shown in Figure 2. 3 bits of data can be stored in the memory cells of the TLC memory to generate four different data states, namely the erase state E and the program states P2, P4, and P6. That is, by performing the method shown in Figure 2, at least a portion of the storage space in the TLC memory can be used as MLC to meet the application needs required for MLC memory.

[0024] However, this method requires execution by the host's CPU, resulting in a complex operating mode. It also requires firmware to run to use the CPU to perform NXOR operations on raw data (e.g., LP data and UP data) to generate MP data, resulting in low efficiency.

[0025] In this regard, embodiments of the present disclosure provide a memory system and a method for operating the same.

[0026] Figure 5 is a flowchart of the operation method of a memory system shown according to an embodiment of the present disclosure. The memory system includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. Referring to Figure 5, the operation method is at least the following steps: S201: A step in which a peripheral circuit determines the (n+1)th group of page data according to the received prefix command and n groups of received page data, wherein n is a positive integer and n+1 is a positive integer less than or equal to m. S202: 2 memory cells in the memory cell array n To generate different data states, the steps include writing n groups of page data and the (n+1)th group of page data to the memory cell array. Includes.

[0027] The memory includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array contains multiple memory cells, each capable of storing m bits of information. For example, the memory is an MLC memory, i.e., m=2. Another example is a TLC memory, i.e., m=3. Yet another example is a QLC memory, i.e., m=4. The peripheral circuits include logic control units, command registers, cache registers, data registers, etc.

[0028] In step S201, the logic control unit in the peripheral circuit reads the prefix command stored in the command register, determines the (n+1)th group of page data according to the read prefix command and the n groups of page data, and may store the (n+1)th group of page data in a cache register or data register. The n groups of page data include at least one of LP data, MP data, UP data, and extra page (XP) data. In a particular embodiment, the peripheral circuit may perform a logical operation on the n groups of page data to generate the (n+1)th group of page data.

[0029] In step S202, upon receiving a write command, n groups of page data and the (n+1)th group of page data are sequentially written to the memory cell array. n Individual, distinct data states are generated within the memory cell array.

[0030] In one example, the memory is MLC memory. If a portion of the storage space within the MLC memory needs to be used as SLC, the peripheral circuitry determines the MP data according to the received prefix command and LP data, and writes the LP data and MP data to the memory cell array to generate two different data states within the memory cell array.

[0031] In one example, the memory is TLC memory. If a portion of the memory space within the TLC memory needs to be used as MLC, the peripheral circuitry determines the UP data according to the received prefix command, LP data, and MP data, and writes the LP data, MP data, and UP data to the memory cell array to generate four different data states within the memory cell array.

[0032] In one example, the memory is TLC memory. If a portion of the storage space within the TLC memory needs to be used as SLC, the peripheral circuitry determines the MP data according to the received prefix command and LP data, and writes at least the LP data and the MP data to the memory cell array to generate two different data states within the memory cell array.

[0033] In one example, the memory is QLC memory. If a portion of the memory space within the QLC memory needs to be used as TLC, the peripheral circuitry determines the XP data according to the received prefix command, LP data, MP data, and UP data, and writes the LP data, MP data, UP data, and XP data to the memory cell array to generate eight different data states within the memory cell array.

[0034] In one example, the memory is QLC memory. If a portion of the storage space within the QLC memory needs to be used as MLC, the peripheral circuitry determines the UP data according to the received prefix command, LP data, and MP data, and writes at least the LP data, MP data, and UP data to the memory cell array to generate four different data states within the memory cell array.

[0035] In one example, the memory is QLC memory. If a portion of the storage space within the QLC memory needs to be used as SLC, the peripheral circuitry determines the MP data according to the received prefix command and LP data, and writes at least the LP data and the MP data to the memory cell array to generate two different data states within the memory cell array.

[0036] In embodiments of the present disclosure, the peripheral circuit determines the (n+1)th group of page data according to the received prefix command and the n groups of received page data, writes the n groups of page data and the (n+1)th group of page data to the memory cell array, and stores 2 n It is possible to generate multiple different data states. That is, a portion of the memory's storage space can be used as at least one of SLC, MLC, TLC, and QLC. In this way, NAND memory can be flexibly configured to realize multiple modes of memory cells, and can have advantages such as fast write speeds, high reliability, large storage capacity, and low cost.

[0037] In addition, the operating mode for determining the (n+1)th group of page data via peripheral circuits within the memory in the embodiments of this disclosure is simpler than logical operations performed by the CPU on the host side, and is beneficial for improving the operational efficiency of the memory while implementing multiple modes of memory cells.

[0038] Furthermore, compared to solutions for developing general-purpose NAND memory, using prefix commands in the operating method provided by the embodiments of this disclosure is more user-friendly, potentially compatible with existing NAND protocols, and leads to savings in development costs.

[0039] In some embodiments, when n+1 is equal to m, the prefix command includes a first subprefix command A, where the first subprefix command A performs an XOR operation on n groups of page data.

[0040] Step S201 described above includes the step of performing an XOR operation on n groups of page data according to a first subprefix command A in order to generate the mth group of page data by a peripheral circuit.

[0041] Step S202 described above includes writing n groups of page data and the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell.

[0042] Taking QLC memory as an example, the memory controller sends a first subprefix command A, LP data, MP data, and UP data to the peripheral circuit, and the peripheral circuit performs an XOR operation on the LP data, MP data, and UP data according to the first subprefix command A to generate XP data. The memory controller sends a write command (e.g., 80h) to the peripheral circuit, and the peripheral circuit begins writing the LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell, generating eight different data states, i.e., as shown in (2) in Figure 6, a portion of the storage space in the QLC memory is used as TLC.

[0043] Note that the first subprefix command A is sent before the 80h command. Specifically, Figure 7(b) shows a write timing diagram to illustrate the use of a portion of the storage space in QLC memory as TLC, and the timing diagram includes the data type signal Cycle Type and the data signal DQx. When writing TLC mode to QLC memory, the first subprefix command A is sent first, followed by the 80h command after the XP data has been determined. Subsequently, address signals C1, C2, R1, R2, and R3 are sent during the address period. The address signals allow for the determination of the logical address of the memory cell to be written to, and LP data, MP data, UP data, and XP data are written to the memory cell. Here, the logical address includes the logical unit number (lun), the plane, the block, and the page address.

[0044] In a specific example, as shown in Figure 8(a), the LP data is the sequence (1111111100000000), the MP data is the sequence (1111000000001111), and the UP data is the sequence (1100001111000011). The peripheral circuit performs an XOR operation on the LP data, MP data, and UP data according to the first subprefix command A in order to generate XP data as the (1100110011001100) sequence, writes the LP data, MP data, UP data, and XP data to the memory cell array, and generates eight data states in the memory cell array as shown in Figure 8(b), these eight data states are erase state E (1111), program state P2 (1100), program state P4 (1001), program state P6 (1010), program state P8 (0011), program state P10 (0000), program state P12 (0101), and program state P14 (0110).

[0045] In this example, to convey the disclosure to those skilled in the art, the LP data is, for example, the sequence (1111111100000000), the MP data is the sequence (1111000000001111), and the UP data is the sequence (1100001111000011), but it should be noted that the disclosure is not limited thereto. The LP data, MP data, and UP data can also be other sequences consisting of "1"s and "0"s, as long as any eight different data states from erase state E to program state P15 can be generated in QLC memory after the XP data is generated by executing a first prefix command A on the LP data, MP data, and UP data.

[0046] Preferably, the LP data is the (1111111100000000) sequence, the MP data is the (1111000000001111) sequence, and the UP data is the (1100001111000011) sequence. As shown in Figure 8(b), when a portion of the memory space in the QLC memory is used as TLC, the threshold voltage difference M2 between two adjacent data states is essentially the same, i.e., the read margin distribution is relatively uniform, which is beneficial in ensuring the accuracy of the read operation when used as TLC.

[0047] In embodiments of this disclosure, if n+1 is equal to m, the peripheral circuit may perform an XOR operation on n groups of page data according to a first subprefix command to generate the m-th group of page data, and write the n groups of page data and the m-th group of page data to the memory cell array. While storing m bits of information in the memory cell, 2 nIt is possible to generate individual different data states. For example, if the memory is QLC, a portion of the storage space within the QLC memory can be used as TLC so that the memory has at least two modes of memory cells. This helps to increase the application scenarios of the memory and better meet customer needs while remaining compatible with mainstream memory.

[0048] In other embodiments, if n+1 is equal to m, the peripheral circuit may also perform an NXOR or copy operation on n groups of page data according to a prefix command to generate the mth group of page data. Here, the selection can be made according to the actual situation, and this disclosure does not impose any particular limitations thereon.

[0049] In some embodiments, before performing step S202, the above operating method further includes the steps of storing n groups of page data in a plurality of data registers, each of which is used to store a group of page data, and storing the m-th group of page data in a cache register. The peripheral circuitry includes a page buffer, and data registers or cache registers may be placed within the page buffer to buffer the page data.

[0050] As illustrated in Figure 9, LP data (1111111100000000) is stored in data register 1, MP data (1111000000001111) is stored in data register 2, and UP data (1100001111000011) is stored in data register 3. After XP data (1100110011001100) is generated, the XP data is stored in the cache register, and after receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0051] In some embodiments, when the difference between m and n is 2, the prefix command includes a second subprefix command B, which indicates that an NXOR operation is performed on n groups of page data.

[0052] Step S201 described above includes the step of performing an NXOR operation on n groups of page data according to a second subprefix command B in order to generate the (n+1)th group of page data by the peripheral circuit.

[0053] The above operation method further includes the step of writing the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell, where the m-th group of page data is either a sequence of all zeros or a sequence of all ones.

[0054] Taking QLC memory as an example, the memory controller sends a second subprefix command B, LP data, and MP data to the peripheral circuit, which then performs an NXOR operation on the LP data and MP data according to the second subprefix command B to generate UP data. A write command (e.g., 80h) is sent to the peripheral circuit, which then begins writing the LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell and generate four different data states, i.e., as shown in (3) in Figure 6, a portion of the storage space in the QLC memory is used as MLC. Here, the XP data is either a sequence of all zeros or a sequence of all ones.

[0055] Note that the second subprefix command B is sent before the 80h command. Specifically, Figure 7(c) shows the timing diagram when a portion of the storage space in QLC memory is used as MLC. When writing MLC mode to QLC memory, the second subprefix command B is sent first, followed by the 80h command after the UP data has been determined. Then, during the address period, address signals C1, C2, R1, R2, and R3 are sent. The address signals allow the logical address of the memory cell to be written to to be determined, and LP data, MP data, UP data, and XP data are written to the memory cell.

[0056] In a specific example, as shown in Figure 8(a), the LP data is the (1111111100000000) sequence and the MP data is the (1111000000001111) sequence. The peripheral circuit performs an NXOR operation on the LP data and MP data according to the second subprefix command B to generate UP data as the (1111000011110000) sequence and XP data as the (1111111111111111) sequence, and writes the LP data, MP data, UP data, and XP data to the memory cell array to generate four data states in the memory cell array, as shown in Figure 8c. These four data states are erase state E (1111), program state P4 (1001), program state P8 (0011), and program state P12 (0101).

[0057] In this example, the LP data is the (1111111100000000) sequence, the MP data is the (1111000000001111) sequence, and the XP data is the (1111111111111111) sequence, which are taken as examples for illustration to convey the present disclosure to those skilled in the art. However, the present disclosure is not limited thereto. As long as any four different data states from the erased state E to the program state P15 can be generated in the QLC memory after the second prefix command B is executed on the LP data and the MP data to generate the UP data, the LP data and the MP data can be other sequences composed of "1" and "0", or the XP data can be a sequence of all 0s.

[0058] Preferably, the LP data is the (1111111100000000) sequence, the MP data is the (1111000000001111) sequence, and the XP data is the (1111111111111111) sequence. As shown in FIG. 8(b), when a part of the storage space in the QLC memory is used as MLC, the threshold voltage difference M3 between two adjacent data states is basically the same, that is, the read merge distribution is relatively uniform, which is beneficial to ensuring the accuracy of the read operation when used as MLC.

[0059] In an embodiment of the present disclosure, when the difference between m and n is 2, the peripheral circuit may execute an XOR operation on n groups of page data according to the second sub-prefix command to generate the (n + 1)-th group of page data, and write the n groups of page data, the (n + 1)-th group of page data, and the m-th group of page data into the memory cell array. While storing m-bit information in the memory cell, 2 nIt is possible to generate individual different data states. For example, if the memory is QLC, a portion of the storage space within the QLC memory can be used as MLC so that the memory has at least two modes of memory cells. This helps to increase the application scenarios of the memory and better meet customer needs while remaining compatible with mainstream memory.

[0060] In other embodiments, if the difference between m and n is 2, the peripheral circuit may further perform an XOR or copy operation on n groups of page data according to a prefix command to generate the (n+1)th group of page data. Here, the selection can be made according to the actual situation, and this disclosure does not impose any particular limitations thereon.

[0061] In some embodiments, before performing step S202, the above operation method further includes the step of storing n groups of page data and the (n+1)th group of page data in a plurality of data registers, each of which is used to store a group of page data, and before writing the mth group of page data to the memory cell array, the above operation method further includes the step of storing the mth group of page data in a cache register.

[0062] As illustrated in Figure 9, LP data (1111111100000000) is stored in data register 1, MP data (1111000000001111) is stored in data register 2, and XP data (11111111111111111) is stored in the cache register. After UP data is generated, UP data (1111000011110000) is stored in data register 3. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0063] In some embodiments, when the difference between m and n is 3, the prefix command includes a third subprefix command C, which indicates that the (n+1)th group of page data is equal to the nth group of page data.

[0064] Step S201 described above includes a step in which peripheral circuits perform a copy operation on n groups of page data according to a third subprefix command C in order to generate the (n+1)th group of page data.

[0065] The above operation method further includes the step of writing the (n+2)th group of page data and the mth group of page data to the memory cell array in order to store m bits of information in the memory cell, where the (n+2)th group of page data and the mth group of page data are either a sequence of all zeros or a sequence of all ones.

[0066] Taking QLC memory as an example, the memory controller sends a third subprefix command C and LP data to the peripheral circuit, which then performs a copy operation on the LP data according to the third subprefix command C to generate MP data. That is, MP data is the same as LP data. A write command (e.g., 80h) is sent to the peripheral circuit, which then begins writing LP data, MP data, UP data, and XP data to the memory cell array to store 4 bits of information in the memory cell and generate two different data states, i.e., as shown in (4) in Figure 6, a portion of the storage space in the QLC memory is used as SLC. Here, the UP data and XP data are sequences of all 0s or sequences of all 1s.

[0067] Note that the third subprefix command C is sent before the 80h command. Specifically, Figure 7(d) shows the timing diagram when a portion of the storage space in QLC memory is used as SLC. When writing SLC mode to QLC memory, the third subprefix command C is sent first, followed by the 80h command after the UP data has been determined. Then, during the address period, address signals C1, C2, R1, R2, and R3 are sent. The address signals allow the logical address of the memory cell to be written to to be determined, and LP data, MP data, UP data, and XP data are written to the memory cell.

[0068] In a specific example, as shown in Figure 8(a), the LP data is in the (1111111100000000) sequence, and the peripheral circuit generates MP data as the (1111111100000000) sequence, generates UP data as the (1111111111111111) sequence, and generates XP data as the (1111111111111111) sequence. To achieve this, the peripheral circuit performs a copy operation on the LP data, and as shown in Figure 8d, it writes the LP data, MP data, UP data, and XP data to the memory cell array to generate two data states in the memory cell array, which are the erase state E(1111) and the program state P8(0011), respectively.

[0069] In this example, the LP data is the (1111111100000000) sequence, the UP data is the (1111111111111111) sequence, and the XP data is the (1111111111111111) sequence, and it should be noted that these are taken as illustrative examples to convey the disclosure to those skilled in the art. However, the disclosure is not limited to these. The LP data may be any other sequence consisting of "1"s and "0"s, or the UP data and XP data may be sequences of all 0s, as long as any two different data states from the erase state E to the program state P15 can be generated in the QLC memory after the third prefix command C is executed on the LP data to generate the MP data.

[0070] Preferably, the LP data is a (1111111100000000) sequence, the UP data is a (1111111111111111) sequence, and the XP data is a (1111111111111111) sequence. As shown in Figure 8(b), when a portion of the storage space in the QLC memory is used as SLC, the threshold voltage difference M4 between the erase state E and the program state P8 is relatively large, which is This is useful for ensuring the accuracy of reading operations when used as an MLC.

[0071] In embodiments of the present disclosure, if the difference between m and n is 3, the peripheral circuit may perform a copy operation on n groups of page data according to a third subprefix command to generate the (n+1)th group of page data, and write the n groups of page data, the (n+1)th group of page data, the (n+2)th group of page data, and the mth group of page data to the memory cell array. While storing m bits of information in the memory cell, 2 nIt is possible to generate individual different data states. For example, if the memory is QLC, a portion of the storage space within the QLC memory can be used as SLC, so that the memory has at least two modes of memory cells. This helps to increase the application scenarios of the memory and better meet customer needs while remaining compatible with mainstream memory.

[0072] In some embodiments, before performing step S202, the above operating method further includes the step of storing n groups of page data and the (n+1)th group of page data in a plurality of data registers, each of which is used to store a group of page data.

[0073] Before writing the (n+2)th group of page data and the mth group of page data to the memory cell array, the above operation method further includes the steps of storing the (n+2)th group of page data in a data register and storing the mth group of page data in a cache register.

[0074] As illustrated in Figure 9, LP data (1111111100000000) is stored in data register 1, UP data (1111111111111111) is stored in data register 3, and XP data (11111111111111111) is stored in the cache register. After MP data is generated, MP data (1111111100000000) is stored in data register 2. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written to the memory cell array.

[0075] In some embodiments, before determining the (n+1)th group of page data, the above operation method, The steps include determining whether the peripheral circuit has received a prefix command and generating the determination result, If the determination result indicates that the peripheral circuit has received a prefix command, the step is to determine the (n+1)th group of page data according to the received prefix command and n groups of page data, If the judgment result indicates that the peripheral circuit has not received the prefix command, then 2 m To generate individual different data states, the steps include writing m groups of page data to a memory cell array. It also includes.

[0076] Taking QLC memory as an example, a logic control unit in the peripheral circuit can read the command register and, based on the read result, determine whether the command register stores a prefix command (e.g., a first subprefix command, a second subprefix command, or a third subprefix command). If the read result indicates that the prefix command is stored in the command register, the peripheral circuit determines the (n+1)th group of page data according to the prefix command and n groups of page data, i.e., a portion of the QLC memory's storage space is used as TLC, MLC, or SLC.

[0077] If the read result indicates that there is no prefix command stored in the command register, the 80h command is sent to the peripheral circuit, which stores m bits of information in the memory cell and 2 in the memory cell array. m To generate m different data states, m groups of page data are written to the memory cell array. Here, as shown in (1) in Figure 6, the storage space for writing the m groups of page data is used as QLC.

[0078] In a specific example, as shown in Figure 8(a), the LP data is the sequence (1111111100000000), the MP data is the sequence (1111000000001111), the UP data is the sequence (1100001111000011), and the XP data is the sequence (1001100110011001). The peripheral circuit writes LP data, MP data, UP data, and XP data to the memory cell array according to the 80h command, generating 16 data states in the memory cell array as shown in Figure 8(a). These 16 data states are erase state E(1111), program state P1(1110), program state P2(1100), program state P3(1101), program state P4(1001), program state P5(1000), program state P6(1010), program state P7(1011), program state P8(0011), program state P9(0010), program state P10(0000), program state P11(0001), program state P12(0101), program state P13(0100), program state P14(0110), and program state P15(0111).

[0079] In embodiments of this disclosure, a peripheral circuit determines whether it has received a prefix command and generates a determination result, which in turn determines whether a portion of the storage space of the QLC memory is to be used as at least one of SLC, MLC, and TLC, thus contributing to the precise configuration of the NAND memory.

[0080] In some embodiments, the above operating method further includes the step of the peripheral circuit storing a group of page data from the n groups of page data in a spare data register if a data register is corrupted. For example, referring to Figure 9, if data register 1 is corrupted, the peripheral circuit stores the LP data in spare data register 4, and / or if data register 2 is corrupted, the peripheral circuit stores the MP data in spare data register 5, and so on.

[0081] In this example, only two spare data registers are shown, and it should be noted that the number of spare data registers in memory is not limited to two, but could be one, three, or more, and this is not limited by this disclosure. In actual applications, the number of spare data registers can be reasonably determined according to the requirements.

[0082] Embodiments of this disclosure also provide a memory controller. The memory controller is coupled to a memory. The memory includes a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The memory controller determines the (n+1)th group of page data according to the peripheral circuits, which have a prefix command and n groups of page data, and places 2 in the memory cell array. n It is configured to send a prefix command and n groups of page data to a peripheral circuit to generate n different data states, where n is a positive integer and n+1 is a positive integer less than or equal to n.

[0083] In some embodiments, the prefix command includes a first subprefix command used to indicate that an XOR operation is performed on n groups of page data.

[0084] Specifically, the memory controller is configured to send a first subprefix command and n groups of page data to the peripheral circuit instructing it to perform an XOR operation on n groups of page data according to the first subprefix command in order to generate the m-th group of page data, where n+1 is equal to m.

[0085] In some embodiments, the prefix command includes a second subprefix command used to indicate that an NXOR operation is performed on n groups of page data.

[0086] Specifically, the memory controller is configured to send a second subprefix command and n groups of page data to peripheral circuits in order to cause them to perform an XOR operation on n groups of page data according to the second subprefix command in order to generate the (n+1)th group of page data.

[0087] The memory controller is further configured to send the m-th group of page data to the peripheral circuit, where the m-th group of page data is either a sequence of all zeros or a sequence of all ones, and the difference between m and n is 2.

[0088] In some embodiments, the prefix command includes a third subprefix command used to indicate that the (n+1)th group of page data is equal to the nth group of page data.

[0089] Specifically, the memory controller is configured to send a third subprefix command and n groups of page data to peripheral circuits in order to cause them to perform copy operations on n groups of page data according to the third subprefix command in order to generate the (n+1)th group of page data.

[0090] The memory controller is further configured to transmit the (n+2)th group of page data and the mth group of page data to the peripheral circuit, where the (n+2)th group of page data and the mth group of page data are either a sequence of all 0s or a sequence of all 1s, and the difference between m and n is 3.

[0091] In some embodiments, the memory controller is further configured to send a write command to the peripheral circuit after sending a prefix command, causing the peripheral circuit to write at least n groups of page data and the (n+1)th group of page data to the memory cell array according to the write command.

[0092] Figure 10 is a schematic diagram of memory 100 as shown in accordance with an embodiment of the present disclosure. Referring to Figure 10, memory 100 is A memory cell array 101 including a memory cell 106 capable of storing m bits of information, Peripheral circuit 102 coupled to memory cell array 101 and Includes, The peripheral circuit 102 is configured to determine the (n+1)th group of page data according to the received prefix command and n groups of received page data, where n is a positive integer and n+1 is a positive integer less than or equal to m. The peripheral circuit 102 has two memory cell arrays 101. n To generate individual different data states, the system is further configured to write n groups of page data and the (n+1)th group of page data to the memory cell array 101.

[0093] The memory cell array 101 may be an array of NAND flash memory cells. The memory cell array 101 is provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically. In some implementations, each NAND memory string 108 includes a plurality of memory cells 106 that are coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0094] In some implementations, each memory cell 106 has two possible data states and is therefore a single-level cell capable of storing 1 bit of data. For example, the first data state "0" may correspond to a first voltage range, and the second data state "1" may correspond to a second voltage range.

[0095] In some embodiments, each memory cell 106 is a cell capable of storing two or more bits of data in five or more data states. For example, each cell may store two bits (also called a multilevel cell), three bits (also called a triple-level cell), or four bits (also called a quad-level cell). Each multilevel cell can be programmed to assume a range of possible nominal storage values. In one example, if each multilevel cell stores two bits of data, the multilevel cell can be programmed to assume one of three possible data states from the erase state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erase state.

[0096] As shown in Figure 10, each NAND memory string 108 may include a source selection transistor (SST) 110 at its source terminal and a drain selection transistor (DST) 112 at its drain terminal. The source selection transistor 110 and drain selection transistor 112 may be configured to activate the selected NAND memory string 108 (a column of the array) during read and write operations.

[0097] In some implementations, the sources of NAND memory strings 108 within the same memory block 104 are connected via the same source line (SL) 114. In other words, according to some implementations, all NAND memory strings 108 within the same memory block 104 have an array common source (ACS).

[0098] In some implementations, the drain selection transistor 112 of each NAND memory string 108 is coupled to the corresponding bit line 116, allowing data to be read from the bit line 116 via an output bus (not shown).

[0099] In some implementations, each NAND memory string 108 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the drain selection transistor 112) or a deselection voltage (e.g., 0V) to the corresponding drain selection gate via one or more drain selection gate lines 111, where the selection voltage is used to turn on the drain selection transistor 112 and the deselection voltage is used to turn off the drain selection transistor 112. And / or, in some implementations, each NAND memory string 108 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the source selection transistor 110) or a deselection voltage (e.g., 0V) to the corresponding source selection gate via one or more source selection gate lines 115, where the selection voltage is used to turn on the source selection transistor 110 and the deselection voltage is used to turn off the source selection transistor 110.

[0100] As shown in Figure 10, the NAND memory string 108 may be organized into multiple memory blocks 104, each of which may have a common source line 114 (e.g., connected to ground). In some implementations, each memory block 104 is the basic data unit for the erase operation; that is, all memory cells on the same memory block 104 are erased simultaneously.

[0101] In some examples, the erase operation may be performed at the half-block level, the quarter-block level, or at any appropriate number or percentage of blocks. Memory cells 106 of adjacent NAND memory strings 108 may be connected by word lines 118 that select which rows of memory cells 106 are affected by read and write operations.

[0102] In some implementations, each word line 118 is referred to as a memory page 120. The size of the memory page 120 in bits may relate to the number of NAND memory strings 108 connected by the word lines 118 in the memory block 104. Each word line 118 may contain multiple control gates (gate electrodes) in each memory cell 106 within the corresponding memory page 120, and gate lines connecting the control gates. A memory cell row can be understood as multiple memory cells 106 located within the same memory page 120.

[0103] Figure 11 is a cross-sectional view of a NAND memory string 108 shown according to an embodiment of the present disclosure. As shown in Figure 11, the NAND memory string 108 may extend perpendicularly onto a substrate 202 through a memory stack layer 204. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0104] The memory stack layer 204 may include alternating gate conductive layers 206 and gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack layer 204 may determine the number of memory cells 106 in the memory cell array 101.

[0105] The gate conductive layer 206 may include, but is not limited to, conductive materials including tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 may include a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 206 may include a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, extending laterally at the top of the memory stack layer 204 as a drain selection gate line 111, extending laterally at the bottom of the memory stack layer 204 as a source selection gate line 115, or extending laterally between the drain selection gate line 111 and the source selection gate line 115 as a word line 118.

[0106] As shown in Figure 11, the NAND memory string 108 includes a channel structure 212 extending vertically through the memory stack layer 204. In some embodiments, the channel structure 212 includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel 220) and a dielectric material (e.g., as a memory film 218). In some embodiments, the semiconductor channel 220 includes silicon, e.g., polysilicon. In some embodiments, the memory film 218 is a composite dielectric layer including a tunnel layer 226, a memory layer 224 (also called a "charge trap / memory layer"), and a barrier layer 222. The channel structure 212 may have a cylindrical shape (e.g., columnar shape). According to some embodiments, the semiconductor channel 220, tunnel layer 226, memory layer 224, and barrier layer 222 are arranged radially in this order from the center of the cylinder toward the outer surface of the cylinder. The tunnel layer 226 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 224 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 222 may include silicon oxide, silicon oxynitride, high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 218 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0107] According to some embodiments, as shown in Figure 11, wells 214 (e.g., P-wells and / or N-wells) are formed within the substrate 202, and the source terminals of the NAND memory string 108 are in contact with the wells 214. In some implementations, the NAND memory string 108 further includes a channel plug 216 at the drain terminal of the NAND memory string 108. It should be understood that additional components of the memory cell array 101 may be formed, including, but are not limited to, gate line gaps / source contacts, local contacts, interconnection layers, etc., although these are not shown in Figure 11.

[0108] Referring back to Figure 10, the peripheral circuit 102 may be coupled to the memory cell array 101 via the bit line 116, word line 118, source line 114, source selection gate line 115, and drain selection gate line 111. The peripheral circuit 102 may include any suitable analog, digital, and mixed-signal circuits to apply voltage and / or current signals to each memory cell 106 via the bit line 116, word line 118, source line 114, source selection gate line 115, and drain selection gate line 111, and to sense the voltage and / or current signals from each memory cell 106 to facilitate the operation of the memory cell array 101.

[0109] In some embodiments, if n+1 is equal to m, the prefix command includes a first subprefix command, which indicates that an XOR operation is performed on n groups of page data.

[0110] Specifically, the peripheral circuit 102 is configured to perform an XOR operation on n groups of page data according to a first subprefix command in order to generate the mth group of page data.

[0111] The peripheral circuit 102 is also configured to write n groups of page data and the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell.

[0112] In some embodiments, the peripheral circuit 102 is A plurality of data registers used to store n groups of page data, wherein each data register is used to store a group of page data, A cache register used to store the mth group of page data and Includes.

[0113] In some embodiments, the peripheral circuit 102 is It includes a spare data register used to store a group of page data within n groups of page data when a data register becomes corrupted.

[0114] In some embodiments, when the difference between m and n is 2, the prefix command includes a second subprefix command, which indicates that an NXOR operation is performed on n groups of page data.

[0115] Specifically, the peripheral circuit 102 is configured to perform an NXOR operation on n groups of page data according to a second subprefix command in order to generate the (n+1)th group of page data.

[0116] The peripheral circuit 102 is further configured to write the mth group of page data to the memory cell array in order to store m bits of information in the memory cell, where the mth group of page data is either a sequence of all zeros or a sequence of all ones.

[0117] In some embodiments, the peripheral circuit 102 is A plurality of data registers used to store n groups of page data and the (n+1)th group of page data, wherein each data register is used to store a group of page data. A cache register used to store the mth group of page data and Includes.

[0118] In some embodiments, if the difference between m and n is 3, the prefix command includes a third subprefix command, the third subprefix command indicating that the (n+1)th group of page data is equal to the nth group of page data.

[0119] Specifically, the peripheral circuit 102 is configured to perform a copy operation on n groups of page data according to a third subprefix command in order to generate the (n+1)th group of page data.

[0120] The peripheral circuit 102 is further configured to write the (n+2)th group of page data and the mth group of page data to the memory cell array in order to store m bits of information in the memory cell, where the (n+2)th group of page data and the mth group of page data are either a sequence of all zeros or a sequence of all ones.

[0121] In some embodiments, the peripheral circuit 102 is A plurality of data registers used to store n groups of page data, the (n+1)th group of page data, and the (n+2)th group of page data, wherein each data register is used to store a group of page data. A cache register used to store the mth group of page data and Includes.

[0122] In some embodiments, the peripheral circuit 102 is Before determining the (n+1)th group of page data, determine whether a prefix command has been received and generate a determination result. If the result indicates that a prefix command has been received, the (n+1)th group of page data is determined according to the received prefix command and the n groups of page data. If the judgment result indicates that no prefix command has been received, then 2 m To generate individual different data states, m groups of page data are written to the memory cell array. It is further configured in this way.

[0123] The peripheral circuitry 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 12 shows several exemplary peripheral circuits 102, including a page buffer / sense amplifier 304, a column decoder / bit-line (BL) driver 306, a row decoder / word-line (WL) driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuits not shown in Figure 12 may be included.

[0124] The page buffer / sense amplifier 304 may be configured to read data from the memory cell array 101 and write (program) data to the memory cell array 101 according to a control signal from the control logic unit 312. In one example, the page buffer / sense amplifier 304 may store one page of write data (programmed data) to be programmed into one memory page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that data is correctly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may further sense a low-power signal from the bit line 116 representing data bits stored in the memory cell 106 and amplify small voltage swings during read operations to a recognizable logic level. The column decoder / bit line driver 306 may be controlled by the control logic unit 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from the voltage generator 310.

[0125] The row decoder / word line driver 30 may be controlled by the control logic unit 312 and configured to select / deselect memory blocks 104 of the memory cell array 101 and select / deselect the word line of memory block 104. The row decoder / word line driver 308 controls the word line voltage (V) generated from the voltage generator 310. WLThe row decoder / word line driver 308 may be further configured to drive the word line 118 using the row decoder / word line driver 308. In some implementations, the row decoder / word line driver 308 may also select / deselect and drive the source selection gate line 115 and the drain selection gate line 111. As described in detail below, the row decoder / word line driver 308 is configured to perform an erase operation on the memory cell 106 coupled to the selected word line 118. The voltage generator 310 may be controlled by the control logic unit 312 and may be configured to generate word line voltages (e.g., read voltage, write voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0126] The control logic unit 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 314 may be coupled to the control logic unit 312 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 may be coupled to the control logic unit 312 and function as a control buffer that buffers control commands received from a host (not shown) and relays them to the control logic unit 312, and buffers status information received from the control logic unit 312 and relays it to the host. Interface 316 may also be coupled to the column decoder / bit line driver 306 via the data bus 318 and function as a data I / O interface and data buffer that buffers data and relays it to and from the memory cell array 101.

[0127] It should be emphasized that the peripheral circuit 102 is configured to perform a write operation provided by the embodiments of this disclosure on a selected row of memory cells among a plurality of rows of memory cells.

[0128] Figure 13 is a schematic diagram of a memory system 400 shown according to an embodiment of the present disclosure. Referring to Figure 13, the memory system 400 is: One or more memories 100 as described in the above embodiment, A memory controller 406, as described in the above embodiment, is coupled to the memory 100 and configured to control the memory 100. Includes.

[0129] System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-car computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having internal storage.

[0130] As shown in Figure 13, the system 400 may include a host 408 and a storage subsystem 402 having one or more memories 100. The storage subsystem further includes a memory controller 406. The host 408 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 408 may be configured to send data to the memory 100, or the host 408 may be configured to receive data from the memory 100.

[0131] Memory 100 may be any memory device disclosed herein. Memory 100 (e.g., a NAND flash memory device (e.g., a 3D NAND flash memory device)) can reduce leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further size reduction of the drive transistor.

[0132] In some implementations, the memory controller 406 is further coupled to the host 408. The memory controller 406 manages the data stored in the memory 100 and can communicate with the host 408.

[0133] In some implementations, the memory controller 406 is designed to operate in low-duty-cycle environments such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones.

[0134] In several implementations, the memory controller 406 is designed for operation in solid-state drives (SSDs) or embedded multimedia cards (eMMCs) in high-duty-cycle environments. SSDs or eMMCs are used as data storage in mobile devices such as smartphones, tablet computers, and laptop computers, as well as in enterprise memory arrays.

[0135] The memory controller 406 may be configured to control the operation of the memory 100, such as read operations, erase operations, and program operations. The memory controller 406 may be further configured to manage various functions related to data stored in or to be stored in the memory 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 406 may be further configured to process error correction codes (ECC) for data read from or written to the memory 100.

[0136] The memory controller 406 may further perform any other appropriate functions, such as formatting the memory 100. The memory controller 406 may communicate with an external device (e.g., host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Device Electronics (IDE) protocol, or Firewire protocol.

[0137] The memory controller 406 and one or more memory units 100 can be integrated into various types of storage devices, for example, contained within the same package (e.g., a universal flash storage (UFS) package or an eMMC package). In other words, the memory system 400 can be implemented and packaged in various types of final electronic products.

[0138] In one example, as shown in Figure 14, a memory controller 406 and a single memory 100 may be integrated into a memory card 502. The memory card 502 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, ES-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may further include a memory card connector 504 that connects the memory card 502 to a host (for example, host 408 in Figure 13).

[0139] In another example, as shown in Figure 14b, a memory controller 406 and multiple memory units 100 may be integrated into a solid-state drive (SSD) 506. The solid-state drive 506 may further include a solid-state drive connector 508 that connects the solid-state drive 506 to a host (e.g., host 408 in Figure 13). In some implementations, the storage capacity and / or operating speed of the solid-state drive 506 is greater than that of the memory card 502.

[0140] It can be understood that the memory controller 406 can perform the operating methods provided by any embodiment of the present disclosure.

[0141] Clearly, the embodiments described above are not limiting to implementation forms, but merely examples for clarity. Those skilled in the art can make various other modifications or alterations based on the above description. It is not necessary, and impossible, to comprehensively enumerate all implementation forms in this specification. Any obvious modifications or alterations derived therefrom fall within the scope of protection created by this disclosure. [Explanation of symbols]

[0142] 1 data register 2 data registers 3 data registers 4. Spare data registers 5. Spare data registers 10 Memory System 11 Controllers 12 memory cell array 13 Scrambler 14 ECC encoders 15 ECC Decoders 16 Desk Rambra 100 memory 101 memory cell array 102 Peripheral Circuits 104 memory blocks 106 memory cells 108 NAND memory string 110 Source Select Transistor (SST), Source Select Transistor 111 Drain Selection Gate Line 112 Drain Select Transistor (DST), Drain Select Transistor 114 Source line (SL), Source line 115 Source Selection Gate Line 116-bit line 118 Wordlines 120 memory pages 202 circuit boards 204 Memory Stack Layer 206 Gate conductive layer 208 Gate dielectric layer 212-channel structure 214 wells 216 Channel Plug 218 Memory Membrane 220 semiconductor channels 222 Barrier layer 224 Memory layer 226 Tunnel Layer 304 Page Buffer / Sense Amplifier 306-column decoder / bitline (BL) driver 308-line decoder / word line (WL) driver 310 Voltage Generator 312 Control Logic Unit 314 registers 316 Interface 318 Data Bus 400 memory system 402 Memory subsystem 406 Memory Controller 408 Host 502 memory card 504 Memory card connector 506 Solid State Drive (SSD), Solid State Drive 508 Solid State Drive Connector

Claims

1. A method of operation for a memory system, wherein the memory system comprises a memory, the memory comprises a memory cell array and peripheral circuits coupled to the memory cell array, the memory cell array comprises memory cells capable of storing m bits of information, m being a positive integer greater than 1, and the method of operation is The peripheral circuit determines the (n+1)th group of page data according to the received prefix command and n groups of received page data, wherein n is a positive integer and n+1 is a positive integer less than or equal to m. Two memory cells are located within the aforementioned memory cell array. n To generate different data states, the steps include writing n groups of the page data and the (n+1)th group of the page data to the memory cell array. The method of operation, including the operation method.

2. If n+1 is equal to m, the prefix command includes a first subprefix command, and the first subprefix command performs an XOR operation on n groups of the page data. The peripheral circuit performs the step of determining the (n+1)th group of page data according to the received prefix command and n groups of page data, To generate the mth group of page data, the peripheral circuit performs the XOR operation on the n groups of page data according to the first subprefix command, The step of writing the n groups of page data and the (n+1)th group of page data to the memory cell array is: The operation method according to claim 1, comprising the step of writing n groups of the page data and the m-th group of the page data to the memory cell array in order to store m bits of information in the memory cell.

3. Before writing the n groups of the page data and the m-th group of the page data to the memory cell array, the operation method A step of storing n groups of the aforementioned page data in a plurality of data registers, wherein each of the data registers is used to store the group of page data. The steps include storing the m-th group of the aforementioned page data in a cache register, and The operating method according to claim 2, further comprising:

4. If the difference between m and n is 2, the prefix command includes a second subprefix command, which indicates that an NXOR operation is performed on n groups of the page data. The peripheral circuit performs the step of determining the (n+1)th group of page data according to the received prefix command and n groups of page data, To generate the (n+1)th group of the page data, the peripheral circuit performs the NXOR operation on the n groups of the page data according to the second subprefix command, The aforementioned operation method, The method of operation according to claim 1, further comprising the step of writing the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell, wherein the m-th group of page data is a sequence of all zeros or a sequence of all ones.

5. If the difference between m and n is 3, the prefix command includes a third subprefix command, the third subprefix command indicating that the (n+1)th group of the page data is equal to the nth group of the page data. The peripheral circuit performs the step of determining the (n+1)th group of page data according to the received prefix command and n groups of page data, To generate the (n+1)th group of the page data, the peripheral circuit performs a copy operation on the n groups of the page data according to the third subprefix command, The aforementioned operation method, The operation method according to claim 1, further comprising the step of writing the (n+2)th group of page data and the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell, wherein the (n+2)th group of page data and the m-th group of page data are all sequences of zeros or all sequences of ones.

6. Before determining the (n+1)th group of the aforementioned page data, the operation method, The steps include determining whether the aforementioned prefix command has been received and generating a determination result, If the determination result indicates that the prefix command has been received, the step of determining the (n+1)th group of the page data according to the received prefix command and the n groups of the page data, The operating method according to claim 1, further comprising:

7. If the determination result indicates that the prefix command has not been received, then 2 m The operation method according to claim 6, wherein m groups of page data are written to the memory cell array in order to generate m different data states.

8. A memory controller, wherein the memory controller is coupled to a memory, and the memory comprises a memory cell array and peripheral circuits coupled to the memory cell array, the memory cell array includes a memory cell capable of storing m bits of information, where m is a positive integer greater than 1, and the memory controller is The peripheral circuit is instructed to determine the (n+1)th group of page data according to the prefix command and n groups of page data, and 2 n A memory controller configured to transmit the prefix command and n groups of the page data to the peripheral circuit in order to generate n different data states, where n is a positive integer and n+1 is a positive integer less than or equal to m.

9. The prefix command includes a first subprefix command, which is used to indicate that an XOR operation is performed on n groups of the page data. The memory controller according to claim 8, wherein the memory controller is configured to transmit the first subprefix command and the n groups of page data to the peripheral circuit in order to cause the peripheral circuit to perform the XOR operation on the n groups of page data in accordance with the first subprefix command in order to generate the m-th group of page data.

10. The prefix command includes a second subprefix command, which is used to indicate that an NXOR operation is performed on n groups of the page data. The memory controller is configured to transmit the second subprefix command and the n groups of page data to the peripheral circuit in order to cause the peripheral circuit to perform the XOR operation on the n groups of page data in accordance with the second subprefix command in order to generate the (n+1)th group of page data. The memory controller according to claim 8, further configured to transmit the m-th group of page data to the peripheral circuit, wherein the m-th group of page data is a sequence of all zeros or a sequence of all ones, and the difference between m and n is 2.

11. The prefix command includes a third subprefix command, the third subprefix command is used to indicate that the (n+1)th group of the page data is equal to the nth group of the page data, The memory controller is configured to transmit the third subprefix command and the n groups of page data to the peripheral circuit in order to cause the peripheral circuit to perform a copy operation on the n groups of page data in accordance with the third subprefix command in order to generate the (n+1)th group of the page data. The memory controller according to claim 8, further configured to transmit the (n+2)th group of page data and the mth group of page data to the peripheral circuit, wherein the (n+2)th group of page data and the mth group of page data are a sequence of all zeros or a sequence of all ones, and the difference between m and n is 3.

12. The aforementioned memory controller The memory controller according to claim 8, further configured to transmit a write command to the peripheral circuit in order to cause the peripheral circuit to write at least n groups of the page data and the (n+1)th group of the page data to the memory cell array in accordance with the write command, after transmitting the prefix command.

13. A memory cell array including a memory cell capable of storing m bits of information, Peripheral circuits coupled to the memory cell array and A memory equipped with, The peripheral circuit is configured to determine the (n+1)th group of page data according to the received prefix command and n groups of received page data, where n is a positive integer and n+1 is a positive integer less than or equal to m. The aforementioned peripheral circuit has two within the memory cell array. n A memory further configured to write n groups of the page data and the (n+1)th group of the page data to the memory cell array in order to generate a number of different data states.

14. If n+1 is equal to m, the prefix command includes a first subprefix command, and the first subprefix command performs an XOR operation on n groups of the page data. Specifically, the peripheral circuit is configured to perform the XOR operation on n groups of the page data in accordance with the first subprefix command in order to generate the mth group of page data. The memory according to claim 13, wherein the peripheral circuit is further configured to write n groups of the page data and the m-th group of the page data to the memory cell array in order to store m bits of information in the memory cell.

15. The aforementioned peripheral circuit A plurality of data registers used to store n groups of the aforementioned page data, wherein each of the data registers is used to store a group of page data, A cache register used to store the mth group of the aforementioned page data and The memory according to claim 14, comprising:

16. The aforementioned peripheral circuit A spare data register used to store groups of n groups of page data when the aforementioned data register is corrupted. The memory according to claim 15, comprising:

17. If the difference between m and n is 2, the prefix command includes a second subprefix command, which indicates that an NXOR operation is performed on n groups of the page data. The peripheral circuit is configured to perform the NXOR operation on n groups of the page data in accordance with the second subprefix command in order to generate the (n+1)th group of the page data. The memory according to claim 13, wherein the peripheral circuit is further configured to write the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell, the m-th group of page data being a sequence of all zeros or a sequence of all ones.

18. If the difference between m and n is 3, the prefix command includes a third subprefix command, the third subprefix command indicating that the (n+1)th group of the page data is equal to the nth group of the page data. Specifically, the peripheral circuit is configured to perform a copy operation on n groups of the page data in accordance with the third subprefix command in order to generate the (n+1)th group of the page data. The memory according to claim 13, wherein the peripheral circuit is further configured to write the (n+2)th group of page data and the m-th group of page data to the memory cell array in order to store m bits of information in the memory cell, wherein the (n+2)th group of page data and the m-th group of page data are all sequences of zeros or all sequences of ones.

19. The aforementioned peripheral circuit Before determining the (n+1)th group of the aforementioned page data, it is determined whether the prefix command has been received and a determination result is generated. If the determination result indicates that the prefix command has been received, the (n+1)th group of the page data is determined according to the received prefix command and the n groups of the page data. The memory according to claim 13, further configured as follows.

20. If the determination result indicates that the prefix command has not been received, the peripheral circuit will, within the memory cell array, 2 m The memory according to claim 19, further configured to write m groups of page data to the memory cell array in order to generate m different data states.

21. One or more memory according to any one of claims 13 to 20, A memory controller according to any one of claims 8 to 12, which is coupled to the memory and configured to control the memory. A memory system equipped with the following features.

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