Liquid crystal display device, method for driving a liquid crystal display device

Abstract

To improve display malfunctions in liquid crystal displays. [Solution] The power-off sequence period includes a first period in which a black tone potential is supplied to the first data line while an active potential is supplied to the plurality of scan lines, and a second period in which the black tone potential is supplied to the first data line while the supply of potential to the plurality of scan lines is stopped.

Description

Technical Field

[0001] This disclosure relates to a liquid crystal display device.

Background Art

[0002] Patent Document 1 discloses a method for a power-off sequence of a liquid crystal display device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a liquid crystal display device, display defects (e.g., bright lines) may occur during power-off or power-on due to point defects (defective sub-pixels).

Means for Solving the Problems

[0005] The liquid crystal display device according to this disclosure includes a first data line, a plurality of scan lines, and a plurality of pixel circuits each including a transistor and a pixel electrode. In each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to any one of the plurality of scan lines. During a power-off sequence period, a first period is included in which a black gradation potential is supplied to the first data line while an active potential is simultaneously supplied to the plurality of scan lines for simultaneous selection, and a second period is included in which a black gradation potential is supplied to the first data line in a state where the potential supply to the plurality of scan lines is stopped.

Effects of the Invention

[0006] According to the liquid crystal display device of this disclosure, display defects are improved.

Brief Description of the Drawings

[0007] [Figure 1] This is a cross-sectional view showing an example of the configuration of a liquid crystal display device according to this embodiment. [Figure 2] This is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. [Figure 3] This is a timing chart showing the driving method of this liquid crystal display device. [Figure 4] Figure 2 is a schematic diagram showing the state of each part of the liquid crystal display device. [Figure 5] This is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. [Figure 6] Figure 5 is a schematic diagram showing the state of each part of the liquid crystal display device. [Figure 7] This is a schematic diagram illustrating a comparative example. [Figure 8] This is a schematic diagram illustrating the principle of emission line generation in the comparative example. [Figure 9] This is a timing chart showing the driving method of this liquid crystal display device. [Figure 10] Figure 2 is a schematic diagram showing the state of each part of the liquid crystal display device. [Figure 11] Figure 5 is a schematic diagram showing the state of each part of the liquid crystal display device. [Figure 12] This is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. [Figure 13] This is a timing chart showing the driving method of this liquid crystal display device. [Figure 14] This is a timing chart showing the driving method of this liquid crystal display device. [Figure 15] This is a schematic diagram showing an in-vehicle display device according to this embodiment. [Modes for carrying out the invention]

[0008] Figure 1 is a cross-sectional view showing an example configuration of a liquid crystal display device according to this embodiment. Figure 2 is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. Figure 3 is a timing chart showing the driving method of the liquid crystal display device. Figure 4 is a schematic diagram showing the driving method of the liquid crystal display device of Figure 2. Figure 5 is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. Figure 6 is a schematic diagram showing the driving method of the liquid crystal display device of Figure 5.

[0009] As shown in Figures 1 to 6, the liquid crystal display device 10 according to this embodiment includes a first data line S1, a plurality of scan lines G1 to Gn, and a plurality of pixel circuits 4, each including a transistor TR and a pixel electrode PE. In each pixel circuit 4, the pixel electrode PE is connected to the first data line S1 via the transistor TR, and the gate electrode of the transistor TR is connected to one of the plurality of scan lines G1 to Gn. The device includes a first period T1 in which a black gradation potential is supplied to the first data line S1 while an active potential is supplied to the plurality of scan lines G1 to Gn during the power-off sequence period, and a second period T2 in which the black gradation potential is supplied to the first data line S1 while the potential supply to the plurality of scan lines G1 to Gn is stopped.

[0010] In the liquid crystal display device 10, as shown in Figures 1 to 6, during the second period T2, the potential of the pixel electrode PE of a normal pixel circuit 4 is maintained (controlled) at the black gradation potential. Therefore, even if a point defect (pixel circuit 4D with a gate-drain short circuit) like the one in Figure 5 exists, display malfunctions (bright lines) are less likely to occur when the power is off or on. In each drawing, the state in which a conductor such as wiring is electrically floating (high impedance) is indicated as FL.

[0011] The power-off sequence period is a period during which predetermined processing associated with the power-off of the liquid crystal display device 10 is performed. In the liquid crystal display device 10, the power-off sequence may include a step of simultaneously selecting to supply an active potential (High) to a plurality of scan lines G1 to Gn while supplying a black gradation potential to the first data line S1, a step of supplying a black gradation potential to the first data line S1 in a state where the potential supply to the plurality of scan lines G1 to Gn is stopped, and a step of stopping the potential supply to the first data line S1.

[0012] As shown in FIGS. 1 and 2, the liquid crystal display device 10 may include a TFT substrate (active matrix substrate) 7, a counter substrate 9, a liquid crystal layer 8 positioned between the TFT substrate 7 and the counter substrate 9, and a backlight BL. The TFT substrate 7, the liquid crystal layer 8, and the counter substrate 9 may constitute a liquid crystal panel LP. In FIG. 2, the TFT substrate 7 is positioned on the backlight BL side with respect to the liquid crystal layer 8, but is not limited thereto. The counter substrate 9 may be positioned on the backlight BL side with respect to the liquid crystal layer 8.

[0013] The pixel circuit 4 may include a transistor TR and a liquid crystal capacitor LC. The liquid crystal capacitor LC may include a pixel electrode PE, a counter electrode CE, and the liquid crystal layer 8. The liquid crystal capacitor LC may constitute a sub-pixel of the liquid crystal display device 10. The liquid crystal layer 8 may be in a normally black mode. The TFT substrate 7 may include a transistor TR, a pixel electrode PE, and a counter electrode CE. The transistor TR may be an N-type transistor. The counter substrate 9 may be a color filter substrate. The counter electrode CE may also be provided on the counter substrate 9.

[0014] The liquid crystal display device 10 may include a driver GD (scan driver) that drives a plurality of scan lines G1 to Gn. In the first period T1, the driver GD may be in an operating state, and in the second period T2, the driver GD may be in a stopped state (a state where the driver GD is not controlled).

[0015] As shown in FIGS. 5 and 6, when a defective circuit 4D in which the gate electrode of the transistor TR and the pixel electrode PE are short-circuited and a normal adjacent circuit 4C adjacent to the defective circuit 4D are included in a plurality of pixel circuits 4 connected to the first data line S1, the adjacent circuit 4C may be maintained in the black display during the first period T1 and the second period T2.

[0016] The second period T2 may include a period from the stop of the potential supply to the plurality of scan lines G1 to Gn (the operation stop of the driver GD) until the transistor TR connected to each scan line is turned off. By doing so, after the transistor TR connected to each scan line (G1 to Gn) is turned off, the potential supply to the data line S1 is stopped (the data line S1 becomes electrically floating). Therefore, even if there are point defects (pixel circuits 4D with gate-drain short circuits as shown in FIG. 5), display defects (for example, bright lines of a plurality of pixel circuits 4 connected to the data line S1) during power-off or power-on are avoided. In the second period T2, the plurality of scan lines G1 to Gn may be electrically floating.

[0017] FIG. 7 is a schematic diagram showing a comparative example. FIG. 8 is a schematic diagram showing the principle of generation of bright lines in the comparative example. As shown in FIGS. 7 and 8, when the potential supply to the plurality of scan lines GL and the potential supply to the data line SL are stopped simultaneously (that is, the plurality of scan lines GL and the data line SL are made electrically floating simultaneously), if there is a pixel circuit 15 with a gate-drain short circuit, charges flow from the scan line GL (a potential close to active High) to the data line SL through the short-circuit transistor of the pixel circuit 15, and the potential of the data line SL rises. As a result, there is a possibility that a plurality of pixel circuits (14 and 15) connected to the data line SL become bright lines.

[0018] The transistor TR of the pixel circuit 4 turns off when the gate electrode falls below the threshold potential Vth, and during the second period T2, the potentials of multiple scan lines G1 to Gn may decrease from the active potential (High) to below the threshold potential Vth. The black gradation potential supplied to the first data line S1 may be the ground potential GND. The threshold potential Vth may be higher than the ground potential GND. The inactive potential (Low) of scan lines G1 to Gn may be lower than the ground potential GND.

[0019] After the first period T1, Gn may be electrically floated from multiple scan lines G1. The length of the second period T2 may be set according to the time constant of the multiple scan lines G1 to Gn. For example, if the time constant is large and it takes a long time for the potential of scan lines G1 to Gn to decrease from active (high) to threshold potential (the potential at which transistor TR turns off), the second period T2 should be made longer. The second period T2 may be the period from when scan lines G1 to Gn are electrically floated until the first data line S1 is electrically floated (the switch circuit SC is decontrolled).

[0020] The liquid crystal display device 10 includes a second data line S3 and a third data line S3, a switch circuit SC, and an output line DW. A data signal of the first color is supplied to the first data line S1, a data signal of the second color is supplied to the second data line S2, and a data signal of the third color is supplied to the third data line S3. The first to third data lines S1 to S3 may be connected to a common output line DW via the switch circuit SC. The first color may be one of three colors: red, green, and blue. The second color may be one of the remaining two colors, and the third color may be the remaining single color.

[0021] The liquid crystal display device 10 may include a driver SD (data driver) that drives the output line DW, and the driver SD may be in an operating state during the first period T1 and the second period T2, and in the third period T3 following the second period T2, the driver SD may be in a stopped state (a state in which the driver SD is not controlled). During the third period T3, the first data line S1, etc., may be electrically floating.

[0022] During normal display periods, the switch circuit SC may selectively connect one of the first to third data lines S1 to S3 to the output line DW. For example, one horizontal scanning period (1H) may be divided into three parts, and the first data line S1 may be selected for the first of the three divided periods, the second data line S2 for the second, and the third data line S3 for the third (time-division drive). This reduces the number of data output terminals and enables higher resolution.

[0023] During the first period T1 and second period T2 of the power-off sequence, a black tone potential is supplied to the output line DW, and the switch circuit SC may connect all of the first to third data lines S1 to S3 to the output line DW. As a result, during the first period T1 and second period T2, a black tone potential is supplied to all of the first to third data lines S1 to S3. That is, all of the first to third data lines S1 to S3 can be controlled to the black tone potential, and during the first period T1, the black tone potential is written to the pixel electrode PE of each pixel circuit 4.

[0024] After the second period T2, the switch circuit SC stops (the switch circuit SC becomes uncontrolled), and the first to third data lines S1 to S3 may become electrically floating.

[0025] The switch circuit SC may include multiple transistors T1, T2, and T3 which are identical in type to the transistor TR of each pixel circuit 4. The first data line S1 may be connected to the output line DW via transistor T1, the second data line S2 may be connected to the output line DW via transistor T2, and the third data line S3 may be connected to the output line DW via transistor T3.

[0026] Figure 9 is a timing chart showing the driving method of this liquid crystal display device. Figure 10 is a schematic diagram showing the driving method of the liquid crystal display device of Figure 2. Figure 11 is a schematic diagram showing the driving method of the liquid crystal display device of Figure 5. As shown in Figures 9 to 11, the liquid crystal display device 10 includes a first period T1 during the power-off sequence period in which a black gradation potential is supplied to the first data line S1 while sequential selection of multiple scan lines G1 to Gn is performed.

[0027] In this way, during the first period T1, the transistor TR is turned off while the black gradation potential is written to the pixel electrode PE in the normal pixel circuit 4. Therefore, as shown in Figure 11, even if a point defect (pixel circuit 4D with a gate-drain short circuit) exists, display malfunctions (bright lines) are less likely to occur when the power is turned off or on. This is because, during the selection period of scan line G3 connected to pixel circuit 4D (the period when the first data line S1 and scan line G3 are short-circuited), the preceding scan line G2 is inactive (low potential), and even when the first data line S1 and scan lines G1 to Gn are electrically floated after the first period T1 (sequential selection of scan lines G1 to Gn), scan lines G1 to Gn are also inactive (low potential).

[0028] The power-off sequence period is a period during which predetermined processing is performed in conjunction with the power-off of the liquid crystal display device 10. In the liquid crystal display device 10, the power-off sequence includes a step of sequentially selecting multiple scan lines G1 to Gn while supplying a black gradation potential to the first data line S1. Sequential selection may be performed by supplying sequential pulses (including a rise from an inactive low potential to an active high potential and a fall from a high potential to a low potential) to the multiple scan lines.

[0029] In the power-off sequence period shown in Figures 9 to 11, during the first period T1, an inactive potential (Low) may be supplied to multiple scan lines G1 to Gn at the end of sequential selection. Following the first period T1, there may be a second period T2 in which the potential supply to the multiple scan lines G1 to Gn is stopped. During the second period T2, the first data line S1 and the multiple scan lines G1 to Gn may be electrically floating. As shown in Figure 11, during the second period T2, the normal adjacent circuit 4C adjacent to the defective circuit 4D is kept black.

[0030] In the normal display period shown in Figure 9, the switch circuit SC may selectively connect one of the first to third data lines S1 to S3 to the output line DW. For example, one horizontal scanning period (1H) may be divided into three parts to obtain three divided periods, with the first data line S1 selected for the first division, the second data line S2 for the second division, and the third data line S3 for the third division (time-division drive).

[0031] In the first period T1 of the power-off sequence shown in Figure 9, a black tone potential is supplied to the output line DW, and the switch circuit SC may connect all of the first to third data lines S1 to S3 to the output line DW. As a result, during the first period T1, a black tone potential is supplied to all of the first to third data lines S1 to S3. That is, all of the first to third data lines S1 to S3 can be controlled to the black tone potential, and during the first period T1, the black tone potential is written to the pixel electrode PE of each pixel circuit 4.

[0032] In Figures 1 and 2, transistors TR and pixel electrodes PE, as well as output lines DW and switch circuits SC (including transistors T1 to T3) may be monolithically formed on the TFT substrate 7. A driver GD (scan driver) for driving multiple scan lines G1 to Gn may also be monolithically formed on the TFT substrate 7.

[0033] Figure 12 is a schematic diagram showing an example configuration of a liquid crystal display device according to this embodiment. Figures 13 and 14 are timing charts showing the driving method of this liquid crystal display device. The liquid crystal display device 10 in Figure 2, etc., is equipped with an output line DW and a switch circuit SC to perform time-division driving, but is not limited to this. As shown in Figure 12, the first data line S1, etc., may be connected to a data driver SD. The liquid crystal display device in Figure 12 can be driven as shown in Figure 13 or Figure 14.

[0034] Figure 15 is a schematic diagram showing an in-vehicle display device according to this embodiment. The in-vehicle display device 20 may include the liquid crystal display device 10 described in Figures 1 to 14.

[0035] The embodiments described above are for illustrative and explanatory purposes only, and not for limitation. It will be apparent to those skilled in the art that many variations are possible based on these examples and descriptions.

[0036] 〔summary〕 It comprises a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode. In each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines. A liquid crystal display device comprising: a first period during which a black gradation potential is supplied to the first data line while an active potential is supplied to the plurality of scan lines simultaneously during a power-off sequence period; and a second period during which the black gradation potential is supplied to the first data line while the supply of potential to the plurality of scan lines is stopped.

[0037] The liquid crystal display device described above, wherein the second period includes the period from the cessation of potential supply to the plurality of scan lines until the transistors connected to each scan line are turned off.

[0038] The liquid crystal display device described above, wherein, during the second period, the plurality of scan lines are electrically floating.

[0039] The liquid crystal display device described above, wherein, when the plurality of pixel circuits include a defective circuit in which the gate electrode of a transistor and the pixel electrode are short-circuited, and a normal adjacent circuit adjacent to the defective circuit, the adjacent circuit is maintained in a black display state during the first period and the second period.

[0040] It comprises a second data line and a third data line, a switch circuit, and an output line. A data signal of the first color is supplied to the first data line. A second color data signal is supplied to the second data line. A third color data signal is supplied to the third data line. The liquid crystal display device described above, wherein the first to third data lines are connected to a common output line via the switch circuit.

[0041] During the normal display period, the switch circuit selectively connects one of the first to third data lines to the output line, as described above for the liquid crystal display device.

[0042] The liquid crystal display device described above, wherein, during the first and second periods, the black gradation potential is supplied to the output line, and the switch circuit connects all of the first to third data lines to the output line.

[0043] The liquid crystal display device described above, wherein the switch circuit stops after the second period and the first to third data lines become electrically floating.

[0044] The liquid crystal display device described above, wherein the switch circuit includes a plurality of transistors that are identical in type to the transistors in each pixel circuit.

[0045] The liquid crystal display device described above, wherein, after the first period, the plurality of scan lines are electrically floating.

[0046] The liquid crystal display device described above, wherein the length of the second period is set according to the time constant of the plurality of scan lines.

[0047] The aforementioned black gradation potential is the ground potential, as described above for the liquid crystal display device.

[0048] It has a normally black liquid crystal layer, The above-mentioned liquid crystal display device, wherein the transistor is of type N.

[0049] The aforementioned transistor turns off when the gate electrode falls below a threshold potential. The liquid crystal display device described above, wherein during the second period, the potential of the plurality of scan lines decreases from the active potential to below the threshold potential.

[0050] The aforementioned liquid crystal display device, wherein the threshold potential is higher than the ground potential.

[0051] It comprises a first data line, multiple scan lines, and multiple pixel circuits, each including a transistor and a pixel electrode. In each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines. The liquid crystal display device described above, wherein the power-off sequence period includes a first period in which a black gradation potential is supplied to the first data line while the plurality of scan lines are sequentially selected.

[0052] In the first period, the liquid crystal display device is configured such that an inactive potential is supplied to the plurality of scan lines at the end of the sequential selection.

[0053] The liquid crystal display device described above, wherein the power-off sequence period includes a second period following the first period in which the supply of potential to the plurality of scan lines is stopped.

[0054] In the second period, the liquid crystal display device described above, wherein the first data line and the plurality of scan lines are electrically floating.

[0055] The liquid crystal display device described above, wherein, when the plurality of pixel circuits include a defective circuit in which the gate electrode of a transistor and the pixel electrode are short-circuited, and a normal adjacent circuit adjacent to the defective circuit, the adjacent circuit is maintained in a black display state during the second period.

[0056] It comprises a second data line and a third data line, a switch circuit, and an output line. A data signal of the first color is supplied to the first data line. A second color data signal is supplied to the second data line. A third color data signal is supplied to the third data line. The liquid crystal display device described above, wherein the first to third data lines are connected to a common output line via the switch circuit.

[0057] The liquid crystal display device described above, wherein, during the first period, the black gradation potential is supplied to the output line, and the switch circuit connects all of the first to third data lines to the output line.

[0058] The liquid crystal display device described above, comprising a TFT substrate in which the pixel electrodes, transistors, output lines, and switch circuits are formed monolithically.

[0059] The liquid crystal display device described above, wherein the driver for driving the plurality of scan lines is monolithically formed on the TFT substrate.

[0060] An in-vehicle display device equipped with the aforementioned liquid crystal display device.

[0061] A method for driving a liquid crystal display device comprising a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode, wherein in each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines, A method for driving a liquid crystal display device, wherein the power-off sequence includes the steps of simultaneously selecting to supply a black gradation potential to the first data line and supply an active potential to the plurality of scan lines, and the steps of supplying a black gradation potential to the first data line while stopping the supply of potential to the plurality of scan lines.

[0062] A method for driving a liquid crystal display device comprising a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode, wherein in each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines, A method for driving a liquid crystal display device, wherein the power-off sequence includes a step of sequentially selecting the plurality of scan lines while supplying a black gradation potential to the first data line. [Explanation of Symbols]

[0063] 4-pixel circuit 7 TFT substrates 8 liquid crystal layers 9 Opposite substrate 10 LCD display device 20 Automotive display device T1 Period 1 T2 Second Period G1~Gn scan lines TR (Turnip in pixel circuit) SC switch circuit T1-T3 (transistors in the switch circuit) GD Scan Driver SD Data Driver S1 First data line S2 Second data line S3 Third data line

Claims

1. It comprises a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode. In each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines. A liquid crystal display device comprising: a first period during which a black gradation potential is supplied to the first data line while an active potential is supplied to the plurality of scan lines simultaneously during a power-off sequence period; and a second period during which the black gradation potential is supplied to the first data line while the potential supply to the plurality of scan lines is stopped.

2. The liquid crystal display device according to claim 1, wherein the second period includes the period from the cessation of potential supply to the plurality of scan lines until the transistors connected to each scan line are turned off.

3. The liquid crystal display device according to claim 1, wherein, in the second period, the plurality of scan lines are electrically floating.

4. The liquid crystal display device according to claim 1, wherein, when the plurality of pixel circuits include a defective circuit in which the gate electrode of a transistor and the pixel electrode are short-circuited, and a normal adjacent circuit adjacent to the defective circuit, the adjacent circuit is maintained in black display during the first period and the second period.

5. It comprises a second data line and a third data line, a switch circuit, and an output line. A data signal of the first color is supplied to the first data line. A second color data signal is supplied to the second data line. A third color data signal is supplied to the third data line. The liquid crystal display device according to claim 1, wherein the first to third data lines are connected to a common output line via the switch circuit.

6. During the normal display period, the switch circuit selectively connects one of the first to third data lines to the output line, as described in claim 5.

7. The liquid crystal display device according to claim 5, wherein, during the first and second periods, the black gradation potential is supplied to the output line, and the switch circuit connects all of the first to third data lines to the output line.

8. The liquid crystal display device according to claim 5, wherein the switch circuit stops after the second period and the first to third data lines become electrically floating.

9. The liquid crystal display device according to claim 5, wherein the switch circuit includes a plurality of transistors that are identical in type to the transistors of each pixel circuit.

10. A liquid crystal display device according to any one of claims 1 to 9, wherein, after the first period, the plurality of scan lines are electrically floated.

11. The liquid crystal display device according to any one of claims 1 to 9, wherein the length of the second period is set according to the time constant of the plurality of scan lines.

12. The liquid crystal display device according to any one of claims 1 to 9, wherein the black gradation potential is the ground potential.

13. It has a normally black liquid crystal layer, The liquid crystal display device according to any one of claims 1 to 9, wherein the transistor is of type N.

14. The aforementioned transistor turns off when the gate electrode falls below a threshold potential. The liquid crystal display device according to claim 13, wherein during the second period, the potential of the plurality of scan lines decreases from the active potential to below the threshold potential.

15. The liquid crystal display device according to claim 14, wherein the threshold potential is higher than the ground potential.

16. It comprises a first data line, multiple scan lines, and multiple pixel circuits, each including a transistor and a pixel electrode. In each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines. A liquid crystal display device, wherein the power-off sequence period includes a first period in which a black gradation potential is supplied to the first data line while the plurality of scan lines are sequentially selected.

17. The liquid crystal display device according to claim 16, wherein in the first period, an inactive potential is supplied to the plurality of scan lines at the end of the sequential selection.

18. The liquid crystal display device according to claim 16, wherein the power off sequence period includes a second period following the first period in which the supply of potential to the plurality of scan lines is stopped.

19. The liquid crystal display device according to claim 18, wherein in the second period, the first data line and the plurality of scan lines are electrically floating.

20. The liquid crystal display device according to claim 18, wherein, when the plurality of pixel circuits include a defective circuit in which the gate electrode of a transistor and the pixel electrode are short-circuited, and a normal adjacent circuit adjacent to the defective circuit, the adjacent circuit is maintained in black during the second period.

21. It comprises a second data line and a third data line, a switch circuit, and an output line. A data signal of the first color is supplied to the first data line. A second color data signal is supplied to the second data line. A third color data signal is supplied to the third data line. The liquid crystal display device according to claim 16, wherein the first to third data lines are connected to a common output line via the switch circuit.

22. The liquid crystal display device according to claim 21, wherein during the first period, the black gradation potential is supplied to the output line, and the switch circuit connects all of the first to third data lines to the output line.

23. The liquid crystal display device according to claim 5 or 21, comprising a TFT substrate on which the pixel electrodes, transistors, output lines, and switch circuits are formed monolithically.

24. The liquid crystal display device according to claim 23, wherein the driver for driving the plurality of scan lines is monolithically formed on the TFT substrate.

25. An in-vehicle display device comprising the liquid crystal display device described in claim 1 or 16.

26. A method for driving a liquid crystal display device comprising a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode, wherein in each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines, A method for driving a liquid crystal display device, wherein the power-off sequence includes the steps of simultaneously selecting to supply a black gradation potential to the first data line and supply an active potential to the plurality of scan lines, and the steps of supplying a black gradation potential to the first data line while stopping the supply of potential to the plurality of scan lines.

27. A method for driving a liquid crystal display device comprising a first data line, a plurality of scan lines, and a plurality of pixel circuits, each including a transistor and a pixel electrode, wherein in each pixel circuit, the pixel electrode is connected to the first data line via the transistor, and the gate electrode of the transistor is connected to one of the plurality of scan lines, A method for driving a liquid crystal display device, wherein the power-off sequence includes a step of sequentially selecting the plurality of scan lines while supplying a black gradation potential to the first data line.

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