Drive circuit and display device

Abstract

The present invention provides a drive circuit and a display device capable of suppressing the degradation of transistors that discharge the nodes of a unit circuit. [Solution] The unit circuit 1a of the gate drive circuit comprises transistors T1 to T4. Transistor T1 outputs a drive signal to the gate line. Transistor T2 is a transistor to which a set signal is input and is a transistor that charges node N. Transistor T3 is a transistor to which a first reset signal is input and is a transistor that discharges node N to the potential of ground GND. Transistor T2 is a transistor to which a second reset signal supplied after the first reset signal is input and is a transistor that discharges node N to the gate off voltage VGL.

Description

Technical Field

[0001] The present disclosure relates to a driving circuit and a display device.

Background Art

[0002] The unit circuit of the driving circuit described in Patent Document 1 includes a first transistor to a third transistor. The first transistor outputs an output signal in response to the input of a clock signal. The second transistor charges a node connected to the gate electrode of the first transistor to a gate-on voltage in response to the input of a previous-stage signal which is an output signal from the previous stage. The third transistor has a gate-off voltage applied to its source electrode and a node connected to its drain electrode. When the clock signal is supplied to the first transistor in a state where the node is charged, the node becomes a potential higher than the gate-on voltage. Further, in response to the input of a subsequent-stage signal which is an output signal from the subsequent stage and a reset signal to the gate electrode of the third transistor, the potential of the node connected to the gate electrode of the first transistor is set to a low potential (gate-off voltage) (reset).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the unit circuit of the drive circuit described in Patent Document 1 above, when a reset signal is input to the gate electrode of the third transistor, which is a transistor that discharges a node in response to the input of a reset signal (when the gate-source voltage becomes greater than or equal to the threshold voltage), the potential of the drain electrode is greater than or equal to the gate-on voltage. Therefore, when a reset signal is input to the gate electrode of the third transistor, a large potential difference (drain-source voltage) is created between the potential of the drain electrode (potential greater than or equal to the gate-on voltage) and the potential of the source electrode (gate-off voltage), generating hot carriers with very high energy. The generation of hot carriers causes the transistor to degrade.

[0005] Therefore, this disclosure has been made to solve the above-mentioned problems, and aims to provide a drive circuit and a display device that can suppress the degradation of transistors that discharge the nodes of a unit circuit. [Means for solving the problem]

[0006] To solve the above problems, the drive circuit according to the first embodiment is a drive circuit that comprises a plurality of unit circuits that output a drive signal to any one of the scan signal lines in the scan signal line group. The unit circuit includes a node, a first transistor that outputs the drive signal to the scan signal line, the node being connected to the gate electrode of the first transistor, a clock signal being applied to the source electrode of the first transistor, and the drain electrode of the first transistor being connected to the scan signal line, a second transistor to which a set signal is input to the unit circuit, the set signal being input to the gate electrode of the second transistor, and the drain electrode of the second transistor being connected to the node, a third transistor to which a first reset signal is input to the unit circuit, the first reset signal being input to the gate electrode of the third transistor, the drain electrode of the third transistor being connected to the node, and a voltage less than the gate-on voltage and higher than the gate-off voltage being applied to the source electrode of the third transistor, and a fourth transistor to which a second reset signal that becomes high at a time later than the first reset signal is input, the second reset signal being input to the gate electrode of the fourth transistor, the drain electrode of the fourth transistor being connected to the node, and the gate-off voltage being applied to the source electrode of the fourth transistor.

[0007] The display device according to the second embodiment comprises a drive circuit according to the first embodiment and a substrate on which the scanning signal line group is arranged. [Effects of the Invention]

[0008] According to the above configuration, the degradation of the transistors (third and fourth transistors) that discharge the nodes of the unit circuit can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing the configuration of a display device 100 in one embodiment. [Figure 2] Figure 2 is a timing diagram illustrating the phases of the clock signals GCK1 to GCK8. [Figure 3] Figure 3 is a block diagram showing the configuration within the display panel 10. [Figure 4] Figure 4 shows the configuration of the gate drive circuit 1. [Figure 5] Figure 5 is a circuit diagram showing the configuration of the unit circuit 1a. [Figure 6] Figure 6 is a timing diagram illustrating the relationship between each terminal and potential of the unit circuit 1a according to one embodiment. [Figure 7] Figure 7 is a diagram illustrating the configuration of unit circuit 200 according to a comparative example. [Figure 8] Figure 8 is a timing diagram illustrating the relationship between each terminal and potential of the unit circuit 200 in a comparative example. [Figure 9] Figure 9 is a diagram illustrating the waveform of the voltage applied to transistor T3a in unit circuit 200 in a comparative example. [Figure 10] Figure 10 is a diagram illustrating the waveform of the voltage applied to transistor T3 in the unit circuit 1a according to the embodiment. [Figure 11] Figure 11 is a diagram illustrating the waveform of the voltage applied to transistor T4 in the unit circuit 1a according to the embodiment. [Modes for carrying out the invention]

[0010] Hereinafter, one embodiment of the present disclosure will be described with reference to the drawings. However, the present disclosure is not limited to the following embodiment, and design modifications can be made as appropriate within the scope of satisfying the configuration of the present disclosure. Furthermore, in the following description, the same reference numerals will be used in common across different drawings for identical parts or parts having similar functions, and repeated descriptions will be omitted. Also, the configurations described in the embodiments and modifications may be combined or modified as appropriate without departing from the gist of the present disclosure. Furthermore, for the sake of clarity, the drawings referenced below may show simplified or schematic representations of the configurations, or some components may be omitted.

[0011] [Overall configuration of the display device] Figure 1 is a block diagram showing the configuration of the display device 100 in this embodiment. Figure 2 is a timing diagram illustrating the phases of the clock signals GCK1 to GCK8. Figure 3 is a block diagram showing the configuration within the display panel 10.

[0012] As shown in Figure 1, the display device 100 includes a display panel 10 and a control board 20. The display panel 10 and the control board 20 are connected via a flexible printed circuit board or the like. The display panel 10 includes a gate drive circuit 1, a display section 2 which is an area where an image is displayed, and a source drive circuit 3. The control board 20 is provided with a timing controller 4, a power supply circuit 5, and a level shifter circuit 6. The display device 100 can be configured, for example, as a liquid crystal display device.

[0013] As shown in Figure 1, the timing controller 4 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates a digital video signal DV, a source start pulse signal SSP, a source clock signal SCK, a gate start pulse signal GSPa, and a gate clock signal GCKa based on the received signals. The timing controller 4 transmits the digital video signal DV, the source start pulse signal SSP, and the source clock signal SCK to the source drive circuit 3. The timing controller 4 also transmits the gate start pulse signal GSPa and the gate clock signal GCKa to the level shifter circuit 6.

[0014] The power supply circuit 5 generates a gate-on voltage VGH and a gate-off voltage VGL based on power input from an external power supply or a battery (not shown). The gate-on voltage VGH and the gate-off voltage VGL are DC voltages with a constant level (voltage value). The gate-on voltage VGH is a voltage higher than the ground potential GND, and a voltage at the same potential as the gate-on voltage VGH is hereinafter referred to as the "High level" (represented as "H" in the figure). The gate-off voltage VGL is a voltage lower than the ground potential GND, and a voltage at the same potential as the gate-off voltage VGL is hereinafter referred to as the "Low level" (represented as "L" in the figure).

[0015] The level shifter circuit 6 generates a gate start pulse signal GSP and clock signals GCK1 to GCK8 based on the gate on voltage VGH and the gate off voltage VGL. As shown in FIG. 2, the clock signals GCK1 to GCK8 are signals that repeat between a High level and a Low level, and are signals for controlling the operation of the gate drive circuit 1. The clock signal GCK2 is delayed by 45 degrees in phase with respect to the clock signal GCK1. The clock signal GCK3 is delayed by 90 degrees in phase with respect to the clock signal GCK1. The clock signal GCK4 is delayed by 135 degrees in phase with respect to the clock signal GCK1. The clock signal GCK5 is delayed by 180 degrees in phase with respect to the clock signal GCK1. The clock signal GCK6 is delayed by 225 degrees in phase with respect to the clock signal GCK1. The clock signal GCK7 is delayed by 270 degrees in phase with respect to the clock signal GCK1. The clock signal GCK8 is delayed by 315 degrees in phase with respect to the clock signal GCK1. The gate start pulse signal GSP is a signal that is input as a set signal to the first-stage unit circuit 1a and the second-stage unit circuit 1a of the gate drive circuit 1, and is a signal for starting the drive of the gate drive circuit 1.

[0016] As shown in FIG. 3, the gate drive circuit 1 is disposed on both or one of the two sides of the display unit 2. In FIGS. 1 and 3, an example in which one gate drive circuit 1 is disposed on each of the two sides of the display unit 2 is illustrated. Since the two gate drive circuits 1 have the same configuration, only the configuration of one of the two gate drive circuits 1 will be described, and the description of the other configuration will be omitted. The gate drive circuit 1 is a gate driver on array (GOA) formed on the active matrix substrate of the display panel 10.

[0017] The display panel 10 is provided with a plurality of gate lines 11 constituting a scanning signal line group connected to the gate driving circuit 1 and a plurality of source lines 12 constituting a source signal line group connected to the source driving circuit 3. The plurality of gate lines 11 and the plurality of source lines 12 are arranged to intersect each other, and pixels are arranged in each region partitioned by the plurality of gate lines 11 and the plurality of source lines 12. The plurality of pixels are arranged in a matrix in the display panel 10.

[0018] Also, as shown in FIG. 3, the pixel is provided with a pixel transistor 13 and a pixel electrode 14. The gate electrode of the pixel transistor 13 is connected to the gate line 11. The source electrode of the pixel transistor 13 is connected to the source line 12. The drain electrode of the pixel transistor 13 is connected to the pixel electrode 14.

[0019] When the pixel transistor 13 is turned on by a driving signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written (charged) into the pixel electrode 14. Thereby, an electric field is formed between the pixel electrode 14 and the common electrode 15 arranged to face the pixel electrode 14. Further, the display unit 2 includes an active matrix substrate, a counter substrate arranged to face the active matrix substrate, and a liquid crystal layer arranged between the active matrix substrate and the counter substrate. The liquid crystal layer is driven by the electric field generated between the pixel electrode 14 and the common electrode 15 to display an image on the display panel 10.

[0020] (Configuration of the gate driving circuit 1) FIG. 4 is a diagram showing the configuration of the gate driving circuit 1. FIG. 5 is a circuit diagram showing the configuration of the unit circuit 1a.

[0021] As shown in Figure 4, the gate drive circuit 1 consists of multiple stages and includes a shift register circuit that sequentially supplies drive signals to gate lines 11 (such as G(n) in the example in Figure 4) in response to the input of clock signals GCK1 to GCK8. The gate drive circuit 1 comprises multiple unit circuits 1a that constitute one of the multiple stages and output drive signals to the connected gate lines 11. The number of unit circuits 1a is the same as the number of gate lines 11. Figure 4 illustrates some of the multiple unit circuits 1a (eight of them).

[0022] The unit circuit 1a receives one of the clock signals GCK1 to GCK8 supplied from the level shifter circuit 6. For example, the unit circuit 1a of the nth stage (where n is a natural number) receives the clock signal GCK1. In addition, the drive signal output from the terminal OUT of the unit circuit 1a of the preceding stage (two stages prior in the example in Figure 4) is input to terminal S as a set signal. Although not shown in the diagram, the gate start pulse signal GSP is input as a set signal to the unit circuit 1a of the first stage and the unit circuit 1a of the second stage.

[0023] In this embodiment, the drive signal output from terminal OUT of the unit circuit 1a of the next stage (three stages later in the example of Figure 4) is input to terminal R1 as the first reset signal for unit circuit 1a. Furthermore, the drive signal output from terminal OUT of the unit circuit 1a of the stage even later than the one mentioned above (five stages later in the example of Figure 4) is input to terminal R2 as the second reset signal for unit circuit 1a. When the gate start pulse signal GSP is input to the unit circuit 1a of the first stage and the unit circuit 1a of the second stage, the drive signal is output to the gate line 11 sequentially from the first stage unit circuit 1a to the final stage unit circuit 1a.

[0024] As shown in Figure 5, the unit circuit 1a includes transistors T1 to T4, capacitor Cbst, and node N. Node N connects transistors T1 to T4 and capacitor Cbst.

[0025] Transistor T1 is a transistor that outputs a drive signal to the gate line 11 connected to the unit circuit 1a. Transistor T1 outputs a drive signal to the gate line 11 according to one of the clock signals GCK1 to GCK8 input to terminal CLK. Bootstrap capacitor Cbst is a capacitor that turns on transistor T1 by the potential increase caused by charging.

[0026] The gate electrode of transistor T1 is connected to node N. The source electrode of transistor T1 is connected to terminal CLK. The drain electrode of transistor T1 is connected to terminal OUT, where the drive signal is output. One end of bootstrap capacitor Cbst is connected to the gate electrode of transistor T1, and the other end of bootstrap capacitor Cbst is connected to the drain electrode of transistor T1.

[0027] Transistor T2 is a transistor that increases (charges) the potential of node N in response to a set signal input. The gate electrode and source electrode of transistor T2 are connected to terminal S to which the set signal is input. The drain electrode of transistor T2 is connected to node N.

[0028] Transistor T3 is a transistor that lowers (discharges) the potential of node N in response to the input of a first reset signal. The gate electrode of transistor T3 is connected to terminal R1, to which the first reset signal is input. In this embodiment, the source electrode of transistor T3 is connected to a terminal having the potential of ground GND. As a result, the potential of the source electrode of transistor T3 is less than the gate-on voltage VGH and higher than the gate-off voltage VGL. The drive signal output from terminal OUT of the (n+3)th stage unit circuit 1a is input to transistor T3 of the nth stage unit circuit 1a as the first reset signal.

[0029] Transistor T4 is a transistor that lowers (discharges) the potential of node N in response to the input of a second reset signal. The gate electrode of transistor T4 is connected to terminal R2, to which the second reset signal is input. In this embodiment, the source electrode of transistor T4 is connected to the terminal to which the gate off voltage VGL is applied. As a result, the potential of the source electrode of transistor T4 becomes the same as the gate off voltage VGL. The drive signal output from terminal OUT of the n+5th stage unit circuit 1a is input to transistor T4 of the nth stage unit circuit 1a as the second reset signal.

[0030] The semiconductor layers of transistors T1 to T4 contain an oxide semiconductor. The oxide semiconductor is an In-Ga-Zn-O system oxide semiconductor, and a crystalline In-Ga-Zn-O system oxide semiconductor can be used. This makes it possible to reduce power consumption, increase the driving speed, and increase the resolution compared to when each transistor is made of amorphous silicon.

[0031] (Operation of unit circuit 1a) Figure 6 is a timing diagram illustrating the relationship between each terminal and potential of the unit circuit 1a according to this embodiment. Figure 6 shows an example of the relationship between each terminal and potential of the unit circuit 1a of the nth stage. Here, a state in which the voltage is higher than the High level is indicated as "HH".

[0032] As shown in Figure 6, the clock signal GCK1 is input to terminal CLK of unit circuit 1a. At time t1, when the set signal is input to terminal S (the voltage becomes "H"), node N is charged from "L" to "H". Then, at time t2, when the potential of terminal CLK becomes "H", the capacitance of capacitor Cbst placed between node N and the drain electrode of transistor T1 causes the potential of node N to rise from "H" to "HH". As a result, the potential of terminal OUT becomes "H", the drive signal (gate signal) is output, and the set signal is output to the unit circuit 1a of the second stage (n+2th stage), the first reset signal is output to the unit circuit 1a of the third stage (n-3rd stage), and the second reset signal is output to the unit circuit 1a of the fifth stage (n-5th stage).

[0033] At time t3, the potential of terminal CLK changes from "H" to "L", and the potential of node N decreases from "HH" to "H".

[0034] At time t4, the first reset signal is input to terminal R1, and the potential of terminal R1 changes from "L" to "H". Here, the potential of the source electrode of transistor T3 is the ground potential GND. Therefore, when the first reset signal is supplied to the gate electrode of transistor T3 and the potential of the gate electrode becomes "H" (time t4), the potential difference between the potential of the drain electrode (gate-on voltage VGH) and the potential of the source electrode (ground potential GND) can be made smaller than the difference between the gate-on voltage VGH and the gate-off voltage VGL. At time t4, as transistor T3 turns on, the potential of node N drops from the gate-on voltage VGH to the ground potential GND.

[0035] At time t5, a second reset signal is input to terminal R2, and the potential of terminal R2 changes from "L" to "H". Here, the potential of the drain electrode of transistor T4 is the ground potential GND. Therefore, when the second reset signal is supplied to the gate electrode of transistor T4 and the potential of the gate electrode becomes "H" (time t5), the potential difference between the drain electrode potential (ground potential GND) and the source electrode potential (gate off voltage VGL) can be made smaller than the difference between the gate on voltage VGH and the gate off voltage VGL. At time t5, as transistor T4 turns on, the potential of node N drops from the ground potential GND to the gate off voltage VGL.

[0036] This configuration allows for a reduction in the drain-source voltage applied to transistors T3 and T4, thereby reducing the rate of degradation of transistors T3 and T4.

[0037] [Comparison results with the comparison example] Next, with reference to Figures 7 to 11, we will describe the results of a comparison between an embodiment of one design (hereinafter referred to as "the embodiment") and a comparative example. Note that in the comparative example, components identical to those in the embodiment will be given the same reference numerals and their descriptions will be omitted. Furthermore, the comparative example is provided as an illustration to explain the effects of the embodiment and does not represent prior art.

[0038] Figure 7 is a diagram illustrating the configuration of unit circuit 200 according to the comparative example. Unit circuit 200 according to the comparative example includes transistor T3c and node Nc. The source electrode of transistor T3c is connected to a terminal to which the gate off voltage VGL is applied. The gate electrode of transistor T3c is connected to terminal R. Node Nc is connected only to the bootstrap capacitor Cbst, transistors T1, T2, and T3c.

[0039] Figure 8 is a timing diagram illustrating the relationship between each terminal and potential of the unit circuit 200 in the comparative example. Figure 8 also shows the unit circuit in the comparative example for the nth stage. As shown in Figure 8, the drive signal from terminal OUT of the (n+3)th stage unit circuit 200 is input to terminal R as a reset signal. At time t11, when the potential of terminal R changes from "L" to "H", the potential of node Nc decreases from "H" to "L".

[0040] Figure 9 illustrates the waveform of the voltage applied to transistor T3a in unit circuit 200 according to a comparative example. Figure 9 shows the potential difference Vgs between the gate electrode and source electrode of transistor T3c, the potential difference Vgs between the drain electrode and source electrode of transistor T3c, and the threshold voltage Vth of transistor T3c. The potential differences Vds and Vgs are results obtained through measurement, simulation, and calculation. As shown in Figure 9, at time t11, the potential difference Vgs changes from below the threshold voltage Vth to above it (crosses it). At this time, the potential difference Vds is higher than the threshold voltage Vth. In this case, hot carriers are generated, and the likelihood of transistor T3c degradation increases.

[0041] Figure 10 is a diagram illustrating the waveform of the voltage applied to transistor T3 in the unit circuit 1a according to the embodiment. Figure 11 is a diagram illustrating the waveform of the voltage applied to transistor T4 in the unit circuit 1a according to the embodiment. Note that the voltage per vertical cell in Figures 10 and 11 is the same as the voltage per vertical cell in Figure 9.

[0042] Figure 10 shows the potential difference Vgs between the gate electrode and source electrode of transistor T3, the potential difference Vds between the drain electrode and source electrode of transistor T3, and the threshold voltage Vth of transistor T3. Figure 11 shows the potential difference Vgs between the gate electrode and source electrode of transistor T4, the potential difference Vds between the drain electrode and source electrode of transistor T4, and the threshold voltage Vth of transistor T4. The potential differences Vds and Vgs of transistor T3 and transistor T4 are results obtained by measurement, respectively.

[0043] As shown in Figure 10, at time t4, the potential difference Vgs crosses from below the threshold voltage Vth to above it. At this time, the difference between the potential difference Vds and the threshold voltage Vth (Vds-Vth) is less than one-quarter of the difference (Vds-Vth) in the comparative example shown in Figure 9. Also, as shown in Figure 11, at time t5, the potential difference Vgs crosses from below the threshold voltage Vth to above it. At this time, the difference between the potential difference Vds and the threshold voltage Vth (Vds-Vth) is less than one-quarter of the difference (Vds-Vth) in the comparative example shown in Figure 9. Thus, in the embodiment, when transistors T3 and T4 are in the ON state, the difference (Vds-Vth) is small, so the generation of hot carriers is suppressed. As a result, degradation of transistors T3 and T4 can be prevented.

[0044] [Differentiation] Although embodiments of the invention have been described above, these embodiments are merely examples for carrying out the invention. Therefore, it is possible to carry out the invention by appropriately modifying the embodiments described above without departing from the spirit of the invention, without being limited to the embodiments described above. Modifications of the embodiments described above will be described below.

[0045] (1) In the above embodiment, an example is shown in which the display device is configured as a liquid crystal display device, but the disclosure is not limited thereto. For example, the display device may be configured as an organic EL display device or a micro LED display device, etc.

[0046] (2) In the above embodiment, an example was shown in which the ground potential GND is applied to the source electrode of transistor T3, but the disclosure is not limited thereto. For example, a voltage different from the ground potential GND may be applied to the source electrode of transistor T3, which is less than the gate-on voltage and higher than the gate-off voltage.

[0047] (3) In the above embodiment, an example was shown in which a drive signal from the unit circuit three stages later (n+3 stage) is used as the first reset signal, and an example was shown in which a drive signal from the unit circuit five stages later (n+5 stage) is used as the second reset signal. However, the disclosure is not limited thereto. For example, at least one of the first reset signal and the second reset signal may be supplied from a level shifter circuit, or a drive signal from a unit circuit other than the unit circuit described above may be used.

[0048] (4) In the above embodiment, an example was shown in which eight phases of the clock signal, GCK1 to GCK8, are provided, but the disclosure is not limited thereto. The clock signal may be provided in single phase to seven phases, or nine or more phases.

[0049] (5) In the above embodiments, an example was shown in which the transistor includes a crystalline In-Ga-Zn-O based oxide semiconductor, but the disclosure is not limited thereto. The transistor may include an amorphous In-Ga-Zn-O based oxide semiconductor, an oxide semiconductor other than In-Ga-Zn-O, or silicon.

[0050] (6) In the above embodiment, an example was shown in which a bootstrap capacitor Cbst is provided in the unit circuit, but the disclosure is not limited thereto. If bootstrap operation can be performed by the capacitance of transistor T1, a bootstrap capacitor does not need to be provided in the unit circuit.

[0051] (7) In the above embodiment, with respect to an n-channel transistor, the electrode with the higher potential is sometimes called the drain electrode. However, in this disclosure, one of the two electrodes is defined as the drain electrode and the other as the source electrode, and the potential of the source electrode may be higher than the potential of the drain electrode.

[0052] The above configuration can also be explained as follows:

[0053] The drive circuit according to the first configuration is a drive circuit comprising a plurality of unit circuits that output a drive signal to any one of the scan signal lines in the scan signal line group. The unit circuit comprises a node, a first transistor that outputs the drive signal to the scan signal line, wherein the node is connected to the gate electrode of the first transistor, a clock signal is applied to the source electrode of the first transistor, and the drain electrode of the first transistor is connected to the scan signal line, a second transistor to which a set signal is input to the unit circuit, wherein the set signal is input to the gate electrode of the second transistor, and the drain electrode of the second transistor is connected to the node, and a third transistor to which a first reset signal is input to the unit circuit. The first configuration includes a third transistor to which the first reset signal is input to the gate electrode of the third transistor, the drain electrode of the third transistor is connected to the node, and a voltage less than the gate-on voltage and higher than the gate-off voltage is applied to the source electrode of the third transistor; and a fourth transistor to which a second reset signal that becomes high at a time later than the first reset signal is input, the second reset signal is input to the gate electrode of the fourth transistor, the drain electrode of the fourth transistor is connected to the node, and the gate-off voltage is applied to the source electrode of the fourth transistor.

[0054] According to the first configuration described above, the drain-source voltage per transistor can be reduced by discharging the node in stages using two transistors (transistor T3 and transistor T4). Specifically, a voltage less than the gate-on voltage and higher than the gate-off voltage (hereinafter referred to as the "intermediate voltage" at this stage) is applied to the source electrode of the third transistor. Therefore, when the first reset signal is supplied to the gate electrode of the third transistor and the potential of the gate electrode becomes high, the potential difference between the potential of the drain electrode and the potential of the source electrode can be made smaller than the difference between the gate-on voltage and the gate-off voltage. As a result, the drain-source voltage applied to the third transistor that discharges the node of the unit circuit can be reduced, and the generation of hot carriers that cause transistor degradation is suppressed. This reduces the rate of degradation of the third transistor. In addition, when the third transistor turns on, the node can be lowered from the gate-on voltage to a potential equal to the intermediate voltage. Then, the gate-off voltage is applied to the source electrode of the fourth transistor. Therefore, when the second reset signal is supplied to the fourth transistor, the node potential can be reduced from the intermediate voltage to the gate-off voltage (reset). When the second reset signal is supplied to the gate electrode of the fourth transistor and the gate electrode potential becomes high level, the potential difference between the drain electrode potential (intermediate voltage) and the source electrode potential (gate-off voltage) can be made smaller than the difference between the gate-on voltage and the gate-off voltage. As a result, the drain-source voltage applied to the fourth transistor that discharges the node of the unit circuit can be reduced, and the generation of hot carriers, which cause transistor degradation, is suppressed. This reduces the rate of degradation of the fourth transistor.

[0055] In the first configuration, the source electrode of the third transistor may be connected to a terminal having a ground potential that is less than the gate-on voltage and higher than the gate-off voltage (second configuration).

[0056] According to the second configuration described above, the ground potential can be used as a potential that is less than the gate-on voltage and higher than the gate-off voltage, thus eliminating the need for a power supply to generate a voltage (potential) that is less than the gate-on voltage and higher than the gate-off voltage.

[0057] In the first or second configuration, the gate electrode of the third transistor may receive a drive signal from a unit circuit that outputs a drive signal at a second time point later than the first time point in which the unit circuit containing the third transistor outputs a drive signal, as the first reset signal. The gate electrode of the fourth transistor may receive a drive signal from a unit circuit that outputs a drive signal after the second time point, as the second reset signal (third configuration).

[0058] According to the third configuration described above, the second reset signal can be supplied to the fourth transistor without inputting a new reset signal to the drive circuit.

[0059] The display device according to the fourth configuration comprises a drive circuit from any one of the first to third configurations, a substrate on which the drive circuit is arranged, and a counter substrate arranged opposite to the substrate (fourth configuration).

[0060] According to the fourth configuration described above, the drain-source voltage applied to the third and fourth transistors that discharge the nodes of the unit circuit can be reduced, thereby providing a display device that can suppress the degradation of the third and fourth transistors. [Explanation of Symbols]

[0061] 1: Gate drive circuit, 1a: Unit circuit, 2: Display unit, 3: Source drive circuit, 4: Timing controller, 5: Power supply circuit, 6: Level shifter circuit, 10: Display panel, 11: Gate line, 12: Source line, 13: Pixel transistor, 14: Pixel electrode, 15: Common electrode, 20: Control board, 100: Display device, 200: Unit circuit, CLK: Terminal, Cbst: Bootstrap capacitor, N: Node, OUT: Terminal, R: Terminal, R1: Terminal, R2: Terminal, S: Terminal, T1: Transistor, T2: Transistor, T3: Transistor, T3a: Transistor, T4: Transistor

Claims

1. A drive circuit comprising multiple unit circuits that output a drive signal to any one of the scan signal lines in a group of scan signal lines, The aforementioned unit circuit is Nodes and A first transistor that outputs the drive signal to the scan signal line, wherein the node is connected to the gate electrode of the first transistor, a clock signal is applied to the source electrode of the first transistor, and the drain electrode of the first transistor is connected to the scan signal line, A second transistor to which a set signal is input to the unit circuit, wherein the set signal is input to the gate electrode of the second transistor and the drain electrode of the second transistor is connected to the node, A third transistor to which a first reset signal is input to the unit circuit, wherein the first reset signal is input to the gate electrode of the third transistor, the drain electrode of the third transistor is connected to the node, and a voltage less than the gate-on voltage and higher than the gate-off voltage is applied to the source electrode of the third transistor, A drive circuit comprising: a fourth transistor to which a second reset signal that becomes high level at a time later than the first reset signal is input, wherein the second reset signal is input to the gate electrode of the fourth transistor, the drain electrode of the fourth transistor is connected to the node, and the gate-off voltage is applied to the source electrode of the fourth transistor.

2. The drive circuit according to claim 1, wherein the source electrode of the third transistor is connected to a terminal having a ground potential that is less than the gate-on voltage and higher than the gate-off voltage.

3. The gate electrode of the third transistor receives, as the first reset signal, a drive signal from a unit circuit that outputs a drive signal at a second time point later than the first time point at which the unit circuit containing the third transistor outputs a drive signal. The drive circuit according to claim 1, wherein a drive signal from a unit circuit that outputs a drive signal after the second time point is input as a second reset signal to the gate electrode of the fourth transistor.

4. A drive circuit according to any one of claims 1 to 3, A display device comprising a substrate on which the aforementioned scanning signal lines are arranged.

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