Identification and positioning of multiple alignment marks within a single image.

Abstract

As the on-wafer density of dies and / or packages continues to increase, the number of alignment marks on the IC will also increase. Lithography or measurement tools will spend more and more time imaging, leading to decreased productivity and increased production costs. [Solution] The system includes a memory and at least one processing unit operably connected to the memory for detecting a plurality of alignment marks in an image of a plurality of dies on a substrate, wherein each die of the plurality of dies includes at least one of the plurality of alignment marks; detecting a plurality of alignment marks, selecting an alignment mark from the plurality of alignment marks, determining the identity of the alignment marks, and determining the position of the alignment marks.

Description

Technical Field

[0001] This specification generally relates to the manufacture of electronic devices. More specifically, this specification relates to identifying and locating multiple alignment marks on a wafer within a single image.

Background Art

[0002] Electronic packaging and assembly are typically used to connect small-sized integrated circuits (ICs) to an interconnect substrate or interposer such as, for example, a printed circuit board (PCB). A PCB typically includes several passive components and ICs for constructing microelectronic devices, and an interposer is a connection substrate embedded in a package chip, on which multiple chiplet ICs are mounted. The semiconductor industry has been growing rapidly because the integration density of various electronic components such as transistors, diodes, resistors, and capacitors continues to improve. For the most part, the improvement in integration density is brought about by repeatedly reducing the minimum feature size, which enables more components to be incorporated in a given area. As the demand for miniaturization of electronic devices increases, more innovative packaging technologies for making semiconductor dies smaller are needed.

Summary of the Invention

[0003] The following description is a simplified summary of the present disclosure intended to facilitate a basic understanding of some aspects of the present disclosure. This summary is not an extensive overview of the present disclosure. It is not intended to identify key or critical elements of the present disclosure nor to delineate the scope of particular embodiments of the present disclosure or the scope of the claims. Its sole purpose is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description presented below.

[0004] A system is provided according to one embodiment. The system includes a memory and at least one processing unit operably connected to the memory for detecting a plurality of alignment marks in an image of a plurality of dies on a substrate, wherein each die of the plurality of dies includes at least one of the plurality of alignment marks; selecting an alignment mark from the plurality of alignment marks; determining the identity of the alignment marks; and determining the position of the alignment marks.

[0005] A method is provided according to other embodiments. This method includes detecting a plurality of alignment marks in an image of a plurality of dies on a substrate using at least one processing apparatus, wherein each die of the plurality of dies includes at least one of the plurality of alignment marks; selecting an alignment mark from the plurality of alignment marks using at least one processing apparatus; determining the identity of the alignment marks using at least one processing apparatus; and determining the position of the alignment marks using at least one processing apparatus.

[0006] In yet another embodiment, a non-transient computer-readable storage medium is provided. The non-transient computer-readable storage medium includes instructions, which, when executed by at least one processing unit, cause at least one processing unit to perform the steps of detecting a plurality of alignment marks in an image of a plurality of dies on a substrate, wherein each die of the plurality of dies includes at least one of the plurality of alignment marks; selecting an alignment mark from the plurality of alignment marks; determining the identity of the alignment marks; and determining the position of the alignment marks.

[0007] The aspects and embodiments of this disclosure will be better understood from the detailed description and accompanying drawings provided below. The following detailed description and accompanying drawings are intended to illustrate, not limit, the aspects and embodiments. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic partial perspective view of a digital lithography system according to several embodiments. [Figure 2] This is a block diagram of a digital lithography system according to several embodiments. [Figure 3] This is a diagram of a digital lithography system according to several embodiments. [Figure 4] This figure shows an example of a die package on a substrate according to several embodiments. [Figure 5] This figure shows an exemplary system for identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 6] This figure shows an exemplary embodiment for identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 7] This is a diagram of an exemplary camera field of view (FOV) that can be used to identify and locate multiple alignment marks within a single image, according to several embodiments. [Figure 8] This figure shows an exemplary embodiment of identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 9] This figure shows an exemplary embodiment of identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 10] This is a flowchart illustrating an exemplary method for identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 11]This is a flowchart illustrating an exemplary method for identifying and locating multiple alignment marks within a single image, according to several embodiments. [Figure 12] A block diagram of a computer system according to a specific embodiment. [Modes for carrying out the invention]

[0009] Digital lithography refers to the process of forming patterns on a substrate without the need for a physical mask by exposing a photoresist with electromagnetic radiation such as laser light, ultraviolet (UV), or near-ultraviolet light, using a virtual mask file. Examples of digital lithography include maskless lithography and direct-write lithography. Digital lithography technology enables high-speed, high-resolution maskless lithography solutions for printed circuit board (PCB) patterning, solder masking, flat panel displays, laser marking, and other digital exposure systems that benefit from high speed and high precision. Using digital lithography, patterns can be directly exposed to the photoresist film without the use of a contact mask (e.g., a photomask). This reduces material costs, improves productivity, and allows for rapid pattern changes. Direct exposure improves productivity compared to systems using narrow laser beams or masks. The advantage of digital lithography is its ability to change lithographic patterns one after another without the cost of creating new photomasks. Specifically, digital lithography can be used to perform large-area patterning during the manufacturing of electronic devices. Some digital lithography systems are implemented using digital micromirror devices (DMDs). A DMD is a micro-electrical-mechanical system (MEMS) with electrical input and optical output that can perform spatial light modulation. More specifically, a DMD may include an array of micromirrors ("mirrors") that can be individually tilted to reflect light in various directions. Each mirror can be tilted to one of two positions: ON (reflecting light) or OFF (deflecting light). Each mirror acts as a pixel, and by quickly switching the mirror between the ON and OFF positions, the DMD can modulate light to generate an image or pattern.When used with a coherent light source such as a laser, a DMD can generate diffraction patterns due to its structure. The arrangement of the DMD's mirrors can produce a blazed grating effect, allowing incident light to be diffracted to multiple orders. With a coherent light source, the diffraction pattern generated by the DMD can be dispersed into a dot pattern, which is obtained through the interference of light reflected from various micromirrors. The color of the dot pattern depends on the wavelength of the light source used. To perform digital lithography (such as maskless lithography) using a DMD, the DMD can project an image (e.g., shape) onto the photoresist on the substrate by controlling the position of each mirror. More specifically, mirrors in the ON position reflect light onto the photoresist, allowing that light ("dose") to illuminate the image at a specific location. Mirrors in the OFF position deflect the light away from the photoresist. The exposed photoresist can then be developed to remove exposed or unexposed areas, depending on the type of photoresist. The image described above is left on the substrate by developing the exposed photoresist. Correspondingly, by using a combination of mirrors in the ON and OFF positions, the photoresist can be selectively exposed to light, and when developed, the photoresist generates an image on the substrate. In order to perform digital lithography, a digital image in a vector graphics format representing the above image may first be converted to a DMD common format, also called an exposure pattern. Converting a digital image to an exposure pattern may involve rasterizing the image to generate a raster image in bitmap format. A bitmap refers to a matrix pattern of pixels (or dots) that represents the original image. For example, the image may be defined by a virtual mask file, such as a file in the GDS II stream format (GDS is an abbreviation for Graphic Design System).GDS is a binary database file format that can represent planar geometric shapes, text labels, and other information about the layout in a hierarchical format.

[0010] In-line metrology refers to the process of directly measuring and inspecting products or parts within the production line or manufacturing process without interrupting the workflow and / or minimizing the need to remove items for inspection. In-line metrology enables real-time quality control, process monitoring, and immediate feedback for adjustments. Measurements can be taken continuously or at regular intervals during production, allowing for early detection of problems or deviations. Numerous in-line metrology systems are automated, reducing human error and increasing efficiency.

[0011] Alignment marks on components of a substrate, also known as fiducial marks, are used to precisely position and align components during various stages of the manufacturing process, such as lithography. For example, a substrate can be a wafer. Alignment marks are raised structural elements or patterns on the surface of the wafer, and may include structural elements or patterns that can be arranged in a specific configuration, such as parallel lines or symmetrical groups. Examples of alignment marks include cross alignment marks formed by intersecting lines, box-in-box alignment marks (i.e., smaller boxes inside larger boxes), and custom marks (e.g., complex shapes and / or patterns).

[0012] Typically, lithography or measurement tools can identify a single alignment mark within a single image to measure its position during alignment. As the on-wafer density of dies and / or packages continues to increase, the number of alignment marks on an IC increases. This causes lithography or measurement tools to spend more and more time on imaging, thus reducing productivity and increasing production costs. Exemplaryly, there may be 400 packages on a wafer, where each package has four corner marks, meaning there are a total of 1600 alignment marks to determine during alignment. Using a typical approach where each alignment mark is identified within its own single image, 1600 images would be taken to determine the position of 1600 alignment marks. If each step takes approximately 2.2 seconds, it could take more than an hour to process all 1600 alignment marks.

[0013] The aspects and embodiments of this disclosure address the aforementioned and other shortcomings of the existing technology by enabling the identification and localization of multiple alignment marks within a single image. The embodiments described herein can be used to determine (e.g., estimate) the location of multiple alignment marks identified within an image area. The alignment marks may belong to various components of a substrate (such as a wafer). Examples of components include dies and / or die packages. The embodiments described herein may further classify and record data that identifies the association between the alignment marks and their respective components.

[0014] The aspects and embodiments of this disclosure offer technical advantages over other approaches. For example, the embodiments described herein can reduce the number of processing resources used during alignment. As another example, the embodiments described herein can reduce the amount of time required to perform alignment. Exemplarily, in the example of 1600 alignment marks above, multiple corner marks may be identified within a single image. Since some images contain multiple marks, for example, the tool can determine the positions of 1600 alignment marks in 450 images. In this example, processing the substrate (e.g., wafer) during alignment may take approximately 17 minutes, which is about 3.5 times faster than in typical embodiments. Further details regarding the identification of multiple alignment marks on a wafer within a single image are described below with reference to Figures 1 to 12.

[0015] Figure 1 is a schematic partial perspective view of a digital lithography system ("System") 100 according to several embodiments. For example, System 100 can implement a digital micromirror device (DMD). System 100 may include a digital lithography subsystem ("Subsystem") 101. Subsystem 101 may include a stage 114 and a processing unit 104. The stage 114 is supported by a pair of tracks 116. The substrate 120 is supported by the stage 114. The stage 114 is operable to move along the pair of tracks 116. The stage 114 can move along the tracks 116 in the X and Y directions as defined in Figure 1. The processing unit 104 is configured to expose a photoresist using one or more image projection systems (IPS) 106 in a digital lithography process. The IPS 106 is supported by supports 108 adjacent to (e.g., straddling) the pair of tracks 116. The support 108 provides an opening 112 through which a pair of tracks 116 and a stage 114 pass beneath the processing unit 104. The subsystem 101 may further include an encoder coupled to the stage.

[0016] The substrate 120 may be formed from any suitable material or combination of materials used as part of a flat panel display, for example, from glass. In other embodiments that can be combined with other embodiments described herein, the substrate 120 may be made from other materials that can be used as part of a flat panel display. The substrate 120 has a thin film formed on it that is patterned by pattern etching or the like, and the thin film to be patterned has a photoresist layer formed on it that is sensitive to electromagnetic radiation (e.g., UV). Positive photoresists contain portions of photoresist that, when exposed to radiation, dissolve in a photoresist developer applied to the photoresist after a pattern has been written to the photoresist using electromagnetic radiation. Negative photoresists contain portions of photoresist that, when exposed to radiation, do not dissolve in a photoresist developer applied to the photoresist after a pattern has been written to the photoresist using electromagnetic radiation. The chemical composition of the photoresist determines whether it is a positive or negative photoresist. Examples of photoresists include, but are not limited to, at least one of diazonaphthoquinone, phenol-formaldehyde resin, poly(methyl methacrylate), poly(methylglutarimide), and SU-8. After exposure of the photoresist to electromagnetic radiation, the resist is developed, leaving an exposed underlying film layer. Subsequently, this underlying film layer is pattern-etched through the photoresist apertures using a patterned photoresist to form portions of the electronic circuitry of the display panel.

[0017] System 100 may further include a lithography controller 122 and a controller 110 that are communicatively connected to subsystem 101. For example, an encoder 118 can provide the lithography controller 122 with information regarding the position of the stage 114. The lithography controller 122 is typically designed to facilitate the control and automation of the processing techniques described herein. The lithography controller 122 may be connected to or communicative with the processing unit 104, the stage 114, and the encoder 118. The processing unit 104 and the encoder 118 can provide information to the lithography controller 122 regarding substrate processing and substrate alignment. For example, the processing unit 104 can provide information to the lithography controller 122 to alert it that substrate processing is complete. The controller 110 is operable to supply one or more virtual mask files corresponding to exposure patterns, or the controller 110 is otherwise configured to perform the processing described herein. The lithography controller 122 facilitates the control and automation of the digital lithography process based on a virtual file provided by the virtual mask software application 102. The virtual mask file, readable by the lithography controller 122, determines which tasks are performed on the substrate. The virtual mask file corresponds to the exposure pattern written to the photoresist using electromagnetic radiation.

[0018] The processing unit 104 may include a pattern generator configured to receive a virtual mask file from the virtual mask software application 102. The virtual mask file may be provided to the processing unit 104 via the lithography controller 122. The processing unit 104 is configured to expose a photoresist using one or more image projection systems (IPSs) 106 in a digital lithography process. One or more IPSs 106 are operable to project a write beam of electromagnetic radiation onto the substrate 120. The exposure pattern generated by the processing unit 104 is projected by the IPS 106, and the photoresist on the substrate 120 is exposed to be the exposure pattern. By exposing the photoresist, one or more various features are formed in the photoresist. In one embodiment that can be combined with other embodiments described herein, each IPS 106 includes a spatial light modulator that modulates incident light to generate a desired image. The spatial light modulator includes a plurality of electrically addressable elements that can be individually controlled. Each electrically addressable element can be in an "ON" position or an "OFF" position based on the digital pattern file 204 (illustrated in FIG. 2). When light reaches the spatial light modulator, the electrically addressable elements in the "ON" position project a plurality of write beams onto a projection lens (not shown). Then, the projection lens projects the write beam onto the substrate 120. The electrically addressable elements include, but are not limited to, digital micromirrors, liquid crystal displays (LCDs), liquid crystal on silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, microshutters, micro LEDs, VCSELs, liquid crystal displays (LCDs), or any solid state emitter of electromagnetic radiation.

[0019] Figure 2 is a block diagram of a digital lithography system ("System") 200 according to several embodiments. As shown, the System 200 may include subsystems 101, a virtual mask software application 102, and a controller 110, as previously described with reference to Figure 1. The controller 110 is operable to facilitate the transfer of a digital pattern file 204 (e.g., data) provided to the controller 110. The controller 110 is operable to run the virtual mask software application 102 to convert the digital pattern file 204 into a virtual mask file (not shown) having an exposure pattern readable by a processing unit 104. Each lithography environment device is operable to be connected to one another via a communication link 101. Each lithography environment device is operable to be connected to the controller 110 via the communication link 101. The lithography environment 200 may be located in the same area or within a production facility, or each of the lithography environment devices may be located in different areas.

[0020] The controller 110 includes a central processing unit (CPU) 212, support circuits 214, and memory 216. The CPU 212 may be any form of computer processor available for use in an industrial setting to control lithography environment devices. Memory 216 is connected to the CPU 212. Memory 216 may be one or more readily available memory, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or local or remote digital storage in any other form. Support circuits 214 are connected to the CPU 212 to support the processor. For example, support circuits 214 may include caches, power supplies, clock circuits, input / output circuits, and subsystems. The CPU 212 may be connected to input / output (I / O) devices found within the support circuits 214 and memory 216. The controller 110 is operable to facilitate the transfer of digital pattern files 204 to the digital lithography system 100 via a communication link 101. The digital pattern file 204 is operable to be provided via the controller 110 to a virtual mask software application 102 or a digital lithography system 100.

[0021] Memory 216 may include one or more software applications, such as virtual mask software application 102. CPU 212 can be a hardware unit or a combination of hardware units capable of executing software applications and processing data. In some configurations, CPU 212 includes a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and / or a combination of such units. CPU 212 is configured to execute one or more software applications, such as virtual mask software application 102, and process stored media data that may be included in memory 216 respectively. Controller 110 controls the transfer of data and files between various lithography environment devices.

[0022] Controller 110 is operable to receive an exposure pattern of a virtual mask file and transfer the exposure pattern to digital lithography system 100 via communication link 101. A virtual mask file (or computer instructions) readable by controller 110, which may also be referred to as an imaging design file, determines which tasks are executable on a substrate. Virtual mask software application 102 is illustrated as separate from controller 110 (e.g., within the cloud), but it is contemplated that virtual mask software application 102 may be stored locally (e.g., within memory 216).

[0023] The virtual mask file corresponds to a pattern written to a photoresist using electromagnetic radiation output by the digital lithography system 100. In one embodiment, which can be combined with other embodiments described herein, the pattern may be formed by one or more patterning devices. For example, one or more patterning devices are configured to perform ion beam etching, reactive ion etching, electron beam (e-beam) etching, wet etching, nanoimprint lithography (NIL), and combinations thereof. The virtual mask file may be provided in various formats. For example, the format of the virtual mask file may be, among other things, either the GDS format or the OASIS format. The virtual mask file contains information corresponding to features of the exposure pattern generated on the substrate (e.g., substrate 120). The virtual mask file may include target regions corresponding to one or more structural elements. The structural elements may be made as geometric shapes (e.g., polygons).

[0024] The lithography model can be a physically based model. For example, the lithography model can be a scalar image model or a vector image model. In some embodiments, the lithography model utilizes a matrix defined by optical properties and / or photoresist properties. For example, the matrix may include a Transmission Cross Coefficient (TCC). In some embodiments, other numerical simulation techniques such as Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), and Source Mask Optimization (SMO) may be used. However, all such models and modeling techniques, whether currently known or to be developed in the future, are intended to be within the scope of disclosure. The lithography model may be constructed to be defined on optical properties (e.g., optical properties related to the digital lithography system 100) and photoresist properties (e.g., properties of the photoresist on which the pattern will be printed, such as the material and processing properties of the photoresist). The characteristics of a photoresist include, but may include, numerical aperture, exposure, irradiation type, irradiation size, and wavelength.

[0025] Once the lithography model is constructed, a virtual mask file can be provided to the lithography model as input. The lithography model can then output predictions of the airborne image and resist profile of the virtual mask file. Post-processing steps may determine the ILS and depth of focus of the features formed on the photoresist of the substrate based on the virtual mask file. The lithography model will use numerical calculations to predict variables necessary to achieve the maximum ILS and depth of focus (or the maximum ILS and depth of focus within other predetermined constraints). These variables include the width and position of the exposure pattern and the pattern bias value. The numerical calculations can be iterative, level set, or other numerical calculation methods capable of solving the lithography model.

[0026] The controller 110 provides the digital pattern file 204 to the virtual mask software application 102. The virtual mask software application 102 is operable to receive the digital pattern file 204 via the communication link 101. The virtual mask software application 102 may be vMASC software. In one embodiment, which can be combined with other embodiments described herein, the virtual mask software application 102 is a software program stored in the memory 216 of the controller 110. The CPU 212 is configured to execute the software program. In another embodiment, which can be combined with other embodiments described herein, the virtual mask software application 102 may be a remote computer server including the controller and memory (e.g., a data store).

[0027] The digital pattern file 204 can be converted into one or more virtual mask files by the virtual mask software application 102. For example, the first virtual mask file may correspond to one exposure pattern, and the second virtual mask file may correspond to other exposure patterns. The virtual mask file is a digital representation of the design to be printed by the digital lithography system 100. The virtual mask file is provided to the digital lithography system 100 via the communication link 101. The virtual mask file is stored in the digital lithography system 100.

[0028] Figure 3 is a diagram of a system 300 including multiple image projection systems (IPS) 301 according to several embodiments. As shown in Figure 3, each IPS 301 can generate a write beam 302 onto the surface 304 of a substrate 120 corresponding to multiple processing positions 312 along multiple trajectories 116, each trajectory 116 being scanned by one or more write beams 302. The movement of the substrate 120 is in the in-scan direction (the primary direction in which scanning takes place), indicated by arrow 315, and the cross-scan direction is indicated by arrow 320. While the substrate 120 moves in the in-scan and cross-scan directions, the entire surface 304 can be patterned by the write beams 302. The number of IPS 301 may vary based on the size of the substrate 120 and / or the speed of the stage 114. In one embodiment, 10 IPS 301 are present in the processing unit 104.

[0029] Each IPS301 includes a light source 352, an aperture 354, a lens 356, an attenuating prism assembly 358, a spatial light modulator (SLM) 360, and a projection lens 366. The components of each of the multiple IPS301 differ according to the SLM360 used. Each SLM360 includes, but is not limited to, a micro-LED, a VCSEL, an array of liquid crystal displays (LCDs), or any solid-state emitter for electromagnetic radiation, and a DMD (digital micromirror device). Each SLM360 may include multiple SLM pixels. Each SLM pixel is individually controllable to project a writing beam. Multiple SLM pixels come together to form a pattern to be written to a photoresist, which is referred to herein as a mask pattern. The projection optical system 366 includes a projection lens, for example, a 10x objective lens, used to project light onto the substrate 120. During operation, each SLM pixel is in either the "on" or "off" position based on mask pattern data provided to the SLM360 by the controller 110. Each SLM pixel in the "on" position forms a write beam, and the corresponding projection optical device 366 then projects this write beam onto the surface of the photoresist layer on the substrate 120 to form pixels of the mask pattern. In some embodiments, each SLM360 includes multiple mirrors, for example, multiple SLM pixels. Each of the multiple mirrors corresponds to one SLM pixel, and this one SLM pixel corresponds to one pixel of the mask pattern. In some embodiments, the SLM360 is a DMD. In some embodiments, the DMD includes more than approximately 4,000,000 mirrors, while in other embodiments, it may include 1920x1080 mirrors, representing the number of pixels in a high-definition television.

[0030] The light source 352 is any suitable light source capable of generating light having a predetermined wavelength, such as a light-emitting diode (LED) or a laser. In one embodiment, the predetermined wavelength is in the blue range or the near-ultraviolet (UV) range (e.g., less than about 450 nm). The attenuation prism assembly 358 includes a plurality of reflective surfaces. During operation, a ray 453 is generated by the light source 352. The ray 353 is reflected by the attenuation prism assembly 358 to the SLM 360. When the ray 353 reaches the mirrors of the SLM 360, each mirror in the "on" position reflects the ray 353 to the projection lens 366. The projection optical system 366 then projects a plurality of writing beams (e.g., "shots") 302 onto the photoresist layer of the substrate 120. The plurality of writing beams 302 form a plurality of pixels of the mask pattern.

[0031] Figure 4 is a figure 400 showing an exemplary substrate (e.g., wafer) 410 and a set of die packages 420 on the substrate 410 according to several embodiments. In this exemplary embodiment, each die package in the set of die packages 420 includes a pair of dies. For example, the set of die packages 420 may include a first die package including dies 422-1 and 422-2, a second die package including dies 422-3 and 422-4, a third die package including dies 422-5 and 422-6, and a fourth die package including dies 422-7 and 422-8. As further shown in Figure 4, each of dies 422-1 to 422-8 includes a plurality of alignment marks. More specifically, in this example, each alignment mark on the die is a corner mark formed around each corner of the die. For example, die 422-1 includes alignment marks 424-1 to 424-4, die 422-2 includes alignment marks 424-5 to 424-8, die 422-3 includes alignment marks 424-9 to 424-12, die 422-4 includes alignment marks 424-13 to 424-16, die 422-5 includes alignment marks 424-17 to 424-20, die 422-6 includes alignment marks 424-21 to 424-24, die 422-7 includes alignment marks 424-25 to 424-28, and die 422-8 includes alignment marks 424-29 to 424-32. This will be explained in more detail below with reference to Figures 5 to 11.

[0032] Figure 5 is a block diagram of an exemplary system 500 according to several embodiments. As shown in Figure 5, the system 500 may include a substrate 410 containing a set of die packages 420, as previously described with reference to Figure 4. The substrate 410 may be located on a stage. The system 500 may further include a camera 510 operably connected to an alignment mark identification system 520. The camera 510 can acquire (e.g., image) an image of the set of die packages 420, and the alignment mark identification system 520 can identify multiple alignment marks on the set of die packages 420 in the image.

[0033] Figure 6 is a 600-figure diagram illustrating an exemplary embodiment of identifying and locating multiple alignment marks within a single image according to several embodiments. As shown in Figure 6, a camera (e.g., camera 510 in Figure 5) has a camera FOV 610A which includes a first set of image regions including image region 620A, and a camera FOV 610B which includes a second set of image regions including image region 620B. In this exemplary example, there are four image regions in the first set of image regions and six image regions in the second set of image regions. Each image region corresponds to the location of a die alignment mark (e.g., a die corner). For example, image region 620A corresponds to the location of alignment mark 424-4 on die 422-1, and image region 620B corresponds to the location of alignment mark 424-15 on die 422-4. The alignment mark identification system (e.g., the alignment mark identification system 520 in Figure 5) is capable of identifying multiple alignment marks corresponding to image areas within and / or within the range of camera FOV 610A and / or camera FOV 610B. As will be described in more detail below with reference to Figure 7, at least one characteristic of camera FOV 610 may be adjusted (e.g., dynamically adjusted) based on manufacturing requirements. Examples of characteristics of camera FOV 610 include the number of alignment marks within the range of camera FOV 610 and the positioning of image areas 620 of camera FOV 610. In this exemplary example, the alignment marks have a rectangular shape. However, the shapes of the alignment marks described herein should not be considered limiting.

[0034] Figure 700 shows exemplary camera FOVs according to several embodiments. For example, Figure 710A is a camera FOV that includes a single image region within the center of the camera FOV. Figure 720A is a camera FOV that includes a single image region off-center. Figure 730A is a camera FOV that includes three image regions. Figure 740A is a camera FOV that includes five image regions. The number and / or location of the image regions should not be considered limiting.

[0035] Figure 800 shows an exemplary embodiment of identifying and locating multiple alignment marks within a single image according to several embodiments. More specifically, Figure 800 illustrates an image cropping approach for identifying and locating multiple alignment marks. In some embodiments, the substrate 410 is rotated by a certain angle, as shown.

[0036] As shown in Figure 8, an alignment mark identification system (e.g., the alignment mark identification system 520 in Figure 5) can identify a first set of alignment marks from the substrate 410. The first set of alignment marks may include one or more "unambiguous marks" that can be used to generate a model of the substrate 410. More specifically, the first set of alignment marks may be identified from a set of images captured by a camera (e.g., the camera 510 in Figure 5). The first set of alignment marks may include one or more alignment marks drawn individually within one or more image regions. In this exemplary embodiment, the first set of alignment marks includes alignment mark 424-1 drawn in image region 810-1, alignment mark 424-14 drawn in image region 810-1, alignment mark 424-19 identified in image region 810-3, and alignment mark 424-32 drawn in image region 810-4.

[0037] Next, the alignment mark identification system can generate a model of the substrate 410 using the first alignment mark set. For example, generating the model may include identifying the position of the wafer (e.g., displacement and / or rotation).

[0038] Next, the alignment mark identification system can acquire an image of a second set of alignment marks within the selected image region. In this exemplary embodiment, the second set of alignment marks includes alignment marks 424-4, 424-7, 424-18, and 424-21, and the selected image region is image region 820.

[0039] Next, the alignment mark identification system can select an alignment mark from a second set of alignment marks in a second image region and determine (e.g., estimate) the position of the selected alignment mark. For example, the position of the selected alignment mark can be determined based on the model and the positions of the alignment marks indicated in the design file. In this exemplary embodiment, the selected alignment mark is the alignment marks 424-18 indicated in box 830. In some embodiments, the position of the selected alignment mark is determined based on the average distance (e.g., weighted average distance) to a first set of alignment marks (e.g., a set of unambiguous alignment marks). The alignment mark identification system can then modify the image to reduce ambiguity. For example, modifying the image may include cropping out portions of the image outside box 830. The alignment mark identification system can then align the selected alignment mark to the model based on the modified image. In some embodiments, aligning the selected alignment mark includes performing pattern matching using the selected alignment mark. A similar process can be performed for each alignment mark in the second alignment mark set.

[0040] Figure 9 is a figure 900 illustrating an exemplary embodiment of identifying and locating multiple alignment marks within a single image, according to several embodiments. More specifically, Figure 900 illustrates a rule-based approach to identifying and locating multiple alignment marks. As shown in Figure 9, a set of alignment marks 910 may include alignment marks "a," "b," "c," "d," "e," and "f." Each alignment mark can be uniquely identified by a specific rule. For example, as shown in Figure 920, alignment mark "a" can be identified as an alignment mark in the set of alignment marks 910 that does not have any alignment marks to its left, above, or diagonally above and to the left of it. As another example, as shown in Figure 930, alignment mark "c" can be identified as an alignment mark in the set of alignment marks 910, where there are alignment marks above and below it, and no alignment marks to its left (for example, left, upper left, or lower left). These rules are provided as examples, and other rules are possible.

[0041] Figure 10 shows a flowchart of an exemplary method 1000 for identifying and locating multiple alignment marks within a single image, according to several embodiments. Method 1000 may be performed by a processing logic unit including hardware (circuits, dedicated logic unit, etc.), computer-readable instructions (executed on a general-purpose computer system or dedicated machine), or a combination of both. In the exemplary embodiment, Method 1000 may be performed by at least one processing unit (e.g., a digital lithography system). Furthermore, it should be understood that the steps shown in Figure 10 may be performed simultaneously or in an order different from the illustrated order.

[0042] In step 1010, the processing logic unit detects multiple alignment marks within an image of multiple dies on a substrate. In some embodiments, the substrate includes a wafer. For example, the substrate may include a set of die packages, where each die package in the set of die packages includes multiple dies (e.g., pairs of dies), and each die includes at least one alignment mark. At least one image may be acquired by a camera, and the multiple alignment marks may be grouped within the image area of ​​the camera.

[0043] In step 1020, the processing logic unit selects an alignment mark from a plurality of alignment marks; in step 1030, the processing logic unit determines the identity of the alignment marks; and in step 1040, the processing logic unit determines the position of the alignment marks. Steps 1020 to 1040 can be repeated for each of the plurality of alignment marks.

[0044] In some embodiments, as previously described with reference to Figure 9, Method 1000 is performed using a rule-based approach in which selected alignment marks may have positions defined by rules. For example, determining the identity of an alignment mark and / or determining the position of an alignment mark may include determining from a plurality of rules which rules the alignment mark satisfies. Each of the plurality of alignment marks may satisfy each of the single rules of the plurality of rules, which corresponds to each identity of each alignment mark. In some embodiments, each of the plurality of rules is defined by at least one of the following: for an alignment mark, one or more other alignment marks exist at one or more first positions, or for an alignment mark, one or more other alignment marks do not exist at one or more second positions.

[0045] In some embodiments, as described earlier with reference to Figure 8 and later with reference to Figure 11, Method 1000 is performed using an image cropping approach.

[0046] Figure 11 shows a flowchart of an exemplary method 1100 for identifying and aligning multiple alignment marks within a single image, according to several embodiments. Method 1100 may be performed by a processing logic unit including hardware (circuits, dedicated logic unit, etc.), computer-readable instructions (executed on a general-purpose computer system or dedicated machine), or a combination of both. In the exemplary embodiment, Method 1100 may be performed by at least one processing unit (e.g., a digital lithography system). Furthermore, it should be understood that the steps shown in Figure 11 may be performed simultaneously or in an order different from the illustrated order.

[0047] Method 1100 may include steps 1010 to 1040, which were described earlier with reference to Figure 10.

[0048] As shown in Figure 11, detecting multiple alignment marks in step 1010 may include acquiring one or more first images of the substrate in step 1110. For example, each of the one or more first images may contain its own single alignment mark.

[0049] Detecting multiple alignment marks in step 1010 may include processing one or more first images in step 1120 to determine the position and orientation of the substrate. More specifically, the position and orientation of the substrate may be determined based on each individual alignment mark.

[0050] Detecting multiple alignment marks in step 1010 may include generating a model of the substrate based on its position and orientation in step 1130.

[0051] Determining the identity of the alignment marks in step 1030 and / or determining the position of the alignment marks in step 1040 may include determining the estimated position of the alignment marks (selected in step 1020) based on the design position of the model and the alignment marks in step 1150. More specifically, the design position may correspond to the design file of the substrate.

[0052] Determining the identity of the alignment marks in step 1030 and / or determining the position of the alignment marks in step 1040 may include narrowing the search field of the alignment marks by generating a corrected image of the alignment marks based on the estimated position of the alignment marks in step 1160. More specifically, other alignment marks of multiple alignment marks may not be included in the corrected image.

[0053] In step 1170, the processing logic unit can align the alignment marks to the model based on the corrected image.

[0054] Further details regarding steps 1010-1040 and 1110-1170 are described earlier with reference to Figures 1-10.

[0055] Figure 12 is a block diagram showing a computer system 1200 according to a particular embodiment. In some embodiments, the computer system 1200 is connected to other computer systems (for example, via a network such as a local area network (LAN), intranet, extranet, or internet). In some embodiments, the computer system 1200 operates as a server or client computer in a client-server environment, or as a peer computer in a peer-to-peer network, or in a distributed network environment. In some embodiments, the computer system 1200 is provided by a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any device capable of executing a set (sequence or other) of instructions that specify the actions that the device should perform. Furthermore, the term “computer” includes any collection of computers that individually or in conjunction execute one or more sets of instructions to perform any one or more of the methods described herein.

[0056] In a further embodiment, the computer system 1200 includes a processing unit 1202, a volatile memory 1204 (e.g., random access memory (RAM)), a non-volatile memory 1206 (e.g., read-only memory (ROM) or electrically-erasable programmable ROM (EEPROM)), and a data storage device 1216, which communicate with each other via a bus 1208.

[0057] In some embodiments, the processing unit 1202 is provided by one or more processors, such as a general-purpose processor (e.g., a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a microprocessor implementing other types of instruction sets, or a microprocessor implementing a combination of instruction set types) or a dedicated processor (e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor).

[0058] In some embodiments, the computer system 1200 further includes a network interface device 1222 (for example, connected to a network 1274). In some embodiments, the computer system 1200 also includes a video display unit 1210 (for example, an LCD), an alphanumeric input device 1212 (for example, a keyboard), a cursor control device 1214 (for example, a mouse), and a signal generator 1220.

[0059] In some embodiments, the data storage device 1216 includes a non-transient computer-readable storage medium 1224 that stores instructions 1226 for recording one or more of the methods or functions described herein. For example, the instructions 1226 may include instructions for controlling the movement of a stage and / or exposure unit of a digital lithography system, and when executed, such instructions can perform a method for performing exposure unit boundary smoothing as described herein.

[0060] In some embodiments, instruction 1226 also resides entirely or partially in the volatile memory 1204 and / or the processing unit 1202 during execution by the computer system 1200, and therefore, in some embodiments, the volatile memory 1204 and the processing unit 1202 also constitute a machine-readable storage medium.

[0061] In the examples shown, the computer-readable storage medium 1224 is shown as a single medium, but the term “non-transitory computer-readable storage medium” includes a single or multiple mediums (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more executable instruction sets. The term “computer-readable storage medium” also includes any tangible medium capable of storing or recording instruction sets for computer execution that cause a computer to execute one or more of the methods described herein. The term “computer-readable storage medium” includes, but is not limited to, solid-state memory, optical media, and magnetic media.

[0062] In some embodiments, the methods, components, and features described herein are implemented by separate hardware components or are incorporated into the functionality of other hardware components such as ASICS, FPGAs, DSPs, or similar devices. In some embodiments, the methods, components, and features are implemented by firmware modules or functional circuits within a hardware device. In some embodiments, the methods, components, and features are implemented by any combination of hardware devices and computer program components, or by computer programs.

[0063] Unless otherwise specified, terms such as “receiving,” “initiating,” or “performing” refer to actions and processes performed or realized by a computer system that manipulates data represented as physical (electronic) quantities in the computer system’s registers and memory, and converts it into other data similarly represented as physical quantities in the computer system’s memory or registers, or in other such information storage devices, transmission devices, or display devices. In some embodiments, terms such as “first,” “second,” “third,” and “fourth” as used herein are intended as symbols for distinguishing between different elements, and the order according to the numerical notation is not significant.

[0064] The embodiments described herein also relate to apparatus for carrying out the methods described herein. In some embodiments, the apparatus includes a general-purpose computer system that is specifically configured for carrying out the methods described herein or is selectively programmed by a computer program stored in the computer system. Such a computer program is stored in a computer-readable tangible storage medium.

[0065] The methods and examples described herein are not inherently related to any particular computer or other device. In some embodiments, various general-purpose systems are used in accordance with the teachings described herein. In some embodiments, more specialized devices are constructed to perform each of the methods and / or their individual functions, routines, subroutines, or processes. Examples of various systems structures described herein are described in the preceding specification.

[0066] The above description provides numerous specific details, such as examples of specific systems, components, and methods, in order to provide a good understanding of some embodiments of the present invention. However, it will be apparent to those skilled in the art that at least some embodiments of the present invention are implementable without these specific details. In other examples, well-known components or methods are not described in detail or are presented in the form of simple block diagrams in order to avoid unnecessarily obscuring the invention. Thus, the specific details described are merely illustrative. Certain implementations may differ from these exemplary details but are still considered to be within the scope of the present invention.

[0067] Throughout this specification, any reference to “one embodiment” means that a particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment. Therefore, the appearance of the phrase “in one embodiment” in various places throughout this specification does not necessarily all refer to the same embodiment. Furthermore, the term “or” is intended to mean inclusive, not exclusive, “or.” Where the terms “about” or “approximately” are used herein, this is intended to mean that the nominal values ​​presented are accurate within a range of ±10%.

[0068] Although the steps of the methods described herein are illustrated and described in a specific order, the order of the steps of each method may be changed so that certain steps are performed in reverse order or certain steps are performed at least partially concurrently with other steps. In other embodiments, instructions or substeps of separate steps may be in a discontinuous and / or alternating configuration.

[0069] It should be understood that the above description is intended to be illustrative and not limiting. A number of other embodiments will become apparent to those skilled in the art upon reading and understanding the description in the prior specification. While this disclosure describes specific embodiments, it will be found that the systems and methods of this disclosure are not limited to the embodiments described herein and can be implemented with modifications within the scope of the appended claims. Accordingly, this specification and the drawings should be considered illustrative, not limiting. Therefore, the scope of this disclosure should be defined in relation to the appended claims, together with the entire scope of equivalents to which such claims are granted.

Claims

1. It is a system, Memory and At least one processing unit operably connected to the memory, The process involves detecting multiple alignment marks within an image of multiple dies on a substrate, wherein each die of the multiple dies includes at least one of the multiple alignment marks. Selecting an alignment mark from the aforementioned multiple alignment marks, To determine the identity of the aforementioned alignment marks, Determining the position of the aforementioned alignment marks, A processing apparatus for performing the following: A system equipped with these features.

2. The system according to claim 1, wherein the plurality of dies are contained within a set of die packages, and each die package in the set of die packages contains one or more of the plurality of dies.

3. In order to detect the plurality of alignment marks, the at least one processing device, Acquiring one or more additional images of the substrate, wherein each of the one or more additional images includes its own single alignment mark. The process of processing one or more additional images to determine the position and orientation of the substrate based on each individual alignment mark, To generate a model of the substrate based on the position and orientation of the substrate, The system according to claim 1, further comprising the following steps.

4. In order to determine the identity of the alignment marks, the at least one processing device, Determining the estimated position of the alignment mark based on the model and the design position of the alignment mark, wherein the design position corresponds to the design file of the substrate, and determining the estimated position. Narrowing the survey field of the alignment marks by generating a corrected image of the alignment marks based on the estimated position of the alignment marks, such that other alignment marks of the plurality of alignment marks are not included in the corrected image. The system according to claim 3, further comprising the following steps.

5. The system according to claim 4, further comprising the at least one processing apparatus aligning the alignment marks to the model based on the modified image.

6. In order to determine the identity of the alignment marks, the at least one processing device determines from a plurality of rules the rules that the alignment marks satisfy, The system according to claim 1, wherein each of the plurality of alignment marks satisfies each of the single rules of the plurality of rules, which corresponds to each of the identity of each of the alignment marks.

7. The system according to claim 6, wherein each of the plurality of rules is defined by at least one of the following: one or more other alignment marks exist at one or more first positions with respect to the alignment mark, or one or more other alignment marks do not exist at one or more second positions with respect to the alignment mark.

8. It is a method, A method for detecting multiple alignment marks in an image of multiple dies on a substrate using at least one processing device, wherein each die of the multiple dies includes at least one of the multiple alignment marks. The at least one processing device selects an alignment mark from the plurality of alignment marks, The identity of the alignment marks is determined by the at least one processing device, The position of the alignment mark is determined by the at least one processing device, Methods that include...

9. The method according to claim 8, wherein the plurality of dies are contained within a set of die packages, and each die package in the set of die packages contains one or more of the plurality of dies.

10. Detecting the aforementioned multiple alignment marks means Acquiring one or more additional images of the substrate, wherein each of the one or more additional images includes its own single alignment mark. The process of processing one or more additional images to determine the position and orientation of the substrate based on each individual alignment mark, To generate a model of the substrate based on the position and orientation of the substrate, The method according to claim 8, further comprising:

11. Determining the identity of the alignment marks is: Determining the estimated position of the alignment mark based on the model and the design position of the alignment mark, wherein the design position corresponds to the design file of the substrate, and determining the estimated position. Narrowing the survey field of the alignment marks by generating a corrected image of the alignment marks based on the estimated position of the alignment marks, such that other alignment marks of the plurality of alignment marks are not included in the corrected image. The method according to claim 10, further comprising:

12. The method according to claim 11, further comprising aligning the alignment marks to the model based on the modified image using at least one processing device.

13. Determining the identity of the alignment marks further includes determining, from among a plurality of rules, which rules the alignment marks satisfy. The method according to claim 8, wherein each of the plurality of alignment marks satisfies each of the single rules of the plurality of rules, which corresponds to each of the identity of each of the alignment marks.

14. The method according to claim 13, wherein each of the plurality of rules is defined by at least one of the following: one or more other alignment marks exist at one or more first positions with respect to the alignment mark, or one or more other alignment marks do not exist at one or more second positions with respect to the alignment mark.

15. A non-transient computer-readable storage medium containing instructions, wherein, when the instructions are executed by at least one processing unit, the at least one processing unit, The process involves detecting multiple alignment marks within an image of multiple dies on a substrate, wherein each die of the multiple dies includes at least one of the multiple alignment marks. Selecting an alignment mark from the aforementioned multiple alignment marks, To determine the identity of the aforementioned alignment marks, Determining the position of the aforementioned alignment marks, Perform a process that includes A non-transient computer-readable storage medium.

16. The non-transient computer-readable storage medium according to claim 15, wherein the plurality of dies are contained within a set of die packages, and each die package in the set of die packages contains one or more of the plurality of dies.

17. Detecting the aforementioned multiple alignment marks means Acquiring one or more additional images of the substrate, wherein each of the one or more additional images includes its own single alignment mark. The process of processing one or more additional images to determine the position and orientation of the substrate based on each individual alignment mark, To generate a model of the substrate based on the position and orientation of the substrate, A non-transient computer-readable storage medium according to claim 15, further comprising:

18. Determining the identity of the alignment marks is: Determining the estimated position of the alignment mark based on the model and the design position of the alignment mark, wherein the design position corresponds to the design file of the substrate, and determining the estimated position. Narrowing the survey field of the alignment marks by generating a corrected image of the alignment marks based on the estimated position of the alignment marks, such that other alignment marks of the plurality of alignment marks are not included in the corrected image. A non-transient computer-readable storage medium according to claim 17, further comprising:

19. The non-transient computer-readable storage medium according to claim 18, further comprising aligning the alignment marks to the model based on the modified image using at least one of the processing devices.

20. Determining the identity of the alignment marks is: Determining from a plurality of rules which the alignment mark satisfies, further comprising determining a rule such that each of the plurality of alignment marks satisfies each of the single rules of the plurality of rules, which corresponds to each of the identity of each of the plurality of alignment marks, The method according to claim 8, wherein each of the plurality of rules is defined by at least one of the following: one or more other alignment marks exist at one or more first positions with respect to the alignment mark, or one or more other alignment marks do not exist at one or more second positions with respect to the alignment mark.

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