Multilayer ceramic capacitor

Abstract

To provide a series-structure multilayer ceramic capacitor that can suppress the occurrence of delamination at the interface between the internal electrode layer and the dielectric layer. [Solution] A multilayer ceramic capacitor 1 includes a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33, and in a dielectric region DA formed by a dielectric layer 20 sandwiched between the first internal electrode layer 31 or the second internal electrode layer 32 in the stacking direction T, a first floating island electrode FE1 is provided in the region between the end face LS of the laminate 10 and the intermediate electrode layer 33, and a second floating island electrode FE2 is provided in the region between the side surface WS of the laminate 10 and the internal electrode layer 30.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, as a multilayer ceramic capacitor that realizes high withstand voltage, a multilayer ceramic capacitor having a structure in which a plurality of capacitor portions are connected in series, so-called a series structure, is known (see Patent Document 1).

[0003] Since a multilayer ceramic capacitor having a series structure forms a series connection capacitance, its withstand voltage is improved while its capacitance tends to decrease. Therefore, as a countermeasure to maintain the capacitance, means such as increasing the number of internal electrode layers and dielectric layers to be laminated are taken.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the number of internal electrode layers and dielectric layers to be laminated is increased, the internal stress caused by the shrinkage difference between the dielectric layer and the internal electrode layer increases, and as a result, peeling may occur at the interface between the internal electrode layer and the dielectric layer.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor having a series structure that can suppress the occurrence of peeling at the interface between an internal electrode layer and a dielectric layer.

Means for Solving the Problems

[0007] The inventors of the present invention have discovered that by arranging electrodes at predetermined locations in the laminate constituting a multilayer ceramic capacitor, the occurrence of delamination at the interface between the internal electrode layer and the dielectric layer can be suppressed, and have completed the present invention.

[0008] In other words, the present invention provides a laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, the laminate having two main surfaces facing each other in the stacking direction, two side surfaces facing each other in the width direction perpendicular to the stacking direction, and two end surfaces, a first end surface and a second end surface, facing each other in the length direction perpendicular to the stacking direction and the width direction. A first external electrode positioned on the first end face, A multilayer ceramic capacitor having a second external electrode disposed on the second end face, The plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer. The first internal electrode layer has a first pull-out portion, one end of which is pulled out to the first end face and connected to the first external electrode, and a first opposing portion connected to the first pull-out portion and facing an internal electrode layer arranged adjacent to it in the stacking direction. The second internal electrode layer has a second pull-out portion, one end of which is pulled out to the second end face and connected to the second external electrode, and a second opposing portion connected to the second pull-out portion and facing an internal electrode layer arranged adjacent to it in the stacking direction. The intermediate electrode layer is not connected to either the first or second external electrode, and is an internal electrode layer that forms a series-connected capacitor element together with the first and second internal electrode layers. In a dielectric region formed by the dielectric layer sandwiched between the first internal electrode layer or the second internal electrode layer in the stacking direction, a first floating island electrode is provided in the region between the end face of the laminate and the intermediate electrode layer. This is a multilayer ceramic capacitor having a second floating island electrode in the region between the side surface of the laminate and the internal electrode layer. [Effects of the Invention]

[0009] According to the present invention, in a so-called series-structure multilayer ceramic capacitor, it is possible to reduce intrinsic stress caused by the difference in shrinkage between the dielectric layer and the internal electrodes, and to suppress delamination at the interface between the dielectric layer and the internal electrodes. [Brief explanation of the drawing]

[0010] [Figure 1] This is an external perspective view of a double-gang multilayer ceramic capacitor according to the first embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1, illustrating the schematic configuration of a double-layered laminate according to the first embodiment. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 2. [Figure 4A] Figure 2 is an IVA-IVA cross-sectional view, which is a cross-sectional view along the first internal electrode layer and the second internal electrode layer. [Figure 4B] Figure 2 shows a cross-sectional view of the IVB-IVB section, which is a cross-sectional view along the intermediate electrode layer. [Figure 5] This figure illustrates the schematic configuration of a triple-layered laminate according to the second embodiment, and corresponds to Figure 2 in the first embodiment. [Figure 6] This figure illustrates the schematic configuration of a four-section laminate according to the third embodiment, and corresponds to Figure 2 in the first embodiment. [Modes for carrying out the invention]

[0011] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto.

[0012] <First Embodiment> A multilayer ceramic capacitor 1 as a double-gang multilayer ceramic electronic component according to the first embodiment of this disclosure will be described with reference to the drawings. The multilayer ceramic capacitor 1 of this embodiment has a small rate of change in capacitance due to temperature changes and is a temperature-compensating capacitor used for filters, high-frequency circuit matching, etc. However, the multilayer ceramic capacitor 1 of this disclosure is not limited to this. Figure 1 is an external perspective view of the double-gang multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 is a cross-sectional view taken along line II-II of Figure 1, which illustrates the schematic configuration of the double-gang multilayer according to the first embodiment. Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4A is a cross-sectional view taken along line IVA-IVA of Figure 2, which is a cross-sectional view along the first internal electrode layer and the second internal electrode layer. Figure 4B is a cross-sectional view taken along line IVB-IVB of Figure 2, which is a cross-sectional view along the intermediate electrode layer.

[0013] Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of the dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. In addition, components described in the specification may be omitted in the drawings, or their number may be omitted. For example, the number of internal electrode layers described in Figures 2 and 3 is 7 for the sake of explanation, but this does not represent the actual number of internal electrode layers 30. The same applies to Figure 6. Furthermore, the terms used in this invention to specify shapes, geometric conditions, and their degree, such as terms like "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, should not be interpreted strictly, but rather to include a range that allows for the expectation of similar functionality.

[0014] As shown in Figure 1, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0015] In FIG. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and the height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10 that is orthogonal to the stacking direction T. In FIG. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10 that is orthogonal to the stacking direction T and the length direction L. The pair of external electrodes 40 are respectively arranged at one end and the other end of the length direction L of the laminate 10.

[0016] In FIGS. 1 to 4B, an XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as the LW cross sections.

[0017] As shown in FIGS. 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in the length direction L orthogonal to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in the width direction W orthogonal to the stacking direction T and the length direction L. When there is no need to particularly distinguish and explain between the first main surface TS1 and the second main surface TS2, they are collectively referred to as the main surface TS. When there is no need to particularly distinguish and explain between the first end surface LS1 and the second end surface LS2, they are collectively referred to as the end surface LS. When there is no need to particularly distinguish and explain between the first side surface WS1 and the second side surface WS2, they are collectively referred to as the side surface WS for explanation.

[0018] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are where three faces of the laminate intersect, and the edges are where two faces intersect. Furthermore, some or all of the surfaces constituting the laminate 10 may have irregularities or other features.

[0019] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the width W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0020] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 that are arranged to sandwich the inner layer 11 in the lamination direction T.

[0021] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 that are alternately stacked in the stacking direction T. The inner layer 11 includes the internal electrode layer 30 located on the side of the first main surface TS1 to the internal electrode layer 30 located on the side of the second main surface TS2 in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0022] Multiple dielectric layers 20 are composed of dielectric materials. The multilayer ceramic capacitor 1 according to this embodiment is a temperature-compensated capacitor as described above, and the dielectric material is a CaZrO3-based (hereinafter sometimes abbreviated as CZ-based) or (Ca,Sr,Ba)(Zr,Ti)O3-based (hereinafter sometimes abbreviated as CSZ-based) dielectric material. The CZ-based and CSZ-based dielectric materials contain a perovskite-type compound containing at least Ca and Zr. The dielectric material contains at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). As an example, the dielectric layer 20 contains a perovskite-type compound containing Ca and Zr, as well as optionally containing Sr and Ti. Specifically, the dielectric layer 20 contains CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), etc. Normally, multilayer ceramic capacitors 1 generate oxygen vacancies when fired in a reducing atmosphere, but CaZrO3, in particular, can suppress the generation of oxygen vacancies due to its high band gap. As a result, high reliability can be obtained. Furthermore, the dielectric material may be made by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0023] The dielectric layer 20 of this embodiment uses a material containing at least one of Ca (calcium), Zr (zirconium), and Ti (titanium), and therefore has a relative permittivity of about 20 to 300, resulting in a smaller capacitance than high-dielectric-constant systems. Furthermore, the dielectric layer 14 of this embodiment has the characteristic that its relative permittivity changes almost linearly with temperature, resulting in excellent heat resistance and high-frequency characteristics. Moreover, the dielectric layer 14 of this embodiment exhibits a negligibly small change in capacitance over time, resulting in low capacitor loss and excellent stability even at high temperatures, high power, and high frequencies. In addition, the dielectric layer 20 exhibits small changes in dielectric constant over time and changes due to applied voltage. Note that the dielectric material is not limited to this, and may also be a high-dielectric-constant ceramic such as BaTiO3 (BT) system.

[0024] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. In particular, the thickness of the dielectric layer 20 is preferably 3 μm or more and 10 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0025] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31, a plurality of second internal electrode layers 32, and an intermediate electrode layer 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other with a distance between them in the length direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layer 33 are arranged alternately in the stacking direction T with a dielectric layer 20 in between.

[0026] The first internal electrode layer 31 is led out to the first end face LS1 and connected to the first external electrode 40A, which will be described later. The second internal electrode layer 32 is led out to the second end face LS2 and connected to the second external electrode 40B, which will be described later. The intermediate electrode layer 33 is not led out to either the first end face LS1 or the second end face LS2, and is not connected to either the first external electrode 40A or the second external electrode 40B, which will be described later. The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32, which are included in the multiple internal electrode layers 30, form a series-connected capacitor element. In the following, when it is not necessary to explain the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 separately, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0027] As shown in Figures 2 and 4A, the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region facing the intermediate electrode layer 33, which is arranged adjacent to the dielectric layer 20 in the stacking direction T, and is located inside the laminate 10. The first internal electrode layer 31 has a first opposing portion EA that is connected to the first lead portion D1 and faces the internal electrode layer 30, which is arranged adjacent to the stacking direction T. The first lead portion D1 is a portion that is drawn out from the first opposing portion EA to the first end face LS1 and is exposed to the first end face LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is drawn out to the first end face LS1 and connected to the first external electrode 40A.

[0028] As shown in Figures 2 and 4A, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region facing the intermediate electrode layer 33, which is arranged adjacent to the dielectric layer 20 in the stacking direction T, and is located inside the laminate 10. The second internal electrode layer 32 has a second opposing portion EB that is connected to the second lead portion D2 and faces the internal electrode layer 30, which is arranged adjacent to the stacking direction T. The second lead portion D2 is a portion that is drawn out from the second opposing portion EB to the second end face LS2 and is exposed to the second end face LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is drawn out to the second end face LS2 and connected to the second external electrode 40B.

[0029] As shown in Figures 2 and 4B, the intermediate electrode layer 33 has a first electrode layer-side opposing portion ECA, a second electrode layer-side opposing portion ECB, and a connecting portion E0. The first electrode layer-side opposing portion ECA is a region facing the first internal electrode layer 31, which is arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 in between, and is located inside the laminate 10. The second electrode layer-side opposing portion ECB is a region facing the second internal electrode layer 32, which is arranged adjacent to the second internal electrode layer 32 in the stacking direction T with the dielectric layer 20 in between, and is located inside the laminate 10. The connecting portion E0 is a portion that connects the first electrode layer-side opposing portion ECA and the second electrode layer-side opposing portion ECB, and is located between the first electrode layer-side opposing portion ECA and the second electrode layer-side opposing portion ECB.

[0030] In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is positioned spaced apart from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is positioned closer to the first end face LS1 than the end 40AE of the first external electrode 40A. However, it is not limited to this, and the end of the intermediate electrode layer 33 on the first end face LS1 side may be positioned closer to the second end face LS2 side than the end 40AE of the first external electrode 40A.

[0031] The end of the intermediate electrode layer 33 on the second end face LS2 side is positioned spaced apart from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the second end face LS2 side is positioned closer to the second end face LS2 than the end 40BE of the second external electrode 40B. However, it is not limited to this, and the end of the intermediate electrode layer 33 on the second end face LS2 side may be positioned closer to the first end face LS1 than the end 40BE of the second external electrode 40B.

[0032] As shown in Figure 2, in the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 and the intermediate electrode layer 33 are stacked alternately on top of each other via the dielectric layer 20.

[0033] In this embodiment, a capacitance CAP1 (first capacitor portion CAP1) is formed when the first opposing portion EA and the first electrode layer side opposing portion ECA face each other via the dielectric layer 20. A capacitance CAP2 (second capacitor portion CAP2) is formed when the second opposing portion EB and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33, which includes the first electrode layer side opposing portion ECA, face each other via the dielectric layer 20. The connecting portion E0 connects capacitance CAP1 and capacitance CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called double-gang series structure, in which two capacitor portions are formed in series.

[0034] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or formed at an angle. The shapes of the first extension portion D1 and the second extension portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0035] The widthwise dimension W of the first opposing portion EA and the widthwise dimension W of the first extension portion D1 may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion EB and the widthwise dimension W of the second extension portion D2 may be the same, or one of them may be narrower. The widthwise dimension W of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the widthwise dimension W of the connecting portion E0 may be the same, or one of them may be smaller.

[0036] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be made of, for example, an Ag-Pd alloy.

[0037] The thickness of each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably 15 or more and 1000 or less.

[0038] As shown in Figures 2 and 3, the first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0039] The laminate 10 has a series capacitor forming section 11E. The series capacitor forming section 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 face each other (the portion that forms capacitance CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 face each other (the portion that forms capacitance CAP2), and a portion that connects capacitance CAP1 and capacitance CAP2 in series. The series capacitor forming section 11E is configured as part of the inner layer 11. Figures 4A and 4B show the width direction W and length direction L range of the series capacitor forming section 11E. Of the series capacitor forming section 11E, the portion that forms capacitance CAP1 (first capacitor section CAP1) and the portion that forms capacitance CAP2 (second capacitor section CAP2) are also called the effective capacitor portion.

[0040] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the series capacitor forming portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the series capacitor forming portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called the W gap or side gap.

[0041] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion located between the series capacitor forming portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion D1. That is, the first end-face outer layer LG1 is an assembly of the portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first lead portions D1. The second end-face outer layer LG2 is a portion located between the series capacitor forming portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion D2. That is, the second end-face outer layer LG2 is an assembly of the portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second lead portions D2. Figures 2, 4A, and 4B show the longitudinal range L of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap. The series capacitor forming portion 11E of the laminate 10 has a series connection region. The series connection region is the portion that includes the dielectric layer 20 and the connecting portion E0, located between the portion that forms capacitance CAP1 and the portion that forms capacitance CAP2. In other words, the series connection region is an aggregate of the central portion in the longitudinal direction L of multiple dielectric layers 20 and multiple connecting portions E0. The series connection region is also called the intermediate gap.

[0042] As shown in Figures 2, 3, and 4B, the multilayer ceramic capacitor 1 has a first floating island electrode FE1 in the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 in a dielectric region DA formed by a dielectric layer 20 sandwiched between a first internal electrode layer 31 or a second internal electrode layer 32 in the stacking direction T. Here, the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 refers to the area in which the first floating island electrode FE1 does not come into contact with either the end face LS of the laminate 10 or the intermediate electrode layer 33. In other words, the multilayer ceramic capacitor 1 has a first floating island electrode FE1 that is not connected to either the first external electrode 40A or the second external electrode 40B in a first dielectric region DA1 formed by a dielectric layer 20 sandwiched between the first internal electrode layer 31 in the stacking direction T of the first end face outer layer portion LG1, in the region between the first end face LS1 and the intermediate electrode layer 33, and in a second dielectric region DA2 formed by a dielectric layer 20 sandwiched between the second internal electrode layer 32 in the stacking direction T of the second end face outer layer portion LG2, in the region between the second end face LS2 and the intermediate electrode layer 33. The first floating island electrode FE1 consists of multiple scattered small electrode pieces (metal pieces), and can be confirmed as a discontinuous group of electrodes when observing any of the LT, WT, or LW cross-sections of the multilayer ceramic capacitor 1 using a scanning electron microscope or metallurgical microscope.

[0043] By arranging the first floating island electrode FE1 in the region between the first end face LS1 and the intermediate electrode layer 33 in the first dielectric region DA1, and in the region between the second end face LS2 and the intermediate electrode layer 33 in the second dielectric region DA2, the proportion of dielectric material in the outer layer portion on the end face side can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the length direction L.

[0044] Furthermore, the first floating island electrode FE1 does not necessarily need to be placed in both the first dielectric region DA1 and the second dielectric region DA2; it may be placed in either the first dielectric region DA1 or the second dielectric region DA2. Alternatively, the first floating island electrode FE1 may be placed alternately in the first dielectric region DA1 and the second dielectric region DA2 so as to be staggered in the stacking direction T.

[0045] It is preferable that the ratio A / B of the length dimension A of the first floating island electrode FE1 in the longitudinal direction L and the length dimension B between the end faces LS of the laminate 10 located on both sides of the length L of the first floating island electrode FE1 and the intermediate electrode layer 33 is 0.17 or more and 0.37 or less. Furthermore, it is preferable that the ratio C / D of the dimension C of the first floating island electrode FE1 in the stacking direction T and the dimension D of the intermediate electrode layer 33 aligned with the first floating island electrode layer FE1 in the stacking direction T is 0.4 or more and 1.0 or less. If the A / B ratio is less than 0.17, the stress relaxation effect of the first floating island electrode FE1 decreases. On the other hand, if the A / B ratio exceeds 0.37, the intermediate electrode layer 33 and the external electrode 40 may become electrically connected through the first floating island electrode FE1, potentially causing a short circuit. Furthermore, if the C / D ratio is less than 0.4, the stress relaxation effect of the first floating island electrode FE1 decreases. On the other hand, if the A / B ratio exceeds 1.0, a difference in shrinkage occurs between the dielectric layer 20 and the internal electrode layer 30, and interfacial delamination increases due to the generation of intrinsic stress.

[0046] By setting the ratio A / B of the dimension A in the longitudinal direction L of the first floating island electrode FE1 to the lengthwise dimension B between the end faces LS of the laminate 10 located on both sides of the lengthwise direction L of the first floating island electrode FE1 and the intermediate electrode layer 33 to 0.17 or more and 0.37 or less, and setting the ratio C / D of the dimension C in the stacking direction T of the first floating island electrode FE1 to the dimension D in the stacking direction T of the intermediate electrode layer 33 aligned with the first floating island electrode FE1 in the lengthwise direction L, the intrinsic stress caused by the difference in shrinkage between the dielectric layer and the internal electrode can be further reduced, especially in the lengthwise direction L where the effect of the difference in shrinkage is large, and interfacial delamination between the dielectric and the internal electrode can be suppressed.

[0047] Furthermore, the multilayer ceramic capacitor 1 has a second floating island electrode FE2 in the region between the side surface WS of the laminate 10 and the internal electrode layer 30, which is not connected to either the first external electrode 40A or the second external electrode 40B. Here, the region between the side surface WS of the laminate 10 and the internal electrode layer 30 refers to the area in which the second floating island electrode FE2 does not come into contact with either the side surface WS of the laminate 10 or the internal electrode layer 30. Specifically, the second floating island electrode FE2 is positioned in the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. By forming the second floating island electrode FE2 in the dielectric region formed by the dielectric layer between the two opposing side surfaces WS of the laminate 10 and the internal electrode layer 30 in the width direction W, the proportion of dielectric material in the outer layer portion of the side surface can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the width direction W. The second floating island electrode FE2 consists of multiple scattered small electrode pieces (metal pieces), and can be confirmed as a discontinuous group of electrodes when observing any of the LT, WT, or LW cross-sections of the multilayer ceramic capacitor 1 using a scanning electron microscope or metallurgical microscope.

[0048] Furthermore, the second floating island electrode FE2 does not necessarily need to be placed in all of the regions between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. It may be placed in any of the regions between the first side surface or the second side surface and the first internal electrode layer or the second internal electrode layer, i.e., the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. Furthermore, the elements may be arranged in a regular or random manner along the stacking direction T, with their positions changing within the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32.

[0049] As shown in Figures 1 and 2, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0050] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0051] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the first lead-out portion D1 of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple first internal electrode layers 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0052] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the second lead-out portion D2 of each of the multiple second internal electrode layers 32 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple second internal electrode layers 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0053] As described above, within the laminate 10, the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB of the second internal electrode layer 32 and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion CAP2).

[0054] The connecting section E0 connects capacitance CAP1 and capacitance CAP2 in series. As a result, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0055] As shown in Figures 2 to 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0056] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the first lead-out portion D1 of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0057] The second base electrode layer 50B is positioned on the second end face LS2. The second base electrode layer 50B is in contact with the second lead-out portion D2 of each of the multiple second internal electrode layers 32 that are exposed on the second end face LS2. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0058] The first base electrode layer 50A and the second base electrode layer 50B each include at least one selected from a baked layer, a thin film layer, and the like.

[0059] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component includes, for example, at least one selected from CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), or titanium oxide (TiO2), etc.

[0060] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by simultaneously baking the laminated chip, which is the material for the laminate 10 having multiple internal electrode layers and dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, it may be formed by baking the laminated chip to obtain the laminate 10, and then applying the conductive paste to the laminate 10 and baking it. In the above configuration, it is preferable to bake a ceramic material added instead of the glass component. In that case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0061] The thickness of the first base electrode layer 50A located on the first end face LS1, corresponding to the length L, is preferably, for example, 3 μm to 200 μm, in the central part of the first base electrode layer 50A in the lamination direction T and width direction W.

[0062] The thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length L, is preferably, for example, 3 μm to 200 μm in the central part of the second base electrode layer 50B in the lamination direction T and width direction W.

[0063] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 25 μm, at the center of the length L and width W of the first base electrode layer 50A provided in this portion.

[0064] If the first base electrode layer 50A is also provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 25 μm, at the center of the first base electrode layer 50A provided in this portion, in the length direction L and the lamination direction T.

[0065] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 25 μm, at the center of the second base electrode layer 50B in the length direction L and width direction W.

[0066] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 25 μm, at the center of the second base electrode layer 50B provided in this portion, in the length direction L and the lamination direction T.

[0067] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers. A thin film layer is a layer on which metal particles are deposited.

[0068] When the first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, it is preferable that they be formed by a thin film formation method such as sputtering or vapor deposition. Here, we will describe a sputtered electrode formed by the sputtering method.

[0069] The first base electrode layer 50A in this embodiment may be composed of a first thin film layer formed by a sputtering electrode. The second base electrode layer 50B may be composed of a second thin film layer formed by a sputtering electrode. When forming the base electrode layer with a sputtering electrode, it is preferable to directly form the sputtering electrode on a part of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10. The first thin film layer formed by the sputtering electrode is located on a part of the first side surface WS1 on the first main surface TS1. The second thin film layer formed by the sputtering electrode is located on a part of the second side surface WS2 on the first main surface TS1.

[0070] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesion force of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or formed by multiple layers. For example, it may be formed by a two-layer structure consisting of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0071] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0072] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0073] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0074] In this embodiment, the first plating layer 60A comprises a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0075] In this embodiment, the second plating layer 60B comprises a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0076] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably between 2 μm and 10 μm.

[0077] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer or cover a part of the baking layer.

[0078] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0079] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. For example, the conductive particles are Ag metal powder. Ag is suitable as an electrode material because it has the lowest resistivity among metals. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0080] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0081] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0082] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0083] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0084] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0085] The conductive resin layer may be formed from multiple layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0086] Furthermore, the first plating layer 60A and the second plating layer 60B may be directly placed on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B. In other words, the multilayer ceramic capacitor 1 may include a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0087] In this case as well, it is preferable that the plating layer consists of multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. For example, if the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may consist only of the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or other plating layers may be formed on the surface of the upper plating layer.

[0088] The thickness of each plating layer, when placed without an undercoat electrode layer, is preferably 2 μm to 10 μm. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0089] Furthermore, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, by reducing the thickness of the base electrode layer, the dimensions of the multilayer ceramic capacitor 1 in the stacking direction T can be reduced, thereby making the multilayer ceramic capacitor 1 lower profile. Alternatively, by reducing the thickness of the base electrode layer, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 can be increased, thereby improving the overall thickness. In this way, by forming the plating layer directly on the laminate 10, the design flexibility of the multilayer ceramic capacitor can be improved.

[0090] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Furthermore, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Also, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0091] <Examples> (Peel test) Using an ultrasonic flaw detection device, 20kHz ultrasound is irradiated onto the sample, and cracks and delamination inside the chip are detected from the difference between the incident wave and the reflected wave. Here, the delamination time at the interface between the dielectric layer and the internal electrode layer, and the time for complete delamination at the interface, were evaluated using the following method. • Polish the tip to expose the internal electrode layer. Clean the exposed surface of the internal electrode layer with a mixed solution mainly composed of ethanol. • Hold the laminated chip with tweezers and secure the tweezers to the stand. Connect the negative terminal power cord of the DC power supply to the top of the tweezers. Then, adjust the position of the stand so that a portion of the laminated chip held by the tweezers is immersed in the sodium hydroxide solution in the petri dish. Immerse one end of the Pt wire, which is connected to the positive terminal power cord of a DC power supply, into the sodium hydroxide solution in a petri dish. A DC power supply is used to apply a 5V voltage to the power cord, and an ultrasonic flaw detection device is used to check for crack formation every minute. The time from when the 5V voltage is first applied until the first interface delamination is confirmed is defined as the interface delamination time. The time from when the 5V voltage is first applied until it is confirmed that the entire interface has been delaminated is defined as the complete interface delamination time.

[0092] (sample) • Multilayer ceramic capacitor dimensions: 3.4mm (L) x 2.7mm (W) x 2.7mm (T) • Rated voltage: 1000V • Dielectric layer: CaZrO3 (Thickness of dielectric layer: 3.96 μm) • Internal electrode layer: Ni (Intermediate electrode layer thickness: 0.82 μm (target value), length L dimension of the outer layer on the end face side: 200 μm (target value)) • First floating island electrode: Present (Example), Absent (Comparative Example) • Second floating island electrode: Present (Example), Absent (Comparative Example) • Laminate structure: Double-layered structure

[0093] (Criteria for evaluating peel test) The criteria for the peel test were as follows: a total interface peel time of 40 minutes or more was marked as ○ (pass), 30 minutes or more but less than 40 minutes was marked as △ (acceptable pass), and less than 30 minutes was marked as × (fail).

[0094] (Short evaluation test) The test involved applying a 1000V DC current to 1000 samples for 60 seconds, followed by measurement of their resistance. Samples with a resistance of 1000Ω or less were identified as having experienced a short circuit.

[0095] (Criteria for short-term evaluation) The criteria for evaluating short circuits were as follows: out of 100 samples, 0 samples with short circuits were rated as ○ (pass), 1 to 5 samples as △ (acceptable pass), and 6 or more samples as × (fail).

[0096] (Dimensional measurement of the intermediate electrode layer and the first floating island electrode) The dimensions of the intermediate electrode layer 33 and the first floating island electrode FE1 can be measured by the following method. First, the cross-section of the multilayer ceramic capacitor 1 is exposed. Specifically, polishing is performed up to the center of the width W of the multilayer ceramic capacitor 1. Next, a scanning electron microscope (SEM) is used to observe the polished cross-section under the conditions of acceleration voltage: 15kV and magnification: 2000x, and the dimensions of each electrode are measured by applying binarization.

[0097] [Table 1]

[0098] It was confirmed that the presence of floating island electrodes resulted in the entire interface delamination time being within the acceptable or permissible range, leading to favorable results. Furthermore, as shown in Table 1, it was confirmed that particularly good results were obtained when the ratio A / B of the dimension A in the longitudinal direction L of the first floating island electrode FE1 and the dimension B in the longitudinal direction between the end faces LS of the laminate 10 located on both sides of the longitudinal direction L of the first floating island electrode FE1 and the intermediate electrode layer 33 was 0.17 or more and 0.37 or less, and when the ratio C / D of the dimension C in the stacking direction T of the first floating island electrode FE1 and the dimension D in the stacking direction T of the intermediate electrode layer 33 aligned with the first floating island electrode FE1 in the longitudinal direction L was 0.4 or more and 1.0 or less.

[0099] <Manufacturing method> Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0100] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known.

[0101] A conductive paste for the internal electrode layers, which forms the first internal electrode layer 31 and the second internal electrode layer 32 on the dielectric sheet, is printed in a predetermined pattern, for example, by screen printing or gravure printing. Furthermore, a conductive paste for the floating island electrode, which forms the second floating island electrode FE2, is printed. This creates a dielectric sheet in which the arrangement of the internal electrode layer 30 and the second floating island electrode shown in Figure 4A forms a single pattern, and this pattern is continuous in the length direction L and the width direction W. Furthermore, the printing of the conductive paste for the floating island electrode to form the second floating island electrode FE2 may be performed before or simultaneously with the printing of the conductive paste for the internal electrode layer to form the first internal electrode layer 31 and the second internal electrode layer 32.

[0102] Furthermore, a conductive paste for the intermediate electrode layer 33 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. In addition, a conductive paste for the floating island electrode is printed to form the first floating island electrode FE1. This creates a dielectric sheet in which the arrangement of the intermediate electrode layer 33 and the first floating island electrode FE1 shown in Figure 4B forms a single pattern, and this pattern is continuous in the length direction L and the width direction W. Furthermore, the printing of the conductive paste for the floating island electrode to form the first floating island electrode FE1 may be performed before or simultaneously with the printing of the conductive paste for the intermediate electrode layer to form the intermediate electrode layer 33. Furthermore, the conductive paste for the floating island electrodes may be printed by screen printing using a discrete pattern mesh.

[0103] Dielectric sheets printed with conductive paste to form the first internal electrode layer 31, the second internal electrode layer 32, and the second floating island electrode FE2 are alternately stacked with dielectric sheets printed with conductive paste to form the intermediate electrode layer 33 and the first floating island electrode FE1. A predetermined number of dielectric sheets without conductive paste are stacked so as to sandwich the stacked sheets from above and below. The dielectric sheets without conductive paste form the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0104] Laminated sheets are pressed in the height direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0105] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0106] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0107] A conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 10.

[0108] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. Subsequently, a baking process is performed to form the base electrode layer. The temperature of this baking process is preferably 700°C to 900°C.

[0109] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0110] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating treatment, either electrolytic plating or electroless plating may be used.

[0111] However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with catalysts or other means to improve the plating deposition rate. Therefore, electroplating is usually preferable. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0112] Furthermore, when a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be positioned to cover the baking layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied onto the baking layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. In addition, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0113] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0114] The present invention is not limited to a dual-gang multilayer ceramic capacitor 1, but can be broadly applied to multilayer ceramic capacitors having a series structure.

[0115] <Second Embodiment> The multilayer ceramic capacitor 1 according to the second embodiment is a triple-gang multilayer ceramic capacitor. The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to Figure 5. In the following description, detailed explanations of the same configuration as in the first embodiment may be omitted. Figure 5 is a diagram for illustrating the schematic configuration of the triple-gang multilayer body according to the second embodiment, and corresponds to Figure 2 in the first embodiment. The manufacturing method of the second embodiment is the same as in the first embodiment, and will not be described.

[0116] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductive layers, multiple second internal electrode layers 32 as multiple second internal conductive layers, and an intermediate electrode layer 33.

[0117] As shown in Figure 5, the intermediate electrode layer 33 according to the second embodiment includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.

[0118] The first intermediate electrode layer 331 has a first electrode layer-side opposing portion EC1A, a first intermediate electrode layer-side opposing portion EC1B, and a first connecting portion E10. The first electrode layer-side opposing portion EC1A is a region facing the first internal electrode layer 31 which is arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first intermediate electrode layer-side opposing portion EC1B is a region facing the second intermediate electrode layer 332 which is arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first connecting portion E10 is a portion that connects the first electrode layer-side opposing portion EC1A and the first intermediate electrode layer-side opposing portion EC1B, and is located between the first electrode layer-side opposing portion EC1A and the first intermediate electrode layer-side opposing portion EC1B.

[0119] The second intermediate electrode layer 332 has a second electrode layer-side opposing portion EC2A, a second intermediate electrode layer-side opposing portion EC2B, and a second connecting portion E20. The second electrode layer-side opposing portion EC2A faces the second internal electrode layer 32 which is arranged adjacent to it in the stacking direction T. The second intermediate electrode layer-side opposing portion EC2B faces the first intermediate electrode layer 331 which is arranged adjacent to it in the stacking direction T. The second connecting portion E20 is a portion that connects the second electrode layer-side opposing portion EC2A and the second intermediate electrode layer-side opposing portion EC2B, and is arranged between the second electrode layer-side opposing portion EC2A and the second intermediate electrode layer-side opposing portion EC2B.

[0120] As shown in Figure 5, in the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the second embodiment, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the length direction L.

[0121] In the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332, and the second internal electrode layer 32 and the first intermediate electrode layer 331 are stacked alternately on top of each other via the dielectric layer 20.

[0122] In this embodiment, capacitance CAP1 (first capacitor portion CAP1) is formed when the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20. Capacitance CAP2 (second capacitor portion CAP2) is formed when the second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer. Capacitance CAP3 (third capacitor portion CAP3) is formed when the first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B face each other via the dielectric layer 20. The first connecting portion E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connecting portion E20 connects capacitance CAP2 and capacitance CAP3 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called triple series structure, in which three capacitor portions are formed in series.

[0123] The laminate 10 has a series capacitor forming section 11E. The series capacitor forming section 11E includes a portion for forming capacitance CAP1, a portion for forming capacitance CAP2, a portion for forming capacitance CAP3, a portion for connecting capacitance CAP1 and capacitance CAP3 in series, and a portion for connecting capacitance CAP2 and capacitance CAP3 in series. The series capacitor forming section 11E is configured as part of the inner layer 11. Of the series capacitor forming section 11E, the portion for forming capacitance CAP1 (first capacitor section CAP1), the portion for forming capacitance CAP2 (second capacitor section CAP2), and the portion for forming capacitance CAP3 (third capacitor section CAP3) are also called the effective capacitor section.

[0124] The series capacitor forming portion 11E of the laminate 10 has a first series connection region and a second series connection region. The first series connection region is a portion that includes the dielectric layer 20 and the first connecting portion E10, located between the portion that forms capacitance CAP1 and the portion that forms capacitance CAP3. The second series connection region is a portion that includes the dielectric layer 20 and the second connecting portion E20, located between the portion that forms capacitance CAP2 and the portion that forms capacitance CAP3. That is, the first series connection region is an aggregate of the portion of the plurality of dielectric layers 20 that overlaps with the first connecting portion E10 when viewed from the stacking direction T, and the plurality of first connecting portions E10. The second series connection region is an aggregate of the portion of the plurality of dielectric layers 20 that overlaps with the second connecting portion E20 when viewed from the stacking direction T, and the plurality of second connecting portions E20.

[0125] As shown in Figure 5, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10 and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0126] The first connection section E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connection section E20 connects capacitance CAP2 and capacitance CAP3 in series. As a result, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0127] The multilayer ceramic capacitor 1 has a first floating island electrode FE1 in the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 in a dielectric region DA formed by a dielectric layer 20 sandwiched between a first internal electrode layer 31 or a second internal electrode layer 32 in the stacking direction T. Here, the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 refers to the area in which the first floating island electrode FE1 does not come into contact with either the end face LS of the laminate 10 or the intermediate electrode layer 33. In other words, the multilayer ceramic capacitor 1 has a first floating island electrode FE1 that is not connected to either the first external electrode 40A or the second external electrode 40B in a first dielectric region DA1 formed by a dielectric layer 20 sandwiched between the first internal electrode layer 31 in the stacking direction T of the first end face outer layer portion LG1, in the region between the first end face LS1 and the intermediate electrode layer 33, and in a second dielectric region DA2 formed by a dielectric layer 20 sandwiched between the second internal electrode layer 32 in the stacking direction T of the second end face outer layer portion LG2, in the region between the second end face LS2 and the intermediate electrode layer 33.

[0128] By arranging the first floating island electrode FE1 in the region between the first end face LS1 and the intermediate electrode layer 33 in the first dielectric region DA1, and in the region between the second end face LS2 and the intermediate electrode layer 33 in the second dielectric region DA2, the proportion of dielectric material in the outer layer portion on the end face side can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the longitudinal direction L.

[0129] Furthermore, the first floating island electrode FE1 does not necessarily need to be placed in both the first dielectric region DA1 and the second dielectric region DA2; it may be placed in either the first dielectric region DA1 or the second dielectric region DA2. Alternatively, the first floating island electrode FE1 may be placed alternately in the first dielectric region DA1 and the second dielectric region DA2 so as to be staggered in the stacking direction T.

[0130] Furthermore, the multilayer ceramic capacitor 1 has a second floating island electrode FE2 in the region between the side surface WS of the laminate 10 and the internal electrode layer 30, which is not connected to either the first external electrode 40A or the second external electrode 40B. Here, the region between the side surface WS of the laminate 10 and the internal electrode layer 30 refers to the area in which the second floating island electrode FE2 does not come into contact with either the side surface WS of the laminate 10 or the internal electrode layer 30. Specifically, the second floating island electrode FE2 is positioned in the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. By forming the second floating island electrode FE2 in the dielectric region formed by the dielectric layer between the two opposing side surfaces WS of the laminate 10 and the internal electrode layer 30 in the width direction W, the proportion of dielectric material in the outer layer portion of the side surface can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the width direction W.

[0131] Furthermore, the second floating island electrode FE2 does not necessarily need to be placed in all of the regions between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. It may be placed in any of the regions between the first side surface or the second side surface and the first internal electrode layer or the second internal electrode layer, i.e., the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. Furthermore, the elements may be arranged in a regular or random manner along the stacking direction T, with their positions changing within the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32.

[0132] <Third Embodiment> Note that the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a four-gang multilayer ceramic capacitor as shown in Figure 6.

[0133] The multilayer ceramic capacitor 1 according to the third embodiment will be described below with reference to Figure 6. In the following description, detailed explanations of the same configuration as in the first embodiment will be omitted. Furthermore, the manufacturing method of the multilayer ceramic capacitor of the third embodiment is the same as that of the multilayer ceramic capacitor of the first embodiment, and will therefore not be described.

[0134] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layer 30 inside the laminate 10 and the external electrode 40. Specifically, while the multilayer ceramic capacitor 1 of the first embodiment had a double-layer internal electrode layer 30, the multilayer ceramic capacitor 1 of the third embodiment has a quadruple-layer internal electrode layer 30, and the configuration of the internal electrode layer 30 inside the laminate 10 differs from that of the first embodiment.

[0135] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductive layers, multiple second internal electrode layers 32 as multiple second internal conductive layers, and an intermediate electrode layer 33.

[0136] As shown in Figure 6, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333.

[0137] The first intermediate electrode layer 331 has a first electrode layer side facing portion EC1A that faces the first internal electrode layer 31 which is arranged adjacent to it in the stacking direction T, a first intermediate electrode layer facing portion EC1B that faces the third intermediate electrode layer 333 which is arranged adjacent to it in the stacking direction T, and a first connecting portion E10.

[0138] The second intermediate electrode layer 332 has a second electrode layer side facing portion EC2A that faces the second internal electrode layer 32 which is arranged adjacent to it in the stacking direction T, a second intermediate electrode layer facing portion EC2B that faces the third intermediate electrode layer 333 which is arranged adjacent to it in the stacking direction T, and a second connecting portion E20.

[0139] The third intermediate electrode layer 333 has a third intermediate electrode layer facing portion EC3A that faces the first intermediate electrode layer 331 which is arranged adjacent to it in the stacking direction T, a fourth intermediate electrode layer facing portion EC3B that faces the second intermediate electrode layer 332 which is arranged adjacent to it in the stacking direction T, and a third connecting portion E30.

[0140] As shown in Figure 6, in the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the third embodiment, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L.

[0141] In the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32, and the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are stacked alternately on top of each other via a dielectric layer 20.

[0142] In this embodiment, capacitance CAP1 (first capacitor portion CAP1) is formed when the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20. Capacitance CAP2 (second capacitor portion CAP2) is formed when the second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer 20. Capacitance CAP3 (third capacitor portion CAP3) is formed when the first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A face each other via the dielectric layer 20. Capacitance CAP4 (fourth capacitor portion CAP4) is formed when the second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B face each other via the dielectric layer 20. The first connecting portion E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connecting portion E20 connects capacitance CAP2 and capacitance CAP4 in series. The third connection section E30 connects capacitance CAP3 and capacitance CAP4 in series. The multilayer ceramic capacitor 1 in this embodiment is a so-called 4-gang series structure multilayer ceramic capacitor 1, in which four capacitor sections are formed in series.

[0143] The laminate 10 has a series capacitor forming section 11E. The series capacitor forming section 11E includes a portion for forming capacitance CAP1, a portion for forming capacitance CAP2, a portion for forming capacitance CAP3, a portion for forming capacitance CAP4, a portion for connecting capacitance CAP1 and capacitance CAP3 in series, a portion for connecting capacitance CAP2 and capacitance CAP4 in series, and a portion for connecting capacitance CAP3 and capacitance CAP4 in series. The series capacitor forming section 11E is configured as part of the inner layer 11. Of the series capacitor forming section 11E, the portion for forming capacitance CAP1 (first capacitor section CAP1), the portion for forming capacitance CAP2 (second capacitor section CAP2), the portion for forming capacitance CAP3 (third capacitor section CAP3), and the portion for forming capacitance CAP4 (fourth capacitor section CAP4) are also called the effective capacitor section.

[0144] The series capacitor forming portion 11E of the laminate 10 has a first series connection region, a second series connection region, and a third series connection region. The first series connection region is located between the portion that forms capacitance CAP1 and the portion that forms capacitance CAP3, and includes the dielectric layer 20 and the first connecting portion E10. The second series connection region is located between the portion that forms capacitance CAP2 and the portion that forms capacitance CAP4, and includes the dielectric layer 20 and the second connecting portion E20. The third series connection region is located between the portion that forms capacitance CAP3 and the portion that forms capacitance CAP4, and includes the dielectric layer 20 and the third connecting portion E30. In other words, the first series connection region is an aggregate of the portion of the multiple dielectric layers 20 that overlaps with the first connecting portion E10 when viewed from the stacking direction T, and the multiple first connecting portions E10. The second series connection region is an aggregate of the portion of the multiple dielectric layers 20 that overlaps with the second connecting portion E20 when viewed from the stacking direction T, and the multiple second connecting portions E20. The third series connection region is an aggregate of the portion of the multiple dielectric layers 20 that overlaps with the third connecting portion E30 when viewed from the stacking direction T, and the multiple third connecting portions E30.

[0145] As shown in Figure 6, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10 and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0146] The first connection section E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connection section E20 connects capacitance CAP2 and capacitance CAP4 in series. The third connection section E30 connects capacitance CAP3 and capacitance CAP4 in series. As a result, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0147] Thus, the multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layer 30 inside the laminate 10. Specifically, while the multilayer ceramic capacitor 1 of the first embodiment had a double-layer internal electrode layer 30, the multilayer ceramic capacitor 1 of the third embodiment has a quadruple-layer internal electrode layer 30, and the configuration of the internal electrode layer 30 inside the laminate 10 differs from the first embodiment.

[0148] The multilayer ceramic capacitor 1 has a first floating island electrode FE1 in the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 in a dielectric region DA formed by a dielectric layer 20 sandwiched between a first internal electrode layer 31 or a second internal electrode layer 32 in the stacking direction T. Here, the region between the end face LS of the laminate 10 and the intermediate electrode layer 33 refers to the area in which the first floating island electrode FE1 does not come into contact with either the end face LS of the laminate 10 or the intermediate electrode layer 33. In other words, the multilayer ceramic capacitor 1 has a first floating island electrode FE1 that is not connected to either the first external electrode 40A or the second external electrode 40B in a first dielectric region DA1 formed by a dielectric layer 20 sandwiched between the first internal electrode layer 31 in the stacking direction T of the first end face outer layer portion LG1, in the region between the first end face LS1 and the intermediate electrode layer 33, and in a second dielectric region DA2 formed by a dielectric layer 20 sandwiched between the second internal electrode layer 32 in the stacking direction T of the second end face outer layer portion LG2, in the region between the second end face LS2 and the intermediate electrode layer 33.

[0149] By arranging the first floating island electrode FE1 in the region between the first end face LS1 and the intermediate electrode layer 33 in the first dielectric region DA1, and in the region between the second end face LS2 and the intermediate electrode layer 33 in the second dielectric region DA2, the proportion of dielectric material in the outer layer portion on the end face side can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the length direction L.

[0150] Furthermore, the first floating island electrode FE1 does not necessarily need to be placed in both the first dielectric region DA1 and the second dielectric region DA2; it may be placed in either the first dielectric region DA1 or the second dielectric region DA2. Alternatively, the first floating island electrode FE1 may be placed alternately in the first dielectric region DA1 and the second dielectric region DA2 so as to be staggered in the stacking direction T.

[0151] Furthermore, the multilayer ceramic capacitor 1 has a second floating island electrode FE2 in the region between the side surface WS of the laminate 10 and the internal electrode layer 30, which is not connected to either the first external electrode 40A or the second external electrode 40B. Here, the region between the side surface WS of the laminate 10 and the internal electrode layer 30 refers to the area in which the second floating island electrode FE2 does not come into contact with either the side surface WS of the laminate 10 or the internal electrode layer 30. Specifically, the second floating island electrode FE2 is positioned in the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. By forming the second floating island electrode FE2 in the dielectric region formed by the dielectric layer between the two opposing side surfaces WS of the laminate 10 and the internal electrode layer 30 in the width direction W, the proportion of dielectric material in the outer layer portion of the side surface can be relatively reduced. This reduces the intrinsic stress caused by the difference in shrinkage between the dielectric layer 20 and the internal electrode layer 30 in the width direction W.

[0152] Furthermore, the second floating island electrode FE2 does not necessarily need to be placed in all of the regions between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. It may be placed in any of the regions between the first side surface or the second side surface and the first internal electrode layer or the second internal electrode layer, i.e., the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32. Furthermore, the elements may be arranged in a regular or random manner along the stacking direction T, with their positions changing within the region between the first side surface WS1 and the first internal electrode layer 31, the region between the first side surface WS1 and the second internal electrode layer 32, the region between the second side surface WS2 and the first internal electrode layer 31, and the region between the second side surface WS2 and the second internal electrode layer 32.

[0153] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention. [Explanation of Symbols]

[0154] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 33 Intermediate electrode layer 40A First external electrode 40B Second external electrode D1 First drawer section D2 Second drawer section DA Dielectric Region DA1 First dielectric region DA2 Second dielectric region EA First opposing part EB Second opposing part FE1 First floating island electrode FE2 Second floating island electrode L (Length direction) LS end face LS1 First end face LS2 Second end face T Stacking direction TS Main Surface TS1 First main surface TS2 Second main surface W (width direction) WS side WS1 First Aspect WS2 Second Aspect

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, having two main surfaces facing each other in the stacking direction, two side surfaces facing each other in the width direction perpendicular to the stacking direction, and two end surfaces, a first end surface and a second end surface, facing each other in the length direction perpendicular to the stacking direction and the width direction, A first external electrode disposed on the first end face, A multilayer ceramic capacitor having a second external electrode disposed on the second end face, The plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer. The first internal electrode layer has a first pull-out portion, one end of which is pulled out to the first end face and connected to the first external electrode, and a first opposing portion connected to the first pull-out portion and facing an internal electrode layer arranged adjacent to it in the stacking direction. The second internal electrode layer has a second pull-out portion, one end of which is pulled out to the second end face and connected to the second external electrode, and a second opposing portion connected to the second pull-out portion and facing an internal electrode layer arranged adjacent to it in the stacking direction. The intermediate electrode layer is not connected to either the first or second external electrode, and is an internal electrode layer that forms a series-connected capacitor element together with the first and second internal electrode layers. In a dielectric region formed by the dielectric layer sandwiched between the first internal electrode layer or the second internal electrode layer in the stacking direction, a first floating island electrode is provided in the region between the end face of the laminate and the intermediate electrode layer. A multilayer ceramic capacitor having a second floating island electrode in the region between the side surface of the laminate and the internal electrode layer.

2. The intermediate electrode layer has a first electrode layer side facing portion that faces the first internal electrode layer which is arranged adjacent to it in the stacking direction, and a second electrode layer side facing portion that faces the second internal electrode layer which is arranged adjacent to it in the stacking direction. The first opposing portion of the first internal electrode layer faces the intermediate electrode layer, which is an internal electrode layer arranged adjacent to it in the stacking direction. The multilayer ceramic capacitor according to claim 1, wherein the second opposing portion of the second internal electrode layer faces the intermediate electrode layer, which is an internal electrode layer arranged adjacent to it in the stacking direction.

3. The intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer. The first intermediate electrode layer has a first electrode layer-side facing portion that faces the first internal electrode layer which is arranged adjacent to it in the stacking direction, and a first intermediate electrode layer-side facing portion that faces the second intermediate electrode layer which is arranged adjacent to it in the stacking direction. The multilayer ceramic capacitor according to claim 1, wherein the second intermediate electrode layer has a second electrode layer-facing portion that faces the second internal electrode layer which is arranged adjacent to it in the stacking direction, and a second intermediate electrode layer-facing portion that faces the first intermediate electrode layer which is arranged adjacent to it in the stacking direction.

4. The intermediate electrode layer includes a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer. The first intermediate electrode layer has a first electrode layer-side facing portion that faces the first internal electrode layer which is arranged adjacent to it in the stacking direction, and a first intermediate electrode layer-side facing portion that faces the third intermediate electrode layer which is arranged adjacent to it in the stacking direction. The second intermediate electrode layer has a second electrode layer-facing portion that faces the second internal electrode layer which is arranged adjacent to it in the stacking direction, and a second intermediate electrode layer-facing portion that faces the third intermediate electrode layer which is arranged adjacent to it in the stacking direction. The multilayer ceramic capacitor according to claim 1, wherein the third intermediate electrode layer has a third intermediate electrode layer facing portion that faces the first intermediate electrode layer which is arranged adjacent to it in the stacking direction, and a fourth intermediate electrode layer facing portion that faces the second intermediate electrode layer which is arranged adjacent to it in the stacking direction.

5. The ratio A / B of the length dimension A of the first floating island electrode to the length dimension B between the end faces of the laminate located on both sides of the length of the first floating island electrode and the intermediate electrode layer is 0.17 or more and 0.37 or less. A multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the ratio C / D of the dimension C of the first floating island electrode in the stacking direction to the dimension D of the intermediate electrode layer aligned longitudinally with the first floating island electrode in the stacking direction is 0.4 or more and 1.0 or less.

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