Trace data acquisition device, integrated circuit, trace data acquisition method, and program

Abstract

When storing CPU operation trace data in memory, it is possible to provide a relatively large amount of trace information while keeping the amount of trace data stored in memory relatively small. [Solution] The trace data acquisition device includes: standard trace data acquisition means for acquiring standard trace data which is trace data of the operation of the CPU and includes data indicating the privileged mode of the CPU; data volume reduction trace data acquisition means for acquiring data volume reduction trace data which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data; transmission means for transmitting the standard trace data; and memory writing means for storing the data volume reduction trace data in memory.

Description

Technical Field

[0001] The present invention relates to a trace data acquisition device, an integrated circuit, a trace data acquisition method, and a program.

Background Art

[0002] Trace data of the operation of a CPU may be stored in a memory. For example, the debug device described in Patent Document 1 stores the value of a program counter and the state of the debug device due to the execution of an instruction in a data memory when an instruction sequence is executed. When this debug device receives a trace data read request, it reads data from the data memory and outputs it.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] From the viewpoint of analyzing the operation of a CPU in more detail, it is preferable to obtain as much information (trace information) as possible from trace data. On the other hand, when storing trace data in a memory with limited capacity, it is preferable that the data amount of the trace data is as small as possible.

[0005] An example of the object of the present disclosure is to provide a trace data acquisition device, an integrated circuit, a trace data acquisition method, and a program that can solve the above-described problems.

Means for Solving the Problems

[0006] According to a first aspect of this disclosure, the trace data acquisition device includes: standard trace data acquisition means for acquiring standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU; data volume reduction trace data acquisition means for acquiring data volume reduction trace data which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data; transmission means for transmitting the standard trace data; and memory writing means for storing the data volume reduction trace data in memory.

[0007] According to a second aspect of the present disclosure, the integrated circuit includes a CPU, standard trace data acquisition means for acquiring standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU, data volume reduction trace data acquisition means for acquiring data volume reduction trace data which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, transmission means for transmitting the standard trace data, and memory writing means for storing the data volume reduction trace data in memory.

[0008] According to a third aspect of this disclosure, a trace data acquisition method includes a trace data acquisition device acquiring standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU; acquiring data-reduced trace data which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data; transmitting the standard trace data; and storing the data-reduced trace data in memory.

[0009] According to a fourth aspect of this disclosure, the program is a program that causes an integrated circuit including a CPU to perform the following actions: acquire standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU; acquire data-reduced trace data which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data; transmit the standard trace data; and store the data-reduced trace data in memory. [Effects of the Invention]

[0010] According to one aspect of this disclosure, a relatively large amount of trace information can be provided, and the amount of trace data to be stored in memory (e.g., the total amount of data for the entire program execution) can be kept relatively small. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example configuration of an on-chip debug circuit according to at least one embodiment. [Figure 2] This figure shows an example of data input and output in an LSI according to at least one embodiment. [Figure 3] This figure shows examples of signal names and contents used by the Ingress Port in the debugable circuit according to at least one embodiment. [Figure 4] This figure shows an example of a trace message used by an on-chip debugging circuit according to at least one embodiment. [Figure 5] This figure shows an example of sending a trace message in single-step mode according to at least one embodiment. [Figure 6] This figure shows an example of a privileged mode transition in single-step mode according to at least one embodiment. [Figure 7] This figure shows an example of a trace message with privileged mode information removed in single-step mode according to at least one embodiment. [Figure 8] It is a diagram showing an example of the configuration of a trace encoder according to at least one embodiment. [Figure 9] It is a diagram showing an example of input / output of data in a trace encoder according to at least one embodiment. [Figure 10] In at least one embodiment, it is a diagram showing an example when the privilege mode is changed after execution of a plurality of instructions. [Figure 11] It is a diagram showing an example of the configuration of a trace data acquisition device according to at least one embodiment. [Figure 12] It is a diagram showing an example of the configuration of an integrated circuit according to at least one embodiment. [Figure 13] It is a diagram showing an example of a processing procedure in a trace data acquisition method according to at least one embodiment.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0013] <First Embodiment> FIG. 1 is a diagram showing an example of the configuration of an on-chip debug circuit according to at least one embodiment. FIG. 1 shows a debug target circuit 110 and an on-chip debug circuit 130 in an LSI (Large Scale Integration) 100 that is a debug target.

[0014] In the configuration shown in FIG. 1, the debug target circuit 110 includes a CPU (Central Processing Unit) 120. The on-chip debug circuit 130 includes a trace encoder 140 and an internal RAM (Random Access Memory) 150. Here, an example will be given where trace data is used for debugging, such as debugging a program executed by the CPU 120 or debugging the hardware of the CPU. However, the use of trace data in the LSI 100 is not limited to debugging. For example, the trace data may be used for tuning the program, such as improving the speed or optimizing the program executed by the CPU 120.

[0015] Data for tracing the operation of the CPU 120 is also referred to as trace data for the operation of the CPU 120 or simply trace data. The trace data may include data indicating the instructions executed by the CPU 120. Further, the trace data may include data indicating the operation mode of the CPU 120 or data indicating the state of the debug target circuit 110 during the operation of the CPU 120, such as the values of the registers in the debug target circuit 110 during the operation of the CPU 120. The information indicated by the trace data is also referred to as trace information. Also, trace data represented in the form of text (character string) is also referred to as a trace message. The trace message corresponds to an example of the trace data.

[0016] The LSI 100 is an LSI in which the CPU 120 and the on-chip debug circuit 130 are integrated on a single chip. The LSI 100 corresponds to an example of a trace data acquisition device. Also, the LSI 100 corresponds to an example of an integrated circuit (IC).

[0017] The CPU 120 performs various processes by executing a program. The debug target circuit 110 is a part of the LSI 100 that is the target of debugging. The debug target circuit 110 may include peripheral circuits of the CPU 120, such as a memory and an input / output circuit, in addition to the CPU 120. The debug target circuit 110 outputs the trace data to the trace encoder 140.

[0018] The on-chip debug circuit 130 converts the trace data output by the circuit to be debugged 110 into trace messages, outputs them, and records them. The trace encoder 140 converts the trace data output by the circuit under debug 110 into trace messages. Internal RAM 150 stores trace messages.

[0019] Figure 2 shows an example of data input and output in LSI100. The following explanation uses the example where CPU 120 is a CPU based on the RISC-V® architecture, and the debugged circuit 110 outputs trace data, including information about the instructions executed by CPU 120 and the state of the debugged circuit 110, via the Ingress Port.

[0020] The Ingress Port is a CPU trace information output signal defined in the "TG RISC-V Nexus Trace Specification". However, the CPU 120 is not limited to a CPU with a specific instruction set architecture (ISA). Also, the format in which the circuit under debug 110 outputs trace data is not limited to a specific format.

[0021] Figure 3 shows an example of the signal names and contents used by the debug target circuit 110 at the Ingress Port. Figure 3 presents the signal information used by the debug target circuit 110 at the Ingress Port in a table format, with one type of signal information shown per row. The "Signal" column shows the signal name. The "Function" column shows the content of the signal indicated in the "Signal" column. In Figure 3, the labels R11 through R19 are assigned sequentially from the top row.

[0022] "itype" indicates the type of all retired instructions. Instruction retirement, in this context, refers to the operation in which the state of the debugged circuit 110 is updated at the final stage of instruction execution by the CPU. "cause" indicates the cause of the exception or interrupt. "tval" indicates the relevant trap value when an exception or interrupt occurs.

[0023] "priv" indicates the privilege level (privileged mode) of all retired instructions. The privileged mode referred to here is the operating mode of the CPU, which defines the limitations on the operations that the CPU can perform. The privileged mode is also called the CPU mode. RISC-V has privileged modes such as U-mode (User Mode), HS-mode (Hypervisor-extended Supervisor Mode), and M-mode (Machine Mode), as well as a privileged mode for debugging called D-mode (Debug Mode).

[0024] "iaddr" indicates the address of the first retired instruction. "context" indicates the context of all retired instructions. "time" indicates time information. "iretire" indicates the number of retired instructions. "ilastsize" indicates the size of the retired instructions.

[0025] The trace encoder 140 uses the Ingress Port input from the circuit under debug 110 to generate trace messages in a processor branch trace based on the "TG RISC-V Nexus Trace Specification". Processor branch tracing is a method for tracing the branch history of instructions executed by the CPU.

[0026] Processor branch tracing allows the execution flow of a program to be traced by recording the address of the branch destination each time the program branches. Using the trace messages generated by the trace encoder 140, it is possible to reconstruct the history information of the program counter (PC) state, and represent the execution flow of the program by the CPU 120. The on-chip debug circuit 130 outputs trace messages generated by the processor branch trace to the outside and also stores them in the internal RAM 150. Storing data in memory is also referred to as storing data in memory.

[0027] Figure 4 shows an example of trace messages used by the on-chip debug circuit 130. Figure 4 shows the trace message information used by the on-chip debug circuit 130 in a table format, with one type of trace message information shown per row. The Trace Message Name column shows the name of the trace message. The Content column shows the content of the trace message indicated in the Trace Message Name column. In Figure 4, the labels R21 through R27 are assigned sequentially from the top row.

[0028] "Ownership Trace" is used to track context changes. "Program Trace.Direct Branch" shows the program trace when there is a change in the program flow and the target address branches, or when the target address is statically known by a subroutine call instruction.

[0029] "Program Trace.Indirect Branch" shows the program trace when the program flow is modified at runtime by a subroutine call, return instruction, asynchronous interrupt / trap, or indirect instruction. "Program Trace.Indirect Branch" is output each time a target address is determined.

[0030] "Error" indicates the type of error that occurred. If there are multiple clients on the device, "Error" also indicates which client generated the error. "Program Trace.Synchronization" indicates trace information that development tools use to periodically synchronize with the program flow. The development tools here are those that restore and encode the historical state information of trace messages. "Program Trace.Synchronization" is also used during trace development.

[0031] "Program Trace.Rsource Full" is a trace message that notifies the system of trace information to prevent information loss when the internal memory storing trace data becomes full. "Program Trace.Correlation" associates the trace flow with termination.

[0032] The trace encoder 140 reduces the amount of data in trace messages in single-step mode.

[0033] Figure 5 shows an example of trace message transmission in single-step mode. Figure 5 shows an example of trace messages transmitted by the trace encoder 140 to the outside of the LSI 100 in single-step mode, presented in a table format. The trace data output by the debugged circuit 110 to the trace encoder 140 is shown in the "Trace Data" column, and the trace message transmitted by the trace encoder 140 based on that trace data is shown in the "Trace Message" column. Furthermore, Figure 5 represents the flow of time from top to bottom; that is, older information is shown at the top of the figure, and newer information is shown at the bottom.

[0034] Figure 6 shows an example of privileged mode transitions in single-step mode. Figure 6 also shows a time-series example of the CPU 120's operating status in single-step mode in tabular format. The CPU 120's operating status is shown in the "CPU Operating Status" column, and the trace messages sent by the trace encoder 140 in that operating status are shown in the "Trace Message" column. In Figure 6, the time flow is from top to bottom. That is, the upper part of the figure shows older information, and the lower part shows newer information.

[0035] In the example in Figure 6, the CPU 120 executes instructions while switching between normal mode (U-mode) and debug mode (D-mode) for each instruction. The debug-targeted circuit 110 notifies the trace encoder 140 of the change in privileged mode when executing instructions in single-step mode using the "priv" Ingress Port, as shown in row R14 of Figure 3. In this way, in single-step mode, the CPU 120 executes instructions one by one, and the circuit under debug 110 outputs trace information in accordance with the execution of the instructions.

[0036] In accordance with the "TG RISC-V Nexus Trace Specification," the trace encoder 140 outputs "Program Trace.Correlation," shown in line R27 of Figure 4, when transitioning to debug mode. Furthermore, when the privileged mode transitions back to normal mode, the trace encoder 140 outputs "Program Trace.Synchronization," shown in line R25 of Figure 4. This allows the trace encoder 140 to notify the stop and start of the trace flow for each instruction.

[0037] Here, in the trace messages output externally by the trace encoder 140, real-time performance is considered important, and information representing the current state is required. On the other hand, the trace messages stored in the internal RAM 150 are retrieved after the program has finished and are likely to be used to verify a series of program operations.

[0038] Information about changes in privileged mode is not necessary for restoring the history information of the program counter state. Therefore, the trace encoder 140 stores the trace message with the privileged mode information removed in the internal RAM 150. Figure 7 shows an example of a trace message with privileged mode information removed in single-step mode. Figure 7 also shows an example of a trace message stored in the internal RAM 150 by the trace encoder 140 in single-step mode, presented in a table format. The trace data output by the debugged circuit 110 to the trace encoder 140 is shown in the "Trace Data" column, and the trace message stored in the internal RAM 150 by the trace encoder 140 based on that trace data is shown in the "Trace Message" column. Furthermore, Figure 7 shows the flow of time from top to bottom; that is, older information is shown at the top of the figure, and newer information is shown at the bottom.

[0039] Comparing the example in Figure 5 with the example in Figure 7, the example in Figure 5 shows "Program Trace.Synchronization" output when transitioning to normal mode (U) and "Program Trace.Correlation" output when transitioning to debug mode (D). In contrast, in the example in Figure 7, these "Program Trace.Synchronization" and "Program Trace.Correlation" entries have been removed.

[0040] Note that "Program Trace.Synchronization" shown in Figure 7 is output at the start of instruction execution and is different from "Program Trace.Synchronization" output when transitioning to normal mode (U). Also, "Program Trace.Correlation" shown in Figure 7 is output at the end of instruction execution and is different from "Program Trace.Correlation" output when transitioning to debug mode (D).

[0041] Figure 8 shows an example of the configuration of the trace encoder 140. In the configuration shown in Figure 8, the trace encoder 140 includes a filter control unit 141, a trace information control unit 142, an external output message generation unit 143, an external output message transmission FIFO 144, an internal RAM message generation unit 145, and an internal RAM message transmission FIFO 146.

[0042] Figure 9 shows an example of data input and output in the trace encoder 140. The filter control unit 141 extracts the information necessary for generating trace messages from the Ingress Port data input from the CPU 120. The filter control unit 141 outputs the extracted information to the trace information control unit 142. The filter control unit 141 may use known processing techniques as the processing it performs. For example, the filter control unit 141 may perform known processing that is performed when acquiring trace data in RISC-V.

[0043] The trace information control unit 142 analyzes the information input from the filter control unit 141 and generates the information necessary for generating trace messages for external output (external transmission). Trace messages for external output are also called standard trace messages. Standard trace messages are treated as examples of trace data and are also called standard trace data.

[0044] The trace information control unit 142 may use known techniques to analyze the information input from the filter control unit 141 and generate the information necessary for generating trace messages for external output. For example, the trace information control unit 142 may perform known processing that is performed when acquiring trace data in RISC-V.

[0045] Furthermore, the trace information control unit 142 generates information necessary for generating a trace message, which is stored in the internal RAM 150, by removing the privileged mode information from the information necessary for generating a standard trace message. Specifically, the trace information control unit 142 generates information necessary for generating a trace message, which is stored in the internal RAM 150, by removing the "private" information of the Ingress Port shown in row R14 of Figure 3 from the information necessary for generating a standard trace message.

[0046] Trace messages stored in internal RAM 150 are also called data-reduced trace messages. Internal RAM 150 is an example of memory that stores data-reduced trace messages. Data-reduced trace messages are treated as an example of trace data and are also called data-reduced trace data.

[0047] The trace information control unit 142 outputs the information necessary for generating standard trace messages to the external output message generation unit 143. The trace information control unit 142 also outputs the information necessary for generating data-reduced trace messages to the internal RAM message generation unit 145.

[0048] The external output message generation unit 143 generates a standard trace message using the information input from the trace information control unit 142. Specifically, the external output message generation unit 143 converts the trace data input from the trace information control unit 142 into text (string). The external output message generation unit 143 may use known techniques for the process of converting trace data into text. For example, the external output message generation unit 143 may perform known processing that is performed when converting trace data into trace messages in RISC-V. The external output message generation unit 143 outputs the generated standard trace message to the external output message transmission FIFO.

[0049] The external output message transmission FIFO 144 transmits standard trace messages input from the external output message generation unit 143 to the outside of the LSI 100. Specifically, the external output message transmission FIFO 144 temporarily stores the standard trace messages input from the external output message generation unit 143 in a FIFO (First-In First-Out) and transmits the standard trace messages in the order they were received.

[0050] The internal RAM message generation unit 145 generates a data-reduced trace message using information input from the trace information control unit 142. In particular, the internal RAM message generation unit 145 generates a data-reduced trace message in which privileged mode information is removed, in comparison with a standard trace message generated by the external output message generation unit 143. The internal RAM message generation unit 145 may further perform data compression on the generated data-reduced trace message.

[0051] The internal RAM message generation unit 145 may use known techniques for the process of converting trace data into text. For example, the internal RAM message generation unit 145 may perform known processing that is performed when converting trace data into trace messages in RISC-V. The internal RAM message generation unit 145 outputs the generated data volume reduction trace message to the internal RAM message transmission FIFO 146.

[0052] The internal RAM message transmission FIFO 146 outputs data-reducing trace messages input from the internal RAM message generation unit 145 to the internal RAM 150. In particular, the internal RAM message transmission FIFO 146 temporarily stores standard trace messages input from the internal RAM message generation unit 145 in the FIFO and outputs data-reducing trace messages in the order they were received. Internal RAM 150 stores data reduction trace messages input from the internal RAM message transmission FIFO 146.

[0053] The combination of the filter control unit 141, the trace information control unit 142, and the external output message generation unit 143 corresponds to an example of a standard trace data acquisition means. The combination of the filter control unit 141, the trace information control unit 142, and the external output message generation unit 143 generates a standard trace message.

[0054] The combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145 is an example of a data volume reduction trace data acquisition means. The combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145 generates data volume reduction trace messages.

[0055] The external output message transmission FIFO144 is an example of a transmission method. The external output message transmission FIFO144 transmits standard trace messages to the outside of the LSI100. The internal RAM message transmission FIFO 146 is an example of a memory writing means. The internal RAM message transmission FIFO 146 stores data-reducing trace messages in the internal RAM 150.

[0056] Furthermore, if the privileged mode changes after the execution of multiple instructions, the trace encoder 140 may generate a data-reduced trace message in which the privileged mode information has been removed and store it in the internal RAM 150.

[0057] Figure 10 shows an example where the privileged mode changes after the execution of multiple instructions. In the example in Figure 6, the privileged mode changes each time CPU 120 executes an instruction, whereas in the example in Figure 10, the privileged mode changes after CPU 120 has executed multiple instructions. Thus, even when the privileged mode changes after the execution of multiple instructions, the trace encoder 140 can reduce the amount of data stored in the internal RAM 150 by generating a data-reduced trace message in which the privileged mode information has been removed.

[0058] As described above, the standard trace data acquisition means, which is a combination of the filter control unit 141, the trace information control unit 142, and the external output message generation unit 143, acquires standard trace data, which is trace data of the operation of the CPU 120, including data indicating the privileged mode of the CPU 120. The data-reducing trace data acquisition means, which is a combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145, acquires data-reducing trace data, which is trace data from which information indicating the privileged mode of the CPU 120 has been removed from standard trace data. The external output message sender FIFO144 sends standard trace messages. The internal RAM message transmission FIFO146 stores data-reducing trace messages in the internal RAM150.

[0059] According to LSI100, a relatively large amount of information can be provided, and the amount of trace message data stored in memory can be kept relatively small. In particular, according to LSI100, a relatively large amount of information can be provided by sending a standard trace message, which is a trace message containing information indicating the privileged mode of CPU120, to an external location. Furthermore, according to LSI100, the amount of trace message data stored in the internal RAM150 can be kept relatively small by storing a data-reduced trace message, which is a trace message from which the information indicating the privileged mode of CPU120 has been removed, in the internal RAM150.

[0060] Furthermore, the data-reducing trace data acquisition means, which combines the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145, generates data-reducing trace messages in a single-step mode in which the privileged mode switches each time the CPU 120 executes an instruction one by one.

[0061] According to LSI100, in single-step mode, where the privileged mode changes each time the CPU120 executes an instruction, the effect of reducing the amount of data stored in the internal RAM150 is expected to be particularly significant, as the data reduction trace message is stored in the internal RAM150.

[0062] As LSI circuits become more complex, it is conceivable to integrate on-chip debugging circuits into LSIs to improve the efficiency of debugging LSI hardware and the programs executed by the LSI. By using on-chip debugging circuits to collect information such as the instructions and processing times generated when the CPU executes a program, information such as which instructions the CPU is executing, how long it is taking, and the core utilization rate can be collected, which can be used for hardware and software bug analysis, as well as for speeding up and optimizing programs.

[0063] When an on-chip debugging circuit is integrated into an LSI, it is conceivable to store debugging information (e.g., trace messages) in the LSI's internal memory. In this case, the memory capacity of the LSI is limited, and it is possible that debugging information can only be stored in memory for a portion of the CPU's program execution time. For example, if a ring buffer is used as the memory for storing debugging information, any debugging information exceeding the memory capacity will be overwritten and lost by subsequent data. Because debugging information can only be stored in memory for a portion of the program's execution time, information about points you want to check may not be stored in memory, making debugging and other tasks difficult.

[0064] In this regard, the inventors of the present invention found that when verifying the operation of a program in single-step mode, trace messages that notify privileged mode (trace messages that notify a change in privileged mode) account for a large proportion of the data stored in memory. From this, the inventors of the present invention gained the insight that the amount of data can be reduced by deleting the privileged mode information from the trace messages in single-step mode. For example, by reducing the trace messages that indicate privileged mode, the amount of data can be reduced by more than half, and calculations showed that it is possible to store more than twice the amount of data in memory compared to when no data reduction is performed.

[0065] Therefore, as described above, the internal RAM message generation unit 145 generates a data-reduced trace message in which privileged mode information is removed when compared with a standard trace message. This allows a relatively large amount of data to be stored in the internal RAM 150, which is expected to improve the efficiency of debugging and other operations. In particular, in single-step mode, the data reduction effect is expected to be significant because the internal RAM message generation unit 145 generates data-reduced trace messages in which privileged mode information has been removed.

[0066] Meanwhile, the external output message generation unit 143 generates a standard trace message including a trace message that notifies the privileged mode and transmits it to the outside of the LSI 100 via the external output message transmission FIFO 144. According to the LSI100, it is possible to provide a relatively large amount of information as a highly real-time external output, while keeping the amount of debug information data stored in memory (for example, the amount of data for the entire program execution) relatively small.

[0067] <Second Embodiment> Figure 11 shows an example of the configuration of a trace data acquisition device according to at least one embodiment. In the configuration shown in Figure 11, the trace data acquisition device 610 includes a standard trace data acquisition unit 611, a data volume reduction trace data acquisition unit 612, a transmission unit 613, and a memory writing unit 614.

[0068] In this configuration, the standard trace data acquisition unit 611 acquires standard trace data, which is trace data of the CPU's operation, including data indicating the privileged mode of the CPU. The data volume reduction trace data acquisition unit 612 acquires data volume reduction trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from standard trace data. The transmitter 613 transmits standard trace data. The memory writing unit 614 stores the data reduction trace data in memory.

[0069] The standard trace data acquisition unit 611 is an example of a standard trace data acquisition means. The data volume reduction trace data acquisition unit 612 is an example of a data volume reduction trace data acquisition means. The transmission unit 613 is an example of a transmission means. The memory writing unit 614 is an example of a memory writing means.

[0070] The trace data acquisition device 610 can provide a relatively large amount of information while keeping the amount of trace data stored in memory relatively small. In particular, the trace data acquisition device 610 can provide a relatively large amount of information by transmitting a standard trace message, which is a trace message that includes information indicating the privileged mode of the CPU. Furthermore, the trace data acquisition device 610 can store a data-reduced trace message in memory, which is a trace message from which the information indicating the privileged mode of the CPU has been removed, while keeping the amount of trace message data stored in memory relatively small.

[0071] <Third Embodiment> Figure 12 shows an example of the configuration of an integrated circuit according to at least one embodiment. In the configuration shown in Figure 12, the integrated circuit 620 includes a CPU 621, a standard trace data acquisition unit 622, a data volume reduction trace data acquisition unit 623, a transmission unit 624, and a memory writing unit 625.

[0072] In this configuration, the standard trace data acquisition unit 622 acquires standard trace data, which is trace data of the operation of the CPU 621, including data indicating the privileged mode of the CPU 621. The data volume reduction trace data acquisition unit 623 acquires data volume reduction trace data, which is trace data from which information indicating the privileged mode of the CPU 621 has been removed from the standard trace data. The transmitter 624 transmits standard trace data. The memory writing unit 625 stores the data-reduced trace data in memory.

[0073] The standard trace data acquisition unit 622 is an example of a standard trace data acquisition means. The data volume reduction trace data acquisition unit 623 is an example of a data volume reduction trace data acquisition means. The transmission unit 624 is an example of a transmission means. The memory writing unit 625 is an example of a memory writing means.

[0074] The integrated circuit 620 can provide a relatively large amount of information while keeping the amount of trace data stored in memory relatively small. In particular, the integrated circuit 620 can provide a relatively large amount of information by sending a standard trace message, which is a trace message that includes information indicating the privileged mode of the CPU 621. Furthermore, the integrated circuit 620 can store a data-reduced trace message in memory, which is a trace message from which the information indicating the privileged mode of the CPU 621 has been removed from the standard trace message, thus keeping the amount of trace message data stored in memory relatively small.

[0075] <Fourth Embodiment> Figure 13 shows an example of the processing steps in a trace data acquisition method according to at least one embodiment. The trace data acquisition method shown in Figure 13 includes acquiring standard trace data (step S611), acquiring data-reduced trace data (step S612), transmitting the data (step S613), and writing the data to memory (step S614).

[0076] In acquiring standard trace data (step S611), the trace data acquisition device acquires standard trace data, which is trace data of the CPU's operation, including data indicating the privileged mode of the CPU. In acquiring data-reduced trace data (step S612), the trace data acquisition device acquires data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from standard trace data. In transmitting data (step S613), the trace data acquisition device transmits standard trace data. In writing data to memory (step S614), the trace data acquisition device stores the reduced-data trace data in memory.

[0077] The trace data acquisition method shown in Figure 13 can provide a relatively large amount of information while keeping the amount of trace data stored in memory relatively small. In particular, the trace data acquisition method shown in Figure 13 can provide a relatively large amount of information by sending a standard trace message, which is a trace message that includes information indicating the privileged mode of the CPU. Furthermore, the trace data acquisition method shown in Figure 13 can keep the amount of trace message data stored in memory relatively small by storing a data-reduced trace message in memory, which is a trace message from which information indicating the privileged mode of the CPU has been removed from the standard trace message.

[0078] Alternatively, a program for executing all or part of the processing performed by the trace encoder 140, trace data acquisition device 610, standard trace data acquisition unit 622, data volume reduction trace data acquisition unit 623, transmission unit 624, and memory writing unit 625 may be recorded on a computer-readable recording medium, and the processing of each unit may be performed by executing the program recorded on this recording medium. For example, these functions or parts thereof may be implemented in firmware. Or, these functions or parts thereof may be executed by the CPU executing a program. The term "computer-readable recording medium" as used herein refers to portable media such as flexible disks, magneto-optical disks, ROMs (Read Only Memory), CD-ROMs (Compact Disc Read Only Memory), and storage devices such as hard disks built into computer systems. Furthermore, the aforementioned functions may be realized through a combination of these media and programs already recorded in the computer system.

[0079] Although embodiments of this invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the spirit of this invention. Furthermore, the embodiments described above can be combined with other embodiments as appropriate.

[0080] Some or all of the above embodiments may also be described as follows, but are not limited to these.

[0081] (Note 1) Standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU, A data-reduced trace data acquisition means that acquires data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, A transmission means for transmitting the aforementioned standard trace data, A memory writing means for storing the aforementioned data volume reduction trace data in memory, A trace data acquisition device equipped with the following features.

[0082] (Note 2) The standard trace data acquisition means generates the standard trace message in a single-step mode in which the privileged mode switches each time the CPU executes an instruction one by one. The data volume reduction trace data acquisition means generates the data volume reduction trace message in the single-step mode. The trace data acquisition device described in Appendix 1.

[0083] (Note 3) The data volume reduction trace data acquisition means generates the data volume reduction trace message when the privileged mode changes after the CPU has executed multiple instructions. The trace data acquisition device described in Appendix 1.

[0084] (Note 4) CPU, Standard trace data acquisition means for acquiring standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU, A data-reduced trace data acquisition means that acquires data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, A transmission means for transmitting the aforementioned standard trace data, A memory writing means for storing the aforementioned data volume reduction trace data in memory, An integrated circuit equipped with the following features.

[0085] (Note 5) The standard trace data acquisition means generates the standard trace message in a single-step mode in which the privileged mode switches each time the CPU executes an instruction one by one. The data volume reduction trace data acquisition means generates the data volume reduction trace message in the single-step mode. The integrated circuit described in Appendix 4.

[0086] (Note 6) The data volume reduction trace data acquisition means generates the data volume reduction trace message when the privileged mode changes after the CPU has executed multiple instructions. The integrated circuit described in Appendix 4.

[0087] (Note 7) The trace data acquisition device, Obtain standard trace data, which is trace data of the CPU's operation, including data indicating the CPU's privileged mode. Data-reduced trace data is obtained, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data. The standard trace data mentioned above is transmitted, The aforementioned data volume reduction trace data is stored in memory. A method for acquiring trace data, including the following.

[0088] (Note 8) By acquiring the standard trace data, the standard trace message is generated in single-step mode, in which the privileged mode switches each time the CPU executes an instruction one by one. By acquiring the aforementioned data volume reduction trace data, the data volume reduction trace message is generated in the single-step mode. The method for acquiring trace data as described in Appendix 7.

[0089] (Note 9) By acquiring the aforementioned data reduction trace data, if the privileged mode changes after the CPU has executed multiple instructions, the data reduction trace message is generated. The method for acquiring trace data as described in Appendix 7.

[0090] (Note 10) In an integrated circuit including a CPU, Obtain standard trace data, which is trace data of the CPU's operation, including data indicating the privileged mode of the CPU. Obtaining data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, The transmission of the aforementioned standard trace data, The aforementioned data volume reduction trace data is stored in memory, A program that executes the command.

[0091] (Note 11) By acquiring the standard trace data, the integrated circuit is made to generate the standard trace message in a single-step mode in which the privileged mode switches each time the CPU executes an instruction one by one. By acquiring the aforementioned data volume reduction trace data, the integrated circuit is made to generate the aforementioned data volume reduction trace message in the single-step mode. The program described in Appendix 10.

[0092] (Note 12) By acquiring the aforementioned data reduction trace data, the integrated circuit is instructed to generate the data reduction trace message when the privileged mode changes after the CPU has executed multiple instructions. The program described in Appendix 10. [Explanation of Symbols]

[0093] 100 LSI 110 Circuits to be debugged 120,621 CPU 130 On-Chip Debug Circuit 140 Trace Encoder 141 Filter Control Unit 142 Trace Information Control Unit 143 External output message generation unit 144 External output message transmission FIFO 145 Message generation unit for internal RAM 146 Message transmission FIFO for internal RAM 150 Internal RAM 610 Trace Data Acquisition Device 611, 622 Standard trace data acquisition unit 612, 623 Data volume reduction trace / data acquisition unit 613, 624 Transmitter 614, 625 Memory writing section 620 Integrated Circuits

Claims

1. Standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU, A data-reduced trace data acquisition means for acquiring data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, A transmission means for transmitting the aforementioned standard trace data, A memory writing means for storing the aforementioned data volume reduction trace data in memory, A trace data acquisition device equipped with [the following features].

2. The data volume reduction trace data acquisition means generates the data volume reduction trace message in a single-step mode in which the privileged mode switches each time the CPU executes an instruction one by one. The trace data acquisition device according to claim 1.

3. The data volume reduction trace data acquisition means generates the data volume reduction trace message when the privileged mode changes after the CPU has executed multiple instructions. The trace data acquisition device according to claim 1.

4. CPU and, Standard trace data acquisition means for acquiring standard trace data which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU, A data-reduced trace data acquisition means for acquiring data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, A transmission means for transmitting the aforementioned standard trace data, A memory writing means for storing the aforementioned data volume reduction trace data in memory, An integrated circuit equipped with the following features.

5. The trace data acquisition device, Obtain standard trace data, which is trace data of the CPU's operation, including data indicating the CPU's privileged mode. A data-reduced trace data is obtained, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data. The standard trace data is transmitted, The aforementioned data volume reduction trace data is stored in memory. A method for acquiring trace data, including the following.

6. In an integrated circuit including a CPU, Obtain standard trace data, which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU. Obtaining data-reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been removed from the standard trace data, Transmitting the aforementioned standard trace data, The aforementioned data volume reduction trace data is stored in memory, A program that executes the command.

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