Firmware evaluation system and firmware evaluation method
The firmware evaluation system addresses inefficiencies in managing background processing waiting times by using special commands to monitor and respond to background processing status without interruption, enhancing evaluation efficiency and data throughput in flash memory devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2026-05-18
AI Technical Summary
Conventional firmware evaluation methods for flash memory devices inefficiently manage waiting times for background processing, leading to reduced data throughput and incomplete execution of background processes, and lack the ability to detect the idle state of the firmware accurately.
A firmware evaluation system and method that utilize an evaluation board to issue special commands to inquire about the completion or incompleteness of background processing in the firmware, and the firmware responds without interrupting the ongoing processing, using the unused space in command processing completion notifications to convey this information.
Enhances firmware evaluation efficiency by minimizing redundant waiting times and ensuring timely detection of background processing completion, thereby improving data throughput and enabling more accurate evaluation of flash memory devices.
Smart Images
Figure 2026080875000001_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a firmware evaluation system and a firmware evaluation method. Here, "evaluation" means testing whether the firmware provides functions in accordance with the standards.
Background Art
[0002] In a flash memory device, by providing the firmware with functions in accordance with the standards, users can easily use the flash memory device. As this standard, UFS (Universal Flash Storage) is widely used in NAND flash memories.
[0003] One of the functions of firmware is background processing. This refers to an internal processing function in which the firmware optimizes system data. The background processing operates before entering an idle state to suppress power consumption when the write / read to the flash memory device is interrupted for a certain period of time. However, what kind of processing operates depends on the internal state of the firmware at that time.
[0004] In the conventional evaluation method, the function evaluation was performed by randomly providing a waiting time to the flash memory device to execute the background processing, resulting in a decrease in evaluation efficiency.
[0005] In a specific example, the amount of data written during a 2-hour evaluation was approximately 360GB. If we estimate the amount without waiting time, it would be approximately 560GB. In other words, in the current evaluation process, the amount of data written in the same amount of time is significantly reduced to about 64% because waiting time is included. Also, the number of background process executions decreased drastically from approximately 5,700 when waiting time was included to approximately 230 when waiting time was removed. If waiting time is removed, background processes are hardly executed at all. Therefore, in the current evaluation, waiting time is included to activate the operation of background processes. In short, it was found that the longer-than-usual evaluation is conducted to compensate for the amount of data written that is reduced by including waiting time.
[0006] Once background processing is complete and the system enters an idle state, no further waiting time is required. However, current evaluation boards for firmware evaluation lack a means to detect whether the firmware is in an idle state. Therefore, the test patterns created by the evaluators use random waiting times. To determine whether this waiting time is appropriate, we examined the firmware's operation logs, including internal processing. We found that the firmware completed background processing and entered an idle state in approximately 20ms to 200ms.
[0007] However, it was found that the test patterns included waiting times ranging from 10us to 5,000ms. This means that in some cases, the firmware is already idle, but the evaluation board continues to wait for redundant periods. It was also found that in some cases the waiting time was too short, causing the next write / read operation to start before background processing was complete.
[0008] For example, as shown in Figure 1, when the evaluation board issues a write / read command to evaluate the suitability of the functionality of the flash memory device's firmware (S11), the firmware continues the write / read process for T1 hours. This T1 hours is the time during which the evaluation board waits for a completion notification from the firmware. A completion notification is sent back from the firmware (S12). Upon receiving this completion notification, the evaluation board transitions to a standby state. Meanwhile, the firmware transitions to background processing.
[0009] The standby time set on the evaluation board is T2, and the next write / read command is issued (S13). At this point, the firmware has not completed background processing, but it interrupts the background processing and moves to the write / read processing corresponding to the write / read command received in step S13. Figure 1 shows an example where the standby time on the evaluation board is insufficient for the firmware to complete background processing, and the background processing is interrupted.
[0010] On the other hand, the situation shown in Figure 2 can also occur. When the evaluation board issues write / read commands to evaluate the suitability of the functionality of the flash memory device's firmware (S21), the firmware continues the write / read process for T1 hours. This T1 hour is the time during which the evaluation board waits for a completion notification from the firmware. A completion notification is sent back from the firmware (S22). Upon receiving this completion notification, the evaluation board transitions to a standby state. Meanwhile, the firmware transitions to background processing.
[0011] The standby time set on the evaluation board is T3, and the next write / read command is issued after time T3 has elapsed (S23). On the other hand, after the firmware completes, it moves to background processing, but the time until background processing is completed is T4, which is much shorter than the standby time T3 set on the evaluation board.
[0012] As described above, after the waiting time T3 set on the evaluation board has elapsed, the next write / read command is issued (S23). However, the firmware has already completed background processing, and the (T4-T3) time in Figure 2 is a redundant and unnecessary waiting time for both the evaluation board and the firmware.
[0013] Patent Document 1 discloses a firmware verification system, and Patent Document 2 discloses a method for reducing the amount of firmware program in an emulator.
[0014] Patent Document 3 discloses an FPGA that enables a reduction in the time required for random testing. To achieve this, it includes a pseudo-random number generator and a seed value change timing generator. The seed value change timing generator includes a counter that counts the number of test steps and a seed value storage unit that stores the count value of this counter and a seed value used to rewrite the pseudo-random number generator.
[0015] Patent Document 4 discloses a method for shortening the test time. To achieve this, the i-th page data of the first device DUT1 is read, and it is determined whether the second device DUT2 is in a ready state. If it is busy, it waits. If it has returned to a ready state, a read command is issued to the first device DUT1, specifying the address of the (i+1)th page to be read next. Subsequently, the i-th page data of the second device DUT2 is read, and then it is determined whether the first device DUT1 is in a ready state. If it is busy, it waits. If the determination is made and it is in a ready state, a read command is issued to the second device DUT2, specifying the address of the (i+1)th page to be read next.
[0016] Patent Document 5 describes a semiconductor testing apparatus aimed at increasing the testing speed and improving productivity by measuring the time required to test a device under test in more detail. This semiconductor test apparatus comprises one or more control cards for testing DUT2 and a controller 3 for controlling the control card 1, and includes a card-side timer provided on the control card for measuring the control time TB required to control the test execution unit provided on the control card, and a waiting time changing unit provided on the controller for changing the waiting time TW reserved for the test execution unit to perform testing of DUT2 based on the control time TB measured by the card-side timer 12. [Prior art documents] [Patent Documents]
[0017] [Patent Document 1] Japanese Patent Publication No. 2014-96032 [Patent Document 2] Japanese Patent Publication No. 2004-341802 [Patent Document 3] International Publication No. 2022-145092 [Patent Document 4] Japanese Patent Publication No. 2009-245485 [Patent Document 5] Japanese Patent Publication No. 2010-112716 [Overview of the Initiative] [Problems that the invention aims to solve]
[0018] As described above, conventional technologies have not been able to appropriately manage the waiting time for background processing of firmware in flash memory devices, thereby enabling efficient firmware evaluation. The present invention provides a firmware evaluation system and a firmware evaluation method that enable efficient firmware evaluation by appropriately adjusting the waiting time for background processing of firmware in a flash memory device. [Means for solving the problem]
[0019] The firmware evaluation system according to an embodiment of the present invention includes an evaluation board having a write / read command issuing means for issuing a write / read command for evaluating the propriety of the function of the firmware of a flash memory device, and the firmware having a command processing completion notification information returning means for receiving the write / read command and returning command processing completion notification information regarding the propriety of the function of the firmware to the evaluation board. The evaluation board is provided with special command issuing means for issuing a special command for inquiring about the completion / incompletion of background processing executed in the firmware, and the firmware is provided with special command response processing means for returning a response regarding the completion / incompletion of background processing without interrupting the background processing being executed when the special command arrives.
[0020] The firmware evaluation method according to an embodiment of the present invention is realized by an evaluation board executing a write / read command issuing step for issuing a write / read command for evaluating the propriety of the function of the firmware of a flash memory device, and the firmware having a command processing completion notification information returning step for receiving the write / read command and returning command processing completion notification information regarding the propriety of the function of the firmware to the evaluation board. In the evaluation board, a special command issuing step for issuing a special command for inquiring about the completion / incompletion of background processing executed in the firmware is executed, and in the firmware, when the special command arrives, a special command response processing step for returning a response regarding the completion / incompletion of background processing without interrupting the background processing being executed is executed.
Brief Description of the Drawings
[0021] [Figure 1]A diagram showing the operation procedure during firmware evaluation performed by a conventional firmware evaluation system, which shows an example in which the background process is interrupted because the waiting time in the standby state of the evaluation board is insufficient for the completion of the background process of the firmware. [Figure 2] A diagram showing the operation procedure during firmware evaluation performed by a conventional firmware evaluation system, which shows an example in which the firmware has already completed the background process, and a wasteful and redundant waiting time has occurred for both the evaluation board and the firmware. [Figure 3] A configuration diagram of the firmware evaluation system according to the present invention. [Figure 4] A diagram showing the operation procedure during firmware evaluation performed by the firmware evaluation system according to the present embodiment.
Embodiments for Carrying Out the Invention
[0022] Hereinafter, embodiments of a firmware evaluation system and a firmware evaluation method according to the present invention will be described with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. FIG. 3 shows a configuration diagram of the firmware evaluation system according to the present invention. Reference numeral 100 denotes a flash memory device, and the flash memory device 100 includes a data storage area 101 and firmware 120.
[0023] The firmware 120 is connected to an evaluation board 200 for evaluating the suitability of the functions of the firmware 120 of the flash memory device 100, receives commands from the evaluation board 200, and returns responses. The evaluation board 200 includes a write / read command issuing means 201 for issuing a write / read command for evaluating the suitability of the functions of the firmware of the flash memory device 100. The evaluation board 200 can also be realized by a personal computer, a smartphone, or the like as long as it has a computer function. <00001The firmware 120 includes a command processing completion notification information return means 121. The command processing completion notification information return means 121 receives the write / read command and returns command processing completion notification information regarding the suitability of the firmware 120's function to the evaluation board 200.
[0025] Furthermore, the evaluation board 200 is equipped with a special command issuing means 202. The special command issuing means 202 issues special commands to inquire about the completion or incompleteness of background processing performed by the firmware 120. Background processing is an internal processing function in which the firmware 120 optimizes system data.
[0026] The issuance of special commands is for monitoring the internal state of firmware 120, and by issuing these special commands at the appropriate time, the aim is to improve the efficiency of firmware evaluation of flash memory device 100.
[0027] The special command issuing means 202 issues special commands by polling. The evaluation board 200 is equipped with an input means 203. The input means 203 consists of a touch input panel or the like, and the evaluator of the firmware evaluation inputs the number of polling cycles and the time interval, and provides this to the special command issuing means 202 to execute the polling.
[0028] Furthermore, the firmware 120 is equipped with a special command response processing means 122. When the special command arrives, this special command response processing means 122 returns a response indicating whether the background processing is complete or incomplete without interrupting the background processing that is currently in progress.
[0029] The special command response processing means 122 packages the response information regarding the completion or incompleteness of background processing into an unused location within the command processing completion notification information, which has a predetermined data length, and returns the response. According to the UFS standard definition, the command processing completion notification information that the firmware 120 returns to the evaluation board 200 is 32-byte formatted information. This includes information such as the amount of data written or read and the cause of command failure, in addition to the success or failure of the command. However, not all 32 bytes are used, and there is an unused area. In this embodiment, the status of background processing is added to this unused area, so that the evaluation board 200 can detect the status of background processing.
[0030] However, issuing a normal write / read command to check the status would interrupt the background processing and restart it from the beginning. Interrupting the background processing for evaluation purposes is not appropriate. Therefore, in this embodiment, although the firmware 120 receives a command, it adds the status (completion or incompleteness of background processing) to the unused area mentioned above only in response to special commands that do not interrupt the background processing. This allows the firmware 120 to detect completion notifications on the evaluation board 200 without interrupting the background processing.
[0031] Figure 4 shows the operating procedure during firmware evaluation performed by the firmware evaluation system according to this embodiment. When the write / read command issuing means 201 of the evaluation board 200 issues a write / read command to evaluate the suitability of the functionality of the firmware 120 of the flash memory device 100 (S31), the firmware 120 continues the write / read process for T5 hours. This T5 hours is the time during which the evaluation board 200 waits for command processing completion notification information from the firmware 120. When the firmware 120 completes the command processing, a completion notification is sent back from the firmware 120 (S32). Upon receiving this completion notification, the evaluation board 200 transitions to a standby state at this point. Meanwhile, the firmware 120 transitions to background processing for T6 hours.
[0032] The special command issuing means 202 of the evaluation board 200 issues special commands by polling based on the number of polls and time intervals input by the firmware evaluation evaluator from the input means 203 (S33-1 to S33-n). The command processing completion notification information return means 121 of the firmware 120 returns command processing completion notification information, which includes response information on whether background processing is complete or not, to the evaluation board 200 (S34-1 to S33-n).
[0033] While firmware 120 is performing background processing for T6 hours, it continues to issue special commands (S33-1 to S33-n) and send command processing completion notification information, including response information indicating whether background processing is complete or not, back to evaluation board 200 (S34-1 to S34-n).
[0034] The command processing completion notification information (S34-n) sent back in response to the special command (S33-n) sent from the evaluation board 200 after the background processing is complete includes completion response information. Upon receiving this, the evaluation board 200's write / read command issuing means 201 issues write / read commands to evaluate the suitability of the functionality of the firmware 120 of the flash memory device 100 (S35), and the firmware 120 continues the write / read process for TX time. During this TX time, the evaluation board 200 waits for the command processing completion notification information from the firmware 120, and after the TX time has elapsed, the firmware 120 sends back the completion notification (S36). The same process continues thereafter.
[0035] As can be seen from Figure 4, if background processing is completed when firmware 120 receives a special command, command processing completion notification information including completion response information will be sent to evaluation board 200. This allows evaluation board 200 to minimize the waiting time after background processing is complete and move on to issuing write / read commands (issuing normal write / read commands) to evaluate the suitability of the firmware 120's functionality in flash memory device 100, thereby achieving both improved evaluation efficiency and appropriate evaluation.
[0036] In other words, by making the previously random waiting time understandable, the background processing can be executed appropriately to maintain the quality of the flash memory device while shortening the execution time of random tests. Furthermore, by quickly proceeding to the next evaluation after the background processing is completed, the detection and analysis of flash memory device defects can be expedited. In addition, since the understanding of the firmware's internal state is not skipped, there is the advantage of being able to appropriately change the test pattern for firmware evaluation, such as concentrating or distributing write and read operations to specific logical addresses. [Explanation of Symbols]
[0037] 100 flash memory devices 101 Storage area 120 firmware 121 Command processing completion notification information return means 122 Special command response processing means 200 Evaluation Boards 201 Write / Read Command Issuance Method 202 Special Command Issuance Method 203 Input means
Claims
1. An evaluation board equipped with a write / read command issuing means for issuing write / read commands to evaluate the suitability of the firmware functionality of a flash memory device, The firmware includes a command processing completion notification information return means that, upon receiving the write / read command, returns command processing completion notification information regarding the suitability of the firmware's functions to the evaluation board, A firmware evaluation system comprising, The evaluation board is equipped with special command issuing means for issuing special commands to inquire about the completion or incompleteness of background processing performed in the firmware. A firmware evaluation system characterized in that the firmware is equipped with a special command response processing means that, upon receiving the special command, returns a response indicating the completion or incompleteness of the background processing without interrupting the background processing that is currently in progress.
2. The firmware evaluation system according to claim 1, characterized in that the special command issuing means issues special commands by polling.
3. The firmware evaluation system according to claim 1, characterized in that the special command response processing means packages response information indicating the completion or incompleteness of background processing at a predetermined unused position in the command processing completion notification information having a predetermined data length and returns a response.
4. The firmware evaluation system according to claim 2, characterized in that the evaluation board is provided with an input means for issuing a special command to perform polling by providing the number of polling cycles and the time interval to the special command issuing means.
5. The firmware evaluation system according to claim 1, characterized in that the write / read command issuing means issues the next write / read command when a response indicating the completion of background processing is obtained from the firmware.
6. The firmware evaluation system according to claim 3, characterized in that the command processing completion notification information includes the amount of data written or read, the range of logical addresses in the flash memory device, and the cause of the command failure.
7. An evaluation board that performs a write / read command issuance step to issue write / read commands to evaluate the suitability of the functionality of the firmware of a flash memory device, The firmware includes a command processing completion notification information return step that, upon receiving the write / read command, returns command processing completion notification information regarding the suitability of the firmware's functions to the evaluation board, A firmware evaluation method realized by, The evaluation board executes a special command issuance step that issues a special command to inquire about the completion or incompleteness of background processing performed in the firmware. The firmware evaluation method is characterized in that, when the special command arrives in the firmware, a special command response processing step is executed that returns a response indicating whether the background processing is complete or incomplete without interrupting the background processing that is currently in progress.
8. The firmware evaluation method according to claim 7, characterized in that the special command is issued by polling in the special command issuance step.
9. The firmware evaluation method according to claim 7, characterized in that the special command response processing step packages response information indicating the completion or incompleteness of background processing at a predetermined unused position in the command processing completion notification information having a predetermined data length and returns a response.
10. The firmware evaluation method according to claim 8, characterized in that the evaluation board provides the number of polling cycles and the time interval to the special command issuance step to perform the polling.
11. The firmware evaluation method according to claim 7, characterized in that, in the write / read command issuance step, the next write / read command is issued when a response indicating the completion of background processing is obtained from the firmware.
12. The firmware evaluation method according to claim 9, characterized in that the command processing completion notification information includes the amount of data written or read, the range of logical addresses in the flash memory device, and the cause of the command failure.