A hardware monitoring device and method based on a PCIe expansion card

Abstract

The application provides a PCIe extension card-based hardware monitoring device and method, and relates to the technical field of hardware monitoring.The device comprises a PCIe communication interface for performing PCIe protocol communication with a host;an independent power supply unit for taking power through an auxiliary standby power supply interface and being isolated from the host side through a digital isolator;an isomorphic processing unit;multi-stage storage units for storing data in stages;a switchable network topology unit having a network physical layer interface and a topology switching circuit;the isomorphic processing unit receives host instructions, controls the working mode of the switchable network topology unit, and schedules the multi-stage storage units to perform testing and store the test results in stages.The application can solve the problem of monitoring failure and data loss caused by operating system crash or power failure in the prior art, continuously monitors and ensures data safety in abnormal system conditions, reduces testing cost, and improves the comprehensiveness of system stability verification.

Description

Technical Field

[0001] This invention relates to the field of hardware monitoring technology, and specifically to a hardware monitoring device and method based on a PCIe expansion card. Background Technology

[0002] Currently, the reliability assurance of existing computer systems mainly relies on two technical paths: one is software monitoring solutions based on the operating system environment. Although these are easy to deploy, the monitoring process is deeply coupled with the host system. Once a system crash, freeze, or unexpected power failure occurs, the monitoring will be interrupted synchronously, resulting in the loss of critical transient data. Furthermore, data stored in the host memory or file system is easily overwritten or tampered with, making it difficult to meet the high reliability requirements of industrial equipment for fault tracing and data auditing. The other is hardware out-of-band management solutions represented by server BMCs. Although these solutions have independent monitoring capabilities independent of the operating system, they rely on customized motherboards and dedicated interfaces, resulting in high hardware costs and poor deployment flexibility, making it difficult to scale up applications in existing general-purpose PCs and industrial control equipment. In the testing field, stability testing for critical interfaces such as PCIe links usually relies on specialized equipment, with limited testing scenarios and the inability to perform tests under real system loads. Meanwhile, stress testing of multiple interfaces such as networks and buses is often performed by independent tools, lacking collaborative testing mechanisms. This makes it difficult to reproduce comprehensive stability failures under conditions where multiple devices share system resources, resulting in fragmented, inefficient, and costly verification of system reliability.

[0003] In summary, existing technologies suffer from several technical problems: the monitoring function is heavily reliant on the host operating system, and the testing methods are fragmented, leading to the loss of critical fault data when the system crashes; the PCIe link verification cost is high; and the stability of multi-interface collaboration is difficult to assess, further affecting the efficiency of system reliability verification. Summary of the Invention

[0004] This application provides a hardware monitoring device and method based on a PCIe expansion card, which addresses the technical problems in the prior art, such as the loss of critical fault data when the system crashes due to the deep dependence of monitoring functions on the host operating system and the fragmentation of testing methods, the high cost of PCIe link verification, and the difficulty in assessing the collaborative stability of multiple interfaces, which further affect the efficiency of system reliability verification.

[0005] In view of the above problems, this application provides a hardware monitoring device and method based on a PCIe expansion card.

[0006] In a first aspect, this application provides a hardware monitoring device based on a PCIe expansion card. The device includes: a PCIe communication interface for PCIe protocol communication with a host; an independent power supply unit powered via an auxiliary standby power interface and isolated from the host via a digital isolator; a heterogeneous processing unit connected to the PCIe communication interface and the independent power supply unit; a multi-level storage unit connected to the heterogeneous processing unit for hierarchical data storage; and a switchable network topology unit connected to the heterogeneous processing unit, having a network physical layer interface and a topology switching circuit. The heterogeneous processing unit receives host commands via the PCIe communication interface, controls the operating mode of the switchable network topology unit according to the host commands, and schedules the multi-level storage unit to perform out-of-band hardware status monitoring, PCIe link protocol layer testing, and network stress testing, storing the test results hierarchically.

[0007] Optionally, the heterogeneous processing unit includes an FPGA processor and a microcontroller unit; wherein the FPGA processor is configured with a protocol test engine for constructing a pseudo-random bit stream and calculating the bit error rate; the microcontroller unit communicates with the FPGA processor via a high-speed internal bus for parameter configuration and test scheduling.

[0008] Optionally, the microcontroller unit is used to run a real-time control program to perform sensor sampling, threshold comparison, abnormal triggering logic, and multi-level storage scheduling. The microcontroller unit is also configured to: when an abnormal triggering event is determined to occur, send a freeze command to the FPGA processor and the multi-level storage unit to simultaneously lock and save key state data before and after the abnormality occurs.

[0009] Optionally, the independent power supply unit further includes a multi-channel isolated DC-DC power conversion module, which is used to isolate and convert the independent power obtained by the independent power supply unit from the auxiliary standby power interface to generate multiple source domains to power the monitoring and test circuits.

[0010] Optionally, the multi-level storage unit includes: a high-speed cache storage layer for real-time caching of sensor sampling data and protocol test raw data; a transient solidification storage layer, using a non-volatile tamper-proof storage medium, for writing and solidifying data within a preset time window in the high-speed cache storage layer after an abnormal triggering event; and a long-term archive storage layer for storing data transferred from the transient solidification storage layer after system recovery.

[0011] Optionally, the switchable network topology unit supports switching between two operating modes: pass-through monitoring mode and loopback stress mode. In the pass-through monitoring mode, external network traffic is passively directed to the heterogeneous processing unit for analysis without interrupting the source data flow. In the loopback stress mode, the transmit and receive channels of the network physical layer interface are internally connected through the topology switching circuit to form a closed loop, which is used to cooperate with the heterogeneous processing unit to perform active network load injection and performance testing.

[0012] Optionally, a management communication interface is used to enable driverless access to the operating system via a firmware-level communication protocol and an extended ROM. Before the operating system starts, the host can identify the hardware monitoring device and read the monitoring status, log data, and data stored in the multi-level storage unit.

[0013] Secondly, this application also provides a hardware monitoring method based on a PCIe expansion card. The method includes: obtaining power independent of the host system power supply for the hardware monitoring device through a standby power interface or auxiliary power supply interface, and then supplying power to the internal circuitry of the hardware monitoring device after isolation and conversion; continuously collecting data from at least one hardware status sensor through a microcontroller unit, continuously monitoring the status parameters of the PCIe link using an FPGA processor, and writing the collected sensor data and link status parameters into a high-speed cache storage layer for cyclic caching in real time; comparing the sensor data and link status parameters with a preset threshold; when an abnormal triggering event is detected, issuing a freeze command to the FPGA processor and multi-level storage unit by the microcontroller unit; in response to the freeze command, the microcontroller unit and the FPGA processor synchronously suspend the current operation, and writing the data within a preset time window based on the freeze time in the high-speed cache storage layer into a tamper-proof, non-volatile, transient, and permanently stored layer.

[0014] Optionally, test instructions from the host are obtained, the switchable network topology unit is controlled to enter the corresponding test working mode, and the test process is executed; wherein, the test working mode includes the PCIe protocol layer loopback test steps: the FPGA processor enables the link loopback injection mode according to the configuration parameters, continuously generates pseudo-random code streams to form test load, counts symbol anomalies, packet errors and retransmissions in the receiving channel, and generates a comprehensive bit error rate statistical result.

[0015] Optionally, the test operation mode further includes: controlling the switchable network topology unit to switch to internal loopback mode, so that the sending end and receiving end of the network physical layer interface form a closed loop; constructing network test data packets through the direct memory access engine of the FPGA processor, sending and receiving them through the switchable network topology unit, and performing cyclic redundancy check on the received test data packets, calculating the delay based on the sending and receiving timestamps; statistically analyzing the network packet loss rate, error rate, and delay distribution indicators based on the number of sent packets, the number of received packets, the number of cyclic redundancy check error packets, and the delay, and generating log data containing the test results after the test process is completed.

[0016] One or more technical solutions provided in this application have at least the following beneficial effects: The system communicates with the host via a PCIe communication interface; an independent power supply unit draws power from an auxiliary standby power interface and is isolated from the host side via a digital isolator; a heterogeneous processing unit is connected to the PCIe communication interface and the independent power supply unit; a multi-level storage unit is connected to the heterogeneous processing unit for hierarchical data storage; and a switchable network topology unit is connected to the heterogeneous processing unit and has a network physical layer interface and topology switching circuitry. The heterogeneous processing unit receives host commands via the PCIe communication interface, controls the operating mode of the switchable network topology unit according to the host commands, and schedules the multi-level storage unit to perform out-of-band hardware status monitoring, PCIe link protocol layer testing, and network stress testing, storing the test results hierarchically. In other words, through the integrated design of the independent power supply unit, heterogeneous processing unit, and multi-level storage unit, a comprehensive technical effect is achieved: even in the event of operating system malfunction or power failure, hardware status monitoring can continue and data is not lost, while simultaneously reducing testing costs and improving system stability verification. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the hardware monitoring device based on a PCIe expansion card according to this application.

[0019] Figure 2 This is a flowchart illustrating a hardware monitoring method based on a PCIe expansion card according to this application.

[0020] Figure labeling: 1. PCIe communication interface; 2. Independent power supply unit; 3. Heterogeneous processing unit; 4. Multi-level storage unit; 5. Switchable network topology unit; 6. Host. Detailed Implementation

[0021] This application provides a hardware monitoring device and method based on a PCIe expansion card to address the technical problems in existing technologies. These problems include the deep dependence of monitoring functions on the host operating system and the fragmented nature of testing methods, leading to the loss of critical fault data during system crashes, high PCIe link verification costs, and difficulty in assessing the stability of multi-interface collaboration, all of which further affect the efficiency of system reliability verification. Through the integrated design of an independent power supply unit, heterogeneous processing unit, and multi-level storage unit, the application achieves the comprehensive technical effect of continuing hardware status monitoring and ensuring no data loss even in the event of operating system malfunctions or power failures, while simultaneously reducing testing costs and improving system stability verification.

[0022] Example 1, please refer to the appendix. Figure 1 This application provides a hardware monitoring device based on a PCIe expansion card, wherein the hardware monitoring device based on a PCIe expansion card is used to implement a hardware monitoring method based on a PCIe expansion card, and the hardware monitoring device based on a PCIe expansion card includes: PCIe communication interface 1 communicates with host 6 via PCIe protocol.

[0023] Specifically, in the entire hardware monitoring device, the PCIe communication interface 1 is the fundamental bridge and prerequisite for realizing all advanced functions. When the device is inserted into the standard PCIe slot of the host 6, the firmware and operating system of the host 6 enumerate and identify the device through the standard PCIe configuration space, treating it as a PCIe endpoint device. All interactions are conducted through this standardized channel. The control software on the host 6 encapsulates monitoring configuration parameters, test start commands, etc., into PCIe memory write transaction data packets, and sends them to the heterogeneous processing unit 3 within the device through this interface. The FPGA can encapsulate the collected raw sensor data, the calculated bit error rate statistics, and the fault log data read from the multi-level storage unit 4 into PCIe memory read transactions or completion messages, and efficiently send them back to the host 6 through the same interface. This process is completed entirely at the hardware protocol level, providing the device with a high-bandwidth, low-latency communication path with the host 6 that is partially decoupled from the operating system state. It is the core gateway for establishing the entire out-of-band monitoring capability and for data inflow and outflow.

[0024] Hardware monitoring devices require real-time transmission of large amounts of sensor data, injection of high-bandwidth test traffic, and the freezing and preservation of massive amounts of status information in the event of a failure. All of these place extremely high demands on bus bandwidth and latency. The PCIe channel can provide a theoretical bandwidth of nearly 4GB / s, which is sufficient to meet these requirements. PCIe is a high-speed interconnect bus for peripheral components, referring to a high-speed serial computer bus standard used to achieve point-to-point high-speed communication connections between the host computer and expansion devices.

[0025] Independent power supply unit 2 draws power through the auxiliary standby power interface and is isolated from the host 6 through a digital isolator.

[0026] Furthermore, the hardware monitoring device based on the PCIe expansion card is also used in the following way: the independent power supply unit 2 further includes a multi-channel isolated DC-DC power conversion module, which is used to isolate and convert the independent power obtained by the independent power supply unit 2 from the auxiliary standby power interface to generate a multi-point source domain to power the monitoring and testing circuits.

[0027] Specifically, independent power supply unit 2 obtains power through standby power supply or external auxiliary power supply, and forms an independent power domain through isolation conversion. When the device is inserted into the PCIe slot and connected to the host 6 power supply, the +5VSB pin of the main power supply will continuously supply power to this unit regardless of whether the host 6 is in a powered-on, standby, or software-powered-off state. This +5VSB from the motherboard first enters a front-end protection and filtering circuit to filter out glitches and noise. Subsequently, it is sent to a multi-channel isolated DC-DC power conversion module, the core of which consists of multiple isolated DC-DC conversion chips or modules, similar to multiple independent power stations, which convert and regulate the input +5VSB to the precise voltage required by the various functional circuits inside the device. For example, it provides clean and stable core and interface voltages for FPGA and high-speed logic circuits; it provides analog and digital power for microcontroller units and their peripheral sensors; at the same time, all these generated power domains are electrically isolated from the input +5VSB, and even more completely isolated from the main power domain of the host 6. To ensure the absolute safety of signal interaction between the device and the host 6, all control signals crossing this power boundary must be transmitted through a digital isolator. Even if a severe power short circuit or surge occurs on the host 6 side, the fault is blocked by the firewall formed by the digital isolator and the isolated power module, and cannot harm the monitoring device itself. Conversely, this ensures that the monitoring device can still operate stably and reliably even under the worst fault of the host 6.

[0028] The auxiliary standby power connector is a power pin on the computer motherboard power connector that continues to supply power even after the host computer is completely powered off (soft shutdown). The most common pin is +5VSB. A digital isolator is an integrated circuit based on magnetic or capacitive coupling technology that allows digital signals to be transmitted between two ends without electrical contact, thereby achieving electrical isolation of up to several kilovolts and preventing high voltage, surges, or ground noise from interfering from one side to the other during a fault. A multi-channel isolated DC-DC power conversion module is a set of power circuits that convert and stabilize the input DC voltage into multiple different output voltages. "Isolated" means that electrical isolation is achieved between the input and output through components such as high-frequency transformers, ensuring the independence of each output power domain. In this solution, the single +5VSB input is converted into multiple isolated power islands, such as +3.3V (for digital logic), +1.8V (for the FPGA core), +1.0V (for the FPGA high-speed interface), and ±12V (for analog sensor power supply).

[0029] Standby power is drawn from within the computer host system and continues to exist even after the host system is powered off or hibernating. The most common type is the +5VSB voltage, conforming to the ATX power supply specification, used as an uninterruptible power supply for monitoring devices. In typical applications, the device automatically draws power from the motherboard's standby power line via its gold fingers or dedicated pins. When the motherboard's +5VSB power is insufficient, an external auxiliary power supply can be used, providing main power by connecting an external 12V / 2A DC adapter. These two input power supplies are managed by a priority switching and protection circuit. Afterward, the power enters the core isolation conversion stage: the input power is fed into one or more multi-channel isolated DC-DC power conversion modules. These modules act like a highly specialized internal power grid, converting the single input voltage. Each output domain is electrically isolated from the input power, completely eliminating the path for surges, drops, or ground loop noise from the host system to be conducted to the monitoring core circuitry. Ultimately, one or more independent power domains were formed within the entire device, operating stably, cleanly, and isolated from the external host environment. This ensured that the internal monitoring brain and memory could receive a continuous and high-quality power supply, regardless of how harsh the external power environment was, thus laying the hardware foundation for it to be a trustworthy independent observer.

[0030] Heterogeneous processing unit 3 is connected to PCIe communication interface 1 and independent power supply unit 2.

[0031] Furthermore, the hardware monitoring device based on a PCIe expansion card is also used in the following ways: the heterogeneous processing unit 3 includes an FPGA processor and a microcontroller unit; wherein, the FPGA processor is configured with a protocol test engine to construct a pseudo-random bit stream and statistically analyze the bit error rate; the microcontroller unit communicates with the FPGA processor via a high-speed internal bus for parameter configuration and test scheduling.

[0032] Furthermore, the hardware monitoring device based on the PCIe expansion card is also used for: the microcontroller unit to run a real-time control program, perform sensor sampling, threshold comparison, abnormal triggering logic, and multi-level storage scheduling, wherein the microcontroller unit is also configured to: when an abnormal triggering event is determined to occur, send a freeze command to the FPGA processor and the multi-level storage unit 4, and synchronously lock and save key state data before and after the abnormality occurs.

[0033] Specifically, the heterogeneous processing unit 3 is a collaborative computing system composed of two or more different types of processor cores, each with its own expertise. It does not refer to multiple homogeneous CPUs, but rather emphasizes the combination of processors such as FPGAs and microcontrollers, which are vastly different in architecture, instruction sets, and areas of expertise. The microcontroller, as the central control core, first completes a self-test after power-on and continuously collects hardware status data such as temperature and voltage through sensor interfaces. When it receives instructions from the host 6 through the PCIe communication interface 1 or determines, based on its own logic, that a task needs to be initiated, it acts as a scheduler.

[0034] The microcontroller precisely configures specific test parameters (such as test mode, data mode, and duration) to the corresponding registers within the FPGA processor via a high-speed internal bus. Immediately afterward, the FPGA's internal protocol test engine is activated and runs at a hardware pace: according to the configuration, its pseudo-random binary sequence generator immediately begins generating a continuous test bitstream at line speed; its error rate statistics logic synchronously compares the data returned from the link loopback and calculates the number of errors in real time. All high-speed, parallel data generation, insertion, capture, and preliminary statistical work is completed by the FPGA processor with nanosecond-level latency. The protocol test engine is a functional module implemented in hardware logic within the FPGA, used to generate, send, receive, and analyze specific communication protocol data, such as the test function specifically for the PCIe protocol layer. Its core includes hardware circuits such as a pseudo-random sequence generator, an error rate comparator, and a packet statistician.

[0035] Meanwhile, the microcontroller unit continuously monitors real-time status summaries from the FPGA, such as the current bit error rate and link status, and executes higher-level decision-making logic, such as determining whether the bit error rate exceeds a safety threshold. Once the microcontroller unit's software logic detects abnormal triggering events such as system reset or voltage anomalies, it immediately sends a freeze command to the FPGA via the high-speed internal bus and schedules multi-level memory units 4 to prepare for data reception. Within a very short time (a few clock cycles) of receiving the instruction, the FPGA locks its internal cached critical status data, and the two work together to instantly preserve the data. This architecture frees the FPGA from cumbersome control and scheduling, allowing it to focus on its high-speed processing advantages; while the microcontroller unit utilizes its software programmability to manage complex processes and peripheral devices. Together, they form a fast and intelligent processing core.

[0036] FPGA stands for Field Programmable Gate Array, a programmable logic device whose logic functions can be configured and reconfigured by users through a hardware description language. It is suitable for implementing high-speed interface processing and protocol logic operations. A microcontroller unit (MCU) is an embedded processing chip integrating a CPU core, memory units, and peripheral interfaces, used to perform functions such as real-time control, data acquisition, and task scheduling. The FPGA processor completes PCIe protocol layer traffic construction, loopback control, and error rate statistics; the MCU runs real-time control programs, responsible for sensor sampling, threshold comparison, anomaly triggering logic, and multi-level memory scheduling.

[0037] After system startup, the real-time control program within the microcontroller unit begins periodically executing tasks. Triggered by precise timers, it sequentially reads sampled values ​​from various hardware status sensors, such as monitoring CPU core voltage, critical power rails on the motherboard, and ambient temperature. After each sample, the program immediately compares these raw data with preset safety thresholds. This comparison is not a simple yes or no, but involves a complex set of anomaly triggering logic. For example, to prevent false alarms from occasional noise, the program may require the voltage to be below the lower limit for three consecutive sampling cycles before confirming an anomaly; for critical digital inputs such as the system reset signal, edge detection is used, and once a high-to-low transition is detected, it is immediately considered the highest-level anomaly. Simultaneously, the microcontroller unit is also responsible for task-level multi-level memory scheduling, managing a circular write pointer to the cache storage layer to ensure that the latest sensor data and the link status summary aggregated from the FPGA are cached in an orderly manner.

[0038] The microcontroller instantly switches to crisis mode only when the exception triggering logic is definitively met. It sends a hardware freeze command pulse to the FPGA via its GPIO port and simultaneously sends a transient save command to the controller of the multi-level storage unit 4 via the control bus. This command has the highest priority and will interrupt any normal tasks of the microcontroller itself. Upon receiving the command, the FPGA locks its internal FIFO cache or register set used for protocol testing and data capture; the multi-level storage controller prepares to read data from the cache. Subsequently, the microcontroller, acting as the overall coordinator, initiates a predefined data transfer sequence, writing data from its own cache and data read from the FPGA within a critical time window surrounding the freeze moment (e.g., 100 milliseconds before the exception to 50 milliseconds after the exception) into the tamper-proof, non-volatile transient solidified storage layer. This entire series of operations, from exception detection to secure data write-to-disk, is completed independently, automatically, and reliably by the microcontroller, even without the host operating system being aware of it or even if it has crashed.

[0039] By deeply integrating the hardware-level parallel high-speed processing capabilities of FPGAs with the software-programmable and flexible control capabilities of microcontrollers, a single device can handle both nanosecond-level precision protocol testing and millisecond-level system monitoring and event handling. The hardware implementation of the protocol testing engine within the FPGA ensures extreme stability and determinism in test traffic generation and error statistics, unaffected by software thread scheduling or system interruptions. The microcontroller, acting as the central controller, can dynamically adjust test parameters and respond to external events, endowing the testing process with a high degree of intelligence and adaptability. When a fault occurs, the microcontroller's rapid software judgment and the FPGA's instant hardware freeze capability seamlessly connect. This rapid response mechanism, combining software and hardware, allows for completion of the freeze within milliseconds, ensuring the capture of fleeting transient crash data and reinforcing the reliability of out-of-band monitoring at the processing level.

[0040] The multi-level storage unit 4 is connected to the heterogeneous processing unit 3 and is used for hierarchical data storage.

[0041] Furthermore, the hardware monitoring device based on a PCIe expansion card is also used in the following way: the multi-level storage unit 4 includes: a high-speed cache storage layer for real-time caching of sensor sampling data and protocol test raw data; a transient solidified storage layer, using a non-volatile tamper-proof storage medium, for writing and solidifying data within a preset time window in the high-speed cache storage layer after an abnormal triggering event; and a long-term archive storage layer for storing data transferred from the transient solidified storage layer after system recovery.

[0042] Specifically, the multi-level storage unit 4 is a hierarchical data storage system constructed using various types and characteristics of storage media based on data access speed, data security, and storage capacity requirements. It intelligently stores data in the most suitable medium at different stages of its lifecycle to achieve the optimal balance between performance, reliability, and cost. The multi-level storage unit 4 includes a high-speed cache storage layer, a transient persistence storage layer, and a long-term archive storage layer.

[0043] A cache storage layer is a volatile memory used for temporary, fast storage of real-time data streams. It is typically composed of static random access memory and is characterized by extremely fast read and write speeds (nanosecond level), supporting high-frequency, uninterrupted data writing. However, its contents are completely lost in the event of a power outage, serving as a real-time data buffer.

[0044] Transient-current persistent storage (TPS) is a non-volatile, tamper-proof storage layer specifically designed to securely and quickly preserve critical transient data during sudden abnormal events (such as power outages or resets). Its typical medium is ferroelectric random access memory (FRAM), which combines near-SRAM high-speed write capabilities, almost unlimited read / write endurance, and the characteristic of data retention even when power is lost. Data written to this layer has hardware-level protection, making it difficult to tamper with using conventional methods.

[0045] The long-term archive storage layer is a storage area used for persistent storage of large amounts of historical monitoring logs, complete test reports, and analyzed fault data. It typically uses high-capacity embedded multimedia memory cards as media. Its characteristics include large capacity (usually tens of GB), low cost, and long data retention time, but relatively slow write speed. It is suitable for non-real-time data dumping and archiving.

[0046] During normal system operation, the massive data streams generated by the heterogeneous processing unit 3, such as sensor waveforms sampled by the microcontroller at a frequency of 1kHz and PCIe link transaction summaries captured by the FPGA at line speed, are continuously and cyclically written to the static random access memory (SRAM) of the cache storage layer. The SRAM is logically organized as a circular buffer, where new data constantly overwrites old data, thus always retaining a complete snapshot of the most recent operating period.

[0047] When the microcontroller detects an abnormal trigger event, a critical turning point occurs in the entire storage process. The microcontroller immediately issues a freeze command to the storage controller and FPGA. Within microseconds of receiving the command, the storage controller stops its cyclic overwrite writes to the static random access memory (SRAM) buffer and locks its internal pointer. Based on a preset strategy, such as saving data from 800 milliseconds before to 200 milliseconds after the abnormal trigger, the corresponding data block address and size in the SRAM are precisely calculated.

[0048] A high-priority data transfer task, driven at high speed by a hardware DMA controller or microcontroller unit, is initiated. This task writes a time-slice of data locked in static random access memory (SRAM), including raw sensor data and link status logs, to the transiently persistent random access memory (RAM) at maximum speed. The write operation to RAM requires no complex erase process and has a near-infinite write endurance, making it ideal for storing such bursty, high-intensity critical data. Once the data is written to RAM, it is permanently stored, even if the device is completely powered off. Furthermore, due to its physical characteristics and access control, it offers high tamper resistance.

[0049] When the host system 6 recovers stability or when engineers perform maintenance, the host 6 software can read the fault transient data stored in the random access memory (RAM) via PCIe communication interface 1 or the management communication interface. To free up valuable RAM space to prepare for the next anomaly and to create a complete historical archive, this data, along with other operational logs, is transferred to an embedded multimedia storage card in a large-capacity long-term archive storage layer, forming a system stability archive that can be queried and analyzed over a long period.

[0050] By employing a layered architecture, the high-speed but volatile cache storage layer handles high-frequency write pressure, the fast and robust transient solidified storage layer is responsible for critical data preservation, and the inexpensive and high-capacity long-term archive storage layer handles massive historical storage tasks. This design, at a reasonable cost, constructs an all-around storage system that can handle high-speed data flows, withstand extreme failures, and accommodate long-term data.

[0051] The switchable network topology unit 5 is connected to the heterogeneous processing unit 3 and has a network physical layer interface and a topology switching circuit.

[0052] Furthermore, the hardware monitoring device based on the PCIe expansion card is also used for: the switchable network topology unit 5 supports switching between two working modes: pass-through monitoring mode and loopback pressure mode; wherein, the pass-through monitoring mode passively directs external network traffic to the heterogeneous processing unit 3 for analysis without interrupting the source data flow; the loopback pressure mode connects the internal transmit and receive channels of the network physical layer interface through the topology switching circuit to form a closed loop, which is used to cooperate with the heterogeneous processing unit 3 to perform active network load injection and performance testing.

[0053] Specifically, the switchable network topology unit 5 integrates a standard network physical layer interface and has hardware circuitry that allows for dynamic switching of network connection modes between different preset structures. Essentially, it is a network behavior and role switcher. The switchable network topology unit 5 is a key hardware hub for achieving integrated network monitoring and stress testing, ultimately supporting multi-interface collaborative stress verification. The switchable network topology unit 5 has a network physical layer interface and a topology switching circuit. The network physical layer interface is a standard Ethernet physical layer transceiver chip and its peripheral circuitry, such as transformers and RJ45 interfaces. It is responsible for performing low-level functions such as network signal encoding, decoding, clock recovery, and link negotiation, serving as the physical gateway for electrical connection between the device and external networks. The topology switching circuit is a hardware circuit composed of high-speed analog switches and drive logic. It can physically change the connection relationship between the transmitting and receiving channels of the network physical layer interface, as well as the data path between the interface and the internal processing unit of the device, based on control signals.

[0054] The direct monitoring mode is a network bypass monitoring operation. In this mode, the device acts as a transparent network splitter or network traffic divider. When external network traffic flows through the device, it is copied and directed to the internal heterogeneous processing unit 3 for analysis without interruption or delay of the original data stream. The device itself does not actively send any data. The loopback stress mode is an internal closed-loop testing operation. In this mode, the topology switching circuit physically short-circuits the transmitting and receiving ends of the network physical layer interface, forming an internal signal loopback path. Simultaneously, the internal heterogeneous processing unit 3 becomes the sole source and destination of traffic, actively generating high-speed network test data packets and injecting them into this closed loop for performance and stability testing.

[0055] In direct monitoring mode, the topology switching circuit is configured for bypass monitoring. Bidirectional traffic from the external network, after passing through the PHY chip, is not only transmitted along the original path but also copied. This copy is typically sent to the network analysis engine within the FPGA via the PHY's mirror port or the FPGA's internal logic. The FPGA can then perform real-time statistics on traffic volume, protocol type, packet length distribution, and even deep packet inspection. All of this is completely transparent to both parties in the original network communication, achieving interference-free, passive out-of-band network monitoring.

[0056] When active testing is required, the heterogeneous processing unit 3 commands the topology switching circuit to switch to loopback stress mode. At this time, two key changes occur in the circuit: First, the external network is physically disconnected, and the PHY's transmit differential pairs and receive differential pairs are internally connected to form an electrical signal closed loop; second, logically, the FPGA's Ethernet media access control layer completely takes over this closed loop, making it the sole communication endpoint.

[0057] The FPGA's direct memory access engine begins operation, efficiently reading pre-generated test data patterns from the host's memory or its own cache, assembling them into standard network frames, such as UDP or TCP frames, typically using the maximum transmission unit (MTU) to increase stress, and sending them out through the Ethernet Media Access Control (MAC) layer and PHY. The data frames instantly return to the FPGA's receiver via an internal loopback path. The FPGA's verification logic performs CRC checks, sequence number comparisons, and timestamp recording on each received frame. By statistically analyzing the number of sent and received frames, the number of erroneous frames, and calculating the round-trip time, the core performance and stability indicators of the network interface under extreme loads, such as packet loss rate, bit error rate, and latency jitter, are accurately determined. More importantly, the PCIe link stress test performed simultaneously with the FPGA, combined with the system sensor status monitored by the microcontroller unit, creates a multi-dimensional stress-driven extreme test scenario involving the network, PCIe bus, and system power / temperature on a single hardware platform, accurately reproducing complex system failures.

[0058] The heterogeneous processing unit 3 receives instructions from the host 6 through the PCIe communication interface 1, controls the working mode of the switchable network topology unit 5 according to the instructions from the host 6, and schedules the multi-level storage unit 4 to perform out-of-band monitoring of hardware status, PCIe link protocol layer testing, and network stress testing, and stores the test results in a hierarchical manner.

[0059] Specifically, the host 6 instructions are command data packets, containing opcodes and related parameters, sent to this monitoring device via standard PCIe memory write transactions, and running on the host 6 control software or firmware. The PCIe communication interface 1 of the device receives the instruction data packets from the host 6 at the hardware level and delivers them to the FPGA processor. The PCIe endpoint logic inside the FPGA parses the instruction content and then transmits it to the microcontroller unit via a high-speed internal bus. The real-time control program in the microcontroller unit acts as the overall commander, decoding the instructions.

[0060] The host 6 controls the switching network topology unit 5's operating mode, switching between pass-through monitoring mode and loopback stress mode. The heterogeneous processing unit 3 acts as the central controller, coordinating, starting, and managing multiple hardware units within the device in terms of timing and resource allocation based on preset logic or received instructions. It continuously collects, analyzes, and records key hardware parameters of the host 6 through its own sensors and microcontroller unit. Utilizing the hardware test engine embedded in the FPGA processor, it actively probes and evaluates the protocol layer health of the PCIe link connected to the device, including constructing test traffic through an internal loopback and statistically analyzing protocol errors such as bit errors and retransmissions to assess the link's stability under stress. By setting the switching network topology unit 5 to loopback mode and having the FPGA processor actively generate high-load network traffic, it measures the physical network interface's extreme performance, packet loss rate, latency, and other indicators. Based on the data's real-time nature, importance, and retention period, the microcontroller unit schedules the storage of data into storage media with different characteristics in the multi-level storage unit 4.

[0061] If the host instruction is to perform a comprehensive stability test, the microcontroller unit (MCU) executes a precise scheduling sequence. First, the MCU checks its own sensor status to ensure it is normal. Then, it sends commands to the FPGA via the internal bus to pre-configure the parameters of its internal PCIe protocol test engine and network DMA engine. The MCU sends a control signal to the switching circuit of the switchable network topology unit 5, switching it from the default pass-through monitoring mode to the loopback stress mode. This process is completed within milliseconds, physically disconnecting the external network and establishing an internal loopback. The MCU sends a start trigger signal to the FPGA. The FPGA then starts two tasks in parallel: one is PCIe link protocol layer testing, continuously performing bit error rate statistics in the background at a set bandwidth; the other is network stress testing, injecting and looping back test traffic at high speed through the loopback network interface. Simultaneously, the MCU itself continuously performs out-of-band hardware status monitoring, sampling sensor data such as voltage and temperature at a fixed frequency. Throughout the entire test process, the MCU is responsible for scheduling the data flow. Monitoring data from sensors, PCIe link status summaries reported by the FPGA, and real-time statistical results from network tests are all written in real-time to the SRAM of the cache storage layer for circular caching by the microcontroller unit. The microcontroller unit's monitoring logic continues to run; if its abnormal triggering logic fails, the microcontroller unit immediately issues a freeze command. Subsequently, multi-level storage unit 4 is scheduled to quickly transfer the critical time window data cached in the SRAM to the FRAM of the transient-hardened storage layer, completing the most critical step in hierarchical storage: tamper-proof hardening. After the test, complete logs and reports can be transferred to the embedded multimedia memory card (eMMC) in the long-term archive storage layer. The embedded multimedia memory card (eMMC) is a non-volatile memory that integrates flash memory chips and a controller into a single-chip package, used for storing system logs, configuration data, and long-term operation records.

[0062] The entire closed loop, from instruction parsing and test execution to data storage, is completed by independent hardware resources within the device. Even if the host 6 experiences a software crash during testing, the already started testing and data preservation process will continue, and the final results will still be securely stored in local random access memory, eliminating the risk of test interruption or data loss due to host system instability.

[0063] Furthermore, the hardware monitoring device based on the PCIe expansion card is also used to: manage the communication interface and perform driverless access to the operating system with the extended ROM through a firmware-level communication protocol. The host 6 can identify the hardware monitoring device and read the monitoring status, log data and data stored in the multi-level storage unit 4 before the operating system starts.

[0064] Specifically, the management communication interface is an independent, lower-level communication path established to implement management functions such as device configuration, status query, and data reading. It achieves driverless access to the operating system via a firmware-level communication protocol and the extended ROM. The firmware-level communication protocol is a command-response communication rule that runs on the host 6 system firmware and the device firmware without relying on any host 6 operating system drivers. It is typically implemented by reading and writing specific registers in the PCIe configuration space or designated memory areas. The protocol itself is very concise, containing only necessary handshakes, commands, and status returns. The extended ROM is an optional read-only memory conforming to the PCI / PCIe specification, physically located on the monitoring device. The program code stored inside is automatically discovered and loaded by the host 6 system firmware during the host 6's power-on self-test. Its main responsibility is to initialize the device's management communication interface and report its existence and capabilities to the system firmware, thereby achieving driverless identification. Operating system driverless access refers to the ability of the host system to communicate with the monitoring device and obtain its services without installing and loading any specific operating system kernel drivers. It usually occurs before the operating system starts or after the operating system has completely failed, and it represents the highest level of device manageability.

[0065] At the hardware level, the management communication interface typically reuses the physical link of PCIe communication interface 1, but is independent in protocol logic. A small-capacity extended ROM chip on the hardware monitoring device is pre-programmed with initialization code compliant with the UEFI standard. When host 6 is powered on, after the CPU executes the initial instructions, the system firmware begins to enumerate the PCIe bus. The firmware reads its PCIe configuration space and detects the presence of the extended ROM. Subsequently, the firmware loads the code in the extended ROM into host 6's memory and executes it. This initializes the device's management communication interface to a stable state, registers a simple device protocol with the system firmware, or provides an application programming interface, displays an optional management menu entry on the screen (e.g., accessed by pressing a specific key), or provides an accessible device handle. At this point, the driverless access channel for the operating system is established. Users or management scripts can invoke the firmware-level communication protocol through the interface provided by the firmware. For example, sending a command to read the latest fault log is translated by the protocol into a write operation to the device's PCIe configuration space or a specified memory-mapped input / output register. The microcontroller unit within the device continuously monitors this management interface. After parsing commands, it can read data from the transient solidified storage layer of the multi-level storage unit 4, and then return the data to the host firmware 6 through the same management interface. The entire process is conducted outside the operating system domain. Even if the hard drive is damaged, the operating system crashes, or the operating system is not installed at all, as long as the motherboard and power supply are basically normal, the most critical historical monitoring data and fault records can be safely retrieved.

[0066] The driverless feature means that no software needs to be installed on the target host 6; it's plug-and-play. Maintenance personnel do not need to prepare operating system installation disks or pre-installed environments containing specific drivers; they can access data using any standard UEFI environment. This significantly reduces deployment complexity and the skill threshold for maintenance personnel, strongly supporting its adoption in large-scale existing equipment deployments. Because the management communication interface and protocol run at the system firmware level, its permissions and isolation level are far higher than in ordinary operating system environments, resulting in a lower risk of malware attacks and tampering.

[0067] In summary, the hardware monitoring device based on a PCIe expansion card provided in this application has the following technical advantages: The system communicates with the host 6 via PCIe communication interface 1 using the PCIe protocol. An independent power supply unit 2 draws power from an auxiliary standby power interface and is isolated from the host 6 via a digital isolator. A heterogeneous processing unit 3 is connected to both the PCIe communication interface 1 and the independent power supply unit 2. A multi-level storage unit 4 is connected to the heterogeneous processing unit 3 for hierarchical data storage. A switchable network topology unit 5 is connected to the heterogeneous processing unit 3 and has a network physical layer interface and topology switching circuitry. The heterogeneous processing unit 3 receives commands from the host 6 via the PCIe communication interface 1, controls the operating mode of the switchable network topology unit 5 according to the commands, and schedules the multi-level storage unit 4 to perform out-of-band hardware status monitoring, PCIe link protocol layer testing, and network stress testing, storing the test results hierarchically. In other words, the integrated design of the independent power supply unit 2, heterogeneous processing unit 3, and multi-level storage unit 4 achieves a comprehensive technical effect: even in the event of operating system malfunction or power failure, hardware status monitoring can continue and data is not lost, while simultaneously reducing testing costs and improving system stability verification.

[0068] Example 2: Based on the same inventive concept as the hardware monitoring device based on a PCIe expansion card in Example 1, this application also provides a hardware monitoring method based on a PCIe expansion card. Please refer to the appendix. Figure 2 The hardware monitoring method based on a PCIe expansion card includes: The hardware monitoring device obtains power independent of the host system's power supply through a standby power interface or auxiliary power supply interface, and then supplies power to the internal circuitry of the hardware monitoring device after isolation and conversion. A microcontroller continuously collects data from at least one hardware status sensor, and an FPGA processor continuously monitors the status parameters of the PCIe link. The collected sensor data and link status parameters are written to a high-speed cache storage layer for cyclic caching in real time. The sensor data and link status parameters are compared with preset thresholds. When an abnormal trigger event is detected, the microcontroller issues a freeze command to the FPGA processor and multi-level storage units. In response to the freeze command, the microcontroller and FPGA processor synchronously suspend their current operations, and the data within a preset time window based on the freeze time in the high-speed cache storage layer is written to a tamper-proof, non-volatile, transient, and permanently stored storage layer.

[0069] Specifically, the hardware monitoring device obtains power independent of the host system's power supply through either a standby power interface or an auxiliary power interface. The standby power interface and auxiliary power interface are two physical methods by which the hardware monitoring device obtains independent power from the host. The standby power interface is typically connected to the motherboard's +5VSB line, which remains energized even after the host is soft-shutdown. The auxiliary power interface provides the device with an independent external power socket, serving as a backup or primary power supply. Both are used to decouple the device from the host's main power system.

[0070] After isolation conversion, an independent power domain is provided for all internal circuits, isolated from host failures. Isolation conversion processes the input power from the above interface through an isolated DC-DC converter, changing the voltage level while establishing a high-voltage electrical isolation barrier between the input and output to block noise, surges, and ground interference that may exist on the host side from entering the core circuits inside the monitoring device.

[0071] The microcontroller unit (MCU), with its predetermined real-time clock, periodically polls all connected hardware status sensors, converting analog signals into digital values. Simultaneously, the FPGA processor, utilizing its hardware parallelism, continuously monitors the link status parameters of its PCIe ports. The MCU, acting as the overall scheduler, writes the collected hardware status sensor and link status parameters into the static random access memory (SRAM) of the cache storage layer. This cache storage layer serves as the system's short-term memory, constantly updating and storing the latest system operation trajectory.

[0072] While writing data, the microcontroller also executes core arbitration logic, rapidly comparing each newly acquired sensor data and the link status summary aggregated from the FPGA with preset thresholds stored internally. These preset thresholds are a set of safety range values ​​predefined by the user or system and stored in the microcontroller's non-volatile memory. Each monitored parameter corresponds to an upper and / or lower threshold, used to automatically determine whether the system is in an abnormal state.

[0073] When the microcontroller's decision logic confirms an abnormal triggering event has occurred, such as a CPU core voltage drop of more than 20% within 1 millisecond, and the PCIe link simultaneously reporting a training error, a freeze command is issued to the controllers of the FPGA processor and multi-level memory units within microseconds. An abnormal triggering event is a system anomaly confirmed by the microcontroller's logic to require initiating an emergency data saving process. Triggering conditions typically include sensor data continuously exceeding a preset threshold, sudden changes, or the detection of specific digital signals. The freeze command is a highest-priority hardware control signal or software command issued by the microcontroller, designed to instruct the control logic of the FPGA processor and multi-level memory units to immediately cease normal activities and enter a data locking and saving state.

[0074] The FPGA processor immediately suspends all test and monitoring data stream generation and locks the latest state of its internal cache. The microcontroller also simultaneously suspends its regular acquisition tasks. The microcontroller and FPGA processor work together to perform data recovery, accurately calculating the corresponding data block in the cache storage layer according to a preset strategy. Through a high-speed data channel, the time-slice data is quickly and completely transferred from volatile static random access memory (SRAM) and written to the tamper-proof, non-volatile transient-hardened memory layer. Once the writing is complete, this crucial on-site evidence revealing the root cause of the fault is permanently hardened and preserved, never to be lost even if the device is completely powered off. The tamper-proof, non-volatile transient-hardened memory layer is a storage medium used to securely preserve transient fault data, specifically referring to ferroelectric random access memory. Its non-volatility ensures that data is not lost after power failure; its tamper-proof feature stems from its hardware write protection mechanism and the controlled access design in this device; transient hardening emphasizes its extremely fast write speed and its purpose of preserving instantaneous data.

[0075] Through a complete chain design, from independent power supply to hardware-level freezing and solidification, the system reliably preserves millisecond-level fault transients—which traditional methods would inevitably lose in scenarios involving complete operating system crashes and potential power supply malfunctions—using hardware guarantees. This solves the core problem of missing information in fault diagnosis. It mandates synchronous, continuous, and high-density acquisition and caching of hardware and bus protocol states, enabling the preserved data to be analyzed for precise causal relationships, much like multi-channel oscilloscope waveforms. The data is ultimately stored in tamper-proof non-volatile memory and read through a firmware-level interface, ensuring the security and reliability of the entire data chain from generation and storage to retrieval.

[0076] Furthermore, the hardware monitoring method based on a PCIe expansion card includes: acquiring test instructions from the host, controlling the switchable network topology unit to enter the corresponding test working mode, and executing the test process; wherein, the test working mode includes a PCIe protocol layer loopback test step: the FPGA processor enables the link loopback injection mode according to the configuration parameters, continuously generates pseudo-random code streams to form the test load, counts symbol anomalies, packet errors and retransmission counts in the receiving channel, and comprehensively generates bit error rate statistics results.

[0077] Specifically, the PCIe communication interface of the hardware monitoring device receives test commands from the host, which are command data packets used to start and configure the test process, including test type, test parameters, and control flags. The microcontroller parses the test commands, extracts the configuration parameters, and controls the switchable network topology unit to enter the corresponding test working mode, including two types: PCIe protocol layer loopback test and network stress test, each targeting different hardware interfaces.

[0078] PCIe protocol layer loopback testing is an active testing method designed to evaluate the stability and signal integrity of the PCIe link protocol layer. The core principle is that the test card sends specific test data to the host through its PCIe interface and requests the host (through the driver or firmware) to return the received data along the original path (loopback). The test card then compares the sent and received data, counts transmission errors, and simulates bidirectional communication, but in reality, it tests the complete data path from the test card to the host and back.

[0079] Link loopback injection mode is a working state of the protocol test engine within the FPGA processor. In this mode, the internal logic of the FPGA is configured to actively generate and send test data streams; simultaneously prepare to receive data streams looping back from the host; and internally implement real-time comparison of sent and received data.

[0080] The microcontroller performs two key operations: First, it precisely configures the aforementioned test parameters to the protocol test engine within the FPGA processor via the internal bus; second, depending on the instruction requirements, it may need to handshake with the host-side test agent program to ensure the host is ready to enter loopback mode. After configuration, the microcontroller sends a start command to the FPGA. The FPGA's protocol test engine then enters link loopback injection mode, and its internal hardware logic begins high-speed generation of pseudo-random bitstreams. This bitstream is encapsulated to form transaction layer data packets conforming to the PCIe protocol format, such as memory write request packets. These test data packets are injected into the PCIe link connected to the host via the FPGA's PCIe physical layer at a specified rate and width. Upon receiving these data packets, the host-side test agent program does not submit them to the upper-layer application but immediately encapsulates their contents into new response packets, such as completion messages, and sends them back to the device via the same PCIe link, forming an application-layer loopback. The FPGA's receiving logic captures these loopback data packets. The dedicated hardware circuitry in the protocol testing engine performs two key tasks in real time: first, it compares the received data payload bit-by-bit with the initially transmitted pseudo-random sequence to count the number of bit errors; second, it analyzes data packets and link status to count symbol anomalies, packet errors, and the number of retransmissions caused by errors. The FPGA summarizes these metrics at set statistical intervals (e.g., per second) to generate a comprehensive bit error rate (BER) statistical result. The BER is typically calculated as: BER = number of erroneous bits / total number of transmitted bits. Simultaneously, the number of symbol errors, packet errors, and retransmissions per second are also recorded. These real-time results are transmitted to the microcontroller unit, which writes them into the cache storage layer and can selectively report them to the host control software in real time via the PCIe interface.

[0081] Symbol anomalies, specifically in the PCIe context, refer to invalid or unexpected control symbols decoded at the physical layer receiver after serial-to-parallel conversion and clock data recovery. Examples include SKP, ELB, and 8b / 10b / 128b / 130b decoding errors, typically caused by signal integrity degradation. Packet errors, at the data link layer, refer to cyclic redundancy check (CRC) errors or sequence number errors in received transaction layer data packets, indicating that the packet content has been altered during transmission. Retransmission counts, at the data link layer, refer to the number of times the receiver detects packet errors and sends a negative acknowledgment to the sender, requesting the retransmission of a specific data packet.

[0082] By analyzing core protocol-layer metrics such as symbol anomalies, bit error rate, and retransmission counts, we can not only determine whether a link is working or not, but also accurately assess its health. For example, a continuously increasing number of symbol anomalies may indicate a slow degradation of signal integrity, providing early warning before serious data errors and system failures occur, thus enabling predictive maintenance.

[0083] Furthermore, the hardware monitoring method based on a PCIe expansion card includes: the test working mode further includes: controlling the switchable network topology unit to switch to internal loopback mode, so that the sending end and receiving end of the network physical layer interface form a closed loop; constructing network test data packets through the direct memory access engine of the FPGA processor, sending and receiving them through the switchable network topology unit, and performing cyclic redundancy check on the received test data packets, calculating the delay based on the sending and receiving timestamps; statistically analyzing the network packet loss rate, error rate, and delay distribution indicators based on the number of sent packets, the number of received packets, the number of cyclic redundancy check error packets, and the delay, and generating log data containing test results after the test process is completed.

[0084] Specifically, the microcontroller performs hardware control operations, sending commands to the switchable network topology unit 5 to drive its internal topology switching circuit, switching the network interface from pass-through monitoring mode to internal loopback mode. This operation is completed in milliseconds, physically establishing a closed-loop path for sending and receiving, thus preparing for subsequent traffic loopback testing.

[0085] The Direct Memory Access (DMA) engine within the FPGA processor is activated. This DMA engine retrieves data from pre-generated data templates or dynamic sequences and rapidly assembles it into complete Ethernet frames. Each frame is assigned a unique, incrementing sequence number, and a transmission timestamp generated by the FPGA's high-precision clock is embedded in the frame header or a specific field. The assembled data frames are continuously ejected by the DMA engine in a back-to-back, almost seamless manner through the FPGA's internal Ethernet Media Access Controller and the network physical layer interface in loopback mode. The throughput can be precisely controlled, from line speed to a specific percentage of bandwidth. The transmitted electrical signals return instantaneously to the receiver through the internal closed loop. The FPGA's receive logic captures these frames and initiates pipelined processing. First, it performs cyclic redundancy check (CRC) to determine if the frame is corrupted. Then, it extracts the sequence number and transmission timestamp from the frame and immediately adds a receive timestamp. For each received packet, the FPGA's hardware counters are updated in real-time: total received packets and number of CRC error packets. Simultaneously, the single-packet delay is calculated as receive timestamp - transmission timestamp, and this delay value is updated in the delay statistics module. Cyclic Redundancy Check (CRC) is a 32-bit checksum field carried at the end of an Ethernet frame. The sender calculates a CRC value based on all the data in the frame and appends it to the frame end; the receiver recalculates the CRC for the received data and compares it with the CRC value at the frame end. If the two do not match, it indicates that a bit error occurred during data transmission, and the frame is recorded as a CRC error packet.

[0086] Throughout the testing process, the microcontroller unit periodically reads these raw counters and statistical snapshots from the FPGA. Based on these snapshots, the microcontroller unit calculates and records key performance indicators (KPIs) in real time, including packet loss rate, error rate, average latency, maximum latency, and latency jitter. After the test process ends, the microcontroller unit summarizes the statistical results of all periods, generating a structured log data containing detailed metrics. This log includes not only the final global statistics but may also include snapshots of abnormal events during the test. The microcontroller unit schedules multi-level storage units to write this complete test log, along with any raw sample data that may be saved, to a long-term archive storage layer, forming a traceable test record. Packet loss rate is the percentage difference between the total number of packets sent and the total number of packets successfully received during the test. The formula is Packet Loss = (Number of packets sent - Number of packets received) / Number of packets sent × 100%, which is a basic indicator for measuring the processing capacity of a network interface or system under high load. Error rate is the CRC error rate, which is the percentage of received packets whose CRC check fails out of the total number of received packets. The formula is: Error Rate = (Number of CRC Error Packets / Number of Received Packets) × 100%. It reflects the transmission quality at the physical layer and data link layer. Delay distribution is a statistical analysis of the delay values ​​calculated from all successfully looped-back packets. The resulting statistical characteristics include not only average delay and maximum / minimum delay, but more importantly, delay jitter (i.e., standard deviation) and the percentile distribution of delay, such as P99 delay, where 99% of packets have a delay below this value. This reflects the stability and determinism of the system's network traffic processing.

[0087] By generating line-rate traffic and internal hardware loopback through hardware DMA, this method enables accurate measurement of the absolute performance of network interfaces in a fully controllable environment free from external interference. High-intensity stress testing not only tests the network PHY chip itself but also forces data packets to traverse the system PCIe bus, consuming host memory bandwidth and CPU interrupt resources. Therefore, packet loss and latency jitter observed during testing often reveal system-level bottlenecks, such as insufficient PCIe bandwidth, inefficient drivers, or memory access conflicts, thus extending testing from single-interface testing to system-level stability verification.

[0088] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The hardware monitoring device and specific example based on a PCIe expansion card in the foregoing embodiment one are also applicable to the hardware monitoring method based on a PCIe expansion card in this embodiment. Through the foregoing detailed description of a hardware monitoring device based on a PCIe expansion card, those skilled in the art can clearly understand the hardware monitoring method based on a PCIe expansion card in this embodiment. Therefore, for the sake of brevity, it will not be described in detail here.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0090] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application also intends to include such modifications and variations.

Claims

1. A hardware monitoring device based on a PCIe expansion card, characterized in that, include: PCIe communication interface, used for PCIe protocol communication with the host; An independent power supply unit draws power from the auxiliary standby power interface and is isolated from the host side by a digital isolator; A heterogeneous processing unit, which is connected to a PCIe communication interface and an independent power supply unit; A multi-level storage unit, connected to the heterogeneous processing unit, is used for hierarchical data storage; A switchable network topology unit is connected to the heterogeneous processing unit and has a network physical layer interface and a topology switching circuit. The heterogeneous processing unit receives host instructions through the PCIe communication interface, controls the working mode of the switchable network topology unit according to the host instructions, and schedules the multi-level storage unit to perform out-of-band hardware status monitoring, PCIe link protocol layer testing, and network stress testing, and stores the test results in a hierarchical manner.

2. The hardware monitoring device based on a PCIe expansion card according to claim 1, characterized in that, The heterogeneous processing unit includes an FPGA processor and a microcontroller unit; The FPGA processor is configured with a protocol testing engine, which is used to construct a pseudo-random bit stream and calculate the bit error rate. The microcontroller communicates with the FPGA processor via a high-speed internal bus for parameter configuration and test scheduling.

3. The hardware monitoring device based on a PCIe expansion card according to claim 2, characterized in that, The microcontroller unit is used to run a real-time control program, perform sensor sampling, threshold comparison, abnormal triggering logic, and multi-level storage scheduling. The microcontroller unit is also configured to send a freeze command to the FPGA processor and the multi-level storage unit when an abnormal triggering event is detected, and to simultaneously lock and save key state data before and after the abnormality occurs.

4. The hardware monitoring device based on a PCIe expansion card according to claim 1, characterized in that, The independent power supply unit also includes a multi-channel isolated DC-DC power conversion module, which is used to isolate and convert the independent power obtained by the independent power supply unit from the auxiliary standby power interface to generate multiple source domains to power the monitoring and test circuits.

5. The hardware monitoring device based on a PCIe expansion card according to claim 1, characterized in that, The multi-level storage unit includes: A high-speed cache storage layer is used to cache sensor sampling data and protocol test raw data in real time; The instantaneous solidified storage layer uses a non-volatile, tamper-proof storage medium to write and solidify data within a preset time window in the cache storage layer after an abnormal triggering event. A long-term archive storage layer is used to store data transferred from the transient solidified storage layer after system recovery.

6. The hardware monitoring device based on a PCIe expansion card according to claim 1, characterized in that, The switchable network topology unit supports switching between two operating modes: pass-through monitoring mode and loopback stress mode; The direct monitoring mode passively directs external network traffic to the heterogeneous processing unit for analysis without interrupting the source data stream. The loopback pressure mode connects the transmit and receive channels of the network physical layer interface internally through a topology switching circuit to form a closed loop, which is used to cooperate with the heterogeneous processing unit to perform active network load injection and performance testing.

7. The hardware monitoring device based on a PCIe expansion card according to claim 1, characterized in that, Also includes: The management communication interface enables driverless access to the operating system via a firmware-level communication protocol and an extended ROM. Before the operating system starts, the host can identify the hardware monitoring device and read the monitoring status, log data, and data stored in the multi-level storage unit.

8. A hardware monitoring method based on a PCIe expansion card, characterized in that, The method, executed by the hardware monitoring device based on a PCIe expansion card according to any one of claims 1 to 7, comprises: The hardware monitoring device obtains power independent of the host system power supply through the standby power interface or auxiliary power supply interface, and then supplies power to the internal circuits of the hardware monitoring device after isolation and conversion. The microcontroller continuously collects data from at least one hardware status sensor, and the FPGA processor continuously monitors the status parameters of the PCIe link. The collected sensor data and link status parameters are written to the high-speed cache storage layer in real time for cyclic caching. The sensor data and link status parameters are compared with a preset threshold. When an abnormal triggering event is detected, the microcontroller sends a freeze command to the FPGA processor and the multi-level storage unit. In response to the freeze command, the microcontroller and the FPGA processor synchronously suspend the current operation and write the data in the cache storage layer within a preset time window based on the freeze time into the tamper-proof non-volatile transient solidified storage layer for solidification and preservation.

9. The hardware monitoring method based on a PCIe expansion card according to claim 8, characterized in that, The method further includes: It receives test commands from the host, controls the switchable network topology unit to enter the corresponding test working mode, and executes the test process; The test working mode includes the PCIe protocol layer loopback test steps: the FPGA processor enables the link loopback injection mode according to the configuration parameters, continuously generates pseudo-random code streams to form the test load, counts symbol anomalies, packet errors and retransmissions in the receiving channel, and generates a comprehensive bit error rate statistical result.

10. The hardware monitoring method based on a PCIe expansion card according to claim 9, characterized in that, The test working mode also includes: Control the switchable network topology unit to switch to internal loopback mode, so that the transmitting end and receiving end of the network physical layer interface form a closed loop; Network test data packets are constructed using the direct memory access engine of the FPGA processor, sent and received via the switchable network topology unit, and cyclic redundancy check is performed on the received test data packets. The delay is calculated based on the timestamps of sending and receiving. Based on the number of packets sent, received, cyclic redundancy check error packets, and latency, statistical analysis is performed on network packet loss rate, error rate, and latency distribution indicators. After the test process is completed, log data containing the test results is generated.

Images