Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that is miniaturized and has high capacitance while maintaining high high-temperature reliability. [Solution] A multilayer ceramic capacitor 1 comprising an inner layer portion 100 including a plurality of inner dielectric layers 20i and a plurality of inner electrode layers 30 that are alternately stacked in the stacking direction T, wherein the line coverage of the end in the width direction W of the first outer inner electrode layer E1 closest to the main surface TS is lower than the line coverage of the end in the width direction W of the second outer inner electrode layer E2 facing the first outer inner electrode layer E1, and Mg or Mn segregates in the separated region of the end of the first outer inner electrode layer E1.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and further dielectric layers are laminated on the upper and lower surfaces thereof, and a pair of external electrodes formed on both end faces of the laminate. The internal electrode layer is formed by a counter electrode portion that forms capacitance and a lead-out electrode portion that extends from the counter electrode portion toward the external electrode.

[0003] In recent years, with the progress of electronics technology, in order to miniaturize and increase the capacitance of multilayer ceramic capacitors, technological development has been promoted to reduce the thickness of dielectric layers and internal electrode layers and increase the number of dielectric layers and internal electrode layers to be laminated.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the thickness of the dielectric layer and the internal electrode layer is reduced, it becomes difficult to form an appropriate layer structure, and a broken portion is likely to occur in the dielectric layer or the internal electrode layer. In particular, at the end of the laminate, since pressure is applied during manufacturing, the continuity of the internal electrode layer is likely to be low, which is likely to cause a decrease in the high-temperature reliability of the multilayer ceramic capacitor.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor having high high-temperature reliability while achieving miniaturization and increased capacitance.

Means for Solving the Problems

[0007] The inventors of the present invention have found that the high-temperature reliability of a multilayer ceramic capacitor can be improved by reducing the line coverage at the widthwise edge of the first outer internal electrode layer closest to the main surface of the laminate, and by segregating a specific metal component in the divided region at the widthwise edge of the first outer internal electrode layer, thereby completing the present invention.

[0008] In other words, the present invention provides a laminate comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction; and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction; two side surfaces opposite to each other in the width direction perpendicular to the stacking direction; and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction. A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The line coverage at the widthwise end of the first outer internal electrode layer closest to the main surface is lower than the line coverage at the widthwise end of the second outer internal electrode layer facing the first outer internal electrode layer. This is a multilayer ceramic capacitor in which Mg or Mn is segregated in the separated region at the end of the first outer inner electrode layer. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is miniaturized and has a large capacitance while possessing high high-temperature reliability. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view showing a multilayer ceramic capacitor. [Figure 2] Figure 1 shows a cross-sectional view (LT section) of a multilayer ceramic capacitor along line II-II. [Figure 3] Figure 1 shows a cross-sectional view (WT section) of a multilayer ceramic capacitor along line III-III. [Figure 4] Figure 1 is a schematic diagram showing the structure of the inner layer of a multilayer ceramic capacitor. [Figure 5] This is a magnified view of region V shown in Figure 3. [Modes for carrying out the invention]

[0011] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. Also, components described in the specification may be omitted in the drawings, or their quantities may be omitted.

[0012] (Multilayer ceramic capacitor) Figure 1 is a perspective view showing a multilayer ceramic capacitor, Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line II-II, and Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line III-III. Figure 4 is a schematic diagram showing the structure of the inner layer of the multilayer ceramic capacitor shown in Figure 1. Figure 5 is an enlarged view of region V shown in Figure 3. The multilayer ceramic capacitor 1 shown in Figures 1 to 5 comprises a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] Figures 1 to 3 show the XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10. Accordingly, the cross section shown in Figure 2 is also called the LT cross section, and the cross section shown in Figure 3 is also called the WT cross section. Furthermore, the length direction L, width direction W, and stacking direction T do not necessarily have to be orthogonal to each other; they may intersect.

[0014] The size of the multilayer ceramic capacitor is preferably such that the dimension in the length direction L is 0.2 mm or more and 10 mm or less, the dimension in the width direction W is 0.1 mm or more and 10 mm or less, and the dimension in the stacking direction T is 0.1 mm or more and 10 mm or less.

[0015] (Stacked body) The stacked body 10 has a substantially rectangular parallelepiped shape, and has a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L. Concavities and convexities may be provided on the surfaces of each surface, or they may be rough. When there is no need to particularly distinguish and explain the first main surface TS1 and the second main surface TS2, they are collectively referred to as the main surface TS. When there is no need to particularly distinguish and explain the first end surface LS1 and the second end surface LS2, they are collectively referred to as the end surface LS. When there is no need to particularly distinguish and explain the first side surface WS1 and the second side surface WS2, they are collectively referred to as the side surface WS for explanation.

[0016] It is preferable that the corners and ridge lines of the stacked body 10 are rounded. A corner is a portion where three surfaces of the stacked body 10 intersect, and a ridge line portion is a portion where two surfaces of the stacked body 10 intersect.

[0017] As shown in FIGS. 2 and 3, the stacked body 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in the stacking direction T. Further, the stacked body 10 has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged so as to sandwich the inner layer portion 100.

[0018] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the functions required for the inner layer portion 100 and the outer layer portion 200 are different. For example, a high dielectric constant is required for the inner dielectric layer 20i, and high moisture resistance, weather resistance, and strength are required for the outer dielectric layer 20o. Therefore, the dielectric layer constituting the inner layer portion 100 will be described as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be described as the outer dielectric layer 20o. However, when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively described as the dielectric layer 20.

[0019] (Inner layer portion) FIG. 4 schematically shows the structure of the inner layer portion 100. The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other through the inner dielectric layer 20i. The inner layer portion 100 is a portion that generates capacitance and functions substantially as a capacitor.

[0020] As the material of the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3, etc. as a main component can be used. Further, as the material of the dielectric layer 20, an Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, etc. may be added as a sub-component.

[0021] The thickness of the inner dielectric layer 20i is not particularly limited, but it is preferably, for example, 0.2 μm or more and 15 μm or less. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0022] (Outer layer portion) The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30 and the first main surface TS1, and the second outer layer portion 202 is disposed between the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30 and the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0023] The outer layer 200 is formed of an insulating material. The first outer layer 201 and the second outer layer 202 can each be composed of multiple outer dielectric layers 20o, or they may be composed of a single outer dielectric layer 20o. Furthermore, the outer dielectric layer 20o can be composed of the same dielectric material as the inner dielectric layer 20i, but it may contain different components from the inner dielectric layer 20i depending on the desired function.

[0024] (Internal electrode layer) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

[0026] The opposing electrode portion 311 and the opposing electrode portion 321 face each other in the stacking direction T of the laminate 10 via the inner dielectric layer 20i. The shape of the opposing electrode portion 311 and the opposing electrode portion 321 is not particularly limited and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are parts that generate capacitance and function substantially as capacitors.

[0027] The lead-out electrode portion 312 extends from the counter electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead-out electrode portion 322 extends from the counter electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The widthwise lengths W of the counter electrode portion 311 and the lead-out electrode portion 312 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed first end face LS1. The widthwise lengths W of the counter electrode portion 321 and the lead-out electrode portion 322 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed second end face LS2.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 mainly contain metallic Ni. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also mainly contain at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, or may contain other components. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition system as the ceramic contained in the inner dielectric layer 20i as components other than the main component. In this specification, the main component metal refers to the metal component with the highest weight percentage.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited.

[0031] Furthermore, a method for measuring the thickness of the inner dielectric layer 20i and the inner electrode layer 30 is to observe the WT cross-section near the center in the length direction L of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the width direction W, or further, the average of measurements taken at multiple locations in the lamination direction T.

[0032] As shown in Figure 3, the laminate 10 has, in the width direction W, an electrode-facing portion W30 on which the internal electrode layer 30 faces, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode-facing portion W30. The first side gap portion WG1 is located between the electrode-facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode-facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but include only the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also referred to as W gaps.

[0033] As shown in Figure 2, the laminate 10 has, in the longitudinal direction L, an electrode-facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode-facing portion L30 and the first end face LS1, and the second end gap portion LG2 is located between the electrode-facing portion L30 and the second end face LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap portion LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the inner dielectric layer 20i, and the second end gap portion LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap portion LG1 functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap portion LG2 functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap portion LG1 and the second end gap portion LG2 are also called L gaps.

[0034] The electrode opposing portion L30 is located where the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32 are located. The leading electrode portion 312 of the first internal electrode layer 31 is located where the first end gap portion LG1 is located, and the leading electrode portion 322 of the second internal electrode layer 32 is located where the second end gap portion LG2 is located.

[0035] One method for measuring the thickness of the laminate 10 is to observe the LT cross section near the center of the width W of the laminate exposed by polishing, or the WT cross section near the center of the length L of the laminate exposed by polishing, using a scanning electron microscope. Alternatively, each value may be the average of measurements taken at multiple locations in the length L or width W. Similarly, a method for measuring the length of the laminate 10 is, for example, to observe the cross-section LT near the center W in the width direction of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction T. Similarly, a method for measuring the width of the laminate 10 is, for example, to observe the WT cross-section near the center in the longitudinal direction L of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction T.

[0036] (external electrode) The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0037] The first external electrode 41 is positioned on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0038] The second external electrode 42 is positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may consist only of the plating layer 416, and the second external electrode 42 may consist only of the plating layer 426.

[0040] The base electrode layer 415 and the base electrode layer 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. In addition, the metal may mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0041] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0042] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-described firing layer, or it may be formed directly on the laminate without forming a firing layer.

[0043] The resin layer is formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate using a coating method and then heating it. The resin layer may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple resin layers.

[0044] The thickness of each layer of the base electrode layer 415 and base electrode layer 425, which are fired layers or resin layers, is not particularly limited and may be 2 μm or more and 220 μm or less.

[0045] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.

[0046] The plating layer 416 covers at least a portion of the underlying electrode layer 415, and the plating layer 426 covers at least a portion of the underlying electrode layer 425. The plating layers 416 and 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0047] The plating layers 416 and 426 may each be formed from multiple layers. Preferably, they are a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The plating layers 416 and 426 can also be a three-layer structure by laminating Cu plating, Ni plating, and Sn plating, respectively. The outermost layer may be Au plating.

[0048] The thickness of each layer of plating layer 416 and plating layer 426 is not particularly limited and may be 1 μm or more and 10 μm or less.

[0049] (Divided area) Figure 5 is an enlarged view of region V shown in Figure 3. The multilayer ceramic capacitor 1 according to this disclosure includes a region A at the edge of the internal electrode layer 30 in the width direction W, which is a region with lower line coverage than the central part of the internal electrode layer 30 in the width direction W. The end region A of the internal electrode layer 30 in the width direction W comprises an internal electrode presence region a1 and a divided region a2. The internal electrode presence region a1 is the region where the internal electrode layer exists, and the divided region a2 is the region between two adjacent internal electrode presence regions a1 in the width direction W. In other words, at the end of the internal electrode layer 30 in the width direction W, there is a divided region a2 formed by the division of the internal electrode layer 30. The presence of a divided region in the internal electrode layer 30 affects the continuity of the internal electrode layer, and can therefore be evaluated by measuring the linear coverage of the internal electrode layer. In other words, the larger the area occupied by the divided region, the lower the linear coverage of the internal electrode layer 30 will be.

[0050] (Line coverage) Line coverage is an indicator of the continuity of the conductive components constituting the internal electrode layer. Comparing the first outer internal electrode layer E1, which is closest to the main surface TS of the laminate 10, with the second outer internal electrode layer E2, which faces the first outer internal electrode layer E1 via the dielectric layer 20, the line coverage at the end of the first outer internal electrode layer E1 in the width direction W is lower than the line coverage at the end of the second outer internal electrode layer E2 in the width direction W. At the end of the first outer internal electrode layer E1 in the width direction W, there are more divided regions a2 formed by the division of the internal electrode layer compared to the end of the second outer internal electrode layer E2.

[0051] (Measurement of line coverage) Line coverage is measured by observing the WT cross-section of a multilayer ceramic capacitor with the internal electrode layers exposed. The line coverage of all internal electrode layers 30 in the width direction W is measured, including the line coverage of the edges in the width direction W of the first outer internal electrode layer E1 and the edges in the width direction W of the second outer internal electrode layer E2. Line coverage is measured for the edges of the internal electrode layer 30 on the first side surface WS1 and the edges of the internal electrode layer 30 on the second side surface WS2. Here, the range from the edge in the width direction W of the internal electrode layer 30 to the center of the internal electrode layer 30 in the width direction W is measured as the range corresponding to the edge in the width direction W of the internal electrode layer. The internal electrode layer 30 has regions where conductive components are present and regions where conductive components are not present. Line coverage is calculated in the SEM image as the ratio of the length in the width direction W of the region actually occupied by the conductive components to the length in the width direction W of the internal electrode layer when the presence or absence of conductive components is not considered, that is, the ratio of the length in the width direction W of the internal electrode layer excluding the region where conductive components are not present to the length in the width direction W of the internal electrode layer when the presence or absence of conductive components is not considered. The magnification of the SEM should be between 1000x and 5000x, but 2000x is preferable. During measurement, conditions such as acceleration voltage and magnification should be kept fixed.

[0052] (segregation) At the end of the first outer internal electrode layer E1 in the width direction W, there is a divided region a2 formed by the division of the internal electrode layer, and Mg or Mn is segregated in this divided region a2. In Figure 5, the portion where Mg or Mn is segregated is indicated by the symbol S.

[0053] Furthermore, the second outer internal electrode layer E2 also has a divided region a2 at its widthwise end W, where Mg or Mn segregates. However, the second outer internal electrode layer E2 has fewer divided regions a2 than the first outer internal electrode layer E1, and the amount of Mg or Mn segregating in the divided region a2 of the second outer internal electrode layer E2 is less than the amount of Mg or Mn segregating in the divided region a2 of the first outer internal electrode layer E1.

[0054] The type and amount of precipitates due to segregation can be confirmed by cutting the multilayer ceramic capacitor and performing wavelength-dispersive X-ray analysis (WDX) on the WT cross-section where the internal electrode layer is exposed.

[0055] In the multilayer ceramic capacitor 1 according to this embodiment, high-temperature reliability is improved by reducing the line coverage at the end of the first outer internal electrode layer E1 in the width direction W that is closest to the main surface TS of the laminate 10, and by causing Mg or Mn segregation in the divided region at the end of the first outer internal electrode layer E1 in the width direction W.

[0056] If a divided region a2 is not placed in the internal electrode layer, and Mg or Mn segregates in the internal electrode region a1, the thickness of the internal electrode layer 30 in the stacking direction T increases in the segregated portion. As a result, the thickness of the dielectric layer 20 around the segregated portion decreases, and high-temperature reliability decreases. On the other hand, as in this embodiment, if a divided region a2 is placed in the internal electrode layer, Mg or Mn segregates in the divided region a2. Therefore, the thickness of the internal electrode layer in the stacking direction T does not increase, and the thickness of the dielectric layer 20 around the segregated portion can be kept constant, improving high-temperature reliability.

[0057] It is preferable to make the line coverage at the end of the first outer internal electrode layer E1 in the width direction W lower than the line coverage at any of the other internal electrode layers in the width direction W, and to segregate a large amount of Mg or Mn in the separated region a2 at the end of the first outer internal electrode layer E1 in the width direction W, as this improves the effect of enhancing high-temperature reliability.

[0058] It is preferable that the line coverage at the edges of the first outer internal electrode layer E1 in the width direction W is 76% or less. If the line coverage exceeds 76%, the partitioned region a2 decreases, and Mg or Mn will segregate not only in the partitioned region a2 but also in the dielectric layer 20, making it difficult to achieve the desired effect due to Mg or Mn segregation. Furthermore, Mg or Mn will segregate in the internal electrode region a1, leading to a decrease in high-temperature reliability.

[0059] (Manufacturing of multilayer ceramic capacitors) Next, we will explain an example of a manufacturing method for multilayer ceramic capacitors.

[0060] First, a ceramic green sheet for forming the dielectric layer and a conductive paste for the internal electrodes are prepared. The conductive paste for the internal electrodes contains a binder and a solvent, but known organic binders and organic solvents can be used. The conductive paste for the internal electrodes forms the internal electrode layer.

[0061] Next, a conductive paste for internal electrodes is printed onto the ceramic green sheet in a predetermined pattern, for example, by screen printing or gravure printing, thereby forming the internal electrode pattern. By adjusting the thickness of the conductive paste and printing, the formed internal electrode layer is adjusted to achieve a predetermined line coverage.

[0062] Next, a predetermined number of outer layer ceramic green sheets without internal electrode patterns are stacked, followed by sequentially stacking ceramic green sheets with internal electrodes formed on top, and then a predetermined number of outer layer ceramic green sheets are stacked on top of those to create a laminated sheet. The ceramic green sheets form the dielectric layer 20 that constitutes the multilayer ceramic capacitor 1.

[0063] The resulting laminated sheet is pressed in the lamination direction T by means of a hydrostatic press or other means to produce a laminated block. Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other means.

[0064] Furthermore, the laminated body 10 is fabricated by firing the laminated chips. The firing temperature at this time depends on the dielectric and internal electrode materials, but is preferably between 900°C and 1300°C. Furthermore, by adjusting the oxygen concentration within a temperature range of 900°C to 1300°C, it is possible to arrange a large amount of Mg or Mn segregation at the widthwise end W of the first outer inner electrode layer E1 closest to the main surface.

[0065] Next, the conductive paste for the base electrode layer 415 is applied to the first end face LS1 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Similarly, the conductive paste for the base electrode layer 425 is applied to the second end face LS2 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Subsequently, the base electrode layers 415 and 425, which are fired layers, are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0066] As described above, the base electrode layers 415 and 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and heating it, or the base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0067] Subsequently, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through these steps, a multilayer ceramic capacitor 1 is obtained.

[0068] Although embodiments of the present invention have been described, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention.

[0069] This invention includes the following combinations.

[0070] <1> A laminate comprising an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction perpendicular to the stacking direction, and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The line coverage at the widthwise end of the first outer internal electrode layer closest to the main surface is lower than the line coverage at the widthwise end of the second outer internal electrode layer facing the first outer internal electrode layer. A multilayer ceramic capacitor in which Mg or Mn is segregated in the divided region at the end of the first outer inner electrode layer.

[0071] <2> The linear coverage of the end of the first outer inner electrode layer is 76% or less. <1> The multilayer ceramic capacitor described above.

[0072] <3> The line coverage of the end of the first outer internal electrode layer is lower than the line coverage of any of the widthwise ends of the other plurality of internal electrode layers. <1> or <2> The multilayer ceramic capacitor described above.

[0073] <4> The amount of Mg or Mn segregated in the divided region at the end of the second outer inner electrode layer is less than the amount of Mg or Mn segregated in the divided region at the end of the first outer inner electrode layer. <1> ~ <3> A multilayer ceramic capacitor as described in any of the following. [Explanation of symbols]

[0074] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Counter electrode section 312 Extraction electrode section 32 Second internal electrode layer 321 Counter electrode section 322 Extraction electrode section 40 External electrode 41 First external electrode 415 Base electrode layer 416 Plating layer 42 Second external electrode 425 Base electrode layer 426 Plating layer 100 Inner layer 200 Outer layer 201 First outer layer 202 Second outer layer E1 1st outer internal electrode layer E2 Second outer internal electrode layer L30 Electrode facing part LG1 First end gap section LG2 Second end gap section W30 Electrode facing part WG1 First side gap section WG2 Second side gap section L (Length direction) T Stacking direction W (width direction) LS end face LS1 First end face LS2 Second end face TS Main Surface TS1 First main surface TS2 Second main surface WS side WS1 First Aspect WS2 Second Aspect

Claims

1. A laminate comprising an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction perpendicular to the stacking direction, and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The line coverage at the widthwise end of the first outer internal electrode layer closest to the main surface is lower than the line coverage at the widthwise end of the second outer internal electrode layer facing the first outer internal electrode layer. A multilayer ceramic capacitor in which Mg or Mn is segregated in the divided region at the end of the first outer inner electrode layer.

2. The multilayer ceramic capacitor according to claim 1, wherein the line coverage of the end of the first outer internal electrode layer is 76% or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the line coverage of the end of the first outer internal electrode layer is lower than the line coverage of any of the widthwise ends of the other plurality of internal electrode layers.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the amount of Mg or Mn segregated in the divided region at the end of the second outer inner electrode layer is less than the amount of Mg or Mn segregated in the divided region at the end of the first outer inner electrode layer.

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