Multilayer ceramic electronic components

Abstract

To provide a multilayer ceramic electronic component that can suppress deterioration of flexural strength and moisture resistance while suppressing an excessive increase in electrical resistance. [Solution] In the multilayer ceramic capacitor 1, the first external electrode layer 20 includes a first base electrode layer 32, a first conductive resin layer 34 disposed on the first base electrode layer 32, and a first plating layer 36 disposed on the first conductive resin layer 34. The first plating layer 36 includes a plating layer body 41 and a connection region 42 that extends from the plating layer body 41 through the first conductive resin layer 34 and is connected to the first base electrode layer 32. The connection portion 43 between the connection region 42 and the first base electrode layer 32 is in the vicinity of the first internal electrode layer 6A.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] As an example of a multilayer ceramic electronic component, there is a multilayer ceramic capacitor. Patent Document 1 describes a multilayer ceramic capacitor using an external electrode including a resin electrode layer. The resin electrode layer is arranged to cover a thick-film Cu layer as a base electrode layer. The resin electrode layer is covered with a Ni plating layer and a Sn plating layer. The conductive resin layer contains a conductive filler and a resin. Ag is used as the conductive filler. Also, an epoxy resin is used as the resin. And, by the plurality of conductive fillers contacting each other, conduction in the conductive resin layer is ensured.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Document 1 discloses a multilayer ceramic capacitor in which a second electrode layer is formed by curing a conductive resin paste on a first electrode layer. Patent Document 1 describes that since the second electrode layer contains a resin, the electrical resistance becomes high, and as a solution, the electrical resistance is reduced by directly connecting the first electrode layer and the plating layer. However, when the first electrode layer and the plating layer are directly connected, stress concentrates at the connection portion, and therefore the stress may propagate through the plating layer and extend into the inside of the laminate. Furthermore, in Patent Document 1, in order to directly connect the first electrode layer and the plating layer, the thickness of the second electrode layer is gradually reduced so that a portion of the first electrode layer is exposed at the end. Therefore, there is a risk that the effect of improving the deflection strength by the second electrode layer will be reduced, or that the moisture resistance will deteriorate due to an increase in the exposed area of ​​the first electrode layer.

[0005] Therefore, the object of the present invention is to provide a multilayer ceramic electronic component that can suppress deterioration of bending strength and moisture resistance while suppressing an excessive increase in electrical resistance. [Means for solving the problem]

[0006] The multilayer ceramic electronic component of the present invention is A laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, The first external electrode is positioned on the third surface, The second external electrode and located on the fourth surface Equipped with, The laminated body is It has a plurality of stacked internal electrodes and a plurality of dielectric layers, and the inner layer portion is the region from the first internal electrode on the first side to the second internal electrode on the second side, The first outer layer is laminated on the first surface side of the inner layer, A second outer layer laminated on the second surface side of the inner layer and It has, The first external electrode is, The base electrode layer, A resin electrode layer disposed on the aforementioned base electrode layer, A plating layer disposed on the resin electrode layer and It has, The aforementioned plating layer is The plating layer body and A connection region extending from the plating layer body so as to penetrate the resin electrode layer and connected to the base electrode, It has, The connection portion between the connection region and the base electrode is located near the first internal electrode. Multilayer ceramic electronic components. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress deterioration of flexural strength and moisture resistance while suppressing an excessive increase in electrical resistance. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view of a multilayer ceramic capacitor according to the first embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 1. [Figure 4] Figure 2 is an enlarged view of region P1, which is a partial cross-sectional view of a multilayer ceramic capacitor. [Figure 5] Figure 4 is a view along arrow V, and is a partial side view of a multilayer ceramic capacitor viewed along its length. [Figure 6] This is a partial cross-sectional view of a multilayer ceramic capacitor according to the second embodiment. [Figure 7] This is a partial side view of the multilayer ceramic capacitor of the third embodiment, viewed in the longitudinal direction. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described based on a multilayer ceramic capacitor 1, which is an example of a multilayer ceramic electronic component. Figure 1 is a perspective view of the multilayer ceramic capacitor 1 of the first embodiment.

[0010] (Laminated structure) The laminate 2 includes a plurality of stacked dielectric layers and a plurality of internal electrode layers. The laminate 2 has an approximately rectangular parallelepiped shape. In the laminate 2, the direction in which the dielectric layers and the internal electrode layers are stacked is defined as the height direction T. Also, the direction orthogonal to the height direction T is defined as the width direction W. The direction orthogonal to the height direction T and the width direction W is defined as the length direction L.

[0011] In the laminate 2, the two faces facing each other in the height direction T are defined as the first main face M1 and the second main face M2, respectively. Also, in the laminate 2, the two faces facing each other in the width direction W are defined as the first side face S1 and the second side face S2, respectively. Also, the first end face E1 and the second end face E2 facing each other in the length direction L are defined. The mounting face of the multilayer ceramic capacitor 1 is the first main face M1. The mounting face is the face facing the wiring board when the multilayer ceramic capacitor 1 is mounted on the wiring board or the like.

[0012] Regarding the cross section of the laminate 2, the cross section taken along line II-II in FIG. 1 is referred to as the LT cross section. Also, the cross section taken along line III-III in FIG. 1 is referred to as the WT cross section.

[0013] It is preferable that the corners and the ridge lines of the laminate 2 are rounded. The corner is the portion where three faces of the laminate 2 intersect. The ridge line is the portion where two faces of the laminate 2 intersect. Also, irregularities or the like may be formed on a part or all of the main face, the side face, and the end face.

[0014] (Dielectric layer) The total number of dielectric layers stacked in the laminate 2 is preferably 15 or more and 2000 or less. The dielectric layer is mainly formed of a ceramic material. As this ceramic material, for example, dielectric ceramics composed mainly of components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used. Also, dielectric ceramics obtained by adding sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components may be used as the ceramic material.

[0015] In this embodiment, various explanations will be given regarding the multilayer ceramic capacitor 1. As mentioned above, the multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component. When piezoelectric ceramic material is used for the laminate 2, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) based ceramic materials.

[0016] When semiconductor ceramics are used in the laminate 2, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel-based ceramic materials.

[0017] When a magnetic ceramic material is used in the laminate 2, the multilayer ceramic electronic component functions as an inductor element. When a multilayer ceramic electronic component functions as an inductor element, the internal electrode layer becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0018] The thickness of each dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0019] (Classification of laminates) Based on Figure 2, the division of the laminate 2 in the height direction T and the length direction L will be explained. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 can be divided in the height direction T into a first outer layer T1, an inner layer T2, and a second outer layer T3. The first outer layer T1, the inner layer T2, and the second outer layer T3 are stacked on top of each other in the height direction T, in the order from the first main surface M1 toward the second main surface M2.

[0020] The first outer layer T1 is the portion between the internal electrode layer closest to the first main surface M1 and the first main surface M1. The inner layer T2 is the region from the internal electrode layer closest to the first main surface M1 (in this embodiment, the first outermost internal electrode layer 6A, described later) to the internal electrode layer closest to the second main surface M2. Within the inner layer T2, multiple internal electrode layers face each other. The second outer layer T3 is the portion between the internal electrode layer closest to the second main surface M2 and the second main surface M2.

[0021] More specifically, the first outer layer T1 is an assembly of multiple dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The second outer layer T3 is an assembly of multiple dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0022] Of the dielectric layers, the dielectric layers located in the first outer layer T1 and the second outer layer T3 are designated as the outer dielectric layer 4. Of the dielectric layers, the dielectric layer located in the inner layer T2 is designated as the inner dielectric layer 5. The first outer layer T1 and the second outer layer T3 may be made of the same material, or they may have different amounts and types of additives.

[0023] The dimensions of the laminate 2 are not particularly limited. The dimension of the laminate 2 in the length direction L is denoted as dimension L. Dimension L is preferably 0.20 mm or more and 3.20 mm or less. The dimension of the laminate 2 in the width direction W is denoted as dimension W. Dimension W is preferably 0.10 mm or more and 2.50 mm or less. The dimension of the laminate 2 in the height direction T is denoted as dimension T. Dimension T is preferably 0.10 mm or more and 2.50 mm or less.

[0024] The division of the laminate 2 in the longitudinal direction L will now be explained. The laminate 2 can be divided in the longitudinal direction L into a first end L1, an L-opposing electrode portion L2, and a second end L3. The first end L1, the L-opposing electrode portion L2, and the second end L3 are arranged in this order in the longitudinal direction L, from the second end face E2 toward the first end face E1.

[0025] The L-opposing electrode portion L2 is the portion where the internal electrode layers face each other in the height direction T. The first end L1 is the portion between the L-opposing electrode portion L2 and the second end face E2. The second end L3 is the portion between the L-opposing electrode portion L2 and the first end face E1. The L-opposing electrode portion L2 corresponds to the opposition electrode portion of the internal electrode layer. The first end L1 and the second end L3 correspond to the lead-out electrode portion of the internal electrode layer. The opposition electrode portion and the lead-out electrode portion will be explained later. The first end L1 and the second end L3 are also called the L-gap.

[0026] The L-shaped counter electrode portion L2 corresponds to the counter electrode portion of the internal electrode layer. Therefore, the L-shaped counter electrode portion L2 is also called the inner layer portion in the L direction.

[0027] The division of the laminate 2 in the width direction W will be explained based on Figure 3. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. The laminate 2 can be divided in the width direction W into a first side portion W1, a W-opposing electrode portion W2, and a second side portion W3. The first side portion W1, the W-opposing electrode portion W2, and the second side portion W3 are arranged in this order from the first side portion S1 to the second side portion S2 in the width direction W.

[0028] The W-opposing electrode portion W2 is the portion where the internal electrode layers face each other in the height direction T. The first side portion W1 is the portion between the W-opposing electrode portion W2 and the first side portion S1. The second side portion W3 is the portion between the W-opposing electrode portion W2 and the second side portion S2. The first side portion W1 and the second side portion W3 are also called the W gap.

[0029] The W-shaped opposing electrode section W2 is the part where the internal electrode layer is located. Therefore, the W-shaped opposing electrode section W2 is also called the W-shaped inner layer section.

[0030] The first side portion W1 and the second side portion W3 are areas in which no internal electrode layer exists in the height direction T. More specifically, the first side portion W1 is located on the side of the first side S1 and includes a dielectric layer located between the first side S1 and the outermost surface W11 of the inner layer portion on the side of the first side S1. The first side portion W1 is also called the outer layer portion on the first side.

[0031] Similarly, the second side portion W3 is located on the side of the second side S2 and includes a dielectric layer located between the second side S2 and the outermost surface W12 of the inner layer portion on the side of the second side S2. The second side portion W3 is also called the outer layer portion on the second side.

[0032] (Internal electrode layer) The internal electrode layer has a plurality of first internal electrode layers 6 and a plurality of second internal electrode layers 7. The first internal electrode layers 6 are internal electrodes exposed on the second end face E2. The second internal electrode layers 7 are internal electrodes exposed on the first end face E1.

[0033] The first internal electrode layer 6 comprises a first opposing electrode portion 8 facing the second internal electrode layer 7, and a first drawn-out electrode portion 10 extending from the first opposing electrode portion 8 to the second end face E2 of the laminate 2. The end of the first drawn-out electrode portion 10 on the second end face E2 side is drawn out to the surface of the second end face E2 of the laminate 2. The end of the first drawn-out electrode portion 10 that is drawn out to the second end face E2 is exposed at the second end face E2.

[0034] The second internal electrode layer 7 comprises a second opposing electrode portion 9 facing the first internal electrode layer 6, and a second drawn-out electrode portion 11 extending from the second opposing electrode portion 9 to the first end face E1 of the laminate 2. The end of the second drawn-out electrode portion 11 on the first end face E1 side is drawn out to the surface of the first end face E1 of the laminate 2. The end of the second drawn-out electrode portion 11 that extends to the first end face E1 is exposed on the first end face E1.

[0035] The shapes of the first counter electrode portion 8 and the second counter electrode portion 9 are not particularly limited. Preferably, the shapes of the first counter electrode portion 8 and the second counter electrode portion 9 are rectangular. However, the corners of the first counter electrode portion 8 and the second counter electrode portion 9 may be rounded. Also, the corners of the first counter electrode portion 8 and the second counter electrode portion 9 may be formed at an angle. Forming at an angle means forming them in a tapered shape.

[0036] The shapes of the first and second lead electrode portions 10 and 11 are not particularly limited. Preferably, the first and second lead electrode portions 10 and 11 are rectangular in shape. However, the corners of the first and second lead electrode portions 10 and 11 may be rounded. Also, the corners of the first and second lead electrode portions 10 and 11 may be formed at an angle. Forming them at an angle means forming them in a tapered shape.

[0037] The width of the first opposing electrode portion 8 and the width of the first leading electrode portion 10 may be the same. Alternatively, one of the widths of the first opposing electrode portion 8 and the first leading electrode portion 10 may be narrower than the other.

[0038] Similarly, the width of the second opposing electrode portion 9 and the width of the second lead-out electrode portion 11 may be the same. Alternatively, one of the widths of the second opposing electrode portion 9 and the second lead-out electrode portion 11 may be narrower than the other.

[0039] The first internal electrode layer 6 and the second internal electrode layer 7 can be made of a suitable conductive material, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. Furthermore, having a Sn layer at the interface between the internal electrode and the inner dielectric layer can mitigate electric field concentration at the interface.

[0040] The internal electrode layer may have a width (length in the width direction W) that decreases as it approaches the exposed end.

[0041] The amount of displacement in the width direction W between adjacent internal electrode layers in the height direction T may be 1.0 μm or less.

[0042] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed when the first counter electrode portion 8 and the second counter electrode portion 9 face each other via the inner dielectric layer 5. As a result, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0043] The thickness of the first internal electrode layer 6 and the second internal electrode layer 7 is preferably, for example, 0.2 μm to 2.0 μm. Furthermore, the total number of the first internal electrode layer 6 and the second internal electrode layer 7 is preferably 15 to 2000.

[0044] (External electrode layer) The external electrode layer includes a first external electrode layer 20 and a second external electrode layer 21. The first external electrode layer 20 is connected to the second internal electrode layer 7. The first external electrode layer 20 is also positioned on a portion of the first main surface M1 and a portion of the second main surface M2, as well as on a portion of the first side surface S1 and a portion of the second side surface S2, from the first end face E1.

[0045] The first external electrode layer 20 on the first end face E1 is designated as the first first end face external electrode layer 22, the first external electrode layer 20 on the first main surface M1 is designated as the first first main surface external electrode layer 23, the first external electrode layer 20 on the second main surface M2 is designated as the first second main surface external electrode layer 24, the first external electrode layer 20 on the first side surface S1 is designated as the first first side surface external electrode layer 25, and the first external electrode layer 20 on the second side surface S2 is designated as the first second side surface external electrode layer 26.

[0046] The second external electrode layer 21 is connected to the first internal electrode layer 6. The second external electrode layer 21 is also positioned on a portion of the first main surface M1 and a portion of the second main surface M2, as well as on a portion of the first side surface S1 and a portion of the second side surface S2, from the second end face E2.

[0047] The second external electrode layer 21 on the first end face E1 is designated as the second first end face external electrode layer 27, the second external electrode layer 21 on the first main surface M1 is designated as the second first main surface external electrode layer 28, the second external electrode layer 21 on the second main surface M2 is designated as the second second main surface external electrode layer 29, the second external electrode layer 21 on the first side surface S1 is designated as the second first side surface external electrode layer 30, and the second external electrode layer 21 on the second side surface S2 is designated as the second second side surface external electrode layer (not shown).

[0048] The first external electrode layer 20 includes a first base electrode layer 32, a first conductive resin layer 34, a first internal plating layer 36, and a first external plating layer 38. The second external electrode layer 21 includes a second base electrode layer 33, a second conductive resin layer 35, a second internal plating layer 37, and a second external plating layer 39.

[0049] The first and second base electrode layers 32 and 33 are layers containing conductive metal and glass components. The first and second conductive resin layers 34 and 35 are layers containing metal components and made of thermosetting resin. The first and second inner plating layers 36 and 37 can be, for example, Ni plating layers. The first and second outer plating layers 38 and 39 can be, for example, Sn plating layers. Each layer will be described in turn below.

[0050] (base electrode layer) The base electrode layer includes a first base electrode layer 32 and a second base electrode layer 33. The first base electrode layer 32 is arranged to wrap around from the first end face E1 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2. The second base electrode layer 33 is arranged to wrap around from the second end face E2 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2.

[0051] The first and second base electrode layers 32 and 33 contain a conductive metal and a glass component. The conductive metal includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The first and second base electrode layers 32 and 33 may contain a dielectric component instead of a glass component, or may contain both a glass component and a dielectric component simultaneously.

[0052] The first base electrode layer 32 and the second base electrode layer 33 may each be formed in multiple layers. Furthermore, the first base electrode layer 32 and the second base electrode layer 33 may be formed by applying a conductive paste containing glass and metal to the laminate and baking it. This baking may be performed simultaneously with the firing of the internal electrodes, or after the firing of the internal electrodes. In this way, the first base electrode layer 32 and the second base electrode layer 33 are configured as baked layers.

[0053] The thickness of the first base electrode layer 32 at the center of the height direction T of the first base electrode layer 32 located at the first end face E1 is preferably, for example, 10 μm or more and 150 μm or less. Similarly, the thickness of the second base electrode layer 33 at the center of the height direction T of the second base electrode layer 33 located at the second end face E2 is preferably, for example, 10 μm or more and 150 μm or less.

[0054] When the first base electrode layer 32 and the second base electrode layer 33 are provided on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, the thickness of the first base electrode layer 32 or the second base electrode layer 33 at the center of the length L of the first base electrode layer 32 or the second base electrode layer 33 located on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is preferably, for example, 5 μm or more and 50 μm or less.

[0055] (Conductive resin layer) A conductive resin layer is placed on top of the base electrode layer. The conductive resin layer contains resin components and metal components. The conductive resin layer has a first conductive resin layer 34 and a second conductive resin layer 35. The first conductive resin layer 34 and the second conductive resin layer 35 contain a thermosetting resin, which is the resin component. Therefore, the first conductive resin layer 34 and the second conductive resin layer 35 are more flexible than the base electrode layer. This is because the base electrode layer consists of, for example, a plating film or a fired product of metal components and glass components.

[0056] Therefore, even if flexural stress is applied to the mounting substrate and physical shock is applied to the multilayer ceramic capacitor, or if shock is applied to the multilayer ceramic capacitor due to thermal cycling, it is possible to suppress the occurrence of cracks in the multilayer ceramic capacitor.

[0057] Specific examples of thermosetting resins included in the conductive resin layer include various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins. Among these, epoxy resin is one of the most suitable resins because it has excellent heat resistance, moisture resistance, and adhesion.

[0058] The conductive resin layer preferably contains a curing agent along with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds can be used as curing agents for the epoxy resin.

[0059] The first conductive resin layer 34 is positioned on the first base electrode layer 32. More specifically, the first conductive resin layer 34 is positioned to cover the first base electrode layer 32. The edges of the first conductive resin layer 34 are in contact with the laminate 2.

[0060] Similarly, the second conductive resin layer 35 is positioned on the second base electrode layer 33. More specifically, the second conductive resin layer 35 is positioned to cover the second base electrode layer 33. The edges of the second conductive resin layer 35 are in contact with the laminate 2.

[0061] The metal components contained in the first conductive resin layer 34 and the second conductive resin layer 35 are preferably metal fillers. The metal components are particularly preferably Ag. Ag may be pure Ag or an alloy containing Ag.

[0062] Ag may be a coating on the surface of a metal powder other than Ag. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0063] Using Ag as a metal filler offers the following advantages: Ag has the lowest resistivity among metals, allowing for the formation of electrodes with low electrical resistance. Furthermore, as a precious metal, Ag is resistant to oxidation, thus improving the weather resistance of the conductive resin layer. By using Ag as a metal filler, the properties of Ag can be maintained while using a less expensive base metal.

[0064] The shape of the metal filler contained in the first conductive resin layer 34 and the second conductive resin layer 35 is not particularly limited. The shape of the metal filler may be spherical, flattened, or the like. The metal filler may be a mixture of spherical metal powder and flattened metal powder.

[0065] The average particle size of the metal filler contained in the first conductive resin layer 34 and the second conductive resin layer 35 is not particularly limited. For example, the average particle size of the metal filler can be between 0.3 μm and 10 μm. The average particle size of the metal filler contained in the conductive resin layer can be determined by laser diffraction particle size measurement (based on ISO 13320). This method of determining the average particle size can be applied regardless of the shape of the filler.

[0066] The metal fillers contained in the first conductive resin layer 34 and the second conductive resin layer 35 are primarily responsible for the conductivity of the conductive resin layers. Specifically, the contact between the metal fillers forms an electrical pathway within the conductive resin layer.

[0067] As mentioned above, the resins included in the first conductive resin layer 34 and the second conductive resin layer 35 can be various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0068] The first conductive resin layer 34 and the second conductive resin layer 35 preferably contain a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as the curing agent.

[0069] The thickness of the first conductive resin layer 34 and the second conductive resin layer 35 is preferably, for example, 10 μm to 200 μm.

[0070] (Plating layer) The plating layer will now be described. As mentioned above, it includes an inner plating layer and an outer plating layer. In other words, the plating layer consists of two layers. However, the plating layer may be a single layer or multiple layers.

[0071] (Inner plating layer) The inner plating layer is disposed on the conductive resin layer. The inner plating layer covers at least a portion of the conductive resin layer. The inner plating layer includes a first inner plating layer 36 and a second inner plating layer 37. The first inner plating layer 36 is disposed on the first conductive resin layer 34. The second inner plating layer 37 is disposed on the second conductive resin layer 35.

[0072] The first inner plating layer 36 and the second inner plating layer 37 can be Ni plating layers. By using Ni plating layers for the inner plating layers, it is possible to suppress the corrosion of the underlying electrode layer and other components by solder when mounting the multilayer ceramic capacitor 1.

[0073] (Outer plating layer) The outer plating layer is located on the inner plating layer. The outer plating layer covers at least a portion of the inner plating layer. The outer plating layer includes a first outer plating layer 38 and a second outer plating layer 39. The first outer plating layer 38 is located on the first inner plating layer 36. The second outer plating layer 39 is located on the second inner plating layer 37.

[0074] The first outer plating layer 38 and the second outer plating layer 39 can be made of Sn plating layers. Sn plating layers have good solder wettability. Therefore, by making the outer plating layers Sn plating layers, the mounting of the multilayer ceramic capacitor 1 to a substrate or the like can be made easier.

[0075] The metals used for the inner and outer plating layers are not limited to the examples described above. The plating layers, including the inner and outer plating layers, may include at least one selected from metals such as Cu, Ni, Ag, Pd, Au, and Sn, as well as alloys such as Ag-Pd alloys.

[0076] The thickness of each plating layer is preferably 3 μm to 9 μm.

[0077] The first external electrode layer 20 will be described below using Figures 4 and 5. Figure 4 is an enlarged view of region P1 in Figure 2 and is a partial cross-sectional view of the multilayer ceramic capacitor. Figure 5 is a view along arrow V in Figure 4 and is a partial side view of the multilayer ceramic capacitor viewed in the length direction. The second external electrode layer 21 is the same as the first external electrode layer 20, so its description will be omitted.

[0078] Figure 4 shows the first end face external electrode layer 22 and the first main surface external electrode layer 23 of the first external electrode layer 20. In the first main surface external electrode layer 23, the first base electrode layer 32 covers a portion of the first main surface M1. The first conductive resin layer 34 covers the first base electrode layer 32 and also covers a portion of the first main surface M1. The first inner plating layer 36 and the first outer plating layer 38 cover the first conductive resin layer 34 and also cover a portion of the first main surface M1.

[0079] The first inner plating layer 36 has a plating layer body 41 and a connection region 42. The plating layer body 41 is the portion disposed on the first conductive resin layer 34. The connection region 42 extends from the plating layer body 41 so as to penetrate the first conductive resin layer 34 and is connected to the first base electrode layer 32. The connection portion 43 between the connection region 42 and the first base electrode layer 32 is in the vicinity of the first outermost inner electrode layer 6A. "In the vicinity of the first outermost inner electrode layer 6A" means a position in the height direction T that is at the same position as the first outermost inner electrode layer 6A or within a predetermined range on both sides of it (for example, 5 μm or less on one side).

[0080] This prevents the underlying electrode layer from being completely covered by the conductive resin layer, thereby suppressing an increase in ESR, and also allows the thickness of the conductive resin layer to be maintained (since there is no need to thin the conductive resin layer), thus suppressing deterioration of flexural strength.

[0081] Specifically, as shown in Figure 5, multiple connection regions 42 are provided. In this embodiment, the cross-section of the connection region 42 is circular, and they are arranged in a single row along the width direction W.

[0082] The holes in the conductive resin layer corresponding to the connection region 42 are holes formed by laser processing. Each hole may be formed by a single pulse of the laser or by multiple pulses.

[0083] The connection region 42 extends linearly parallel to the reference plane R1, which extends along the length direction L and the width direction W.

[0084] The connecting portion 43 is located on the first main surface M1 side of the inner layer T2 in the height direction T. In other words, the connecting portion 43 is located outside the inner layer T2 in the height direction T. This makes it possible to move the entry path of moisture-resistant degradation components that penetrate through the internal electrodes away from the internal electrodes, thereby improving moisture resistance.

[0085] The connection portion 43 is located at least 2 μm outside the first outermost inner electrode layer 6A in the height direction T. Specifically, H1 in Figures 4 and 5 is at least 2 μm. This makes it possible to move the entry path of moisture-resistant degradation components that penetrate along the inner electrode away from the inner electrode, thereby improving moisture resistance.

[0086] The connection portion 43 is located on the second main surface M2 side of the first main surface M1 in the height direction T. In other words, the connection portion 43 is located within the region of the first outer layer T1 in the height direction T. This makes it possible to move the starting point of stress propagation away from the outer surface side (mounting surface side) where deflection stress tends to concentrate.

[0087] The length L of the connection region 42 is 1.5 μm or more. In other words, since the thickness of the second conductive resin layer 35 is kept at 1.5 μm or more, and the second inner plating layer 37 and the second base electrode layer 33 are partially directly connected, deterioration of moisture resistance can be suppressed.

[0088] In the longitudinal section of the laminate 2 parallel to the width direction W, the connection region 42 is circular and has a diameter of 10 μm or more and 200 μm or less. Since the diameter is 10 μm or more, it is possible to prevent the area of ​​the connection portion 43 from becoming excessively small, thereby suppressing the increase in ESR. Since the diameter is 200 μm or less, it is possible to prevent the area of ​​the above region from becoming excessively large, thereby suppressing the deterioration of moisture resistance.

[0089] If the connection area 42 is not circular, it is preferable that the minimum width is 10 μm or more and 200 μm or less.

[0090] As shown in Figure 5, when viewed in the longitudinal direction L, the total area of ​​the connection region (for example, the total area of ​​the connection portion 43) relative to the area of ​​the first outer layer portion T1 is preferably in the range of 0.01 to 10.0%, and more preferably in the range of 0.1 to 1.0%.

[0091] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited.

[0092] (Manufacturing method for multilayer ceramic capacitors) An example of a manufacturing method for a multilayer ceramic capacitor 1 is described below. (1) Prepare a dielectric sheet and a conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known organic binders and organic solvents can be used for these binders and solvents.

[0093] (2) A conductive paste for internal electrodes is printed on the dielectric sheet in a predetermined pattern to form the internal electrode pattern. Printing can be done, for example, by screen printing or gravure printing.

[0094] (3) A predetermined number of dielectric sheets for the outer layer are laminated. The dielectric sheets for the outer layer do not have the internal electrode pattern printed on them. Dielectric sheets with the internal electrode pattern printed on them are then laminated sequentially on top of them. Furthermore, a predetermined number of dielectric sheets for the outer layer are laminated on top of those. This creates a laminated sheet.

[0095] (4) A laminated block is produced by pressing the laminated sheets in the height direction. The pressing is performed by means such as a hydrostatic press.

[0096] (5) Cut the laminated block to the specified size. This will cut out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded. The rounding can be done by barrel polishing or the like.

[0097] (6) The laminated chips are fired. This produces a laminate. The firing temperature is preferably 900°C to 1400°C. The firing temperature can be changed depending on the materials of the dielectric and internal electrodes.

[0098] (Underlay electrode) (7) A conductive paste to serve as the base electrode is applied to both end faces of the laminate to form the base electrode layer. In this embodiment, a baked layer was formed as the base electrode layer. When forming the baked layer, the conductive paste is applied to a predetermined position on the laminate. The conductive paste contains glass components and metal. The application can be carried out by methods such as dipping. After application, a baking process is performed to form the base electrode layer. The temperature of the baking process at this time is preferably 700°C to 950°C.

[0099] (Conductive resin layer) (8) The conductive resin layer is formed on the base electrode layer. To form the conductive resin layer, first prepare a conductive resin paste. The conductive resin paste contains resin components and metal components. Apply this conductive resin paste to the base electrode layer. This application can be done by dipping. After application, heat treatment is performed at a temperature of 200°C to 550°C. This heat treatment causes the resin to heat-cur. This forms the conductive electrode layer. The atmosphere during heat treatment is preferably a nitrogen gas atmosphere. In addition, to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm.

[0100] After forming the conductive resin layer, a laser is used to create holes that penetrate the conductive resin layer to achieve the desired angle, shape, and size. For example, the laser conditions can be set to an oscillation wavelength of 800-1000 nm and an output energy of 6-9 mJ / Pulse.

[0101] (9) After forming the conductive resin layer, Ni plating layers are formed on the surface of the conductive resin layer as the first inner plating layer and the second inner plating layer. As a result, a portion of the Ni plating layer penetrates into the holes of the conductive resin layer, forming a connection region 42. In this way, the first base electrode layer 32 and the first inner plating layer 36 are directly connected. Electrolytic plating can be used as the method for forming the first Ni plating layer and the second Ni plating layer. Furthermore, barrel plating is preferably used as the plating method.

[0102] (Second Embodiment) In the first embodiment, the connection region extends parallel to the reference plane. However, the direction in which the connection region extends is not limited to the first embodiment.

[0103] The second embodiment will be described using Figure 6. Figure 6 is a partial cross-sectional view of the multilayer ceramic capacitor of the second embodiment.

[0104] The first inner plating layer 36 has a plating layer body 41 and a connecting region 44. The plating layer body 41 is the portion disposed on the first conductive resin layer 34. The connecting region 44 extends from the plating layer body 41 through the first conductive resin layer 34 and is connected to the first base electrode layer 32. The connection portion 45 between the connecting region 42 and the first base electrode layer 32 is located near the first outermost inner electrode layer 6A.

[0105] As shown in Figure 6, the connection region 44 extends linearly so as it approaches the connection portion 45, it moves away from the reference plane R1 in the height direction T.

[0106] In a longitudinal section along the length L of the laminate 2, the angle θ1 that the connection region 44 makes with respect to the reference plane R1 is 0° or more and 60° or less. More preferably, the angle θ1 is 20 to 40°.

[0107] This allows the stress that would occur when the first inner plating layer 36 and the first underlay electrode layer 32 were in direct contact to be directed in a direction that extends outward from the laminate. As a result, the propagation of stress into the interior of the laminate 2 can be mitigated.

[0108] The connecting portion 45 is located on the first main surface M1 side of the inner layer T2 in the height direction T. In other words, the connecting portion 45 is located outside the inner layer T2 in the height direction T. This makes it possible to move the entry path of moisture-resistant degradation components that penetrate through the internal electrodes away from the internal electrodes, thereby improving moisture resistance.

[0109] The connection portion 45 is located at least 2 μm outside the first outermost inner electrode layer 6A in the height direction T. Specifically, H2 in Figure 6 is at least 2 μm. This makes it possible to move the entry path of moisture-resistant degradation components that penetrate along the inner electrode away from the inner electrode, thereby improving moisture resistance.

[0110] The connection portion 43 is located on the second main surface M2 side of the first main surface M1 in the height direction T. In other words, the connection portion 43 is located within the region of the first outer layer T1 in the height direction T. This makes it possible to move the starting point of stress propagation away from the outer surface side (mounting surface side) where deflection stress tends to concentrate.

[0111] In the second embodiment as well, a multilayer ceramic capacitor can be obtained that can suppress deterioration of deflection strength and moisture resistance while suppressing an excessive increase in electrical resistance.

[0112] (Third embodiment) In the first and second embodiments, the connection region of the plating layer had a thin rod-like structure, but the shape of the connection region is not particularly limited. The third embodiment will be described using Figure 7. Figure 7 is a partial side view of the multilayer ceramic capacitor of the third embodiment, viewed along its length. Since the multilayer ceramic capacitor of the third embodiment has the same basic structure as the multilayer ceramic capacitor of the first embodiment, only the differences will be described below.

[0113] As shown in Figure 7, multiple connection regions 46 are provided. In this embodiment, the cross-section of the connection region 46 is elongated in the width direction W, and they are arranged in a single row along the width direction W.

[0114] The holes in the conductive resin layer corresponding to the connection region 46 are holes formed by laser processing. Each hole may be formed, for example, by multiple pulse irradiations.

[0115] In the third embodiment, a multilayer ceramic electronic component can be obtained that suppresses deterioration of deflection strength and moisture resistance while suppressing an excessive increase in electrical resistance.

[0116] (modified version) Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0117] Pores in the conductive resin layer may be formed using equipment other than laser processing.

[0118] The number, position, cross-sectional shape, direction of extension, and cross-sectional area of ​​the connection regions of the plating layer are not particularly limited. As a modification of the first embodiment, the multiple first regions may be arranged in the width direction W or the height direction T. Alternatively, the multiple first regions may be provided over the entire surface of the first outer layer, for example. As a modification of the second embodiment, the pores of the conductive resin layer corresponding to the multiple first regions may extend long in the height direction T, or they may extend in other directions.

[0119] <1> A laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, The first external electrode is positioned on the third surface, The second external electrode and located on the fourth surface Equipped with, The laminated body is It has a plurality of stacked internal electrodes and a plurality of dielectric layers, and the inner layer portion is the region from the first internal electrode on the first side to the second internal electrode on the second side, The first outer layer is laminated on the first surface side of the inner layer, A second outer layer laminated on the second surface side of the inner layer and It has, The first external electrode is, The base electrode layer, A resin electrode layer disposed on the aforementioned base electrode layer, A plating layer disposed on the resin electrode layer and It has, The first plating layer is The plating layer body and A connection region extending from the plating layer body so as to penetrate the first resin electrode layer and connected to the first underlay electrode layer, It has, The connection portion between the connection region and the underlying electrode layer is located near the first internal electrode layer. Multilayer ceramic electronic components.

[0120] <2> The connection region extends linearly, parallel to a reference plane extending along the first direction, or as it approaches the connection portion, it moves away from the reference plane outward in the stacking direction. In the longitudinal section of the laminate along the first direction, the angle that the connection region makes with respect to the reference plane is 0° or more and 60° or less. <1> Multilayer ceramic electronic components as described above.

[0121] <3> The connecting portion is located on the first surface side of the inner layer portion in the stacking direction. <1> or <2> Multilayer ceramic electronic components as described above.

[0122] <4> The connecting portion is located at a distance of 2 μm or more in the stacking direction from the internal electrode located on the first surface side among the plurality of internal electrodes. <3> Multilayer ceramic electronic components as described above.

[0123] <5> The connecting portion is located on the second surface side of the first surface in the stacking direction. <1> ~ <4> A multilayer ceramic electronic component as described in any of the following.

[0124] <6> The dimension of the connection region in the first direction is 1.5 μm or more. <1> ~ <5> A multilayer ceramic electronic component as described in any of the following.

[0125] <7> In the longitudinal section of the laminate parallel to the second direction, the minimum width of the connection region is 10 μm or more and 200 μm or less. <1> ~ <6> A multilayer ceramic electronic component as described in any of the following.

[0126] <8> The aforementioned plating layer contains Ni. <1> ~ <7> A multilayer ceramic electronic component as described in any of the following. [Explanation of Symbols]

[0127] 1: Multilayer ceramic capacitor (multilayer ceramic electronic component) 2: Laminate 4: Outer dielectric layer (dielectric layer) 5: Inner dielectric layer (dielectric layer) 6: First internal electrode layer (internal electrode) 6A: First outermost inner electrode layer (first inner electrode) 7: Second internal electrode layer (internal electrode) 20: First external electrode layer (external electrode) 21: Second external electrode layer (external electrode) 32: First underlay electrode layer 34: First conductive resin layer (resin electrode layer) 36: First inner plating layer 41: Plating layer body 42: Connection area 43: Connection part 44: Connection area 45: Connection part 46: Connection area M1: First principal surface (first face) M2: Second principal surface (second face) E1: First end face (third face) E2: Second end face (fourth face) S1: First side (fifth side) S2: Second side (sixth side) T1: First outer layer T2: Inner layer T3: Second outer layer L: Length direction (first direction) W: Width direction (second direction) T: Height direction (stack direction)

Claims

1. A laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, The first external electrode is arranged on the third surface, The second external electrode and the fourth surface are located on the above-mentioned surface. Equipped with, The laminated body is It has a plurality of stacked internal electrodes and a plurality of dielectric layers, and the inner layer portion is the region from the first internal electrode on the first side to the second internal electrode on the second side, The first outer layer is laminated on the first surface side of the inner layer, A second outer layer laminated on the second surface side of the inner layer and It has, The first external electrode is, The base electrode layer, A resin electrode layer disposed on the aforementioned base electrode layer, A plating layer disposed on the resin electrode layer and It has, The aforementioned plating layer is The plating layer body and A connection region extending from the plating layer body so as to penetrate the resin electrode layer and connected to the underlay electrode layer, It has, The connection portion between the connection region and the underlying electrode layer is located near the first internal electrode. Multilayer ceramic electronic components.

2. The connection region extends linearly, parallel to a reference plane extending along the first direction, or as it approaches the connection portion, it moves away from the reference plane outward in the stacking direction. The multilayer ceramic electronic component according to claim 1, wherein in a longitudinal cross-section of the laminate along the first direction, the angle that the connection region makes with respect to the reference plane is 0° or more and 60° or less.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the connecting portion is located on the first surface side of the inner layer portion in the stacking direction.

4. The multilayer ceramic electronic component according to claim 3, wherein the connection portion is located at a distance of 2 μm or more outward in the stacking direction from the internal electrode that is located on the first surface side among the internal electrodes.

5. The multilayer ceramic electronic component according to claim 3, wherein the connecting portion is located on the second surface side of the first surface in the stacking direction.

6. The multilayer ceramic electronic component according to claim 1 or 2, wherein the dimension of the connection region in the first direction is 1.5 μm or more.

7. The multilayer ceramic electronic component according to claim 1 or 2, wherein in a longitudinal cross-section of the laminate parallel to the second direction, the minimum width of the connection region is 10 μm or more and 200 μm or less.

8. The multilayer ceramic electronic component according to claim 1 or 2, wherein the plating layer contains Ni.

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