Observation system

Abstract

This system provides an observation system that can continuously observe changes in phenomena related to a target, even if the output signal of a sensor installed in a radiation environment is degraded by radiation. [Solution] The observation system 11 according to the present invention is configured by connecting a sensor unit 13, which is radiation resistant and acquires sensing data relating to an object, and a management unit 15, which has a signal processing unit 33 that performs predetermined processing on a digital signal including the sensing data acquired by the sensor unit 13, via a communication cable 17. The signal processing unit 33 includes a receiving unit 35 that receives sensing data and a synchronization code. The receiving unit 35 has multiple determination bit patterns set for determining the synchronization code, and searches for whether the determination bit pattern is included in the bit sequence relating to sensing data over a predetermined time width by switching between multiple determination bit patterns, and recognizes the synchronization code.

Description

Technical Field

[0001] The present invention relates to an observation system for observing changes in phenomena related to an object in a radiation environment.

Background Art

[0002] For example, in radiation utilization facilities such as nuclear power plants, a plurality of imaging systems equipped with image sensors are provided for the purpose of observing changes in phenomena related to objects such as equipment installed at various locations within the facility. Also, imaging systems equipped with image sensors are utilized for applications such as internal investigations associated with the decommissioning of nuclear power plants.

[0003] [[ID=十六]]For example, Patent Document 1 discloses an invention of an imaging system in which an imaging sensor unit is provided separately in a region with a high-level radiation environment and an image processing unit is provided separately in a region with a low-radiation environment, and the image processing unit is operated in the low-radiation environment (see paragraph 0126 of Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the imaging system according to Patent Document 1, there is a concern that deterioration of pixel data and the like due to radiation may occur during the process of transmitting pixel data and the like captured by the imaging sensor unit to the image processing unit, which may hinder the observation of changes in phenomena related to the object.

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide an observation system capable of continuously observing changes in phenomena related to an object even when the output signal of a sensor unit installed in a radiation environment is deteriorated by radiation. [Means for solving the problem]

[0007] To solve the above problems, the observation system according to the present invention is An observation system comprising a sensor unit having radiation resistance and acquiring sensing data relating to a target, and a management unit equipped with a signal processing unit that performs predetermined processing on a digital signal including the sensing data acquired by the sensor unit, connected via a communication medium, wherein the system observes changes in phenomena relating to the target based on the processing content of the signal processing unit, The sensor unit digitally outputs a synchronization code consisting of the sensing data itself and a predetermined signal pattern indicating the boundaries of the sensing data. The signal processing unit provided in the management unit includes a receiving unit that receives the sensing data and the synchronization code, and an output unit that outputs a signal based on the sensing data received by the receiving unit. The receiving unit is equipped with multiple determination bit patterns set for determining the synchronization code, and its most important feature is that it searches for whether the determination bit pattern is included in the bit sequence of the sensing data over a predetermined time width by switching between the multiple determination bit patterns, and recognizes the synchronization code. [Effects of the Invention]

[0008] According to the present invention, even if the output signal of a sensor installed in a radiation environment is degraded by radiation, an observation system can be provided that can continuously observe changes in phenomena related to the target. Other issues, configurations, and effects will be described in detail in the following embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram illustrating the overview of an observation system according to an embodiment of the present invention. [Figure 2A]This is an explanatory diagram illustrating the time-dependent characteristics of signal voltages related to pixel data and synchronization codes when the transmission distance of the wired communication medium connecting the sensor unit and the management unit is relatively short. [Figure 2B] This is an explanatory diagram illustrating the time-dependent characteristics of signal voltages related to pixel data and synchronization codes when the transmission distance of the wired communication medium connecting the sensor unit and the management unit is relatively large. [Figure 3] This is an explanatory diagram illustrating the synchronization code recognition method according to the first embodiment. [Figure 4] This is an explanatory diagram illustrating the synchronization code recognition method according to the first embodiment. [Figure 5] This is a flowchart illustrating the operation of the first synchronous code recognition algorithm applied to the control unit in an observation system according to an embodiment of the present invention. [Figure 6] This is a flowchart illustrating the operation of a second synchronous code recognition algorithm applied to a control unit in an observation system according to an embodiment of the present invention. [Figure 7] This is a flowchart illustrating the operation of a third synchronous code recognition algorithm applied to a control unit in an observation system according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] Multiple observation systems according to the present invention will be described in detail with reference to the drawings as appropriate.

[0011] [Background and Overview of the Observation System 11 According to an Embodiment of the Present Invention] First, the background and overview of the observation system 11 according to an embodiment of the present invention will be explained with reference to Figure 1. FIG. 1 is a block diagram showing an overview of an observation system 11 according to an embodiment of the present invention. FIG. 2A is an explanatory diagram showing the time-dependent characteristics of signal voltages related to pixel data and a synchronization code when the transmission distance of a communication cable (communication medium) 17 connecting the sensor unit 13 and the management unit 15 is relatively small (0.5 m). FIG. 2B is an explanatory diagram showing the time-dependent characteristics of signal voltages related to pixel data and a synchronization code when the transmission distance of the communication cable 17 is relatively large (50 m).

[0012] As shown in FIG. 1, an observation system 11 according to an embodiment of the present invention includes a sensor unit 13 having radiation resistance and acquiring sensing data related to a target, and a management unit 15 including a signal processing unit 33 that performs predetermined processing on a digital signal including the sensing data acquired by the sensor unit 13. The management unit 15 and the sensor unit 13 are connected via a communication cable 17 and configured to have a function of observing a change in a phenomenon related to the target based on the processing content of the signal processing unit 33. The management unit 15 is provided in a normal environment not affected by radiation.

[0013] In the description of the observation system 11 described below, an example will be given in which the sensor unit 13 acquires pixel data using an image sensor 21 including an optical system 19. In this example, the pixel data corresponds to "sensing data related to the target".

[0014] In the sensor unit 13 installed in a radiation environment, in addition to protection by a shielding wall (not shown), a redundant circuit and a device structure that is hardly affected by radiation are adopted. Thereby, the radiation resistance of the sensor unit 13 is improved.

[0015] The inventors of the present invention conducted a γ-ray irradiation test using the sensor unit 13 to which radiation resistance technology was applied as a test subject. As a result, although the sensor unit 13 was operating normally, a problem was confirmed that the receiving unit 35 provided in the signal processing unit 33 could not recognize a digital signal including pixel data and the like transmitted from the sensor unit 13 via the communication cable 17.

[0016] Therefore, the inventors of the present invention have intensively studied an observation system 11 capable of continuously observing changes in a phenomenon related to a target even when the output signal related to the sensor unit 13 is deteriorated by radiation. As a result, the inventors of the present invention have finally completed the present invention.

[0017] The sensor unit 13 digitally outputs pixel data (sensing data) itself and a synchronization code (see FIGS. 2A and 2B) in the form of differential signals (one or more pairs of LVDS signals). In addition, the sensor unit 13 digitally outputs a clock signal that controls the operation timing of the sensor unit 13 and the management unit 15 belonging to the observation system 11. The clock signal is shared between the sensor unit 13 and the management unit 15 via a clock signal line 23 belonging to the communication cable 17.

[0018] The synchronization code has a predetermined signal pattern indicating the delimiter of pixel data and the start of a frame. By the synchronization code, the start and end timings of pixel data in units of frames can be recognized. As the synchronization code, a pathological signal in which either a code 0 or a code 1 is continuous is used in consideration of preventing confusion with the combination of codes exhibited by the bit string related to the pixel data.

[0019] When signal level attenuation and baseline shift (see FIGS. 2A and 2B in comparison) due to long-distance transmission via the communication cable 17 occur in the pathological signal used as the synchronization code, an on / off [0 / 1] determination error occurs, resulting in an error bit. In addition, the radiation resistance of the sensor unit 13 deteriorates due to radiation. Then, for example, when a driver for digital signal processing provided in the sensor unit 13 is constituted by a MOSFET, the slew rate of the MOSFET decreases, and as a result, it becomes easier to generate error bits.

[0020] If no error bits occur in the pathological signal used as a synchronization code, the pathological signal is scrambled, bit converted, etc., in the sensor unit 13, then transmitted to the management unit 15 via the communication cable 17, where it is restored by the signal processing unit 33 in the management unit 15 and received normally.

[0021] However, if an error bit occurs in the pathological signal, the synchronization code that defines the boundaries of pixel data and the start of a frame cannot be recognized, and therefore the start and end timings of the pixel data cannot be recognized. As a result, the observation system 11 malfunctions.

[0022] However, installing a digital converter or multiple relays in the sensor unit 13, which is installed in a radiation environment, in order to prevent malfunctions in the observation system 11 is not practical from the standpoint of space efficiency, etc. Therefore, it is desirable to configure a signal processing unit 33 that can receive pixel data and synchronization code even if an error bit occurs in the pathological signal (synchronization code) transmitted via the communication cable 17.

[0023] Therefore, the management unit 15, which constitutes a part of the observation system 11 according to the embodiment of the present invention, controls the frame rate of the image sensor 21 provided in the sensor unit 13, generates control signals (including SPI communication signals for register setting related to the sensor unit 13) for controlling the sensor unit 13, and further includes a control unit 31 that controls the sensor unit 13 and the signal processing unit 33 based on the generated control signals. The aforementioned control signal is sent from the management unit 15 to the sensor unit 13 via the control signal line 25 belonging to the communication cable 17. Furthermore, the control unit 31 supplies power to the sensor unit 13 via the power supply line 27 belonging to the communication cable 17.

[0024] As described above, the signal processing unit 33 in the management unit 15 has the function of performing predetermined processing on digital signals, including pixel data and synchronization codes, acquired by the sensor unit 13. To realize this function, the signal processing unit 33 is configured to include a receiving unit 35, a storage unit 37, and a video output unit 39.

[0025] The receiving unit 35 receives pixel data and synchronization code, which are digital signals transmitted from the sensor unit 13 via the differential signal line 29 belonging to the communication cable 17, in the form of differential signals (one or more pairs of LVDS signals).

[0026] Specifically, the receiving unit 35 is equipped with multiple determination bit patterns set for determining the synchronization code, and searches for whether the determination bit pattern is included in the bit sequence of pixel data over a predetermined time length (e.g., one frame), by switching between the multiple determination bit patterns, and recognizes the synchronization code. The functions of the receiving unit 35 and the configuration of the determination bit pattern will be described in detail later.

[0027] The storage unit 37 has the function of storing the pixel data received by the receiving unit 35. The storage unit 37 is not particularly limited, but for example, a dual-port RAM can be suitably used.

[0028] The video output unit 39 reads pixel data stored in the dual-port RAM, which is one embodiment of the memory unit 37, converts it into a video signal based on a predetermined video standard, and outputs it. The video output unit 39 corresponds to the "output unit". The video signal output by the video output unit 39 is sent to the display device 41, and the image captured by the image sensor 21 provided in the sensor unit 13 is displayed on the display screen.

[0029] [Basic principles of synchronous code recognition] Here, the basic principles of synchronous code recognition will be explained with reference to Figures 3 and 4. Figure 3 is a schematic diagram illustrating the synchronization code recognition method according to the first embodiment. Figure 4 is a schematic diagram illustrating the synchronization code recognition method according to the second embodiment. In the examples in Figures 3 and 4, the bit sequence belonging to the region of interest among the synchronization codes shown in Figures 2A and 2B is displayed in an enlarged view.

[0030] The regular code shown in Figure 3 refers to a synchronized code in which no bit errors occur within the bit sequence belonging to the region of interest. The first code shown in Figure 3 refers to a synchronization code in which a bit error occurs within the bit sequence belonging to the region of interest (number of error bits: 1 / bolded sign [0] represents the error bit). The second code shown in Figure 3 refers to a synchronization code in which a bit error occurs in the bit sequence belonging to the region of interest (number of error bits: 2 / the bolded sign

[00] represents the error bit). The third code shown in Figure 3 refers to a synchronization code in which a bit error occurs in the bit sequence belonging to the region of interest (number of error bits: 3 / the bolded sign

[000] represents the error bit). The fourth code shown in Figure 3 refers to a synchronization code in which a bit error has occurred in the bit sequence belonging to the region of interest (number of error bits: 4 / the bolded code

[0000] represents the error bit).

[0031] The synchronization codes shown in Figure 3 show that the degree of degradation (number of error bits) increases in the order from the first regular code downwards (1st code, 2nd code, 3rd code, 4th code).

[0032] Here, the multiple determination bit patterns consist of a reference determination bit pattern (for example, a 24-bit bit sequence) used as a criterion for determining whether the synchronization code has been recognized, and first to fourth determination bit patterns obtained by sequentially subtracting one bit from the total number of bits (24 bits) of the reference determination bit pattern.

[0033] Each of the multiple decision bit patterns consists of a decision bit sequence where the sign value of either 0 or 1 appears immediately after a sequence of pre-set bits where the sign value of either 0 or 1 is consecutive. In the example shown in Figure 3, the first group [000000000000000000] consisting of 18 consecutive zeros corresponds to the "reserve bit sequence," and the second group [111111111111111111111111] consisting of 24 consecutive ones corresponds to the "decision bit sequence."

[0034] Next, the synchronization code recognition method according to the first embodiment will be described with reference to Figure 3. When recognizing a synchronization code using the synchronization code recognition method according to the first embodiment, the receiving unit 35 searches for whether any of the determination bit patterns are included in the bit sequence of pixel data over a predetermined time width (for example, one frame) using pattern matching technology by switching between multiple determination bit patterns, and recognizes the synchronization code.

[0035] As shown in Figure 3, for example, in the case where the synchronization code is a normal code (number of error bits: 0), the reference judgment bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width (e.g., one frame).

[0036] The receiving unit 35 searches for a determination bit pattern within the bit sequence of pixel data over a predetermined time interval using pattern matching technology with a reference determination bit pattern (determination bit sequence) from among multiple set determination bit patterns. When the reference determination bit pattern is found in the bit sequence of pixel data, the receiving unit 35 recognizes the synchronization code.

[0037] Furthermore, for example, in the case where the synchronization code is the second code (error bits: 2), the second determination bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width (e.g., one frame).

[0038] Next, the receiver 35 searches using pattern matching technology with the reference judgment bit pattern from among the multiple set judgment bit patterns, but the reference judgment bit pattern does not hit in the bit sequence related to the pixel data. Then, the receiver 35 searches using pattern matching technology with the first judgment bit pattern from among the multiple set judgment bit patterns. In this search as well, the first judgment bit pattern does not hit in the bit sequence related to the pixel data. Next, the receiver 35 searches using pattern matching technology with the second judgment bit pattern from among the multiple set judgment bit patterns. Then, the second judgment bit pattern hits in the bit sequence related to the pixel data. In this way, the receiver 35 recognizes the synchronization code.

[0039] In the observation system 11 to which the synchronization code recognition method according to the first embodiment is applied, multiple determination bit patterns are appropriately switched and used according to the number of bit errors that occur in the bit sequence related to the synchronization code (due to the length of the signal transmission distance, degradation of semiconductor elements due to radiation exposure of the sensor unit 13), and the system sequentially searches whether any of the determination bit patterns are included in the bit sequence related to the pixel data over a predetermined time width (for example, one frame), and recognizes the synchronization code.

[0040] Furthermore, in the observation system 11 to which the synchronization code recognition method according to the first embodiment is applied, the locations where error bits are expected to occur are limited to the inversion boundary between 0→1 or 1→0. Therefore, when setting multiple judgment bit patterns, it is possible to do so with a simple procedure of only removing the leading bit of the reference judgment bit pattern.

[0041] According to the observation system 11 to which the synchronization code recognition method of the first embodiment is applied, even if the output signal of the sensor unit 13 installed in a radiation environment is degraded by radiation, etc., it is possible to continuously observe changes in phenomena related to the target while simplifying the program that describes the synchronization code recognition algorithm.

[0042] Next, the synchronization code recognition method according to the second embodiment will be described with reference to Figure 4. The synchronization code recognition method according to the second embodiment adds a configuration requirement to the configuration requirements of the synchronization code recognition method according to the first embodiment, which is that the number of codes belonging to the spare bit sequence located immediately before the determination bit sequence exceeds a predetermined threshold.

[0043] In other words, when recognizing a synchronization code using the synchronization code recognition method according to the second embodiment, the receiving unit 35 recognizes a synchronization code if a determination bit pattern consisting of a determination bit sequence is included in the bit sequence relating to pixel data over a predetermined time width (for example, one frame), and the count of codes belonging to the reserve bit sequence exceeds a predetermined threshold.

[0044] As shown in Figure 4, for example, in the case where the synchronization code is a normal code (number of error bits: 0), the bit sequence relating to the pixel data over a predetermined time width (e.g., one frame) contains a reference determination bit pattern (determination bit sequence), and the count of codes belonging to the reserve bit sequence [a bit sequence with 18 consecutive codes 0] exceeds a predetermined threshold

[17] .

[0045] The receiving unit 35 first searches using pattern matching technology with a reference determination bit pattern from among the multiple set determination bit patterns. Then, if the reference determination bit pattern (determination bit sequence) is found in the bit sequence related to the pixel data, it is found. Next, the receiving unit 35 compares the number of codes

[18] belonging to the spare bit sequence [a bit sequence consisting of 18 consecutive codes 0] located immediately before the reference determination bit pattern (determination bit sequence: a bit sequence consisting of 24 consecutive codes 1) with a predetermined threshold

[17] . In this case, the number of codes

[18] belonging to the spare bit sequence exceeds the predetermined threshold

[17] .

[0046] In short, the receiving unit 35 recognizes the synchronization code on the condition that a reference determination bit pattern (determination bit sequence) is included in the bit sequence relating to the pixel data over a predetermined time width, and that the count of codes belonging to the spare bit sequence

[18] exceeds a predetermined threshold

[17] .

[0047] Furthermore, for example, in the case where the synchronization code is the second code (number of error bits: 2), the bit sequence relating to the pixel data over a predetermined time width (e.g., one frame) contains the second determination bit pattern, and the count of codes belonging to the spare bit sequence [a bit sequence with 20 consecutive codes 0] exceeds a predetermined threshold

[17] .

[0048] Next, the receiver 35 searches using pattern matching technology with the reference judgment bit pattern from among the multiple set judgment bit patterns, but the reference judgment bit pattern does not hit in the bit sequence related to the pixel data. Next, the receiver 35 searches using pattern matching technology with the first judgment bit pattern from among the multiple set judgment bit patterns. In this search as well, the first judgment bit pattern does not hit in the bit sequence related to the pixel data. Next, the receiver 35 searches using pattern matching technology with the second judgment bit pattern from among the multiple set judgment bit patterns. Then, the second judgment bit pattern hits in the bit sequence related to the pixel data.

[0049] Next, the receiving unit 35 compares the number of codes

[20] belonging to the spare bit sequence [a bit sequence consisting of 20 consecutive codes 0] located immediately before the second determination bit pattern (determination bit sequence: a bit sequence consisting of 22 consecutive codes 1) with a predetermined threshold

[17] . In this case, the number of codes

[20] belonging to the spare bit sequence exceeds the predetermined threshold

[17] .

[0050] In short, the receiving unit 35 recognizes the synchronization code on the condition that the bit sequence relating to the pixel data over a predetermined time width includes a second determination bit pattern (determination bit sequence), and that the count of codes belonging to the reserve bit sequence

[20] exceeds a predetermined threshold

[17] .

[0051] In the observation system 11 to which the synchronization code recognition method according to the second embodiment is applied, a plurality of determination bit patterns are appropriately switched and used according to the number of bit errors occurring in the bit sequence related to the synchronization code, and a sequential search is performed to see if any of the determination bit patterns are included in the bit sequence related to pixel data over a predetermined time width (e.g., one frame). As a result of this search, the synchronization code is recognized on the condition that any of the determination bit patterns (determination bit sequence) are included in the bit sequence related to pixel data over a predetermined time width, and the number of codes belonging to the spare bit sequence located immediately before the determination bit sequence exceeds a predetermined threshold.

[0052] In the observation system 11 to which the synchronization code recognition method according to the second embodiment is applied, when recognizing a synchronization code from a bit sequence relating to pixel data over a predetermined time width, in addition to searching by pattern matching technology that switches and applies multiple set determination bit patterns (determination bit sequences), a configuration is adopted that loads requirements based on the number of codes belonging to the spare bit sequence located immediately before the determination bit sequence. Therefore, in addition to the effects of the observation system 11 to which the synchronization code recognition method according to the first embodiment is applied, it is possible to expect the effect of suppressing misrecognition of synchronization codes.

[0053] As a modification of the synchronization code recognition method according to the second embodiment, the constituent requirements of the synchronization code recognition method according to the second embodiment may be further modified to include the requirement that the total number of bits belonging to the determination bit pattern (determination bit sequence) plus the number of codes belonging to the spare bit sequence converges to a predetermined range.

[0054] As shown in Figure 4, for example, in the case where the synchronization code is a normal code (number of error bits: 0), the bit sequence relating to the pixel data over a predetermined time width (e.g., one frame) contains a reference determination bit pattern (determination bit sequence), the count of codes belonging to the spare bit sequence [a bit sequence with 18 consecutive code 0s] exceeds a predetermined threshold

[17] , and the number of integrated bits [total number of bits belonging to the determination bit sequence (24) + count of codes belonging to the spare bit sequence (18) = 42] converges to a predetermined range (e.g., 40 < number of integrated bits < 44).

[0055] This modification is based on the fact that, considering the mechanism by which error bits occur in the synchronization code, there is a high probability that a trade-off relationship exists between the total number of bits belonging to the decision bit sequence and the number of codes belonging to the spare bit sequence, where a decrease in one increases the other.

[0056] According to the observation system 11 to which the synchronization code recognition method according to a modification of the second embodiment is applied, when recognizing a synchronization code from a bit sequence relating to pixel data over a predetermined time width, in addition to searching by pattern matching technology that switches and applies multiple set determination bit patterns (determination bit sequences), a configuration is adopted that weights requirements based on the number of codes belonging to the spare bit sequence located immediately before the determination bit sequence, and the convergence condition of the integrated bit number. Therefore, in addition to the effects of the observation system 11 to which the synchronization code recognition method according to the second embodiment is applied, the effect of suppressing misrecognition of synchronization codes can be further enhanced.

[0057] [Operation of the first synchronous code recognition algorithm] Next, the operation of the first synchronization code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention will be described with reference to Figure 5. Figure 5 is a flowchart illustrating the operation of the first synchronous code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention. As a prerequisite, the receiving unit 35 basically performs a search process to determine whether any of the determination bit patterns are included in the bit sequence of pixel data within a predetermined time width. Also, the frame rate related to the image sensor 21 is assumed to be set to a predetermined initial value.

[0058] In step S51 shown in Figure 5, the receiving unit 35 searches for the reference determination bit pattern (reference determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0059] If the search in step S51 does not find a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S52.

[0060] On the other hand, if the search in step S51 finds a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 recognizes the synchronization code and jumps the processing flow to step S55.

[0061] In step S52, the receiving unit 35 searches for the first determination bit pattern (first determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0062] If the search in step S52 does not find a match for the first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S53.

[0063] On the other hand, if the search in step S52 finds a first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S55.

[0064] In step S53, the receiving unit 35, in the search process, uses the second determination bit pattern (second determination bit sequence) from among the multiple set determination bit patterns to search for the second determination bit sequence using pattern matching technology.

[0065] If the search in step S53 does not find a match for the second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S54.

[0066] On the other hand, if the search in step S53 finds a second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S55.

[0067] In step S54, the receiving unit 35 searches for the nth decision bit pattern (the nth decision bit sequence) from among the multiple set decision bit patterns using pattern matching technology during the search process. (where n is a natural number of 3 or greater.)

[0068] If the search in step S54 does not find a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 terminates the series of search processes.

[0069] On the other hand, if the search in step S54 finds a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S55.

[0070] In step S55, the signal processing unit 33 uses the determination bit pattern (determination bit sequence) hit by the search process to receive pixel data and synchronization code, and performs predetermined signal processing to recognize the start and end timings for the pixel data on a frame-by-frame basis.

[0071] Subsequently, the dual-port RAM, which is one embodiment of the memory unit 37, stores the pixel data received by the receiving unit 35. The video output unit 39 reads the pixel data stored in the dual-port RAM, converts it into a video signal based on a predetermined video standard, and outputs it. The video signal output by the video output unit 39 is sent to the display device 41, and the image captured by the image sensor 21 provided in the sensor unit 13 is displayed on the display screen.

[0072] As one embodiment of the memory unit 37, if a dual-port RAM having a memory capacity of one frame or more is used, even if synchronization cannot be achieved between the data transmission speed related to the image sensor 21 and the readout speed related to the video output unit 39, the video shift phenomenon can be suppressed.

[0073] In the observation system 11 to which the first synchronous code recognition algorithm is applied, the receiving unit 35 is: A preliminary search is performed to determine if the reference judgment bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width. If, as a result of the first search, the reference determination bit pattern cannot be found in the bit sequence relating to the pixel data, then, using the multiple determination bit patterns in a switching manner, an n-th search (where n is a natural number greater than or equal to 2) is performed to determine whether a determination bit pattern different from the reference determination bit pattern is included in the bit sequence relating to the pixel data. If, as a result of the n-th search, one of the multiple determination bit patterns is recognized in the bit sequence related to the pixel data, signal processing is performed to receive the pixel data and the synchronization code using the recognized determination bit pattern.

[0074] According to the observation system 11 to which the first synchronization code recognition algorithm is applied, the search process aimed at recognizing the synchronization code is performed while appropriately switching the determination bit pattern. Therefore, even if the output signal of the sensor unit 13 installed in a radiation environment is degraded by radiation, the appropriate synchronization code can be quickly recognized, and observation of changes in phenomena related to the target can be performed without interruption.

[0075] [Operation of the second synchronous code recognition algorithm] Next, the operation of the second synchronization code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention will be described with reference to Figure 6. Figure 6 is a flowchart illustrating the operation of the second synchronous code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention.

[0076] The first synchronous code recognition algorithm and the second synchronous code recognition algorithm share the same basic operation. The difference between the first synchronization code recognition algorithm and the second synchronization code recognition algorithm is that, in step S65, if pixel data and synchronization codes cannot be received despite a search process aimed at synchronization code recognition being performed while the frame rate related to the image sensor 21 is provisionally set to a predetermined initial value, the control unit 31 in the management unit 15 performs a low frame rate reduction process to lower the frame rate related to the image sensor 21 from the predetermined initial value.

[0077] As a prerequisite, the receiving unit 35 basically performs a search process to determine whether any of the determination bit patterns are included in the bit sequence of pixel data within a predetermined time width. Also, the frame rate related to the image sensor 21 is assumed to be set to a predetermined initial value.

[0078] In step S61 shown in Figure 6, the receiving unit 35 searches for the reference determination bit pattern (reference determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0079] If the search in step S61 does not find a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S62.

[0080] On the other hand, if the search in step S61 finds a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 recognizes the synchronization code and jumps the processing flow to step S66.

[0081] In step S62, the receiving unit 35 searches for the first determination bit sequence (first determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0082] If the search in step S62 does not find a match for the first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S63.

[0083] On the other hand, if the search in step S62 finds a first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S66.

[0084] In step S63, the receiving unit 35 searches for the second determination bit pattern (second determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0085] If the search in step S63 does not find a match for the second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S64.

[0086] On the other hand, if the search in step S63 finds a second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S66.

[0087] In step S64, the receiving unit 35 searches for the nth decision bit pattern (the nth decision bit sequence) from among the multiple set decision bit patterns using pattern matching technology during the search process. (where n is a natural number of 3 or greater.)

[0088] If the search in step S64 does not find a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S65.

[0089] On the other hand, if the search in step S64 finds a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S66.

[0090] In step S65, if, despite performing a search process aimed at recognizing a synchronization code while the frame rate of the image sensor 21 is provisionally set to a predetermined initial value, pixel data and a synchronization code cannot be received, the control unit 31 in the management unit 15 performs a low frame rate processing to reduce the frame rate of the image sensor 21 from the predetermined initial value. However, when performing frame rate reduction processing, a lower limit is set for the frame rate. This is because if the frame rate drops too low, the video will appear choppy and unnatural.

[0091] Specifically, if the receiving unit 35 performs a search process aimed at recognizing a synchronization code while the frame rate related to the image sensor 21 is provisionally set to a predetermined initial value, but fails to recognize any of the multiple determination bit patterns, it sends a low frame rate instruction signal to the control unit 31 to reduce the frame rate related to the image sensor 21.

[0092] When the control unit 31 receives the low frame rate instruction signal from the receiving unit 35, it generates a low frame rate control signal that reduces the frame rate of the image sensor 21 from its initial value, and controls the sensor unit 13 and the signal processing unit 33 based on the generated low frame rate control signal.

[0093] When the sensor unit 13 receives the low frame rate control signal from the control unit 31, it controls the frame rate of the image sensor 21 to be reduced from its initial value. When the signal processing unit 33 receives the low frame rate control signal from the control unit 31, it provisionally sets the frame rate for the image sensor 21, which has been reduced from the initial value, and returns the processing flow to step S61, causing the receiving unit 35 to re-execute the search process (see steps S61 to S64) aimed at recognizing the synchronization code.

[0094] In step S66, the signal processing unit 33 uses the determination bit pattern (determination bit sequence) hit by the search process to receive pixel data and synchronization code, and performs predetermined signal processing to recognize the start and end timings for the pixel data on a frame-by-frame basis.

[0095] Subsequently, the dual-port RAM, which is one embodiment of the memory unit 37, stores the pixel data received by the receiving unit 35. The video output unit 39 reads the pixel data stored in the dual-port RAM, converts it into a video signal based on a predetermined video standard, and outputs it. The video signal output by the video output unit 39 is sent to the display device 41, and the image captured by the image sensor 21 provided in the sensor unit 13 is displayed on the display screen.

[0096] In the observation system 11 to which the second synchronization code recognition algorithm is applied, if pixel data and synchronization codes cannot be received despite performing a search process aimed at synchronization code recognition, the receiving unit 35, in accordance with the low frame rate control signal received from the control unit 31, provisionally sets the frame rate related to the image sensor 21 to a value lower than the initial value, and performs a primary search to see if the reference determination bit pattern is included in the bit sequence related to the pixel data over a predetermined time width. If, as a result of the first search, the reference determination bit pattern cannot be found in the bit sequence relating to the pixel data, then, using the multiple determination bit patterns in a switching manner, an n-th search (where n is a natural number greater than or equal to 2) is performed to determine whether a determination bit pattern different from the reference determination bit pattern is included in the bit sequence relating to the pixel data. If, as a result of the n-th search, one of the multiple determination bit patterns is recognized in the bit sequence related to the pixel data, signal processing is performed to receive the pixel data and synchronization code using the recognized determination bit pattern. However, if none of the multiple determination bit patterns are recognized, a low frame rate instruction signal is sent to the control unit 31 to further reduce the frame rate related to the image sensor 21.

[0097] According to the observation system 11 to which the second synchronization code recognition algorithm is applied, if pixel data and synchronization codes cannot be received despite performing a search process aimed at synchronization code recognition while appropriately switching the judgment bit pattern, the receiving unit 35, in accordance with the low frame rate control signal received from the control unit 31, temporarily sets the frame rate related to the image sensor 21 to a value lower than the initial value, and then re-executes the search process aimed at synchronization code recognition while appropriately switching the judgment bit pattern. Therefore, compared to the observation system 11 to which the first synchronization code recognition algorithm is applied, even if the output signal of the sensor unit 13 installed in a radiation environment is degraded by radiation, the number of error bits can be suppressed by appropriately using a frame rate appropriate to the environmental conditions, and the appropriate synchronization code can be recognized quickly and accurately, enabling uninterrupted observation of phenomena related to the target.

[0098] [Operation of the third synchronous code recognition algorithm] Next, the operation of the third synchronization code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention will be described with reference to Figure 7. Figure 7 is a flowchart illustrating the operation of the third synchronous code recognition algorithm applied to the management unit 15 of the observation system 11 according to an embodiment of the present invention.

[0099] The second synchronous code recognition algorithm and the third synchronous code recognition algorithm share the same basic operation. The difference between the second synchronization code recognition algorithm and the third synchronization code recognition algorithm is that in step S76, it is determined whether or not the frame rate reduction process has been performed, and in step S78, the processing timing is updated after the frame rate reduction process has been performed and the synchronization code has been recognized.

[0100] As a prerequisite, the receiving unit 35 basically performs a search process to determine whether any of the determination bit patterns are included in the bit sequence of pixel data within a predetermined time width. Also, the frame rate related to the image sensor 21 is assumed to be set to a predetermined initial value.

[0101] In step S71 shown in Figure 7, the receiving unit 35 searches for the reference determination bit sequence using pattern matching technology, with the reference determination bit sequence being one of the multiple set determination bit patterns used in the search process.

[0102] If the search in step S71 does not find a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S72.

[0103] On the other hand, if the search in step S71 finds a reference determination bit pattern (reference determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 recognizes the synchronization code and jumps the processing flow to step S76.

[0104] In step S72, the receiving unit 35 searches for the first determination bit sequence (first determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0105] If the search in step S72 does not find a match for the first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S73.

[0106] On the other hand, if the search in step S72 finds a first determination bit pattern (first determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S76.

[0107] In step S73, the receiving unit 35 searches for the second determination bit pattern (second determination bit sequence) from among the multiple set determination bit patterns using pattern matching technology during the search process.

[0108] If the search in step S73 does not find a match for the second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S74.

[0109] On the other hand, if the search in step S73 finds a second determination bit pattern (second determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S76.

[0110] In step S74, the receiving unit 35 searches for the nth decision bit pattern (the nth decision bit sequence) from among the multiple set decision bit patterns using pattern matching technology during the search process. (where n is a natural number of 3 or greater.)

[0111] If the search in step S74 does not find a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 proceeds to the next step S75.

[0112] On the other hand, if the search in step S74 finds a match for the nth determination bit pattern (nth determination bit sequence) in the bit sequence related to the pixel data, the receiving unit 35 jumps the processing flow to step S76.

[0113] In step S75, if, despite performing a search process aimed at recognizing a synchronization code while the frame rate of the image sensor 21 is provisionally set to a predetermined initial value, pixel data and synchronization codes cannot be received, the control unit 31 in the management unit 15 performs a low frame rate processing to reduce the frame rate of the image sensor 21 from the predetermined initial value.

[0114] When the signal processing unit 33 receives the low frame rate control signal from the control unit 31, it provisionally sets the frame rate for the image sensor 21, which has been reduced from the initial value, and returns the processing flow to step S71, causing the receiving unit 35 to re-execute the search process (see steps S71 to S74) aimed at recognizing the synchronization code.

[0115] In step S76, the signal processing unit 33 determines whether or not it has performed the frame rate reduction process. If the determination in step S76 is that the low frame rate processing has not been performed, the signal processing unit 33 proceeds to the next step S77. On the other hand, if the determination in step S76 indicates that the frame rate reduction process has been executed, the signal processing unit 33 jumps the processing flow to step S78.

[0116] In step S77, the signal processing unit 33 uses the determination bit pattern (determination bit sequence) hit by the search process to receive pixel data and synchronization code, and performs predetermined signal processing to recognize the start and end timings for the pixel data on a frame-by-frame basis.

[0117] Subsequently, the dual-port RAM, which is one embodiment of the memory unit 37, stores the pixel data received by the receiving unit 35. The video output unit 39 reads the pixel data stored in the dual-port RAM, converts it into a video signal based on a predetermined video standard, and outputs it. The video signal output by the video output unit 39 is sent to the display device 41, and the image captured by the image sensor 21 provided in the sensor unit 13 is displayed on the display screen.

[0118] In step S78, the receiving unit 35 terminates the series of search processes. When the series of search processes is completed, the control unit 31 in the management unit 15 performs a final setting, updating the frame rate, which is lower than the initially set value, to the new initial value if it was able to recognize the reference judgment bit pattern or one of the multiple judgment bit patterns. As a result, the control unit 31 updates the processing timing after the low frame rate processing has been executed and the synchronization code has been recognized.

[0119] In the observation system 11 to which the third synchronous code recognition algorithm is applied, the receiving unit 35 is: With the frame rate of the image sensor 21 provisionally set to a value lower than the initial value, if the first search result allows the recognition of a reference determination bit pattern in the bit sequence of the pixel data, or if the nth search result allows the recognition of one of the multiple determination bit patterns in the bit sequence of the pixel data, the search for whether the reference determination bit pattern or multiple determination bit patterns are included in the bit sequence of the pixel data for each subsequent frame is terminated. When the search is completed, the control unit 31 in the management unit 15 performs the final setting, updating the frame rate, which is lower than the provisionally set initial value, to the new initial value if it was able to recognize either the reference judgment bit pattern or one of the multiple judgment bit patterns.

[0120] According to the observation system 11 to which the third synchronization code recognition algorithm is applied, when a series of searches aimed at synchronization code recognition is completed, the control unit 31 in the management unit 15 performs a final setting to update the frame rate, which is a value lower than the provisionally set initial value when a reference judgment bit pattern or any of the multiple judgment bit patterns is recognized, as the new initial value. Therefore, compared to the observation system 11 to which the second synchronization code recognition algorithm is applied, even if the output signal of the sensor unit 13 installed in a radiation environment is degraded by radiation, the number of error bits can be suppressed by appropriately updating the frame rate to suit the environmental conditions, and the observation of phenomena related to the target can be performed without interruption while recognizing a more appropriate synchronization code quickly and accurately.

[0121] [Other Embodiments] The embodiments described above are examples of the embodiment of the present invention. Therefore, the technical scope of the present invention should not be interpreted as being limited by these embodiments, as the present invention can be implemented in various forms without departing from its gist or its main features.

[0122] Furthermore, some of the configurations of the embodiments described here can be replaced with those of other embodiments, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace some of the configurations of each embodiment with those of other embodiments.

[0123] For example, in the description of the observation system 11 according to the present invention, when performing a search process aimed at recognizing a synchronized code in the first to third synchronized code recognition algorithms, an example was given in which a reference determination bit pattern (reference determination bit sequence), a first determination bit pattern (first determination bit sequence), a second determination bit pattern (second determination bit sequence), a third determination bit pattern (third determination bit sequence), ... nth (n is a natural number greater than or equal to 4) determination bit pattern (nth determination bit sequence) are applied in the order listed. However, the present invention is not limited to this example. For example, you can choose any order you like, such as setting the application order of the judgment bit pattern to alternate bits or setting it randomly.

[0124] Furthermore, in the description of the observation system 11 according to the present invention, an upper limit may be set for n (where n is a natural number greater than or equal to 4) in the nth (where n is a natural number greater than or equal to 4) determination bit pattern. This is because setting n too large may raise concerns about misrecognition of the synchronization code.

[0125] Furthermore, in the description of the observation system 11 according to the present invention, the sensor unit 13 was described as acquiring pixel data captured using an image sensor as sensing data relating to the target, but the present invention is not limited to this example. The sensor unit 13 may, for example, adopt a configuration that acquires the temperature, pressure, position, momentum, and energy of the target as sensing data relating to the target.

[0126] Finally, in the observation system 11 according to the present invention, the management unit 15 may adopt a configuration that estimates the cumulative dose of radiation irradiated to the sensor unit 13 based on the combination of the frame rate and determination bit pattern related to the image sensor 21 when the synchronization code is successfully recognized. With this configuration, it becomes possible to understand the radiation environment in which the sensor unit 13 is located. As a result, for example, it can be expected that the maintenance timing of the sensor unit 13 can be appropriately managed. [Explanation of symbols]

[0127] 11 Observation Systems 13 Sensor section 15 Management Department 17. Communication cable (communication medium) 19 Optical system 21 Image Sensor 23 Clock signal line 25 Control signal line 27 Power supply line 29 Differential signal lines 31 Control Unit 33 Signal Processing Unit 35 Receiving section 37 Memory section 39. Video output section (output section) 41 Display device

Claims

1. An observation system comprising a sensor unit having radiation resistance and acquiring sensing data relating to a target, and a management unit equipped with a signal processing unit that performs predetermined processing on a digital signal including the sensing data acquired by the sensor unit, connected via a communication medium, wherein the system observes changes in phenomena relating to the target based on the processing content of the signal processing unit, The sensor unit digitally outputs a synchronization code consisting of the sensing data itself and a predetermined signal pattern indicating the boundaries of the sensing data. The signal processing unit provided in the management unit includes a receiving unit that receives the sensing data and the synchronization code, and an output unit that outputs a signal based on the sensing data received by the receiving unit. The receiving unit is equipped with multiple determination bit patterns set for determining the synchronization code, and searches for whether the determination bit pattern is included in the bit sequence of the sensing data over a predetermined time width by switching between the multiple determination bit patterns, and recognizes the synchronization code. An observation system characterized by the following:

2. An observation system according to claim 1, The aforementioned plurality of determination bit patterns are It consists of a reference determination bit pattern used as a criterion for determining whether the aforementioned synchronization code has been recognized, and one or more determination bit patterns obtained by subtracting the total number of bits of the reference determination bit pattern. Each of the aforementioned plurality of determination bit patterns consists of a determination bit sequence in which the other sign value appears immediately after a preliminary bit sequence in which one of the sign values, either 0 or 1, is consecutive. An observation system characterized by the following:

3. In the observation system described in claim 2, The receiving unit recognizes the synchronization code when the bit sequence of the sensing data over a predetermined time width contains the determination bit pattern consisting of the determination bit sequence, and the count of codes belonging to the reserve bit sequence exceeds a predetermined threshold. An observation system characterized by the following:

4. An observation system according to claim 2 or 3, The aforementioned sensor unit is The system includes an image sensor that acquires pixel data representing the brightness information of pixels related to the object being observed, and digitally outputs the pixel data itself, as well as a synchronization code consisting of a predetermined signal pattern indicating the boundary of the pixel data and the start of a frame. The signal processing unit provided in the control unit is The system comprises a receiving unit that receives the pixel data and the synchronization code, a storage unit that stores the pixel data received by the receiving unit, and a video output unit that converts the pixel data read from the storage unit into a video signal and outputs it. The memory unit is a dual-port RAM with a storage capacity of one frame or more. An observation system characterized by the following:

5. The observation system according to claim 4, The receiving unit is A preliminary search is performed to determine whether the aforementioned reference determination bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width. If, as a result of the first search, the reference determination bit pattern cannot be recognized in the bit sequence relating to the pixel data, then, using the multiple determination bit patterns in a switching manner, an n-th search (where n is a natural number of 2 or greater) is performed to determine whether a determination bit pattern different from the reference determination bit pattern is included in the bit sequence relating to the pixel data. If, as a result of the n-th search, one of the multiple determination bit patterns is recognized in the bit sequence relating to the pixel data, then signal processing is performed to receive the pixel data and the synchronization code using the recognized determination bit pattern. An observation system characterized by the following:

6. The observation system according to claim 4, The aforementioned management department, The sensor unit further comprises a control unit that generates a control signal for controlling the frame rate of the image sensor provided in the sensor unit, and controls the sensor unit and the signal processing unit based on the generated control signal, The receiving unit, with the frame rate related to the image sensor temporarily set to an initial value, A preliminary search is performed to determine whether the aforementioned reference determination bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width. If the first search results in the recognition of the reference determination bit pattern within the bit sequence of the pixel data, the recognized reference determination bit pattern is used to perform signal processing to receive the pixel data and the synchronization code. However, if the reference determination bit pattern cannot be recognized, the nth search (where n is a natural number of 2 or greater) is performed by switching between the multiple determination bit patterns to determine whether a determination bit pattern different from the reference determination bit pattern is included in the bit sequence of the pixel data. If, as a result of the n-th search, one of the multiple determination bit patterns is recognized in the bit sequence relating to the pixel data, signal processing is performed to receive the pixel data and the synchronization code using the recognized determination bit pattern. However, if none of the multiple determination bit patterns are recognized, a low frame rate instruction signal is sent to the control unit to reduce the frame rate relating to the image sensor. An observation system characterized by the following:

7. The observation system according to claim 6, The control unit provided in the aforementioned management unit is: Upon receiving the low frame rate instruction signal from the receiving unit, the unit generates a low frame rate control signal that reduces the frame rate of the image sensor relative to its initial value, and controls the sensor unit and the signal processing unit based on the generated low frame rate control signal. Subsequently, the receiving unit provisionally sets the frame rate of the image sensor to a value lower than the initial value, A preliminary search is performed to determine whether the aforementioned reference determination bit pattern is included in the bit sequence relating to the pixel data over a predetermined time width. If, as a result of the first search, a reference determination bit pattern is recognized in the bit sequence relating to the pixel data, the recognized reference determination bit pattern is used to perform signal processing to receive the pixel data and the synchronization code. However, if the reference determination bit pattern cannot be recognized, an n-th search (where n is a natural number of 2 or greater) is performed by switching between the multiple determination bit patterns to determine whether a determination bit pattern different from the reference determination bit pattern is included in the bit sequence relating to the pixel data. If, as a result of the n-th search, one of the multiple determination bit patterns is recognized in the bit sequence relating to the pixel data, signal processing is performed to receive the pixel data and the synchronization code using the recognized determination bit pattern. However, if none of the multiple determination bit patterns are recognized, a low frame rate instruction signal is sent to the control unit to further reduce the frame rate relating to the image sensor. An observation system characterized by the following:

8. An observation system according to claim 6 or 7, The receiving unit is With the frame rate of the image sensor provisionally set to a value lower than the initial value, if the first search result allows the reference determination bit pattern to be recognized in the bit sequence of the pixel data, or if the nth search result allows any of the multiple determination bit patterns to be recognized in the bit sequence of the pixel data, the search for whether the reference determination bit pattern or the multiple determination bit patterns is included in the bit sequence of the pixel data for each subsequent frame is terminated. When the search is completed, the control unit in the management unit performs a final setting, updating the frame rate to a new initial value that is lower than the initially set value if the reference judgment bit pattern or any of the multiple judgment bit patterns is recognized. An observation system characterized by the following:

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