Indication device

Abstract

To improve the degree of freedom in the placement of pixel electrodes. [Solution] The display device 10 comprises scanning wiring 27, signal wiring 28, control wiring 29, a plurality of pixel electrodes 26, a first switching element 24, and a second switching element 25. The first switching element 24 has a first electrode 24A connected to the scanning wiring 27, a second electrode 24B connected to the signal wiring 28, a third electrode 24C, and a first semiconductor part 24D. The second switching element 25 has a fourth electrode 25A connected to the control wiring 29, a fifth electrode 25B connected to the third electrode 24C, a sixth electrode 25C, and a second semiconductor part 25D. The first pixel electrode 26α included in the plurality of pixel electrodes 26 has a first main body part 26Aα and a first connection wiring part 26Bα connected to the first main body part 26Aα and the sixth electrode 25C. The first connection wiring part 26Bα intersects with the control wiring 29 or the signal wiring 28.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a display device with improved freedom in arranging pixel electrodes.

Background Art

[0002] Conventionally, as an example of a display device, the one described in Patent Document 1 below is known. Patent Document 1 discloses a liquid crystal display device as a display device. The liquid crystal display device described in Patent Document 1 includes scanning lines and signal lines provided in a matrix, a control line provided in parallel with the signal lines, a first switch element that is turned on by a drive signal applied to the scanning line and applies a signal applied to the signal line to liquid crystal, and a second switch element that is connected in series to the first switch element and is turned on / off controlled by a signal applied to the control line.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the liquid crystal display device described in Patent Document 1, the number of signal lines can be reduced, thus avoiding the need for a narrower terminal pitch in the data driver, which can lead to reduced power consumption and lower costs. However, in the liquid crystal display device described in Patent Document 1, the polarity of the image signal supplied to the signal line is reversed each time an image signal is written to the pixels of each row. As a result, the image signal supplied to the signal line tends to become blunted, and there is a problem that power consumption increases. Here, in order to reduce power consumption, if, for example, the polarity of the image signal supplied to the signal line is reversed every frame in the liquid crystal display device described in Patent Document 1, there may be cases where pixels with the same polarity are arranged alternately in two rows, making streaky display defects easily visible. This is because, in the liquid crystal display device described in Patent Document 1, the arrangement of the pixel electrodes connected to the second switch element is fixed.

[0005] The technology described herein was developed based on the circumstances described above, and aims to improve the degree of freedom in the arrangement of pixel electrodes. [Means for solving the problem]

[0006] (1) A display device relating to the technology described herein comprises: scanning wiring extending in a first direction; signal wiring extending in a second direction intersecting the first direction and intersecting the scanning wiring; control wiring extending in the second direction, spaced apart from the signal wiring and intersecting the scanning wiring; a plurality of pixel electrodes arranged in a matrix with respect to the first and second directions; a first switching element; a second switching element, wherein the first switching element comprises: a first electrode connected to one of the scanning wiring and the control wiring; a second electrode connected to the signal wiring; a third electrode; and the second electrode. The second switching element has a first semiconductor portion connected to the third electrode and arranged superimposed on the first electrode, and the second switching element has a fourth electrode connected to the other of the scanning wiring and the control wiring, a fifth electrode connected to the third electrode, a sixth electrode connected to the pixel electrode, and a second semiconductor portion connected to the fifth electrode and the sixth electrode and arranged superimposed on the fourth electrode, and the plurality of pixel electrodes include a first pixel electrode, the first pixel electrode has a first main body portion and a first connection wiring portion connected to the first main body portion and the sixth electrode, the first connection wiring portion intersects with the control wiring or the signal wiring.

[0007] (2) In addition to (1) above, the display device may be arranged such that the first main body is positioned between the first connection wiring section and the second switching element to which the first connection wiring section is connected, with the control wiring or the signal wiring in between.

[0008] (3) In addition to (1) or (2) above, the display device may have the first electrode connected to the scanning wiring and the fourth electrode connected to the control wiring.

[0009] (4) In addition to (3) above, the display device may be configured such that the second switching element is positioned closer to the control wiring than to the signal wiring.

[0010] (5) In addition to (3) or (4) above, the display device may be configured such that the first switching element is positioned closer to the signal wiring than to the control wiring.

[0011] (6) In addition to any of (3) to (5) above, the display device has a plurality of control wirings arranged at intervals in the first direction, and the plurality of control wirings include a first control wiring and a second control wiring, a plurality of signal wirings arranged at intervals in the first direction, and the plurality of signal wirings include a first signal wiring, a plurality of second switching elements arranged at intervals in the first direction, and the plurality of second switching elements include a first control switching element which is a second switching element having the fourth electrode connected to the first control wiring, and the fourth electrode connected to the second control wiring The first switching element includes a second control switching element which is the second switching element having electrodes, and a plurality of the first switching elements are arranged at spaced intervals in the first direction, and the plurality of the first switching elements may include a first signal switching element which is the first switching element having a second electrode connected to the first signal wiring and a third electrode connected to the fifth electrode of the first control switching element, and a second signal switching element which is the first switching element having a second electrode connected to the first signal wiring and a third electrode connected to the fifth electrode of the second control switching element.

[0012] (7) In addition to (6) above, the display device also includes a first signal supply unit connected to a plurality of control wirings and supplying signals to the plurality of control wirings, wherein the first signal supply unit may supply a high level potential to the first control wiring and the second control wiring at different timings.

[0013] (8) In addition to (6) or (7) above, the display device may also include, among the plurality of control wirings, a third control wiring and a fourth control wiring, among the plurality of signal wirings, a second signal wiring, among the plurality of second switching elements, a third control switching element which is a second switching element having a fourth electrode connected to the third control wiring, and a fourth control switching element which is a second switching element having a fourth electrode connected to the fourth control wiring, and among the plurality of first switching elements, a third signal switching element which is a first switching element having a second electrode connected to the second signal wiring and a third electrode connected to the fifth electrode of the third control switching element, and a fourth signal switching element which is a first switching element having a second electrode connected to the second signal wiring and a third electrode connected to the fifth electrode of the fourth control switching element.

[0014] (9) In addition to (8) above, the display device may also include: a first short-circuit wiring extending along the first direction and connected to the first signal wiring and the second signal wiring to short-circuit the first signal wiring and the second signal wiring; a first lead wiring connected to any of the first signal wiring, the second signal wiring, or the first short-circuit wiring; and a second signal supply unit connected to the first lead wiring to supply a signal to the first lead wiring.

[0015] (10) In addition to (9) above, the display device also includes a first signal supply unit connected to a plurality of control wirings and supplying signals to each of the plurality of control wirings, wherein the first signal supply unit supplies high-level potentials to the first control wiring, the second control wiring, the third control wiring, and the fourth control wiring at different timings, and the second signal supply unit supplies a signal to the first signal switching element in synchronization with the timing at which a high-level potential is supplied to the first control wiring, supplies a signal to the second signal switching element in synchronization with the timing at which a high-level potential is supplied to the second control wiring, supplies a signal to the third signal switching element in synchronization with the timing at which a high-level potential is supplied to the third control wiring, and supplies a signal to the fourth signal switching element in synchronization with the timing at which a high-level potential is supplied to the fourth control wiring.

[0016] (11) In addition to any of (8) to (10) above, the display device further includes a first signal wiring sandwiched between the first control wiring and the second control wiring in the first direction, a second signal wiring sandwiched between the third control wiring and the fourth control wiring in the first direction, a plurality of the signal wirings including a third signal wiring sandwiched between the second control wiring and the third control wiring in the first direction, a plurality of the first switching elements including a fifth signal switching element which is the first switching element having the second electrode connected to the third signal wiring, and a fifth signal switching element which has the second electrode connected to the third signal wiring. The array includes a sixth signal switching element which is a first switching element arranged with the third signal wiring between it and a switching element, and the plurality of second switching elements include a fifth control switching element which is a second switching element having a fifth electrode connected to the third electrode of the fifth signal switching element, and a sixth control switching element which is a second switching element having a fifth electrode connected to the third electrode of the sixth signal switching element, wherein the fourth electrode of the fifth control switching element may be connected to the second control wiring, and the fourth electrode of the sixth control switching element may be connected to the third control wiring.

[0017] (12) In addition to (11) above, the display device further includes, among the plurality of signal wirings, a fourth signal wiring that sandwiches the fourth control wiring between itself and the second signal wiring in the first direction, among the plurality of first switching elements, a seventh signal switching element which is a first switching element having a second electrode connected to the fourth signal wiring, and among the plurality of second switching elements, a seventh control switching element which is a second switching element having a fifth electrode connected to the third electrode of the seventh signal switching element, and the fourth electrode of the seventh control switching element may be connected to the fourth control wiring.

[0018] (13) In addition to (11) or (12) above, the display device further includes, in addition to (11) or (12) above, a plurality of pixel electrodes, a plurality of first pixel electrodes, the second pixel electrode having a second body portion and a second connection wiring portion connected to the second body portion and the sixth electrode and not intersecting with either the control wiring or the signal wiring, the plurality of first pixel electrodes having a first body portion located on the opposite side of the first signal wiring side in the first direction with respect to the first control wiring, the first connection wiring portion connected to the sixth electrode of the first control switching element and intersecting with the first control wiring, the first body portion sandwiched between the third signal wiring and the third control wiring in the first direction, the first connection wiring portion connected to the sixth electrode of the third control switching element and intersecting with the third control wiring, and the first body portion in the first direction The first pixel electrode is sandwiched between the third control wiring and the second signal wiring, with the first connection wiring portion connected to the sixth electrode of the sixth control switching element and intersecting the third control wiring. The plurality of second pixel electrodes may include a second pixel electrode whose second body portion is sandwiched between the first signal wiring and the second control wiring in a first direction, with the second connection wiring portion connected to the sixth electrode of the second control switching element; a second pixel electrode whose second body portion is sandwiched between the second signal wiring and the fourth control wiring in a first direction, with the second connection wiring portion connected to the sixth electrode of the fourth control switching element; and a second pixel electrode whose second body portion is sandwiched between the second control wiring and the third signal wiring in a first direction, with the second connection wiring portion connected to the sixth electrode of the fifth control switching element.

[0019] (14) In addition to (13) above, the display device may have the first main body and the second main body having the same area, and the first connection wiring section and the second connection wiring section having the same area.

[0020] (15) In addition to (13) or (14) above, the display device may have the same length in the first connection wiring section from the first main body to the sixth electrode and the same length in the second connection wiring section from the second main body to the sixth electrode.

[0021] (16) In addition, the display device, in addition to (11) or (15) above, includes a plurality of first pixel electrodes, where the plurality of first pixel electrodes include: a first pixel electrode whose first main body is sandwiched between the first signal wiring and the second control wiring in a first direction, and whose first connection wiring portion is connected to the sixth electrode of the first control switching element and intersects with the first signal wiring; a first pixel electrode whose first main body is sandwiched between the second control wiring and the third signal wiring in a first direction, and whose first connection wiring portion is connected to the sixth electrode of the second control switching element and intersects with the second control wiring; and a first pixel electrode whose first main body is sandwiched between the third signal wiring and the third control wiring in a first direction, and whose first connection wiring portion is connected to the sixth electrode of the fifth control switching element The first pixel electrode is connected to and intersects with the third signal wiring; the first main body is sandwiched between the third control wiring and the second signal wiring in a first direction, and the first connection wiring portion is connected to the sixth electrode of the sixth control switching element and intersects with the third control wiring; the first main body is sandwiched between the second signal wiring and the fourth control wiring in a first direction, and the first connection wiring portion is connected to the sixth electrode of the third control switching element and intersects with the second signal wiring; and the first main body is located on the opposite side of the fourth control wiring in a first direction from the second signal wiring side, and the first connection wiring portion is connected to the sixth electrode of the fourth control switching element and intersects with the fourth control wiring.

[0022] (17) Further, in addition to the above (13) or the above (16), the display device includes a second signal supply unit connected to the plurality of signal wirings and supplying signals to the plurality of signal wirings, and signals supplied by the second signal supply unit to the first signal wiring and the second signal wiring and signals supplied by the second signal supply unit to the third signal wiring may have opposite polarities.

[0023] (18) Further, in addition to the above (17), the display device includes a first signal supply unit connected to the plurality of control wirings and supplying signals to the plurality of control wirings, and the second signal supply unit may supply signals of the same polarity to the first signal wiring, the second signal wiring, and the third signal wiring in synchronization with the supply of high-level potentials to the first control wiring, the second control wiring, the third control wiring, and the fourth control wiring from the first signal supply unit, respectively.

[0024] (19) Further, in addition to the above (1) or the above (2), the first electrode may be connected to the control wiring, and the fourth electrode may be connected to the scanning wiring.

Advantages of the Invention

[0025] According to the technology described in this specification, the degree of freedom in arranging pixel electrodes can be improved.

Brief Description of the Drawings

[0026] [Figure 1] Planar view of a liquid crystal panel, a driver, a flexible substrate, and a control substrate according to Embodiment 1 [Figure 2] Cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1 [Figure 3] Planar view showing a pixel array of an array substrate constituting a liquid crystal panel according to Embodiment 1 [Figure 4] Cross-sectional view taken along line iv-iv of FIG. 3 in the liquid crystal panel according to Embodiment 1 [Figure 5] Cross-sectional view taken along line v-v of FIG. 3 in the liquid crystal panel according to Embodiment 1 [Figure 6]Cross-sectional view of the liquid crystal panel according to Embodiment 1, shown along line vi-vi in ​​Figure 3. [Figure 7] Plan view showing the first range A1 shown in Figure 3 relating to Embodiment 1 [Figure 8] Plan view showing the second range A2 shown in Figure 3 relating to Embodiment 1 [Figure 9] Plan view showing the third range A3 shown in Figure 3 relating to Embodiment 1 [Figure 10] Circuit diagram showing the electrical configuration of the liquid crystal panel according to Embodiment 1 [Figure 11] Timing chart relating to the operation of the first TFT and second TFT according to Embodiment 1 [Figure 12] Figure 11 schematically shows the pixel arrangement in the array substrate according to Embodiment 1, and is a plan view showing the polarity of the charged pixel electrodes based on the timing chart in Figure 11. [Figure 13] A timing chart relating to the operation of the first TFT and second TFT according to Embodiment 1, the timing chart after the display period of one frame in Figure 11. [Figure 14] Figure 13 schematically shows the pixel arrangement in the array substrate according to Embodiment 1, and is a plan view showing the polarity of the charged pixel electrodes based on the timing chart in Figure 13. [Figure 15] Plan view showing the pixel arrangement of the array substrate constituting the liquid crystal panel according to Embodiment 2 [Figure 16] Plan view showing the first to fourth pixel rows in Figure 15 relating to Embodiment 2 [Figure 17] Plan view showing the third to sixth pixel rows in Figure 15 relating to Embodiment 2 [Figure 18] Plan view showing the 5th to 8th pixel rows in Figure 15 relating to Embodiment 2 [Figure 19] Circuit diagram showing the electrical configuration of the liquid crystal panel according to Embodiment 2 [Figure 20] Timing chart relating to the operation of the first TFT and second TFT according to Embodiment 2 [Figure 21]Figure 20 schematically shows the pixel arrangement in the array substrate according to Embodiment 2, and is a plan view showing the polarity of the charged pixel electrodes based on the timing chart in Figure 20. [Figure 22] A timing chart relating to the operation of the first TFT and second TFT according to Embodiment 2, the timing chart after the display period of one frame in Figure 20. [Figure 23] Figure 22 schematically shows the pixel arrangement in the array substrate according to Embodiment 2, and is a plan view showing the polarity of the charged pixel electrodes based on the timing chart in Figure 22. [Figure 24] Plan view showing the pixel arrangement of the array substrate constituting the liquid crystal panel according to Embodiment 3. [Figure 25] Circuit diagram showing the electrical configuration of the liquid crystal panel according to Embodiment 3 [Modes for carrying out the invention]

[0027] <Embodiment 1> Embodiment 1 will be explained with reference to Figures 1 to 14. In this embodiment, a liquid crystal display device (display device) 10 is illustrated. Note that parts of each drawing show the X, Y, and Z axes, and each axis is drawn so that it corresponds to the direction shown in each drawing. Also, the upper side of Figures 2, 4, 5, and 6 is considered the front side, and the lower side of the same figure is considered the back side.

[0028] As shown in Figure 1, the liquid crystal display device 10 comprises at least a horizontally elongated rectangular liquid crystal panel (display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light for display purposes. The backlight device is positioned on the back side (rear side) of the liquid crystal panel 11 and includes a light source that emits white light (e.g., an LED) and an optical component that converts the light from the light source into planar light by applying an optical effect. The central part of the main surface of the liquid crystal panel 11 is designated as the display area AA where images are displayed. In contrast, the outer peripheral part of the frame-shaped (picture frame-shaped) area surrounding the display area AA on the main surface of the liquid crystal panel 11 is designated as the non-display area NAA where images are not displayed.

[0029] The liquid crystal panel 11 will be described with reference to Figure 2 in addition to Figure 1. As shown in Figures 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. Of the pair of substrates 20 and 21, the front side is the opposing substrate 20, and the back side is the array substrate 21. Both the opposing substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are substances whose optical properties change when an electric field is applied, is interposed between the pair of substrates 20 and 21. A sealing portion 23 is provided between the outer edges of the pair of substrates 20 and 21 to seal the liquid crystal layer 22. The sealing portion 23 is formed in the shape of a rectangular frame surrounding the liquid crystal layer 22. Polarizing plates 16 are attached to the outer surfaces of both substrates 20 and 21.

[0030] As shown in Figures 1 and 2, the opposing substrate 20 has a shorter short side dimension than the array substrate 21. The opposing substrate 20 is bonded to the array substrate 21 such that one end in the short side direction (Y-axis direction) is aligned with it. Therefore, the other end of the array substrate 21 in the short side direction is an exposed portion 21A that protrudes laterally from the opposing substrate 20. This exposed portion 21A is entirely a non-display area (NAA), and a driver (second signal supply unit) 12 for supplying various signals and a flexible substrate 13 are mounted on it.

[0031] As shown in Figures 1 and 2, the driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) mounting. The driver 12 consists of an LSI chip with an internal drive circuit. The driver 12 processes various signals transmitted by the flexible substrate 13 and, for example, supplies image signals to the source wiring 28, which will be described later. The driver 12 is positioned adjacent to one side of the display area AA in the Y-axis direction on the exposed portion 21A, and is sandwiched between the flexible substrate 13 and the display area AA, as described below. Two drivers 12 are positioned at spaced intervals in the X-axis direction on the exposed portion 21A. The driver 12 has a horizontally elongated rectangular shape in its planar form. The longer side dimension of the driver 12 is smaller than the longer side dimension of the display area AA.

[0032] The flexible substrate 13 is constructed by forming a large number of wiring patterns on a substrate made of a synthetic resin material (e.g., polyimide resin) that has insulating and flexible properties. As shown in Figures 1 and 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to the control substrate (first signal supply unit) 14. The flexible substrate 13 is connected to the end of the exposed portion 21A that is opposite to the display area AA side in the Y-axis direction relative to the driver 12. In other words, the flexible substrate 13 is mounted in the exposed portion 21A at a position that sandwiches the driver 12 between it and the display area AA. The control substrate 14 is constructed by mounting multiple circuit components on a rigid substrate made of synthetic resin (e.g., paper phenol or glass epoxy resin). The multiple circuit components include a power supply IC (Integrated Circuit) for outputting power, a timing controller for generating various signals to be supplied to the driver 12, and a level shifter IC for controlling (stepping down / stepping up) the voltage level. The control board 14 has a connector section to which the flexible board 13 and the like are connected. The control board 14 is positioned so as to overlap the back side of the backlight device by bending the flexible board 13 in a folded manner. The control board 14 supplies various signals to the driver 12 and also supplies control signals (switch signals) to the control wiring 29, which will be described later. The control signals are signals that periodically have a potential higher than the threshold voltage of the second TFT 25, which will be described later.

[0033] As shown in Figure 1, a gate drive circuit (third signal supply unit) 15 is provided in the non-display area NAA of the array substrate 21. A pair of gate drive circuits 15 are provided so as to sandwich the display area AA from both sides in the X-axis direction. The gate drive circuits 15 are provided in a vertically elongated strip-shaped area extending along the short side direction (Y-axis direction) of the array substrate 21. The gate drive circuits 15 are for supplying scanning signals to the gate wiring 27, which will be described later, and are monolithically provided on the array substrate 21. The scanning signal is set to a potential higher than the threshold voltage of the first TFT 24, which will be described later.

[0034] As shown in Figure 3, multiple first TFTs (first switching elements) 24, second TFTs (second switching elements) 25, and pixel electrodes 26 are arranged in a matrix-like configuration in the display area AA of the array substrate 21. Multiple first TFTs 24, second TFTs 25, and pixel electrodes 26 arranged along the X-axis constitute one pixel row, and multiple pixel rows are arranged along the Y-axis. Multiple first TFTs 24, second TFTs 25, and pixel electrodes 26 arranged along the Y-axis constitute one pixel column, and multiple pixel columns are arranged along the X-axis. Around the first TFTs 24, second TFTs 25, and pixel electrodes 26, gate wiring (scanning wiring) 27, source wiring (signal wiring, image wiring, data wiring) 28, and control wiring 29 are arranged to surround them in a roughly grid-like manner.

[0035] As shown in Figure 3, the gate wiring 27 extends almost straight along the X-axis direction (first direction) across the display area AA and connects to multiple first TFTs 24 that constitute one pixel row. Multiple gate wirings 27 are arranged side by side with spacing in the Y-axis direction (second direction). The number of gate wirings 27 is the same as the number of pixel electrodes 26 arranged in the Y-axis direction.

[0036] As shown in Figure 3, the source wiring 28 extends roughly along the Y-axis, traversing the display area AA, and connects to multiple first TFTs 24 that make up two adjacent pixel rows, with the source wiring 28 in between. The source wiring 28 is repeatedly bent along its course and has a sloping portion that is slightly inclined with respect to the Y-axis and a straight portion that extends almost straight along the Y-axis. Multiple source wirings 28 are arranged with spacing in the X-axis direction.

[0037] As shown in Figure 3, the control wiring 29 extends roughly along the Y-axis direction, traversing the display area AA longitudinally, similar to the source wiring 28, and connects to multiple second TFTs 25 that constitute two adjacent pixel rows on either side of the control wiring 29. Multiple control wirings 29 are arranged at intervals along the X-axis direction. Similar to the source wiring 28, the control wiring 29 is repeatedly bent along its length, and has a sloping portion that is slightly inclined with respect to the Y-axis direction and a straight portion that extends almost straight along the Y-axis direction. The source wiring 28 and the control wiring 29 are arranged alternately and repeatedly at approximately the same intervals along the X-axis direction. The number of source wirings 28 and control wirings 29 is approximately the same, and their sum is equal to the number of pixel electrodes 26 arranged along the X-axis direction.

[0038] As shown in Figure 3, the first TFT 24 and the second TFT 25 are positioned between the source wiring 28 and the control wiring 29 in the X-axis direction, and between the gate wiring 27 and the pixel electrode 26 (more specifically, the main body 26A, which will be described later) in the Y-axis direction. The first TFT 24 is connected to the gate wiring 27, the source wiring 28, and the second TFT 25. The first TFT 24 is driven based on the scanning signal supplied to the gate wiring 27, and can supply the image signal supplied to the source wiring 28 to the second TFT 25 accordingly. Therefore, in this embodiment, the first TFT 24 can be said to be a signal TFT (signal switching element) that receives an image signal from the source wiring 28.

[0039] As shown in Figure 3, the second TFT 25 is connected to the pixel electrode 26, the control wiring 29, and the first TFT 24. The second TFT 25 is driven based on the control signal supplied to the control wiring 29, and accordingly can supply the image signal supplied from the first TFT 24 to the pixel electrode 26. Therefore, in this embodiment, the second TFT 25 can be said to be a control TFT (control switching element) that controls whether or not an image signal is supplied to the pixel electrode 26. As will be described in detail later, by controlling the driving of the first TFT 24 and the second TFT 25 at an appropriate timing, the pixel electrode 26 can be charged to the potential related to the image signal supplied to the source wiring 28.

[0040] As shown in Figure 3, the pixel electrode 26 has a vertically elongated main body 26A and a connecting wiring portion 26B that connects the main body 26A to the second TFT 25. The main body 26A is positioned between the first TFT 24 and the second TFT 25 and the gate wiring 27 in the Y-axis direction, and between the source wiring 28 and the control wiring 29 in the X-axis direction. Multiple main body 26A are arranged in a line along the X-axis direction with the source wiring 28 or control wiring 29 in between, and multiple main body 26A arranged along the X-axis direction constitute a pixel row. The multiple first TFT 24 and second TFT 25 that constitute a pixel row are positioned between the main body 26A and the gate wiring 27 in the Y-axis direction that constitute the same pixel row. Multiple main body sections 26A are arranged in a row along the Y-axis direction, with at least a portion of the first TFT 24, second TFT 25, and gate wiring 27 sandwiched between them, and the multiple main body sections 26A arranged along the Y-axis direction constitute a pixel row. The multiple first TFT 24 and second TFT 25 that constitute the pixel row are arranged in the Y-axis direction, sandwiched between the main body section 26A and the gate wiring 27 that constitute the same pixel row. The main body section 26A is bent in the longitudinal direction of its own long side so as to follow the source wiring 28 and control wiring 29. Specifically, the main body section 26A has both long side edges that are slightly inclined with respect to the Y-axis direction and is bent once at approximately the center position, forming a shallow V-shape with an obtuse apex angle. Both side edges of the main body section 26A are parallel to the inclined portions of the source wiring 28 and control wiring 29. The main body section 26A has a bent portion at approximately the center position in the longitudinal direction. Each main body 26A has multiple (five in Figure 3) slits 26C formed along its longitudinal direction. The specific number, shape, and formation range of the slits 26C can be changed as appropriate, in addition to those shown in the illustration.

[0041] As shown in Figure 3, the connection wiring section 26B is routed from the main body section 26A to be connected to the second TFT 25 (drain wiring section 43, which will be described later). The portion of the connection wiring section 26B that connects to the second TFT 25 is wider than other parts. The detailed configuration of the connection wiring section 26B will be explained later.

[0042] The cross-sectional configuration of the pixel electrodes 26 in the liquid crystal panel 11 near the center in the Y-axis direction will be explained with reference to Figure 4. Figure 4 is a schematic cross-sectional view along the line iv-iv in Figure 3. On the inner surface of the display area AA of the array substrate 21, as shown in Figure 4, a common electrode 30 is formed below the pixel electrodes 26, superimposed on all of the pixel electrodes 26. A common potential signal (reference potential signal) of a common potential (reference potential) is supplied to the common electrode 30 from the control substrate 14 via the flexible substrate 13, and it extends planarly over almost the entire display area AA. As the pixel electrodes 26 are charged, a potential difference is generated between the superimposed pixel electrodes 26 and the common electrode 30. A fringe electric field (oblique electric field) is generated between the edge of the slit 26C in the pixel electrode 26 and the common electrode 30, including a component along the main surface of the array substrate 21 as well as a component normal to the main surface of the array substrate 21. Therefore, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this fringe electric field. In other words, the liquid crystal panel 11 according to this embodiment is set to FFS (Fringe Field Switching) mode.

[0043] As shown in Figure 4, the display area AA of the opposing substrate 20 constituting the liquid crystal panel 11 is provided with a number of color filters 31 at positions that overlap with each pixel electrode 26 on the array substrate 21. The color filters 31 are arranged in an alternating pattern of three colors, red (R), green (G), and blue (B), along the X-axis. Each of the three color filters 31 extends along the Y-axis (second direction), so that the whole is arranged in a roughly striped pattern. More specifically, each of the three color filters 31 extends roughly along the Y-axis parallel to the inclined portions of the source wiring 28 and control wiring 29, and is repeatedly bent in a zigzag pattern, similar to the source wiring 28 and control wiring 29. The color filters 31 are facing the main body 26A of the pixel electrode 26 on the array substrate 21 side. The color filters 31 and pixel electrode 26 facing each other constitute a pixel PX, which is a display unit.

[0044] As shown in Figure 4, the display area AA of the opposing substrate 20 is provided with light-shielding portions (black matrices) 32 that separate adjacent color filters 31 (pixel electrodes 26) in the X-axis and Y-axis directions, respectively. The light-shielding portions 32 are provided not only in the display area AA but also in the non-display area NAA. In the display area AA, the light-shielding portions 32 form a grid so as to overlap with each TFT 24, 25, gate wiring 27, source wiring 28 and control wiring 29, but in the non-display area NAA, they are generally solid. An overcoat film 33 is formed on the upper layer side of the color filters 31 and the light-shielding portions 32, as shown in Figure 4. The overcoat film 33 is provided as a solid over almost the entire area of ​​the opposing substrate 20. The overcoat film 33 is made of an organic material such as acrylic resin (e.g., PMMA) and functions to flatten steps that occur on the layer below it. Furthermore, a first alignment film 34 is provided on the upper side of the overcoat film 33 (the innermost surface of the opposing substrate 20) to orient the liquid crystal molecules contained in the liquid crystal layer 22. The first alignment film 34 is made of, for example, polyimide.

[0045] Here, various films laminated on the inner surface of the array substrate 21 will be explained using Figure 5. Figure 5 is a schematic cross-sectional view along the vv line in Figure 3. As shown in Figure 5, the array substrate 21 has the following layers laminated on it from the bottom: a first metal film, a gate insulating film 35, a semiconductor film, a second metal film, a first interlayer insulating film 36, a planarization film 37, a first transparent electrode film, a second interlayer insulating film 38, a second transparent electrode film, and a second orientation film 39. The first and second metal films are single-layer films or laminated films or alloys made of different types of metal materials, respectively, selected from copper, titanium, aluminum, molybdenum, tungsten, etc., thereby providing conductivity and light shielding properties. The first metal film constitutes gate wiring 27, etc. The second metal film constitutes source wiring 28 and control wiring 29, etc. The semiconductor film is a thin film using, for example, an oxide semiconductor as the material, and constitutes a part of each TFT 24, 25, etc. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes a common electrode 30, etc. The second transparent electrode film constitutes a pixel electrode 26, etc. The second alignment film 39, like the first alignment film 34, is made of, for example, polyimide, and can align the liquid crystal molecules contained in the liquid crystal layer 22.

[0046] The gate insulating film 35, the first interlayer insulating film 36, and the second interlayer insulating film 38 are each made of silicon nitride (SiN xThe planarization film 37 is made of an inorganic material such as silicon dioxide (SiO2). The planarization film 37 is made of an organic material such as PMMA (acrylic resin). The planarization film 37 has a thickness of, for example, 1 μm to 3 μm, which is much larger than the thickness of the gate insulating film 35, the first interlayer insulating film 36, and the second interlayer insulating film 38. The inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side) is planarized by this planarization film 37. The gate insulating film 35 keeps the lower layer first metal film and the upper layer semiconductor film and second metal film in an insulating state. For example, the intersection of the gate wiring 27 made of the first metal film and the source wiring 28 made of the second metal film is kept in an insulating state by the gate insulating film 35. The first interlayer insulating film 36 and the planarization film 37 keep the lower layer semiconductor film and second metal film and the upper layer first transparent electrode film in an insulating state. For example, the source wiring 28 made of the second metal film and the common electrode 30 made of the first transparent electrode film are kept insulated by the first interlayer insulating film 36 and the planarization film 37. The second interlayer insulating film 38 keeps the lower first transparent electrode film and the upper second transparent electrode film in an insulated state. For example, the common electrode 30 made of the first transparent electrode film and the pixel electrode 26 made of the second transparent electrode film are kept in an insulated state by the second interlayer insulating film 38.

[0047] Figure 6 is a schematic cross-sectional view along the line vi-vi in ​​Figure 3. As shown in Figures 3 and 6, the display area AA of the opposing substrate 20 is provided with spacers 40 that protrude toward the array substrate 21 along the Z-axis direction. The spacers 40 contact the second alignment film 39 on the array substrate 21 side, thereby maintaining the distance between the pair of substrates 20 and 21, i.e., the cell gap (thickness of the liquid crystal layer 22), so as not to fall below a certain level. The spacers 40 are located near the intersections of the gate wiring 27 and source wiring 28, and near the intersections of the gate wiring 27 and control wiring 29. The number of spacers 40 installed is equal to the sum of the intersections of the gate wiring 27 and source wiring 28 and the intersections of the gate wiring 27 and control wiring 29. The spacers 40 are made of an organic material such as PMMA (acrylic resin), and their thickness is approximately the same as the thickness of the planarization film 37. The spacers 40 include two types of spacers 40 with different protrusion heights. Of the two types of spacers 40, the spacer with a relatively larger protrusion height (main spacer) 40 has its protruding tip surface constantly in contact with the second orientation film 39 on the array substrate 21 side. In contrast, a clearance is left between the protruding tip surface of the spacer with a relatively smaller protrusion height (sub-spacer) 40 and the second orientation film 39 on the array substrate 21 side, allowing for bending (deformation) of either substrate 20 or 21.

[0048] Next, the configurations of each TFT 24 and 25 will be described. Figure 7 is a plan view showing the first range A1 shown in Figure 3. As shown in Figure 5, the first TFT 24 has a first gate electrode (first electrode) 24A, a first source electrode (second electrode) 24B, a first drain electrode (third electrode) 24C, and a first semiconductor portion 24D. As shown in Figure 7, the first TFT 24 is positioned closer to the source wiring 28 than to the control wiring 29 (second TFT 25) in the X-axis direction. In this way, the distance between the first source electrode 24B of the first TFT 24 and the source wiring 28 connected to the first source electrode 24B can be shortened compared to the case where the first TFT is positioned closer to the control wiring 29 than to the source wiring 28. As a result, the signal supplied from the source wiring 28 to the first source electrode 24B is less likely to be blunted due to parasitic capacitance and electrical resistance. Furthermore, the first TFT24 is positioned closer to the gate wiring 27 (specifically, the gate wiring 27 to which the first TFT24 is connected) than the second TFT25 in the Y-axis direction.

[0049] As shown in Figure 5, the first gate electrode 24A consists of a portion of the first metal film. As shown in Figure 7, the first gate electrode 24A consists of a portion that is partially widened from the gate wiring 27 extending along the X-axis. More specifically, the first gate electrode 24A is the portion of the gate wiring 27 that protrudes upward along the Y-axis in Figure 7 from the portion adjacent to the portion that intersects with the source wiring 28. The scanning signal transmitted by the gate wiring 27 is supplied to the first gate electrode 24A.

[0050] As shown in Figure 5, the first source electrode 24B consists of a part of the second metal film. As shown in Figure 7, the first source electrode 24B consists of a partially widened portion of the source wiring 28 that extends along the Y-axis. More specifically, the first source electrode 24B is a portion of the source wiring 28 that protrudes along the X-axis to the left or right in Figure 7 from the portion adjacent to the portion that intersects with the gate wiring 27. The tip portion of the first source electrode 24B that protrudes from the source wiring 28 is superimposed on the first gate electrode 24A, as shown in Figure 5.

[0051] As shown in Figure 5, the first drain electrode 24C is made up of a part of the second metal film. The first drain electrode 24C is positioned at a distance from the first source electrode 24B in the X-axis direction. Of the first drain electrode 24C, the portion on the first source electrode 24B side in the X-axis direction is superimposed on the first gate electrode 24A. The portion of the first drain electrode 24C opposite to the first source electrode 24B side in the X-axis direction is connected to the relay wiring section 41, which will be described next.

[0052] As shown in Figure 5, the relay wiring section 41 is made of a part of the second metal film and is directly connected to the first drain electrode 24C. As shown in Figure 7, the relay wiring section 41 extends along the X-axis direction, with one end (source wiring 28 side) connected to the first drain electrode 24C mentioned above, and the other end (control wiring 29 side) connected to the second source electrode 25B, which will be described later. In this way, the relay wiring section 41 has the function of relaying the first TFT 24 and the second TFT 25. Furthermore, the line width of the relay wiring section 41 is smaller than the respective width dimensions of the first drain electrode 24C and the second source electrode 25B to which it is connected.

[0053] As shown in Figure 5, the first semiconductor portion 24D consists of a part of the semiconductor film. The first semiconductor portion 24D is superimposed on the first gate electrode 24A, which consists of a part of the first metal film, via a gate insulating film 35. The first semiconductor portion 24D is kept insulated from the superimposed first gate electrode 24A by the gate insulating film 35. The first semiconductor portion 24D extends along the X-axis, with one end (the source wiring 28 side) connected to the first source electrode 24B and the other end (the control wiring 29 side) connected to the first drain electrode 24C. When a potential higher than the threshold voltage of the first TFT 24 is supplied to the first gate electrode 24A as a scanning signal from the gate wiring 27, a channel region is created in the first semiconductor portion 24D, allowing charge to move between the first source electrode 24B and the first drain electrode 24C through this channel region.

[0054] As shown in Figure 5, the second TFT 25 has a second gate electrode (fourth electrode) 25A, a second source electrode (fifth electrode) 25B, a second drain electrode (sixth electrode) 25C, and a second semiconductor section 25D. As shown in Figure 7, the second TFT 25 is positioned closer to the control wiring 29 in the X-axis direction than to the source wiring 28 (first TFT 24) in the X-axis direction. In this way, the distance between the second gate electrode 25A of the second TFT 25 and the control wiring 29 connected to the second gate electrode 25A can be shortened compared to the case where the second TFT is positioned closer to the source wiring 28 than to the control wiring 29. This makes it less likely for the signal supplied from the control wiring 29 to the second gate electrode 25A to be blunted due to parasitic capacitance and electrical resistance. Furthermore, the second TFT 25 is positioned further from the gate wiring 27 (specifically, the gate wiring 27 to which the first TFT 24 is connected) in the Y-axis direction than to the first TFT 24.

[0055] As shown in Figure 5, the second gate electrode 25A is made up of a part of the first metal film. The second gate electrode 25A is positioned at a distance in the X-axis direction from the portion of the control wiring 29 adjacent to the portion that intersects with the gate wiring 27. The second gate electrode 25A is connected to the connecting electrode 42, which will be described next.

[0056] As shown in Figure 6, the connecting electrode 42 is made of a part of the first metal film and is directly connected to the second gate electrode 25A. As shown in Figure 7, the connecting electrode 42 extends along the X-axis direction and intersects with the control wiring 29. The connecting electrode 42 is connected to each second gate electrode 25A of the second TFT 25, which has different ends in the X-axis direction. The two second TFT 25s connected to one connecting electrode 42 are arranged symmetrically with respect to the control wiring 29 in the X-axis direction. In the gate insulating film 35 interposed between the connecting electrode 42 and the control wiring 29, a first contact hole CH1 is provided with an opening at a position that overlaps with both the connecting electrode 42 and the control wiring 29, as shown in Figure 6. The connecting electrode 42 and the control wiring 29, which overlap each other, are connected through the first contact hole CH1. The control signal transmitted by the control wiring 29 is supplied to the second gate electrode 25A via the connecting electrode 42.

[0057] As shown in Figure 5, the second source electrode 25B is made of a part of the second metal film and is directly connected to the relay wiring section 41. As shown in Figure 7, the second source electrode 25B extends from the other end of the relay wiring section 41 along the Y-axis toward the opposite side from the gate wiring 27. The tip portion of the second source electrode 25B that extends from the relay wiring section 41 is superimposed on the second gate electrode 25A.

[0058] As shown in Figure 5, the second drain electrode 25C is made up of a part of the second metal film. The second drain electrode 25C is positioned at a distance from the second source electrode 25B in the Y-axis direction. Of the second drain electrode 25C, the portion on the second source electrode 25B side in the X-axis direction is superimposed on the second gate electrode 25A. The portion of the second drain electrode 25C opposite to the second source electrode 25B side in the Y-axis direction is connected to the drain wiring section 43, which will be described next.

[0059] As shown in Figure 5, the drain wiring section 43 consists of a part of the second metal film and is directly connected to the second drain electrode 25C. As shown in Figure 7, the drain wiring section 43 extends from the part of the second drain electrode 25C opposite to the second source electrode 25B side, along the X-axis toward the source wiring 28 side, and then along the Y-axis toward the gate wiring 27 side. The end of the drain wiring section 43 opposite to the second drain electrode 25C side is wider than the other parts, and this wider portion is arranged to overlap with the end of the connection wiring section 26B of the pixel electrode 26. Of the first interlayer insulating film 36, planarization film 37, and second interlayer insulating film 38 interposed between the drain wiring section 43 and the connection wiring section 26B, a second contact hole CH2 is provided with an opening at a position that overlaps with both the drain wiring section 43 and the connection wiring section 26B, as shown in Figure 5. The overlapping drain wiring section 43 and the connecting wiring section 26B are connected through the second contact hole CH2. In this way, the drain wiring section 43 has the function of connecting the second drain electrode 25C and the pixel electrode 26. The drain wiring section 43 can also be considered as a part of the second drain electrode 25C.

[0060] As shown in Figure 5, the second semiconductor portion 25D consists of a part of the semiconductor film. The second semiconductor portion 25D is superimposed on the second gate electrode 25A, which consists of a part of the first metal film, via a gate insulating film 35. The second semiconductor portion 25D is kept insulated from the superimposed second gate electrode 25A by the gate insulating film 35. As shown in Figure 7, the second semiconductor portion 25D extends along the Y-axis, with one end (the gate wiring 27 side) connected to the second source electrode 25B and the other end (the main body portion 26A side) connected to the second drain electrode 25C. When a potential higher than the threshold voltage of the second TFT 25 is supplied to the second gate electrode 25A as a control signal from the control wiring 29, a channel region is created in the second semiconductor portion 25D, allowing charge to move between the second source electrode 25B and the second drain electrode 25C through this channel region.

[0061] Now, as shown in Figures 7 to 10, the multiple pixel electrodes 26 in this embodiment include multiple first pixel electrodes 26α and multiple second pixel electrodes 26β, each having the following configuration. In the following, the main body 26A and connecting wiring 26B constituting the first pixel electrode 26α will be referred to as the "first main body" and the "first connecting wiring," respectively, with the subscript "α" added to their reference numerals. The main body 26A and connecting wiring 26B constituting the second pixel electrode 26β will be referred to as the "second main body" and the "second connecting wiring," respectively, with the subscript "β" added to their reference numerals. When referring to them collectively without distinction, no subscript will be added to the reference numerals. Figure 8 is a plan view showing the second range A2 shown in Figure 3. Figure 9 is a plan view showing the third range A3 shown in Figure 3.

[0062] The first connection wiring section 26Bα constituting the first pixel electrode 26α is arranged to intersect with the control wiring 29 or source wiring 28, as shown in Figures 7 to 9. The first main body section 26Aα constituting the first pixel electrode 26α is arranged between itself and the second TFT 25 to which the first connection wiring section 26Bα is connected, with the control wiring 29 or source wiring 28 in between. Therefore, the first main body section 26Aα constituting the first pixel electrode 26α is connected by the first connection wiring section 26Bα to the second TFT 25 which belongs to a different pixel row than the one to which it belongs. In contrast, the second connection wiring section 26Bβ constituting the second pixel electrode 26β is arranged not to intersect with either the control wiring 29 or the source wiring 28. Therefore, the second main body section 26Aβ constituting the second pixel electrode 26β is connected by the second connection wiring section 26Bβ to the second TFT 25 which belongs to the same pixel row as the one to which it belongs.

[0063] As described above, the first pixel electrode 26α has a first connection wiring section 26Bα that connects to the first main body 26Aα and the second drain electrode 25C of the second TFT 25, as shown in Figures 7 to 9, and this first connection wiring section 26Bα intersects with the source wiring 28 or the control wiring 29. By intersecting the first connection wiring section 26Bα with the source wiring 28 or the control wiring 29, the degree of freedom in the placement of the first main body 26Aα of the first pixel electrode 26α can be increased, and the first pixel electrode 26α can be connected to the second TFT 25 which belongs to a different pixel row than the pixel row to which the first main body 26Aα belongs. If the degree of freedom in the arrangement of the first main body 26Aα of the first pixel electrode 26α is increased, then, compared to a conventional display device in which the arrangement of pixel electrodes 26 is fixed, even if an image signal is supplied to each source wiring 28 in which the polarity does not reverse during a certain frame display period, but the polarity reverses every frame display period, pixels with the same polarity will not alternate in two rows, and vertical streak-like display defects will be less visible. Therefore, it becomes possible to reduce power consumption while ensuring display quality.

[0064] Furthermore, as shown in Figures 7 to 9, the area of ​​the first pixel electrode 26α and the second pixel electrode 26β are equivalent to that of the first main body 26Aα and the second main body 26Aβ, and the area of ​​the first connecting wiring section 26Bα and the second connecting wiring section 26Bβ are also equivalent. In other words, since the area of ​​the first pixel electrode 26α and the second pixel electrode 26β are equivalent, the capacitance (electric field strength) generated between the first pixel electrode 26α and the common electrode 30 and the capacitance (electric field strength) generated between the second pixel electrode 26β and the common electrode 30 become equivalent. As a result, display unevenness is less likely to occur between the pixel PX to which the first pixel electrode 26α belongs and the pixel PX to which the second pixel electrode 26β belongs.

[0065] Furthermore, as shown in Figures 7 to 9, the length of the first connecting wiring section 26Bα from the first main body 26Aα to the drain wiring section 43 (second drain electrode 25C) and the length of the second connecting wiring section 26Bβ from the second main body 26Aβ to the drain wiring section 43 are made equal. For example, even if variations occur in the width of the first connecting wiring section 26Bα and the second connecting wiring section 26Bβ due to manufacturing reasons, the above-mentioned equal lengths of the first connecting wiring section 26Bα and the second connecting wiring section 26Bβ make it less likely for differences to occur in the area of ​​the first connecting wiring section 26Bα and the second connecting wiring section 26Bβ. This makes it less likely for display inconsistencies to occur.

[0066] In the following, when distinguishing between multiple control wirings 29, the leftmost control wiring 29 in Figures 3 and 10 will be designated as the "first control wiring" and its designation will be denoted with the subscript "α". The second control wiring 29 from the left in Figures 3 and 10 will be designated as the "second control wiring" and its designation will be denoted with the subscript "β". The third control wiring 29 from the left in Figures 3 and 10 will be designated as the "third control wiring" and its designation will be denoted with the subscript "γ". The rightmost control wiring 29 in Figures 3 and 10 will be designated as the "fourth control wiring" and its designation will be denoted with the subscript "δ". When referring to them collectively without distinction, no subscript will be added to the designation.

[0067] Furthermore, when distinguishing between multiple source wirings 28, the source wiring 28 located between the first control wiring 29α and the second control wiring 29β in the X-axis direction is designated as the "first source wiring" and its designation is denoted by the subscript "α", the source wiring 28 located between the third control wiring 29γ and the fourth control wiring 29δ in the X-axis direction is designated as the "second source wiring" and its designation is denoted by the subscript "β", and the source wiring 28 located between the second control wiring 29β and the third control wiring 29γ in the X-axis direction is designated as the "third source wiring". The subscript "γ" is added to the designation of the source wiring, the source wiring 28 located on the opposite side of the second source wiring 28β side to the fourth control wiring 29δ in the X-axis direction is designated as the "fourth source wiring" and the subscript "δ" is added to its designation, the source wiring 28 located on the opposite side of the first source wiring 28α side to the first control wiring 29α in the X-axis direction is designated as the "fifth source wiring" and the subscript "ζ" is added to its designation, and when referring to them collectively without distinction, no subscript is added to the designation.

[0068] Furthermore, when distinguishing between multiple first TFTs 24, one first TFT 24 having a first source electrode 24B connected to the first source wiring 28α is designated as the "first signal TFT (first signal switching element)" and its designation is denoted with the subscript "α", the other first TFT 24 having a first source electrode 24B connected to the first source wiring 28α is designated as the "second signal TFT (second signal switching element)" and its designation is denoted with the subscript "β", one first TFT 24 having a first source electrode 24B connected to the second source wiring 28β is designated as the "third signal TFT (third signal switching element)" and its designation is denoted with the subscript "γ", and the other first TFT 24 having a first source electrode 24B connected to the second source wiring 28β is designated as the "fourth signal TFT (fourth signal switching element)" and its designation is denoted with the subscript "δ", and so on. One first TFT 24 having a first source electrode 24B connected to source wiring 28γ shall be designated as the "fifth signal TFT (fifth signal switching element)" and its designation shall be subscripted "ζ", the other first TFT 24 having a first source electrode 24B connected to the third source wiring 28γ shall be designated as the "sixth signal TFT (sixth signal switching element)" and its designation shall be subscripted "η", the first TFT 24 having a first source electrode 24B connected to the fourth source wiring 28δ shall be designated as the "seventh signal TFT (seventh signal switching element)" and its designation shall be subscripted "θ", and the first TFT 24 having a first source electrode 24B connected to the fifth source wiring 28ζ shall be designated as the "eighth signal TFT (eighth signal switching element)" and its designation shall be subscripted "ι", and when referring to them collectively without distinction, no subscript shall be added to the designation.

[0069] Furthermore, when distinguishing between multiple second TFTs 25, a second TFT 25 having a second gate electrode 25A connected to the first control wiring 29α and a second source electrode 25B connected to the first drain electrode 24C of the first signal TFT 24α is designated as the "first control TFT (first control switching element)" and its designation is given the subscript "α". A second TFT 25 having a second gate electrode 25A connected to the second control wiring 29β and a second source electrode 25B connected to the first drain electrode 24C of the second signal TFT 24β is designated as the "second control TFT (second control switching element)". A second TFT 25 having a second gate electrode 25A connected to the third control wiring 29γ and a second source electrode 25B connected to the first drain electrode 24C of the third signal TFT 24γ, with the subscript "β" added to its symbol, is designated as a "third control TFT (third control switching element)" and its symbol is designated as a "fourth control TFT (fourth control switching element)" and its symbol is designated as a "fourth control TFT (fourth control switching element)" and its symbol is designated as a "fourth control TFT (fourth control switching element)" and its symbol is designated as a "fourth control TFT (fourth control switching element)" and its symbol is designated as a "fourth control TFT (fourth control switching element)". A second TFT25 having a second gate electrode 25A connected to the second control wiring 29β and a second source electrode 25B connected to the first drain electrode 24C of the fifth signal TFT24ζ is designated as the "fifth control TFT (fifth control switching element)" and its designation is given the subscript "ζ". A second TFT25 having a second gate electrode 25A connected to the third control wiring 29γ and a second source electrode 25B connected to the first drain electrode 24C of the sixth signal TFT24η is designated as the "sixth control TFT (sixth control switching element)" and its designation is given the subscript "η". A second TFT 25 having a second gate electrode 25A connected to line 29δ and a second source electrode 25B connected to the first drain electrode 24C of the seventh signal TFT 24θ is referred to as the "seventh control TFT (seventh control switching element)" and its designation is denoted by the subscript "θ". A second TFT 25 having a second gate electrode 25A connected to the first control wiring 29α and a second source electrode 25B connected to the first drain electrode 24C of the eighth signal TFT 24ι is referred to as the "eighth control TFT (eighth control switching element)" and its designation is denoted by the subscript "ι". When referring to them collectively without distinction,No subscripts shall be added to the symbols.

[0070] In this embodiment, the first pixel electrode 26α is connected to each of the multiple second TFTs 25: the first control TFT 25α, the third control TFT 25γ, the sixth control TFT 25η, and the eighth control TFT 25ι. When distinguishing between the multiple first pixel electrodes 26α, the subscript "1" is added to the code of the first pixel electrode 26α connected to the first control TFT 25α, the subscript "2" is added to the code of the first pixel electrode 26α connected to the third control TFT 25γ, the subscript "3" is added to the code of the first pixel electrode 26α connected to the sixth control TFT 25η, and the subscript "4" is added to the code of the first pixel electrode 26α connected to the eighth control TFT 25ι. When referring to them collectively without distinction, no subscript is added to the code.

[0071] Furthermore, among the multiple second TFTs 25, the second control TFT 25β, the fourth control TFT 25δ, the fifth control TFT 25ζ, and the seventh control TFT 25θ are each connected to a second pixel electrode 26β. When distinguishing between the multiple second pixel electrodes 26β, the code of the second pixel electrode 26β connected to the second control TFT 25β is given the subscript "1", the code of the second pixel electrode 26β connected to the fourth control TFT 25δ is given the subscript "2", the code of the second pixel electrode 26β connected to the fifth control TFT 25ζ is given the subscript "3", and the code of the second pixel electrode 26β connected to the seventh control TFT 25θ is given the subscript "4". When referring to them collectively without distinction, no subscript is added to the code.

[0072] The first main body portion 26Aα of the first pixel electrode 26α1 connected to the first control TFT 25α is positioned between the fifth source wiring 28ζ and the first control wiring 29α in the X-axis direction, as shown in Figure 7, and constitutes an adjacent pixel row with the first control wiring 29α in between to the pixel row to which the first control TFT 25α belongs. In other words, the first main body portion 26Aα of the first pixel electrode 26α1 connected to the first control TFT 25α constitutes the first pixel row C1, counting from the left end in Figures 3 and 10. Furthermore, the first main body portion 26Aα of the first pixel electrode 26α1 is positioned mostly below the gate wiring 27 in Figure 7 relative to the first control TFT 25α in the Y-axis direction, and constitutes an adjacent pixel row with the gate wiring 27 in between to the pixel row to which the first control TFT 25α belongs. The first connection wiring section 26Bα of the first pixel electrode 26α1 is routed so as to intersect with the first control wiring 29α along the way from the first main body 26Aα to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the first control TFT 25α. Specifically, the first connection wiring section 26Bα of the first pixel electrode 26α1 extends from the drain wiring section 43 to which it is to be connected, along the X-axis toward the first control wiring 29α, then extends along diagonal directions with respect to the X-axis and Y-axis, intersecting with the first control wiring 29α, and finally reaching the first main body 26Aα to which it is to be connected.

[0073] The second main body portion 26Aβ of the second pixel electrode 26β1 connected to the second control TFT 25β is positioned between the first source wiring 28α and the second control wiring 29β in the X-axis direction, as shown in Figure 7, and constitutes the pixel row to which the second control TFT 25β belongs. In other words, the second main body portion 26Aβ of the second pixel electrode 26β1 connected to the second control TFT 25β constitutes the third pixel row C3, the third from the left end in Figures 3 and 10. Furthermore, the second main body portion 26Aβ of the second pixel electrode 26β1 is positioned in close proximity to the second control TFT 25β in the Y-axis direction without any gate wiring 27 in between, and constitutes the pixel row to which the second control TFT 25β belongs. The second connection wiring portion 26Bβ of the second pixel electrode 26β1 is routed so as not to cross either the source wiring 28 or the control wiring 29 along the way from the second main body portion 26Aβ to which it is to be connected, to the drain wiring portion 43 connected to the second drain electrode 25C of the second control TFT 25β. Specifically, the second connection wiring portion 26Bβ of the second pixel electrode 26β1 extends from the drain wiring portion 43 to which it is to be connected along the X-axis toward the first source wiring 28α side, then bends, forming a roughly U-shape, to the second main body portion 26Aβ to which it is to be connected. In this way, the second connection wiring portion 26Bβ of the second pixel electrode 26β1 has a folded shape as a whole.

[0074] The first main body portion 26Aα of the first pixel electrode 26α4 connected to the 8th control TFT 25ι is positioned between the first control wiring 29α and the first source wiring 28α in the X-axis direction, as shown in Figure 7, and constitutes an adjacent pixel row with the first control wiring 29α in between to the pixel row to which the 8th control TFT 25ι belongs. In other words, the first main body portion 26Aα of the first pixel electrode 26α4 connected to the 8th control TFT 25ι constitutes the second pixel row C2, counting from the left end in Figures 3 and 10. Furthermore, the first main body portion 26Aα of the first pixel electrode 26α4 is positioned so that there is no gate wiring 27 between it and the 8th control TFT 25ι in the Y-axis direction, and constitutes the pixel row to which the 8th control TFT 25ι belongs. The first connection wiring section 26Bα of the first pixel electrode 26α4 is routed so as to intersect with the first control wiring 29α along the way from the first main body 26Aα to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the eighth control TFT 25ι. More specifically, the first connection wiring section 26Bα of the first pixel electrode 26α4 extends from the drain wiring section 43 to which it is to be connected, along the X-axis towards the first control wiring 29α, intersects with the first control wiring 29α, and then extends along diagonal directions with respect to the X-axis and Y-axis to reach the first main body 26Aα to which it is to be connected.

[0075] The first main body portion 26Aα of the first pixel electrode 26α2 connected to the third control TFT 25γ is positioned between the third source wiring 28γ and the third control wiring 29γ in the X-axis direction, as shown in Figure 8, and constitutes an adjacent pixel row with the third control wiring 29γ in between to the pixel row to which the third control TFT 25γ belongs. In other words, the first main body portion 26Aα of the first pixel electrode 26α2 connected to the third control TFT 25γ constitutes the fifth pixel row C5, the fifth from the left end in Figures 3 and 10. Furthermore, the first main body portion 26Aα of the first pixel electrode 26α2 is positioned mostly below the gate wiring 27 in the Y-axis direction relative to the third control TFT 25γ, and constitutes an adjacent pixel row with the gate wiring 27 in between to the pixel row to which the third control TFT 25γ belongs. The first connection wiring section 26Bα of the first pixel electrode 26α2 is routed so as to intersect with the third control wiring 29γ along the way from the first main body 26Aα to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the third control TFT 25γ. Specifically, the first connection wiring section 26Bα of the first pixel electrode 26α2 extends from the drain wiring section 43 to which it is to be connected, along the X-axis toward the third control wiring 29γ, then extends along diagonal directions with respect to the X-axis and Y-axis, intersecting with the first control wiring 29α, and reaching the first main body 26Aα to which it is to be connected. The first connection wiring section 26Bα of the first pixel electrode 26α2 has the same planar shape as the first connection wiring section 26Bα of the first pixel electrode 26α1, and their line width and area are approximately the same.

[0076] The second main body portion 26Aβ of the second pixel electrode 26β3 connected to the fifth control TFT 25ζ is positioned between the second control wiring 29β and the third source wiring 28γ in the X-axis direction, as shown in Figure 8, and constitutes the pixel row to which the fifth control TFT 25ζ belongs. In other words, the second main body portion 26Aβ of the second pixel electrode 26β3 connected to the fifth control TFT 25ζ constitutes the fourth pixel row C4, the fourth from the left end in Figures 3 and 10. Furthermore, the second main body portion 26Aβ of the second pixel electrode 26β3 is mostly positioned below the fifth control TFT 25ζ in the Y-axis direction, with the gate wiring 27 in between, and constitutes the adjacent pixel row to the pixel row to which the fifth control TFT 25ζ belongs, with the gate wiring 27 in between. The second connection wiring section 26Bβ of the second pixel electrode 26β3 is routed so as not to cross either the source wiring 28 or the control wiring 29 along the way from the second main body 26Aβ to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the fifth control TFT 25ζ. Specifically, the second connection wiring section 26Bβ of the second pixel electrode 26β3 extends from the drain wiring section 43 to which it is to be connected along the X-axis toward the third source wiring 28γ, then bends, extends along the Y-axis while crossing at least a part of the gate wiring 27, and then reaches the second main body 26Aβ to which it is to be connected. Thus, the second connection wiring section 26Bβ of the second pixel electrode 26β3 is generally L-shaped.

[0077] The first main body portion 26Aα of the first pixel electrode 26α3 connected to the sixth control TFT 25η is positioned between the third control wiring 29γ and the second source wiring 28β in the X-axis direction, as shown in Figure 8, and constitutes an adjacent pixel row with the third control wiring 29γ in between to the pixel row to which the sixth control TFT 25η belongs. In other words, the first main body portion 26Aα of the first pixel electrode 26α3 connected to the sixth control TFT 25η constitutes the sixth pixel row C6, the sixth from the left end in Figures 3 and 10. Furthermore, the first main body portion 26Aα of the first pixel electrode 26α3 is positioned so that there is no gate wiring 27 between it and the sixth control TFT 25η in the Y-axis direction, and constitutes the pixel row to which the sixth control TFT 25η belongs. The first connection wiring section 26Bα of the first pixel electrode 26α3 is routed so as to intersect with the third control wiring 29γ along the way from the first main body 26Aα to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the sixth control TFT 25η. Specifically, the first connection wiring section 26Bα of the first pixel electrode 26α3 extends from the drain wiring section 43 to which it is to be connected, along the X-axis toward the third control wiring 29γ, intersects with the third control wiring 29γ, and then extends along diagonal directions with respect to the X-axis and Y-axis to reach the first main body 26Aα to which it is to be connected. The first connection wiring section 26Bα of the first pixel electrode 26α3 has a planar shape similar to the first connection wiring section 26Bα of the first pixel electrode 26α4, and their line width and area are approximately the same.

[0078] The second main body portion 26Aβ of the second pixel electrode 26β2 connected to the fourth control TFT 25δ is positioned between the second source wiring 28β and the fourth control wiring 29δ in the X-axis direction, as shown in Figure 9, and constitutes the pixel row to which the fourth control TFT 25δ belongs. In other words, the second main body portion 26Aβ of the second pixel electrode 26β2 connected to the fourth control TFT 25δ constitutes the seventh pixel row C7, which is the seventh from the left end in Figures 3 and 10. Furthermore, the second main body portion 26Aβ of the second pixel electrode 26β2 is positioned in close proximity to the second control TFT 25β in the Y-axis direction without the gate wiring 27 in between, and constitutes the pixel row to which the fourth control TFT 25δ belongs. The second connection wiring section 26Bβ of the second pixel electrode 26β2 is routed so as not to cross either the source wiring 28 or the control wiring 29 along the way from the second main body 26Aβ to which it is to be connected, to the drain wiring section 43 connected to the second drain electrode 25C of the fourth control TFT 25δ. Specifically, the second connection wiring section 26Bβ of the second pixel electrode 26β2 extends from the drain wiring section 43 to which it is to be connected along the X-axis toward the second source wiring 28β side, then bends, forming a roughly U-shape, to the second main body 26Aβ to which it is to be connected. In this way, the second connection wiring section 26Bβ of the second pixel electrode 26β2 has a folded shape as a whole. The second connection wiring section 26Bβ of the second pixel electrode 26β2 has the same planar shape as the second connection wiring section 26Bβ of the second pixel electrode 26β1, and their line width and area are approximately the same.

[0079] The second main body portion 26Aβ of the second pixel electrode 26β4 connected to the seventh control TFT 25θ is positioned between the fourth control wiring 29δ and the fourth source wiring 28δ in the X-axis direction, as shown in Figure 3, and constitutes the pixel row to which the seventh control TFT 25θ belongs, as shown in Figure 8. In other words, the second main body portion 26Aβ of the second pixel electrode 26β4 connected to the seventh control TFT 25θ constitutes the eighth pixel row C8, the eighth from the left end in Figures 3 and 10. Furthermore, the second main body portion 26Aβ of the second pixel electrode 26β4 is mostly positioned below the gate wiring 27 in Figure 8 relative to the seventh control TFT 25θ in the Y-axis direction, and constitutes the adjacent pixel row to the pixel row to which the seventh control TFT 25θ belongs, separated by the gate wiring 27. The second connection wiring section 26Bβ of the second pixel electrode 26β4 is routed so as not to cross either the source wiring 28 or the control wiring 29 along the way from the second main body 26Aβ to which it is to be connected to the drain wiring section 43 connected to the second drain electrode 25C of the seventh control TFT 25θ. Specifically, the second connection wiring section 26Bβ of the second pixel electrode 26β4 extends from the drain wiring section 43 to which it is to be connected along the X-axis toward the fourth source wiring 28δ, then bends, extends along the Y-axis while crossing at least a part of the gate wiring 27, and then reaches the second main body 26Aβ to which it is to be connected. Thus, the second connection wiring section 26Bβ of the second pixel electrode 26β4 is approximately L-shaped overall. The second connection wiring section 26Bβ of the second pixel electrode 26β4 has a planar shape similar to the second connection wiring section 26Bβ of the second pixel electrode 26β3, and its line width and area are approximately the same.

[0080] As shown in Figure 10, the non-display area NAA of the array substrate 21 is provided with a short-circuit wiring 44 that short-circuits two source wirings 28, a lead wiring 45 that extends from the source wirings 28 to the driver 12, and a plurality of control trunk wirings 46-49 that connect to the control wiring 29. The short-circuit wiring 44, lead wiring 45, and control trunk wirings 46-49 are arranged in the Y-axis direction between the display area AA and the driver 12 (see Figure 1).

[0081] As shown in Figure 10, the short-circuit wiring 44 extends along the X-axis direction, with both ends connected to two source wirings 28 that are to be connected. The short-circuit wiring 44 intersects with two control wirings 29 and with one source wiring 28 that is not to be connected. The short-circuit wiring 44 includes the short-circuit wiring 44 connected to the nth source wiring 28 and the (n+2)th source wiring 28, and the short-circuit wiring 44 connected to the (n+1)th source wiring 28 and the (n+3)th source wiring 28 (n: natural number). The short-circuit wiring 44 can be made of, for example, a part of the first metal film, in which case a contact hole for connecting the short-circuit wiring 44 and the source wiring 28 should be provided at the overlapping position of the short-circuit wiring 44 and the source wiring 28 to be connected within the gate insulating film 35. If the short-circuit wiring 44 is made of a part of the first metal film, then short circuits between the short-circuit wiring 44 and the source wiring 28 that intersects with the short-circuit wiring 44, and short circuits between the short-circuit wiring 44 and the control wiring 29 that intersects with the short-circuit wiring 44, are both prevented by the gate insulating film 35.

[0082] In the following, when distinguishing between multiple short-circuit wirings 44, the short-circuit wiring 44 connected to the first source wiring 28α and the second source wiring 28β will be referred to as the "first short-circuit wiring" and its designation will be amended with the subscript "α", the short-circuit wiring 44 connected to the third source wiring 28γ and the fourth source wiring 28δ will be referred to as the "second short-circuit wiring" and its designation will be amended with the subscript "β", and when referring to them collectively without distinction, no subscript will be added to the designation.

[0083] As shown in Figure 10, the lead wire 45 extends along the Y-axis, with one end connected to the source wire 28 and the other end connected to the driver 12 (see Figure 1). In this embodiment, the lead wire 45 is connected to one of the two source wires 28 that are short-circuited by the short-circuit wire 44. The lead wire 45 can be made of, for example, a part of the second metal film, in which case it will be directly connected to the source wire 28 to which it is connected. The image signals supplied to each of the two source wires 28 that are short-circuited by the short-circuit wire 44 are supplied to the lead wire 45 from the driver 12. Therefore, compared to the case where the first short-circuit wire 44α is omitted and the first source wire 28α and the second source wire 28β are each connected to the driver 12, the number of wires in the area between the driver 12 and the display area AA in the non-display area NAA can be reduced. This is advantageous for achieving a narrow bezel.

[0084] In the following, when distinguishing between multiple lead wires 45, the lead wire 45 connected to the first source wire 28α will be referred to as the "first lead wire" and its designation will be given the subscript "α", the lead wire 45 connected to the fourth source wire 28δ will be referred to as the "second lead wire" and its designation will be given the subscript "β", and the lead wire 45 connected to the fifth source wire 28ζ will be referred to as the "third lead wire" and its designation will be given the subscript "γ". When referring to them collectively without distinction, no subscript will be added to the designation.

[0085] As shown in Figure 10, the multiple control trunk wires 46-49 extend along the X-axis in at least the region sandwiched between the display area AA and the driver 12, and are arranged side by side with spacing in the Y-axis direction. The multiple control trunk wires 46-49 include the first control trunk wire 46 connected to the first control trunk wire 29α, the second control trunk wire 47 connected to the second control trunk wire 29β, the third control trunk wire 48 connected to the third control trunk wire 29γ, and the fourth control trunk wire 49 connected to the fourth control trunk wire 29δ. Each end of the multiple control trunk wires 46-49 is connected to a terminal that is connected to the flexible substrate 13. As a result, control signals are supplied to the multiple control trunk wires 46-49 from the control board 14 via the flexible substrate 13.

[0086] This embodiment has the structure described above, and its operation will now be explained mainly using Figures 10 to 14. Figures 11 and 13 show the signal waveforms for gate wiring 27, source wiring 28α to 28ζ, and control wiring 29α to 29δ. Figure 13 shows the waveforms of each signal output after one frame display period, following the output of each signal shown in Figure 11. Specifically, Figures 11 and 13 show, from top to bottom, a scanning signal G1 transmitted by a predetermined gate wiring 27, a control signal SWA transmitted by a first control wiring 29α, a control signal SWB transmitted by a second control wiring 29β, a control signal SWC transmitted by a third control wiring 29γ, a control signal SWD transmitted by a fourth control wiring 29δ, an image signal S1 transmitted by a first source wiring 28α and a second source wiring 28β, and an image signal S2 (image signal S0 transmitted by a fifth source wiring 28ζ) transmitted by a third source wiring 28γ and a fourth source wiring 28δ. Note that the image signal S0 transmitted by the fifth source wiring 28ζ has the same polarity as the image signal S2 transmitted by the third source wiring 28γ and a fourth source wiring 28δ, and is therefore shown together as "S0 / S2". Note that the image signals S0 and S2 only need to have the same polarity, and their voltages during each period may be different from each other. On the other hand, Figures 12 and 14 schematically illustrate the pixel electrodes 26α1~26α4, 26β1~26β4, gate wiring 27, source wiring 28α~28ζ, and control wiring 29α~29δ, and indicate the positive and negative polarity of the image signal written to each pixel electrode 26α1~26α4, 26β1~26β4 with the signs "+" and "-".

[0087] As shown in Figures 1, 10, and 11, when a high-level potential of the scan signal G1 (hereinafter referred to as "high potential") is supplied from the gate drive circuit 15 to a gate wiring 27, the control board 14 supplies high potentials of control signals SWA to SWD to each control wiring 29α to 29δ at different timings in synchronization with this. At the same time, the driver 12 supplies image signals S0 to S2 to each source wiring 28α to 28ζ in synchronization with the timing at which control signals SWA to SWD are supplied to each control wiring 29α to 29δ. Here, the high potential is a potential higher than the threshold voltage of the first TFT 24 and the second TFT 25. The period during which control signals SWA to SWD are at high potential is approximately 1 / 4 of the period during which the scan signal G1 is at high potential, that is, the reciprocal of the total number of control signals SWA to SWD. Furthermore, the first source wiring 28α and the second source wiring 28β are supplied with a positive polarity image signal S1, while the third source wiring 28γ and the fourth source wiring 28δ are supplied with a negative polarity image signal S2, and the fifth source wiring 28ζ is supplied with a negative polarity image signal S0. In other words, the driver 12 has reverse polarity for image signal S1 and image signals S0 and S2. The control signals SWA to SWD output from the control board 14 are supplied to the control wirings 29α to 29δ via the flexible board 13 and control trunk wirings 46 to 49. The image signal S1 output from the driver 12 is supplied to the first source wiring 28α and the second source wiring 28β via the first lead wiring 45α and the first short circuit wiring 44α. The image signal S2 output from the driver 12 is supplied to the third source wiring 28γ and the fourth source wiring 28δ via the second lead wiring 45β and the second short circuit wiring 44β. The image signal S0 output from the driver 12 is supplied to the fifth source wiring 28ζ via the third lead wiring 45γ.

[0088] Specifically, as shown in Figures 10 and 11, when a high potential of the scanning signal G1 is supplied to the gate wiring 27, all first TFTs 24 constituting the pixel row to which the first TFT 24 connected to the gate wiring 27 to which the scanning signal G1 is supplied belongs are driven simultaneously. While a high potential of the scanning signal G1 is supplied to the gate wiring 27, high potentials of the control signals SWA to SWD are supplied in the order of first control wiring 29α, second control wiring 29β, third control wiring 29γ, and fourth control wiring 29δ. More specifically, the timing of the rising edge of the high potential of the scanning signal G1 coincides with the rising edge of the high potential of the control signal SWA. The timing of the falling edge of the high potential of the control signal SWA coincides with the rising edge of the high potential of the control signal SWB. The timing of the falling edge of the high potential of the control signal SWB coincides with the rising edge of the high potential of the control signal SWC. The timing of the falling edge of the high potential of control signal SWC coincides with the rising edge of the high potential of control signal SWD. The timing of the falling edge of the high potential of control signal SWD coincides with the falling edge of the high potential of scan signal G1.

[0089] As shown in Figures 10 and 11, while the gate wiring 27 is supplied with a high potential of the scanning signal G1, each source wiring 28α to 28ζ is supplied with image signals S0 to S2 in synchronization with the timing when the control signals SWA to SWD become high. When the multiple first TFTs 24 connected to the gate wiring 27 are driven simultaneously, the image signals S0 to S2 supplied to each source wiring 28α to 28ζ are supplied to the second source electrode 25B of the second TFT 25. At this time, among the multiple second TFTs 25, the one supplied with the control signals SWA to SWD, which become high at the second gate electrode 25A, is selectively driven. As a result, the pixel electrode 26 connected to the selectively driven second TFT 25 is selectively charged to the potential related to the image signals S0 to S2.

[0090] Specifically, as shown in Figures 10 and 11, while the control signal SWA is at a high potential, the driver 12 synchronously supplies the image signal S1 to the first signal TFT 24α (first pixel electrode 26α1) and the image signal S0 to the eighth signal TFT 24ι (first pixel electrode 26α4) to the first lead wire 45α and the third lead wire 45γ, respectively. Here, while the control signal SWA is at a high potential, the control signals SWB~SWD are at a low potential (hereinafter referred to as low potential). Therefore, while the control signal SWA is at a high potential, the first control TFT 25α and the eighth control TFT 25ι connected to the first control wiring 29α are driven, but the second control TFT 25β and the fifth control TFT 25ζ connected to the second control wiring 29β, the third control TFT 25γ and the sixth control TFT 25η connected to the third control wiring 29γ, and the fourth control TFT 25δ and the seventh control TFT 25θ connected to the fourth control wiring 29δ are not driven. Therefore, the image signal S1 supplied from the driver 12 to the first source wiring 28α and the second source wiring 28β via the first lead wiring 45α and the first short-circuit wiring 44α is supplied to the first pixel electrode 26α1 via the jointly driven first signal TFT 24α and the first control TFT 25α, but is not supplied to the second pixel electrode 26β1, the first pixel electrode 26α2, and the second pixel electrode 26β2, which are connected to the second control TFT 25β, the third control TFT 25γ, and the fourth control TFT 25δ, which are in an undriven state. On the other hand, the image signal S0 supplied from the driver 12 to the fifth source wiring 28ζ is supplied to the first pixel electrode 26α4 via the jointly driven eighth signal TFT 24ι and the eighth control TFT 25ι. As a result, the first pixel electrode 26α1 belonging to the first pixel row C1 is charged to a positive potential related to the image signal S1, as shown in Figure 12, and the first pixel electrode 26α4 belonging to the second pixel row C2 is charged to a negative potential related to the image signal S0.

[0091] As shown in Figures 10 and 11, while the control signal SWB is at a high potential, the driver 12 synchronously supplies the image signal S1 to the second signal TFT 24β (second pixel electrode 26β1) and the image signal S2 to the fifth signal TFT 24ζ (second pixel electrode 26β3) to the first lead wire 45α and the second lead wire 45β, respectively. Here, while the control signal SWB is at a high potential, the control signals SWA, SWC, and SWD are at a low potential. Therefore, while the control signal SWB is at a high potential, the second control TFT 25β and the fifth control TFT 25ζ connected to the second control wiring 29β are driven, but the first control TFT 25α and the eighth control TFT 25ι connected to the first control wiring 29α, the third control TFT 25γ and the sixth control TFT 25η connected to the third control wiring 29γ, and the fourth control TFT 25δ and the seventh control TFT 25θ connected to the fourth control wiring 29δ are not driven. Therefore, the image signal S1 supplied from the driver 12 to the first source wiring 28α and the second source wiring 28β via the first lead wiring 45α and the first short-circuit wiring 44α is supplied to the second pixel electrode 26β1 via the second signal TFT 24β and the second control TFT 25β which are driven together, but it is not supplied to the first pixel electrode 26α1, the first pixel electrode 26α2, and the second pixel electrode 26β2 which are connected to the first control TFT 25α, the third control TFT 25γ, and the fourth control TFT 25δ, which are in an undriven state. On the other hand, the image signal S2 supplied from the driver 12 to the third source wiring 28γ and the fourth source wiring 28δ via the second lead wiring 45β and the second short-circuit wiring 44β is supplied to the second pixel electrode 26β3 via the jointly driven fifth signal TFT 24ζ and fifth control TFT 25ζ, but is not supplied to the first pixel electrode 26α3 and the second pixel electrode 26β4 connected to the sixth control TFT 25η and the seventh control TFT 25θ, which are in an undriven state. As a result, the second pixel electrode 26β1 belonging to the third pixel row C3 is charged to a positive potential related to the image signal S1, as shown in Figure 12, and the second pixel electrode 26β3 belonging to the fourth pixel row C4 is charged to a negative potential related to the image signal S2.

[0092] As shown in Figures 10 and 11, while the control signal SWC is at a high potential, the driver 12 synchronously supplies the image signal S1 to the third signal TFT 24γ (first pixel electrode 26α2) and the image signal S2 to the sixth signal TFT 24η (first pixel electrode 26α3) to the first lead wire 45α and the second lead wire 45β, respectively. Here, while the control signal SWC is at a high potential, the control signals SWA, SWB, and SWD are at a low potential. Therefore, while the control signal SWC is at a high potential, the third control TFT 25γ and the sixth control TFT 25η connected to the third control wiring 29γ are driven, but the first control TFT 25α and the eighth control TFT 25ι connected to the first control wiring 29α, the second control TFT 25β and the fifth control TFT 25ζ connected to the second control wiring 29β, and the fourth control TFT 25δ and the seventh control TFT 25θ connected to the fourth control wiring 29δ are not driven. Therefore, the image signal S1 supplied from the driver 12 to the first source wiring 28α and the second source wiring 28β via the first lead wiring 45α and the first short-circuit wiring 44α is supplied to the first pixel electrode 26α2 via the jointly driven third signal TFT 24γ and third control TFT 25γ, but is not supplied to the first pixel electrode 26α1, the second pixel electrode 26β1, and the second pixel electrode 26β2, which are connected to the first control TFT 25α, the second control TFT 25β, and the fourth control TFT 25δ, which are in an undriven state. On the other hand, the image signal S2 supplied from the driver 12 to the third source wiring 28γ and the fourth source wiring 28δ via the second lead wiring 45β and the second short-circuit wiring 44β is supplied to the first pixel electrode 26α3 via the sixth signal TFT 24η and the sixth control TFT 25η, which are driven together, but is not supplied to the second pixel electrodes 26β3 and 26β4 connected to the fifth control TFT 25ζ and the seventh control TFT 25θ, which are in an undriven state. As a result, the first pixel electrode 26α2 belonging to the fifth pixel row C5 is charged to a positive potential related to the image signal S1, as shown in Figure 12, and the first pixel electrode 26α3 belonging to the sixth pixel row C6 is charged to a negative potential related to the image signal S2.

[0093] As shown in Figures 10 and 11, while the control signal SWD is at a high potential, the driver 12 synchronously supplies the image signal S1 to the fourth signal TFT 24δ (second pixel electrode 26β2) and the image signal S2 to the seventh signal TFT 24θ (second pixel electrode 26β4) to the first lead wire 45α and the second lead wire 45β, respectively. Here, while the control signal SWD is at a high potential, the control signals SWA, SWB, and SWC are at a low potential. Therefore, while the control signal SWD is at a high potential, the fourth control TFT 25δ and the seventh control TFT 25θ connected to the fourth control wiring 29δ are driven, but the first control TFT 25α and the eighth control TFT 25ι connected to the first control wiring 29α, the second control TFT 25β and the fifth control TFT 25ζ connected to the second control wiring 29β, and the third control TFT 25γ and the sixth control TFT 25η connected to the third control wiring 29γ are not driven. Therefore, the image signal S1 supplied from the driver 12 to the first source wiring 28α and the second source wiring 28β via the first lead wiring 45α and the first short-circuit wiring 44α is supplied to the second pixel electrode 26β2 via the jointly driven fourth signal TFT 24δ and fourth control TFT 25δ, but is not supplied to the first pixel electrode 26α1, the second pixel electrode 26β1, and the first pixel electrode 26α2, which are connected to the first control TFT 25α, the second control TFT 25β, and the third control TFT 25γ, which are in an undriven state. On the other hand, the image signal S2 supplied from the driver 12 to the third source wiring 28γ and the fourth source wiring 28δ via the second lead wiring 45β and the second short-circuit wiring 44β is supplied to the second pixel electrode 26β4 via the seventh signal TFT 24θ and the seventh control TFT 25θ, which are driven together, but is not supplied to the second pixel electrode 26β3 and the first pixel electrode 26α3, which are connected to the fifth control TFT 25ζ and the sixth control TFT 25η, which are in an undriven state. As a result, the second pixel electrode 26β2 belonging to the seventh pixel row C7 is charged to a positive potential related to the image signal S1, as shown in Figure 12, and the second pixel electrode 26β4 belonging to the eighth pixel row C8 is charged to a negative potential related to the image signal S2.

[0094] In this way, a high potential is supplied to each gate wiring 27 sequentially as scanning signals G1, G2, and G3. When the signals shown in Figure 11 are output during the period when the scanning signals are at a high potential, the first pixel electrode 26α1 belonging to the first pixel row C1, the second pixel electrode 26β1 belonging to the third pixel row C3, the first pixel electrode 26α2 belonging to the fifth pixel row C5, and the second pixel electrode 26β2 belonging to the seventh pixel row C7 are each charged to a positive potential, as shown in Figure 12. The first pixel electrode 26α4 belonging to the second pixel row C2, the second pixel electrode 26β3 belonging to the fourth pixel row C4, the first pixel electrode 26α3 belonging to the sixth pixel row C6, and the second pixel electrode 26β4 belonging to the eighth pixel row C8 are each charged to a negative potential. Therefore, by sequentially supplying a high potential as a scanning signal to multiple gate wirings 27, adjacent pixel rows in the X-axis direction become opposite in polarity to each other, resulting in a "row inversion drive" where pixel rows with the same polarity are not adjacent. The reason why such a "row inversion drive" is realized is that the first connection wiring section 26Bα of the first pixel electrode 26α intersects with the source wiring 28 or control wiring 29, thereby ensuring the degree of freedom in the placement of the first main body section 26Aα. It is assumed that the polarity of each image signal S0 to S2 remains unchanged during a certain frame display period. For example, if the image signal S1 during the period when a high potential is supplied as the scanning signal G1 is positive polarity, then the image signal S1 during the period when a high potential is supplied as the scanning signals G2 and G3 supplied to the subsequent gate wirings 27 will also be positive polarity. Conversely, if the image signals S0 and S2 during the period when a high potential is supplied as the scanning signal G1 are negative polarity, then the image signals S0 and S2 during the period when a high potential is supplied as the scanning signals G2 and G3 supplied to the subsequent gate wirings 27 will also be negative polarity.

[0095] After each signal shown in Figure 11 is output and one frame has been displayed, each signal shown in Figure 13 is output. Of the signals shown in Figure 13, the scan signal G1 and control signals SWA~SWD are the same as those shown in Figure 11, but the image signals S0~S2 have the opposite polarity to those shown in Figure 11. Specifically, the first source wiring 28α and the second source wiring 28β are supplied with the negative polarity image signal S1, the third source wiring 28γ and the fourth source wiring 28δ are supplied with the positive polarity image signal S2, and the fifth source wiring 28ζ is supplied with the positive polarity image signal S0.

[0096] When each signal shown in Figure 13 is output, as shown in Figure 14, the first pixel electrode 26α1 belonging to the first pixel row C1, the second pixel electrode 26β1 belonging to the third pixel row C3, the first pixel electrode 26α2 belonging to the fifth pixel row C5, and the second pixel electrode 26β2 belonging to the seventh pixel row C7 are each charged to a negative potential. The first pixel electrode 26α4 belonging to the second pixel row C2, the second pixel electrode 26β3 belonging to the fourth pixel row C4, the first pixel electrode 26α3 belonging to the sixth pixel row C6, and the second pixel electrode 26β4 belonging to the eighth pixel row C8 are each charged to a positive potential. In other words, the polarity is reversed compared to the pixel electrodes 26α1~26α and 26β1~26β4 shown in Figure 12.

[0097] As described above, according to this embodiment, it is possible to distribute the signal supplied to one first source wiring 28α to a first pixel electrode 26α1, which is a pixel electrode 26 to be connected to the first control TFT 25α connected to the first control wiring 29α, and to a second pixel electrode 26β1, which is a pixel electrode 26 to be connected to the second control TFT 25β connected to the second control wiring 29β. Furthermore, it is possible to distribute the signal supplied to one second source wiring 28β to a first pixel electrode 26α2, which is a pixel electrode 26 to be connected to the third control TFT 25γ connected to the third control wiring 29γ, and to a second pixel electrode 26β2, which is a pixel electrode 26 to be connected to the fourth control TFT 25δ connected to the fourth control wiring 29δ. Furthermore, the signal supplied to one third source wiring 28γ can be distributed to the second pixel electrode 26β3, which is the pixel electrode 26 to be connected to the fifth control TFT 25ζ connected to the second control wiring 29β, and to the first pixel electrode 26α3, which is the pixel electrode 26 to be connected to the sixth control TFT 25η connected to the third control wiring 29γ. This reduces the number of source wirings 28 that need to be installed.

[0098] Furthermore, during a certain frame display period, while a high potential is supplied to the gate wiring 27 as a scanning signal, the driver 12 supplies image signals of the same polarity (positive or negative) to the first source wiring 28α and the second source wiring 28β, and also supplies image signals of the same polarity (negative or positive) to the third source wiring 28γ and the fourth source wiring 28δ. In other words, during a certain frame display period, the polarity of the image signals supplied to each source wiring 28 does not reverse. Therefore, compared to the case where the driver 12 supplies image signals of the opposite polarity to each source wiring 28 at the timing when a control signal is supplied from the control board 14 to each control wiring 29, the power consumption required for the driver 12 to supply image signals can be reduced.

[0099] As described above, the liquid crystal display device (display device) 10 of this embodiment includes gate wiring (scanning wiring) 27 extending along a first direction, source wiring (signal wiring) 28 extending along a second direction intersecting the first direction and intersecting the gate wiring 27, control wiring 29 extending along the second direction, spaced apart from the source wiring 28 and intersecting the gate wiring 27, a plurality of pixel electrodes 26 arranged in a matrix in the first and second directions, a first TFT (first switching element) 24, and a second TFT (second switching element) 25. The first TFT 24 includes a first gate electrode (first electrode) 24A connected to one of the gate wiring 27 and the control wiring 29, a first source electrode (second electrode) 24B connected to the source wiring 28, a first drain electrode (third electrode) 24C, and the first source electrode 24B and the first drain The second TFT 25 has a first semiconductor portion 24D connected to the in electrode 24C and superimposed on the first gate electrode 24A, a second gate electrode (fourth electrode) 25A connected to the other of the gate wiring 27 and the control wiring 29, a second source electrode (fifth electrode) 25B connected to the first drain electrode 24C, a second drain electrode (sixth electrode) 25C connected to the pixel electrode 26, and a second semiconductor portion 25D connected to the second source electrode 25B and the second drain electrode 25C and superimposed on the second gate electrode 25A, and a plurality of pixel electrodes 26 include a first pixel electrode 26α, the first pixel electrode 26α has a first main body portion 26Aα and a first connection wiring portion 26Bα connected to the first main body portion 26Aα and the second drain electrode 25C, the first connection wiring portion 26Bα intersects with the control wiring 29 or the source wiring 28.

[0100] When a high potential is supplied to the gate wiring 27, the first TFT 24 or the second TFT 25 connected to the gate wiring 27 is driven. When a high potential is supplied to the control wiring 29, the first TFT 24 or the second TFT 25 connected to the control wiring 29 is driven. When a signal is supplied to the source wiring 28 in synchronization with the timing when the first TFT 24 is driven, the signal from the source wiring 28 is supplied from the first source electrode 24B to the first drain electrode 24C via the first semiconductor section 24D. When the second TFT 25 is driven in synchronization with the timing when the first TFT 24 is driven, the signal from the first drain electrode 24C is supplied from the second source electrode 25B to the second drain electrode 25C via the second semiconductor section 25D. As a result, the pixel electrode 26 connected to the second drain electrode 25C is charged. The first pixel electrode 26α, included in the multiple pixel electrodes 26, has a first connection wiring section 26Bα connected to the first main body 26Aα and the second drain electrode 25C, and this first connection wiring section 26Bα intersects with the source wiring 28 or control wiring 29. By intersecting the first connection wiring section 26Bα with the source wiring 28 or control wiring 29 in this way, the degree of freedom in the placement of the first main body 26Aα of the first pixel electrode 26α can be increased. If the degree of freedom in the placement of the first main body 26Aα of the first pixel electrode 26α is increased, even if an image signal is supplied to each source wiring 28 in which the polarity does not reverse during a certain frame display period, but the polarity reverses every frame display period, pixels with the same polarity will not alternate in two rows, and vertical streak-like display defects will be less visible. Therefore, it is possible to reduce power consumption while ensuring display quality.

[0101] Furthermore, the first main body portion 26Aα is positioned between the second TFT 25 to which the first connection wiring portion 26Bα is connected, with the control wiring 29 or source wiring 28 in between. The first main body portion 26Aα and the second TFT 25 to which the first connection wiring portion 26Bα is connected are positioned with the control wiring 29 or source wiring 28 in between. The first main body portion 26Aα and the second TFT 25 in this positional relationship can be connected by the first connection wiring portion 26Bα which intersects with the control wiring 29 or source wiring 28. This increases the degree of freedom in the placement of the first pixel electrode 26α relative to the first main body portion 26Aα.

[0102] Furthermore, the first gate electrode 24A is connected to the gate wiring 27, and the second gate electrode 25A is connected to the control wiring 29. When a high potential is supplied to the gate wiring 27, the first TFT 24 having the first gate electrode 24A connected to the gate wiring 27 is driven. When a high potential is supplied to the control wiring 29, the second TFT 25 having the second gate electrode 25A connected to the control wiring 29 is driven.

[0103] Furthermore, the second TFT 25 is positioned closer to the control wiring 29 than to the source wiring 28. Compared to the case where the second TFT is positioned closer to the source wiring 28 than to the control wiring 29, the distance between the second gate electrode 25A of the second TFT 25 and the control wiring 29 connected to the second gate electrode 25A can be shortened. This makes it less likely for the signal supplied from the control wiring 29 to the second gate electrode 25A to be blunted due to parasitic capacitance or electrical resistance.

[0104] Furthermore, the first TFT 24 is positioned closer to the source wiring 28 than to the control wiring 29. Compared to the case where the first TFT is positioned closer to the control wiring 29 than to the source wiring 28, the distance between the first source electrode 24B of the first TFT 24 and the source wiring 28 connected to the first source electrode 24B can be shortened. This makes it less likely for the signal supplied from the source wiring 28 to the first source electrode 24B to be blunted due to parasitic capacitance or electrical resistance.

[0105] Furthermore, multiple control lines 29 are arranged at spaced intervals in the first direction, and each of the multiple control lines 29 includes a first control line 29α and a second control line 29β. Multiple source lines 28 are arranged at spaced intervals in the first direction, and each of the multiple source lines 28 includes a first source line (first signal line) 28α. Multiple second TFTs 25 are arranged at spaced intervals in the first direction, and each of the multiple second TFTs 25 includes a first control TFT (first control switching element) 25α which is a second TFT 25 having a second gate electrode 25A connected to the first control line 29α, and a second control TFT 25 which is a second TFT 25 having a second gate electrode 25A connected to the second control line 29β. The first TFT 24 includes a TFT (second control switching element) 25β, and multiple first TFTs 24 are arranged at spaced intervals in a first direction, with the multiple first TFTs 24 including a first signal TFT (first signal switching element) 24α which is a first TFT 24 having a first source electrode 24B connected to a first source wiring 28α and a first drain electrode 24C connected to a second source electrode 25B of the first control TFT 25α, and a second signal TFT (second signal switching element) 24β which is a first TFT 24 having a first source electrode 24B connected to a first source wiring 28α and a first drain electrode 24C connected to a second source electrode 25B of the second control TFT 25β. A signal is supplied to the first source wiring 28α in synchronization with the timing when a high potential is supplied to the first control wiring 29α while a high potential is supplied to the gate wiring 27. As a result, the first control TFT 25α connected to the first control wiring 29α and the first signal TFT 24α connected to the first control TFT 25α are driven, and the signal supplied to the first source wiring 28α is supplied to the pixel electrode 26 to which the first control TFT 25α is connected. Meanwhile, while a high potential is supplied to the gate wiring 27, a signal is supplied to the first source wiring 28α in synchronization with the timing when a high potential is supplied to the second control wiring 29β. As a result, the second control TFT 25β connected to the second control wiring 29β and the second signal TFT 24β connected to the second control TFT 25β are driven, and the signal supplied to the first source wiring 28α is supplied to the pixel electrode 26 to which the second control TFT 25β is connected.Based on the above, it becomes possible to distribute the signal supplied to one first source wiring 28α to the pixel electrode 26 to be connected to the first control TFT 25α which is connected to the first control wiring 29α, and to the pixel electrode 26 to be connected to the second control TFT 25β which is connected to the second control wiring 29β.

[0106] Furthermore, the system includes a control board (first signal supply unit) 14 connected to multiple control wirings 29 and supplying signals to the multiple control wirings 29. The control board 14 supplies a high potential to the first control wiring 29α and the second control wiring 29β at different timings. In this way, by supplying a high potential to the first control wiring 29α and the second control wiring 29β from the control board 14 at different timings, the signal supplied to one source wiring 28 can be distributed to the pixel electrode 26 that is the target of connection to the first control TFT 25α connected to the first control wiring 29α, and to the pixel electrode 26 that is the target of connection to the second control TFT 25β connected to the second control wiring 29β.

[0107] Furthermore, the multiple control lines 29 include a third control line 29γ and a fourth control line 29δ, the multiple source lines 28 include a second source line (second signal line) 28β, and the multiple second TFTs 25 include a third control TFT (third control switching element) 25γ which is a second TFT 25 having a second gate electrode 25A connected to the third control line 29γ, and a fourth control TFT (fourth control switching element) 25δ which is a second TFT 25 having a second gate electrode 25A connected to the fourth control line 29δ, and multiple first The TFT24 includes a third signal TFT (third signal switching element) 24γ, which is a first TFT24 having a first source electrode 24B connected to the second source wiring 28β and a first drain electrode 24C connected to the second source electrode 25B of the third control TFT25γ, and a fourth signal TFT (fourth signal switching element) 24δ, which is a first TFT24 having a first source electrode 24B connected to the second source wiring 28β and a first drain electrode 24C connected to the second source electrode 25B of the fourth control TFT25δ. While a high potential is supplied to the gate wiring 27, a signal is supplied to the second source wiring 28β in synchronization with the timing when a high potential is supplied to the third control wiring 29γ. As a result, the third control TFT 25γ connected to the third control wiring 29γ and the third signal TFT 24γ connected to the third control TFT 25γ are driven, and the signal supplied to the second source wiring 28β is supplied to the pixel electrode 26 to which the third control TFT 25γ is connected. Meanwhile, while a high potential is supplied to the gate wiring 27, a signal is supplied to the second source wiring 28β in synchronization with the timing when a high potential is supplied to the fourth control wiring 29δ. As a result, the fourth control TFT 25δ connected to the fourth control wiring 29δ and the fourth signal TFT 24δ connected to the fourth control TFT 25δ are driven, and the signal supplied to the second source wiring 28β is supplied to the pixel electrode 26 to which the fourth control TFT 25δ is connected.As described above, it becomes possible to distribute the signal supplied to one first source wiring 28α to the pixel electrode 26 to be connected to the first control TFT 25α connected to the first control wiring 29α, and to the pixel electrode 26 to be connected to the second control TFT 25β connected to the second control wiring 29β. In addition, it becomes possible to distribute the signal supplied to one second source wiring 28β to the pixel electrode 26 to be connected to the third control TFT 25γ connected to the third control wiring 29γ, and to the pixel electrode 26 to be connected to the fourth control TFT 25δ connected to the fourth control wiring 29δ.

[0108] Furthermore, the system includes a first short-circuit wiring 44α that extends along the first direction and is connected to the first source wiring 28α and the second source wiring 28β to short-circuit the first source wiring 28α and the second source wiring 28β; a first lead wiring 45α that is connected to either the first source wiring 28α, the second source wiring 28β, or the first short-circuit wiring 44α; and a driver (second signal supply unit) 12 that is connected to the first lead wiring 45α and supplies a signal to the first lead wiring 45α. In this way, by supplying a signal from the driver 12 to the first lead wiring 45α, a signal can be supplied to the first source wiring 28α and the second source wiring 28β that are short-circuited by the first short-circuit wiring 44α. Since only one first lead wiring 45α needs to be connected to the driver 12, this is preferable for achieving a narrow bezel compared to the case where the first short-circuit wiring 44α is omitted and the first source wiring 28α and the second source wiring 28β are each connected to the driver 12.

[0109] Furthermore, the system includes a control board 14 connected to multiple control wires 29 and supplying signals to each of the control wires 29. The control board 14 supplies high-level potentials to the first control wire 29α, the second control wire 29β, the third control wire 29γ, and the fourth control wire 29δ at different timings. The driver 12 supplies a signal to the first signal TFT 24α in synchronization with the timing when a high-level potential is supplied to the first control wire 29α, a signal to the second signal TFT 24β in synchronization with the timing when a high-level potential is supplied to the second control wire 29β, a signal to the third signal TFT 24γ in synchronization with the timing when a high-level potential is supplied to the third control wire 29γ, and a signal to the fourth signal TFT 24δ in synchronization with the timing when a high-level potential is supplied to the fourth control wire 29δ. When a signal is supplied from the driver 12 to the first lead wire 45α in synchronization with the timing when a high potential is supplied from the control board 14 to the first control wire 29α, the first signal TFT 24α and the first control TFT 25α are both driven, and a signal is supplied to the pixel electrode 26 to which the first control TFT 25α is connected. When a signal is supplied from the driver 12 to the first lead wire 45α in synchronization with the timing when a high potential is supplied from the control board 14 to the second control wire 29β, the second signal TFT 24β and the second control TFT 25β are both driven, and a signal is supplied to the pixel electrode 26 to which the second control TFT 25β is connected. When a signal is supplied from the driver 12 to the first lead wire 45α in synchronization with the timing when a high potential is supplied from the control board 14 to the third control wire 29γ, the third signal TFT 24γ and the third control TFT 25γ are both driven, and a signal is supplied to the pixel electrode 26 to which the third control TFT 25γ is connected. When a high potential is supplied from the control board 14 to the fourth control wiring 29δ, and a signal is supplied from the driver 12 to the first lead wiring 45α in synchronization with this timing, the fourth signal TFT 24δ and the fourth control TFT 25δ are both driven, and a signal is supplied to the pixel electrode 26 to which the fourth control TFT 25δ is connected.

[0110] Furthermore, the first source wiring 28α is sandwiched between the first control wiring 29α and the second control wiring 29β in the first direction, the second source wiring 28β is sandwiched between the third control wiring 29γ and the fourth control wiring 29δ in the first direction, and the multiple source wirings 28 include a third source wiring (third signal wiring) 28γ sandwiched between the second control wiring 29β and the third control wiring 29γ in the first direction, and the multiple first TFTs 24 include a fifth signal TFT (fifth signal switching element) 24ζ which is a first TFT 24 having a first source electrode 24B connected to the third source wiring 28γ, and a third source wiring between the first source electrode 24B connected to the third source wiring 28γ and the fifth signal TFT 24ζ The array includes a sixth signal TFT (sixth signal switching element) 24η, which is a first TFT 24 arranged to sandwich 28γ, and a plurality of second TFTs 25, including a fifth control TFT (fifth control switching element) 25ζ, which is a second TFT 25 having a second source electrode 25B connected to the first drain electrode 24C of the fifth signal TFT 24ζ, and a sixth control TFT (sixth control switching element) 25η, which is a second TFT 25 having a second source electrode 25B connected to the first drain electrode 24C of the sixth signal TFT 24η, where the second gate electrode 25A of the fifth control TFT 25ζ is connected to the second control wiring 29β, and the second gate electrode 25A of the sixth control TFT 25η is connected to the third control wiring 29γ. While a high potential is supplied to the gate wiring 27, a signal is supplied to the third source wiring 28γ in synchronization with the timing when a high potential is supplied to the second control wiring 29β. As a result, the fifth control TFT 25ζ connected to the second control wiring 29β and the fifth signal TFT 24ζ connected to the fifth control TFT 25ζ are driven, and the signal supplied to the third source wiring 28γ is supplied to the pixel electrode 26 to which the fifth control TFT 25ζ is connected. Meanwhile, while a high potential is supplied to the gate wiring 27, a signal is supplied to the third source wiring 28γ in synchronization with the timing when a high potential is supplied to the third control wiring 29γ. As a result, the sixth control TFT 25η connected to the third control wiring 29γ and the sixth signal TFT 24η connected to the sixth control TFT 25η are driven, and the signal supplied to the third source wiring 28γ is supplied to the pixel electrode 26 to which the sixth control TFT 25η is connected.

[0111] Furthermore, the multiple source lines 28 include a fourth source line (fourth signal line) 28δ that has a fourth control line 29δ between it and the second source line 28β in the first direction, the multiple first TFTs 24 include a seventh signal TFT (seventh signal switching element) 24θ which is a first TFT 24 having a first source electrode 24B connected to the fourth source line 28δ, and the multiple second TFTs 25 include a seventh control TFT (seventh control switching element) 25θ which is a second TFT 25 having a second source electrode 25B connected to the first drain electrode 24C of the seventh signal TFT 24θ, and the second gate electrode 25A of the seventh control TFT 25θ is connected to the fourth control line 29δ. While a high potential is supplied to the gate line 27, a signal is supplied to the fourth source line 28δ in synchronization with the timing when a high potential is supplied to the fourth control line 29δ. As a result, the seventh control TFT 25θ connected to the fourth control wiring 29δ and the seventh signal TFT 24θ connected to the fifth control TFT 25ζ are driven, and the signal supplied to the fourth source wiring 28δ is supplied to the pixel electrode 26 to which the seventh control TFT 25θ is connected.

[0112] Furthermore, the multiple pixel electrodes 26 include multiple first pixel electrodes 26α and multiple second pixel electrodes 26β, and the second pixel electrode 26β has a second main body portion 26Aβ and a second connecting wiring portion 26Bβ which is connected to the second main body portion 26Aβ and the second drain electrode 25C and does not intersect with either the control wiring 29 or the source wiring 28, and the multiple first pixel electrodes 26α have a first main body portion 26Aα positioned on the opposite side from the first source wiring 28α side in the first direction with respect to the first control wiring 29α The first connection wiring section 26Bα is connected to the second drain electrode 25C of the first control TFT 25α and intersects with the first control wiring 29α, forming a first pixel electrode 26α1, the first main body section 26Aα is sandwiched between the third source wiring 28γ and the third control wiring 29γ in the first direction, the first connection wiring section 26Bα is connected to the second drain electrode 25C of the third control TFT 25γ and intersects with the third control wiring 29γ, forming a first pixel electrode 26α2, and the first main body section 26Aα is connected to the third control wiring 2 in the first direction The array includes a first pixel electrode 26α3 sandwiched between 9γ and the second source wiring 28β, with the first connection wiring portion 26Bα connected to the second drain electrode 25C of the sixth control TFT 25η and intersecting with the third control wiring 29γ, and a plurality of second pixel electrodes 26β, the array includes a second main body portion 26Aβ sandwiched between the first source wiring 28α and the second control wiring 29β in the first direction, with the second connection wiring portion 26Bβ connected to the second drain electrode 25C of the second control TFT 25β and a second pixel electrode 26β1 The second main body 26Aβ is sandwiched between the second source wiring 28β and the fourth control wiring 29δ in the first direction, and the second connection wiring 26Bβ is connected to the second drain electrode 25C of the fourth control TFT 25δ, forming a second pixel electrode 26β2; and the second main body 26Aβ is sandwiched between the second control wiring 29β and the third source wiring 28γ in the first direction, and the second connection wiring 26Bβ is connected to the second drain electrode 25C of the fifth control TFT 25ζ, forming a second pixel electrode 26β3. The signal supplied to the first source wiring 28α is supplied to the first pixel electrode 26α1 connected to the first control TFT 25α when a high potential is supplied to the first control wiring 29α, and to the second pixel electrode 26β1 connected to the second control TFT 25β when a high potential is supplied to the second control wiring 29β.The signal supplied to the second source wiring 28β is supplied to the first pixel electrode 26α2 connected to the third control TFT 25γ when a high potential is supplied to the third control wiring 29γ, and to the second pixel electrode 26β2 connected to the fourth control TFT 25δ when a high potential is supplied to the fourth control wiring 29δ. The signal supplied to the third source wiring 28γ is supplied to the second pixel electrode 26β3 connected to the fifth control TFT 25ζ when a high potential is supplied to the second control wiring 29β, and to the first pixel electrode 26α3 connected to the sixth control TFT 25η when a high potential is supplied to the third control wiring 29γ.

[0113] Furthermore, the first main body portion 26Aα and the second main body portion 26Aβ have equivalent areas, and the first connecting wiring portion 26Bα and the second connecting wiring portion 26Bβ have equivalent areas. In this way, the areas of the first pixel electrode 26α and the second pixel electrode 26β become equal. This makes it less likely for display inconsistencies to occur.

[0114] Furthermore, the length from the first main body 26Aα to the second drain electrode 25C in the first connection wiring section 26Bα and the length from the second main body 26Aβ to the second drain electrode 25C in the second connection wiring section 26Bβ are made equivalent. For example, even if variations occur in the widths of the first connection wiring section 26Bα and the second connection wiring section 26Bβ due to manufacturing reasons, the aforementioned lengths of the first connection wiring section 26Bα and the second connection wiring section 26Bβ are made equivalent, making it less likely for differences to occur in the area of ​​the first connection wiring section 26Bα and the second connection wiring section 26Bβ. This makes it less likely for display inconsistencies to occur.

[0115] Furthermore, the system includes a driver 12 connected to multiple source wirings 28 and supplying signals to the multiple source wirings 28, wherein the signals supplied by the driver 12 to the first source wiring 28α and the second source wiring 28β are of opposite polarity to the signals supplied by the driver 12 to the third source wiring 28γ. When the first pixel electrode 26α is connected to the first control TFT 25α, the third control TFT 25γ and the sixth control TFT 25η, respectively, and the second pixel electrode 26β is connected to the second control TFT 25β, the fourth control TFT 25δ and the fifth control TFT 25ζ, respectively, when signals of opposite polarity are supplied from the driver 12 to the first source wiring 28α, the second source wiring 28β and the third source wiring 28γ, adjacent pixel electrodes 26 in the first direction are charged to potentials of opposite polarity to each other. Specifically, the second pixel electrode 26β connected to the second control TFT 25β and the second pixel electrode 26β connected to the fifth control TFT 25ζ have opposite polarity, the second pixel electrode 26β connected to the fifth control TFT 25ζ and the first pixel electrode 26α connected to the third control TFT 25γ have opposite polarity, the first pixel electrode 26α connected to the third control TFT 25γ and the first pixel electrode 26α connected to the sixth control TFT 25η have opposite polarity, and the first pixel electrode 26α connected to the sixth control TFT 25η and the second pixel electrode 26β connected to the fourth control TFT 25δ have opposite polarity. This makes streaky display defects less visible.

[0116] Furthermore, the driver 12 supplies signals of the same polarity to the first source wiring 28α, second source wiring 28β, and third source wiring 28γ, respectively, in synchronization with the supply of high-level potential from the control board 14 to the first control wiring 29α, second control wiring 29β, third control wiring 29γ, and fourth control wiring 29δ, respectively. In this way, compared to the case where the polarity of the signal supplied from the driver 12 to each source wiring 28 is reversed each time a high potential is supplied from the control board 14 to each control wiring 29, the power consumption required to supply the signals can be reduced.

[0117] <Embodiment 2> Embodiment 2 will be described with reference to Figures 15 to 23. This Embodiment 2 shows a case where the configuration of the connection wiring section 126B is changed. Note that redundant explanations of the structure, operation, and effects, which are the same as those described in Embodiment 1, will be omitted.

[0118] As shown in Figure 15, the multiple pixel electrodes 126 in this embodiment are all first pixel electrodes 126α, and do not include the second pixel electrode 26β (see Figure 3) described in Embodiment 1. In other words, the connection wiring portions 126B provided on the multiple pixel electrodes 126 are all first connection wiring portions 126Bα, and intersect with the source wiring 128 or control wiring 129. The detailed arrangement and configuration of the first main body portion 126Aα and the first connection wiring portion 126Bα will be described below.

[0119] Hereafter, when distinguishing between multiple first pixel electrodes 126α, the first pixel electrode 126α connected to the first control TFT 125α will have the subscript "5" added to its code, the first pixel electrode 126α connected to the second control TFT 125β will have the subscript "6" added to its code, the first pixel electrode 126α connected to the third control TFT 125γ will have the subscript "7" added to its code, the first pixel electrode 126α connected to the fourth control TFT 125δ will have the subscript "8" added to its code, and the fifth control The first pixel electrode 126α connected to TFT125ζ is denoted by the subscript "9", the first pixel electrode 126α connected to the sixth control TFT125η is denoted by the subscript "10", the first pixel electrode 126α connected to the seventh control TFT125θ is denoted by the subscript "11", and the first pixel electrode 126α connected to the eighth control TFT125ι is denoted by the subscript "12". When referring to them collectively without distinction, no subscript is added to the code.

[0120] In this embodiment, as shown in Figure 15, the arrangement of the first main body portion 126Aα constituting the first pixel electrode 126α differs for each pixel row. Specifically, among the multiple pixel rows arranged along the Y-axis, in the odd-numbered pixel rows counting from the top edge of Figure 15 (for example, the first pixel row R1 and the third pixel row R3 counting from the top edge of Figure 15), the first main body portion 126Aα of the first pixel electrode 126α12 is located in the second pixel column C2, the first main body portion 126Aα of the first pixel electrode 126α5 is located in the third pixel column C3, and the fourth pixel column C4 is The first main body 126Aα of the first pixel electrode 126α6 is located in the fifth pixel row C5, the first main body 126Aα of the first pixel electrode 126α9 is located in the sixth pixel row C6, the first main body 126Aα of the first pixel electrode 126α10 is located in the seventh pixel row C7, and the first main body 126Aα of the first pixel electrode 126α8 is located in the eighth pixel row C8. Thus, in odd-numbered pixel rows, the first main body 126Aα to be connected to the second TFT 125 is located on the right side of Figures 15 to 18.

[0121] On the other hand, in the even-numbered pixel rows counting from the top edge of Figure 15 (for example, the second pixel row R2, the second from the top edge of Figure 15), as shown in Figure 15, the first main body 126Aα of the first pixel electrode 126α5 is located in the first pixel column C1, the first main body 126Aα of the first pixel electrode 126α6 is located in the second pixel column C2, and the first of the first pixel electrode 126α9 is located in the third pixel column C3. The main body 126Aα is located in the fourth pixel row C4, the first main body 126Aα of the first pixel electrode 126α10 is located in the fifth pixel row C5, the first main body 126Aα of the first pixel electrode 126α7 is located in the sixth pixel row C6, and the first main body 126Aα of the first pixel electrode 126α8 is located in the seventh pixel row C7. Thus, in even-numbered pixel rows, the first main body 126Aα to be connected to the second TFT 125 is located on the left side of Figures 15 to 18.

[0122] To arrange the first main body 126Aα as described above, the first connecting wiring section 126Bα constituting the first pixel electrode 126α has different intersecting wirings 128 and 129 for each pixel row, as shown in Figures 16 to 18. Figure 16 is a plan view showing the first pixel row C1 to the fourth pixel row C4. Figure 17 is a plan view showing the third pixel row C3 to the sixth pixel row C6. Figure 18 is a plan view showing the fifth pixel row C5 to the eighth pixel row C8. In the following, the first pixel row R1 will be described as an odd-numbered pixel row, and the second pixel row R2 will be described as an even-numbered pixel row.

[0123] In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α12 intersects with the first control wiring 129α on its way from the drain wiring portion 143 (second drain electrode 125C) of the eighth control TFT 125ι to the first main body portion 126Aα to be connected, as shown in Figure 16. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α5 intersects with the first source wiring 128α on its way from the drain wiring portion 143 of the first control TFT 125α to the first main body portion 126Aα to be connected. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α6 intersects with the second control wiring 129β on its way from the drain wiring portion 143 of the second control TFT 125β to the first main body portion 126Aα to be connected. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α9 intersects with the third source wiring 128γ on its way from the drain wiring portion 143 of the fifth control TFT 125ζ to the first main body portion 126Aα to be connected, as shown in Figure 17. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α10 intersects with the third control wiring 129γ on its way from the drain wiring portion 143 of the sixth control TFT 125η to the first main body portion 126Aα to be connected. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α7 intersects with the second source wiring 128β on its way from the drain wiring portion 143 of the third control TFT 125γ to the first main body portion 126Aα to be connected, as shown in Figure 18. In the first pixel row R1, the first connection wiring portion 126Bα of the first pixel electrode 126α8 intersects with the fourth control wiring 129δ on its way from the drain wiring portion 143 of the fourth control TFT 125δ to the first main body portion 126Aα to which it is connected. Thus, in the first pixel row R1, all of the first connection wiring portions 126Bα extend from the drain wiring portion 143 to the right in Figures 15 to 18.

[0124] In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α5 intersects with the first control wiring 129α on its way from the drain wiring portion 143 of the first control TFT 125α to the first main body portion 126Aα to be connected, as shown in Figure 16. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α6 intersects with the first source wiring 128α on its way from the drain wiring portion 143 of the second control TFT 125β to the first main body portion 126Aα to be connected. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α9 intersects with the second control wiring 129β on its way from the drain wiring portion 143 of the fifth control TFT 125ζ to the first main body portion 126Aα to be connected. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α10 intersects with the third source wiring 128γ on its way from the drain wiring portion 143 of the sixth control TFT 125η to the first main body portion 126Aα to be connected, as shown in Figure 17. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α7 intersects with the third control wiring 129γ on its way from the drain wiring portion 143 of the third control TFT 125γ to the first main body portion 126Aα to be connected. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α8 intersects with the second source wiring 128β on its way from the drain wiring portion 143 of the fourth control TFT 125δ to the first main body portion 126Aα to be connected, as shown in Figure 18. In the second pixel row R2, the first connection wiring portion 126Bα of the first pixel electrode 126α11 intersects with the fourth control wiring 129δ on its way from the drain wiring portion 143 of the seventh control TFT 125θ to the first main body portion 126Aα to which it is connected. Thus, in the second pixel row R2, all of the first connection wiring portions 126Bα extend from the drain wiring portion 143 to the left in Figures 15 to 18.

[0125] This embodiment has the structure described above, and its operation will now be explained mainly using Figures 19 to 23. Figures 20 and 22 show the signal waveforms of the gate wiring 127, source wiring 128α to 128ζ, and control wiring 129α to 129δ. Figure 22 shows the waveforms of the signals output after one frame display period, following the output of the signals shown in Figure 20. Figures 20 and 22 show the scan signal G1, the control signals SWA to SWD, and the image signals S0 to S2, similar to Figures 11 and 13. On the other hand, Figures 21 and 23 schematically illustrate the first pixel electrodes 126α5 to 126α12, the gate wiring 127, the source wiring 128α to 128ζ, and the control wiring 129α to 129δ, and indicate the positive and negative polarity of each first pixel electrode 126α5 to 126α12 with the signs "+" and "-".

[0126] As shown in Figures 19 and 20, when a high potential of scanning signals G1 and G2 is supplied from the gate drive circuit 15 to a gate wiring 127, the control board 14 supplies high potentials of control signals SWA and SWD to each control wiring 129α to 129δ at different timings in synchronization with this supply. Simultaneously, the driver 12 supplies image signals S0 and S2 to each source wiring 128α to 128ζ, respectively, in synchronization with the timing at which control signals SWA and SWD are supplied to each control wiring 129α to 129δ. The relationship between the timing at which high potentials are supplied as scanning signals G1 and G2 and the timing at which high potentials are supplied as control signals SWA and SWD is as described in Embodiment 1. Furthermore, the relationship between the timing at which high potentials are supplied as control signals SWA and SWD and the timing at which image signals S0 and S2 are supplied is as described in Embodiment 1. Furthermore, regarding the polarity of image signals S0 to S2, as explained in Embodiment 1, image signal S1 and image signals S0 and S2 have opposite polarities.

[0127] Specifically, as shown in Figures 19 and 20, multiple first TFTs 124 belonging to the first pixel row R1 are driven collectively when a high potential of the scan signal G1 is supplied to the connected gate wiring 127. While the high potential of the scan signal G1 is supplied to the gate wiring 127, high potentials of the control signals SWA~SWD are supplied to the first control wiring 129α, second control wiring 129β, third control wiring 129γ, and fourth control wiring 129δ in that order. Meanwhile, while the high potential of the scan signal G1 is supplied to the gate wiring 127, image signals S0~S2 are supplied to each source wiring 128α~128ζ in synchronization with the timing when the control signals SWA~SWD become high. The operation of each control TFT 125α~125ι is as described in Embodiment 1. In Figure 20, a positive polarity image signal S1 and negative polarity image signals S0 and S2 are supplied to each source wiring 128α to 128ζ.

[0128] Each first pixel electrode 126α belonging to the first pixel row R1 is charged to the polarity shown in Figure 21 when the TFTs 124 and 125 are driven based on the scan signal G1 and control signals SWA~SWD. Specifically, the first pixel electrode 126α12 belonging to the second pixel row C2 is charged to a negative potential related to the image signal S0, the first pixel electrode 126α5 belonging to the third pixel row C3 is charged to a positive potential related to the image signal S1, the first pixel electrode 126α6 belonging to the fourth pixel row C4 is charged to a positive potential related to the image signal S1, the first pixel electrode 126α9 belonging to the fifth pixel row C5 is charged to a negative potential related to the image signal S2, the first pixel electrode 126α10 belonging to the sixth pixel row C6 is charged to a negative potential related to the image signal S2, the first pixel electrode 126α7 belonging to the seventh pixel row C7 is charged to a positive potential related to the image signal S1, and the first pixel electrode 126α8 belonging to the eighth pixel row C8 is charged to a positive potential related to the image signal S1. Thus, in the first pixel row R1, pairs of first pixel electrodes 126α, which are arranged consecutively in the X-axis direction, have potentials of the same polarity. Specifically, in the first pixel row R1, the (4n-3)th pixel column and the (4n-2)th pixel column, counting from the left end of Figure 21, have a negative potential, and the (4n-1)th pixel column and the 4nth pixel column have a positive potential (n: natural number).

[0129] On the other hand, each first pixel electrode 126α belonging to the second pixel row R2 is charged to the polarity shown in Figure 21 when the TFTs 124 and 125 are driven based on the scanning signal G1 and the control signals SWA~SWD. Specifically, the first pixel electrode 126α5 belonging to the first pixel row C1 is charged to a positive potential related to the image signal S1, the first pixel electrode 126α6 belonging to the second pixel row C2 is charged to a positive potential related to the image signal S1, the first pixel electrode 126α9 belonging to the third pixel row C3 is charged to a negative potential related to the image signal S2, the first pixel electrode 126α10 belonging to the fourth pixel row C4 is charged to a negative potential related to the image signal S2, the first pixel electrode 126α7 belonging to the fifth pixel row C5 is charged to a positive potential related to the image signal S1, the first pixel electrode 126α8 belonging to the sixth pixel row C6 is charged to a positive potential related to the image signal S1, and the first pixel electrode 126α11 belonging to the seventh pixel row C7 is charged to a negative potential related to the image signal S2. Thus, in the second pixel row R2, just like in the first pixel row R1, pairs of first pixel electrodes 126α arranged consecutively in the X-axis direction have the same polarity. Specifically, in the second pixel row R2, the (4n-3)th pixel column and the (4n-2)th pixel column, counting from the left end of Figure 21, have a positive polarity, while the (4n-1)th pixel column and the 4nth pixel column have a negative polarity (n: natural number). In other words, in the first pixel row R1 and the second pixel row R2, the first pixel electrodes 126α belonging to the same pixel column have opposite polarity.

[0130] After each signal shown in Figure 20 is output and one frame has been displayed, each signal shown in Figure 22 is output. Of the signals shown in Figure 22, the scan signal G1 and control signals SWA~SWD are the same as those shown in Figure 20, but the image signals S0~S2 have the opposite polarity to those shown in Figure 20. Specifically, the first source wiring 128α and the second source wiring 128β are supplied with the negative polarity image signal S1, the third source wiring 128γ and the fourth source wiring 128δ are supplied with the positive polarity image signal S2, and the fifth source wiring 128ζ is supplied with the positive polarity image signal S0.

[0131] When each signal shown in Figure 22 is output, as shown in Figure 23, in the first pixel row R1, the first pixel electrode 126α12 belonging to the second pixel column C2 is charged to a positive potential related to the image signal S0, the first pixel electrode 126α5 belonging to the third pixel column C3 is charged to a negative potential related to the image signal S1, the first pixel electrode 126α6 belonging to the fourth pixel column C4 is charged to a negative potential related to the image signal S1, the first pixel electrode 126α9 belonging to the fifth pixel column C5 is charged to a positive potential related to the image signal S2, the first pixel electrode 126α10 belonging to the sixth pixel column C6 is charged to a positive potential related to the image signal S2, the first pixel electrode 126α7 belonging to the seventh pixel column C7 is charged to a negative potential related to the image signal S1, and the first pixel electrode 126α8 belonging to the eighth pixel column C8 is charged to a negative potential related to the image signal S1. Thus, the polarity is reversed compared to the pixel electrodes 126α5 to 126α12 shown in Figure 21. Specifically, in the first pixel row R1, the (4n-3)th and (4n-2)th pixel rows, counting from the left edge of Figure 23, have a positive potential, while the (4n-1)th and 4nth pixel rows have a negative potential (n: natural number).

[0132] Meanwhile, in the second pixel row R2, the first pixel electrode 126α5 belonging to the first pixel column C1 is charged to a negative potential related to the image signal S1, the first pixel electrode 126α6 belonging to the second pixel column C2 is charged to a negative potential related to the image signal S1, the first pixel electrode 126α9 belonging to the third pixel column C3 is charged to a positive potential related to the image signal S2, the first pixel electrode 126α10 belonging to the fourth pixel column C4 is charged to a positive potential related to the image signal S2, the first pixel electrode 126α7 belonging to the fifth pixel column C5 is charged to a negative potential related to the image signal S1, the first pixel electrode 126α8 belonging to the sixth pixel column C6 is charged to a negative potential related to the image signal S1, and the first pixel electrode 126α11 belonging to the seventh pixel column C7 is charged to a positive potential related to the image signal S2. Thus, the polarity is reversed from that of the pixel electrodes 126α5 to 126α12 shown in Figure 21. Specifically, in the second pixel row R2, the (4n-3)th and (4n-2)th pixel columns, counting from the left end of Figure 23, have a negative potential, while the (4n-1)th and 4nth pixel columns have a positive potential (n: natural number). In other words, the first pixel electrodes 126α belonging to the same pixel column in the first pixel row R1 and the second pixel row R2 have opposite polarities. Therefore, in this embodiment, when two first pixel electrodes 126α that are adjacent in the X-axis direction and have the same polarity are considered as one pair, adjacent pairs in the X-axis and Y-axis directions have opposite polarities, resulting in a staggered arrangement.

[0133] As described above, according to this embodiment, the plurality of pixel electrodes 126 include a plurality of first pixel electrodes 126α, and the plurality of first pixel electrodes 126α include a first main body portion 126Aα sandwiched between the first source wiring 128α and the second control wiring 129β in the first direction, and a first connection wiring portion 126Bα connected to the second drain electrode 125C of the first control TFT 125α and intersecting with the first source wiring 128α, and the first main body portion 126Aα in the first direction The first pixel electrode 126α6 is sandwiched between the second control wiring 129β and the third source wiring 128γ, with the first connection wiring section 126Bα connected to the second drain electrode 125C of the second control TFT 125β and intersecting with the second control wiring 129β, and the first main body section 126Aα is sandwiched between the third source wiring 128γ and the third control wiring 129γ in the first direction, with the first connection wiring section 126Bα connected to the second drain electrode 125C of the fifth control TFT 125ζ and the third A first pixel electrode 126α9 intersects with the source wiring 128γ, and a first main body 126Aα is sandwiched between the third control wiring 129γ and the second source wiring 128β in the first direction, and a first connection wiring section 126Bα is connected to the second drain electrode 125C of the sixth control TFT 125η and intersects with the third control wiring 129γ, and a first main body 126Aα is sandwiched between the second source wiring 128β and the fourth control wiring 129δ in the first direction, and the first connection The first pixel electrode 126α7 is connected to the second drain electrode 125C of the third control TFT 125γ and intersects with the second source wiring 128β, and the first main body 126Aα is located on the opposite side of the second source wiring 128β side in the first direction with respect to the fourth control wiring 129δ, and the first connecting wiring 126Bα is connected to the second drain electrode 125C of the fourth control TFT 125δ and intersects with the fourth control wiring 129δ, and includes a first pixel electrode 126α8. The signal supplied to the first source wiring 128α is supplied to the first pixel electrode 126α5 connected to the first control TFT 125α when the signal is high potential to the first control wiring 129α, and is supplied to the first pixel electrode 126α6 connected to the second control TFT 125β when the high potential is supplied to the second control wiring 129β.The signal supplied to the second source wiring 128β is supplied to the first pixel electrode 126α7 connected to the third control TFT 125γ when a high potential is supplied to the third control wiring 129γ, and to the first pixel electrode 126α8 connected to the fourth control TFT 125δ when a high potential is supplied to the fourth control wiring 129δ. The signal supplied to the third source wiring 128γ is supplied to the first pixel electrode 126α9 connected to the fifth control TFT 125ζ when a high potential is supplied to the second control wiring 129β, and to the first pixel electrode 126α10 connected to the sixth control TFT 125η when a high potential is supplied to the third control wiring 129γ.

[0134] The system includes a driver 12 connected to multiple source lines 128 and supplying signals to the multiple source lines 128, wherein the signals supplied by the driver 12 to the first source line 128α and the second source line 128β and the signals supplied by the driver 12 to the third source line 128γ are of opposite polarity. When the first pixel electrode 126α is connected to the first control TFT 125α, the second control TFT 125β, the third control TFT 125γ, the fourth control TFT 125δ, the fifth control TFT 125ζ, and the sixth control TFT 125η, respectively, when signals of opposite polarity are supplied from the driver 12 to the first source line 128α, the second source line 128β, and the third source line 128γ, two pixel electrodes 126 that are consecutively aligned in the first direction will have potentials of the same polarity. More specifically, the first pixel electrode 126α connected to the first control TFT 125α and the first pixel electrode 126α connected to the second control TFT 125β have the same polarity, the first pixel electrode 126α connected to the second control TFT 125β and the first pixel electrode 126α connected to the fifth control TFT 125ζ have opposite polarity, the first pixel electrode 126α connected to the fifth control TFT 125ζ and the first pixel electrode 126α connected to the sixth control TFT 125η have the same polarity, the first pixel electrode 126α connected to the sixth control TFT 125η and the first pixel electrode 126α connected to the third control TFT 125γ have opposite polarity, and the first pixel electrode 126α connected to the third control TFT 125γ and the first pixel electrode 126α connected to the fourth control TFT 125δ have the same polarity.

[0135] <Embodiment 3> Embodiment 3 will be described with reference to Figure 24 or Figure 25. This Embodiment 3 shows a case where the configurations of the first TFT224 and the second TFT225 are changed from those of Embodiment 1 described above. Note that redundant explanations of the same structure, operation, and effects as in Embodiment 1 will be omitted.

[0136] As shown in Figures 24 and 25, the first TFT 224 in this embodiment is connected to the control wiring 229. In contrast, the second TFT 225 is connected to the gate wiring 227. Specifically, the first gate electrode 224A constituting the first TFT 224 is connected to the control wiring 229. Therefore, the first TFT 224 is driven based on a control signal supplied from the control board 14 to the control wiring 229. The second gate electrode 225A constituting the second TFT 225 is connected to the gate wiring 227. Therefore, the second TFT 225 is driven based on a scanning signal supplied from the gate drive circuit 15 to the gate wiring 227.

[0137] As shown in Figure 24, the first TFT 224 is positioned closer to the control wiring 229 than to the source wiring 228 in the X-axis direction. Accordingly, the first source electrode 224B constituting the first TFT 224 is connected to the source wiring 228 via the source wiring section 50. The source wiring section 50 is positioned between the main body section 226A and the drain wiring section 243 in the Y-axis direction. The source wiring section 50 extends along the X-axis direction, with one end connected to the first source electrode 224B and the other end connected to the source wiring 228. The source wiring section 50 is made of a part of the second metal film and is directly connected to the first source electrode 224B and the source wiring 228. The second TFT 225 is positioned closer to the source wiring 228 than to the control wiring 229 in the X-axis direction.

[0138] In this configuration, as shown in Figure 25, while the gate wiring 227 is supplied with a high potential of the scanning signal G1, the control wirings 229α to 229δ are supplied with high potentials of the control signals SWA to SWD in a predetermined order, and the source wirings 228α to 228ζ are supplied with image signals S0 to S2 in synchronization with the timing when the control signals SWA to SWD reach a high potential. Of the multiple first TFTs 224, the one to which the control signals SWA to SWD, which reach a high potential, are supplied to the first gate electrode 224A is selectively driven. The image signals S0 to S2 supplied to each source wiring 228α to 228ζ are supplied from the first drain electrode 224C of the driven first TFT 224 to the second source electrode 225B of the second TFT 225. In contrast, the multiple second TFTs 225 connected to the gate wiring 227 are driven collectively. Therefore, among the multiple second TFT225s, the pixel electrode 226 connected to the second TFT225 to which image signals S0 to S2 are supplied from the driven first TFT224 is selectively charged to the potential related to the image signals S0 to S2.

[0139] As described above, according to this embodiment, the first gate electrode 224A is connected to the control wiring 229, and the second gate electrode 225A is connected to the gate wiring 227. When a signal is supplied to the gate wiring 227, the second TFT 225 having the second gate electrode 225A connected to the gate wiring 227 is driven. When a signal is supplied to the control wiring 229, the first TFT 224 having the first gate electrode 224A connected to the control wiring 229 is driven.

[0140] <Other Embodiments> The technology disclosed herein is not limited to the embodiments described above in the description and drawings, but also includes, for example, the following embodiments.

[0141] (1) The specific planar arrangement of the pixel electrodes 26, 126, and 226 in the main body parts 26A and 226A can be changed as appropriate, in addition to the arrangement shown in the figure.

[0142] (2) The specific planar shape (wiring path) of the connection wiring sections 26B, 126B of the pixel electrodes 26, 126, 226 can be changed as appropriate, in addition to what is shown. For example, in the configurations described in Embodiments 1 and 3, each connection wiring section 26B of multiple pixel electrodes 26, 226 belonging to a certain pixel row may all be connected to the second TFTs 25, 225 belonging to the same pixel row. Also, in the configuration described in Embodiment 2, a part of each connection wiring section 126B of multiple pixel electrodes 126 belonging to a certain pixel row may be connected to the second TFT 125 belonging to a different pixel row.

[0143] (3) The specific planar shape of the main body portions 26A and 226A of the pixel electrodes 26, 126 and 226 can be changed from those shown, for example, they may be a vertically elongated shape without bends, or they may be a horizontally elongated shape. In addition, the main body portions 26A and 226A may be a vertically elongated or horizontally elongated shape with multiple bends.

[0144] (4) The specific planar arrangement of the first TFTs 24, 124, and 224 can be changed as appropriate in addition to the arrangement shown. For example, in the configurations described in Embodiments 1 and 2, the first TFTs 24 and 124 may be positioned closer to the control wirings 29 and 129 than to the source wirings 28 and 128 in the X-axis direction. Also, in the configurations described in Embodiments 1 and 2, the first TFTs 24 and 124 may be positioned at an intermediate position between the source wirings 28 and 128 and the control wirings 29 and 129 in the X-axis direction. Also, in the configuration described in Embodiment 3, the first TFT 224 may be positioned closer to the source wiring 228 than to the control wiring 229 in the X-axis direction. Also, in the configuration described in Embodiment 3, the first TFT 224 may be positioned at an intermediate position between the control wiring 229 and the source wiring 228 in the X-axis direction.

[0145] (5) The specific planar arrangement of the second TFTs 25, 125, and 225 can be changed as appropriate in addition to the arrangement shown. For example, in the configurations described in Embodiments 1 and 2, the second TFTs 25 and 125 may be positioned closer to the source wiring 28 and 128 than to the control wiring 29 and 129 in the X-axis direction. Also, in the configurations described in Embodiments 1 and 2, the second TFTs 25 and 125 may be positioned at an intermediate position between the source wiring 28 and 128 and the control wiring 29 and 129 in the X-axis direction. Also, in the configuration described in Embodiment 3, the second TFT 225 may be positioned closer to the control wiring 229 than to the source wiring 228 in the X-axis direction. Also, in the configuration described in Embodiment 3, the second TFT 225 may be positioned at an intermediate position between the control wiring 229 and the source wiring 228 in the X-axis direction.

[0146] (6) The number of control wires 29, 129, and 229 installed may be an even number or an odd number.

[0147] (7) The ratio of the number of source wires 28, 128, 228 to the number of control wires 29, 129, 229 can be changed as appropriate, in addition to the figures shown.

[0148] (8) The first lead wire 45α may be connected to the second source wires 28β and 128β. Similarly, the second lead wire 45β may be connected to the third source wires 28γ and 128γ.

[0149] (9) The lead wire 45 may be connected to the short-circuit wire 44.

[0150] (10) The source wiring 28, 128, 228 and the control wiring 29, 129, 229 may be configured to extend straight along the Y-axis. In that case, the main body portions 26A, 226A of the pixel electrodes 26, 126, 226 and the color filter 31 may be configured to extend straight along the Y-axis so as to be parallel to the side edges of the source wiring 28, 128, 228 and the control wiring 29, 129, 229.

[0151] (11) The short-circuit wiring 44 may be provided to short-circuit three or more source wirings 28, 128, 228.

[0152] (12) Multiple control lines 29, 129, 229 may be supplied from the control board 14 with three or fewer types or five or more types of control signals with different timings.

[0153] (13) The short-circuit wiring 44 can be omitted. In that case, individual lead wires 45 are connected to the multiple source wires 28, 128, and 228, and the image signal from the driver 12 is supplied individually to each source wire 28, 128, and 228 via each lead wire 45.

[0154] (14) The driver 12 may supply control signals to each control wire 29, 129, 229. In this case, the driver 12 constitutes a "first signal supply unit" in addition to the "second signal supply unit".

[0155] (15) The planar arrangement and number of spacers 40 can be changed as appropriate, in addition to what is shown in the diagram.

[0156] (16) The driver 12 may be mounted on the flexible substrate 13 using COF (Chip On Film). Alternatively, the gate driver may be mounted on the array substrate 21 instead of the gate drive circuit 15.

[0157] (17) The semiconductor film material constituting each semiconductor section 24D, 25D may be amorphous silicon material, polycrystalline polysilicon material, or the like.

[0158] (18) The configuration of each TFT 24, 25, 124, 125, 224, 225 may be a top gate type, double gate type, etc., in addition to the bottom gate type shown in the drawing.

[0159] (19) The pixel electrodes 26, 126, and 226 may be made of a first transparent electrode film, and the common electrode 30 may be made of a second transparent electrode film. In that case, it is preferable to form a slit in the common electrode 30 for orientation control.

[0160] (20) The planar shape of the liquid crystal panel 11 may be a vertically elongated rectangle, square, circle, semicircle, oval, ellipse, trapezoid, etc.

[0161] (21) The liquid crystal panel 11 may be of a type other than transmissive, such as reflective or semi-transmissive. If the liquid crystal panel 11 is of a reflective type, the backlight device can be omitted.

[0162] (22) The display mode of the LCD panel 11 may be MVA (Multi-domain Vertical Alignment) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, etc.

[0163] (23) The display device may be something other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an electronic paper display. In the case of an electronic paper display using a microcapsule electrophoresis method, the common electrode 30 is formed on the opposing substrate 20 side, and the pixel electrodes 26 formed on the array substrate 21 may be made of not only transparent electrode material but also highly reflective metallic materials such as platinum, silver, animium, and nickel. Furthermore, as a substance whose optical properties change with the application of an electric field, a microcapsule layer is held between the pixel electrode 26 and the common electrode 30, rather than the liquid crystal layer 22, and the first alignment layer 34 and the second alignment layer 39 are not formed. Here, the microcapsule layer contains a large number of microcapsules, and each microcapsule is made of transparent resin with a diameter of several tens to several hundreds of μm. Inside the microcapsules are positively charged white particles and negatively charged black particles dispersed in a transparent dispersion medium. The display can be achieved by applying a positive or negative voltage to the microcapsule layer and causing the white and black particles inside the microcapsules to undergo electrophoresis. [Explanation of Symbols]

[0164] 10…Liquid crystal display device (display device), 12…Driver (second signal supply unit), 14…Control board (first signal supply unit), 24,124,224…First TFT (first switching element), 24α…First signal TFT (first signal switching element), 24β…Second signal TFT (second signal switching element), 24γ…Third signal TFT (third signal switching element), 24δ…Fourth signal TFT (fourth signal switching element), 24ζ…Fifth signal TFT (fifth signal switching element), 24η…Sixth signal TFT (sixth signal switching element), 24θ…Seventh signal TFT T (7th signal switching element), 24A, 224A... 1st gate electrode (1st electrode), 24B, 224B... 1st source electrode (2nd electrode), 24C, 124C, 224C... 1st drain electrode (3rd electrode), 24D... 1st semiconductor section, 25, 125, 225... 2nd TFT (2nd switching element), 25α, 125α... 1st control TFT (1st control switching element), 25β, 125β... 2nd control TFT (2nd control switching element), 25γ, 125γ... 3rd control TFT (3rd control switching element), 25δ, 125δ... 4th control TFT (4th control switch) Pixel electrodes, 25ζ, 125ζ…5th control TFT (5th control switching element), 25η, 125η…6th control TFT (6th control switching element), 25θ, 125θ…7th control TFT (7th control switching element), 25A, 225A…2nd gate electrode (4th electrode), 25B, 225B…2nd source electrode (5th electrode), 25C, 125C…2nd drain electrode (6th electrode), 25D…2nd semiconductor section, 26, 126, 226…Pixel electrodes, 26α, 26α1, 26α2, 26α3, 126α5, 126α6, 126α7, 126α8, 126α9, 126α 10…First pixel electrode, 26Aα,126Aα…First main body, 26Bα,126Bα…First connection wiring section, 26β,26β1,26β2,26β3…Second pixel electrode, 26Aβ…Second main body, 26Bβ…Second connection wiring section, 27,127,227…Gate wiring (scanning wiring), 28,128,228…Source wiring (signal wiring), 28α,128α…First source wiring (first signal wiring), 28β,128β…Second source wiring (second signal wiring), 28γ,128γ…Third source wiring (third signal wiring), 28δ,128δ…Fourth source wiring (fourth signal wiring), 29,129,229... control wiring, 29α, 129α... first control wiring, 29β, 129β... second control wiring, 29γ, 129γ... third control wiring, 29δ, 129δ... fourth control wiring, 44α... first short circuit wiring, 45α... first lead wiring,

Claims

1. Scanning wiring extending along the first direction, A signal wiring extending along a second direction intersecting the first direction and intersecting the scanning wiring, Control wiring extending along the second direction, spaced apart from the signal wiring, and intersecting the scanning wiring, A plurality of pixel electrodes arranged in a matrix in the first and second directions, First switching element, A second switching element is provided, The first switching element includes a first electrode connected to one of the scanning wiring and the control wiring, a second electrode connected to the signal wiring, a third electrode, and a first semiconductor portion connected to the second electrode and the third electrode and arranged superimposed on the first electrode. The second switching element includes a fourth electrode connected to the other of the scanning wiring and the control wiring, a fifth electrode connected to the third electrode, a sixth electrode connected to the pixel electrode, and a second semiconductor portion connected to the fifth electrode and the sixth electrode and arranged superimposed on the fourth electrode. The plurality of pixel electrodes include a first pixel electrode, The first pixel electrode has a first main body and a first connecting wiring portion connected to the first main body and the sixth electrode. The first connection wiring section is a display device that intersects with the control wiring or the signal wiring.

2. The display device according to claim 1, wherein the first main body is arranged between the first connection wiring portion and the second switching element to which the first connection wiring portion is connected, with the control wiring or the signal wiring in between.

3. The first electrode is connected to the scanning wiring, The display device according to claim 1 or claim 2, wherein the fourth electrode is connected to the control wiring.

4. The display device according to claim 3, wherein the second switching element is positioned closer to the control wiring than to the signal wiring.

5. The display device according to claim 3, wherein the first switching element is positioned closer to the signal wiring than to the control wiring.

6. Multiple control wires are arranged at intervals in the first direction. The plurality of control wirings include a first control wiring and a second control wiring, Multiple signal lines are arranged at intervals in the first direction. The multiple signal lines include a first signal line. Multiple second switching elements are arranged at intervals in the first direction. The plurality of second switching elements include a first control switching element which is a second switching element having a fourth electrode connected to the first control wiring, and a second control switching element which is a second switching element having a fourth electrode connected to the second control wiring, Multiple first switching elements are arranged at positions spaced apart in the first direction. The plurality of the first switching elements include: A first signal switching element having a second electrode connected to the first signal wiring and a third electrode connected to the fifth electrode of the first control switching element, The display device according to claim 3, comprising a second signal switching element which is a first switching element having a second electrode connected to the first signal wiring and a third electrode connected to the fifth electrode of the second control switching element.

7. It includes a first signal supply unit that is connected to a plurality of the control wirings and supplies signals to the plurality of the control wirings, The display device according to claim 6, wherein the first signal supply unit supplies a high-level potential to the first control wiring and the second control wiring at different timings.

8. The plurality of control wirings include a third control wiring and a fourth control wiring, The multiple signal lines include a second signal line. The plurality of second switching elements include a third control switching element which is the second switching element having the fourth electrode connected to the third control wiring, and a fourth control switching element which is the second switching element having the fourth electrode connected to the fourth control wiring, The plurality of first switching elements include a third signal switching element which is a first switching element having a second electrode connected to the second signal wiring and a third electrode connected to the fifth electrode of the third control switching element, The display device according to claim 6, further comprising a fourth signal switching element which is a first switching element having a second electrode connected to the second signal wiring and a third electrode connected to the fifth electrode of the fourth control switching element.

9. A first short-circuit wiring extending along the first direction and connected to the first signal wiring and the second signal wiring, which short-circuits the first signal wiring and the second signal wiring, A first lead wire connected to either the first signal wire, the second signal wire, or the first short circuit wire, The display device according to claim 8, further comprising: a second signal supply unit connected to the first lead wiring and supplying a signal to the first lead wiring.

10. It includes a first signal supply unit that is connected to a plurality of control wirings and supplies signals to each of the plurality of control wirings, The first signal supply unit supplies high-level potentials to the first control wiring, the second control wiring, the third control wiring, and the fourth control wiring at different timings. The display device according to claim 9, wherein the second signal supply unit supplies a signal to the first signal switching element in synchronization with the timing at which a high level potential is supplied to the first control wiring, supplies a signal to the second signal switching element in synchronization with the timing at which a high level potential is supplied to the second control wiring, supplies a signal to the third signal switching element in synchronization with the timing at which a high level potential is supplied to the third control wiring, and supplies a signal to the fourth signal switching element in synchronization with the timing at which a high level potential is supplied to the fourth control wiring.

11. The first signal wiring is sandwiched between the first control wiring and the second control wiring in the first direction. The second signal wiring is sandwiched between the third control wiring and the fourth control wiring in the first direction. The plurality of signal wirings include a third signal wiring that is sandwiched between the second control wiring and the third control wiring in the first direction. The plurality of first switching elements include a fifth signal switching element which is a first switching element having a second electrode connected to the third signal wiring, and a sixth signal switching element which is a first switching element having a second electrode connected to the third signal wiring and arranged with the third signal wiring in between it and the fifth signal switching element. The plurality of second switching elements include a fifth control switching element which is a second switching element having a fifth electrode connected to the third electrode of the fifth signal switching element, and a sixth control switching element which is a second switching element having a fifth electrode connected to the third electrode of the sixth signal switching element, The fifth control switching element has the fourth electrode connected to the second control wiring, The display device according to claim 8, wherein the sixth control switching element is connected to the fourth electrode and the third control wiring.

12. The plurality of signal wirings include a fourth signal wiring that, in the first direction, has the fourth control wiring sandwiched between it and the second signal wiring. The plurality of first switching elements include a seventh signal switching element which is a first switching element having a second electrode connected to the fourth signal wiring, The plurality of second switching elements include a seventh control switching element which is a second switching element having a fifth electrode connected to the third electrode of the seventh signal switching element. The display device according to claim 11, wherein the seventh control switching element is connected to the fourth electrode and the fourth control wiring.

13. The plurality of pixel electrodes include a plurality of first pixel electrodes and a plurality of second pixel electrodes. The second pixel electrode has a second main body and a second connection wiring portion that is connected to the second main body and the sixth electrode and does not intersect with either the control wiring or the signal wiring. Multiple of the first pixel electrodes include: The first main body is located on the opposite side of the first signal wiring side with respect to the first control wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the first control switching element and intersects with the first pixel electrode, The first main body is sandwiched between the third signal wiring and the third control wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the third control switching element and intersects with the first pixel electrode of the third control wiring, The first main body is sandwiched between the third control wiring and the second signal wiring in a first direction, and the first connection wiring portion is connected to the sixth electrode of the sixth control switching element and includes the first pixel electrode that intersects with the third control wiring, Multiple of the above-mentioned second pixel electrodes are: The second main body is sandwiched between the first signal wiring and the second control wiring in the first direction, and the second connection wiring is connected to the second pixel electrode which is connected to the sixth electrode of the second control switching element, The second main body is sandwiched between the second signal wiring and the fourth control wiring in the first direction, and the second connection wiring portion is connected to the second pixel electrode which is connected to the sixth electrode of the fourth control switching element, The display device according to claim 11, wherein the second main body is sandwiched between the second control wiring and the third signal wiring in a first direction, and the second pixel electrode is connected to the sixth electrode of the fifth control switching element via a second connection wiring portion.

14. The first main body and the second main body have the same area. The display device according to claim 13, wherein the first connection wiring section and the second connection wiring section have the same area.

15. The display device according to claim 13, wherein the length from the first main body to the sixth electrode in the first connection wiring section is equal to the length from the second main body to the sixth electrode in the second connection wiring section.

16. The plurality of pixel electrodes include a plurality of first pixel electrodes, Multiple of the first pixel electrodes include: The first main body is sandwiched between the first signal wiring and the second control wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the first control switching element and intersects with the first pixel electrode, The first main body is sandwiched between the second control wiring and the third signal wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the second control switching element and intersects with the first pixel electrode, The first main body is sandwiched between the third signal wiring and the third control wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the fifth control switching element and intersects with the third signal wiring of the first pixel electrode, The first main body is sandwiched between the third control wiring and the second signal wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the sixth control switching element and intersects with the third control wiring and the first pixel electrode, The first main body is sandwiched between the second signal wiring and the fourth control wiring in the first direction, and the first connection wiring portion is connected to the sixth electrode of the third control switching element and intersects with the second signal wiring of the first pixel electrode, The display device according to claim 11, wherein the first main body is located on the opposite side of the second signal wiring side with respect to the fourth control wiring in a first direction, and the first connection wiring portion is connected to the sixth electrode of the fourth control switching element and includes the first pixel electrode that intersects with the fourth control wiring.

17. It includes a second signal supply unit that is connected to a plurality of the signal wirings and supplies signals to the plurality of the signal wirings, The display device according to claim 13, wherein the signals supplied by the second signal supply unit to the first signal wiring and the second signal wiring and the signals supplied by the second signal supply unit to the third signal wiring are of opposite polarity.

18. It includes a first signal supply unit that is connected to a plurality of the control wirings and supplies signals to the plurality of the control wirings, The display device according to claim 17, wherein the second signal supply unit supplies signals of the same polarity to the first signal wiring, the second signal wiring, the third control wiring, and the third signal wiring, respectively, in synchronization with the supply of a high-level potential from the first signal supply unit to the first control wiring, the second control wiring, the third control wiring, and the fourth control wiring, respectively.

19. The first electrode is connected to the control wiring, The display device according to claim 1 or 2, wherein the fourth electrode is connected to the scanning wiring.

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