Image forming apparatus that generates developing voltage

Abstract

To improve the circuit configuration for generating the AC voltage component of the development voltage. [Solution] The image forming apparatus includes a voltage generation circuit that generates a developing voltage applied to a developer that develops an electrostatic latent image carried by an image carrier. The voltage generation circuit includes an H-bridge circuit consisting of two switches connected to the first terminal and two switches connected to the second terminal of the primary side circuit of a transformer, a power supply connected to two signal paths of the H-bridge circuit, and a drive circuit that outputs a first drive signal to control the on / off state of one signal path and a second drive signal to control the on / off state of the other signal path. An AC voltage component having an amplitude dependent on the duty cycle of the time over which positive and negative voltages are applied to the primary side circuit is generated in the secondary side circuit of the transformer. The voltage generation circuit outputs the developing voltage, which is superimposed with the AC voltage component generated in the secondary side circuit, to the developer.

Description

[Technical Field]

[0001] This disclosure relates to an image forming apparatus for generating a developing voltage. [Background technology]

[0002] Conventionally, electrophotographic image forming apparatuses are known that form an electrostatic latent image on the surface of an image carrier and develop the electrostatic latent image by supplying toner from a developer to the image carrier. In such image forming apparatuses, superimposing an AC voltage component on the development voltage applied to the developer facilitates the transfer of toner from the developer to the image carrier, thereby improving development performance. Generally, a square wave is used as the waveform of the AC voltage component.

[0003] In electrophotographic printing, image quality degradation can occur, such as ring marks in the toner image caused by discharge between the developer and the image carrier, and white spots caused by toner being drawn to high-density areas instead of low-density areas. Patent Document 1 discloses a technique to prevent this image quality degradation by creating a difference in the positive and negative voltage amplitudes of the AC voltage component of the development voltage. The image forming apparatus described in Patent Document 1 generates an AC voltage component in the secondary winding by alternately applying positive and negative voltages to the primary winding of the transformer using an H-bridge circuit, and superimposes this AC voltage component on the development voltage output to the developer. Voltage adjustment circuits are connected to the two high-side switches of the H-bridge circuit, and the difference in voltage adjusted by these voltage adjustment circuits results in a difference in the positive and negative voltage amplitudes of the AC voltage component. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 5506267 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, the circuit configuration described in Patent Document 1 still has room for improvement in terms of the number of components and the area of ​​the circuit board. For example, if the waveform of the AC voltage component can be made into a desired waveform without providing a voltage adjustment circuit, the cost can be reduced by reducing the number of components, and the miniaturization of the circuit board can be promoted.

[0006] In view of the circumstances described above, this disclosure aims to improve the configuration of a circuit for generating the AC voltage component of the developing voltage. [Means for solving the problem]

[0007] From one perspective, an image forming apparatus comprises an image carrier that carries an electrostatic latent image, a developer that develops the electrostatic latent image carried by the image carrier, and a voltage generation circuit that generates a development voltage applied to the developer. The voltage generation circuit includes a transformer, an H-bridge circuit consisting of a first switch and a second switch connected to a first terminal of the primary side circuit of the transformer, and a third switch and a fourth switch connected to a second terminal of the primary side circuit of the transformer, a power supply connected to the first switch and the third switch of the H-bridge circuit, a drive circuit that outputs a first drive signal for controlling the on / off state of the first switch and the fourth switch, and a second drive signal for controlling the on / off state of the second switch and the third switch, and a DC output circuit that outputs a DC voltage component. The image forming apparatus further comprises: a control circuit that outputs a target voltage signal representing a target waveform; a detection circuit that detects the AC voltage component of the developing voltage output from the voltage generation circuit to the developing unit and outputs a detection voltage signal representing the waveform of the detected AC voltage component; and a control signal generation circuit that generates a first control signal that instructs the first switch and the fourth switch to be turned on or off, and a second control signal that instructs the second switch and the third switch to be turned on or off, based on a comparison between the target voltage signal from the control circuit and the detection voltage signal from the detection circuit, and outputs the generated first control signal and the second control signal to the drive circuit. An AC voltage component having an amplitude dependent on the duty cycle of the time during which a positive voltage is applied to the primary side circuit by the first drive signal turning on the first switch and the fourth switch in accordance with the first control signal, and the time during which a negative voltage is applied to the primary side circuit by the second drive signal turning on the second switch and the third switch in accordance with the second control signal, is generated in the secondary side circuit of the transformer. The voltage generation circuit outputs the developing voltage to the developing unit, which is obtained by superimposing the AC voltage component generated in the secondary circuit of the transformer onto the DC voltage component output from the DC output circuit. [Effects of the Invention]

[0008] According to this disclosure, it becomes possible to output a desired waveform of the AC voltage component of the developing voltage of an image forming apparatus using a circuit with fewer components or a smaller size. [Brief explanation of the drawing]

[0009] [Figure 1] A circuit diagram showing an example of a conventional circuit configuration for generating a developing voltage. [Figure 2] A schematic diagram showing an example of the general configuration of an image forming apparatus according to one embodiment. [Figure 3] A circuit diagram showing an example of the configuration of a voltage generation circuit according to the first embodiment. [Figure 4] A time chart showing an example of the signal level transitions of several signals in the first embodiment. [Figure 5] A circuit diagram showing an example of the configuration of a voltage generation circuit according to the second embodiment. [Figure 6] A time chart showing an example of the signal level transitions of several signals in the second embodiment. [Figure 7] A circuit diagram showing an example of the configuration of a voltage generation circuit according to the third embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the scope of the claims. While the embodiments describe multiple features, not all of these features are necessary, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0011] <1. Examples of circuit configurations in related technologies> Figure 1 is a circuit diagram showing an example of a conventional circuit configuration for generating a developing voltage related to the technology of this disclosure. The voltage generation circuit 91 in Figure 1 generates a developing voltage to be output to a developing unit 99 under the control of a controller 90. The voltage generation circuit 91 includes a voltage control circuit 92, an AC output circuit 93, and a DC output circuit 94. The AC output circuit 93 includes a transformer T91, an H-bridge circuit consisting of four switches Q91, Q92, Q93, and Q94, a first voltage adjustment circuit 95, a second voltage adjustment circuit 96, and a power supply 97. The four switches Q91, Q92, Q93, and Q94 of the H-bridge circuit may be, for example, n-channel field-effect transistors (FETs).

[0012] The first switch Q91 and the second switch Q92 of the H-bridge circuit are connected to the first terminal of the primary circuit of the transformer. More specifically, the source of the first switch Q91 is connected to the first terminal of the primary circuit of the transformer, the drain is connected to the output terminal of the first voltage regulation circuit 95, and the gate is connected to the voltage control circuit 92. The first switch Q91 receives the first drive signal D from the voltage control circuit 92. Q91 When the voltage level rises above the threshold voltage, it switches to the energized state (on). The source of the second switch Q92 is grounded, the drain is connected to the first terminal of the primary circuit of the transformer, and the gate is connected to the voltage control circuit 92. The second switch Q92 receives the second drive signal D from the voltage control circuit 92. Q92 When the level becomes high, it switches to an energized state.

[0013] The third switch Q93 and the fourth switch Q94 of the H-bridge circuit are connected to the second terminal of the primary circuit of the transformer. More specifically, the source of the third switch Q93 is connected to the second terminal of the primary circuit of the transformer, the drain is connected to the output terminal of the second voltage regulation circuit 96, and the gate is connected to the voltage control circuit 92. The third switch Q93 receives the third drive signal D from the voltage control circuit 92. Q93When it reaches a high level, it switches to the energized state. The source of the fourth switch Q94 is grounded, the drain is connected to the second terminal of the primary side circuit of the transformer, and the gate is connected to the voltage control circuit 92. The fourth switch Q94 is a fourth drive signal D input from the voltage control circuit 92 Q94 When it reaches a high level, it switches to the energized state.

[0014] The first voltage adjustment circuit 95 is an emitter follower circuit including a transistor Q95 and a capacitor C91. The collector of the transistor Q95 is connected to the power supply 97, the base is connected to the voltage control circuit 92, and the emitter is connected to the output terminal of the first voltage adjustment circuit 95. The voltage of the power supply 97 is, for example, +24V. The transistor Q95 outputs a power supply voltage Va depending on the voltage of the first voltage setting signal S VP+ from the emitter. That is, the first voltage adjustment circuit 95 generates a power supply voltage Va corresponding to the value of the first voltage setting signal S VP+ .

[0015] The second voltage adjustment circuit 96 is an emitter follower circuit including a transistor Q96 and a capacitor C92. The collector of the transistor Q96 is connected to the power supply 97, the base is connected to the voltage control circuit 92, and the emitter is connected to the output terminal of the second voltage adjustment circuit 96. The transistor Q96 outputs a power supply voltage Vb depending on the voltage of the second voltage setting signal S VP- from the emitter. That is, the second voltage adjustment circuit 96 generates a power supply voltage Vb corresponding to the value of the second voltage setting signal S VP- . The power supply voltage Vb may be different from the power supply voltage Va.

[0016] When the voltage control circuit 92 turns on the first and fourth drive signals D Q91 , D Q94 and turns off the second and third drive signals D Q92 , D Q93 (the first drive state), a positive power supply voltage Va is applied to the primary side circuit of the transformer T91. Also, when the voltage control circuit 92 turns off the first and fourth drive signals D Q91 , D Q94 and turns on the second and third drive signals DQ92 , D Q93 When this is turned on (second drive state), a negative power supply voltage Vb is applied to the primary circuit of transformer T91. As the first and second drive states of transformer T91 are repeated alternately, an AC voltage component Vac with different amplitudes for positive and negative (a so-called biased duty cycle waveform) is generated in the secondary circuit of transformer T91.

[0017] The DC output circuit 94 receives the DC setting signal S from the voltage control circuit 92. DC The AC output circuit 93 outputs a DC voltage component Vdc corresponding to the value of to one end of the secondary circuit of transformer T91. The other end of the secondary circuit of transformer T91 is connected to the developer 99 via the output terminal of the voltage generation circuit 91. Therefore, the AC output circuit 93 outputs a developed voltage (Vdc + Vac), in which the AC voltage component Vac generated in the secondary circuit of transformer T91 is superimposed on the DC voltage component Vdc, to the developer 99.

[0018] The circuit configuration shown in Figure 1 still has room for improvement in terms of the number of components and board area. For example, the first voltage adjustment circuit 95 and the second voltage adjustment circuit 96 play a role in adjusting the positive and negative amplitudes of the AC voltage component, but a relatively large space needs to be provided between the power supply 97 and the developer 99 for the voltage adjustment circuits. Therefore, if the waveform of the AC voltage component can be made into the desired waveform without providing these voltage adjustment circuits, the cost will be reduced by reducing the number of components, and the miniaturization of the board will be promoted.

[0019] <2. Example of image forming apparatus configuration> Figure 2 is a schematic diagram showing an example of the general configuration of an image forming apparatus 100 according to one embodiment. In the example in Figure 2, the image forming apparatus 100 is a color printer that forms images using an electrophotographic method. In other embodiments, the technology according to this disclosure may also be applied to a monochrome printer.

[0020] The image forming apparatus 100 includes image forming units 100a, 100b, 100c, and 100d, an intermediate transfer belt 5, a secondary transfer roller 7, a fuser 8, a cassette 9, and a controller 10. Each of the image forming units 100a, 100b, 100c, and 100d forms a toner image of four color components: yellow (Y), magenta (M), cyan (C), and black (K). The configurations of these image forming units 100a, 100b, 100c, and 100d may be identical except for the differences in color components; therefore, the configuration of image forming unit 100a will be used as an example in this explanation. In other embodiments, a color image may be formed by a combination of other color components.

[0021] The image forming unit 100a includes a photosensitive drum 1a, a charging roller 2a, a laser scanner 3a, a developer 4a, and a primary transfer roller 6a. The photosensitive drum 1a is an image carrier that is rotated counterclockwise in the figure. The charging roller 2a is subjected to a charging voltage to uniformly charge the surface of the photosensitive drum 1a. The laser scanner 3a exposes the surface of the photosensitive drum 1a with laser light according to the input image signal, thereby forming an electrostatic latent image on the surface of the photosensitive drum 1a. The developer 4a is subjected to a developing voltage and supplies toner as a developer to the photosensitive drum 1a, thereby developing the electrostatic latent image carried by the photosensitive drum 1a and forming a toner image. The primary transfer roller 6a is subjected to a primary transfer voltage and transfers the toner image formed on the surface of the photosensitive drum 1a to the intermediate transfer belt 5. The four toner images formed by the image forming units 100a, 100b, 100c, and 100d are sequentially superimposed and transferred to form a full-color toner image (color image) on the intermediate transfer belt 5. The intermediate transfer belt 5 then transports the color image to the secondary transfer position where the secondary transfer roller 7 is located.

[0022] Cassette 9 contains a bundle of sheets. Sheets P are separated one by one from the bundle and fed from cassette 9 to the transport path. Sheets P are fed to the secondary transfer position in time with the arrival of the color image on the intermediate transfer belt 5 at the secondary transfer position. The secondary transfer roller 7 is subjected to a secondary transfer voltage and transfers the color image on the intermediate transfer belt 5 to sheet P. The fuser 8 fixes the color image to sheet P by heating and pressurizing it. The controller 10 controls the image forming operation of the image forming apparatus 100 as described above.

[0023] Although not shown in Figure 2, each of the image forming units 100a to 100d includes a voltage generation circuit that generates the development voltage applied to the developing units 4a to 4d. These voltage generation circuits output a development voltage to the developing units 4a to 4d in which a rectangular wave AC voltage component is superimposed on a DC voltage component, in order to improve development performance. In the following section, we will focus on one of these voltage generation circuits and describe in detail several embodiments of its circuit configuration.

[0024] <3. First Embodiment> Figure 3 is a circuit diagram showing an example of the configuration of the voltage generation circuit 20 according to the first embodiment. Referring to Figure 3, the voltage generation circuit 20 includes a target control circuit 11, a control signal generation circuit 14, an AC output circuit 21, a DC output circuit 24, an AC detection circuit 25, and an output terminal 26. The target control circuit 11 is connected to the controller 10. The output terminal 26 is connected to the developer 4a, 4b, 4c, or 4d.

[0025] (1) Generation of AC voltage components The AC output circuit 21 includes a transformer T11, an H-bridge circuit consisting of four switches Q11, Q12, Q13, and Q14, a drive circuit 22, and a power supply 23. The four switches Q11, Q12, Q13, and Q14 of the H-bridge circuit may be, for example, n-channel FETs.

[0026] The first switch Q11 and the second switch Q12 of the H-bridge circuit are connected to the first terminal N1 of the primary side circuit of the transformer. More specifically, the source of the first switch Q11 is connected to the first terminal N1, the drain is connected to the power supply 23, and the gate is connected to the drive circuit 22. The voltage of the power supply 23 is, for example, +24V. The source of the second switch Q12 is grounded, the drain is connected to the first terminal N1, and the gate is connected to the drive circuit 22.

[0027] The third switch Q13 and the fourth switch Q14 of the H-bridge circuit are connected to the second terminal N2 of the primary side circuit of the transformer. More specifically, the source of the third switch Q13 is connected to the second terminal N2, the drain is connected to the power supply 23, and the gate is connected to the drive circuit 22. The source of the fourth switch Q14 is grounded, the drain is connected to the second terminal N2, and the gate is connected to the drive circuit 22.

[0028] In other words, in this embodiment, the first switch Q11 and the third switch Q13 on the high side of the H-bridge circuit of the AC output circuit 21 are directly connected to the power supply 23 without going through a voltage adjustment circuit as shown in Figure 1. This is also the case in the second and third embodiments described later.

[0029] The drive circuit 22 receives the first control signal S from the control signal generation circuit 14. C1 Based on this, a first drive signal D controls the on / off state of the first switch Q11 and the fourth switch Q14. Q1 This is output to the gate of the first switch Q11 and the gate of the fourth switch Q14. For example, the drive circuit 22 outputs the first control signal S C1 By amplifying the first drive signal D Q1 The first switch Q11 and the fourth switch Q14 generate the first drive signal D Q1 When the level becomes high, it switches to an energized state.

[0030] Furthermore, the drive circuit 22 receives a second control signal S from the control signal generation circuit 14. C2Based on this, a second drive signal D controls the on / off state of the second switch Q12 and the third switch Q13. Q2 This is output to the gate of the second switch Q12 and the gate of the third switch Q13. For example, the drive circuit 22 outputs the second control signal S C2 By amplifying the second drive signal D Q2 The second switch Q12 and the third switch Q13 generate the second drive signal D Q2 When the signal level becomes high, it switches to the powered state. First drive signal D Q1 and second drive signal D Q2 It cannot be turned on simultaneously at any given time.

[0031] The drive circuit 22 may also include a bootstrap circuit to supply a voltage higher than +24V to the gates of the first switch Q11 and the third switch Q13 on the high side of the H-bridge circuit.

[0032] The first drive signal D should be present during the period when the AC component of the development voltage is positive. Q1 The first switch Q11 and the fourth switch Q14 are turned on, and the second drive signal D is also turned on during the same period. Q2 When the second switch Q12 and the third switch Q13 are turned off, a positive voltage of 24V is applied to the primary circuit of transformer T11. Also, during the period when the AC component of the developing voltage should be negative, the first drive signal D Q1 The first switch Q11 and the fourth switch Q14 are turned off, and the second drive signal D is turned off during the same period. Q2 When the second switch Q12 and the third switch Q13 are turned on, a negative voltage of -24V is applied to the primary circuit of the transformer T11. In this case, the absolute values ​​of the positive and negative voltages are equal. On the other hand, in this embodiment, the first drive signal D is used to make the AC component of the developing voltage positive. Q1 The intermittent ON signal applies a positive voltage to the primary circuit of transformer T11 for a certain period of time, and the second drive signal D makes the AC component of the developing voltage negative. Q2 The duty cycle between the time a negative voltage is applied to the primary circuit by intermittently instructing it to turn on is variably controlled. And the first drive signal D Q1The positive amplitude and second drive signal D depend on the duty cycle. Q2 An AC voltage component Vac with a negative amplitude, dependent on the duty cycle, is generated in the secondary circuit of transformer T11. Specifically, the first drive signal D Q1 The higher the duty cycle, the larger the positive amplitude of the AC voltage component Vac becomes (approaching +24V), and the second drive signal D Q2 The higher the duty cycle, the larger the negative amplitude of the AC voltage component Vac becomes (approaching -24V). The control signal generation circuit 14, described later, generates a first control signal S such that these positive and negative amplitudes of the AC voltage component Vac approach the target value. C1 and second control signal S C2 This is output to the drive circuit 22.

[0033] (2) Output of the developing voltage The DC output circuit 24 receives the DC setting signal S from the target control circuit 11. DC A DC voltage component Vdc, whose magnitude depends on the AC voltage, is output to one end of the secondary circuit of transformer T11. The other end of the secondary circuit of transformer T11 is connected to output terminal 26. Therefore, the AC voltage component Vac output from AC output circuit 21 is superimposed on the DC voltage component Vdc output from DC output circuit 24. The voltage generation circuit 20 outputs a developing voltage Vdc+Vac, which is equal to the sum of the DC voltage component Vdc and the AC voltage component Vac thus generated, to the developing units 4a, 4b, 4c, or 4d via output terminal 26.

[0034] (3) Generation of the target waveform The target control circuit 11 includes a target waveform generation unit 12 and a digital-to-analog (D / A) converter 13. The target waveform generation unit 12 communicates serially with the controller 10. The target waveform generation unit 12 receives commands from the controller 10 for generating the target waveform.

[0035] The target waveform represents a waveform similar to the waveform of the developing voltage to be applied to the developing units 4a, 4b, 4c, or 4d. The target waveform may be the sum of an AC voltage component, which is a square wave, and a DC voltage component, which exhibits a constant voltage, similar to the waveform of the developing voltage. The frequency of the AC voltage component of the target waveform is equal to the frequency of the AC voltage component of the developing voltage. The controller 10 may determine the target waveform in such a way as to suppress a decrease in the developing performance of the developing unit caused by changes in the operating conditions of the image forming apparatus 100 (for example, changes in environmental conditions such as temperature or humidity, or deterioration of components due to long-term use). For example, the target control circuit 11 may increase the negative amplitude of the AC voltage component of the target waveform if the likelihood of image quality degradation such as ring marks or white spots is higher.

[0036] The controller 10 can provide the target waveform generation unit 12 with waveform information indicating, for example, the magnitude of the DC voltage component of the target waveform, as well as the positive amplitude, negative amplitude, and frequency of the AC voltage component. The target waveform generation unit 12 generates a digital signal that simulates the target waveform in response to a command from the controller 10, and outputs the generated digital signal to the D / A converter 13. The D / A converter 13 converts the signal format of the digital signal input from the target waveform generation unit 12 from digital to analog, thereby generating the target voltage signal W TG The target control circuit 11 generates the target voltage signal W generated by the D / A converter 13. TG The signal is output to the control signal generation circuit 14. The target control circuit 11 also outputs a DC setting signal S that indicates the magnitude of the DC voltage component of the developed voltage. DC This is output to the DC output circuit 24.

[0037] (4) Control of duty cycle The AC detection circuit 25 detects the AC voltage component of the developing voltage output from the voltage generation circuit 20 to the developing units 4a, 4b, 4c, or 4d, and generates a detected voltage signal W representing the waveform of the detected AC voltage component. DET This is output to the control signal generation circuit 14.

[0038] The control signal generation circuit 14 receives the target voltage signal W from the target control circuit 11. TGAnd the detected voltage signal W from the AC detection circuit 25 DET Based on the comparison with, the first control signal S C1 and second control signal S C2 Generates the first control signal S. C1 This is a sequence of pulse signals that instruct the first switch Q11 and the fourth switch Q14 to be turned on or off. Second control signal S C2 This is a sequence of pulse signals that indicate the on or off states of the second switch Q12 and the third switch Q13. The width of the on period and the width of the off period in each cycle of these pulse signals vary.

[0039] In this embodiment, the control signal generation circuit 14 is implemented as a simple comparison circuit 15. The comparison circuit 15 generates, for example, a target voltage signal W TG and detected voltage signal W DET Based on the comparison between the two, the first control signal S is controlled according to the control logic shown in Table 1 below. C1 and second control signal S C2 The signal level can be determined.

[0040] [Table 1]

[0041] According to Table 1, the first control signal S C1 The target voltage signal W TG The detected voltage signal W DET When the voltage is higher than this, it becomes high level, instructing the first switch Q11 and the fourth switch Q14 to turn on. Also, the first control signal S C1 The target voltage signal W TG The detected voltage signal W DET The second control signal S becomes low when it shows a voltage lower than the specified value, instructing the first switch Q11 and the fourth switch Q14 to turn off. C2 The target voltage signal W TG The detected voltage signal W DET When the voltage is lower than this, it becomes high level, instructing the second switch Q12 and the third switch Q13 to turn on. Also, the second control signal S C2 The target voltage signal W TGis the detected voltage signal W DET becomes low level when showing a voltage higher than that, and instructs the second switch Q12 and the third switch Q13 to turn off. In this example, the first control signal S C1 and the second control signal S C2 are a sequence of pulse signals inverted with respect to each other.

[0042] For example, assume that the developing voltage is maintained at V p+ and V p- in the high level section and the low level section respectively (V p+ > Vdc > V p- ), and the target voltage signal W TG shows voltages V1 and V2 in the high level section and the low level section respectively (V1 > V2). At the rising edge of the target voltage signal W TG , the target voltage signal W TG changes from V2 to V1, and until the detected voltage signal W DET follows this change, W TG > W DET . Then, the first control signal S C1 is turned on, the second control signal S C2 is instructed to turn off, a positive voltage is applied to the primary side circuit of the transformer T11 of the AC output circuit 21, and as a result, the duty ratio of the positive voltage increases, and the AC voltage component Vac of the developing voltage rises. Eventually, when the AC voltage component Vac exceeds V1 due to overshoot, W TG ≦ W DET . Then, the first control signal S C1 is turned off, the second control signal S C2 is instructed to turn on, a negative voltage is applied to the primary side circuit of the transformer T11 of the AC output circuit 21, and as a result, the duty ratio of the negative voltage increases, and the AC voltage component Vac of the developing voltage decreases. Eventually, when the AC voltage component Vac falls below V1 due to undershoot, W TG > W DET . Then, the first control signal S C1 is turned on, the second control signal S C2 is instructed to turn off, and a positive voltage is applied again to the primary side circuit of the transformer T11 of the AC output circuit 21. The target voltage signal W TGWhile it is maintained at V1, two control signals S C1 and S C2 repeatedly turn on and off at high speed like this. As a result, the AC voltage component Vac will be maintained near the target value while including pulsations during the high-level interval. The same applies to the fall of the target voltage signal W TG and the subsequent low-level interval.

[0043] The ideal frequency of the AC voltage component of the developing voltage is, for example, about 12 kHz. On the other hand, the speed of response to the feedback of the detection voltage signal W DET described above is generally sufficiently faster than 12 kHz. Therefore, the control deviation that becomes the largest immediately after the rise at the beginning of the high-level interval and the fall at the beginning of the low-level interval attenuates in the middle of each interval, and the developing voltage converges to a constant target value in the middle of each interval. However, in this embodiment, the pulsations, that is, the repeated slight positive and negative differences from the target value of the developing voltage, are directly converted into the pulses of the first control signal S C1 and the second control signal S C2 . Therefore, both the first control signal S C1 and the second control signal S C2 repeatedly turn on and off over the entire period of the AC voltage component Vac, and the amplitude of the AC voltage component Vac is controlled by the width of the on-period and the width of the off-period for each pulse period.

[0044] (5) Example of the temporal transition of the signal level FIG. 4 is a time chart showing an example of the transition of the signal levels of several signals in this embodiment. Chart 51 shows an example of the transition of the target voltage signal W<{0000100}>and the detection voltage signal W DET . Chart 52 shows an example of the transition of the first control signal S C1 and the second control signal S C2 . Chart 53 shows an example of the transition of the developing voltage output from the AC output circuit 21.

[0045] In Chart 51, the target voltage signal W TGis a rectangular wave that repeats a period consisting of a low-level interval of length T- and a high-level interval of length T+. In the illustrated example, the period from time t1 to t4 corresponds to one low-level interval, and the voltage of the target voltage signal W TG in the low-level interval is equal to V2. In this embodiment, T- < T+. Also, the period from time t4 to t7 corresponds to one high-level interval, and the voltage of the target voltage signal W TG in the high-level interval is equal to V1. On the other hand, the detection voltage signal W DET indicated by the dashed line is a substantially rectangular wave that repeats on and off following the fall and rise of the target voltage signal W TG . In the illustrated example, the detection voltage signal W DET reaches the low level (V2) at time t2, lagging behind the fall of the target voltage signal W TG at time t1. From time t3 to time t4, the detection voltage signal W DET is maintained near the target value of the low level while including pulsations. Also, the detection voltage signal W DET reaches the high level (V1) at time t5, lagging behind the rise of the target voltage signal W TG at time t4. From time t6 to time t7, the detection voltage signal W DET is maintained near the target value of the high level while including pulsations.

[0046] The voltage range of the target voltage signal W TG and the detection voltage signal W DET is, for example, 0 to V CC [V], and V CC is determined by the power supply voltage of the control system. V CC / 2 corresponding to the center of this range corresponds to the origin of the AC voltage component Vac. In other words, a voltage higher than V CC / 2 corresponds to the positive voltage of the AC voltage component Vac, and a voltage lower than V CC / 2 corresponds to the negative voltage value of the AC voltage component Vac.

[0047] The first control signal S C1 shown in chart 52 is such that the target voltage signal W TG of chart 51 is the detection voltage signal W DETHigh levels over a longer period than the target voltage signal W TG The detected voltage signal W DET It shows a low level for a shorter period than the second signal S. C2 The target voltage signal W TG The detected voltage signal W DET High level in a shorter period than the target voltage signal W TG The detected voltage signal W DET It shows low levels over a longer period.

[0048] The development voltage Vdc+Vac shown in Chart 53 is the sum of the DC voltage component Vdc and the AC voltage component Vac. In the illustrated example, the positive amplitude of the AC voltage component Vac is |V p+ -Vdc|, negative amplitude is |Vdc-V p- It is equal to |, and the negative amplitude is greater than the positive amplitude.

[0049] (6) Summary of the first embodiment According to the first embodiment described above, two switch pairs in the H-bridge circuit are rapidly switched on and off by simple feedback control based on a comparison between a target voltage signal and a detection voltage signal representing the detection result of the AC voltage component of the output voltage to the developer. This makes it possible to change the duty cycle of the time during which a positive voltage is applied to the primary circuit of the transformer and the time during which a negative voltage is applied in accordance with the target voltage signal, thereby generating AC voltage components with desired positive and negative amplitudes in the secondary circuit of the transformer.

[0050] In particular, the configuration of the voltage generation circuit 20 in the first embodiment eliminates the need for a voltage adjustment circuit, which was present in conventional circuit configurations to differentiate the positive and negative amplitudes of the AC component of the developing voltage. Therefore, the number of components in the device is reduced, manufacturing costs are lowered, and the miniaturization of the circuit board is promoted.

[0051] For the purpose of preventing image degradation such as ring marks or white spots in toner images, the target value of the negative amplitude of the AC voltage component may be set to a value greater than the target value of the positive amplitude. However, the technology relating to this disclosure is not limited to such examples. The target value of the negative amplitude of the AC voltage component may be set to a value equal to or less than the target value of the positive amplitude.

[0052] In the example shown in Figure 3, the control signal generation circuit 14 is an analog circuit that compares the target voltage signal and the detected voltage signal, both of which are analog signals. However, the control signal generation circuit 14 may also be configured as a digital circuit that compares digital signals. In that case, instead of omitting the D / A converter 13 in the target control circuit 11, analog-to-digital (A / D) conversion may be applied to the detected voltage signal from the AC detection circuit 25.

[0053] <4. Second Embodiment> Figure 5 is a circuit diagram showing an example of the configuration of the voltage generation circuit 30 according to the second embodiment. Referring to Figure 5, the voltage generation circuit 30 includes a target control circuit 11, a control signal generation circuit 34, an AC output circuit 21, a DC output circuit 24, an AC detection circuit 25, and an output terminal 26. The target control circuit 11 is connected to the controller 10. The output terminal 26 is connected to the developer 4a, 4b, 4c, or 4d.

[0054] The configurations of the target control circuit 11, AC output circuit 21, DC output circuit 24, and AC detection circuit 25 according to the second embodiment may be the same as those in the first embodiment described in the previous section.

[0055] (1) Control of duty cycle The control signal generation circuit 34 receives the target voltage signal W from the target control circuit 11. TG And the detected voltage signal W from the AC detection circuit 25 DET Based on the comparison with, the first control signal S C1 and second control signal S C2 Generates the first control signal S. C1 This is a sequence of pulse signals that instruct the first switch Q11 and the fourth switch Q14 to be turned on or off. Second control signal SC2 This is a sequence of pulse signals that instruct the second switch Q12 and the third switch Q13 to be turned on or off. Similar to the first embodiment, the pulse width of these pulse signals is variable, and the positive and negative amplitudes of the AC voltage component Vac output from the AC output circuit 21 are controlled by pulse width modulation (PWM). In the first embodiment, the switching period of the two control signals is the target voltage signal W TG Detection voltage signal W DET Although it is passively determined depending on the deviation, in the second embodiment, the switching period of the two control signals is determined by the carrier signal S described later. CR It is actively set as the period.

[0056] In this embodiment, the control signal generation circuit 34 performs more advanced feedback control to suppress output ripple or other noise appearing in the development voltage output to the developer. The control signal generation circuit 34 includes a first comparator circuit 35, a feedback (FB) control circuit 36, a carrier wave generation circuit 37, and a second comparator circuit 38.

[0057] The first comparison circuit 35 receives the target voltage signal W TG Detection voltage signal W DET The deviation is calculated, and the deviation signal S represents the calculated deviation. DF This is output to the FB control circuit 36.

[0058] The FB control circuit 36 ​​receives the deviation signal S DF The target voltage signal W is controlled by feedback control (e.g., PI control or PID control) based on the deviation represented by the error. TG Detection voltage signal W DET Modulated voltage signal S that is modulated so that the deviation is eliminated. MOD The FB control circuit 36 ​​outputs the deviation signal S. DF For the deviation represented by , at least proportional (P) control using a proportional gain and integral (I) control including multiplication of the cumulative value of the deviation by an integral gain are applied. The FB control circuit 36 ​​may further apply differential (D) control using a differential gain. The values ​​of these gains are determined in advance by tuning and incorporated into the FB control circuit 36.

[0059] The carrier wave generation circuit 37 generates a carrier signal S having a frequency sufficiently higher than the frequency of the AC voltage component Vac that the AC output circuit 21 should generate. CR This generates the AC voltage component Vac, for example, the frequency of which may be approximately 12 kHz as described above, and the carrier signal S CR The frequency may be approximately 100 MHz. In this embodiment, the carrier signal S CR 0V and maximum voltage V CC It may be a triangular wave that repeatedly exhibits linear voltage increases and decreases between the two points.

[0060] The second comparison circuit 38 receives the modulated voltage signal S from the FB control circuit 36. MOD and the carrier signal S from the carrier wave generation circuit 37 CR Based on the comparison with, the first control signal S C1 and second control signal S C2 The second comparison circuit 38 generates the first control signal S according to the control logic shown in Table 2 below, for example. C1 and second control signal S C2 The signal level can be determined:

[0061] [Table 2]

[0062] According to Table 2, the first control signal S C1 is the modulated voltage signal S MOD is the carrier signal S CR When the voltage is higher than this, it becomes high level, instructing the first switch Q11 and the fourth switch Q14 to turn on. Also, the first control signal S C1 is the modulated voltage signal S MOD is the carrier signal S CR The second control signal S becomes low when it shows a voltage lower than the specified value, instructing the first switch Q11 and the fourth switch Q14 to turn off. C2 is the modulated voltage signal S MOD is the carrier signal S CRbecomes high level when indicating a voltage lower than, and instructs the turning on of the second switch Q12 and the third switch Q13. Also, the second control signal S C2 is a modulation voltage signal S MOD becomes low level when indicating a voltage higher than the carrier signal S CR and instructs the turning off of the second switch Q12 and the third switch Q13. In this example, the first control signal S C1 and the second control signal S C2 are sequences of pulse signals inverted with respect to each other.

[0063] (2) Example of the temporal transition of signal levels FIG. 6 is a time chart showing an example of the transition of signal levels of some signals in the present embodiment. Chart 61 shows an example of the transition of the target voltage signal W TG and the detected voltage signal W DET . Chart 62 shows an example of the transition of the modulation voltage signal S MOD and the carrier signal S CR . Chart 63 shows an example of the transition of the first control signal S C1 and the second control signal S C2 . Chart 64 shows an example of the transition of the developing voltage output from the AC output circuit 21.

[0064] In chart 61, the target voltage signal W TG indicated by a solid line is a rectangular wave that repeats a cycle consisting of a low-level section of length T- and a high-level section of length T+. In the present embodiment, T- < T+. In the illustrated example, the period from time t1 to t4 corresponds to one low-level section, and in the low-level section, the voltage of the target voltage signal W TG is equal to V2. Also, the period from time t4 to t7 corresponds to one high-level section, and in the high-level section, the voltage of the target voltage signal W TG is equal to V1. On the other hand, the detected voltage signal W DET indicated by a broken line is a substantially rectangular wave that repeats on and off following the fall and rise of the target voltage signal W TG . In the illustrated example, the detected voltage signal W DET is the target voltage signal W at time t1TG The detection voltage signal W reaches a low level (V2) at time t2, later than the falling edge of the signal, and converges at time t3. DET The target voltage signal W at time t4 is TG It reaches a high level (V1) at time t5, later than the rise time, and converges at time t6.

[0065] Target voltage signal W TG and detected voltage signal W DET The voltage range is, for example, 0~V CC [V] is V CC This is determined by the power supply voltage of the control system. The middle of this range corresponds to V CC / 2 corresponds to the origin of the AC voltage component Vac. In other words, V CC A voltage higher than / 2 is the positive voltage of the AC voltage component Vac, V CC A voltage lower than / 2 corresponds to a negative voltage value of the AC voltage component Vac.

[0066] The modulated voltage signal S shown in Chart 62 MOD The target voltage signal W TG Detection voltage signal W DET This is the signal generated by the FB control circuit 36 ​​as a result of the PI control or PID control described above based on the deviation. Modulated voltage signal S MOD The target voltage signal W TG and detected voltage signal W DET It tracks fluctuations and displays a voltage near voltage D2 in the low-level section and near voltage D1 in the high-level section. Carrier signal S CR The target voltage signal W TG Voltage zero and maximum voltage V at a period sufficiently shorter than the period. CC It is a triangular wave that travels back and forth between these two points.

[0067] The first control signal S shown in Chart 63 C1 This is the modulated voltage signal S in Chart 62. MOD is the carrier signal S CR High levels over a longer period than the modulated voltage signal S MOD is the carrier signal S CRIt shows a low level for a shorter period than the first signal S. C1 The duty cycle of the modulated voltage signal S MOD ga V CC If equal to 100%, the modulated voltage signal S MOD ga V CC The second control signal S is 50% when it is equal to / 2, and 0% when the voltage is equal to zero. C2 is the modulated voltage signal S MOD is the carrier signal S CR A high level over a period shorter than that, modulated voltage signal S MOD is the carrier signal S CR It shows a low level for a longer period than the second signal S. C2 The duty cycle of the modulated voltage signal S MOD ga V CC If equal to 0%, the modulated voltage signal S MOD ga V CC It is 50% when it is equal to / 2, and 100% when the voltage is equal to zero.

[0068] The development voltage Vdc+Vac shown in Chart 64 is the sum of the DC voltage component Vdc and the AC voltage component Vac. In the illustrated example, the positive amplitude of the AC voltage component Vac is |V p+ -Vdc|, negative amplitude is |Vdc-V p- It is equal to |, and the negative amplitude is greater than the positive amplitude.

[0069] The following will explain the signal level progression in more detail over time. During the period T1 from time t0 to t1, the target voltage signal W TG This belongs to the high-level section and exhibits a steady voltage V1. During period T1, the modulated voltage signal S MOD As a result of feedback control, the voltage D1 is steadily displayed, and the first control signal S is accordingly. C1 The duty cycle is approximately 0.7, and the second control signal S C2The duty cycle is approximately 0.3. This means that a positive voltage (24V) is applied to the primary circuit of transformer T11 for approximately 70% of the time, and a negative voltage (-24V) is applied to the primary circuit of transformer T11 for approximately 30% of the time. In this case, the time average of the applied voltage to the primary circuit is a positive value, and the voltage generated in the secondary circuit of transformer T11 is a positive value (V p+ -Vdc) is obtained. As a result, the voltage generation circuit 30 produces a voltage V p+ It outputs a development voltage indicating the following:

[0070] At time t1, the target voltage signal W TG The signal transitions to a low-level section, and its voltage changes from V1 to V2. Then the target voltage signal W TG The detected voltage signal W DET Since it falls below this value, the modulated voltage signal S MOD As a result of feedback control, it begins to descend. Accordingly, the first control signal S C1 The duty cycle of the second control signal S decreases, while the duty cycle of the second control signal S C2 The duty cycle increases. As a result, the developed voltage output from the voltage generation circuit 30 is V p+ From V p- Descending towards it.

[0071] At time t2, the developed voltage output from the voltage generation circuit 30 is the target value V p- It goes past the V mark and then descends (undershoot), p- It oscillates around it. At time t3, the development voltage is V p- It converges (stabilizes) to a certain point.

[0072] During the period T4 from time t3 to t4, the target voltage signal W TG This belongs to the low-level section and exhibits a steady voltage V2. During period T4, the modulated voltage signal S MOD As a result of feedback control, the voltage D2 is constantly observed, and the first control signal S is accordingly. C1 The duty cycle is approximately 0.2, and the second control signal S C2The duty cycle is approximately 0.8. This means that the proportion of time during which a positive voltage (24V) is applied to the primary circuit of transformer T11 is approximately 20%, and the proportion of time during which a negative voltage (-24V) is applied to the primary circuit of transformer T11 is approximately 80%. In this case, the time average of the applied voltage to the primary circuit will be a negative value, and the voltage generated in the secondary circuit of transformer T11 will be a negative value (V p- -Vdc) is obtained. As a result, the voltage generation circuit 30 produces a voltage V p- It outputs a development voltage indicating the following:

[0073] At time t4, the target voltage signal W TG The signal then transitions to a high-level section, and its voltage changes from V2 to V1. Then the target voltage signal W TG The detected voltage signal W DET Since it exceeds the modulated voltage signal S MOD The first control signal S begins to rise as a result of feedback control. C1 The duty cycle of the second control signal S increases, while the duty cycle of the second control signal S C2 The duty cycle decreases. As a result, the developed voltage output from the voltage generation circuit 30 is V p- From V p+ It rises towards [destination].

[0074] At time t5, the developed voltage output from the voltage generation circuit 30 is the target value V p+ It went too far up (overshoot), V p+ It oscillates around it. At time t6, the development voltage is V p+ It converges (stabilizes) to a certain point.

[0075] The changes in the signal levels of each signal during the period T7 from time t6 to t7, and in the period thereafter, are the same as the changes described for time t0 to t6.

[0076] (3) Summary of the second embodiment According to the second embodiment described above, the two switch pairs of the H-bridge circuit are rapidly switched on and off by feedback control based on a comparison between the target voltage signal and the detection voltage signal representing the detection result of the AC voltage component of the output voltage to the developer. This allows the duty cycles of the time during which a positive voltage is applied to the primary circuit of the transformer and the time during which a negative voltage is applied to follow the target voltage signal, thereby generating AC voltage components with desired positive and negative amplitudes in the secondary circuit of the transformer.

[0077] Furthermore, according to the second embodiment, the on / off cycles of the two switch pairs in the H-bridge circuit are actively set as the cycle of the carrier signal. Therefore, compared to the first embodiment, in which the switching cycle of the control pulse is passively determined, the second embodiment can improve the tracking ability of the developed voltage with respect to the target waveform. In addition, in the second embodiment, it is easy to design the device so that the switching cycle is optimized in terms of suppressing noise such as output ripple in the developed voltage, or suppressing the temperature rise of components.

[0078] In the second embodiment, although the configuration of the control signal generation circuit becomes more complex, similar to the first embodiment, a voltage adjustment circuit is not required within the AC output circuit 21 that handles high voltages to make the positive and negative amplitudes of the AC component of the developed voltage different. Therefore, the manufacturing cost of the device can be reduced, and the degree of freedom in circuit design can be increased, promoting miniaturization of the substrate.

[0079] <5. Third Embodiment> The duty cycle control described above for generating the desired AC voltage component of the development voltage may be achieved without deviation feedback, as in the first and second embodiments. In the third embodiment described in this section, the voltage generation circuit 40 generates a development voltage having the desired AC voltage component by so-called open control using a predetermined sequence of control signals stored in memory, instead of deviation feedback from the target.

[0080] Figure 7 is a circuit diagram showing an example of the configuration of the voltage generation circuit 40 according to the third embodiment. Referring to Figure 7, the voltage generation circuit 40 includes a control signal generation circuit 44, an AC output circuit 21, a DC output circuit 24, and an output terminal 26. The control signal generation circuit 44 is connected to the controller 10. The output terminal 26 is connected to the developer 4a, 4b, 4c, or 4d.

[0081] The configurations of the AC output circuit 21 and DC output circuit 24 according to the third embodiment may be the same as those in the first and second embodiments described above.

[0082] The control signal generation circuit 44 includes a memory 45 and a signal generation circuit 46. The signal generation circuit 46 performs serial communication with the controller 10.

[0083] Memory 45 pre-stores the first waveform information and the second waveform information. The first waveform information is the first drive signal D that should be output from the drive circuit 22 to the first switch Q11 and the fourth switch Q14. Q1 This defines the ideal signal waveform. The second waveform information is the second drive signal D that should be output from the drive circuit 22 to the second switch Q12 and the third switch Q13. Q2 Define the ideal signal waveform of the first drive signal D. Q1 and second drive signal D Q2 Since both are sequences of pulse signals, the first waveform information and the second waveform information define at least the on / off timing of each signal. The switching frequency of the pulse signals shall be sufficiently higher than the frequency of the desired AC voltage component of the developed voltage. First drive signal D Q1 and second drive signal D Q2 The ideal signal waveform can be determined, for example, through pre-shipment testing of the product.

[0084] The signal generation circuit 46 reads first waveform information and second waveform information from the memory 45 in response to a command from the controller 10, and generates a first control signal S according to the first waveform information. C1 It generates a second control signal S according to the second waveform information. C2The signal generation circuit 46 then generates the first control signal S that it has generated. C1 and second control signal S C2 The signal is output to the drive circuit 22. The signal generation circuit 46 also outputs a DC setting signal S that indicates the magnitude of the DC voltage component of the development voltage. DC This is output to the DC output circuit 24.

[0085] The drive circuit 22 receives the first control signal S C1 By amplifying the first drive signal D Q1 Generates the first drive signal D Q1 The first switch Q11 and the fourth switch Q14 output this signal. The drive circuit 22 also outputs the second control signal S C2 By amplifying the second drive signal D Q2 Generates the second drive signal D Q2 This is output to the second switch Q12 and the third switch Q13.

[0086] In this embodiment, the first control signal S C1 and second control signal S C2 The signal waveform may be one of those illustrated in Chart 52 or Chart 63. Both signal waveforms typically represent a pulse train that repeatedly switches pulses on and off for PWM over the entire period of the AC voltage component Vac, with the frequency of the PWM control being sufficiently higher than the frequency of the AC voltage component Vac. First drive signal D Q1 and second drive signal D Q2 The waveform is the first control signal S C1 and second control signal S C2 The waveforms are similar to those of the original, and only the signal level may differ as a result of amplification. In the first and second embodiments, the waveforms of these control signals and drive signals are variable through feedback control, whereas in this embodiment, the waveforms of these control signals and drive signals are fixed.

[0087] In this embodiment, the duty cycles for the time a positive voltage is applied to the primary circuit of transformer T11 and the time a negative voltage is applied to the primary circuit are determined by the definition of the signal sequence in advance. An AC voltage component Vac with an amplitude dependent on this duty cycle is generated in the secondary circuit of transformer T11. The voltage generation circuit 40 outputs a developing voltage Vdc+Vac, which is equal to the sum of the DC voltage component Vdc output from the DC output circuit 24 and this AC voltage component Vac, to the developing units 4a, 4b, 4c, or 4d via the output terminal 26.

[0088] In one embodiment, the memory 45 may pre-store multiple sets of first waveform information and second waveform information corresponding to target waveforms with different development voltages. The controller 10 selects one of the above multiple sets of first waveform information and second waveform information, for example, to suppress a decrease in development performance caused by changes in the operating conditions of the image forming apparatus 100, and sends a command to the signal generation circuit 46 indicating the selected set. In response to the received command, the signal generation circuit 46 selectively reads the set of first waveform information and second waveform information selected by the controller 10 from the memory 45 and issues a first control signal S according to the read information. C1 and second control signal S C2 Generates.

[0089] As an example, the first set of multiple sets includes first and second waveform information for generating AC voltage components with a relatively small ratio of negative amplitude to positive amplitude. The second set of multiple sets includes first and second waveform information for generating AC voltage components with a relatively large ratio of negative amplitude to positive amplitude. In this example, a first control signal S is generated according to the waveform information of the first set. C1 The duty cycle of the first control signal S is generated according to the second set of waveform information. C1 It is greater than the duty cycle. Naturally, three or more sets of first and second waveform information may be provided.

[0090] According to the third embodiment described above, the two switch pairs of the H-bridge circuit are rapidly switched on and off by open control using a predetermined signal sequence stored in memory. As a result, the duty cycles of the time a positive voltage is applied to the primary circuit of the transformer and the time a negative voltage is applied change as designed, making it possible to generate AC voltage components with desired positive and negative amplitudes in the secondary circuit of the transformer.

[0091] In the voltage generation circuit 40 of the third embodiment, a voltage adjustment circuit, which was present in conventional circuit configurations, is not required to make the positive and negative amplitudes of the AC component of the developing voltage different. Therefore, the number of components in the device is reduced, manufacturing costs are lowered, and the degree of freedom in circuit design is increased, promoting miniaturization of the circuit board.

[0092] In the third embodiment, since the signal waveform of the drive signal is predetermined by waveform information, the selection of development voltage waveforms that can be generated in the voltage generation circuit 40 is limited to predetermined candidates. However, in the embodiments described above, multiple selections of waveform information are provided, so the development voltage waveform can be selected in such a way that a decrease in the development performance of the developer is suppressed in response to changes in operating conditions such as changes in environmental conditions or deterioration of materials.

[0093] In the first and second embodiments described above, the target control circuit 11 can generate a target waveform having any amplitude and frequency (not limited to predefined options), and bring the waveform of the developed voltage closer to that target waveform. Therefore, in these embodiments, more flexible voltage control can be achieved compared to the third embodiment.

[0094] <6. Other Embodiments> The above embodiment can also be implemented in the form of a process in which a program that implements one or more functions is supplied to a system or device via a network or storage medium, and one or more processors in the computer of that system or device read and execute the program. It can also be implemented by a circuit (e.g., an ASIC) that implements one or more functions.

[0095] While this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the exemplary embodiments disclosed. The following claims should be given the broadest possible interpretation to encompass all such modifications and equivalent structures and functions. [Explanation of symbols]

[0096] 100: Image forming apparatus, 1a, 1b, 1c, 1d: Photoreceptor (image carrier), 4a, 4b, 4c, 4d: Developer, 10: Controller, 11: Target control circuit, 14, 34, 44: Control signal generation circuit, 20, 30, 40: Voltage generation circuit, T11: Transformer, Q11: First switch, Q12: Second switch, Q13: Third switch, Q14: Fourth switch, 22: Drive circuit, 23: Power supply, 24: DC output circuit, 25: AC detection circuit, 35: First comparator circuit, 36: Feedback control circuit, 37: Carrier generation circuit, 38: Second comparator circuit, 45: Memory

Claims

1. An image forming apparatus, An image carrier that carries an electrostatic latent image, A developing unit for developing the electrostatic latent image carried by the image carrier, A voltage generation circuit that generates a developing voltage to be applied to the developing unit, Equipped with, The voltage generation circuit is Transformer and An H-bridge circuit comprising a first switch and a second switch connected to the first terminal of the primary side circuit of the transformer, and a third switch and a fourth switch connected to the second terminal of the primary side circuit of the transformer, A power supply connected to the first switch and the third switch of the H-bridge circuit, A drive circuit that outputs a first drive signal for controlling the on / off state of the first switch and the fourth switch, and a second drive signal for controlling the on / off state of the second switch and the third switch, A DC output circuit that outputs a DC voltage component, Includes, The image forming apparatus is A control circuit that outputs a target voltage signal representing the target waveform, A detection circuit that detects the AC voltage component of the developing voltage output from the voltage generation circuit to the developing unit and outputs a detection voltage signal representing the waveform of the detected AC voltage component, A control signal generation circuit generates a first control signal that instructs the first switch and the fourth switch to be turned on or off, and a second control signal that instructs the second switch and the third switch to be turned on or off, based on a comparison between the target voltage signal from the control circuit and the detection voltage signal from the detection circuit, and outputs the generated first control signal and second control signal to the drive circuit. Furthermore, it is equipped with An AC voltage component having an amplitude dependent on the duty cycle of the time during which a positive voltage is applied to the primary circuit by the first drive signal turning on the first switch and the fourth switch in accordance with the first control signal, and the time during which a negative voltage is applied to the primary circuit by the second drive signal turning on the second switch and the third switch in accordance with the second control signal, is generated in the secondary circuit of the transformer. The voltage generation circuit outputs the developed voltage to the developer, which is obtained by superimposing the AC voltage component generated in the secondary circuit of the transformer onto the DC voltage component output from the DC output circuit. Image forming apparatus.

2. The first control signal instructs the first switch and the fourth switch to turn on when the target voltage signal indicates a voltage higher than the detected voltage signal, and instructs the first switch and the fourth switch to turn off when the target voltage signal indicates a voltage lower than the detected voltage signal. The second control signal instructs the second and third switches to turn on when the target voltage signal is lower than the detected voltage signal, and instructs the second and third switches to turn off when the target voltage signal is higher than the detected voltage signal. The image forming apparatus according to claim 1.

3. The aforementioned control signal generation circuit is A feedback control circuit outputs a modulated voltage signal that is modulated so as to eliminate the deviation of the detected voltage signal relative to the target voltage signal, through feedback control based on the deviation of the detected voltage signal relative to the target voltage signal. A carrier wave generation circuit that generates a carrier signal having a frequency higher than the AC voltage component, A comparison circuit that generates the first control signal and the second control signal based on a comparison between the modulated voltage signal from the feedback control circuit and the carrier signal from the carrier wave generation circuit, The image forming apparatus according to claim 1, including the following:

4. The image forming apparatus according to claim 3, wherein the feedback control circuit applies at least proportional control and integral control to the deviation.

5. The first control signal instructs the first and fourth switches to turn on when the modulated voltage signal shows a voltage higher than the carrier signal, and instructs the first and fourth switches to turn off when the modulated voltage signal shows a voltage lower than the carrier signal. The second control signal instructs the second and third switches to turn on when the modulated voltage signal shows a voltage lower than the carrier signal, and instructs the second and third switches to turn off when the modulated voltage signal shows a voltage higher than the carrier signal. The image forming apparatus according to claim 3.

6. The image forming apparatus according to claim 3, wherein the carrier signal is a triangular wave.

7. The image forming apparatus according to claim 1, wherein the control circuit determines the target waveform in such a way that a decrease in the developing performance of the developing unit caused by a change in the operating conditions of the image forming apparatus is suppressed.

8. The image forming apparatus according to claim 1, wherein the first switch and the third switch of the H-bridge circuit are directly connected to the power supply without going through a voltage adjustment circuit.

9. The image forming apparatus according to claim 1, wherein the second switch and the fourth switch of the H-bridge circuit are grounded.

10. An image forming apparatus, An image carrier that carries an electrostatic latent image, A developing unit for developing the electrostatic latent image carried by the image carrier, A voltage generation circuit that generates a developing voltage to be applied to the developing unit, Equipped with, The voltage generation circuit is Transformer and An H-bridge circuit comprising a first switch and a second switch connected to the first terminal of the primary side circuit of the transformer, and a third switch and a fourth switch connected to the second terminal of the primary side circuit of the transformer, A power supply connected to the first switch and the third switch of the H-bridge circuit, A drive circuit that outputs a first drive signal for controlling the on / off state of the first switch and the fourth switch, and a second drive signal for controlling the on / off state of the second switch and the third switch, A DC output circuit that outputs a DC voltage component, Includes, The image forming apparatus is A control signal generation circuit reads from memory first waveform information defining the signal waveform of the first drive signal and second waveform information defining the signal waveform of the second drive signal, and outputs a first control signal generated according to the first waveform information and a second control signal generated according to the second waveform information to the drive circuit. Furthermore, The drive circuit generates a first drive signal by amplifying the first control signal, and generates a second drive signal by amplifying the second control signal. An AC voltage component having an amplitude dependent on the duty cycle of the time during which a positive voltage is applied to the primary circuit by the first drive signal turning on the first and fourth switches, and the time during which a negative voltage is applied to the primary circuit by the second drive signal turning on the second and third switches, is generated in the secondary circuit of the transformer. The voltage generation circuit outputs the developing voltage, which is obtained by superimposing the AC voltage component generated in the secondary circuit of the transformer onto the DC voltage component output from the DC output circuit, to the developing unit. The signal waveform defined by the first waveform information and the signal waveform defined by the second waveform information represent a pulse train for pulse width modulation at a frequency higher than the frequency of the AC voltage component over the entire period of the AC voltage component. Image forming apparatus.

11. The memory pre-stores multiple sets of the first waveform information and the second waveform information, each corresponding to a target waveform with a different development voltage. The control signal generation circuit selectively reads one of the plurality of sets of first waveform information and second waveform information, and generates the first control signal and second control signal according to the first waveform information and second waveform information of the read set, in order to suppress a decrease in the development performance of the developer due to changes in the operating conditions of the image forming apparatus. The image forming apparatus according to claim 10.

12. The image forming apparatus according to claim 10, wherein the first switch and the third switch of the H-bridge circuit are directly connected to the power supply without going through a voltage adjustment circuit.

13. The image forming apparatus according to claim 10, wherein the second switch and the fourth switch of the H-bridge circuit are grounded.

Images