LED display device and method for manufacturing the same

Abstract

To provide a display device that can improve process efficiency. [Solution] An embodiment of the Specified Display Device includes a substrate including a display area and a non-display area disposed on at least one side of the display area, a bending area between the display area and the non-display area, a plurality of insulating layers disposed on the substrate, a bank disposed on the plurality of insulating layers, and a first dam disposed in a dam area between the display area and the bending area, on which at least one microLED is disposed on the bank and an optical layer is disposed on the plurality of insulating layers, the first dam may include a first dam layer made of the same material as the bank.

Description

Technical Field

[0001] The present disclosure relates to an LED display device and a method for manufacturing the same, and more particularly, to an LED display device and a method for manufacturing the same that can improve the thickness change of an upper layer due to a step of an insulating film end portion in a bending region of a non-display region.

Background Art

[0002] In recent years, with the increase in the size of display devices, the demand for flat display elements with less space occupation has been increasing, and organic electroluminescent display (OLED) devices including liquid crystal display (LCD) devices or organic light emitting diodes (OLEDs) have been developing at a rapid pace in the technology of flat display devices.

[0003] In recent years, in order to overcome the above problems of liquid crystal display devices and / or organic light emitting display devices, LED display devices using LEDs (Light emitting diodes) as light emitting elements have been proposed. Miniature LEDs such as mini-LEDs or ultra-miniature LEDs such as micro-LEDs can be used in the LED display devices.

[0004] Such an LED display device is a display device that arranges ultra-small LEDs in the order of mini or micro in each sub-pixel to embody an image, and has great advantages in terms of low power consumption and miniaturization.

[0005] In such an LED display device, lower planarization is important for the arrangement of LEDs. An insulating layer formed of an organic substance can be arranged for lower planarization.

[0006] In the non-display region of the LED display device, the end region of the insulating layer is not flat, and the thickness gradually decreases, resulting in steps and thickness changes. Such steps and thickness changes at the end portion can also cause thickness changes in the upper layer.

[0007] A method is needed to prevent changes in the thickness of the upper layer due to such steps and thickness variations in the insulating film. [Overview of the project] [Problems that the invention aims to solve]

[0008] This disclosure aims to solve the aforementioned problems and improve process efficiency without using additional steps, while preventing changes in the thickness of the upper layer due to steps and thickness changes in the lower insulating film. [Means for solving the problem]

[0009] A display device according to one embodiment of the present disclosure includes a substrate including a display area and a non-display area disposed on at least one side of the display area, a bending area between the display area and the non-display area, a plurality of insulating layers disposed on the substrate, a bank disposed on the plurality of insulating layers, and a first dam disposed in a dam area between the display area and the bending area, on which at least one microLED is disposed on the bank and an optical layer is disposed on the plurality of insulating layers, the first dam may include a first dam layer made of the same material as the bank.

[0010] A display device according to one embodiment of the present disclosure includes a substrate including a display area, a non-display area disposed on at least one side of the display area, and a bending area between the display area and the non-display area; a plurality of insulating layers disposed on the substrate; a bank disposed on the plurality of insulating layers; and at least one microLED disposed on the bank; an optical layer disposed on the plurality of insulating layers; and at least one dam disposed in a dam area between the display area and the bending area, wherein the at least one dam may include a first dam layer made of the same material as the bank. [Effects of the Invention]

[0011] This disclosure makes it possible to improve the structural change characteristics of the upper layer due to steps and thickness changes at the end of the lower insulating film in the non-display area of ​​an LED display device.

[0012] This disclosure makes it possible to make the thickness of the upper layer, which is involved in light emission efficiency, uniform.

[0013] This disclosure makes it possible for the light emitted from the LEDs to be uniform in the central and outer parts of the display area.

[0014] The effects of this disclosure are not limited to those mentioned above, and any other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0015] [Figure 1] This is an exploded perspective view of a display device according to one embodiment of this specification. [Figure 2] This is a plan view of a display device according to one embodiment of this specification. [Figure 3] This is a plan view of the display device, enlarged from the three regions shown in Figure 2. [Figure 4] This is a plan view of the display device, enlarged from the four regions shown in Figure 2. [Figure 5] This is a plan view of a display device according to one embodiment of this specification. [Figure 6] This is an enlarged view of a light-emitting element according to one embodiment of this specification. [Figure 7] This is a cross-sectional view along line A-A' in Figure 3 relating to one embodiment of this specification. [Figure 8] This is a cross-sectional view along line A-A' in Figure 3 relating to one embodiment of this specification. [Figure 9] This is a cross-sectional view along line B-B' in Figure 4, relating to one embodiment of this specification. [Figure 10] This is a cross-sectional view along line C-C' in Figure 4 relating to another embodiment of this specification. [Figure 11] This is a plan view showing a display device according to an embodiment of this specification.

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] The advantages and features of this specification, and the method for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and is embodied in a variety of different forms. Merely, these embodiments are provided so that the disclosure of this specification becomes complete and so that those having ordinary knowledge in the technical field to which this specification pertains can be fully informed of the scope of the invention.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, and thus this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining this specification, if it is determined that a specific explanation of related known technologies may muddy the gist of this specification, the detailed explanation thereof will be omitted. When terms such as "including", "having", or "being made" mentioned in this specification are used, other parts can be added as long as terms such as "only" are not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0018] When interpreting a component, it is interpreted as including an error range even without a separate explicit description of the error range.

[0019] When it is an explanation of a positional relationship, for example, when the positional relationship between two parts is described such as "above", "on the upper part", "on the lower part", "next to", or "adjacent to", one or more other parts may be located between the two parts as long as terms such as "immediately", "directly", or "close" are not used.

[0020] When it is an explanation of a temporal relationship, for example, when the temporal precedence relationship is described such as "after", "subsequent to", "next", or "before", it may include the case where it is not continuous as long as terms such as "immediately" or "directly" are not used.

[0021] While terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0022] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component in question.

[0023] Where it is stated that one component is “connected,” “joined,” “attached,” or “pasted” to another component, it should be understood that the component may be directly connected, joined, attached, or pasted to the other component, but other components may be interposed between each component that may be indirectly connected, joined, attached, or pasted unless otherwise explicitly stated.

[0024] Where it is stated that a component or layer "contacts" or "overlays" another component or layer, it should be understood that the component or layer may directly contact or overlap with another component or layer, but other components may be interposed between each component that may indirectly contact or overlap, unless otherwise explicitly stated.

[0025] "At least one" should be understood to include all combinations of one or more related components. For example, "at least one of the first, second, and third components" means not just the first, second, or third component, but all combinations of two or more of the first, second, and third components.

[0026] The terms "first direction," "second direction," "third direction," and "axial direction" should not be interpreted solely as geometric relationships where the relationships are perpendicular to each other, but may mean that there are broader directions within the scope in which the configuration of this specification can function.

[0027] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0028] Various embodiments of this specification will be described in detail below with reference to the attached drawings.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment of this specification. Figure 2 is a plan view of the display device according to one embodiment of this specification. Figures 3 and 4 are enlarged views of the display device according to one embodiment of this specification.

[0030] Referring to Figures 1 to 4, a display device 1000 according to one embodiment of this specification may include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 200, a support substrate 300, a ductile circuit board 400, and a printed circuit board 500. The cover member 200 can be attached to the display panel 100 using the adhesive layer 295. The adhesive layer 295 may also be placed between the display panel 100 and the polarizing layer 293, or between the display panel 100 and the support substrate 300.

[0031] The adhesive layer 295 may include, but is not limited to, an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive (PSA).

[0032] For example, the display panel 100 of the display device 1000 may include a substrate 110. The substrate 110 may be a member that supports other components of the display device 1000. The substrate 110 may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also be made of a flexible material. For example, the substrate 110 may be made of a flexible plastic material such as polyimide (PI). However, the examples in this specification are not limited thereto.

[0033] The display panel 100 can embody information, video, and / or images provided to the user. For example, the display panel 100 may include a display area AA and a non-display area NA. For example, the substrate 110 may include a display area AA and a non-display area NA. The display area AA and non-display area NA are not limited to the substrate 110, but may be described in relation to the display device 1000 in general.

[0034] Display area AA may be the area where the image is displayed. Display area AA may contain multiple pixels PX. Each of the multiple pixels PX may consist of multiple subpixels. Each of the multiple subpixels may have multiple microLEDs arranged around it. The multiple microLEDs may be configured differently depending on the type of display device 1000.

[0035] The non-display area NA may be an area where no image is displayed. Various wirings and circuits for driving multiple pixels PX of the display area AA may be arranged in the non-display area NA. For example, various wirings and drive circuits may be mounted in the non-display area NA, and a pad portion PAD to which integrated circuits and printed circuits are connected may be arranged, but the embodiments of this specification are not limited thereto.

[0036] For example, the drive circuit may be a data drive circuit and / or a gate drive circuit, but the embodiments herein are not limited thereto. Wiring may be provided to supply control signals for controlling the drive circuit. For example, the control signals may include various timing signals, including a clock signal, an input data enable signal, and a synchronization signal, but the embodiments herein are not limited thereto. The control signals may be received through a pad section PAD. For example, a link wiring LL for transmitting signals may be provided in a non-display area NA. For example, drive components such as a ductile circuit board 400 and a printed circuit board 500 may be connected to the pad section PAD.

[0037] According to this specification, the non-display area NA may include a first non-display area NA1, a bending area BA, and a second non-display area NA2. For example, the first non-display area NA1 may be an area surrounding at least a portion of the display area AA. The bending area BA is an area extending from at least one of the multiple sides of the first non-display area NA1 and may be a bendable area. The second non-display area NA2 is an area extending from the bending area BA and may have a pad portion PAD. For example, the bending area BA may be in a bent state, and the remaining area of ​​the substrate 110 excluding the bending area BA may be in a flat state. In this case, the bending of the bending area BA may cause the second non-display area NA2 to be located on the back surface of the display area AA. However, the embodiments of this specification are not limited thereto.

[0038] The display area AA of the substrate 110 or the display device 1000 can be configured in various shapes depending on the design of the display device 1000. For example, the display area AA may be configured in a rectangular shape with rounded corners, but the embodiments described herein are not limited to this. To give other examples, the display area AA may be configured in a rectangular shape with right-angled corners, a circular shape, etc., but the embodiments described herein are not limited to these.

[0039] According to this specification, the width of the second non-display area NA2, where multiple pad electrodes PE are arranged, may be wider than the width of the bending area BA, where only multiple link wirings LL are arranged. Similarly, the width of the display area AA, where multiple subpixels are arranged, may be wider than the width of the bending area BA, where only multiple link wirings LL are arranged. In the drawings, the width of the bending area BA is shown to be narrower than the width of other areas of the substrate 110, but the shape of the substrate 110 including the bending area BA is illustrative, and the embodiments described herein are not limited thereto.

[0040] Referring to Figure 4, multiple pixel driver circuits PD can be arranged in display area AA. The multiple pixel driver circuits PD may be circuits for driving multiple sub-pixel micro-LEDs. Each of the multiple pixel driver circuits PD includes multiple transistors, including a drive transistor, and a storage capacitor, and can supply control signals, power, and drive current to the multiple sub-pixel micro-LEDs to control the light emission operation of the multiple micro-LEDs. For example, the pixel driver circuit PD may include power supply wiring and signal wiring for controlling the on / off and / or light emission time of the micro-LEDs. For example, the multiple pixel driver circuits PD may be drive drivers manufactured on a semiconductor substrate using a MOSFET (Metal-oxide-silicon field effect transistor) manufacturing process, but the embodiments described herein are not limited thereto. A drive driver includes multiple pixel driver circuits PD and can drive multiple sub-pixels.

[0041] Referring together with Figure 1, a ductile circuit board 400 and a printed circuit board 500 may be arranged at the bottom of the display panel 100. The ductile circuit board 400 and the printed circuit board 500 may be arranged at least on one side edge of the display panel 100, but the embodiments herein are not limited thereto.

[0042] A pad section PAD containing multiple pad electrodes PE may be arranged in the second non-display area NA2. A drive component including one or more ductile circuit boards (or flexible films) 400 and printed circuit boards 500 may be attached to or bonded to the pad section PAD. The multiple pad electrodes PE of the pad section PAD are electrically connected to one or more ductile circuit boards (or flexible films) 400, and can transmit various signals (or power) from the printed circuit boards 500 and ductile circuit boards (or flexible films) 400 to multiple pixel drive circuits PD in the display area AA.

[0043] The ductile circuit board (or flexible film) 400 may be a film in which various components are arranged on a ductile base film. For example, a drive IC such as a gate driver IC or a data driver IC may be arranged on the ductile circuit board (or flexible film) 400, but the embodiments herein are not limited thereto.

[0044] The printed circuit board 500 may include at least one hole 510, but the embodiments herein are not limited thereto. An internal component that senses ambient light or temperature, etc., which can be supplied to multiple sensors, may be arranged in the area corresponding to at least one hole 510. For example, the internal component may include an ambient light sensor (ALS) or a temperature sensor, but the embodiments herein are not limited thereto. For example, the hole 510 may be a transparent hole, but the embodiments herein are not limited thereto.

[0045] Referring to Figures 1 to 3, multiple link wirings LL may be arranged in the non-display area NA. The multiple link wirings LL may be wirings that transmit various signals from one or more ductile circuit boards (or flexible films) 400 and printed circuit boards 500 to the display area AA. The multiple link wirings LL may extend from multiple pad electrodes PE in the second non-display area NA2 toward the bending area BA and the first non-display area NA1 and be electrically connected to multiple drive wirings VL in the display area AA.

[0046] Multiple drive wirings VL can be arranged in the display area AA and electrically connected to each of the multiple pixel drive circuits PD.

[0047] When the bending region BA is bent, a portion of the multiple link wirings LL may also be bent. Stress may concentrate on the bent portion of the link wirings LL, which may cause cracks to form in the link wirings LL. Therefore, the multiple link wirings LL may be made of a highly ductile conductive material to reduce cracking when the bending region BA is bent. For example, the multiple link wirings LL may be made of a highly ductile conductive material such as gold (Au), silver (Ag), or aluminum (Al), but the embodiments described herein are not limited to these. Furthermore, the multiple link wirings LL may be made of one of the various conductive materials used in the display region AA. For example, the multiple link wirings LL may be made of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg), or alloys thereof, but the embodiments described herein are not limited to these. The multiple link wirings LL may be made of a multilayer structure containing various conductive materials. For example, multiple link wirings LL may be constructed in a triple-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments described herein are not limited thereto.

[0048] Figures 4 to 10 are plan views and cross-sectional views of a display device according to one embodiment of this specification.

[0049] For example, Figure 4 is an enlarged plan view of a display area containing multiple pixels. For example, Figure 5 is an enlarged plan view of a display area containing a single pixel. Figure 6 is an enlarged cross-sectional view of a microLED area, Figure 7 is a cross-sectional view along line A-A' in Figure 3 according to one embodiment of this specification, and Figure 8 is a cross-sectional view along line A-A' in Figure 3 according to another embodiment of this specification.

[0050] Figures 4 and 5 show multiple signal lines TL, multiple communication lines NL, multiple first electrodes CE1, multiple contact electrodes CCE, multiple banks BNK, multiple micro-LEDEDs, and second electrodes CE2, but the embodiments described herein are not limited thereto.

[0051] Referring to Figures 4 and 5, multiple pixels PX, each composed of multiple subpixels, can be arranged in the display area AA. Each of the multiple subpixels includes a micro-LEDED and can emit light independently. The multiple subpixels can be arranged in a matrix configuration with multiple rows and multiple columns, but the embodiments herein are not limited to this.

[0052] Each of the multiple pixels PX may include one or more first subpixels SP1, one or more second subpixels SP2, and one or more third subpixels SP3. For example, one pixel PX may include a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3. A pair of first subpixels SP1 may consist of a 1-1 subpixel SP1a and a 1-2 subpixel SP1b. A pair of second subpixels SP2 may consist of a 2-1 subpixel SP2a and a 2-2 subpixel SP2b. A pair of third subpixels SP3 may consist of a 3-1 subpixel SP3a and a 3-2 subpixel SP3b. For example, one pixel PX may include a 1-1 subpixel SP1a and a 1-2 subpixel SP1b, a 2-1 subpixel SP2a and a 2-2 subpixel SP2b, and a 3-1 subpixel SP3a and a 3-2 subpixel SP3b, but the embodiments herein are not limited thereto.

[0053] Multiple subpixels constituting a single pixel PX can be arranged in various ways. For example, in a single pixel PX, a pair of first subpixels SP1 may be arranged in the same column, a pair of second subpixels SP2 in the same column, and a pair of third subpixels SP3 in the same column. The first subpixels SP1, the second subpixels SP2, and the third subpixels SP3 may be arranged in the same row. The number and arrangement of multiple subpixels constituting a single pixel PX are exemplary, and the embodiments herein are not limited thereto.

[0054] Multiple signal lines TL may be arranged in the region between multiple subpixels. Multiple signal lines TL may extend in the column direction between multiple subpixels. Multiple signal lines TL may be lines that transmit the anode voltage from a pixel drive circuit PD to multiple subpixels. For example, multiple signal lines TL may be electrically connected to multiple pixel drive circuits PD and multiple first electrodes CE1 of multiple subpixels. The anode voltage output by the pixel drive circuit PD can be transmitted to the multiple first electrodes CE1 of multiple subpixels through the multiple signal lines TL. For example, the first electrode CE1 may be an electrode electrically connected to the anode electrode 134 of a micro-LEDED. Thus, the anode voltage from the signal lines TL can be transmitted to the anode electrode 134 of the micro-LEDED through the first electrode CE1.

[0055] Multiple signal lines TL may include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. The first signal line TL1 and the second signal line TL2 may each be electrically connected to a pair of first subpixels SP1. The third signal line TL3 and the fourth signal line TL4 may each be electrically connected to a pair of second subpixels SP2. The fifth signal line TL5 and the sixth signal line TL6 may each be electrically connected to a pair of third subpixels SP3.

[0056] A first signal wiring TL1 may be located on one side of a pair of first subpixels SP1, and a second signal wiring TL2 may be located on the other side of the pair of first subpixels SP1. The first signal wiring TL1 may be electrically connected to the first electrode CE1 of one of the pair of first subpixels SP1, for example, the 1-1 subpixel SP1a. The second signal wiring TL2 may be electrically connected to the first electrode CE1 of the remaining first subpixel SP1 of the pair, for example, the 1-2 subpixel SP1b.

[0057] A third signal wiring TL3 may be located on one side of a pair of second subpixels SP2, and a fourth signal wiring TL4 may be located on the other side of the pair of second subpixels SP2. For example, the third signal wiring TL3 may be located adjacent to the second signal wiring TL2. The third signal wiring TL3 may be electrically connected to the first electrode CE1 of one of the second subpixels SP2 of the pair, for example, subpixel 2-1 SP2a. The fourth signal wiring TL4 may be electrically connected to the first electrode CE1 of the remaining second subpixel SP2 of the pair, for example, subpixel 2-2 SP2b.

[0058] A fifth signal wiring TL5 may be located on one side of a pair of third subpixels SP3, and a sixth signal wiring TL6 may be located on the other side of the pair of third subpixels SP3. For example, the fifth signal wiring TL5 may be located adjacent to the fourth signal wiring TL4. The sixth signal wiring TL6 may be located adjacent to the first signal wiring TL1 connected to an adjacent pixel PX. The fifth signal wiring TL5 may be electrically connected to the first electrode CE1 of one of the pair of third subpixels SP3, for example, the 3-1 subpixel SP3a. The sixth signal wiring TL6 may be electrically connected to the first electrode CE1 of the remaining third subpixel SP3 of the pair, for example, the 3-2 subpixel SP3b.

[0059] Multiple signal lines TL may consist of conductive materials. For example, multiple signal lines TL may consist of single or multilayer structures of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the examples herein are not limited to these.

[0060] Multiple communication lines NL may be arranged in the region between multiple pixels PX. Multiple communication lines NL may extend in the row direction from the region between the multiple pixels PX. Multiple communication lines NL may be arranged in the region between multiple second electrodes CE2 and may not superimpose on the multiple second electrodes CE2. For example, multiple communication lines NL may be lines used for short-range communication such as NFC (Near Field Communication). Multiple communication lines NL may function as antennas. For example, multiple communication lines NL may be multiple connection lines, etc., but the embodiments herein are not limited thereto.

[0061] According to this specification, a bank BNK may be arranged for each of a plurality of subpixels. The plurality of bank BNKs may be structures on which a plurality of microLEDEDs are attached. The plurality of bank BNKs can guide the position of the plurality of microLEDEDs in a transfer step of transferring the plurality of microLEDEDs to the display device 1000. The plurality of microLEDEDs may be transferred onto the plurality of bank BNKs in the transfer step of the plurality of microLEDEDs. The plurality of bank BNKs may be a bank pattern or a structure, etc., but the embodiments herein are not limited thereto.

[0062] The bank BNK of the first subpixel SP1, the bank BNK of the second subpixel SP2, and the bank BNK of the third subpixel SP3 may be arranged spaced apart from each other. The bank BNK of the first subpixel SP1, the bank BNK of the second subpixel SP2, and the bank BNK of the third subpixel SP3 may be configured to be separated. Thus, the bank BNKs of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, to which different types of microLEDEDs are transferred, can be easily identified.

[0063] For example, multiple bank BNKs may consist of organic insulating materials. Multiple bank BNKs may consist of single or multilayer organic insulating materials. For example, multiple bank BNKs may consist of photoresist, polyimide (PI), or acrylic-based materials, but the examples herein are not limited to these.

[0064] A first electrode CE1 may be placed on each of multiple subpixels. The first electrode CE1 may be placed on a bank BNK. For example, each first electrode CE1 may be placed on the top and side surfaces of multiple banks BNK.

[0065] At least a portion of the first electrode CE1 may extend outside the bank BNK and be electrically connected to the signal wiring TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of the first-1 subpixel SP1a may extend to one side of the first-1 subpixel SP1a and be electrically connected to the first signal wiring TL1, and a portion of the first electrode CE1 of the first-2 subpixel SP1b may extend to the other side of the first-2 subpixel SP1b and be electrically connected to the second signal wiring TL2.

[0066] The first electrode CE1 is electrically connected to the anode electrode 134 of the micro-LEDED and can transmit the anode voltage from the pixel driving circuit PD to each of the multiple sub-pixels via the signal wiring TL. Different voltages may be applied to the first electrode CE1 of each of the multiple sub-pixels depending on the displayed image. For example, different voltages may be applied to the first electrode CE1 of each of the multiple sub-pixels. Therefore, the first electrode CE1 may be a pixel electrode, and the embodiments described herein are not limited thereto.

[0067] The multiple micro-LEDEDs may include a first micro-LED 130, a second micro-LED 140, and a third micro-LED 150. The first micro-LED 130 may be located in a first sub-pixel SP1. The second micro-LED 140 may be located in a second sub-pixel SP2. The third micro-LED 150 may be located in a third sub-pixel SP3. For example, one of the first micro-LED 130, the second micro-LED 140, and the third micro-LED 150 may be a red micro-LED, another may be a green micro-LED, and the rest may be blue micro-LEDs, but the embodiments herein are not limited thereto. Thus, by combining the red, green, and blue light emitted by the multiple micro-LEDEDs, a variety of hues of light, including white, can be realized. The types of multiple micro-LEDEDs are illustrative, and the embodiments herein are not limited thereto.

[0068] A second electrode CE2 may be placed on each of the multiple subpixels. The second electrode CE2 may be placed on a micro-LEDED. The second electrode CE2 may be electrically connected to the pixel drive circuit PD through multiple contact electrodes CCE.

[0069] For example, the second electrode CE2 is electrically connected to the cathode electrode 135 of the micro-LEDED and can transmit the cathode voltage from the pixel driving circuit PD to the micro-LEDED. The same cathode voltage may be applied to the second electrode CE2 of each of the multiple sub-pixels. For example, the same voltage may be applied to the second electrode CE2 of each of the multiple sub-pixels and the cathode electrode 135 of the micro-LEDED. Therefore, the second electrode CE2 may be a common electrode, but the embodiments described herein are not limited to this.

[0070] At least some of the subpixels may share the second electrode CE2. At least some of the second electrode CE2 of each of the subpixels may be electrically connected to one another. By applying the same voltage to the second electrode CE2, at least some of the subpixels may share and use the second electrode CE2. For example, the second electrode CE2 of at least some of the pixels PX arranged in the same row may be connected to one another. For example, one second electrode CE2 may be placed on multiple pixels PX. One second electrode CE2 may be placed for every n subpixels.

[0071] For example, some of the second electrodes CE2 of each of multiple subpixels may be arranged separately from each other. For instance, the second electrode CE2 connected to the pixel PX of the nth row and the second electrode CE2 connected to the pixel PX of the (n+1)th row may be arranged separately from each other. For example, multiple second electrodes CE2 may be arranged separately from each other, separated by multiple communication lines NL extending in the row direction.

[0072] Multiple second electrodes CE2 are made of a transparent conductive material, and light emitted by the micro-LEDED can be directed towards the top of the second electrodes CE2. For example, the second electrodes CE2 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), but the examples herein are not limited to these.

[0073] Multiple contact electrodes CCE can be arranged on the substrate 110. For example, multiple contact electrodes CCE can be arranged spaced apart from multiple banks BNK and multiple signal lines TL. Each of the multiple second electrodes CE2 can be superimposed on at least one contact electrode CCE. For example, one second electrode CE2 can be superimposed on multiple contact electrodes CCE.

[0074] For example, multiple contact electrodes CCE can be electrically connected to multiple second electrodes CE2. Multiple contact electrodes CCE can be positioned between the substrate 110 and the multiple second electrodes CE2, and can transmit the cathode voltage from the pixel driving circuit PD to the second electrodes CE2.

[0075] When using microLEDs as microLEDEDs, the display device 1000 can be manufactured by forming multiple microLEDs on a wafer and transferring the microLEDs to the substrate 110 of the display device 1000. Various defects may occur during the process of transferring multiple microLEDEDs of a fine size from the wafer to the substrate 110. For example, in some subpixels, a non-transfer defect may occur where the microLEDED is not transferred, and in other subpixels, a defect may occur where the microLEDED is transferred outside its designated position due to alignment errors. Also, even if the transfer process proceeds normally, the transferred microLEDED itself may be defective. Therefore, considering defects during the transfer process of multiple microLEDEDs, multiple microLEDEDs emitting light of the same hue can be transferred to a single subpixel. The lighting inspection of the multiple microLEDEDs can be carried out, and only the one microLEDED that is ultimately judged to be normal can be used.

[0076] For example, both the 1-1 microLED 130a and the 1-2 microLED 130b can be transferred to a single pixel PX, and their defects can be checked. If both the 1-1 microLED 130a and the 1-2 microLED 130b are determined to be normal, only the 1-1 microLED 130a can be used, and the 1-2 microLED 130b does not need to be used. Therefore, even if multiple microLEDs emitting light of the same hue are transferred to a single pixel PX, ultimately only one microLED may be used.

[0077] Therefore, one of the pair of micro-LEDEDs may be the main (or primary) micro-LEDED, and the remaining micro-LEDED may be a redundant micro-LEDED. The redundant micro-LEDED may be an extra micro-LEDED transferred in case of failure of the main micro-LEDED. When the main micro-LEDED fails, the redundant micro-LEDED can be used as a substitute. Thus, by transferring both the main micro-LEDED and the redundant micro-LEDED to a single pixel PX, the degradation of display quality due to failure of the main micro-LEDED and the redundant micro-LEDED can be minimized.

[0078] Ultimately, a black matrix BM can be formed in the display area AA and non-display area NA of a redundant micro-LEDED or main micro-LEDED, excluding the light-emitting area of ​​the micro-LED used in each subpixel, thereby preventing light emitted from micro-LEDs not used in each subpixel from being emitted upwards.

[0079] Figure 6 is an enlarged view of a light-emitting element according to one embodiment of this specification. Referring to Figure 6, the first micro-LED 130, which is a light-emitting element, may include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and a sealing film 136, but the embodiments of this specification are not limited thereto. For example, the sealing film 136 may not be included in the first micro-LED 130.

[0080] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may be embodied in a compound semiconductor such as a III-V or II-VI semiconductor, and may be doped with an impurity (or dopant). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may be a semiconductor layer doped with an n-type impurity, and the other may be a semiconductor layer doped with a p-type impurity, but the examples of this specification are not limited thereto. For example, one or more of the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type or p-type impurities in substances such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but the examples of this specification are not limited thereto.

[0081] The active layer 132 may be disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may be configured as one of a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum beam structure, but the examples herein are not limited thereto. For example, the active layer 132 may be composed of indium gallium nitride (InGaN) or gallium nitride (GaN), but the examples herein are not limited thereto.

[0082] An anode electrode 134 may be positioned below the first semiconductor layer 131. The anode electrode 134 may be composed of a conductive material capable of eutectic bonding with the solder pattern SDP. For example, the anode electrode 134 may be composed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or alloys thereof, but the examples herein are not limited thereto.

[0083] The cathode electrode 135 may be located on the second semiconductor layer 133. For example, the cathode electrode 135 may electrically connect the second semiconductor layer 133 and the second electrode CE2. The cathode voltage output by the pixel driving circuit PD may be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 may be made of a transparent conductive material so that light emitted by the micro-LEDED can be directed towards the top of the micro-LEDED, but the embodiments herein are not limited thereto. For example, the cathode electrode 135 may be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), but the embodiments herein are not limited thereto. The encapsulation film 136 may be placed on at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 may surround at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0084] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 may be placed on the sides of the first semiconductor layer 131, the sides of the active layer 132, and the sides of the second semiconductor layer 133. For example, the encapsulation film 136 may consist of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but the examples herein are not limited thereto.

[0085] Figure 7 is a cross-sectional view along line A-A' in Figure 3. Figure 7 is a cross-sectional view of the display area AA, dam area DA, first non-display area NA1, bending area BA, and second non-display area NA2 according to one embodiment of this specification.

[0086] On the other hand, for illustrative purposes, Figure 3 shows that the cutting line A-A' does not overlap with the drive wiring VL and link wiring LL. However, the cutting line A-A' in Figure 3 is intended to indicate the same position as the adjacent drive wiring VL and link wiring LL.

[0087] Referring to Figure 7, the first buffer layer 111a and the second buffer layer 111b may be arranged in the remaining area of ​​the substrate 110 excluding the bending region BA.

[0088] The first buffer layer 111a and the second buffer layer 111b may be arranged in the display area AA, the dam area DA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b may consist of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments herein are not limited thereto.

[0089] For example, portions of the first buffer layer 111a and the second buffer layer 111b located on the bending region BA may be removed. The upper surface of the substrate 110 located in the bending region BA may be exposed from the first buffer layer 111a and the second buffer layer 111b. By removing the first buffer layer 111a and the second buffer layer 111b, which are made of inorganic insulating material, in the bending region BA, cracks in the first buffer layer 111a and the second buffer layer 111b that may occur during bending can be minimized.

[0090] Multiple alignment keys MK may be placed between the first buffer layer 111a and the second buffer layer 111b. These multiple alignment keys MK may be configured to identify the position of the pixel drive circuit PD during the manufacturing process of the display device 1000. For example, they may be configured to align the positions of the pixel drive circuit PD transferred onto the adhesive layer 112. Alternatively, the multiple alignment keys MK may be omitted.

[0091] An adhesive layer 112 may be placed on the second buffer layer 111b. The adhesive layer 112 may be placed in the display area AA and the dam area DA, the first non-display area NA1, the bending area BA, and the second non-display area NA2. To give another example, at least a portion of the adhesive layer 112 may be removed in the non-display area NA, which includes the bending area BA. For example, the adhesive layer 112 may consist of one of the following: an adhesive polymer, an epoxy resin, a UV-curable resin, a polyimide series, an acrylate series, a urethane series, and polydimethylsiloxane (PDMS), but the examples herein are not limited to these.

[0092] A pixel drive circuit PD may be placed on the adhesive layer 112 in the display area AA. When the pixel drive circuit PD is embodied in a drive driver, the drive driver may be mounted on the adhesive layer 112 by a transfer process, but the embodiments herein are not limited thereto.

[0093] The first protective layer 113a and the second protective layer 113b may be arranged on the adhesive layer 112 and the upper or side surface of the pixel drive circuit PD. The first protective layer 113a and the second protective layer 113b may be arranged to surround the side surface of the pixel drive circuit PD, but the embodiments herein are not limited thereto. For example, the second protective layer 113b may be arranged to cover at least a portion of the upper surface of the pixel drive circuit PD.

[0094] For example, at least one of the first protective layer 113a and the second protective layer 113b, which are located on the bending region BA, may be omitted. For example, the first protective layer 113a may be located entirely on the display region AA, the dam region DA, and the non-display region NA, while the second protective layer 113b may be located partially on the display region AA, the dam region DA, the first non-display region NA1, and the second non-display region NA2. For example, a portion of the second protective layer 113b located on the bending region BA may be removed. However, the embodiments of this specification are not limited thereto.

[0095] The first protective layer 113a and the second protective layer 113b may be composed of an organic insulating material, but the examples herein are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be an overcoating layer or an insulating layer, but the examples herein are not limited thereto.

[0096] According to this specification, a plurality of first connection wires 121 may be arranged on the second protective layer 113b in the display area AA. The plurality of first connection wires 121 may be wires for electrically connecting the pixel drive circuit PD to other components. For example, the pixel drive circuit PD may be electrically connected to a plurality of signal wires TL and a plurality of contact electrodes CCE, etc., through the plurality of first connection wires 121. For example, the plurality of first connection wires 121 may include a 1-1 connection wire 121a, a 1-2 connection wire 121b, a 1-3 connection wire 121c, and a 1-4 connection wire 121d, and the 1-1 connection wire 121a, a 1-2 connection wire 121b, a 1-3 connection wire 121c, and a 1-4 connection wire 121d may be electrically connected through contact holes formed in the insulating layer between each connection wire, but the embodiments herein are not limited thereto. Each of the multiple first connection lines 121 is a line that points to a signal line located on the same layer, and the multiple first connection lines 121 may include signal lines to which different signals are applied.

[0097] For example, a third protective layer 114 may be placed on the second protective layer 113b. The third protective layer 114 may be placed entirely over the display area AA, the dam area DA, and the non-display area NA.

[0098] In the bending region BA, the third protective layer 114 can cover or overlap the sides of the second protective layer 113b and the top surface of the first protective layer 113a. The third protective layer 114 may be composed of an organic insulating material. For example, the third protective layer 114 may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 may be composed of the same material, but the examples herein are not limited thereto.

[0099] A plurality of first-to-second connection wirings 121b may be arranged on the third protective layer 114, and a first insulating layer 115a may be arranged on the plurality of first-to-second connection wirings 121b. The first insulating layer 115a may be arranged entirely over the display area AA and the non-display area NA, but the embodiments herein are not limited thereto. The first insulating layer 115a may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the first insulating layer 115a may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0100] Multiple first- to third connection wires 121c may be arranged on the first insulating layer 115a. Multiple first- to third connection wires 121c may be electrically connected to multiple first- to second connection wires 121b. For example, the first- to third connection wires 121c may be electrically connected to the first- to second connection wires 121b through contact holes in the first insulating layer 115a.

[0101] A second insulating layer 115b may be placed on a plurality of first-to-third connection wirings 121c. The second insulating layer 115b may be placed in the remaining area excluding the bending area BA, but the embodiments herein are not limited thereto. The second insulating layer 115b may be placed in the display area AA, the first non-display area NA1, and the second non-display area NA2, but the embodiments herein are not limited thereto. For example, a portion of the second insulating layer 115b placed in the bending area BA may be removed. The second insulating layer 115b may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the second insulating layer 115b may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0102] Multiple first- to fourth connection wires 121d may be arranged on the second insulating layer 115b. Multiple first- to fourth connection wires 121d may be electrically connected to multiple first- to third connection wires 121c. For example, the first- to fourth connection wires 121d may be electrically connected to the first- to third connection wires 121c through contact holes in the second insulating layer 115b.

[0103] Multiple signal lines TL may be arranged on the third insulating layer 115c in display area AA. Multiple signal lines TL may extend into areas between multiple banks BNK. For example, multiple signal lines TL may be arranged adjacent to any one of the multiple banks BNK.

[0104] According to this specification, a plurality of second connection lines 122 may be arranged on the second protective layer 113b in the non-display area NA. The plurality of second connection lines 122 may be wiring for transmitting signals transmitted to the pad portion PAD on the ductile circuit board (or flexible film) 400 and the printed circuit board 500 (see Figure 1) to the pixel driving circuit PD of the display area AA. For example, the plurality of second connection lines 122 may be electrically connected to a plurality of pad electrodes PE and be able to receive signals applied from the ductile circuit board (or flexible film) 400 and the printed circuit board 500.

[0105] For example, multiple second connection wires 122 may extend from the pad portion PAD toward the display area AA and transmit signals to the wiring of the display area AA. In this case, the multiple second connection wires 122 may function as link wires LL. The multiple second connection wires 122 may include 2-1 connection wires 122a, 2-2 connection wires 122b, 2-3 connection wires 122c, and 2-4 connection wires 122d. Thus, signals from the ductile circuit board (or flexible film) 400 and the printed circuit board 500 may be transmitted to the 2-1 connection wire 122a through the 2-4 connection wires 122d, 2-3 connection wires 122c, and 2-2 connection wires 122b.

[0106] The multiple first connecting wires 121 and the multiple second connecting wires 122 may be formed from either a conductive material with excellent ductility or one of a variety of conductive materials used in the display area AA.

[0107] For example, the multiple first connecting wires 121 and the multiple second connecting wires 122 may be composed of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of silver (Ag) and magnesium (Mg), or alloys thereof, but the embodiments herein are not limited thereto.

[0108] A third insulating layer 115c may be placed on a plurality of first connection wires 121 and a plurality of second connection wires 122. The third insulating layer 115c may be placed in the remaining area excluding the bending area BA, but the embodiments herein are not limited thereto. The third insulating layer 115c may be placed in the display area AA, the dam area DA, the first non-display area NA1, and the second non-display area NA2. A portion of the third insulating layer 115c in the bending area BA may be removed. The third insulating layer 115c may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the third insulating layer 115c may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0109] In the bending region BA, the substrate 110 is bent, and the second non-display region NA2 may overlap the display region AA in at least a portion. In order for the substrate 110 to be bent, the layers placed on the substrate 110 may be minimized to prevent the occurrence of cracks. Therefore, it is not necessary to form the first buffer layer 111a, the second buffer layer 111b, the second protective layer 113b, the second insulating layer 115b, or the third insulating layer 115c in the bending region BA, but the embodiments of this specification are not limited thereto.

[0110] For example, when patterning is performed so that the ends of a first buffer layer 111a, second buffer layer 111b, second protective layer 113b, second insulating layer 115b, or third insulating layer 115c, which may be formed of an organic material, do not form in the bending region BA, the thickness of the patterned ends of the first buffer layer 111a, second buffer layer 111b, second protective layer 113b, second insulating layer 115b, or third insulating layer 115c can be changed in terms of step and thickness, such that the thickness of the patterned ends gradually decreases towards the ends compared to the thickness of the layers located on the display region side.

[0111] As a result, the adhesive layer 112, the first protective layer 113a, the first insulating layer 115a, and the third insulating layer 115c, which are positioned below or above the first buffer layer 111a, the second buffer layer 111b, the second protective layer 113b, the second insulating layer 115b, or the third insulating layer 115c, may tilt with an angle of inclination as they approach the bending region along the decreasing thickness of the lower layers.

[0112] Multiple banks BNK may be arranged on the third insulating layer 115c in display area AA. Multiple banks BNK may be arranged so as to superimpose on each of multiple subpixels. One or more micro-LEDEDs emitting light of the same hue may be placed on top of each of the multiple banks BNK.

[0113] Multiple bank BNKs may consist of photoresists, polyimides (PI), or photoacrylic materials, but the examples herein are not limited to these.

[0114] The dam region DA is located between the display region AA and the bending region BA, and more specifically, it may be located between the display region AA and the first non-display region NA1. The dam region DA may include a portion inclined along the slope of the lower insulating layer, and the embodiments herein are not limited thereto.

[0115] A first dam (DAM) may be located in the dam region (DA). The first dam (DAM) may include a first dam layer (301) formed from the same material and using the same process as the multiple banks (BNK). The multiple banks (BNK) and the first dam layer (301) may be formed to have different heights and widths through a half-tone mask process. The height of the first dam layer (301) may be greater than that of the multiple banks (BNK), and the width of the first dam layer (301) may be greater than that of the multiple banks (BNK), but the embodiments herein are not limited thereto.

[0116] Multiple contact electrodes CCE may be arranged on the third insulating layer 115c in the display area AA. The multiple contact electrodes CCE can supply the cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0117] A first electrode CE1 may be positioned on bank BNK. For example, the first electrode CE1 may extend from an adjacent signal trace TL toward the top of bank BNK. The first electrode CE1 may be positioned on the top surface and the side surface of bank BNK. For example, the first electrode CE1 may extend from a signal trace TL on the top surface of the third insulating layer 115c toward the side surface and the top surface of bank BNK.

[0118] The first electrode CE1 may be composed of multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but the examples herein are not limited thereto.

[0119] The first conductive layer CE1a may be placed on bank BNK. The second conductive layer CE1b may be placed on the first conductive layer CE1a. The third conductive layer CE1c may be placed on the second conductive layer CE1b. The fourth conductive layer CE1d may be placed on the third conductive layer CE1c. For example, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d may each be composed of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but the examples herein are not limited thereto.

[0120] According to this specification, some of the conductive layers constituting the first electrode CE1 that have good reflective efficiency may be configured as alignment keys and / or reflectors for aligning the micro-LEDEDs.

[0121] For example, in order to configure the second conductive layer CE1b as a reflector, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b may be partially removed or etched. For example, the upper surface of the second conductive layer CE1b may be exposed by removing or etching a portion of the third conductive layer CE1c and the fourth conductive layer CE1d located on the bank BNK. For example, the central portion and frame portion (or edge portion) of the third conductive layer CE1c and the fourth conductive layer CE1d where the solder pattern SDP is located may be left intact, and the remaining portion may be removed. For example, the frame portion (or edge portion) of the third conductive layer CE1c, which is made of titanium (Ti), and the fourth conductive layer CE1d, which is made of indium tin oxide (ITO), do not need to be etched. This prevents corrosion of other conductive layers of the first electrode CE1 by the TMAH (TetraMethylAmmoniumHydroxide) solution used in the masking process of the first electrode CE1.

[0122] According to this specification, the first conductive layer CE1a and the third conductive layer CE1c may contain titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may contain aluminum (Al). The fourth conductive layer CE1d may contain a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) which has good adhesion to the solder pattern SDP and is corrosion-resistant and acid-resistant. However, the examples herein are not limited thereto.

[0123] According to this specification, the signal wiring TL, contact electrode CCE, and pad electrode PE, which are arranged in the same layer as the first electrode CE1, may be composed of multiple layers of conductive material, but the embodiments herein are not limited thereto.

[0124] According to this specification, a solder pattern SDP may be placed on the first electrode CE1 for each of several subpixels. The solder pattern SDP can be used to bond a micro-LEDED to the first electrode CE1, thereby electrically connecting the first electrode CE1 and the micro-LEDED. For example, the first electrode CE1 and the anode electrode 134 of the micro-LEDED can be electrically connected through eutectic bonding using the solder pattern SDP, but the embodiments herein are not limited thereto. For example, if the solder pattern SDP is made of indium (In) and the anode electrode 134 of the micro-LEDED is made of gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded by applying heat and pressure during the transfer process of the micro-LEDED. The micro-LEDED can be bonded to the solder pattern SDP and the first electrode CE1 through eutectic bonding without the need for a separate adhesive. For example, the solder pattern SDP may be made of indium (In), tin (Sn), or alloys thereof, but the embodiments herein are not limited thereto. For example, the solder pattern SDP may be a bonding pad or a joining pad, but the examples herein are not limited thereto.

[0125] According to this specification, the passivation layer 116 may be placed on a plurality of signal lines TL, a plurality of first electrodes CE1, a plurality of contact electrodes CCE, and a third insulating layer 115c. For example, the passivation layer 116 may be placed in a display area AA, a dam area DA, a first non-display area NA1, and a second non-display area NA2. In the dam area DA, the passivation layer 116 may be placed on the first dam layer 301. A portion of the passivation layer 116 placed in the bending area BA may be removed. A portion of the passivation layer 116 covering a plurality of pad electrodes PE in the second non-display area NA2 may be removed. Since the passivation layer 116 is placed to cover the remaining area excluding the bending area BA, the plurality of pad electrodes PE, and the area where the solder pattern SDP is placed, the penetration of moisture or impurities into the micro-LEDED can be reduced. For example, the passivation layer 116 may consist of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but the examples herein are not limited thereto.

[0126] A micro-LEDED may be placed on the solder pattern SDP for each of the multiple sub-pixels. A first micro-LED130 may be placed on the first sub-pixel SP1. A second micro-LED140 may be placed on the second sub-pixel SP2.

[0127] According to this specification, a first optical layer 117a may be arranged to surround a plurality of micro-LEDEDs in display area AA. For example, the first optical layer 117a may be arranged to cover a plurality of micro-LEDEDs and a bank BNK in the area of ​​a plurality of subpixels. For example, the first optical layer 117a may cover the bank BNK, a portion of the passivation layer 116, and the space between the plurality of micro-LEDEDs. The first optical layer 117a may be arranged to cover the space between a plurality of micro-LEDEDs contained in a single pixel PX, and between a plurality of bank BNKs. For example, the first optical layer 117a may extend in a first direction and be spaced apart from each other in a second direction intersecting the first direction. For example, the first optical layer 117a may be arranged to surround the sides of the micro-LEDEDs and bank BNK between the passivation layer 116 and the second electrode CE2, but the embodiments herein are not limited thereto. For example, the first optical layer 117a may be a diffusion layer or a sidewall diffusion layer, but the embodiments described herein are not limited thereto.

[0128] The first optical layer 117a may include an organic insulating material in which fine particles are dispersed, but the examples herein are not limited thereto. For example, the first optical layer 117a may consist of a siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but the examples herein are not limited thereto. Light from multiple micro-LEDEDs can be scattered by the fine particles dispersed in the first optical layer 117a and emitted outside the display device 1000. Thus, the first optical layer 117a can improve the extraction efficiency of light emitted by the multiple micro-LEDEDs.

[0129] For example, the first optical layer 117a may be located in each of several pixels PX, or it may be located together in some of the pixels PX located in the same row, but the embodiments herein are not limited thereto. For example, each of several pixels PX may have a first optical layer 117a, or several pixels PX may share one first optical layer 117a. Another example is that each of several subpixels may separately include a first optical layer 117a, but the embodiments herein are not limited thereto.

[0130] A second optical layer 117b may be placed on a passivation layer 116 where the first optical layer 117a is not located. For example, the second optical layer 117b may be placed so as to surround the first optical layer 117a. For example, the second optical layer 117b may be in contact with the side surface of the first optical layer 117a. For example, the second optical layer 117b may be placed in a region between multiple pixels PX. However, the embodiments of this specification are not limited thereto. For example, the second optical layer 117b may be a diffusion layer, a diffusion layer window, or a window diffusion layer, etc., but the embodiments of this specification are not limited thereto.

[0131] The second optical layer 117b may be composed of an organic insulating material, but the examples herein are not limited thereto. The second optical layer 117b may be composed of the same material as the first optical layer 117a, but the examples herein are not limited thereto. For example, the first optical layer 117a may contain fine particles, while the second optical layer 117b does not have to contain fine particles. For example, the second optical layer 117b may be made of a siloxane, but the examples herein are not limited thereto.

[0132] The second optical layer 117b does not need to be placed in the bending region BA, the first non-display region NA1, and the second non-display region NA2. The second optical layer 117b may be placed in the display region AA and the dam region DA.

[0133] The first dam 1DAM of the dam area DA may further include a second dam layer 302 located on the first dam layer 301.

[0134] The second dam layer 302 can be formed using the same material and process as the second optical layer 117b.

[0135] The cathode electrode of the micro-LEDED (135 in Figure 6) is exposed, and thereafter, a portion of the first optical layer 117a on the cathode electrode 135 may be removed for connection with the second electrode CE2. Referring to Figure 7, a masking process may be carried out to form a contact hole CH1 in the second optical layer 117b for the second electrode CE2 and the connecting electrode CCE. At this time, a second dam layer 302 may be formed on the first dam layer 301.

[0136] The second dam layer 302 may be narrower than the first dam layer 301, and the embodiments described herein are not limited thereto.

[0137] The first dam layer 301 of the first dam 1DAM formed in the dam region DA can prevent the end of the second optical layer 117b adjacent to the bending region BA from gradually thinning along the inclined surface due to the inclination of the lower insulating layer. The side portion of the first dam layer 301 on the side facing the display region AA can stop the flow of the second optical layer 117b.

[0138] This minimizes the thickness variation of the second optical layer 117b in the central and outer parts of the display area AA, thereby making the luminous efficiency uniform across all areas of the display area AA.

[0139] A second electrode CE2 may be formed in the micro-LED of the display area AA, on the upper part of the first optical layer 117a and the second optical layer 117b, and inside the contact hole CH1.

[0140] For example, the second electrode CE2 may be electrically connected to multiple contact electrodes CCE through the contact hole CH1 of the second optical layer 117b. The second electrode CE2 may be placed on multiple micro-LEDEDs and electrically connected to the cathode electrode 135. For example, the second electrode CE2 may include, but is not limited to, a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0141] A third optical layer 117c may be placed on the second electrode CE2. The third optical layer 117c may be placed so as to overlap the plurality of micro-LEDEDs and the first optical layer 117a. Since the third optical layer 117c is placed on top of the second electrode CE2 and the plurality of micro-LEDEDs, it can improve unevenness that may occur in some of the plurality of micro-LEDEDs, and the light emitted by the plurality of micro-LEDEDs is uniformly diffused by the third optical layer 117c and extracted to the outside of the display device 1000, so the brightness uniformity of the display device 1000 can be improved.

[0142] The third optical layer 117c may be composed of an organic insulating material in which fine particles are dispersed, but the examples herein are not limited thereto. For example, the third optical layer 117c may be composed of a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are dispersed, but the examples herein are not limited thereto. For example, the third optical layer 117c may be composed of the same material as the first optical layer 117a, but the examples herein are not limited thereto. For example, the third optical layer 117c may be a diffusion layer or a top diffusion layer, etc., but the examples herein are not limited thereto.

[0143] In the display area AA, a black matrix BM may be arranged on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c, and the black matrix BM may be formed to fill the inside of the contact hole CH1.

[0144] For example, the black matrix BM can fill the contact holes of the second optical layer 117b. Since the black matrix BM is configured to cover the display area AA, it can reduce the mixing of light and external light reflection of multiple subpixels. For example, since the black matrix BM is also placed in the contact holes where the second electrode CE2 and the contact electrode CCE are connected, it can prevent light leakage between multiple adjacent subpixels.

[0145] The black matrix BM may be positioned extending into the dam area DA. The black matrix BM may be positioned at least partially on the first dam layer 301.

[0146] If the black matrix BM is formed from organic material, the black matrix BM may also thin along the lower inclined surface. When the black matrix BM thins, light leakage of micro-LEDEDs may occur in the bending region BA.

[0147] By positioning the black matrix BM extending over the first dam layer 301, which has a certain height, it is possible to prevent the black matrix BM from flowing along the slope and becoming thinner.

[0148] When the passivation layer 116 is positioned on the first dam layer 301, the black matrix BM may be positioned in direct contact with at least a portion of the upper surface of the passivation layer 116, but the embodiments herein are not limited thereto.

[0149] For example, the black matrix BM may consist of an opaque material, but the examples herein are not limited thereto. For example, the black matrix BM may be an organic insulating material to which a black pigment or black dye has been added, but the examples herein are not limited thereto.

[0150] A cover layer 118 may be placed on the black matrix BM in display area AA. The cover layer 118 can protect the structure beneath it. For example, the cover layer 118 may be made of an organic insulating material, but the examples herein are not limited thereto. For example, the cover layer 118 may be made of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the cover layer 118 may be an overcoating layer or an insulating layer, but the examples herein are not limited thereto.

[0151] The cover layer 118 may have a sloping surface in the dam region DA and gradually decrease in thickness. The cover layer 118 may be positioned at least partially on top of the first dam 1DAM, with its end positioned on the second dam layer 302 of the first dam 1DAM, and may be positioned so as not to extend into the bending region BA.

[0152] The cover layer 118 may be formed to be thicker than the adhesive layer 112, the first protective layer 113a, the third protective layer 114, and the first insulating layer 115a, which are placed in the bending region BA to protect the micro-LEDED and electrodes of the display region AA. If the cover layer 118 extends beyond the bending region BA, the total thickness of the layers placed in the bending region BA will increase, which may cause bending defects.

[0153] A polarizing layer 293 may be placed on the cover layer 118 via a first adhesive layer 291. Furthermore, a cover member 200 may be placed on the polarizing layer 293 via a second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may include optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA), but the examples herein are not limited thereto.

[0154] Figure 8 is a cross-sectional view along line A-A' in Figure 3 relating to another embodiment of this specification.

[0155] The explanations for components shown in Figure 8 that are identical to or correspond to those in Figure 7 will be omitted or simplified.

[0156] The first dam (1DAM) and the second dam (2DAM) are positioned on the third insulating layer 115c in the dam area DA. Additional dams may be added to the dam area DA as needed in the design.

[0157] The second dam (2DAM) may, but is not limited to, include a third dam layer (303) and a fourth dam layer (304) positioned on the third dam layer (303). The third dam layer (303) may be formed using the same process and materials as the multiple banks (BNK) and the first dam layer (301) of the first dam (1DAM).

[0158] The heights of the first dam layer 301 and the second dam layer 303 may be the same, and the widths of the first dam layer 301 and the second dam layer 303 may be different, but the embodiments described herein are not limited thereto.

[0159] For example, the width of the first dam layer 301 is formed to be wider than the width of the second dam layer 303, so that the first dam 1DAM can stably support the end of the second optical layer 117b with the first dam layer 301.

[0160] The fourth dam layer 304 of the second dam (2DAM) can be formed using the same process and materials as the second dam layer 302 and the second optical layer 117b.

[0161] The fourth dam layer 304 may be formed at the same height as the second dam layer 302 and the second optical layer 117b, and their widths may differ from each other, but the embodiments herein are not limited thereto.

[0162] The passivation layer 116 may extend to the second dam 2DAM in the dam area DA. The passivation layer 116 may be located between the first dam layer 301 and the second dam layer 302 of the first dam 1DAM and between the third dam layer 303 and the fourth dam layer 304 of the second dam 2DAM, but the embodiments herein are not limited thereto.

[0163] The cover layer 118 may extend beyond the first dam 1DAM to the second dam 2DAM. Even if the cover layer 118 extends beyond the first dam 1DAM, it is possible to prevent the cover layer 118 from extending to the bending region BA at the second dam 2DAM.

[0164] A polarizing layer 293 may be placed on the cover layer 118 via a first adhesive layer 291. A cover member 200 may be placed on the polarizing layer 293 via a second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may include optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA), but the examples herein are not limited thereto.

[0165] Figure 9 is a cross-sectional view along line B-B' in Figure 4. The display device 1000 according to this specification can be cut according to the size of the display device 1000 in a panel state formed from the substrate 110 to the cover layer 118.

[0166] Figure 4 shows a pixel PXL formed at the end of the display device 1000, and side B may be a trimming line that cuts the panel formed from the substrate 110 to the cover layer 118.

[0167] A first micro-LED 130, a second micro-LED 140, and a third micro-LED 150 may be arranged on bank BNK, and a second electrode CE may be commonly connected to the first micro-LED 130, the second micro-LED 140, and the third micro-LED 150.

[0168] At the trimming line, the insulating layer formed of organic material on the substrate 110 is cut after the entire deposition process is complete, so that the end surface does not have to be tilted.

[0169] The panel formed from the substrate 110 to the cover layer 118 can be cut so that the ends of the substrate 101 and the passivation layer 116, and the insulating layers 111a, 111b, 112, 113, 114, 115a, 115b, and 115c placed between the substrate 101 and the passivation layer 116, coincide, but the embodiments herein are not limited thereto.

[0170] Furthermore, the ends of the substrate 101, the second diffusion layer 117b, the black matrix BM, and the cover layer 118 may coincide, but the examples herein are not limited to this.

[0171] Figure 10 is a cross-sectional view along C-C' in Figure 4. C-C' in Figure 4 is the end portion of the display device 1000, an area where pixels PXL are not placed. Side C may be a trimming line that cuts the panel formed from the substrate 110 to the cover layer 118. At the trimming line, the insulating layer formed of organic material on the substrate 110 is cut after all deposition processes are completed, so the end surface does not need to be tilted. Figure 10 is an area where pixels PXL are not placed, and a second electrode CE2 does not need to be placed on top of it.

[0172] The panel formed from the substrate 110 to the cover layer 118 can be cut so that the ends of the substrate 101 and the passivation layer 116, and the insulating layers 111a, 111b, 112, 113, 114, 115a, 115b, and 115c placed between the substrate 101 and the passivation layer 116, coincide, but the embodiments herein are not limited thereto.

[0173] Furthermore, the edges of the substrate 101 may coincide with the edges of the second diffusion layer 117b, the black matrix BM, and the cover layer 118, but the examples herein are not limited to this.

[0174] Figure 11 is an example of a device to which the display device according to the embodiments of this specification is applied, and according to Figure 11, the electronic device may be included in the wearable device 1100. The display device 1000 according to the embodiments of this specification may be applied to a mobile device, a laptop computer, a monitor or a TV, but the embodiments of this specification are not limited thereto.

[0175] Such an electronic device may include a case 1005, a display panel 100, and a display device 1000.

[0176] A display device according to one or more embodiments of this specification may be described as follows.

[0177] A display device according to one embodiment of this specification includes a substrate including a display area and a non-display area disposed on at least one side of the display area, a bending area between the display area and the non-display area, a plurality of insulating layers disposed on the substrate, a bank disposed on the plurality of insulating layers, and a first dam disposed in a dam area between the display area and the bending area, on which at least one microLED is disposed on the bank and an optical layer is disposed on the plurality of insulating layers, the first dam may include a first dam layer made of the same material as the bank.

[0178] According to other features of this specification, the first dam may further include a second dam layer located on the first dam layer in the dam area and consisting of the same material as the optical layer.

[0179] According to other features of this specification, it may further include a black matrix disposed on the optical layer.

[0180] According to other features of this specification, the black matrix may be positioned extending into the dam area and at least partially positioned on the first dam layer.

[0181] According to other features of this specification, the invention further includes a protective layer disposed on the black matrix, the protective layer may be disposed at least partially on the first dam.

[0182] According to other features of this specification, the insulating layer placed in the bending region may be at least one of a plurality of insulating layers placed in the display region of the substrate.

[0183] According to other features of this specification, a second dam may be further included between the first dam and the bending area.

[0184] According to other features of this specification, the second dam may include a third layer made of the same material as the bank.

[0185] According to other features of this specification, the second dam may further include a fourth layer made of the same material as the optical layer on the third layer.

[0186] According to other features of this specification, the invention further includes a plurality of insulating layers and a passivation layer disposed on the bank, the passivation layer may extend into the dam area.

[0187] A display device according to one embodiment of this specification includes a substrate including a display area, a non-display area disposed on at least one side of the display area, and a bending area between the display area and the non-display area; a plurality of insulating layers disposed on the substrate; a bank disposed on the plurality of insulating layers; and at least one microLED disposed on the bank; an optical layer disposed on the plurality of insulating layers; and at least one dam disposed in a dam area between the display area and the bending area, wherein the at least one dam may include a first dam layer made of the same material as the bank.

[0188] According to other features of this specification, at least one dam may further include a second dam layer located on a first dam layer and made of the same material as the optical layer.

[0189] According to other features of this specification, the black matrix may be positioned extending into the dam area and at least partially positioned on the first dam layer.

[0190] According to other features of this specification, the invention further includes a cover layer positioned on the black matrix, the cover layer not having to be positioned on at least one side of the dam that is on the bending region side.

[0191] According to other features of this specification, at least one end of the substrate may coincide with the end of the black matrix.

[0192] According to other features of this specification, a bank may be arranged on multiple insulating layers, and at least one microLED may be arranged on the bank.

[0193] According to other features of this specification, the insulating layer placed in the bending region may be at least one of a plurality of insulating layers placed in the display region of the substrate.

[0194] According to other features of this specification, the invention further includes a drive circuit disposed on a substrate and multiple insulating layers, the drive circuit may be electrically connected to a micro-LED.

[0195] According to other features of this specification, each of the microLEDs may include an anode electrode located at the bottom of the microLED and a cathode electrode located at the top of the microLED.

[0196] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. [Explanation of Symbols]

[0197] 100 Display Panels 110 circuit boards

Claims

1. A substrate including a display area, a non-display area disposed on at least one side of the display area, and a bending area disposed between the display area and the non-display area, A plurality of insulating layers arranged on the substrate, A bank arranged on the plurality of insulating layers, At least one microLED arranged on the bank, An optical layer disposed on the plurality of insulating layers, The dam area between the display area and the bending area, The dam includes a first dam located in the aforementioned dam area, The first dam is a display device comprising a first dam layer made of the same material as the bank.

2. The display device according to claim 1, wherein the first dam is disposed on the first dam layer in the dam region and further comprises a second dam layer made of the same material as the optical layer.

3. The display device according to claim 1, further comprising a black matrix disposed on the optical layer.

4. The display device according to claim 3, wherein the black matrix extends into the dam region and is at least partially positioned on the first dam layer.

5. The black matrix further includes a protective layer disposed on the black matrix, The display device according to claim 3, wherein the protective layer is disposed at least partially on the first dam.

6. The display device according to claim 1, wherein the insulating layer disposed in the bending region is at least one of the plurality of insulating layers disposed in the display region of the substrate.

7. The display device according to claim 1, further comprising a second dam between the first dam and the bending region.

8. The display device according to claim 7, wherein the second dam includes a third dam layer made of the same material as the bank.

9. The display device according to claim 8, wherein the second dam further includes a fourth layer made of the same material as the optical layer on the third dam layer.

10. The plurality of insulating layers and the passivation layer disposed on the bank further include The display device according to claim 8, wherein the passivation layer is arranged to extend into the dam region.

11. A substrate including a display area, a non-display area disposed on at least one side of the display area, and a bending area between the display area and the non-display area, The display area comprises a plurality of insulating layers arranged on the substrate, A bank arranged on the plurality of insulating layers, At least one microLED arranged on the bank, An optical layer disposed on the plurality of insulating layers, A black matrix arranged on the optical layer, It includes at least one dam located in the dam area between the display area and the bending area, A display device comprising a first dam layer made of the same material as the bank, wherein at least one of the dams includes the same material as the bank.

12. The display device according to claim 11, wherein the at least one dam further comprises a second dam layer disposed on the first dam layer and made of the same material as the optical layer.

13. The display device according to claim 11, wherein the black matrix extends into the dam region and is at least partially positioned on the first dam layer.

14. The black matrix further includes a cover layer placed on the black matrix, The display device according to claim 11, wherein the cover layer is not disposed on the side of the at least one dam that is on the bending region side.

15. The display device according to claim 11, wherein at least one end of the substrate coincides with the end of the black matrix.

16. The banks are arranged on the plurality of insulating layers, The display device according to claim 11, wherein at least one microLED is arranged on the bank.

17. The display device according to claim 11, wherein the insulating layer disposed in the bending region is at least one of the plurality of insulating layers disposed in the display region of the substrate.

18. The system further includes the aforementioned substrate and a drive circuit disposed on the plurality of insulating layers, The display device according to claim 11, wherein the drive circuit is electrically connected to the micro LED.

19. The display device according to claim 18, wherein each of the plurality of microLEDs includes an anode electrode located below the microLED and a cathode electrode located above the microLED.

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