Display boards and display devices

Abstract

To provide a display board and a display device. [Solution] The display substrate has a plurality of subpixels, each subpixel including a pixel driving circuit provided in a driving circuit layer and a light-emitting device provided in a light-emitting device layer, the driving circuit layer includes first signal lines and second signal lines provided parallel to each other and arranged periodically, and is configured to provide different electrical signals to the plurality of subpixels, the black matrix layer includes a plurality of first light-transmitting apertures and a plurality of second light-transmitting apertures, each of the plurality of first light-transmitting apertures exposing the light-emitting devices of the plurality of subpixels, each of the plurality of second light-transmitting apertures provided between the plurality of first light-transmitting apertures, the orthographic projection of each of the plurality of second light-transmitting apertures on the base substrate is located between the orthographic projection of one first signal line on the base substrate and the orthographic projection of one second signal line on the base substrate that is closest to one first signal line. The display substrate is light-transmitting through the plurality of second light-transmitting apertures.

Description

Technical Field

[0001] This application claims the priority of International Application No. PCT / CN2021 / 073725 filed on January 26, 2021 and the priority of Chinese Patent Application No. 202110726478.2 filed on June 29, 2021, and all the content disclosed in the above Chinese patent application is incorporated herein by reference as part of this application.

[0002] Embodiments of the present disclosure relate to a display substrate and a display device.

Background Art

[0003] OLED (Organic Light Emitting Diode) display devices have a series of advantages such as self-emission, high contrast, high resolution, wide viewing angle, low power consumption, high response speed, and low manufacturing cost, and have become one of the main development directions of next-generation display devices, and thus are attracting increasing attention.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a display substrate having a plurality of subpixels arranged in a plurality of rows and a plurality of columns, comprising a base substrate, a drive circuit layer provided on the base substrate, a light-emitting device layer provided on the side of the drive circuit layer away from the base substrate, and a black matrix layer provided on the side of the light-emitting device layer away from the base substrate, wherein each of the plurality of subpixels comprises a pixel drive circuit provided on the drive circuit layer and a light-emitting device provided on the light-emitting device layer, the pixel drive circuit is configured to drive the light-emitting device, and the drive circuit layers are provided parallel to each other and arranged periodically. The black matrix layer includes a first signal line and a second signal line, the first signal line and the second signal line configured to provide different electrical signals to the plurality of subpixels, the black matrix layer includes a plurality of first light-transmitting apertures and a plurality of second light-transmitting apertures, the plurality of first light-transmitting apertures each expose the light-emitting devices of the plurality of subpixels, the plurality of second light-transmitting apertures each are provided between the plurality of first light-transmitting apertures, and the orthographic projection of the plurality of second light-transmitting apertures on the base substrate is located between the orthographic projection of one first signal line on the base substrate and the orthographic projection of one second signal line on the base substrate that is closest to the one first signal line.

[0005] For example, in a display board according to at least one embodiment of the present disclosure, the first signal line is a light emission control line, and the second signal line is a reset voltage line.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of subpixels in a plurality of rows and columns includes at least one row of first subpixels and at least one row of second subpixels adjacent to the at least one row of first subpixels and located below the at least one row of first subpixels, wherein the pixel driving circuit of the at least one row of first subpixels shares one light emission control line and one reset voltage line, the pixel driving circuit of the at least one row of second subpixels shares one light emission control line and one reset voltage line, and between the orthographic projection on the base substrate of the light emission control line shared by the pixel driving circuit of the at least one row of first subpixels and the orthographic projection on the base substrate of the reset voltage line shared by the pixel driving circuit of the at least one row of second subpixels, there is an orthographic projection on the base substrate of one row of second light-transmitting apertures.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the drive circuit layer includes third and fourth signal lines provided parallel to each other and arranged periodically, the third and fourth signal lines intersect the first and second signal lines, respectively, the third and fourth signal lines are configured to provide different electrical signals to the plurality of subpixels, and the orthographic projections of the plurality of second light-transmitting apertures on the base substrate are each located between the orthographic projection of one third signal line on the base substrate and the orthographic projection of one fourth signal line adjacent to the one third signal line on the base substrate.

[0008] For example, in a display board according to at least one embodiment of the present disclosure, the third signal line is a first power line, and the fourth signal line is a data line.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the first signal line, the second signal line, the third signal line, and the fourth signal line define a plurality of first regions, and the orthographic projections of the plurality of second light-transmitting apertures on the base substrate are each located within the orthographic projections of the plurality of first regions on the base substrate.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel driving circuit includes a thin-film transistor and a memory capacitor, the thin-film transistor includes a gate provided on the base substrate, the memory capacitor includes a first capacitor electrode and a second capacitor electrode provided on the base substrate, the second capacitor electrode is provided on the side of the first capacitor electrode away from the base substrate, and the light emission control signal line is provided on the same layer as the gate and the first capacitor electrode.

[0011] For example, in a display board according to at least one embodiment of the present disclosure, the reset voltage line is provided on the same layer as the second capacitor electrode.

[0012] For example, a display substrate according to at least one embodiment of the present disclosure further includes a planarization layer provided on the side of the drive circuit layer away from the base substrate, and a pixel definition layer located on the side of the planarization layer away from the base substrate, wherein the pixel definition layer includes a plurality of subpixel apertures, and the light-emitting device includes a first electrode layer, a light-emitting material layer, and a second electrode layer, which are stacked in order away from the base substrate, wherein the first electrode layer is provided on the side of the planarization layer away from the base substrate, and the pixel definition layer is provided on the side of the first electrode layer away from the base substrate, and the plurality of subpixel apertures each expose the first electrode layer of the light-emitting device of the plurality of subpixels, the planarization layer includes a plurality of vias, the first electrode layers of the light-emitting devices of the plurality of subpixels are each electrically connected to the pixel drive circuit of the plurality of subpixels by the plurality of vias, and the plurality of vias corresponding to a plurality of subpixels located in the same row include a first via, a second via, and a third via, and the first line penetrates the first via and the second via but not the third via.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projections of at least some of the plurality of vias on the base substrate are each located within the orthographic projections of the plurality of first regions on the base substrate.

[0014] For example, a display substrate according to at least one embodiment of the present disclosure further includes a plurality of connecting electrodes provided on the side of the planarization layer closer to the base substrate, the first electrode layers of the plurality of subpixel light-emitting devices each electrically connected to the plurality of connecting electrodes by the plurality of vias, the plurality of connecting electrodes electrically connected to the pixel driving circuits of the plurality of subpixels, and the orthogonal projection of at least a portion of the plurality of connecting electrodes on the base substrate lies within the orthogonal projection of a plurality of first regions on the base substrate.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of subpixels include red subpixels, green subpixels, and blue subpixels, with one blue subpixel, one red subpixel, and two green subpixels forming one repeating unit, the plurality of subpixels constituting a plurality of repeating units arranged in multiple rows and multiple columns, and the four vias corresponding to one adjacent blue subpixel, one red subpixel, and two green subpixels located in the same row are not on the same straight line.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, three vias corresponding to three adjacent green subpixels located in the same row are not on the same straight line.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the second line sequentially penetrates multiple vias corresponding to multiple subpixels located in the same column.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the drive circuit layer includes a plurality of light-transmitting portions, the plurality of light-transmitting portions are light-transmitting in a direction perpendicular to the surface of the base substrate, and at least some of the plurality of second light-transmitting openings are provided in a one-to-one correspondence with at least some of the plurality of light-transmitting portions, and are configured to transmit light that forms a predetermined angular range with the surface of the base substrate.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, in the correspondingly provided second light-transmitting opening and light-transmitting portion, the planar shape of the second light-transmitting opening and the planar shape of the light-transmitting portion are at least partially the same in a direction parallel to the surface of the base substrate, and the planar size of the second light-transmitting opening is less than the planar size of the light-transmitting portion.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the first signal line, the second signal line, the third signal line, the fourth signal line, and the plurality of connecting electrodes jointly define the plurality of light-transmitting portions.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, one second light-transmitting aperture is provided corresponding to each of the plurality of subpixels.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, in the correspondingly provided second light-transmitting aperture and light-transmitting portion, in a direction parallel to the surface of the base substrate, the planar shape of the second light-transmitting aperture is circular, the planar shape of the light-transmitting portion is polygonal, and the planar size of the second light-transmitting aperture is less than the planar size of the light-transmitting portion.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, one second light-transmitting aperture is provided corresponding to every two subpixels among the plurality of subpixels.

[0024] For example, in a display substrate according to at least one embodiment of the present disclosure, the distance between two adjacent second light-transmitting apertures among the plurality of second light-transmitting apertures is 50 μm-60 μm.

[0025] For example, in a display substrate according to at least one embodiment of the present disclosure, in the correspondingly provided second light-transmitting aperture and light-transmitting portion, the orthographic projection of the second light-transmitting aperture on the base substrate is located inside the orthographic projection of the light-transmitting portion on the base substrate.

[0026] For example, in the display substrate according to at least one embodiment of the present disclosure, at least one of the plurality of first light-transmitting openings has an arcuate edge.

[0027] For example, in the display substrate according to at least one embodiment of the present disclosure, in a direction parallel to the plate surface of the base substrate, the planar shape of at least one of the plurality of first light-transmitting openings is elliptical, semi-elliptical, circular, semi-circular, track-shaped or semi-track-shaped.

[0028] For example, in the display substrate according to at least one embodiment of the present disclosure, in a direction perpendicular to the plate surface of the base substrate, the plurality of sub-pixel openings and the plurality of first light-transmitting openings correspond and overlap one-to-one. In one corresponding sub-pixel opening and one first light-transmitting opening, in a direction parallel to the plate surface of the base substrate, the planar shape of the sub-pixel opening and the planar shape of the first light-transmitting opening are the same.

[0029] For example, in the display substrate according to at least one embodiment of the present disclosure, the orthographic projection of the sub-pixel opening on the base substrate is located within the orthographic projection of the first light-transmitting opening on the base substrate.

[0030] For example, the display substrate according to at least one embodiment of the present disclosure further includes a color film layer. The color film layer includes a plurality of color film patterns, and the plurality of color film patterns are respectively provided in the plurality of first light-transmitting openings.

[0031] At least one embodiment of the present disclosure further provides a display device including the display substrate according to the embodiment of the present disclosure.

[0032] For example, a display device according to at least one embodiment of the present disclosure further includes a patterned touch surface and an image sensor array, the image sensor array being provided on the side of the drive circuit layer away from the light-emitting device layer and including a plurality of image sensors, the plurality of image sensors being configured to receive light emitted from a plurality of light-emitting devices in the light-emitting device layer, reflected by the pattern on the patterned touch surface, and passing through the second light-transmitting aperture to reach the plurality of image sensors for pattern collection.

[0033] At least one embodiment of the present disclosure provides a display substrate having a plurality of subpixels arranged in a plurality of rows and columns, and comprising a base substrate, a drive circuit layer provided on the base substrate, a light-emitting device layer provided on the side of the drive circuit layer away from the base substrate, and a black matrix layer provided on the side of the light-emitting device layer away from the base substrate, each of the plurality of subpixels comprising a pixel drive circuit provided on the drive circuit layer and a light-emitting device provided on the light-emitting device layer, the pixel drive circuit configured to drive the light-emitting device, the drive circuit layer comprising first signal lines and second signal lines provided parallel to each other and arranged periodically, the first signal lines and the second signal lines configured to provide different electrical signals to the plurality of subpixels, the black matrix layer comprising a plurality of first light-transmitting apertures and a plurality of second light-transmitting apertures, each of the plurality of first light-transmitting apertures exposing the light-emitting devices of the plurality of subpixels, each of the plurality of second light-transmitting apertures provided between the plurality of first light-transmitting apertures, and the orthogonal projection of the plurality of second light-transmitting apertures on the base substrate each being one The display substrate is located between the orthographic projection of a first signal line on the base substrate and the orthographic projection of a second signal line on the base substrate that is closest to the first signal line, and the display substrate further includes a planarization layer provided on the side of the drive circuit layer away from the base substrate, and a pixel definition layer located on the side of the planarization layer away from the base substrate, the pixel definition layer includes a plurality of subpixel apertures, and the light-emitting device includes a first electrode layer, a light-emitting material layer and a second electrode layer, which are stacked in order away from the base substrate, and the first electrode layer is located on the side of the planarization layer The pixel definition layer is provided on the side away from the base substrate, the first electrode layer is provided on the side away from the base substrate, and the plurality of subpixel apertures each expose the first electrode layer of the subpixel light-emitting device, the planarization layer includes a plurality of vias, the first electrode layers of the subpixel light-emitting devices are each electrically connected to the subpixel drive circuit of the plurality of subpixels by the plurality of vias, the plurality of vias corresponding to the plurality of subpixels located in the same row include a first via, a second via, and a third via, and the first straight line penetrates the first via and the second via,It does not penetrate the third via.

[0034] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the drawings of the embodiments are briefly described below, and as will be apparent, the drawings described below relate only to some embodiments of this disclosure and do not limit this disclosure. [Brief explanation of the drawing]

[0035] [Figure 1] Figure 1 is a schematic partial plan view of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic partial cross-sectional view of a display substrate according to at least one embodiment of the present disclosure. [Figure 3] Figure 3 is a schematic partial plan view of the pixel definition layer and black matrix layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic partial plan view of the planarization layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 5] Figure 5 is a schematic partial cross-sectional view of a display substrate according to at least one embodiment of the present disclosure. [Figure 6] Figure 6 is another schematic partial plan view of a display substrate according to at least one embodiment of the present disclosure. [Figure 7A] Figure 7A is a schematic diagram of a pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure. [Figure 7B] Figure 7B is a schematic diagram of another pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure. [Figure 8] Figure 8 shows a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 9A] Figure 9A is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 9B]Figure 9B is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 10A] Figure 10A is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 10B] Figure 10B is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 11A] Figure 11A is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 11B] Figure 11B is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after each functional layer has been sequentially stacked. [Figure 12A] Figure 12A is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 12B] Figure 12B is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after each functional layer has been sequentially stacked. [Figure 13A] Figure 13A is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after each functional layer has been sequentially stacked. [Figure 13B] Figure 13B is a schematic partial plan view of each functional layer of a display substrate according to at least one embodiment of the present disclosure, and a schematic partial plan view after the functional layers have been sequentially stacked. [Figure 14] Figure 14 is a schematic partial plan view of the black matrix layer and color film layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 15] Figure 15 is a schematic cross-sectional view of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0036] To further clarify the purpose, technical proposal and advantages of the embodiments of this disclosure, the technical proposal of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. As is obvious, the embodiments described are some embodiments of this disclosure, not all embodiments. Any other embodiments that a person skilled in the art can obtain without creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0037] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by those skilled in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are used simply to distinguish different components. Similar terms such as “includes” or “incorporates” mean that the element or article appearing after the word covers the element or article and its equivalents listed before the word, but do not exclude other elements or parts. Similar terms such as “connected” or “linked” include electrical connections, whether direct or indirect, and are not limited to physical or mechanical connections. Terms such as “up,” “down,” “left,” and “right” are used simply to indicate relative positions, and if the absolute position of the object being described changes, the relative position may change accordingly.

[0038] To prevent light reflection from the screen, conventional OLED display substrates typically have a polarizing plate attached to the substrate to improve usability in ambient light. However, the inventors of this disclosure have found that the transmittance of polarizing plates is usually only about 40%, resulting in a low light extraction rate for the display substrate and high power consumption.

[0039] In some embodiments, COE (Cover film On Encapsulation) technology, that is, a technology that replaces polarizers with color films (CF), is used to improve the light extraction rate of display substrates, and this technology is also advantageous for the development of highly integrated, lightweight, and thin display substrates. In COE technology, a black matrix layer is formed on the display substrate, and the black matrix layer has light-transmitting openings at positions corresponding to the light-emitting devices of the subpixels, which allow light emitted by the light-emitting devices of the subpixels to pass through. The color film is provided in these light-transmitting openings. In this case, the black matrix layer can absorb light and further shield some of the metal in the display substrate, thereby reducing the light reflectivity of the display substrate. On the other hand, in order to realize functions such as fingerprint recognition, a photosensitive element such as an image sensor is usually provided on the non-display side of the display substrate. In this case, the display substrate also needs a certain light transmittance so that signal light incident from the display side of the display substrate can pass through the display substrate and reach the non-display side. However, the structure of conventional display substrates makes it difficult to realize a light-transmitting region that can transmit signal light. Therefore, it is necessary to reconfigure part of the structure of the display substrate so that the display substrate can transmit signal light.

[0040] At least one embodiment of the present disclosure provides a display substrate and a display device, the display substrate having a plurality of subpixels arranged in a plurality of rows and a plurality of columns, and comprising a base substrate, a drive circuit layer provided on the base substrate, a light-emitting device layer provided on the side of the drive circuit layer away from the base substrate, and a black matrix layer provided on the side of the light-emitting device layer away from the base substrate, each of the plurality of subpixels comprising a pixel drive circuit provided on the drive circuit layer and a light-emitting device provided on the light-emitting device layer, the pixel drive circuit configured to drive the light-emitting device, and the drive circuit layers are provided parallel to each other and periodic The black matrix layer includes a plurality of first and second signal lines arranged in a specific pattern, the first and second signal lines configured to provide different electrical signals to a plurality of subpixels, the black matrix layer includes a plurality of first light-transmitting apertures and a plurality of second light-transmitting apertures, each of which exposes the light-emitting devices of a plurality of subpixels, and each of which is positioned between the plurality of first light-transmitting apertures, with the orthographic projection of each of the plurality of second light-transmitting apertures on the base substrate located between the orthographic projection of one first signal line on the base substrate and the orthographic projection of the second signal line closest to the first signal line on the base substrate.

[0041] In the display substrate according to at least one embodiment of the present disclosure, the black matrix layer has a plurality of second light-transmitting openings, which can be used to transmit light, for example, to transmit signal light for a photosensitive element, and the plurality of second light-transmitting openings are provided between a first signal line and the second signal line closest to the first signal line in a direction parallel to the surface of the base substrate, and in this case a large light-transmitting region can be formed between the first signal line and the second signal line closest to the first signal line, and therefore, by providing the second light-transmitting openings in this position, a sufficient size is possible, sufficient light can be transmitted, and the display effect of the display substrate is not impaired.

[0042] The display substrate and display device according to the embodiments of this disclosure will be described in detail below with reference to several specific examples.

[0043] At least one embodiment of the present disclosure provides a display substrate, Figure 1 shows a partial plan schematic of the display substrate, Figure 2 shows a partial cross-sectional schematic of the display substrate, and Figure 3 shows a partial plan schematic of the pixel definition layer and black matrix layer of the display substrate.

[0044] As shown in Figures 1-3, the display substrate has a plurality of subpixels SP arranged in multiple rows and columns, and includes a base substrate 101, a drive circuit layer 102 provided on the base substrate, a light-emitting device layer provided on the side of the drive circuit layer 102 away from the base substrate 101, and a black matrix layer 113 provided on the side of the light-emitting device layer away from the base substrate 101.

[0045] For example, each subpixel includes a pixel driving circuit provided in the driving circuit layer 102 and a light-emitting device EM provided in the light-emitting device layer, and the pixel driving circuit is electrically connected to the light-emitting device EM and configured to drive the light-emitting device EM. For example, as shown in Figure 1, the driving circuit layer 102 includes a first signal line S1 and a second signal line S2 provided parallel to each other and arranged periodically, and the first signal line S1 and the second signal line S2 are configured to provide different electrical signals to a plurality of subpixels SP.

[0046] Furthermore, considering process errors and structural errors in actual production, the formed signal lines may not be straight lines, for example, they may have uneven parts. In the embodiments of this disclosure, "parallel to each other" means that the angle formed in the extension direction of the first signal line S1 and the second signal line S2 is within a range of 15 degrees, and they do not necessarily have to be strictly parallel.

[0047] For example, as shown in Figures 1-3, the black matrix layer includes a plurality of first light-transmitting apertures 1131 and a plurality of second light-transmitting apertures 1132, each of which exposes a plurality of sub-pixel light-emitting devices EM and allows light emitted by each of the plurality of sub-pixel light-emitting devices EM to pass through. The plurality of second light-transmitting apertures 1132 are each located between the plurality of first light-transmitting apertures 1131, and as shown in Figure 1, the orthographic projection of each of the plurality of second light-transmitting apertures 1132 on the base substrate 101 is located between the orthographic projection of one first signal line S1 on the base substrate 101 and the orthographic projection of one second signal line S2 that is closest to the first signal line S1 on the base substrate 101.

[0048] For example, in some embodiments, the first signal line S1 is the light emission control line EMT, and the second signal line is the reset voltage line VNT, which will be described in detail later.

[0049] For example, in some embodiments, a plurality of subpixels SP in multiple rows and columns includes at least one row of first subpixels SP1 (a first subpixel SP1 in a row is illustrated as an example) and at least one row of second subpixels SP2 (a second subpixel SP2 in a row is illustrated as an example) adjacent to and below the first subpixel SP1 in the at least one row (i.e., located in the next row after the first subpixel SP1 or scanned after the first subpixel SP1 when performing circuit scanning), and the first subpixel S The pixel driving circuit of P1 shares one light emission control line EMT1 and one reset voltage line VNT1, and the pixel driving circuit of at least one row of second subpixels shares one light emission control line EMT2 and one reset voltage line VNT2. In this case, between the orthographic projection of the light emission control line EM1 shared by the pixel driving circuits of at least one row of first subpixels SP1 on the base substrate 101 and the orthographic projection of the reset voltage line VNT2 shared by the pixel driving circuits of at least one row of second subpixels SP2 on the base substrate 101, there is an orthographic projection of one row of second light-transmitting apertures 1132 on the base substrate 101.

[0050] For example, in another embodiment, the pixel driving circuit for multiple rows of first subpixels SP1 may share one light emission control line EMT1 and one reset voltage line VNT1, and the pixel driving circuit for multiple rows of second subpixels may share one light emission control line EMT2 and one reset voltage line VNT2. In this case, the orthographic projection on the base substrate 101 of the light emission control line EMT1 shared by the pixel driving circuit for the multiple rows of first subpixels SP1 and the orthographic projection on the base substrate 101 of the reset voltage line VNT2 shared by the pixel driving circuit for the multiple rows of second subpixels SP2 include the orthographic projection on the base substrate 101 of one row of second light-transmitting apertures 1132.

[0051] For example, as shown in Figure 1, a plurality of subpixels SP in multiple rows and columns further includes at least one row of third subpixels SP3 (the row of third subpixels SP3 is shown as an example) adjacent to at least one row of second subpixels SP2 and located below at least one row of second subpixels SP2, and the pixel driving circuit of the at least one row of third subpixels SP3 shares one light emission control line (not shown) and one reset voltage line VNT3, and in this case, between the orthographic projection on the base substrate 101 of the light emission control line EMT2 shared by the pixel driving circuit of at least one row of second subpixels SP2 and the orthographic projection on the base substrate 101 of the reset voltage line VNT3 shared by the pixel driving circuit of at least one row of third subpixels SP3, there is an orthographic projection on the base substrate 101 of one row of second light-transmitting apertures 1132.

[0052] For example, in some embodiments, as shown in Figures 1 and 2, the drive circuit layer 102 includes a plurality of light-transmitting portions 1020, and the plurality of light-transmitting portions 1020 are light-transmitting in a direction perpendicular to the surface of the base substrate 101. For example, at least some of the second light-transmitting openings 1132 are provided in a one-to-one correspondence with at least some of the light-transmitting portions 1020 and are arranged to transmit light that forms a predetermined angular range with the surface of the base substrate 101. For example, as shown in Figure 2, a light ray L can pass through the second light-transmitting openings 1132 and light-transmitting portions 1020 in order from the display side of the display substrate (i.e., the upper side in the figure) to the non-display side of the display substrate (i.e., the lower side in the figure) so that a photosensitive element, such as an image sensor, provided on the non-display side of the display substrate is exposed to light and operates.

[0053] For example, as shown in Figure 1, in a direction parallel to the base substrate 101, a row of light-transmitting sections 1020 is included between the light emission control signal line EM1 shared by the pixel driving circuits of at least one row of first subpixels SP1 and the reset voltage line VNT2 shared by the pixel driving circuits of at least one row of second subpixels SP2, and a row of light-transmitting sections 1020 is included between the light emission control signal line EMT2 shared by the pixel driving circuits of at least one row of second subpixels SP2 and the reset voltage line VNT3 shared by the pixel driving circuits of at least one row of third subpixels SP3. In this case, the light-transmitting sections 1020 have a large area between the light emission control signal line and the reset voltage line, and in combination with the second light-transmitting aperture 1132, a sufficient light-transmitting effect can be achieved.

[0054] For example, as shown in Figure 1, the drive circuit layer includes third signal lines S3 and fourth signal lines S4 that are provided parallel to each other and arranged periodically, the third signal line S3 and fourth signal line S4 intersect, for example, perpendicular to, the first signal line S1 and second signal line S2, respectively, and the third signal line S3 and fourth signal line S4 are configured to provide different electrical signals to multiple subpixels, and the orthographic projections of multiple second light-transmitting apertures 1032 on the base substrate 101 are each located between the orthographic projection of one third signal line S3 on the base substrate 101 and the orthographic projection of one fourth signal line S4 adjacent to the third signal line on the base substrate 101.

[0055] For example, in some embodiments, the third signal line S3 is the first power line VDD1, and the fourth signal line S4 is the data line DT, which will be described in detail later.

[0056] For example, as shown in Figure 1, the first signal line S1, the second signal line S2, the third signal line S3, and the fourth signal line S4 define a plurality of first regions RG, i.e., regions enclosed by dashed lines in the figure, and the orthographic projections of the plurality of second light-transmitting apertures 1032 on the base substrate 101 are each located within the orthographic projections of the plurality of first regions RG on the base substrate 101. For example, in some examples, as shown in Figure 1, in correspondingly provided second light-transmitting apertures 1132 and light-transmitting portions 1020, the planar shape of the second light-transmitting aperture 1132 and the planar shape of the light-transmitting portion 1020 are at least partially the same in the direction parallel to the surface of the base substrate 101. For example, as shown in Figure 1, at least a portion of the contour of the second light-transmitting aperture 1132 follows the contour of the light-transmitting portion 1020, and the planar size of the second light-transmitting aperture 1132 is less than the planar size of the light-transmitting portion 1020. For example, in the correspondingly provided second light-transmitting opening 1132 and light-transmitting portion 1020, the orthographic projection of the second light-transmitting opening 1132 on the base substrate 101 is located inside the orthographic projection of the light-transmitting portion 1020 on the base substrate 101.

[0057] For example, in some embodiments, as shown in Figure 1, one second light-transmitting aperture 1132 is provided corresponding to each subpixel SP, thereby ensuring a sufficient number and size of second light-transmitting apertures 1132 on the display substrate and achieving a sufficient light-transmitting effect.

[0058] For example, as shown in Figure 2, the pixel driving circuit includes at least one thin-film transistor TFT and a memory capacitor Cst, the thin-film transistor TFT including an active layer 1021, gate 1022, source 1023 and drain 1024 provided on a base substrate 101. The source 1023 of the thin-film transistor TFT is electrically connected to the first electrode layer 104 of the light-emitting device EM. The memory capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2 provided on the base substrate 101, the second capacitor electrode C2 being provided on the side of the first capacitor electrode C1 away from the base substrate 101. For example, in some embodiments, the light emission control signal line EMT is provided on the same layer as the gate 1022 and the first capacitor electrode C1. For example, in some embodiments, the reset voltage line VNT is provided on the same layer as the second capacitor electrode C2.

[0059] For example, the pixel driving circuit may be formed as a 2T1C (two thin-film transistors and one memory capacitor), 6T1C (six thin-film transistors and one memory capacitor), and thus include multiple thin-film transistors, which have a stacked structure similar to or the same as the thin-film transistors shown in Figure 2. Figure 2 shows only thin-film transistors directly connected to the light-emitting device, and these thin-film transistors may be driving thin-film transistors, light-emitting control thin-film transistors, and so on.

[0060] However, in the embodiments of this disclosure, "provided in the same layer" means that two or more functional layers (or structural layers) are in the same layer in the hierarchical structure of the display substrate and are formed of the same material; that is, in the manufacturing process, the two or more functional layers (or structural layers) may be formed from the same material layer and the required patterns and structures may be formed by the same patterning process.

[0061] Furthermore, as shown in Figure 2, the display panel may further include structures such as a buffer layer 103 provided on the base substrate 101, a first gate insulating layer 1024 provided on the active layer 1021, a second gate insulating layer 1025 provided on the gate 1022 and the first capacitor electrode C1, an interlayer insulating layer 1026 provided on the second capacitor electrode CE2, and a passivation layer 1027 provided on the source 1023 and the drain 1024. For example, a plurality of light-transmitting portions 1020 include a light-transmitting insulating material, and this light-transmitting insulating material includes the light-transmitting insulating material of insulating layers such as the first gate insulating layer 1024, the second gate insulating layer 1025, the interlayer insulating layer 1026, and the passivation layer 1027.

[0062] For example, in some embodiments, as shown in Figure 2, the display substrate may further include a planarization layer 109 provided on the side of the drive circuit layer 102 away from the base substrate 101, and a pixel definition layer 108 located on the side of the planarization layer 109 away from the base substrate 101. The pixel definition layer 108 includes a plurality of sub-pixel apertures 1081, and the light-emitting device EM includes a first electrode layer 104, a light-emitting material layer 105, and a second electrode layer 106 that are stacked in order in the direction away from the base substrate 101, with the first electrode layer 104 provided on the side of the planarization layer 109 away from the base substrate 101, and the pixel definition layer 108 provided on the side of the first electrode layer 104 away from the base substrate 101, and the plurality of sub-pixel apertures 1081 each expose the first electrode layer 104 of the light-emitting device EM of the plurality of sub-pixels. For example, the planarization layer 109 includes multiple vias VA, and the first electrode layer 104 of the light-emitting devices EM of the multiple subpixels is electrically connected to the pixel driving circuits of the multiple subpixels by multiple vias VA.

[0063] For example, in some embodiments, as shown in Figures 1 and 2, the first electrode layer 104 includes a main body portion 1041 and a connecting portion 1042, the connecting portion 1042 is configured to be electrically connected to a pixel driving circuit, for example, by via VA in the planarization layer 109, and at least a portion of the main body portion 1041 is exposed by a sub-pixel aperture 1081.

[0064] For example, Figure 4 shows a planar arrangement of multiple vias VA in the planarization layer 109. Combining this with Figures 1 and 4, three vias VA corresponding to at least three adjacent subpixels located in the same row are not on the same straight line. That is, the positions of the three vias VA corresponding to at least three adjacent subpixels are offset from each other, so that no single straight line can pass through the three vias VA corresponding to at least three adjacent subpixels.

[0065] For example, as shown in Figure 4, multiple vias VA corresponding to multiple subpixels located in the same row include a first via VA1, a second via VA2, and a third via VA3, and the first straight line ST1 passes through the first via VA1 and the second via VA2, but not through the third via VA3. For example, the extension direction of the first straight line ST1 is parallel to the extension directions of the first signal line S1 and the second signal line S2, and is shown as the horizontal direction in the figure.

[0066] For example, as shown in Figures 1 and 4, the orthographic projections of at least some of the multiple vias VA on the base substrate 101 are each located within the orthographic projections of the multiple first regions RG on the base substrate 101. That is, the orthographic projections of the multiple vias VA on the base substrate 101 have an overlapping portion with the orthographic projections of the multiple first regions RG on the base substrate 101, or the orthographic projections of the multiple vias VA on the base substrate 101 are each located within the orthographic projections of the multiple first regions RG on the base substrate 101.

[0067] In the embodiments of this disclosure, the multiple vias VA of the planarization layer 109 are designed so that they do not lie on the same straight line, thereby avoiding the wiring of the pixel driving circuit and forming one large light-transmitting region, and thus forming a light-transmitting portion 1020 with a sufficient area.

[0068] For example, in some embodiments, multiple subpixels include red subpixels, green subpixels, and blue subpixels, with one blue subpixel, one red subpixel, and two green subpixels forming one repeating unit, and multiple subpixels constituting multiple repeating units arranged in multiple rows and columns. For example, as shown in Figure 4, the four vias VA1-VA4 corresponding to one adjacent blue subpixel, one red subpixel, and two green subpixels located in the same row are not on the same straight line. For example, in Figure 4, the red subpixel corresponds to via VA1, the two green subpixels correspond to vias VA2 and VA4, and the blue subpixel corresponds to via VA3.

[0069] For example, in some embodiments, three vias corresponding to three adjacent green subpixels located in the same row are not on the same straight line. For example, Figure 4 shows two vias VA2 and VA4 corresponding to two adjacent green subpixels located in the same row and belonging to the same repeating unit, with the position of via VA5 corresponding to the green subpixel to the right of via VA4 in the figure indicated by a dashed box. In this case, the three vias VA2, VA4, and VA5 corresponding to three adjacent green subpixels located in the same row are not on the same straight line.

[0070] For example, as shown in Figure 4, multiple vias corresponding to multiple subpixels located in the same column lie on the same straight line; that is, one straight line can pass through multiple vias VA corresponding to multiple subpixels located in the same column. As shown in Figure 4, the second straight line ST2 passes sequentially through multiple vias VA corresponding to multiple subpixels located in the same column. For example, the extension direction of the second straight line ST2 is parallel to the extension directions of the third signal line S3 and the fourth signal line S4, and is shown as perpendicular in the figure. This enables the multiple subpixels to be aligned in the column direction.

[0071] For example, in some embodiments, as shown in Figure 2, the display substrate may further include structures such as a spacer 107 provided on the pixel definition layer 108 and an encapsulation layer EN provided on the light-emitting device EM of the sub-pixels. For example, the encapsulation layer EN may include a plurality of sub-encapsulation layers to improve its encapsulation effect. For example, the encapsulation layer EN may be a composite encapsulation layer, including a first inorganic encapsulation layer 110, a second organic encapsulation layer 111, and a third inorganic encapsulation layer 112. For example, the first inorganic encapsulation layer 110 and the second inorganic encapsulation layer 112 may be formed from inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the first organic encapsulation layer 111 may be formed from an organic material such as polyimide (PI) or epoxy resin. The composite encapsulation layer can provide multiple layers of protection to the functional structure in the display panel and has a better encapsulation effect.

[0072] For example, Figure 5 shows another schematic partial cross-sectional view of a display substrate according to at least one embodiment of the present disclosure. In this embodiment, as shown in Figure 5, the display substrate further includes a connecting electrode 1043, which is provided on the side of the planarization layer 109 closer to the base substrate 101, and the connecting portion 1042 of the first electrode layer 104 of the light-emitting device EM is electrically connected to the pixel driving circuit by the connecting electrode 1043. In this case, the connecting portion 1042 of the first electrode layer 104 is connected to the connecting electrode 1043 by a via VA in the planarization layer 109, and the connecting electrode 1043 is connected to the source 1023 of the thin-film transistor TFT by a via in another planarization layer 1091.

[0073] For example, as shown in Figure 1, the orthographic projections of at least some of the multiple connection electrodes 1043 (Figure 12A shows a schematic plan view of the multiple connection electrodes 1043) on the base substrate 10 are located within the orthographic projections of the multiple first regions RG on the base substrate 10. That is, the orthographic projections of the multiple connection electrodes 1043 on the base substrate 10 overlap with the orthographic projections of the multiple first regions RG on the base substrate 10, or the orthographic projections of the multiple connection electrodes 1043 on the base substrate 10 are each located within the orthographic projections of the multiple first regions RG on the base substrate 10. See Figure 1.

[0074] For example, as shown in Figure 1, the first signal line S1, the second signal line S2, the third signal line S2, the fourth signal line S4, and the multiple connecting electrodes 1043 jointly define multiple light-transmitting portions 1020, that is, the region surrounded by the first signal line S1, the second signal line S2, the third signal line S2, the fourth signal line S4, and the multiple connecting electrodes 1043 is multiple light-transmitting portions 1020.

[0075] In this embodiment, the vias VA in the planarization layer 109 have the same arrangement as in Figure 4, and will not be described in detail here. For other structures of the display substrate shown in Figure 5, refer to the display substrates shown in Figures 1-3, and will not be described in detail here.

[0076] For example, in the embodiments of this disclosure, the base substrate 101 may include a flexible insulating material such as polyimide (PI) or a rigid insulating material such as a glass substrate. For example, in some examples, the base substrate 101 may have a laminated structure in which a plurality of flexible layers and a plurality of barrier layers are alternately provided. In this case, the flexible layers may include polyimide, and the barrier layers may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the buffer layer 103 may include inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride. The active layer 1021 can be made of materials such as polysilicon and metal oxides, the first gate insulating layer 1024 and the second gate insulating layer 1025 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, the gate 1022 and the first capacitor electrode C1 can be made of metallic materials such as copper, aluminum, titanium and cobalt, and can be formed as a single layer or multilayer structure, for example, a multilayer structure such as titanium / aluminum / titanium and molybdenum / aluminum / molybdenum, and the second capacitor electrode C2 can be made of metallic or alloy materials such as copper, aluminum, titanium and cobalt, between layers The insulating layer 1026 can be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride; the passivation layer 1027 can be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride; the source drains 1023 and 1024 can be made of metallic materials such as copper, aluminum, titanium, and cobalt, and can be formed as a single-layer or multilayer structure, for example, a multilayer structure such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum; the first electrode layer 104 is, for example, an anode layer and contains a metal oxide such as ITO or IZO, or a metal such as Ag, Al, or Mo or an alloy thereof. The material of the light-emitting material layer 105 may be an organic light-emitting material, for example, the material of the light-emitting material layer 105 can be selected to emit light of a specific color (e.g., red light, blue light, or green light) according to the needs.The second electrode layer 106 is, for example, a cathode layer and includes a metal or alloy thereof such as Mg, Ca, Li, or Al, or a metal oxide such as IZO or ZTO, or a conductive organic material such as PEDOT / PSS (poly-3,4-ethylenedioxythiophene / polystyrene sulfonate). The planarization layer 109 (and planarization layer 1091), pixel definition layer 108, and spacer 107 can be made of an organic insulating material such as polyimide. The embodiments of this disclosure do not particularly limit the materials of each functional layer.

[0077] For example, Figure 6 shows another schematic partial plan view of a display substrate according to at least one embodiment of the present disclosure. In this embodiment, as shown in Figure 6, in the correspondingly provided second light-transmitting opening 1132 and light-transmitting portion 1020, the planar shape of the second light-transmitting opening 1132 is circular, the planar shape of the light-transmitting portion 1020 is polygonal in a direction parallel to the surface of the base substrate 101, and the planar size of the second light-transmitting opening 1132 is less than the planar size of the light-transmitting portion 1020.

[0078] For example, as shown in Figure 6, in the correspondingly provided second light-transmitting aperture 1132 and light-transmitting portion 1020, the orthographic projection of the second light-transmitting aperture 1132 on the base substrate 101 is located inside the orthographic projection of the light-transmitting portion 1020 on the base substrate 101. In this case, the second light-transmitting aperture 1132 may be a pinhole type light-transmitting element, and the photosensitive element located on the non-display side of the display substrate can perform fingerprint recognition based on the principle of an image sensor or pinhole imaging.

[0079] For example, in the embodiment shown in Figure 6, the need for pinhole imaging is met by providing one second light-transmitting aperture 1132 corresponding to every two subpixels. For example, in some examples, the distance D between two adjacent second light-transmitting apertures 1132 among the multiple second light-transmitting apertures 1132 is 50 μm-60 μm, such as 52 μm, 55 μm, or 58 μm. For example, the distance between two adjacent second light-transmitting apertures 1132 located in the same row or two adjacent second light-transmitting apertures 1132 located in the same column is both 50 μm-60 μm.

[0080] For example, regarding other structures of the display board shown in Figure 6, refer to the explanation of the display board in Figures 1-3, and a detailed explanation will not be provided here.

[0081] For example, in some embodiments, as shown in Figures 3 and 6, at least one of the plurality of first light-transmitting openings 1311 (e.g., each) has an arc-shaped edge. For example, in some embodiments, in a direction parallel to the surface of the base substrate 101, the planar shape of at least one of the plurality of first light-transmitting openings 1131 (e.g., each) is an elliptical (or mango-shaped), semi-elliptical, circular, semi-circular, track-shaped, or semi-track-shaped shape or a variation thereof.

[0082] In the embodiments of this disclosure, the first light-transmitting aperture 1131 having an arc-shaped edge reduces and eliminates the phenomenon in which ambient light diffracts at the edge of the first light-transmitting aperture 1131 of the black matrix layer 113, causing color separation of the display substrate, and further improves the display effect of the display substrate. In the embodiments of this disclosure, the color separation phenomenon is a phenomenon in which, when the display substrate is turned off, color separation (e.g., red, green, and blue) occurs in reflected light under ambient light (e.g., under a point light source, a line light source).

[0083] However, in the embodiments of this disclosure, the track shape is a shape similar to a track, formed by one rectangle and two opposing arcs on either side of the rectangle, and the track shape has two opposing parallel right sides and two opposing arcs. The mango shape may be considered a variation of the ellipse, and as shown in Figure 6, has two opposing arc-shaped edges.

[0084] For example, as shown in Figures 3 and 6, in a direction perpendicular to the surface of the base substrate 101, the multiple sub-pixel apertures 1081 and the multiple first light-transmitting apertures 1131 correspond one-to-one and overlap. For each corresponding sub-pixel aperture 1081 and one first light-transmitting aperture 1131, the planar shape of the sub-pixel aperture 1081 and the planar shape of the first light-transmitting aperture 1131 are the same in a direction parallel to the surface of the base substrate 101, and both are shown as elliptical (or mango-shaped) in the figures. For example, in some cases, the planar shape of the main body portion 1041 of the first electrode layer 104 of the light-emitting device EM is the same as the planar shapes of the sub-pixel aperture 1081 and the first light-transmitting aperture 1131.

[0085] For example, as shown in Figures 3 and 6, the orthographic projection of the sub-pixel aperture 1081 on the base substrate 101 lies within the orthographic projection of the first light-transmitting aperture 1131 on the base substrate 101, that is, the planar size of the sub-pixel aperture 1081 is less than the planar size of the first light-transmitting aperture 1131. For example, the orthographic projection of the first light-transmitting aperture 1131 on the base substrate 101 lies within the orthographic projection of the main body portion 1041 on the base substrate 101, that is, the planar size of the first light-transmitting aperture 1131 is less than the planar size of the main body portion 1041. As a result, the display substrate according to the embodiment of this disclosure can reduce and eliminate the color separation phenomenon of the display substrate, as well as save energy consumption and conserve resources.

[0086] For example, as shown in Figure 2, in some embodiments, the display substrate may further include a color film layer 114, the color film layer 114 comprising a plurality of color film patterns 1141, each of which is provided in a plurality of first light-transmitting apertures 1131. This allows light emitted by the sub-pixel light-emitting device EM to pass through the color film patterns 1141 and be emitted, thereby improving the purity of the emitted light.

[0087] For example, Figure 14 shows a partial planar schematic of the black matrix layer and color film layer of the display substrate, and also shows a planar schematic of a plurality of first light-transmitting apertures 1131, a plurality of second light-transmitting apertures 1132, and a plurality of color film patterns 1141. As shown in Figure 14, in a direction perpendicular to the surface of the base substrate 101, the plurality of color film patterns 1141 include a first color film pattern 1141A that at least partially overlaps the light-emitting device of a first subpixel (e.g., a red subpixel), and a second color film pattern 1141B that at least partially overlaps the light-emitting device of a second subpixel (e.g., a green subpixel). In a direction parallel to the surface of the base substrate 101, the planar shape of the first color film pattern 1141A is different from the planar shape of the second color film pattern 1141B, and the area of ​​the first color film pattern 1141A is larger than the area of ​​the second color film pattern 1141B.

[0088] For example, as shown in Figure 14, the planar shape of the first color film pattern 1141A is approximately rectangular, for example, a rectangle with a notch, and the planar shape of the second color film pattern 1141B is approximately semi-elliptical. For example, the areas of the first color film pattern 1141A and the second color film pattern 1141B are each larger than the area of ​​the first light-transmitting opening 1131 that covers them, thereby achieving sufficient filtering.

[0089] For example, in some cases, the ratio of the area of ​​the first color film pattern 1141A to the area of ​​the second color film pattern 1141B is in the range of (1 to 1.5):1, such as 1.2:1 or 1.4:1.

[0090] For example, as shown in Figure 14, in a direction perpendicular to the surface of the base substrate 101, the multiple color film patterns 1141 further include a third color film pattern 1141C that at least partially overlaps with the light-emitting device of the third subpixel (e.g., blue subpixel). In a direction parallel to the surface of the base substrate 101, the planar shape of the third color film pattern 1141C differs from the planar shapes of the first color film pattern 1141A and the second color film pattern 1141B, and the area of ​​the third color film pattern 1141C is larger than the area of ​​the first color film pattern 1141A and the second color film pattern 1141B. For example, the planar shape of the third color film pattern 1141C is irregular, thereby effectively realizing a filtering effect.

[0091] For example, in some embodiments, the ratio of the area of ​​the first color film pattern 1141A, the area of ​​the second color film pattern 1141B, and the area of ​​the third color film pattern 1141C is in the range of (1~1.5):1:(1~1.6), such as 1.2:1:1.1 or 1.4:1:1.3.

[0092] For example, as shown in Figure 14, in a direction perpendicular to the surface of the base substrate 101, the multiple color film patterns 1141 further include a fourth color film pattern 1141D that at least partially overlaps with the light-emitting device of the fourth subpixel (e.g., a green subpixel). In a direction parallel to the surface of the base substrate 101, the planar shape of the fourth color film pattern 1141D is approximately the same as the planar shape of the second color film pattern 1141B, and the area of ​​the fourth color film pattern 1141D is approximately equal to the area of ​​the second color film pattern 1141D.

[0093] For example, the planar shape of the fourth color film pattern 1141D is approximately semi-elliptical, and its area is approximately equal to the area of ​​the second color film pattern 1141D. For example, the difference between the area of ​​the fourth color film pattern 1141D and the area of ​​the second color film pattern 1141D is 10% or less of the area of ​​the second color film pattern 1141D.

[0094] In the embodiments of this disclosure, the black matrix layer 113 absorbs light rays incident on the display substrate, reducing the reflectivity of ambient light by the display substrate and improving the display effect of the display substrate. By covering the black matrix layer 113 with a color film layer 114, the color film layer 114 can perform secondary absorption of light rays incident on the display substrate, thereby further reducing the reflectivity of ambient light by the display substrate and improving the display effect of the display substrate. Tests were conducted on a plurality of color film patterns 1141 shown in Figure 14, and it was found that when the plurality of color film patterns 1141 have the shape and size distribution shown in Figure 14, the plurality of color film patterns 1141 can sufficiently achieve filtering and light reflection effects, improving the display effect of the display substrate.

[0095] For example, in some embodiments, as shown in Figure 14, the fourth color film pattern 1141D and the fourth photon aperture 1132D partially overlap in a direction perpendicular to the surface of the base substrate 101.

[0096] For example, in some cases, as shown in Figure 14, the horizontal size 1141A~1 of the first color film pattern 1141A corresponding to the first subpixel P1 is 27μm~33μm, for example 28μm, 29μm or 30μm, and the vertical size 1141A~2 is 30μm~35μm, for example 32μm, 33μm or 34μm, and the horizontal size 1141B~1 of the second color film pattern 1141B corresponding to the second subpixel P2 is 20μm~25μm, for example 21μm, 22μm or 23μm, and the vertical size 1141B~2 is 23μm~28μm, for example 25μm or 26μm. Or 27 μm, for example, the horizontal size 1141C~1 of the third color film pattern 1141C corresponding to the third subpixel P3 is 32 μm~38 μm, for example 34 μm, 35 μm or 36 μm, and the vertical size 1141C~2 is 35 μm~45 μm, for example 38 μm, 40 μm or 42 μm, for example, the horizontal size 1141D~1 of the fourth color film pattern 1141D corresponding to the fourth subpixel P4 is 20 μm~25 μm, for example 21 μm, 22 μm or 23 μm, and the vertical size 1141D~2 is 23 μm~28 μm, for example 25 μm, 26 μm or 27 μm.

[0097] For example, the minimum distance between the edges of multiple color film patterns 1141 and the edges of multiple second light-transmitting apertures 1132 is 1 μm to 5 μm. For example, as shown in Figure 3, for at least some adjacent color film patterns 1141 and second light-transmitting apertures 1132, there is a gap between the color film patterns 1141 and the second light-transmitting apertures 1132, and the minimum distance between the edges of the color film patterns 1141 and the edges of the second light-transmitting apertures 1132 is 1 μm to 5 μm, thereby preventing the color film patterns 1141 from filtering the light that has passed through the second light-transmitting apertures 1132.

[0098] For example, as shown in Figures 14 and 6, for one color film pattern 1141 and one subpixel aperture 1081 corresponding to the same subpixel, the planar shape of the color film pattern 1141 is different from the planar shape of the subpixel aperture 1081. For example, at least some of the edges of a plurality of second light-transmitting apertures 1132 are parallel to at least some of the edges of the adjacent color film pattern 1141. For example, in the area shown by the dashed frame in Figure 14, some of the edges of the second light-transmitting aperture 1132 are parallel to some of the edges of the adjacent color film pattern 1141.

[0099] For example, as shown in Figure 2, the display substrate may further include a protective cover plate 115 provided on the black matrix layer 113 and the color film layer 114, thereby protecting the structure of the display substrate. For example, the protective cover plate 115 may be a glass cover plate and may be bonded to the display substrate by an optically transparent adhesive (not shown).

[0100] The structure and circuit arrangement of each functional layer of the display substrate according to an embodiment of this disclosure will be described in detail below with reference to one specific example. In this example, the subpixels drive the light-emitting device EM using a 7T1C pixel driving circuit.

[0101] For example, Figure 7A shows a circuit diagram of a 7T1C pixel circuit. As shown in Figure 7A, the pixel circuit includes a drive circuit 122, a data writing circuit 126, a compensation circuit 128, a memory circuit 127, a first light emission control circuit 123, a second light emission control circuit 124, and a reset circuit 129.

[0102] For example, the drive circuit 122 includes a control terminal 131, a first terminal 132, and a second terminal 133, and is configured to control the drive current flowing through the light-emitting device EM. The control terminal 131 of the drive circuit 122 is connected to the first node N1, the first terminal 132 of the drive circuit 122 is connected to the second node N2, and the second terminal 133 of the drive circuit 122 is connected to the third node N3.

[0103] For example, the data writing circuit 126 includes a control terminal, a first terminal, and a second terminal, the control terminal being configured to receive a first scan signal, the first terminal being configured to receive a data signal, and the second terminal being connected to the first terminal 132 (second node N2) of the drive circuit 122 and configured to write the data signal to the first terminal 132 of the drive circuit 122 in response to the first scan signal Ga1. For example, the first terminal of the data writing circuit 126 is connected to the data line 12 to receive the data signal, and the control terminal is connected to the scan line 11 to receive the first scan signal Ga1.

[0104] For example, during the data writing phase, the data writing circuit 126 can be turned on in response to the first scanning signal Ga1, thereby writing the data signal to the first terminal 132 (second node N2) of the drive circuit 122 and storing the data signal in the storage circuit 127. This allows, for example, during the light emission phase, to generate a drive current that drives the light emission of the light-emitting device EM according to the data signal.

[0105] For example, the compensation circuit 128 includes a control terminal, a first terminal and a second terminal, the control terminal is configured to receive a second scanning signal Ga2, the first terminal and the second terminal are electrically connected to the control terminal 131 and the second terminal 133 of the drive circuit 122, respectively, and the compensation circuit is configured to perform threshold compensation on the drive circuit 120 in response to the second scanning signal.

[0106] For example, the memory circuit 127 is electrically connected to the control terminal 131 and the first voltage terminal VDD of the drive circuit 122 and is configured to store the data signal written by the data writing circuit 126. For example, during the data writing and compensation phase, the compensation circuit 128 may be turned on in response to the second scanning signal Ga2, thereby storing the data signal written by the data writing circuit 126 in the memory circuit 127. For example, simultaneously during the data writing and compensation phase, the compensation circuit 128 may be electrically connected to the control terminal 131 and the second terminal 133 of the drive circuit 122, thereby storing related information on the threshold voltage of the drive circuit 122 in association with the memory circuit, thereby allowing the drive circuit 122 to be controlled using the stored data signal and threshold voltage during the light emission phase, thereby compensating the output of the drive circuit 122.

[0107] For example, the first light emission control circuit 123 is connected to the first terminal 132 (second node N2) and the first voltage terminal VDD of the drive circuit 122, and is configured to apply the first power supply voltage of the first voltage terminal VDD to the first terminal 132 of the drive circuit 122 in response to the first light emission control signal. For example, as shown in Figure 7A, the first light emission control circuit 123 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.

[0108] For example, the second light emission control circuit 124 is connected to the second light emission control terminal EM2, the first terminal 510 of the light emission device EM, and the second terminal 132 of the drive circuit 122, and is configured to apply a drive current to the light emission device EM in response to the second light emission control signal.

[0109] For example, during the light emission phase, the second light emission control circuit 123 turns on in response to the second light emission control signal provided by the second light emission control terminal EM2, thereby allowing the drive circuit 122 to apply a drive current to the light-emitting device EM via the second light emission control circuit 123 to cause it to emit light. During the non-light emission phase, the second light emission control circuit 123 turns off in response to the second light emission control signal, thereby preventing current from flowing through the light-emitting device EM and causing it to emit light, and improving the contrast of the corresponding display device.

[0110] For example, during the initialization phase, the second light emission control circuit 124 can be turned on in response to the second light emission control signal, thereby enabling a reset operation on the drive circuit 122 and the light emission device EM in combination with the reset circuit.

[0111] For example, the second light emission control signal EM2 may be the same as or different from the first light emission control signal EM1, and they may be connected to the same or different signal output terminals.

[0112] For example, the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light-emitting device EM, and is configured to apply a reset voltage to the first terminal 134 of the light-emitting device EM in response to a reset signal. In some other examples, as shown in Figure 7A, the reset signal may also be applied to the control terminal 131 of the drive circuit, i.e., the first node N1. For example, the reset signal may be the second scan signal, and the reset signal may be any other signal synchronized with the second scan signal, and the embodiments of this disclosure are not limited thereto. For example, as shown in Figure 7A, the reset circuit 129 is connected to the first terminal 134, the reset voltage terminal Vinit, and the reset control terminal Rst (reset control line) of the light-emitting device EM, respectively. For example, during the initialization phase, the reset circuit 129 may be turned on in response to a reset signal, thereby applying a reset voltage to the first terminal 134 and the first node N1 of the light-emitting device EM, thereby performing a reset operation on the drive circuit 122, the compensation circuit 128, and the light-emitting device EM, and removing the effects of the previous light-emitting phase.

[0113] For example, the light-emitting device EM includes a first terminal 134 and a second terminal 135, wherein the first terminal 134 of the light-emitting device EM is configured to receive a drive current from the second terminal 133 of the drive circuit 122, and the second terminal 135 of the light-emitting device EM is configured to be connected to a second voltage terminal VSS. For example, in one example, as shown in Figure 7A, the first terminal 134 of the light-emitting device EM may be connected to a third node N3 by a second light-emitting circuit 124. Embodiments of the present disclosure include, but are not limited to, this configuration. For example, the light-emitting device EM may be various types of OLEDs, such as top-emission, bottom-emission, and dual-emission, which can emit red light, green light, blue light, or white light, and the first electrode layer and second electrode layer of the OLED function as the first terminal 134 and second terminal 135 of the light-emitting device, respectively. Embodiments of the present disclosure do not limit the specific structure of the light-emitting device.

[0114] However, in the description of the embodiments of this disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual existing components, but rather indicate the junction points where related circuits are connected in the circuit diagram.

[0115] In the description of the embodiments of this disclosure, the symbol Vd can not only indicate a data signal terminal but also the level of a data signal; similarly, the symbols Ga1 and Ga2 can not only indicate the first scan signal and the second scan signal, but also the first scan signal terminal and the second scan signal terminal; Rst can not only indicate a reset control terminal but also the reset signal; Vinit can not only indicate a reset voltage terminal but also the reset voltage; VDD can not only indicate a first voltage terminal but also the first power supply voltage; and VSS can not only indicate a second voltage terminal but also the second power supply voltage. The following embodiments are the same and will not be described in detail.

[0116] Figure 7B is a circuit diagram of a specific implementation example of the pixel circuit shown in Figure 7A. As shown in Figure 7B, the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a memory capacitor Cst. For example, the first transistor T1 is used as a driving transistor, and the remaining second to seventh transistors are used as switching transistors.

[0117] For example, as shown in Figure 7B, the drive circuit 122 may be implemented as a first transistor T1. The gate of the first transistor T1 is connected to the first node N1 as the control terminal 131 of the drive circuit 122, the first pole of the first transistor T1 is connected to the second node N2 as the first terminal 132 of the drive circuit 122, and the second pole of the first transistor T1 is connected to the third node N3 as the second terminal 133 of the drive circuit 122.

[0118] For example, as shown in Figure 7B, the data writing circuit 126 may be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first pole of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second pole of the second transistor T2 is connected to the first terminal 132 (second node N2) of the drive circuit 122. For example, the second transistor T2 is a P-type transistor, and for example, the active layer is a thin-film transistor doped with polysilicon at low temperature.

[0119] For example, as shown in Figure 7B, the compensation circuit 128 may be implemented as a third transistor T3. The gate of the third transistor T3 is connected to the second scan line (second scan signal terminal Ga2) to receive the second scan signal, the first pole of the third transistor T3 is connected to the control terminal 131 (first node N1) of the drive circuit 122, and the second pole of the third transistor T3 is connected to the second terminal 133 (third node N3) of the drive circuit 122.

[0120] For example, as shown in Figure 7B, the memory circuit 127 may be implemented as a memory capacitor Cst, which includes a first capacitor electrode C1 and a second capacitor electrode C2, the first capacitor electrode C1 being connected to a first voltage terminal VDD and the second capacitor electrode C2 being connected to a control terminal 131 of the drive circuit 122.

[0121] For example, as shown in Figure 7B, the first light emission control circuit 123 may be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light emission control line (first light emission control terminal EM1) to receive the first light emission control signal, the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, and the second pole of the fourth transistor T4 is connected to the first terminal 132 (second node N2) of the drive circuit 122.

[0122] For example, the light-emitting device EM may be specifically implemented as a light-emitting diode (OLED), the first electrode layer (in this case, the anode) of which is connected to the fourth node N4 and configured to receive a drive current from the second terminal 133 of the drive circuit 122 by the second light-emitting control circuit 124, and the second electrode layer (in this case, the cathode) of the light-emitting device EM is connected to the second voltage terminal VSS and configured to receive the second power supply voltage. For example, the second voltage terminal may be grounded, i.e., VSS may be 0V.

[0123] For example, the second light emission control circuit 124 may be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light emission control line (second light emission control terminal EM2) to receive the second light emission control signal, the first pole of the fifth transistor T5 is connected to the second terminal 133 (third node N3) of the drive circuit 122, and the second pole of the fifth transistor T5 is connected to the first terminal 134 (fourth node N4) of the light emission device EM.

[0124] For example, the reset circuit 129 may include a first reset circuit and a second reset circuit, the first reset circuit being configured to apply a first reset voltage Vini1 to a first node N1 in response to a first reset signal Rst1, and the second reset circuit being configured to apply a second reset voltage Vini2 to a fourth node N4 in response to a second reset signal Rst2. For example, as shown in Figure 7B, the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7. The gate of the sixth transistor T6 is connected to a first reset control terminal Rst1 to receive the first reset signal Rst1, the first pole of the sixth transistor T6 is connected to a first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second pole of the sixth transistor T6 is connected to a first node N1. The gate of the seventh transistor T7 is connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second pole of the seventh transistor T7 is connected to the fourth node N4.

[0125] The transistors used in the embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics, and in the embodiments of this disclosure, thin-film transistors will be used as examples. The source and drain of the transistors used here may have symmetrical structures, and therefore, their source and drain may have the same structure. In the embodiments of this disclosure, in order to distinguish between the two poles of the transistor excluding the gate, one is directly described as the first pole and the other as the second pole.

[0126] For example, as shown in Figure 1, the first signal line S1 is a light emission control line EMT, used to transmit the first light emission control signal EM1 and the second light emission control signal EM2, and the second signal line S2 is a reset voltage line VNT, used to transmit the first reset voltage Vinit1 and the second reset voltage Vini2. For example, on the side of the reset voltage line VNT away from the light emission control line EMT, there is further a reset control line RST, which is used to transmit the first reset signal Rst1 and the second reset signal Rst2.

[0127] The layout design of the above-mentioned pixel driving circuit will be described in detail below.

[0128] For example, Figure 8 shows a schematic diagram of the semiconductor layer of the display substrate, which is used to form the active layer of thin-film transistors T1-T7 of the pixel driving circuits for multiple subpixels. Figure 8 shows two rows of subpixel pixel driving circuits. Hereinafter, the pixel driving circuits for four directly adjacent subpixels (i.e., the first subpixel 100a, the second subpixel 100b, the third subpixel 100c, and the fourth subpixel 100d) will be described as an example. The dashed lines in the figure indicate the region where the pixel driving circuit for each subpixel is located, and the embodiments of this disclosure are not limited to this layout.

[0129] For example, a first gate insulating layer is further provided on the semiconductor layer, and although not shown, the first gate insulating layer 1024 in Figure 5 can be seen.

[0130] For example, Figure 9A shows a schematic diagram of the first gate metal layer of a display substrate, which is provided on the first gate insulating layer, and Figure 9B shows a schematic diagram of the first gate metal layer and semiconductor layer of the display substrate stacked together.

[0131] For example, as shown in Figures 9A and 9B, the first gate metal layer includes multiple light emission control lines (EMT), multiple reset control lines (RST), multiple scan lines (GATE), and the first capacitor electrode C1 of multiple memory capacitors (Cst). For example, the portions of the light emission control lines (EMT), reset control lines (RST), scan lines (GATE), and the first capacitor electrode C1 of the memory capacitors (Cst) that overlap with the active layer of the thin-film transistors T1-T7 constitute the gate of the thin-film transistors T1-T7. Each of the multiple light emission control lines (EMT), multiple reset control lines (RST), and multiple scan lines (GATE) is electrically connected in a one-to-one correspondence with multiple rows of subpixels to provide the corresponding electrical signals.

[0132] For example, a second gate insulating layer is further provided on the first gate metal layer, and although not shown, the second gate insulating layer 1025 in Figure 5 can be seen.

[0133] Figure 10A shows a schematic diagram of the second gate metal layer of the display substrate, which is provided on the second gate insulating layer, and Figure 10B shows a schematic diagram of the display substrate with the second gate metal layer, the first gate metal layer and the semiconductor layer stacked on top of each other.

[0134] For example, as shown in Figures 10A and 10B, the second gate metal layer includes a second capacitor electrode C2 of a memory capacitor Cst and a plurality of reset voltage lines VNT. The second capacitor electrode C2 of the memory capacitor Cst overlaps at least partially with the first capacitor electrode C1 to form a capacitor. The plurality of reset voltage lines VNT are electrically connected in a one-to-one correspondence to multiple rows of subpixels to provide the corresponding electrical signals.

[0135] For example, an interlayer insulating layer is further provided on the second gate metal layer, and although not shown, refer to the interlayer insulating layer 1026 in Figure 5.

[0136] Figure 11A shows a schematic diagram of the first source-drain metal layer of the display substrate, which is provided on an interlayer insulating layer, and Figure 11B shows a schematic diagram of the display substrate with the first source-drain metal layer, second gate metal layer, first gate metal layer, and semiconductor layer stacked.

[0137] As shown in Figures 11A and 11B, the first source-drain metal layer includes a plurality of first power lines VDD1. For example, each of the plurality of first power lines VDD1 is electrically connected in a one-to-one correspondence to a plurality of rows of subpixels to provide a first power supply voltage. For example, the first source-drain metal layer further includes a plurality of data lines DT. The plurality of data lines DT are electrically connected in a one-to-one correspondence to a plurality of rows of subpixels to provide data signals. For example, the first source-drain metal layer further includes a plurality of connecting electrodes CL, which are used to connect a second capacitor electrode C2 to the first electrode of a third transistor T3, or to connect a first electrode line VNT to a sixth transistor T6, or to connect a second electrode of a fifth transistor T5 to the first electrode layer of a light-emitting device, etc.

[0138] For example, a passivation layer and a planarization layer are further provided on the first source-drain metal layer. Although not shown, refer to the passivation layer 1027 and the planarization layer 1091 in Figure 5.

[0139] Figure 12A shows a schematic diagram of the second source-drain metal layer of the display substrate, which is provided on the planarization layer 1091. Figure 12B shows a schematic diagram of the display substrate with the second source-drain metal layer, the first source-drain metal layer, the second gate metal layer, the first gate metal layer, and the semiconductor layer stacked on top of each other.

[0140] As shown in Figures 12A and 12B, the second source-drain metal layer includes a second power line VDD2, which is grid-like. For example, the second power line VDD2 is electrically connected to the first power line VDD1, thereby contributing to a reduction in resistance in the power line, reducing the voltage drop in the power line, and contributing to the uniform transmission of the first power supply voltage to each sub-pixel of the display board. For example, the second source-drain metal layer may further include a connecting electrode 1043 used to connect the first electrode layer of the light-emitting device to the first electrode of the first transistor T1.

[0141] For example, another planarization layer is provided on the second source-drain metal layer, and although not shown, refer to the planarization layer 109 in Figure 5, which contains multiple vias VA.

[0142] Figure 13A shows a schematic diagram of the first electrode material layer of the display substrate, which is provided on the passivation layer 109. Figure 13B shows a schematic diagram of the display substrate with the first electrode material layer, second source-drain metal layer, first source-drain metal layer, second gate metal layer, first gate metal layer, and semiconductor layer stacked.

[0143] As shown in Figures 13A and 13B, the first electrode material layer includes the first electrode layers of multiple subpixel light-emitting devices EM, and each of the first electrode layers of the multiple subpixel light-emitting devices EM is connected to the connecting electrode 1043 by multiple vias VA in the planarization layer 109. For example, the light-emitting material layer of the light-emitting device EM is provided on the first electrode layer, and the second electrode layer is provided on the light-emitting material layer.

[0144] For example, other functional layers such as an encapsulation layer and a black matrix layer are further formed above the light-emitting device EM, but these will not be described in detail here.

[0145] At least one embodiment of the present disclosure further provides a display device, Figure 15 showing a schematic cross-sectional view of the display device, which includes a display substrate according to an embodiment of the present disclosure, the display substrate in Figure 2 shown in the figure as an example.

[0146] For example, in some embodiments, the display device further includes a patterned touch surface S and an image sensor array 30, where, for example, the surface of a protective cover plate 115 is realized as the patterned touch surface S. The image sensor array is located on the side of the drive circuit layer 102 away from the light-emitting device layer and includes a plurality of image sensors 31 (one is illustrated as an example), the plurality of image sensors 31 being configured to receive light emitted from a plurality of light-emitting devices EM in the light-emitting device layer and reflected by the pattern on the patterned touch surface S (e.g., fingerprint, palm print, etc.), which passes through the second light-transmitting aperture 1132 and reaches the plurality of image sensors 31 for pattern acquisition.

[0147] For example, as shown in Figure 15, the drive circuit layer includes a plurality of light-transmitting sections 1020, and one second light-transmitting opening 1132 corresponds to one light-transmitting section 1020. In this case, the plurality of image sensors 31 are configured to receive light that is emitted from a plurality of light-emitting devices EM in the light-emitting device layer, reflected by the pattern on the pattern touch surface S, and passes through the plurality of second light-transmitting openings 1132 in the black matrix layer and the plurality of light-transmitting sections 1020 in the drive circuit layer to reach the plurality of image sensors 31 in order to collect patterns. As a result, the plurality of image sensors 31 can sufficiently receive light reflected by the pattern through the plurality of second light-transmitting openings 1132 and the plurality of light-transmitting sections 1020, thereby improving the pattern recognition speed and pattern recognition accuracy.

[0148] The display devices according to the embodiments of this disclosure may further have other structures, which can be specifically described by referring to related technologies and will not be described in detail here.

[0149] Furthermore, the following points need to be explained.

[0150] (1) The drawings of the embodiments of this disclosure relate only to structures relevant to the embodiments of this disclosure, and other structures should be referred to by the usual design.

[0151] (2) For clarity, in the drawings illustrating embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, i.e., these drawings are not drawn to actual scale. To make it clear, when it is stated that an element such as a layer, film, region or substrate is located "above" or "below" another element, the element may be located "directly" above or below the other element, or an intermediate element may be present.

[0152] (3) New embodiments can be obtained by combining the embodiments and features of the embodiments herein, as long as they do not contradict each other.

[0153] While specific embodiments of this disclosure have been described above, the scope of protection of this disclosure is not limited thereto, and should be governed by the scope of protection of the claims.

Claims

1. A display substrate having a plurality of subpixels arranged in a plurality of rows and a plurality of columns, comprising a base substrate, a drive circuit layer provided on the base substrate, a light-emitting device layer provided on the side of the drive circuit layer away from the base substrate, and a black matrix layer provided on the side of the light-emitting device layer away from the base substrate, Each of the plurality of subpixels includes a pixel driving circuit provided in the driving circuit layer and a light-emitting device provided in the light-emitting device layer, and the pixel driving circuit is configured to drive the light-emitting device. The drive circuit layer includes a first signal line and a second signal line that are provided parallel to each other and arranged periodically. The plurality of subpixels in the plurality of rows and columns includes at least one first subpixel in one row, and at least one second subpixel in one row that is adjacent to the first subpixel in the at least one row and located below the first subpixel in the at least one row. The pixel driving circuit for at least one row of first subpixels shares one light emission control line and one reset voltage line, and the pixel driving circuit for at least one row of second subpixels shares one light emission control line and one reset voltage line. The black matrix layer includes a plurality of first light-transmitting apertures and a plurality of second light-transmitting apertures, each of the plurality of first light-transmitting apertures exposing the light-emitting devices of the plurality of subpixels, and each of the plurality of second light-transmitting apertures is provided between the plurality of first light-transmitting apertures. Between the orthographic projection on the base substrate of the light emission control line shared by the pixel driving circuit of at least one row of first subpixels and the orthographic projection on the base substrate of the reset voltage line shared by the pixel driving circuit of at least one row of second subpixels, the orthographic projection on the base substrate of one row of second light-transmitting apertures is included. Display board.

2. The display board according to claim 1, wherein the first signal line is a light emission control line and the second signal line is a reset voltage line.

3. The drive circuit layer includes a third signal line and a fourth signal line that are provided parallel to each other and arranged periodically, and the third signal line and the fourth signal line intersect with the first signal line and the second signal line, respectively. The display board according to claim 1, wherein the orthographic projections of the plurality of second light-transmitting apertures on the base substrate are each located between the orthographic projection of one third signal line on the base substrate and the orthographic projection of one fourth signal line adjacent to the one third signal line on the base substrate.

4. The display board according to claim 3, wherein the first signal line and the second signal line are configured to provide different electrical signals to the plurality of subpixels, and the third signal line and the fourth signal line are configured to provide different electrical signals to the plurality of subpixels.

5. The display board according to claim 4, wherein the third signal line is a first power line and the fourth signal line is a data line.

6. The first signal line, the second signal line, the third signal line, and the fourth signal line define a plurality of first regions, The display substrate according to claim 4, wherein the orthographic projections of the plurality of second light-transmitting apertures on the base substrate are each located within the orthographic projections of the plurality of first regions on the base substrate, or the orthographic projections of the plurality of second light-transmitting apertures on the base substrate each partially overlap with the orthographic projections of the plurality of first regions on the base substrate.

7. The pixel driving circuit includes a thin-film transistor and a memory capacitor, the thin-film transistor includes a gate provided on the base substrate, the memory capacitor includes a first capacitor electrode and a second capacitor electrode provided on the base substrate, the second capacitor electrode is provided on the side of the first capacitor electrode away from the base substrate, The light emission control signal line is provided in the same layer as the gate and the first capacitor electrode. The reset voltage line is provided in the same layer as the second capacitor electrode. The display board according to claim 2.

8. The drive circuit layer further includes a planarization layer provided on the side away from the base substrate, and a pixel definition layer located on the side away from the base substrate of the planarization layer, wherein the pixel definition layer includes a plurality of subpixel apertures. The light-emitting device includes a first electrode layer, a light-emitting material layer, and a second electrode layer, which are stacked in order away from the base substrate, the first electrode layer being provided on the side of the planarization layer away from the base substrate, the pixel definition layer being provided on the side of the first electrode layer away from the base substrate, and the plurality of sub-pixel apertures each expose the first electrode layer of the light-emitting device of the plurality of sub-pixels. In a direction perpendicular to the surface of the base substrate, the plurality of subpixel apertures and the plurality of first light-transmitting apertures correspond one-to-one and overlap. The display substrate according to any one of claims 1 to 6, wherein in a corresponding subpixel aperture and a first light-transmitting aperture, the planar shape of the subpixel aperture and the planar shape of the first light-transmitting aperture are the same in a direction parallel to the surface of the base substrate.

9. The drive circuit layer includes a plurality of light-transmitting portions, and the plurality of light-transmitting portions are light-transmitting in a direction perpendicular to the surface of the base substrate. At least some of the plurality of second light-transmitting openings are provided in a one-to-one correspondence with at least some of the plurality of light-transmitting portions, and are configured to transmit light that forms a predetermined angular range with the surface of the base substrate. The display substrate according to any one of claims 3-6, wherein the first signal line, the second signal line, the third signal line, the fourth signal line, and the plurality of connecting electrodes jointly define the plurality of light-transmitting portions.

10. The display substrate according to claim 9, wherein in the correspondingly provided second light-transmitting opening and light-transmitting portion, the planar shape of the second light-transmitting opening and the planar shape of the light-transmitting portion are at least partially the same in a direction parallel to the plate surface of the base substrate.

11. The display substrate according to claim 9, wherein in the correspondingly provided second light-transmitting opening and light-transmitting portion, the planar shape of the second light-transmitting opening is circular and the planar shape of the light-transmitting portion is polygonal in a direction parallel to the plate surface of the base substrate.

12. The display substrate according to any one of claims 1 to 6, wherein one second light-transmitting aperture is provided corresponding to every two subpixels among the plurality of subpixels.

13. The display substrate according to claim 12, wherein the distance between two adjacent second light-transmitting apertures among the plurality of second light-transmitting apertures is 50 μm - 60 μm.

14. The planarization layer includes a plurality of vias, and the first electrode layer of the light-emitting device of the plurality of subpixels is electrically connected to the pixel driving circuit of the plurality of subpixels by the plurality of vias. The display substrate according to claim 8, wherein the multiple vias corresponding to multiple subpixels located in the same row include a first via, a second via, and a third via, and the first straight line penetrates the first via and the second via, but does not penetrate the third via.

15. The display substrate according to claim 8, wherein the orthographic projection of the subpixel aperture on the base substrate is located within the orthographic projection of the first light-transmitting aperture on the base substrate.

16. A display device comprising a display board according to any one of claims 1 to 6.

Images