Display panels and display devices

Abstract

To provide a display panel and a display device. [Solution] The display panel includes a first display area, a second display area located on one side of the first display area, a plurality of subpixels located in at least the first and second display areas, a plurality of pixel groups located in the first display area, wherein at least one of the plurality of pixel groups includes at least two subpixels, and a first power line configured to provide a first voltage signal to the pixel circuit, including a plurality of first conductors and a plurality of second conductors, wherein at least one of the plurality of first conductors includes a first subwire extending along a first direction and a second subwire extending along a second direction, and the second subwire is electrically connected to at least one of the plurality of second conductors. The display panel provides greater stability to the mesh structure of the first power line, reduces voltage drop in the first power line, and thereby improves the uniformity of the brightness of the display panel.

Description

Technical Field

[0001] This disclosure claims the priority of Chinese Patent Application No. 202010621890.3, filed on June 30, 2020, and the entire content disclosed in the above Chinese patent application is incorporated herein by reference as part of this disclosure.

[0002] At least one embodiment of this disclosure relates to a display panel and a display device.

Background Art

[0003] Based on the design of an under-screen camera, a display panel usually includes a high pixel density (Pixels Per Inch, PPI) region and a low PPI region. However, in a general display panel, the light transmittance of the low PPI region is low, which is disadvantageous for improving the display effect in the imaging region of the camera.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a display panel comprising: a first display area; a second display area located at least to one side of the first display area; a plurality of subpixels located in the first and second display areas, wherein the density of subpixels in the first display area is less than the density of subpixels in the second display area, the subpixels comprising a plurality of subpixels including a pixel circuit; a plurality of pixel groups located in the first display area, wherein at least one of the plurality of pixel groups comprises at least two subpixels; and a first power line configured to provide a first voltage signal to the pixel circuit, wherein the first power line comprises a plurality of first conductors and a plurality of second conductors, and the plurality The first conductor extends from the second display area to the first display area and is electrically connected to the plurality of pixel groups, the plurality of second conductors are located in the first display area and between adjacent first conductors, the plurality of second conductors extend along a first direction, adjacent second conductors are spaced apart from each other along the first direction, the plurality of second conductors are electrically connected to the plurality of pixel groups, at least one of the plurality of first conductors includes a first sub-wiring extending along a first direction and a second sub-wiring extending along a second direction, the first direction and the second direction intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conductors.

[0005] For example, in a display panel according to at least one embodiment of the present disclosure, the at least two subpixels include a first subpixel and a second subpixel arranged along the first direction, at least one of the plurality of second conductors electrically connects the first subpixel and the second subpixel, and the second subwire and the plurality of second conductors are located in different layers.

[0006] For example, in a display panel according to at least one embodiment of the present disclosure, the subpixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor each being connected to the second transistor, the second transistor being connected to the light-emitting element, and the first transistor including a first active part and a second active part connected via a conductive part.

[0007] For example, in a display panel according to at least one embodiment of the present disclosure, the second wire further includes a connecting arm that is spaced apart from and partially overlaps in a third direction with respect to the conductive portion of a subpixel in the pixel group that overlaps with the second wire, the third direction being perpendicular to the first direction and perpendicular to the second direction.

[0008] For example, in a display panel according to at least one embodiment of the present disclosure, the shape of the connecting arm includes a C-shape.

[0009] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of pixel groups includes a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected by a plurality of wires.

[0010] For example, a display panel according to at least one embodiment of the present disclosure further includes connecting wires, wherein the orthographic projection on the base substrate of at least two of the plurality of wirings between adjacent first and second pixel groups lies within the orthographic projection on the base substrate of the connecting wires.

[0011] For example, in a display panel according to at least one embodiment of the present disclosure, there are a plurality of gaps between the plurality of wirings, and the orthographic projection of at least one of the plurality of gaps on the base substrate at least partially overlaps with the orthographic projection of the connecting conductor on the base substrate.

[0012] For example, in a display panel according to at least one embodiment of the present disclosure, the pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control line, and an initialization signal line, each providing the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control line, and an initialization signal, wherein the plurality of wires are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light emission control line, the initialization signal line, and the first conductor.

[0013] For example, in a display panel according to at least one embodiment of the present disclosure, the connecting wire has a stopper installed on the same layer as the connecting wire and integrally formed therewith, the subpixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor and a storage capacitor, the first transistor is connected to the second transistor and the storage capacitor, respectively, the second transistor is connected to the light-emitting element, the first transistor includes a first active part and a second active part connected via a conductive part, the stopper and the conductive part of one pixel unit in the pixel group that overlaps with the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

[0014] For example, in a display panel according to at least one embodiment of the present disclosure, at least a portion of the orthographic projection of the connecting conductor on the base substrate is located between the orthographic projections of the adjacent first and second pixel groups on the base substrate.

[0015] For example, in a display panel according to at least one embodiment of the present disclosure, the first reset signal line, second reset signal line, gate line, light emission control line, initialization signal line, and second conductor of the first pixel group are connected to the first reset signal line, second reset signal line, gate line, light emission control line, initialization signal line, and second conductor of the second pixel group, respectively, via the plurality of wirings.

[0016] For example, in a display panel according to at least one embodiment of the present disclosure, the connecting conductor and the second conductor are located on the same layer and integrally formed, or the connecting conductor and the initialization signal line are located on the same layer and integrally formed, or the connecting conductor and the first conductor are located on the same layer.

[0017] For example, in a display panel according to at least one embodiment of the present disclosure, the at least two subpixels further include a third subpixel and a fourth subpixel, the third subpixel and the fourth subpixel being arranged along the first direction and located on one side of the first subpixel and the second subpixel along the second direction, and being electrically connected to another of the plurality of second conductors, and the second subwire being electrically connected to at least one of the plurality of second conductors.

[0018] For example, in a display panel according to at least one embodiment of the present disclosure, the second subwiring is located on a different layer from the second subwiring and has a stopper connected by a via, and the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

[0019] For example, in a display panel according to at least one embodiment of the present disclosure, the first direction is perpendicular to the second direction.

[0020] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of second conductors are arranged sequentially along the first direction.

[0021] For example, in a display panel according to at least one embodiment of the present disclosure, the adjacent second conductors are not directly connected.

[0022] For example, in a display panel according to at least one embodiment of the present disclosure, the first conductor and the second conductor are connected by vias that penetrate an insulating layer.

[0023] For example, in the display panel according to at least one embodiment of the present disclosure, the first power line further includes a third conductor and a fourth conductor. The third conductor extends along the second direction and extends from the second display area to the first display area. The second conductor is electrically connected to the third conductor. The fourth conductor extends along the second direction, the second conductor is electrically connected to the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

[0024] For example, in the display panel according to at least one embodiment of the present disclosure, a plurality of fourth conductors located between adjacent third conductors and arranged in sequence along the second direction are included, and adjacent fourth conductors are installed at intervals from each other in the second direction.

[0025] For example, in the display panel according to at least one embodiment of the present disclosure, the first conductor and the third conductor are located in the same layer, and the fourth conductor and the third conductor are located in the same layer.

[0026] For example, in the display panel according to at least one embodiment of the present disclosure, the first display area includes a plurality of light transmission areas located between adjacent pixel groups.

[0027] For example, in the display panel according to at least one embodiment of the present disclosure, the plurality of pixel groups and the wiring connected to the adjacent pixel groups surround the plurality of light transmission areas.

[0028] At least one embodiment of the present disclosure further provides a display device including the display panel according to any embodiment of the present disclosure.

[0029] For example, the display device according to at least one embodiment of the present disclosure further includes a sensor. The sensor is installed on one side of the display panel, and the orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.

[0030] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the drawings of the embodiments are briefly described below, and it is clear that the drawings described below represent only a few embodiments of this disclosure and do not limit the disclosure. [Brief explanation of the drawing]

[0031] [Figure 1A] Figure 1A is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1B] Figure 1B is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1C] Figure 1C is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 2] Figure 2 is a schematic diagram of a second display area of ​​a display panel according to at least one embodiment of the present disclosure. [Figure 3] Figure 3 is a schematic diagram of a first display area of ​​a display panel according to at least one embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic diagram of subpixels and signal lines providing signals to subpixels in a display panel according to at least one embodiment of the present disclosure. [Figure 5] Figure 5 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 6A] Figure 6A is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 6B] Figure 6B is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 6C] Figure 6C is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 6D] Figure 6D is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 6E] Figure 6E is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 6F] Figure 6F is a diagram of a pixel circuit and its stacked structure according to some embodiments of the present disclosure. [Figure 7] Figure 7 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 8A] Figure 8A is a schematic diagram of the region A11 shown in Figure 7, after enlargement. [Figure 8B] Figure 8B is a schematic diagram of region A12 shown in Figure 7, after enlargement. [Figure 8C] Figure 8C is a plan view of the semiconductor pattern of the display panel shown in Figure 7. [Figure 9] Figure 9 is a plan view of the first conductive pattern layer of the display panel shown in Figure 7. [Figure 10] Figure 10 is a plan view of the second conductive pattern layer of the display panel shown in Figure 7. [Figure 11] Figure 11 is a plan view of the third conductive pattern layer of the display panel shown in Figure 7. [Figure 12] Figure 12 is a plan view of another display panel according to at least one embodiment of the present disclosure. [Figure 13] Figure 13 is a schematic diagram of region A21 shown in Figure 12, after enlargement. [Figure 14] Figure 14 is a plan view of the semiconductor pattern of the display panel shown in Figure 12. [Figure 15] Figure 15 is a plan view of the first conductive pattern layer of the display panel shown in Figure 12. [Figure 16] Figure 16 is a plan view of the second conductive pattern layer of the display panel shown in Figure 12. [Figure 17] Figure 17 is a plan view of the third conductive pattern layer of the display panel shown in Figure 12. [Figure 18] Figure 18 is a schematic diagram of another display panel relating to at least one embodiment of the present disclosure. [Figure 19] Figure 19 is a plan view of the semiconductor pattern of the display panel shown in Figure 18. [Figure 20] Figure 20 is a plan view of the first conductive pattern layer of the display panel shown in Figure 18. [Figure 21]Figure 21 is a plan view of the second conductive pattern layer of the display panel shown in Figure 18. [Figure 22] Figure 22 is a plan view of the third conductive pattern layer of the display panel shown in Figure 18. [Figure 23] Figure 23 is a schematic cross-sectional view of a pixel circuit of a display panel according to at least one embodiment of the present disclosure. [Figure 24] Figure 24 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure. [Figure 25] Figure 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0032] To more clearly explain the purpose, technical proposals, and advantages of the embodiments of this disclosure, the technical proposals of the embodiments of this disclosure will be clearly and completely described below with reference to the drawings of the embodiments of this disclosure. Clearly, the embodiments described are only a selection of embodiments of this disclosure, not all embodiments. All other embodiments that a person skilled in the art could obtain without creative work based on the embodiments of this disclosure described are all within the scope of protection of this disclosure.

[0033] Unless otherwise defined, technical and scientific terms used in this disclosure should have the ordinary meanings that a person skilled in the art would understand. Terms such as “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are used solely to distinguish different components. Similarly, similar terms such as “includes” or “equip” mean that the element or component listed before the term covers the element or component and its equivalents listed after the term, but do not exclude other elements or components. Similar terms such as “connected” or “bonded” may include direct or indirect electrical connections, not limited to physical or mechanical connections. Terms such as “up,” “down,” “left,” and “right” are used solely to indicate relative positions, and such relative positions may change as the absolute position of the subject changes.

[0034] Because people love taking selfies, a front camera is necessary. However, the front camera and sensor occupy some space, and traditionally, methods for positioning the front camera have involved using a notch screen, a teardrop notch screen, or an AA hole (Active Area), meaning that a hole is made within the AA area and both the camera hole and sensor are placed within the AA area. However, neither of these two methods can meet the needs of a full screen. Therefore, by selecting under-screen camera technology, the aperture ratio of the screen is improved by changing the pixel density, and the camera is placed at the bottom of the screen, so that the completeness of the full-screen display is not compromised.

[0035] To achieve a bezel-less full-screen design, under-screen camera technology must be used, which requires a large aperture ratio for the display panel. Therefore, while meeting the above needs, how to configure the display panel structure to ensure the display effect is a pressing issue that needs to be resolved urgently.

[0036] At least one embodiment of the present disclosure provides a display panel comprising: a first display area; a second display area located at least to one side of the first display area; a plurality of subpixels located in the first and second display areas, wherein the density of subpixels in the first display area is less than the density of subpixels in the second display area, the subpixels comprising a plurality of subpixels including a pixel circuit; a plurality of pixel groups located in the first display area, wherein at least one of the plurality of pixel groups comprises a plurality of pixel groups including at least two subpixels; and a first power line configured to provide a first voltage signal to the pixel circuit, wherein the first power line comprises a plurality of first conductors and a plurality of second conductors, and a plurality of first The conductor extends from a second display area to a first display area and is electrically connected to a plurality of pixel groups, the plurality of second conductors are located in the first display area and between adjacent first conductors, the plurality of second conductors extend along a first direction, adjacent second conductors are spaced apart from each other along the first direction, and the plurality of second conductors include a first power line electrically connected to a plurality of pixel groups, at least one of the plurality of first conductors includes a first sub-wiring extending along a first direction and a second sub-wiring extending along a second direction, the first and second directions intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conductors.

[0037] The display panel according to the embodiment of this disclosure improves the stability of the mesh structure of the first power line, reduces the voltage drop in the first power line, and thereby improves the uniformity of the brightness of the display panel, thereby improving the display effect in the imaging area of ​​the camera.

[0038] The embodiments of this disclosure will be described in detail below with reference to the drawings.

[0039] In typical display panels, a mesh structure is used for the first power line in both high-PPI and low-PPI regions. To improve the stability of the mesh structure of the first power line, reduce voltage drop in the first power line, and increase the uniformity of the brightness of the display panel, thereby improving the display effect in the camera's imaging region, the display panel according to the embodiment of this disclosure optimizes the signal lines in the low-PPI region. For example, in the embodiment of this disclosure, the horizontally and vertically arranged conductors of the mesh first power line are optimized.

[0040] Figures 1A to 1C are schematic diagrams of display panels according to some embodiments of the present disclosure. As shown in Figures 1A to 1C, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is a low-pixel density (Pixels Per Inch, PPI) area, and the second display area R2 is a high-PPI area. The first display area R1 is a partially light-transmitting area. As shown in Figures 1A to 1C, the second display area R2 is located at least on one side of the first display area R1. The display panels shown in Figures 1A and 1B further include a third area R3. A sensor, such as a camera, may be installed in the first display area R1 (see Figure 1C), or in the first display area R1 and the third area R3 (see Figures 1A and 1B). The third area R3 shown in Figures 1A and 1B may be a perforated area, i.e., the material at the location corresponding to the third area R3 is removed to form a through-hole. The sensor can receive ambient light. Taking a camera as an example, by implementing an under-screen camera, when the screen is used normally, the first display area corresponding to the sensor can display the screen normally. However, when the camera is capturing an image, the first display area can transmit ambient light, supporting normal use. For example, the sensor is installed on the non-display side of the display panel. The sensor is also called an under-screen device.

[0041] Figure 1A further illustrates a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 include a first gate line GL1, and the plurality of data lines 313 include a first data line DL1. The first gate line GL1 extends from the second display area R2 to the first display area R1. The first data line DL1 extends from the first display area R1 to the second display area R2. In embodiments of this disclosure, the extension of an element from the first display area R1 to the second display area R2 may be understood as the element being located in the first display area R1 and the second display area R2, or as the extension of an element from the second display area R2 to the first display area R1. For clarity in the illustration, Figure 1A illustrates some gate lines 113 and some data lines 313, and the number of gate lines 113 and data lines 313 may be determined as needed. The plurality of gate lines 113 and the plurality of data lines 313 intersect with each other and are insulated from each other.

[0042] Figure 2 is a schematic diagram of a second display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 3 is a schematic diagram of a first display area of ​​a display panel according to at least one embodiment of the present disclosure. As shown in Figures 2 and 3, the display panel includes a plurality of subpixels P0, the plurality of subpixels P0 including a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104. For example, the display panel includes a plurality of pixel groups P1 located in a first display area R1, and at least one of the plurality of pixel groups P1 includes at least two subpixels. For example, in some embodiments, a pixel group P1 may include four subpixels, for example, as shown in Figure 3, one first subpixel 101, one second subpixel 102, one third subpixel 103, and one fourth subpixel 104 constitute one pixel group P1. For example, in some other embodiments, a pixel group P1 may include two subpixels, for example, as shown in Figure 5, one first subpixel 101 and one second subpixel 102 constitute one pixel group P1. For example, a pixel group P1 may further include three subpixels (see Figure 18), and embodiments of this disclosure are not limited thereto. For example, a pixel group P1 is a repeating unit, arranged in an array in a second display area R2. As shown in Figure 3, in the first display area R1, a pixel group P1 is also called a pixel island P1, and the following embodiments are the same, so a detailed explanation is omitted. The first display area R1 includes a plurality of light-transmitting areas R0 located between adjacent pixel islands P1. The light-transmitting region R0 can transmit ambient light. For example, the light-transmitting region R0 may include a base substrate and a transparent insulating layer located on the base substrate, and the light-transmitting region R0 has no light-shielding structure, for example, no metal wiring. For example, the light-transmitting region R0 is located within a region surrounded by four adjacent pixel islands P1, but is not limited to this. For example, as shown in Figure 3, adjacent pixel islands P1 are spaced apart.

[0043] For example, the length of each of the multiple light-transmitting regions R0 is approximately the same as the length of a single subpixel. For example, wiring connected to a group of pixels and adjacent groups of pixels surrounds multiple light-transmitting regions R0.

[0044] For example, in the example shown in Figure 7, one pixel island may further include two subpixels, for example, a first subpixel 101 and a second subpixel 102, for example, the first subpixel 101 being a red subpixel and the second subpixel 102 being a green subpixel. For example, in the embodiment shown in Figure 18, one pixel island P1 may further include three subpixels, for example, a first subpixel 101, a second subpixel 102, and a third subpixel 103, for example, the first subpixel 101 being a red subpixel, the second subpixel 102 being a green subpixel and the third subpixel 103. Pixel 103 is a blue subpixel, and for example, the three subpixels are located in a row. For example, in the example shown in Figure 12, one pixel island may further include four subpixels, for example, a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104, for example, the first subpixel 101 is a red subpixel, the second subpixel 102 is a green subpixel, the third subpixel 103 is a blue subpixel, and the fourth subpixel 104 is a green subpixel. In other embodiments, the pixel group may use pixel units of other colors. Of course, in other embodiments, the arrangement of the multiple subpixels P0 in the display panel is not limited to those shown in Figures 2 and 3. The embodiments of this disclosure are not limited thereto.

[0045] As shown in Figures 2 and 3, multiple subpixels P0 are located in the first display area R1 and the second display area R2, and the density of pixel units in the first display area R1 is less than the density of pixel units in the second display area R2. Or, the density of subpixels in the first display area R1 is less than the density of subpixels in the second display area R2. The density of pixel units in the first display area R1 shown in Figure 3 is one-quarter of the density of pixel units in the second display area R2. That is, the density of subpixels in the first display area R1 shown in Figure 3 is one-quarter of the density of subpixels in the second display area R2. The arrangement of light-transmitting areas R0 and pixel units in the first display area R1 is not limited to that shown in Figure 3 and may be set as needed. For example, in other embodiments, the density of subpixels in the first display area R1 may be a value other than one-quarter, such as one-half, one-third, one-sixth, or one-eighth of the density of subpixels in the second display area R2, and the embodiments of this disclosure are not limited thereto.

[0046] For example, as shown in Figures 1A and 3, the display panel further includes gate lines 113 and data lines 313. The gate lines 113 and data lines 313 are isolated from each other. Each gate line 113 connects a row of subpixels, and each data line 313 connects a column of subpixels. For example, a gate line 113 is configured to provide a scan signal to a row of subpixels.

[0047] For example, as shown in Figures 1A and 3, data line 313 includes a first data line DL1. The first data line DL1 is located at least in the first display area R1. For example, the first data line DL1 extends from the first display area R1 to the second display area R2.

[0048] For example, as shown in Figures 1A and 3, the gate line includes a first gate line GL1, which extends from the second display area R2 to the first display area R1. As shown in Figure 3, the light transmission area R0 is enclosed by, but is not limited to, two adjacent first gate lines GL1 and two adjacent first data lines DL1.

[0049] Figure 4 is a schematic diagram of subpixels and signal lines that provide signals to subpixels in a display panel according to one embodiment of the present disclosure. As shown in Figure 4, the display panel includes a plurality of subpixels P0, each subpixel P0 including a light-emitting element EMC and a pixel circuit 10 that provides a driving current to the light-emitting element EMC, the light-emitting element EMC being an organic electroluminescent element, which may be an organic light-emitting diode (OLED), for example.

[0050] As shown in Figure 4, the display panel further includes an initialization signal line 210, an illumination control signal line 110, a data line 313, a first power line 311, and a second power line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The illumination control signal line 110 is configured to provide an illumination control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the second power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, with the first voltage signal ELVDD being greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its value may, for example, be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited to this; for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit 10 is controlled by signals such as the scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM, and outputs a drive current to drive the light-emitting element EMC to emit light. As shown in Figure 4, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.

[0051] Figure 5 is a schematic diagram of a display panel according to some embodiments of the present disclosure. In Figure 5, a pixel island P1 is described as containing two subpixels, but each pixel island P1 may contain three or four subpixels, and the specific connection relationships are similar thereto. A detailed explanation is omitted here, and the embodiments of the present disclosure are not limited thereto.

[0052] As shown in Figure 5, the first power line 311 includes a plurality of first conductors L1 and a plurality of second conductors L2. For example, the first power line 311 may further include a plurality of third conductors L3. For example, the first conductor L1 extends from the second display area R2 to the first display area R1 and is electrically connected to a plurality of pixel groups (i.e., pixel islands) P1. The plurality of second conductors L2 are located in the first display area R1 and are located between adjacent first conductors L1, each second conductor L2 extends along the first direction D1, and the plurality of second conductors L2 are electrically connected to a plurality of pixel groups P1. For example, the third conductor L3 is located at least in the first display area R1, for example, the third conductor L3 extends from the second display area R2 to the first display area R1, the third conductor L3 extends along the second direction D2, the first direction D1 and the second direction D2 intersect, and adjacent second conductors L2 are spaced apart from each other along the first direction D1, adjacent second conductors L2 are connected to each other via the first conductor L1, and are connected to the third conductor L3 to receive the first voltage signal ELVDD. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first conductor L1 extends along the first direction D1. For example, in embodiments of this disclosure, the second conductor L2 is located only in the first display area R1. In the embodiments of this disclosure, an element extending along a certain direction is not necessarily a straight line, but may have curved or broken portions. For example, the extending direction of an element is a general tendency of the element to extend, and each portion of the element does not necessarily extend along that direction.

[0053] For example, as shown in Figure 5, the first wire L1 and the second wire L2 are connected to subpixels located in corresponding rows within two adjacent pixel islands P1, but are not limited to this, and in other embodiments, the pixel island P1 may include two or more rows of subpixels. For example, as shown in Figures 6A to 6E, the pixel island P1 includes at least one row of two pixel units, and the second wire L2 overlaps with the two pixel units in that row. For example, as shown in Figure 5, the first wire L1 is located between two adjacent pixel islands P1, and the second wires L2, which overlap with the two adjacent pixel islands P1, are connected via the first wire L1.

[0054] For example, as shown in Figure 5, multiple second conductors L2 are arranged sequentially along the first direction D1. For example, as shown in Figure 5, adjacent second conductors L2 are not directly connected but are connected, for example, by jumper, i.e., via first conductors L1 located in different layers, thereby increasing the stability of the braided structure of the first power line, reducing the voltage drop in the first power line, and thereby increasing the uniformity of the brightness of the display panel. Of course, adjacent second conductors L2 may be directly connected, and the embodiments of this disclosure are not limited thereto.

[0055] For example, as shown in Figure 5, in order to improve the light transmittance of the first display area, the length of the portion of the first conductor L1 located in the first display area R1 in the first direction D1 is longer than the length of the second conductor L2 in the first direction D1.

[0056] For example, as shown in Figure 5, the first power line 311 further includes a fourth conductor L4, the fourth conductor L4 extending along a second direction D2, and the second conductor L2 is connected to the fourth conductor L4 to receive a first voltage signal ELVDD, and the length of the fourth conductor L4 in the second direction D2 is less than or equal to the length of the third conductor L3 in the second direction D2. In the display panel shown in Figure 5, the length of the fourth conductor L4 in the second direction D2 is less than the length of the third conductor L3 in the second direction D2.

[0057] For example, as shown in Figure 5, to further improve the light transmittance of the first display area, multiple fourth conductors L4 are provided, which are arranged sequentially along the second direction D2, with adjacent fourth conductors L4 spaced apart from each other in the second direction D2. For example, as shown in Figure 5, multiple fourth conductors L41 are located between third conductors L31 and L32, where L31 and L32 are adjacent third conductors L3. Although Figure 5 shows five fourth conductors L41, the number of fourth conductors L4 located between adjacent third conductors L3 is not limited to that shown in the figure and may be set as needed. Since multiple fourth conductors L4 are spaced apart from each other in the second direction D2, this is equivalent to eliminating the portion of some first power lines in a typical display panel that is installed along the second direction, thereby reducing wiring, optimizing wiring space, and improving light transmittance.

[0058] For example, as shown in Figure 5, the first power line 311 further includes a fifth conductor L5, which extends along the first direction D1 and is located in the second display area R2, and is installed at a distance from each other along the first direction D1 along the adjacent second conductor L2. As a result, wiring is reduced and light transmittance is improved at the boundary between the first and second display areas.

[0059] The embodiments of this disclosure do not limit the number of pixel units included in each pixel island or the arrangement of the pixel units.

[0060] As shown in Figure 5, in the display panel, the first power line 311 further includes a plurality of sixth conductors L6, which are located in the second display area R2 and extend along the second direction D2. In the second display area R2, the plurality of fifth conductors L5 and the plurality of sixth conductors L6 are installed at an intersection. In the embodiments of this disclosure, both the fifth conductors L5 and the sixth conductors L6 are located only in the second display area R2.

[0061] As shown in Figure 5, the same gate line 113 connects subpixels located in the second display areas on both sides of the first display area R1 to subpixels located within the first display area R1, thereby forming a row of subpixels. In the embodiments of this disclosure, the form of the first conductor is not limited and only needs to extend from the second display area R2 to the first display area R1. The first power line in Figure 5 may be replaced with the first power line in other embodiments of this disclosure. Furthermore, the extension form of the gate line 113 is not limited to that shown in Figure 5, and only needs to be arranged in a way that allows pixels in the second display area R2 to connect to pixels in the first display area R1. For example, in the first display area R1, the gate lines of subpixels in corresponding rows of two adjacent pixel islands are connected via a seventh conductor L7 (i.e., a jumper), and of course, the gate lines of subpixels in corresponding rows of two adjacent pixel islands may be directly connected, and the embodiments of this disclosure are not limited to this.

[0062] For example, the correspondence between the remaining signal lines (e.g., the initialization signal line that provides the initialization signal Vint, the light emission control signal line that provides the light emission control signal EM) and one pixel island P1 is as shown in Figure 5, and the embodiments of this disclosure are not limited thereto, and a detailed explanation is omitted here.

[0063] For example, in the display panel shown in Figure 5, the first conductor and two adjacent second conductors are in contact, for example, by vias that penetrate the insulating layer.

[0064] For example, in the embodiments of this disclosure, a row of subpixels is a subpixel connected to the same gate line 113, and a column of subpixels is a subpixel connected to the same data line 313. In the embodiments of this disclosure, the first, second, and fifth conductors L1, L2, and L5 all extend along the row direction (i.e., the first direction D1), and the third, fourth, and sixth conductors L3, L4, and L6 extend along the column direction (i.e., the second direction D2), but the embodiments are not limited thereto. In other embodiments, the first, second, and fifth conductors L1, L2, and L5 all extend along the column direction, and the third, fourth, and sixth conductors L3, L4, and L6 extend along the row direction, and the second direction D2 and the first direction D1 are replaced by each other accordingly.

[0065] In Figure 5, a pixel island is shown as an example containing two subpixels (e.g., one row of subpixels), but in other embodiments, a pixel island may contain three or more subpixels (e.g., two rows of subpixels), in which case the multiple second wires may be understood as second wires connected to subpixels in the same row on a single pixel island. If the first wire L1, the second wire L2, and the fifth wire L5 all extend along the column direction, and the third wire L3, the fourth wire L4, and the sixth wire L6 extend along the row direction, the multiple second wires may be understood as second wires connected to subpixels in the same column on a single pixel island.

[0066] Hereinafter, several embodiments of this disclosure will be described with reference to Figures 6A to 24. In Figures 6A to 24, the pixel circuit of 7T1C will be described as an example.

[0067] Figure 6A is a schematic diagram of the pixel circuit of a display panel according to one embodiment of the present disclosure. Figure 6B is a plan view of the semiconductor pattern in a display panel according to one embodiment of the present disclosure. Figure 6C is a plan view of the first conductive pattern layer in a display panel according to one embodiment of the present disclosure. Figure 6D is a plan view of the second conductive pattern layer in a display panel according to one embodiment of the present disclosure. Figure 23 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. Figure 24 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. In the embodiments of the present disclosure, for clarity in the illustration, the insulating layer is shown in the form of vias in the plan views, and the insulating layer itself is made transparent.

[0068] However, Figures 6B-6F are hierarchical diagrams of pixel circuits containing two subpixels each, although they may contain more or fewer subpixels, and the structure of the pixel circuit may be designed with the layout of one of the pixels shown in Figures 6B-6F, and the embodiments of this disclosure are not limited thereto. For example, in Figure 6F, the pixel structure of the first subpixel 101 is described as an example, and the pixel structures of the remaining subpixels, such as the second, third, and fourth subpixels, are similar and are not described in detail.

[0069] For example, as shown in Figure 6A, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light emission control line 110 is configured to provide a light emission control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the second power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, with the first voltage signal ELVDD being greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its value may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited to this; for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit is controlled by signals such as the scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM, and outputs a drive current to drive the light-emitting element 20 to emit light. The light-emitting element 20 emits red light, green light, blue light, or white light, etc., under the drive of the corresponding pixel circuit 10.

[0070] As shown in Figure 6A, the pixel circuit 10 includes a drive transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The drive transistor T1 is electrically connected to the light-emitting element 20 and outputs a drive current to drive the light-emitting element 20 to emit light, controlled by signals such as a scan signal SCAN, a data signal DATA, a first voltage signal ELVDD, and a second voltage signal ELVSS.

[0071] For example, a display panel according to an embodiment of the present disclosure further includes a data drive circuit and a scan drive circuit. The data drive circuit is configured to provide a data signal DATA to a sub-pixel P0 in response to a command from the control circuit, and the scan drive circuit is configured to provide signals such as an illumination control signal EM, a scan signal SCAN, a first reset control signal RST1, and a second reset signal RST2 to the sub-pixel P0 in response to a command from the control circuit. For example, the control circuit includes, but is not limited to, an external integrated circuit (IC). For example, the scan drive circuit is a GOA (Gate driver On Array) structure mounted on the display panel or a drive chip (IC) structure bonded to the display panel. For example, different drive circuits may provide the illumination control signal EM and the scan signal SCAN, respectively. For example, the display panel further includes a power supply (not shown) to provide the above voltage signals, which may be a voltage source or a current source as needed, and the power supply is configured to provide a first voltage signal ELVDD, a second voltage signal ELVSS, and an initialization signal Vint, etc., to the sub-pixel P0 via a first power line 311, a second power line 312, and an initialization signal line 210, respectively.

[0072] As shown in Figure 6A, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first pole T21 and second pole T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first pole T11 of the drive transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the drive transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the drive transistor T1.

[0073] For example, as shown in Figure 6A, the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control line 110.

[0074] For example, as shown in Figure 6A, the first pole T41 and second pole T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the drive transistor T1, respectively. The first pole T51 and second pole T52 of the second light-emitting control transistor T5 are electrically connected to the second pole T12 of the drive transistor T1 and the pixel electrode E1 of the light-emitting element 20 (which may be the anode of the OLED), respectively. The common electrode E2 of the light-emitting element 20 (which may be a common electrode of the OLED, such as the cathode) is electrically connected to the second power line 312.

[0075] For example, as shown in Figure 6A, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the drive transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0076] Figure 6B shows the semiconductor pattern SCP, and Figure 6C shows the first conductive pattern layer LY1, with a first gate insulating layer placed between the first conductive pattern layer LY1 and the semiconductor pattern SCP. By doping the semiconductor pattern SCP with the first conductive pattern layer LY1 as a mask, the regions of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retain semiconductor properties, forming a channel for a thin-film transistor, while the regions of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 become conductive, forming a source or drain for a thin-film transistor. Figure 6A shows the active layer ALT formed after the semiconductor pattern SCP has been partially made conductive.

[0077] As shown in Figure 6C, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and the first pole C11 of a storage capacitor C1. Figure 6C further shows the first portion DL11 (conductor 114) of the first data line DL1. For example, as shown in Figure 7, in embodiments of the present disclosure, the gate line 113 of the current row is further connected to the second reset control signal line 112 located in the same row.

[0078] Figure 6D shows the second conductive pattern layer LY2, and a second gate insulating layer is installed between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes stoppers BK0 and BK1, initialization signal line 210, and the second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 for two subpixels of one pixel island is integrally formed and used as the second conductor L2. The second pole C12 of the storage capacitor C1 has an opening OPN. The interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. The first gate insulating layer, the second gate insulating layer and interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3 can be described in the description in this art, and a detailed explanation is omitted here.

[0079] Figure 6E shows the third conductive pattern layer LY3, which includes the first conductor L1, the third conductor L3 (part of the first power line 311), the fourth conductor L4 (part of the first power line 311), the second data line DL12 (part of the data line 313), the first connection electrode 31a, the second connection electrode 31b, the third connection electrode 31c, and the fourth connection electrode 31d.

[0080] For example, as shown in Figure 6E, at least one of a plurality of first conductors L1 includes a first sub-wiring L111 extending along a first direction D1 and a second sub-wiring L112 extending along a second direction D2, the second sub-wiring L112 being electrically connected to at least one of a plurality of second conductors L2. For example, as shown in Figure 11, the second sub-wiring L112 is electrically connected to the second conductor L2 of the corresponding row in an adjacent pixel island. For example, as shown in Figures 13 and 17, the second sub-wiring L112 is electrically connected to two second conductors L2 in one pixel island and two second conductors L2 in an adjacent pixel island. Embodiments of the present disclosure are not limited thereto.

[0081] For example, the second sub-wiring L112 is connected to stopper BK0 by a via that penetrates the interlayer insulation layer, and is connected to the second conductor L2 by a via that penetrates the interlayer insulation layer.

[0082] Figure 6F is a diagram of the stacked structure shown in Figures 6B-6E. As shown in Figures 6B-8A, the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 via a via, the first power line 311 is electrically connected to the first pole T41 of the first light emission control transistor T4 via a via, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 via a via, and the first power line 311 is electrically connected to the conductive block BK1 via a via. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 via a via, the other end of the first connection electrode 31a is connected to the first pole T61 of the first reset transistor T6 via a via, and the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211. One end of the second connecting electrode 31b is electrically connected via a via to the second pole T62 of the first reset transistor T6, and the other end of the second connecting electrode 31b is electrically connected via a via to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1), thereby electrically connecting the second pole T62 of the first reset transistor T6 to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connecting electrode 31c is electrically connected via a via to the second initialization signal line 212, and the other end of the third connecting electrode 31c is connected via a via to the first pole T71 of the second reset transistor T7, further electrically connecting the first pole T71 of the second reset transistor T7 to the second initialization signal line 212. The fourth connecting electrode 31d is electrically connected via a via to the second pole T52 of the second light emission control transistor T5. The fourth connecting electrode 31d may be electrically connected to the pixel electrode E1 (see Figure 6A) of the subsequently formed light-emitting element 20. For example, the positional relationship between the first connecting electrode 31a and the third connecting electrode 31c can be seen by referring to the position in Figure 6E, which is not shown in Figure 6F for clarity and brevity.

[0083] In some embodiments of this disclosure, the transistors used may be thin-film transistors, field-effect transistors, or other switching devices having the same characteristics. The source and drain of the transistors used herein may be structurally symmetrical, and therefore the source and drain may not be structurally distinguishable. In one embodiment of this disclosure, in order to distinguish the two poles other than the gate of a transistor, one pole is directly described as the first pole and the other pole as the second pole, and therefore, in embodiments of this disclosure, the first and second poles of all or some transistors are interchangeable as needed. For example, in an embodiment of this disclosure, the first pole of a transistor may be the source and the second pole may be the drain, or the first pole of a transistor may be the drain and the second pole may be the source.

[0084] Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. In the embodiments of this disclosure, the example will be that all transistors are P-type transistors. Based on the description and teaching of the embodiments of this disclosure, a person skilled in the art will readily conceive, without requiring any creative work, that at least some of the transistors in the pixel circuits of the embodiments of this disclosure are N-type transistors, that is, that the embodiments use N-type transistors or a combination of N-type and P-type transistors, and therefore these embodiments also fall within the scope of protection of this disclosure.

[0085] Figures 6A to 6F illustrate a 7T1C pixel circuit as an example, and embodiments of this disclosure include, but are not limited to, this. Furthermore, embodiments of this disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may have a structure including yet another number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and embodiments of this disclosure are not limited to these.

[0086] Figure 23 is a schematic cross-sectional view of a pixel circuit of a display panel according to some embodiments of the present disclosure. For example, as shown in Figure 23, the display panel includes a thin-film transistor 50 and a storage capacitor C1. The thin-film transistor 50 includes an active layer ATL1 located on a base substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL1 away from the base substrate BS, and a gate GE located on the side of the first gate insulating layer GI1 away from the base substrate BS. The display panel further includes a second gate insulating layer GI2 located on the side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the base substrate BS, and a source or drain CNE1 located on the side of the interlayer insulating layer ILD away from the base substrate BS. For example, when the thin-film transistor 50 is implemented as an N-type transistor, CNE1 represents the source of the thin-film transistor 50 and CNE2 represents the drain of the thin-film transistor 50. When the thin-film transistor 50 is implemented as a P-type transistor, CNE1 represents the drain of the thin-film transistor 50 and CNE2 represents the source of the thin-film transistor 50. The active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 located on either side of the channel CN11, respectively. The connecting electrode CNE1 is connected to the second electrode ET2 by vias that penetrate the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 and the gate GE are located in the same layer and are both located in the first conductive pattern layer LY1, while the second electrode C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD and is located in the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is the source and the other is the drain. The connecting electrode CNE1 is located in the third conductive pattern layer LY3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the source or drain CNE1 is the first part of the fourth connecting electrode 31d shown in Figure 6E or 6F, and the thin-film transistor 50 may be the second light emission control transistor T5.

[0087] As shown in Figure 23, the display panel further includes a light-emitting element EMC, which includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2. The pixel electrode E1 is connected to a connecting electrode CNE1 by vias that penetrate the passivation layer PVX and the planarization layer PLN. The display panel further includes a package layer CPS, which includes a first package layer CPS1, a second package layer CPS2, and a third package layer CPS3. For example, the first package layer CPS1 and the third package layer CPS3 are inorganic material layers, and the second package layer CPS2 is an organic material layer. For example, the pixel electrode E1 is the anode and the common electrode E2 is the cathode, but is not limited to this.

[0088] For example, the light-emitting element EMC includes an organic light-emitting diode. The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer EML includes at least a light-emitting layer and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, or an electron injection layer.

[0089] As shown in Figure 23, the display panel further includes a pixel definition layer (PDL) and a spacer (PS). The pixel definition layer (PDL) has an aperture configured to limit the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the spacer (PS) is configured to support the fine metal mask when forming the light-emitting functional layer (EML). Figure 23 shows, but is not limited to, spacer (PS) being installed on both opposing sides of the light-emitting element.

[0090] For example, a data line is configured to input a data signal to a pixel unit, and a first power line is configured to input a first voltage signal to a drive transistor. A second power line is configured to input a second voltage signal to a sub-pixel. The first voltage signal is a constant voltage, and the second voltage signal is a constant voltage; for example, the first voltage signal is a positive voltage and the second voltage signal is a negative voltage, but is not limited to this. For example, in some embodiments, the first voltage signal is a positive voltage and the second power line is grounded.

[0091] As shown in Figure 23, in the embodiments of this disclosure, the first insulating layer ISL1 includes at least one of the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0092] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS are all made of insulating material. For example, the material of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX includes, but is not limited to, at least one of SiOx and SiNx. For example, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS may be made of organic insulating material, for example, resin, but is not limited to this.

[0093] As shown in Figure 6F, the threshold compensation transistor T3 includes a first active part CN1 and a second active part CN2 connected via a conductive part CP. As shown in Figures 8B and 10, the second wire L2 further includes a connecting arm L21. The threshold compensation transistor T3 is a double-gate transistor, and the conductive part CP is in a floating state when the threshold compensation transistor T3 is off, and is susceptible to jumps due to the influence of the surrounding line voltage. Voltage jumps in the conductive part CP affect the leakage current of the threshold compensation transistor T3 and also affect the luminescence brightness of the pixel unit. Therefore, it is necessary to stabilize the voltage of the conductive part CP, and for this reason, a capacitor is formed between the stopper and the conductive part CP, and the stopper may have a constant voltage signal to stabilize the voltage of the conductive part CP in the floating state. The stopper BK0, stopper BK1 and the connecting arm referred to in the embodiments of this disclosure all play a role in stabilizing the voltage of the conductive part CP.

[0094] Figure 7 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 8A is a magnified schematic diagram of region A11 shown in Figure 7. Figure 8B is a magnified schematic diagram of region A12 shown in Figure 7. Figure 8C is a plan view of the semiconductor pattern of the display panel shown in Figure 7. Figure 9 is a plan view of the first conductive pattern layer of the display panel shown in Figure 7. Figure 10 is a plan view of the second conductive pattern layer of the display panel shown in Figure 7. Figure 11 is a plan view of the third conductive pattern layer of the display panel shown in Figure 7.

[0095] For example, as shown in Figure 7, at least two subpixels include a first subpixel 101 and a second subpixel 102 arranged along a first direction D1. For example, as shown in Figure 8A, at least one of the multiple second conductors L2 electrically connects the first subpixel 101 and the second subpixel 102, and the second subwiring L112 and the multiple second conductors L2 are located in a different layer.

[0096] For example, as shown in Figure 6A, the subpixel P0 further includes a light-emitting element 20, and the pixel circuit includes a first transistor (e.g., a threshold compensation transistor T3) and a second transistor (e.g., a second light-emitting control transistor T5 shown in Figure 6A), the first transistor T3 is connected to the second transistor T5, and the second transistor T5 is connected to the light-emitting element 20, and for example, as shown in Figure 6F, the first transistor T3 includes a first active part CN1 and a second active part CN2 connected via a conductive part CP.

[0097] For example, as shown in Figures 8B and 10, the second conductor L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive part CP of one subpixel in the pixel group that overlaps with the second conductor L2 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3 (see Figure 24), and the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2.

[0098] For example, as shown in Figures 8B and 10, the shape of the connecting arm L21 includes a C-shape. The connecting arm L21 only needs to be roughly C-shaped, and of course, it may have other shapes as long as it can perform its role in stabilizing the threshold compensation transistor T3.

[0099] As shown in Figure 24, the connecting arm L21 partially overlaps with the conductive part CP of the threshold compensation transistor T3 to form a capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are placed between the connecting arm L21 and the conductive part CP. Figure 24 further shows the second active part CN2. Capacitor C0 may also be called a stabilizing capacitor, and the connecting arm L21 and the conductive part CP are the two plates of capacitor C0. As shown in Figure 24, the gate GE2 and the second active part CN2 overlap in a direction perpendicular to the base substrate BS. Gate GE2 is one gate of the threshold compensation transistor T3. As shown in Figure 24, a portion of the second connecting electrode 31b (see Figure 6E) is used as the second electrode T32 (e.g., drain) of the threshold compensation transistor T3.

[0100] For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2, and the third direction D3 is perpendicular to the base substrate BS. A first gate insulating layer GI1 and a second gate insulating layer GI2 are installed between the connecting arm L21 and the conductive part CP. For example, the first direction D1 and the second direction D2 are parallel to the main surface of the base substrate BS, and the third direction D3 is perpendicular to the main surface of the base substrate BS. Various elements are manufactured on the main surface of the base substrate BS.

[0101] As shown in Figures 6F, 8A, and 24, the stopper BK0 and the conductive part of one subpixel in the pixel island that overlaps with the first conductor L1 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. As shown in Figures 6F, 8A, and 24, the stopper BK0 and the conductive part CP of one subpixel in the pixel island that overlaps with the first conductor L1 (the lower right subpixel in Figure 8A) are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3.

[0102] For example, as shown in Figures 6A, 6F, 8B, and 24, the second conductor L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive portion CP of one subpixel in the pixel island that overlaps with the second conductor L2 (the upper right subpixel in Figure 7, i.e., the subpixel in Figure 8B) are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. For example, the first transistor and the second transistor are a threshold compensation transistor T3 and a light emission control transistor connected to a light-emitting element in the pixel circuit 10, respectively. For example, the light emission control transistor connected to the light-emitting element is the second light emission control transistor T5. Of course, in other embodiments of this disclosure, the stopper or connecting arm that forms a capacitor with the conductive portion CP of the first transistor in the pixel island may be in other forms, and is not limited thereto.

[0103] For example, as shown in Figure 6D, the initialization signal line 210 includes multiple hollow regions HP, and the second conductor L2 is located within one of the hollow regions HP and surrounded by the portion of the initialization signal line that surrounds the hollow region HP, and the second conductor L2 does not overlap with the portion of the initialization signal line that surrounds the hollow region HP. That is, the second conductor L2 is completely surrounded by the portion of the initialization signal line that surrounds the hollow region HP. In the embodiments of this disclosure, the hollow regions HP are locations corresponding to portions of the thin film that were removed during the manufacturing of the initialization signal line 210.

[0104] For example, as shown in Figure 8A, the first conductor L1 includes the first sub-wiring L111 and the second sub-wiring L112, and the first sub-wiring L111 of the first conductor L1 and the second conductor L2 are not located on the same layer, and the second sub-wiring L112 of the first conductor L1 and the second conductor L2 are not located on the same layer. As shown in Figures 8A, 10, and 11, the second conductor L2 is located on the second conductive pattern layer LY2, and the first conductor L1 is located on the third conductive pattern layer LY3.

[0105] For example, as shown in Figure 3, the data line 313 includes a first data line DL1 that extends from the first display area R1 to the second display area R2. For example, as shown in Figure 8A, the first portion DL11 of the first data line DL1 partially overlaps with the orthographic projection of the third conductor L3 on the base substrate BS. This configuration is advantageous for reducing wiring area and improving light transmittance.

[0106] For example, as shown in Figures 6C, 6D, 7, and 8A, the first data line DL1 includes a first portion DL11 and a second portion DL12. The first portion DL11 of the first data line DL1 partially overlaps with the third conductor L3, and the second portion DL12 of the first data line DL1 does not overlap with the third conductor L4. The first portion DL11 and the second portion DL12 of the first data line DL1 are located in different layers. For example, in Figure 8A, the first portion DL11 (conductor 214) of the left first data line DL1 is located in the second conductive pattern layer, the second portion DL12 of the left first data line DL1 is located in the third conductive pattern layer, the first portion DL11 (conductor 114) of the right first data line DL1 in Figure 8A is located in the first conductive pattern layer shown in Figure 9, and the second portion DL12 of the right first data line DL1 in Figure 8A is located in the third conductive pattern layer shown in Figure 11. For example, as shown in Figures 3, 19, and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands P1.

[0107] For example, as shown in Figure 3, two first data lines DL1 are provided, and each of the two first data lines DL1 is connected to two adjacent rows of subpixels. For example, as shown in Figure 8A, the first portion DL11 of the two first data lines partially overlaps the orthographic projection of the same third conductor L3 on the base substrate BS. With this configuration, the data lines located between the pixel islands in two adjacent rows of subpixels can be hidden beneath the third conductor, thereby reducing the wiring area and improving light transmittance.

[0108] For example, the first conductor L1 and the second conductor L2 are located in different layers and are connected by vias that penetrate the insulating layer. As shown in Figures 8A and 11, the first conductor L1 is located in the third conductive pattern layer LY3, and the second conductor is located in the second conductive pattern layer LY2. As shown in Figures 23 and 24, an interlayer dielectric layer ILD is installed between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the second sub-wiring L112 of the first conductor L2 and the second conductor L2 are connected by vias that penetrate the interlayer dielectric layer ILD.

[0109] For example, as shown in Figure 11, the first conductor and the third conductor L3 are located in the same layer, and both are located in the third conductive pattern layer LY3. The fourth conductor L4 and the third conductor L3 are located in the same layer, and both are located in the third conductive pattern layer LY3.

[0110] For example, a plurality of pixel groups includes a plurality of first pixel groups (i.e., pixel islands) and a plurality of second pixel groups (i.e., pixel islands) arranged at intervals, and adjacent first and second pixel groups are connected by a plurality of wires (for example, wires L11 between gate lines connecting adjacent pixel islands, wires L13 (i.e., 210) between initialization signal lines connecting adjacent pixel islands, wires L14 between light emission control signal lines connecting adjacent pixel islands, and a first conductor L1, etc.).

[0111] For example, as shown in Figures 8A and 10, the display panel 1 further includes connecting wires Ld, and the orthographic projections on the base substrate of at least two of the multiple wirings between adjacent first and second pixel groups lie within the orthographic projections on the base substrate of the connecting wires Ld. For example, in some embodiments, there are multiple gaps between the multiple wirings, and the orthographic projection on the base substrate of at least one of the multiple gaps at least partially overlaps with the orthographic projection on the base substrate of the connecting wires Ld, thereby preventing light leakage due to gaps between wirings.

[0112] For example, as shown in Figures 6A-6F, the pixel circuit 10 includes a first reset signal line 111, a second reset signal line 112, a gate line 113, a light emission control line 110, and an initialization signal line 210, respectively, to provide the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal. The plurality of wirings are selected from at least two of the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control line 110, the initialization signal line 210, and the first conductor. For example, the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control line 110, the initialization signal line 21, and the second conductor of the first pixel group are connected via the plurality of wirings to the second reset signal line 112, the gate line 113, the light emission control line 110, the initialization signal line 210, and the second conductor of the second pixel group, respectively.

[0113] For example, as shown in Figures 8A and 10, at least a portion of the orthographic projection of the connecting wire Ld on the base substrate lies between the orthographic projections of the adjacent first and second pixel groups on the substrate, and the connecting wire Ld and the initialization signal line are located on the same layer and formed integrally.

[0114] Figure 18 is a schematic diagram of a display panel in which one pixel island includes three subpixels according to at least one embodiment of the present disclosure. For example, one pixel island includes a first subpixel 101, a second subpixel 102, and a third subpixel 103. Figure 19 is a plan view of the semiconductor pattern of the display panel shown in Figure 18. Figure 20 is a plan view of the first conductive pattern layer of the display panel shown in Figure 18. Figure 21 is a plan view of the second conductive pattern layer of the display panel shown in Figure 18. Figure 22 is a plan view of the third conductive pattern layer of the display panel shown in Figure 18.

[0115] For example, the connection structure between the display panel shown in Figure 18 and the display panel shown in Figure 7 is almost the same. The difference is that in Figure 18, adjacent pixel islands are located in the same row, while in Figure 7, adjacent pixel islands are offset from each other. For a related explanation of Figure 18, please refer to the related explanations in Figures 7-11, and a detailed explanation will be omitted here.

[0116] For example, as shown in Figures 18 and 21, the connecting conductor Ld is located on the same layer as the second conductor L2 and is formed integrally with it. However, the connecting conductor Ld may also be located on the same layer as the first conductor L1 and installed integrally with it, and the embodiments of this disclosure are not limited thereto.

[0117] For example, in this embodiment, as shown in Figure 21, the connecting wire Ld has a stopper BK0 that is installed on the same layer as the connecting wire Ld and is integrally formed with it. The stopper and the conductive part of one pixel unit in the BK0 pixel group that overlaps with the first wire L1 are spaced apart from each other in the third direction D1 and partially overlap in the third direction D3, thereby ensuring the stability of the threshold compensation transistor T3. A detailed explanation can be found in the above description, and a detailed explanation is omitted here.

[0118] Figure 12 is a schematic diagram of a display panel in which one pixel island includes four subpixels according to at least one embodiment of the present disclosure. For example, one pixel island includes a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104. Figure 13 is an enlarged schematic diagram of region A21 shown in Figure 12. Figure 14 is a plan view of the semiconductor pattern of the display panel shown in Figure 12. Figure 15 is a plan view of the first conductive pattern layer of the display panel shown in Figure 12. Figure 16 is a plan view of the second conductive pattern layer of the display panel shown in Figure 12. Figure 17 is a plan view of the third conductive pattern layer of the display panel shown in Figure 12.

[0119] For example, in some embodiments of the present disclosure, as shown in Figure 12, at least two subpixels further include a third subpixel 103 and a fourth subpixel 104, the third subpixel 103 and the fourth subpixel 104 being arranged along a first direction D1 and located on one side of the first subpixel 101 and the second subpixel 102 along a second direction D2, the third subpixel 103 and the fourth subpixel 104 being electrically connected to another of a plurality of second wires L2 (e.g., a second wire L21 located below the layout shown in Figure 16), and the second subwire L112 being electrically connected to at least one of a plurality of second wires, for example, a second wire L2 located on the first row of pixels (i.e., the first subpixel 101 and the second subpixel 102) and / or a second wire L21 located on the second row of pixels (i.e., the third subpixel 103 and the fourth subpixel 104).

[0120] For example, the display panel shown in Figure 12 and the display panel shown in Figure 7 are almost identical, but the difference lies in the layer on which the wiring of two adjacent pixel groups is located. Specifically, for example, as shown in Figure 15, the gate line wiring L11 connecting two adjacent pixel islands is located in the first conductive pattern layer LY2, whereas in Figure 7 it is located in the third conductive pattern layer LY3, and the initialization signal line 111 extends from the second display area R2 to the first display area R1 in the first conductive pattern layer, and as shown in Figure 16, the initialization signal line 111 may be further connected via wiring Lrest located in the second conductive pattern layer.

[0121] For example, as shown in Figures 16 and 10, the second sub-wiring L112 has a stopper BK0, which is located on a different layer from the second sub-wiring L112 and connected by a via. For example, as shown in Figure 24, the stopper BK0 is located on the second conductive pattern layer, and the second sub-wiring L112 is located on the third conductive pattern layer LY3 shown in Figures 17 and 11. Therefore, in this embodiment, the stopper BK0 is connected to the second sub-wiring L112 by a via that penetrates the insulating layer, thereby ensuring the stability of the threshold compensation transistor T3.

[0122] However, the remaining structure of the display panel (e.g., stopper BK0), the first conductor L1, etc. can be found in the explanations in Figures 7-11, and a detailed explanation is omitted here.

[0123] At least one embodiment of the present disclosure further provides a display device, which includes any of the above-described display panels. For example, the display device may be a display device such as an organic light-emitting diode (OLED) display, or any product or component with a display function that includes such display devices, such as a television, digital camera, mobile phone, wristwatch, tablet PC, laptop, or navigator.

[0124] Figure 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 25, the display device 2 includes a display panel 1 and a sensor 3. For example, the sensor 3 is installed on one side of the display panel 1.

[0125] For example, as shown in Figures 1A-1C, the sensor 3 is installed on the second side of the display panel 1 and is configured to receive light from the first side of the display panel. For example, the first side of the display panel 1 is used for display, and the first display area R1 allows light from the first side of the display panel to be transmitted at least partially to the second side of the display panel.

[0126] For example, the orthographic projection of sensor 3 on the base substrate overlaps at least partially with the first display area R1.

[0127] For clarity and brevity, not all component units of the display device are described in the embodiments of this disclosure. Those skilled in the art can provide and install other structures not shown as needed to realize the basic functions of the display device, and the embodiments of this disclosure are not limited thereto.

[0128] The technical effects of the display device 2 according to the above embodiment can be understood by referring to the technical effects of the display panel 1 according to the embodiment of this disclosure, and a detailed explanation is omitted here.

[0129] In addition, (1) Unless otherwise defined, the same reference numerals in the embodiments and drawings of this disclosure have the same meaning. (2) In the drawings of the embodiments of the present disclosure, only the structures relating to the embodiments of the present disclosure are shown, and other structures should refer to general designs. (3) For clarity, in drawings illustrating embodiments of the present disclosure, the thickness of a layer or region is magnified. To make it clear, when an element such as a layer, film, region or substrate is described as being located "above" or "below" another element, the element may be located "directly" above or below the other element, or an intermediate element may be present. (4) Where there is no conflict, the features of the same and different embodiments of the present disclosure can be combined with each other.

[0130] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can easily conceive of within the technical scope disclosed herein should all fall within the scope of protection of the present disclosure. Accordingly, the scope of protection of the present disclosure should be the same as the scope of protection of the claims.

Claims

1. It is a display panel, The first display area and, A second display area located at least on one side of the first display area, A plurality of subpixels located in the first display area and the second display area, wherein the density of subpixels in the first display area is less than the density of subpixels in the second display area, and the subpixels include a plurality of subpixels including a pixel circuit. A plurality of pixel groups located in the aforementioned first display area, wherein at least one of the plurality of pixel groups comprises a plurality of pixel groups including at least two subpixels, A first power line is configured to provide a first voltage signal to the pixel circuit and extends from the first display area to the second display area, It includes a plurality of data lines connected to the plurality of pixel groups and configured to provide data signals to the plurality of pixel groups, A display panel in which, between adjacent pixel groups, the orthographic projection on the base substrate of a portion of at least one of the plurality of data lines is located within the orthographic projection on the base substrate of the first power line.

2. The display panel according to claim 1, wherein, between adjacent pixel groups, the orthographic projection on the base substrate of a portion of each of two adjacent data lines is located within the orthographic projection on the base substrate of the same first power line.

3. The display panel according to claim 1, wherein a portion of the line segment of at least one data line extends along a direction in which adjacent pixel groups face each other.

4. The first power line includes a plurality of first conductors and a plurality of second conductors, the plurality of first conductors extending from the second display area to the first display area and electrically connected to the plurality of pixel groups, the plurality of second conductors located in the first display area and between adjacent first conductors, the plurality of second conductors extending along a first direction, adjacent second conductors spaced apart from each other along the first direction, and the plurality of second conductors electrically connected to the plurality of pixel groups. The display panel according to claim 1, wherein at least one of the plurality of first conductors includes a first sub-wiring extending in a first direction and a second sub-wiring extending in a second direction, the first direction and the second direction intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conductors.

5. The display panel according to claim 4, wherein the at least two subpixels include a first subpixel and a second subpixel arranged along the first direction, at least one of the plurality of second conductors electrically connects the first subpixel and the second subpixel, and the second subwire and the plurality of second conductors are located in different layers.

6. The display panel according to claim 5, wherein the subpixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is connected to the second transistor and the storage capacitor respectively, the second transistor is connected to the light-emitting element, and the first transistor is connected via a conductive portion to a first active portion and a second active portion.

7. The display panel according to claim 6, wherein the second conductor further includes a connecting arm that is spaced apart from each other in a third direction and partially overlaps with the conductive portion of one subpixel in the pixel group that overlaps with the second conductor, the third direction being perpendicular to the first direction and perpendicular to the second direction.

8. The display panel according to claim 7, wherein the shape of the connecting arm includes a C-shape.

9. The display panel according to claim 4, wherein the plurality of pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected by a plurality of wires.

10. The display panel according to claim 9, further comprising connecting conductors, wherein the orthographic projection on the base substrate of at least two of the plurality of wirings between adjacent first pixel groups and second pixel groups lies within the orthographic projection on the base substrate of the connecting conductors.

11. The display panel according to claim 9, wherein there are multiple gaps between the multiple wirings, and the orthographic projection of at least one of the multiple gaps on the base substrate at least partially overlaps with the orthographic projection of the connecting conductor on the base substrate.

12. Each pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control line, and an initialization signal line, respectively, to provide the pixel circuit with a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal. The display panel according to any one of claims 9-11, wherein the plurality of wirings are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the first conductor.

13. The connecting conductor has a stopper that is installed in the same layer as the connecting conductor and is integrally formed with it. The sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is connected to the second transistor and the storage capacitor respectively, the second transistor is connected to the light-emitting element, and the first transistor includes a first active part and a second active part connected via a conductive part, The display panel according to claim 10, wherein the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

14. The display panel according to claim 12, wherein the orthographic projection of the connecting conductor on the base substrate is at least partially located between the orthographic projections of the adjacent first and second pixel groups on the base substrate.

15. The display panel according to claim 14, wherein the first reset signal line, second reset signal line, gate line, light emission control line, initialization signal line and second conductor of the first pixel group are connected to the first reset signal line, second reset signal line, gate line, light emission control line, initialization signal line and second conductor of the second pixel group, respectively, via the plurality of wirings.

16. The display panel according to claim 15, wherein the connecting conductor and the second conductor are located on the same layer and integrally formed, or the connecting conductor and the initialization signal line are located on the same layer and integrally formed, or the connecting conductor and the first conductor are located on the same layer.

17. The display panel according to claim 6, wherein the at least two subpixels further include a third subpixel and a fourth subpixel, the third subpixel and the fourth subpixel being arranged along the first direction and located on one side of the first subpixel and the second subpixel along the second direction, and being electrically connected to another of the plurality of second conductors, and the second subwire being electrically connected to at least one of the plurality of second conductors.

18. The second sub-wiring is located on a different layer from the second sub-wiring and has a stopper connected by a via, The display panel according to claim 6 or 17, wherein the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductor are spaced apart from each other in the third direction and partially overlap in the third direction.

19. The display panel according to claim 4, wherein the first direction is perpendicular to the second direction.

20. The display panel according to claim 4, wherein the plurality of second conductors are arranged sequentially along the first direction.

21. The display panel according to claim 4, wherein the adjacent second conductor is not directly connected.

22. The display panel according to claim 4, wherein the first conductor and the second conductor are connected by vias that penetrate the insulating layer.

23. The first power line further includes a third conductor and a fourth conductor, The third conductor extends along the second direction, from the second display area to the first display area, and the second conductor is electrically connected to the third conductor. The display panel according to claim 4, wherein the fourth conductor extends along the second direction, the second conductor is electrically connected to the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

24. The display panel according to claim 4, comprising a plurality of fourth conductors located between adjacent third conductors and arranged sequentially along the second direction, wherein adjacent fourth conductors are spaced apart from each other in the second direction.

25. The display panel according to claim 23, wherein the first conductor and the third conductor are located on the same layer, and the fourth conductor and the third conductor are located on the same layer.

26. The display panel according to claim 1, wherein the first display area includes a plurality of light-transmitting areas located between adjacent pixel groups.

27. The display panel according to claim 25, wherein the wiring connected to the plurality of pixel groups and adjacent pixel groups surrounds the plurality of light-transmitting regions.

28. A display device comprising a display panel according to any one of claims 1 to 27.

29. It further includes sensors, The display device according to claim 28, wherein the sensor is installed on one side of the display panel, and the orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.

Images