Semiconductor equipment

Abstract

We provide semiconductor devices with large memory capacity. [Solution] A semiconductor device having a plurality of insulators, a first conductor 132A and a first semiconductor 151, wherein the first conductor is located on the first upper surface of the first insulator 101A and on the first lower surface of the second insulator 101B. The third insulator 102 is located in a region including the side surface of the first insulator, the second upper surface of the first insulator, the side surface of the first conductor, the second lower surface of the second insulator, and the side surface of the second insulator. On the formation surface of the third insulator, a fourth insulator 111, a fifth insulator 104, and a first semiconductor are stacked in order, and the sixth insulator 109a is located in a region of the formation surface of the fifth insulator that overlaps with the first conductor. The seventh insulator 105 is located in a region including the formation surface of the first semiconductor and the formation surface of the sixth insulator. The fourth insulator has the function of accumulating charge, and by applying a potential to the first conductor, a tunnel current is induced between the first semiconductor and the fourth insulator via the fifth insulator.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a semiconductor wafer, a memory device, and an electronic device.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Storage devices, processors, electronic devices, methods for driving them, methods for manufacturing them, and inspections thereof. A method, or a system having at least one of them, can be given as an example. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have been used. The equipment includes a central processing unit (CPU) and a graphics processing unit. Electronic components such as GPUs, memory devices, and sensors are used, and these electronic components are micro Improvements are being made in various aspects, such as miniaturization and lower power consumption.

[0004] In particular, the amount of data handled by the aforementioned electronic devices is increasing, and storage capacity There is a demand for storage devices with large storage capacity. As a means of increasing storage capacity, for example, patent documents Reference 1 describes a three-dimensional NAND memory element using a metal oxide as the channel formation region. This has been disclosed. [Prior art documents]

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] When manufacturing a three-dimensional NAND memory element, the semiconductor layer applied to the memory element is divided into a channel formation region and a low-resistance region. In particular, when using a metal oxide as the semiconductor layer, how to form the low-resistance region of the metal oxide becomes important. The transistor using a metal oxide as the semiconductor layer has a region with a low carrier concentration (or, in this specification, may be described by other expressions such as intrinsic, substantially intrinsic, etc.) functioning as the channel formation region, and a region with a high carrier concentration functioning as the low-resistance region. Therefore, in the manufacturing of a three-dimensional NAND memory element using a metal oxide as the semiconductor layer, the separation between the channel formation region and the low-resistance region becomes an issue.

[0007] One aspect of the present invention is to provide a novel semiconductor device having a semiconductor layer in which a channel formation region and a low-resistance region are separated. Or, one aspect of the present invention is to provide a storage device having the semiconductor device. Or, one aspect of the present invention is to provide an electronic device using the storage device having the semiconductor device. Or, one aspect of the present invention is to provide a storage device with a large data capacity. Or, one aspect of the present invention is to provide a highly reliable storage device.

[0008] ​​​​​​​​​​​​ The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Issues not mentioned in this section can be found in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the problems. One aspect of the present invention addresses the problems listed above, as well as other problems. You don't need to solve all of them. [Means for solving the problem]

[0009] (1) One aspect of the present invention relates to a semiconductor having first to seventh insulators, a first conductor, and a first semiconductor. This is a conductive device in which the first conductor is located on the first upper surface of the first insulator, and the first conductor is located on the second insulator. Located on the first lower surface of the edge, the third insulator is located on the side surface of the first insulator and on the second upper surface of the first insulator. A region including the side surface of the first conductor, the second lower surface of the second insulator, and the side surface of the second insulator. The fourth insulator is positioned on the forming surface of the third insulator, and the fifth insulator is positioned on the forming surface of the fourth insulator. The first semiconductor is located on the formation surface of the fifth insulator, and the sixth insulator is in the shape of the first semiconductor. Of the formed surface, the region that overlaps with the first conductor via the third to fifth insulators, and the seventh insulator The edge body has a first semiconductor formation surface superimposed on the first insulator, and a first semiconductor superimposed on the second insulator. A semiconductor characterized by being located in a region that includes a conductor formation surface and a sixth insulator formation surface. It is a device.

[0010] (2) Alternatively, one aspect of the present invention comprises a first to seventh insulator, a first conductor, and a first semiconductor. The semiconductor device is such that the first conductor is located on the first upper surface of the first insulator, and the first conductor is The third insulator is located on the first lower surface of the second insulator, and the third insulator is located on the second upper surface of the first insulator and the first conductor Located in a region including the side surface and the second lower surface of the second insulator, the fourth insulator has the shape of the third insulator. Of the formed surface, there is a region that overlaps with the first conductor, a region that overlaps with the second upper surface of the first insulator, and The fifth insulator is located in a region that includes the region overlapping with the second lower surface of the second insulator, and the fourth insulator is located in a region that includes the region of the second insulator. The forming surface, the region overlapping with the side surface of the first insulator, and the region overlapping with the side surface of the second insulator, The region including the first semiconductor is located on the formation surface of the fifth insulator, and the sixth insulator is located on the first Located in the semiconductor formation surface, in the region where it overlaps with the first conductor via the third to fifth insulators. The seventh insulator has a first semiconductor formation surface superimposed on the first insulator, and a second insulator superimposed on the second insulator. It is characterized by being located in a region that includes the formation surface of the first semiconductor and the formation surface of the sixth insulator. It is a semiconductor device.

[0011] (3) Alternatively, one aspect of the present invention comprises a first to seventh insulator, a first conductor, a first semiconductor, and a second A semiconductor device having a semiconductor, wherein the first conductor is located on the first upper surface of the first insulator, The first conductor is located on the first lower surface of the second insulator, and the second semiconductor is located on the side surface of the first conductor. The third insulator is formed from the second upper surface of the first insulator, the side surface of the second semiconductor, and the second lower surface of the second insulator. The fourth insulator is located in a region including the surface, and the fourth insulator is located in a region including the surface forming the third insulator, overlapping with the first conductor. The area to be folded, the area to be superimposed on the second upper surface of the first insulator, and the area to be superimposed on the second lower surface of the second insulator The fifth insulator is located in a region including the region and the forming surface of the fourth insulator and the first insulator Located in a region that includes the region overlapping with the upper surface and the region overlapping with the second lower surface of the second insulator. The first semiconductor has a formation surface for the fifth insulator, a region that overlaps with the side surface of the first insulator, and the second insulator The sixth insulator is located in a region that includes the side of the body and the region that overlaps with it, and the first semiconductor is formed on the surface of the first semiconductor. Of these, the region located in which the first conductor is superimposed via the second semiconductor and the third to fifth insulators, The seventh insulator has a first semiconductor formation surface superimposed on the first insulator, and a second insulator superimposed on it. It is characterized by being located in a region that includes the formation surface of the first semiconductor and the formation surface of the sixth insulator. It is a semiconductor device.

[0012] (4) Alternatively, in one aspect of the present invention, in (1) to (3) above, the fourth insulator stores charge It has the function of applying an electric potential to the first conductor, thereby releasing the charge contained in the first semiconductor. A semiconductor device characterized by the accumulation of a fourth insulator.

[0013] (5) Alternatively, one aspect of the present invention comprises a first to third insulator, a fifth to seventh insulator, and a first conductor A semiconductor device having a second conductor and a first semiconductor, wherein the first conductor is a first insulating Located on the first upper surface of the body, the first conductor is located on the first lower surface of the second insulator, and the third insulator is In the region including the second upper surface of the first insulator, the side surface of the first conductor, and the second lower surface of the second insulator The second conductor is located in the region of the third insulator's formation surface that overlaps with the first conductor. The fifth insulator has a region of the third insulator's formation surface that overlaps with the second upper surface of the first insulator, and Located in a region that includes the region overlapping with the second lower surface of the second insulator and the formation surface of the second conductor. The first semiconductor has a formation surface for the fifth insulator, a region that overlaps with the side surface of the first insulator, and the second insulator The sixth insulator is located in a region that includes the side of the body and the region that overlaps with it, and the first semiconductor is formed on the surface of the first semiconductor. Of these, the region that overlaps with the first conductor via the third insulator, the second conductor, and the fifth insulator is located. The seventh insulator has a first semiconductor formation surface superimposed on the first insulator, and a second insulator superimposed on the second insulator. It is characterized by being located in a region that includes the formation surface of the first semiconductor and the formation surface of the sixth insulator. It is a semiconductor device.

[0014] (6) Alternatively, in one aspect of the present invention, in (5) above, the second conductor has a function of accumulating charge. By applying an electric potential to the first conductor, the charge contained in the first semiconductor becomes the second conductor. This semiconductor device is characterized by its ability to accumulate in the body.

[0015] (7) Alternatively, in one aspect of the present invention, in any one of (1) to (6) above, the third conductor The semiconductor device is characterized in that the third conductor is located on the formation surface of the seventh insulator. .

[0016] (8) Alternatively, in one aspect of the present invention, in any one of (1) to (7) above, the first semiconductor is The first semiconductor has a low-resistance region at and near the interface with the seventh insulator, and the first semiconductor is a first conductive A semiconductor device characterized by having a channel-forming region in a region that overlaps with an electric body. be.

[0017] (9) Alternatively, in one aspect of the present invention, in (8) above, the first semiconductor has a metal oxide and low The resistive region contains a conductive compound, and the compound is a component contained in the metal oxide, and A semiconductor device characterized by having a component contained in an insulator.

[0018] (10) Alternatively, in one aspect of the present invention, in (8) above, the first semiconductor has a metal oxide and low The resistive region contains a conductive compound, and the compound is composed of components found in metal oxides and gold A semiconductor device characterized by having a group element.

[0019] (11) Alternatively, one aspect of the present invention comprises a first to seventh insulator, a first conductor, a second conductor, and a first A semiconductor device having a semiconductor and a second semiconductor, wherein the first conductor is the first insulator Located on the upper surface, the first conductor is located on the first lower surface of the second insulator, and the second conductor is the second insulator Located on the upper surface of the body, the second conductor is located on the lower surface of the third insulator, and the fourth insulator is the first insulator The side of the body, the second upper surface of the first insulator, the side of the first conductor, the second lower surface of the second insulator, Located in a region including the side surface of the second insulator, the side surface of the second conductor, and the side surface of the third insulator, The first semiconductor is located on the formation surface of the fourth insulator, and the fifth insulator is located on the formation surface of the first semiconductor. , located in the region superimposed on the first conductor via the fourth insulator, the sixth insulator is located in the region superimposed on the first insulator A first semiconductor formation surface superimposed with the second insulator, and a first semiconductor formation surface superimposed with the second insulator, Formation surface of the first semiconductor superimposed with two conductors, and formation of the first semiconductor superimposed with a third insulator. The second semiconductor is located in a region including the surface and the surface on which the fifth insulator is formed, and the second semiconductor is located on the surface on which the sixth insulator is formed A semiconductor device characterized in that the seventh insulator is located on the formation surface of the second semiconductor, and the seventh insulator is located on the formation surface of the second semiconductor. be.

[0020] (12) Alternatively, one aspect of the present invention comprises a first to seventh insulator, a first conductor, a second conductor, and a first A semiconductor device having a first semiconductor and a third semiconductor, wherein the first conductor is on the first upper surface of the first insulator The first conductor is located on the first lower surface of the second insulator, and the second conductor is located on the upper surface of the second insulator. Located on the surface, the second conductor is located on the underside of the third insulator, and the third semiconductor is located on the side of the first conductor. Located on the surface, the fourth insulator is located on the side surface of the first insulator, the second top surface of the first insulator, and the third semiconductor The forming surface, the second lower surface of the second insulator, the side surface of the second insulator, the side surface of the second conductor, and the third The first semiconductor is located in a region including the side surface of the insulator, and the fourth semiconductor is located on the formation surface of the insulator. 5. The insulator has a first conductive surface on which the first semiconductor is formed, via the fourth insulator and the third semiconductor. Located in the region superimposed with the electric body, the sixth insulator superimposed with the first insulator forms the first semiconductor. A surface, a first semiconductor formation surface superimposed on a second insulator, and a first semiconductor superimposed on a second conductor. The formation surface of the body, the formation surface of the first semiconductor superimposed on the third insulator, and the formation surface of the fifth insulator, The region containing the second semiconductor is located on the formation surface of the sixth insulator, and the seventh insulator is located on the second This semiconductor device is characterized by being located on the semiconductor formation surface.

[0021] (13) Alternatively, in one aspect of the present invention, the third conductor is provided in (11) or (12) above. Furthermore, the semiconductor device is characterized in that the third conductor is located on the formation surface of the seventh insulator.

[0022] (14) Alternatively, in one aspect of the present invention, in any one of (11) to (13) above, the first The semiconductor has a low-resistance region at and near the interface with the sixth insulator, and the first semiconductor is A semiconductor characterized by having a channel-forming region in the region superimposed on the first conductor. It is a body device.

[0023] (15) Alternatively, in one aspect of the present invention, in (14) above, the first semiconductor has a metal oxide, The low-resistance region contains a conductive compound, and this compound is a component found in metal oxides. A semiconductor device characterized by having a component contained in the sixth insulator.

[0024] (16) Alternatively, in one aspect of the present invention, in (14) above, the first semiconductor has a metal oxide, The low-resistance region contains a compound, which is composed of components found in metal oxides and metal elements. This is a semiconductor device characterized by having [a certain feature].

[0025] (17) Alternatively, one aspect of the present invention relates to a semiconductor device described in any one of (1) to (16) above. This is a semiconductor wafer that has multiple regions and areas for dicing.

[0026] (18) Alternatively, one aspect of the present invention relates to a semiconductor device described in any one of (1) to (16) above, and It is a memory device having peripheral circuits.

[0027] (19) Alternatively, one aspect of the present invention is an electronic device having the storage device described in (18) above and a housing. It is a vessel. [Effects of the Invention]

[0028] According to one aspect of the present invention, a semiconductor layer is formed in which a channel-forming region and a low-resistance region are separated. A novel semiconductor device having the above characteristics can be provided. Or, according to one aspect of the present invention, A storage device having the semiconductor device can be provided. Or, according to one aspect of the present invention... Therefore, an electronic device using a memory device having the said semiconductor device can be provided. According to one aspect of the present invention, a storage device with a large data capacity can be provided. According to one aspect of the present invention, a highly reliable storage device can be provided.

[0029] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of, in some cases, the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0030] [Figure 1] A circuit diagram showing an example configuration of a semiconductor device. [Figure 2] A circuit diagram showing an example configuration of a semiconductor device. [Figure 3] A circuit diagram showing an example configuration of a semiconductor device. [Figure 4] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 5] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 6] Perspective view, top view, and cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 7] Perspective view, top view, and cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 8]A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 9] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 10] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 11] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 12] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 13] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 14] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 15] A top view illustrating an example of semiconductor device fabrication. [Figure 16] A top view illustrating an example of semiconductor device fabrication. [Figure 17] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 18] A top view illustrating an example of semiconductor device fabrication. [Figure 19] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 20] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 21] A top view illustrating an example of semiconductor device fabrication. [Figure 22] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 23] A top view illustrating an example of semiconductor device fabrication. [Figure 24] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 25] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 26] A top view illustrating an example of semiconductor device fabrication. [Figure 27] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 28] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 29]A top view illustrating an example of semiconductor device fabrication. [Figure 30] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 31] A top view illustrating an example of semiconductor device fabrication. [Figure 32] A circuit diagram showing an example configuration of a semiconductor device. [Figure 33] A circuit diagram showing an example configuration of a semiconductor device. [Figure 34] A circuit diagram showing an example configuration of a semiconductor device. [Figure 35] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 36] Perspective view, top view, and cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 37] Perspective view, top view, and cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 38] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 39] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 40] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 41] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 42] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 43] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 44] A top view illustrating an example of semiconductor device fabrication. [Figure 45] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 46] A top view illustrating an example of semiconductor device fabrication. [Figure 47] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 48] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 49] A top view illustrating an example of semiconductor device fabrication. [Figure 50]A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 51] A top view illustrating an example of semiconductor device fabrication. [Figure 52] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 53] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 54] A top view illustrating an example of semiconductor device fabrication. [Figure 55] A cross-sectional diagram illustrating a semiconductor device. [Figure 56] A cross-sectional diagram illustrating a semiconductor device. [Figure 57] A cross-sectional diagram illustrating a semiconductor device. [Figure 58] A cross-sectional diagram illustrating a semiconductor device. [Figure 59] A block diagram showing an example of a storage device. [Figure 60] A flowchart illustrating an example of electronic component manufacturing, a perspective view of an electronic component, and a perspective view of a semiconductor wafer. [Figure 61] A diagram illustrating the range of atomic ratios for metal oxides. [Figure 62] A block diagram explaining the CPU. [Figure 63] A perspective view showing an example of an electronic device. [Figure 64] A perspective view showing an example of an electronic device. [Modes for carrying out the invention]

[0031] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called Oxide Semiconductor or simply OS) They are classified into categories such as the following. For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes referred to as oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor (metal oxide semiconductor). It can be abbreviated as OS (iconductor). It can also be written as OS FET. In such cases, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. It is possible.

[0032] Furthermore, in this specification, a transistor having silicon in the channel formation region is referred to as Si It is sometimes written as "transistor".

[0033] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0034] (Embodiment 1) In this embodiment, the circuit configuration, operating method, and of a semiconductor device according to one aspect of the disclosed invention are described. The manufacturing method will be explained. Note that in the following description, for example, "[x,y]" is It refers to the element in the xth row and yth column, and "[z]" refers to the element in the zth row or zth column. These notations are omitted when there is no need to specify rows or columns.

[0035] <Circuit Configuration Example 1> First, let's look at the circuit configuration of a NAND memory element, which is an example of a semiconductor device, as shown in Figure 1(A Refer to the following for explanation. Figure 1(A) shows the circuit diagram of a NAND memory element on page 1. The NAND memory elements on page 1 are memory cells MC[1] to memory cells MC n memory cells of [n] (where n is an integer greater than or equal to 1), and a distribution for controlling them. Line WL[1] to wiring WL[n], wiring BL and wiring SL, and the page to select The transistors STr and BTr, and for controlling the transistor STr It has wiring SSL and wiring BSL for controlling transistor BTr. The wiring WL is the control gate of the cell transistor of the memory cell MC described later (in this specification, etc., It is sometimes simply referred to as a gate.) It functions as a wire that applies potential to the wiring SL and The wiring BL supplies potential to the first and / or second terminals of the cell transistor of the memory cell MC. It functions as wiring.

[0036] Each memory cell MC has a cell transistor CTr. Generally, the cell A transistor is a transistor that operates with normally-on characteristics, and has a control gate and a charge It has a storage layer. The charge storage layer is superimposed on the channel formation region via a tunnel insulating film. The control gate is located in a region that overlaps with the charge storage layer via a blocking film. It is located there. The cell transistor applies a write potential to the control gate, and the cell transistor By applying a predetermined potential to either the first or second terminal of the zista, tunnel current is generated. This occurs, and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. Therefore, in a cell transistor in which electrons are injected into the charge storage layer, the threshold voltage is The cost will increase. Furthermore, an insulator or conductor (floating gate) can be used as the charge storage layer. This is possible. The detailed operating principle of the semiconductor device shown in Figure 1(A) will be described later.

[0037] The first terminal of cell transistor CTr is connected to cell transistor C of the adjacent memory cell MC. It is electrically connected in series with the second terminal of Tr. In other words, the circuit configuration is as shown in Figure 1(A). This configuration consists of n cell transistors (CTr) electrically connected in series. The second terminal of the cell transistor CTr of the memory cell MC[1] is connected to the transistor STr It is electrically connected to the first terminal of the cell transistor CTr of the memory cell MC[n]. The terminal is electrically connected to the first terminal of transistor BTr. And the memory cell Control gate of each cell transistor CTr of MC[1] to memory cell MC[n] It is electrically connected to each of the wirings WL[1] through WL[n]. Transistor The second terminal of STr is electrically connected to the wiring SL, and the gate of transistor STr is connected to the wiring It is electrically connected to wire SSL. The second terminal of transistor BTr is electrically connected to wiring BL. They are connected, and the gate of transistor BTr is electrically connected to wiring BSL.

[0038] The channel formation region of the cell transistor CTr is made of silicon, or as described in Embodiment 4. It is preferable to have a metal oxide in the channel-forming region. M, an element (for example, aluminum, gallium, yttrium, tin, etc.) ), if the metal oxide contains one or more elements selected from zinc, the metal acid Since the metal oxide functions as a wide-bandgap semiconductor, the metal oxide forms a channel-forming region. The cell transistors included have a very low off-current characteristic. In other words, off This makes it possible to reduce the leakage current in the cell transistor CTr that is in this state. Therefore, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced. Also, the transistor The channel formation regions of transistors STr and BTr also contain the aforementioned metal oxides. It is possible.

[0039] Furthermore, the channel formation region of transistor STr and / or transistor BTr is a cell The channel formation region of the transistor CTr can be configured differently. For example, the cell The aforementioned material containing the metal oxide is applied to the channel formation region of the transistor CTr. The channel formation region of transistor STr and / or transistor BTr contains silicon. The materials can be applied.

[0040] Furthermore, one aspect of the present invention is not limited to the semiconductor device shown in Figure 1(A). In short, the circuit configuration can be achieved by appropriately modifying the semiconductor device shown in Figure 1(A). For example, One aspect of the present invention, as shown in Figure 1(B), involves a back gate in the cell transistor CTr. A semiconductor device provided may also be used. Note that the semiconductor device shown in Figure 1(B) is a semiconductor device provided in Figure 1 In addition to the semiconductor device configuration shown in (A), memory cell MC[1] to memory cell M A back gate is provided in the cell transistor CTr of C[n], and the back gate Each is electrically connected to the wiring BGL. The semiconductor shown in Figure 1(B) The device has wiring BGL which has cell traces of memory cell MC[1] to memory cell MC[n] It is not configured to be electrically connected to each of the back gates of the CTr, Each gate is electrically connected independently, providing each with a different potential. A power supply configuration is also possible. An example of the operation of the semiconductor device shown in Figure 1(B) will be described later. do.

[0041] By the way, if you want to further increase the memory capacity of the semiconductor device shown in Figures 1(A) and 1(B), The memory cells MC shown in 1(A) and (B) should be arranged in a matrix. For example, if the memory cells MC shown in Figure 1(A) are arranged in a matrix, In that case, the circuit configuration will be as shown in Figure 2. Note that in this specification, etc., the configuration shown in Figure 2 Multiple NAND memory elements are referred to as a single block of NAND memory elements.

[0042] The semiconductor device shown in Figure 2 is the same as the semiconductor device shown in Figure 1(A) (NAND memory on page 1). The elements are arranged in m rows (where m is an integer greater than or equal to 1), and the wiring is WL. It is configured to be electrically connected to share memory cells (MCs) in the same row. The semiconductor device shown in Figure 2 is a matrix-shaped semiconductor device with n rows and m columns, and memory cells M It has C[1,1] to memory cells MC[n,m]. Therefore, the semiconductor device shown in Figure 2. This includes wiring WL[1] to wiring WL[n], wiring BL[1] to wiring BL[m], and wiring BSL[1] or wiring BSL[m], wiring SL[1] or wiring SL[m], and wiring SS L[1] or wiring SSL[m] is electrically connected by. Specifically, Morisel MC[j,i](where j is an integer between 1 and n, and i is an integer between 1 and m) The control gate of the cell transistor CTr is electrically connected to the wiring WL[j]. Wiring SL[i] is electrically connected to the second terminal of transistor STr[i], and wiring BL[i] is electrically connected to the second terminal of transistor BTr[i].

[0043] Figure 2 shows memory cell MC[1,1], memory cell MC[1,i], and memory cell M C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC [j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[ n,m], wiring WL[1], wiring WL[j], wiring WL[n], wiring BL[1], wiring B L[i], wiring BL[m], wiring BSL[1], wiring BSL[i], wiring BSL[m], Wiring SL[1], Wiring SL[i], Wiring SL[m], Wiring SSL[1], Wiring SSL[i ], wiring SSL[m], cell transistor CTr, transistor BTr[1], transistor Transistor BTr[i], Transistor BTr[m], Transistor STr[1], Transistor Only the transistor STr[i] and STr[m] are shown in the diagram; other wiring and components are not shown. Symbols and codes have been omitted.

[0044] Furthermore, the semiconductor devices shown in Figure 1(B) are arranged in m columns (where m is an integer greater than or equal to 1). The arrangement is shown in Figure 3. Note that the semiconductor device shown in Figure 3 contains all the memory cells. The MC has a configuration in which each transistor is equipped with a back gate, Therefore, the semiconductor device shown in Figure 3 has wiring B for electrically connecting each back gate. It has GL[1] to wiring BGL[m]. Note that the semiconductor device shown in Figure 3 is shown in Figure Refer to the description of the semiconductor device shown in section 2.

[0045] The semiconductor devices shown in Figures 2 and 3 are based on the semiconductor devices in Figures 1(A) and (B), respectively. The present invention is configured with the elements arranged in a kus-shape, but one aspect of the present invention is not limited to this. One aspect of the present invention involves modifying the semiconductor device shown in Figures 2 and 3 to obtain an appropriate circuit configuration. Yes, it is possible. For example, in Figures 2 and 3, transistor BTr[1] to transistor BTr[ The wiring for controlling [m] is shown in the diagram, with wiring BSL[1] to wiring BSL[m] respectively. As shown, transistors BTr[1] to BTr[m] are used as a single wire. The gate may also be electrically connected. Similarly, the transistor STr[1] to The wiring for controlling the transistor STr[m] is also wire SSL[1] to wire SSL[m]. Instead of ], transistor STr[1] to transistor STr[m] are treated as a single wire. The gate may also be electrically connected to the system.

[0046] <Example of operation method 1> Next, regarding an example of the operation method of the semiconductor device shown in Figures 1(A) and (B), see Figure 4(A). (B), Figure 5(A)(B) will be used to explain. Note that the low level used in the following explanation The terms "potential" and "high-level potential" do not refer to a specific potential; rather, they vary depending on the wiring. The potentials can also differ. For example, the low-level potential and high-level potential applied to the wiring BSL. Each of these is a different potential from the low-level potential and high-level potential applied to the wiring BL. That's good too.

[0047] Potential V PGM This is applied to the control gate of the cell transistor CTr, thereby controlling the cell transistor The potential V is the potential at which electrons can be injected into the charge storage layer of the CTr. PS is, cell Applying this to the control gate of transistor CTr turns on the cell transistor CTr. This is the potential at which it is possible. It is assumed that the appropriate potential is applied to the wiring SL.

[0048] Furthermore, in this example of operation method, unless otherwise specified, the wiring BGL shown in Figure 1(B) is A potential within the range in which the cell transistor CTr operates normally is pre-applied. Therefore, the operation of the semiconductor devices shown in Figures 1(A) and (B) can be considered similarly. It is possible.

[0049] <<Writing operation>> Figure 4(A) is a timing chart showing an example of the operation of writing data to a semiconductor device. The timing chart in Figure 4(A) shows the wiring WL[p] (where p is an integer between 1 and n). . ), wiring WL[j] (where j is an integer between 1 and n and not p) .) This shows the change in the magnitude of the potential in wiring BSL, wiring SSL, and wiring BL. The timing chart in Figure 4(A) shows an example of the operation of writing data to the memory cell MC[p]. This indicates that.

[0050] Prior to time T10, a low-level potential is supplied to wiring BL.

[0051] Furthermore, between time T10 and time T13, wiring SSL is always supplied with low-level power. A voltage is supplied. This applies a low-level potential to the gate of transistor STr. Therefore, transistor STr is turned off.

[0052] Between time T10 and time T11, a high-level potential was applied to the wiring BSL. It starts. As a result, between time T10 and time T11, the gate of transistor BTr Because the potential of the terminal reaches a high potential, the transistor BTr turns on. When transistor BTr turns on, the cell transistor of memory cell MC[n] A low-level potential supplied from wiring BL is applied to the first terminal of the CTr generator.

[0053] Between time T11 and time T12, the wiring WL[j] has a potential V PS The application This is initiated. As a result, between time T11 and time T12, memory cell MC[j] The potential of the control gate of the cell transistor CTr is potential V. PS It reaches this point. In the memory cell MC[n], the first terminal of the cell transistor CTr is supplied from the wiring BL. Because a low-level potential is supplied, the cell transistors of the memory cell MC[n] The zistar CTr is turned on. Also, this causes the cell of memory cell MC[n-1] A low-level potential supplied from wiring BL is applied to the first terminal of the transistor CTr. This means that the cell transistors CTr in the memory cell MC[j] are sequentially turned on. This is the result.

[0054] Furthermore, between time T11 and time T12, the wiring WL[p] has a potential V PG M The application of power is started. As a result, between time T11 and time T12, the memory cells The potential of the control gate of the cell transistor CTr in MC[p] is potential V. PGM Reach Furthermore, the aforementioned operation causes the cell transistor CTr of the memory cell MC[p] to Because a low-level potential supplied from wiring BL is applied to terminal 1, the memory cell MC[ Electrons are injected into the charge storage layer from the channel formation region of the cell transistor CTr possessed by [p]. This allows data to be written to the memory cell MC[p]. From the channel formation region of the cell transistor CTr in the recell MC[p] to the charge storage layer The injection of electrons increases the threshold voltage of the cell transistor CTr.

[0055] Up to time T12, the low-level potential supplied from wiring BL was transmitted to transistor ST Assume that the current is applied to the first terminal of r. Between time T12 and time T13, Low-level potential is applied to line WL[j] and wiring WL[p] from time T12 to time Between time point T13 and the current point, the potentials of wiring WL[j] and wiring WL[p] are at a low level. It becomes an electric potential.

[0056] From time T13 onward, a low-level potential is applied to the wiring BSL. After time T13, the gate potential of transistor BTr becomes low, The transistor BTr is turned off. Also, the timing chart in Figure 4(A) is shown. However, at this time, a low-level potential is not supplied to the wiring BSL, and the potential of the wiring BL is supplied to a high level. By setting the potential to a certain level, the transistor BTr can be turned off.

[0057] Through the above operations, data is written to the semiconductor device shown in Figures 1(A) and (B). It is possible.

[0058] <<Read operation>> Figure 4(B) is a timing chart showing an example of data reading operation from a semiconductor device. Yes. The timing chart in Figure 4(B) shows wiring WL[p] and wiring WL[q] (where q is 1 It is an integer between n and n and not p. ), wiring WL[j] (where j is 1 or greater An integer less than or equal to n and not p or q. ) Wiring BSL, Wiring SSL, Wiring S Indicates the change in the magnitude of the potential of L, and I is the current flowing between wiring SL and wiring BL READ of Indicates the change in magnitude. Note that the timing chart in Fig. 4(B) shows an example of the operation of reading data from memory cell MC [p] and memory cell MC[q]. And the electrons are injected into the charge storage layer of the cell transistor CTr of memory cell MC[p], and it is assumed that no electrons are injected into the charge storage layer of the cell transistor CTr of memory cell MC[q].

[0059] Prior to time T20, a low-level potential is supplied to wiring SL.

[0060] Between time T20 and time T21, a high-level potential is applied to wiring BSL and wiring SSL. As a result, between time T20 and time T21, the potentials of the gates of transistor BTr and transistor STr reach the high-level potential, so transistors BTr and transistor STr become on states. Also, when transistor STr becomes on, the low-level potential supplied from wiring SL is applied to the second terminal of the cell transistor CTr of memory cell MC[1].

[0061] Between time T21 and time T22, the application of potential V is started to wiring WL[q] and wiring WL[j]. As a result, between time T21 and time T22, the potentials of the control gates of the cell transistors CTr of memory cell MC[q] and memory cell MC[j] reach potential V PS PS At this time, memory cell MC[q] and memory cell MC ​​​​​​​​​[j] The second terminal of the cell transistor CTr is supplied with a low-level potential from the wiring SL. When applied, the cell transistor CTr turns ON.

[0062] Meanwhile, between time T21 and time T22, low-level electricity was supplied to wiring WL[p]. A position is applied. As a result, between time T21 and time T22, memory cell MC[ The control gate potential of the cell transistor CTr possessed by [p] becomes a low-level potential. Then, electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p]. Therefore, the threshold voltage of the cell transistor CTr of the memory cell MC[p] is rising. Therefore, for the reasons stated above, the cell transistor CTr of the memory cell MC[p] is in the off state. Therefore, no current flows between wiring SL and wiring BL. In other words, at this time, the current flowing through wiring BL is... By measuring the amount and showing that no current flows between wiring SL and wiring BL, the memory Electrons are injected into the charge storage layer of the cell transistor CTr in cell MC[p]. Yes, I can.

[0063] Between time T22 and time T23, wiring WL[p], wiring WL[q], wiring Low-level potential is supplied to each of the WL[j]. This starts from time T22. Between time T23 and the time T23, each of the memory cells MC[1] through MC[n] possesses The potential of the control gate of the cell transistor CTr becomes a low-level potential.

[0064] Between time T23 and time T24, the potential V is present in the wiring WL[j]. PS The supply is open This is initiated. As a result, between time T23 and time T24, the memory cell MC[j] The potential of the control gate of the cell transistor CTr is potential V. PS It reaches this point. Low power supplied from wiring SL to the first terminal of the cell transistor CTr of the Morisel MC[j] When a level potential is applied, the cell transistor CTr turns ON.

[0065] Furthermore, between time T23 and time T24, the potential V is applied to the wiring WL[p]. PS for The supply is started. As a result, between time T23 and time T24, the memory cell MC[ The control gate of the cell transistor CTr in p] is at potential V PS It reaches... Electrons are injected into the charge storage layer of the cell transistor CTr in the Morissel MC[p]. Therefore, the threshold voltage of the cell transistor CTr of the memory cell MC[p] is rising, The control gate of the cell transistor CTr has a potential V PS Because it is applied, in this example of operation The cell transistor CTr is assumed to be in an effectively ON state.

[0066] Then, between time T23 and time T24, low-level electricity was transmitted to wiring WL[q]. A position is applied. As a result, between time T23 and time T24, memory cell M The control gate potential of the cell transistor CTr possessed by C[q] becomes a low-level potential. Oh, the cell transistor CTr in the memory cell MC operates with normally-on characteristics. Therefore, the first terminal of the cell transistor CTr of the memory cell MC[q] is connected to the wiring SL or Even when a low-level potential is applied, the cell transistor CTr remains in the ON state. This is the result.

[0067] In other words, each cell tracer of memory cell MC[1] to memory cell MC[n] Because the converter CTr is in the ON state, current flows between each source and drain. In other words, at this time, the amount of current flowing through wiring BL is measured, and the current between wiring SL and wiring BL is measured. By indicating that current is flowing, the cell transistor C of the memory cell MC[q] It can be said that no electrons have been injected into the charge storage layer of Tr.

[0068] Between time T24 and time T25, wiring WL[p], wiring WL[q], wiring Low-level potential is supplied to each of the WL[j]. This starts from time T24. Between time T25 and the time T25, each of the memory cells MC[1] through MC[n] has The potential of the control gate of the cell transistor CTr becomes a low-level potential.

[0069] From time T25 onward, low-level potential is applied to wiring BSL and wiring SSL. This means that between time T25 and time T26, transistor BTr and transistor Because the potential of each gate of the STr transistor becomes a low-level potential, the BTr transistor And transistor STr turns off.

[0070] In other words, when reading data from a memory cell MC, the cell transistor of that memory cell MC... A low-level potential is applied to the control gate of the DISTA CTr, and the cells of the other memory cells MC are A high-level potential is applied to the control gate of the transistor CTr, causing a current to flow between wiring SL and wiring BL. By measuring the amount of current, it is possible to read the data held in the memory cell MC. It is possible.

[0071] Through the above operations, data can be written to the semiconductor device shown in Figures 1(A) and (B). And data can be read.

[0072] <<Erase Operation>> Figure 5(A) shows an example of the operation of erasing data held in a semiconductor device using timing control. This is a chart. The timing chart in Figure 5(A) shows the wiring WL[j] (where j is 1 The potentials of wiring BSL, wiring SSL, wiring BL, and wiring SL are between n and n (an integer greater than or equal to n). This shows the change in size. Note that the erase operation on NAND memory elements is performed one page at a time. It shall be conducted in the following order.

[0073] Before time T30, a low-level potential is supplied to wiring BL and wiring SL. .

[0074] Furthermore, between time T30 and time T33, wiring WL[j] always has a low level A potential is being supplied.

[0075] Between time T30 and time T31, high-level electrical currents were supplied to wiring BSL and wiring SSL. The position is started to be applied. As a result, between time T30 and time T31, the transient Because the gate potentials of both transistor BTr and transistor STr reach a high potential level. Transistors BTr and STr turn ON. Also, transistor B When Tr and transistor STr are turned ON, the memory cell MC[1] has A low-level potential supplied from the wiring SL is applied to the second terminal of the cell transistor CTr. Then, the first terminal of the cell transistor CTr of the memory cell MC[n] is connected to the wiring BL. A low-level potential supplied from there is applied.

[0076] Between time T31 and time T32, the potential V is present in wiring BL and wiring SL. ER mark The addition begins. Note that the potential V ER This is because the high-level potential flowing through wiring BL and wiring SL is greater than The potential is also set to a high level. As a result, between time T31 and time T32, The cells of all cell transistors CTr in the recell MC[1] or memory cell MC[n] Because the potential of the channel formation region rises, the charge injected into the charge storage layer of each cell transistor CTr The electrons that are present are pulled out towards the channel-forming region.

[0077] Between time T32 and time T33, wiring BL and wiring SL had a low-level potential The application process begins.

[0078] From time T33 onward, low-level potential is applied to wiring BSL and wiring SSL. This means that between time T33 and time T34, transistor BTr and transistor Because the potential of each gate of the STr transistor becomes a low-level potential, the BTr transistor And transistor STr turns off.

[0079] The above operations will erase the data from the semiconductor device shown in Figures 1(A) and (B). It is possible.

[0080] Furthermore, in the semiconductor device shown in Figure 1(B), by using wiring BGL, the above-mentioned A different erasure operation can be performed from the one described above. An example of this operation is shown in Figure 5(B). vinegar.

[0081] Before time T40, a low-level potential is supplied to wiring BL and wiring SL. .

[0082] Furthermore, between time T40 and time T45, wiring WL[j] is always at a low level. A potential is supplied.

[0083] Between time T40 and time T41, low-level electrical currents were transmitted to wiring BSL and wiring SSL. The application of the position is initiated. As a result, between time T40 and time T41, the transistor Because the gate potentials of transistors BTr and STr become low-level potentials, Transistors BTr and STr are turned off. Therefore, the transistors The first terminal of STr and the first terminal of transistor BTr are in a floating state. .

[0084] Furthermore, between time T40 and time T41, the potential V is present in wiring BGL. BGER mark The addition begins. Note that the potential V BGER The potential is set to a very high potential. Transistor STr The first terminal of the device and the first terminal of transistor BTr are in a floating state, and at time T Between 40 and time T41, the potential of wiring BGL is V BGER As a result, memo The cells of all cell transistors CTr in the recell MC[1] or memory cell MC[n] The potential of the channel formation region is boosted by capacitive coupling. Therefore, each cell transistor C Electrons injected into the charge storage layer of the transistor are pulled out towards the channel formation region.

[0085] Between time T41 and time T42, high-level electricity was supplied to wiring BSL and wiring SSL. The application of the position is initiated. As a result, between time T41 and time T42, the transient Because the gate potentials of both transistor BTr and transistor STr reach a high potential level. Transistor BTr and transistorr STr are turned on.

[0086] Between time T42 and time T43, the application of a high-level potential to wiring BL is started. As a result, between time T42 and time T43, electrons extracted from the charge storage layer of cell transistor CT r can flow through wiring BL. Between time T43 and time T44, the application of a low-level potential to wiring BL is started. Subsequently, at time T44, the application of a low-level potential to wiring BSL and wiring SSL is started. As a result, since the potential of each gate of transistorr BTr and transistorr STr becomes a low-level potential, transistorr BTr and transistorr STr are turned off. Finally, after time T45, a low-level potential is supplied to wiring BGL.

[0087] Between time T43 and time T44, the application of a low-level potential to wiring BL is started. Subsequently, at time T44, the application of a low-level potential to wiring BSL and wiring SSL is started. As a result, since the potential of each gate of transistorr BTr and transistorr STr becomes a low-level potential, transistorr BTr and transistorr STr are turned off. Finally, after time T45, a low-level potential is supplied to wiring BGL. As described above, by using wiring BGL, data can also be erased from the semiconductor device shown in Fig. 1(B).

[0088] As described above, by using wiring BGL, data can also be erased from the semiconductor device shown in Fig. 1(B).

[0089] <Structural Example and Manufacturing Method Example 1> Hereinafter, in order to help understand the structure of the semiconductor device having the circuit configurations of Figs. 1 to 3 described above, the manufacturing method thereof will be described.

[0090] Figs. 6(A), (B), and (C) are examples of schematic diagrams showing the semiconductor device of Fig. 2 or Fig. 3. Fig. 6(A) shows a perspective view of the semiconductor device, and Fig. 6(B) shows a top view of Fig. 6(A). Further, Fig. 6(C) shows a cross-sectional view corresponding to the dashed line A1 - A2 in Fig. 6(B). Fig. 6(A) shows a perspective view of the semiconductor device, and Fig. 6(B) shows a top view of Fig. 6(A). Further, Fig. 6(C) shows a cross-sectional view corresponding to the dashed line A1 - A2 in Fig. 6(B).

[0091] ​​​​ The semiconductor device has a structure in which wiring WL and an insulator (a region not shown with hatching in FIG. 6) are laminated.

[0092] In addition, an opening is formed so as to penetrate the insulator and the wiring WL through the structure at once. And, in order to provide the memory cell MC in the region AR through which the wiring WL penetrates, an insulator, a conductor, and a semiconductor are formed in the opening. Note that the conductor functions as a source electrode or a drain electrode of the cell transistor CTr of the memory cell MC, and the semiconductor functions as a channel formation region of the cell transistor CTr. Also, without forming the conductor, a channel formation region and a low resistance region are formed in the semiconductor, and the low resistance region may be applied as a source electrode or a drain electrode of the cell transistor CTr. In FIGS. 6(A), (B), and (C), the region where an insulator, a conductor, and a semiconductor are formed in the opening is illustrated as a region HL. In particular, in FIG. 6(A), the region HL included in the structure is illustrated with a broken line. When a back gate is provided in the transistor included in the memory cell MC, the conductor included in the region HL may also function as a wiring BGL for electrically connecting to the back gate. That is, in FIG. 6, it shows that the semiconductor device shown in any of FIGS. 1(A) and (B) is formed in the region SD1, and the semiconductor device shown in FIG. 2 or FIG. 3 is formed in the region SD2.

[0093]

[0094] By the way, the region TM where the wiring WL is exposed is a connection terminal for applying a potential to the wiring WL. ​​​​​​​​It functions as a child. In other words, by electrically connecting the wiring to the region TM, the celltra A potential can be applied to the gate of the converter CTr.

[0095] The shape of region TM is not limited to the configuration example shown in Figure 6. The device is configured such that, for example, an insulator is formed on the region TM shown in Figure 6, and an opening is made in the insulator. A section may be provided, and a conductive material PG may be formed to fill the opening (Figure 7(A), (B), (C)). Note that wiring ER is formed on the conductive material PG, This electrically connects wiring ER and wiring WL. Note that in Figure 7(A) The conductive material PG contained within the structure is shown with a dashed line, and the dashed line of region HL is omitted. It is.

[0096] In the following example of a fabrication method 1, memory cells MC shown in Figures 1 to 3 are formed in region AR. I will explain the method for doing so.

[0097] <<Example of manufacturing method 1>> Figures 8 to 14 are cross-sectional views illustrating an example of the fabrication of the semiconductor device shown in Figure 1(A). In particular, Figure 8 shows a cross-sectional view of the cell transistor CTr in the channel length direction. In the cross-sectional view of Figure 14, some elements have been omitted for clarity.

[0098] As shown in Figure 8(A), the semiconductor device in Figure 1(A) is located above the substrate (not shown). An insulator 101A is placed, a conductor 132A is placed on the insulator 101A, and a conductor An insulator 101B placed on 132A, and a conductor 132 placed on the insulator 101B It has B and an insulator 101C placed on the conductor 132B. A laminate having a plurality of conductors and a plurality of insulators (in subsequent processes, insulators, conductors, etc. other than these may also be included.) is referred to as laminate 100. is also included.)

[0099] As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, there are a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, etc. Also, as the semiconductor substrate, for example, semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Further, there are semiconductor substrates in which an insulator region is included inside the aforementioned semiconductor substrates, for example, SOI (Silicon On Insulator) substrates, etc. As the conductor substrate, there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. Or, there are substrates having a nitride of a metal, substrates having an oxide of a metal, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulator substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, those in which elements are provided on these substrates may be used. As the elements provided on the substrate, there are a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, etc. There are also substrates having a nitride of a metal, substrates having an oxide of a metal, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulator substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, those in which elements are provided on these substrates may also be used. As the elements provided on the substrate, there are a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, etc.

[0100] Also, a flexible substrate may be used as the substrate. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the flexible substrate. In that case, between the non-flexible substrate and the transistor After fabricating a transistor on a non-flexible substrate, the transistor is peeled off and transferred to a flexible substrate. There is also a method of peeling off the transistor and transferring it to a flexible substrate. In that case, between the non-flexible substrate and the transistor It is preferable to provide a release layer between the inverter and the substrate. Furthermore, a sheet with woven fibers can be used as the substrate. A film or foil may be used. The substrate may also be stretchable. It may have the property of returning to its original shape when the bending or pulling is stopped. It may have the property of not returning to its original shape. The substrate may be, for example, 5 μm to 700 μm. More preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. It has a region that constitutes thickness. Thinning the substrate makes semiconductor devices containing transistors lighter. This is possible. Also, by making the substrate thinner, flexibility can be improved even when using glass or other materials. This may include properties that allow the material to return to its original shape after bending or pulling is stopped. Therefore, it is necessary to mitigate the impact applied to the semiconductor device on the substrate due to drops, etc. This allows us to provide robust semiconductor devices.

[0101] Flexible substrates include, for example, metals, alloys, resins, or glass, or their fibers. Fibers and other materials can be used. The lower the coefficient of thermal expansion of the flexible substrate, the more deformation due to the environment is suppressed. It is preferable to have it controlled. As a flexible substrate, for example, if the coefficient of thermal expansion is 1 × 10 -3 / K or less, 5 x 10 -5 / K or less, or 1 × 10 -5 Materials with a temperature of / K or less should be used. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.) Examples include polyimide, polycarbonate, and acrylic. In particular, aramid has a high coefficient of thermal expansion. Because of its low coefficient of friction, it is suitable as a flexible substrate.

[0102] In the manufacturing example described in this embodiment, a heat treatment is included in the process, so the substrate Therefore, it is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0103] Conductor 132A (conductor 132B) functions as wiring WL as shown in Figure 1(A).

[0104] Examples of conductors 132A and 132B include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanilla Dium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metallic elements selected from thenium and others can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like nitrates, Silicides such as nickel silicide may also be used.

[0105] Furthermore, the conductors 132A and 132B are applicable to the semiconductor 151 described later. A conductive material containing metal elements and oxygen found in metal oxides may also be used. Conductive materials containing metallic elements and nitrogen may also be used. For example, titanium nitride, tantalum nitride. Conductive materials containing nitrogen, such as tincture, may also be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide with added silicon may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By being present, it may be possible to capture hydrogen or water that may be introduced from surrounding insulators, etc. be.

[0106] Furthermore, conductors 132A and 132B suppress the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material that has a controlling function. For example, tantalum, tantalum nitride It is preferable to use materials such as titanium, titanium nitride, ruthenium, or ruthenium oxide. It can be a single layer or a multi-layer structure.

[0107] Furthermore, multiple conductive materials formed from the above materials may be stacked and used. For example, as described above. A laminated structure may be formed by combining a material containing a metallic element with a conductive material containing oxygen. Furthermore, for example, a combination of a material containing the aforementioned metal element and a conductive material containing nitrogen. A laminated structure may also be used. For example, a material containing the aforementioned metal element and oxygen may be used. A laminated structure combining a conductive material and a conductive material containing nitrogen may also be used. By applying an insulator having an excess oxygen region as an insulator in contact with a conductor, the insulation of the conductor can be improved. In the region in contact with the edge, oxygen may diffuse. This can affect materials containing metallic elements. A laminated structure may be formed by combining the material and an oxygen-containing conductive material. Furthermore, by applying an insulator having an excess nitrogen region as an insulator in contact with the conductor, the conductor In the region in contact with the insulator, nitrogen may diffuse. This can cause metallic elements to be present. A laminated structure may be formed by combining a non-conductive material with a conductive material containing nitrogen.

[0108] Note that conductor 132A and conductor 132B may each be made of the same material. Furthermore, they may be made of different materials. In other words, a semiconductor device according to one aspect of the present invention is constructed. The materials to be applied to the conductor 132A and conductor 132B are selected and used as appropriate. can.

[0109] There are no particular limitations on the method for forming the conductors 132A and 132B. For example, sputtering CVD method (including thermal CVD, MOCVD, PECVD, etc.), MBE (Mol ecular beam epitaxy) method, ALD (Atomic Layer D) eposition) method, PLD (Pulsed Laser Deposition) It can be formed by methods such as [specific method / technology].

[0110] The insulators 101A to 101C may have impurity concentrations such as water or hydrogen. It is preferable that the material has reduced properties. For example, insulator 101A to insulator 101 The amount of hydrogen desorbed from C is determined by thermal desorptiometry (TDS). In spectroscopy, the surface temperature of the insulating film is 50°C or higher. In the range below 0°C, the amount of desorption converted to hydrogen molecules is insulator 101A to insulator Convert to a value per unit area of ​​any one of the 10¹C values, then 2 × 10 15 molecular / cm² 2 The following is preferably 1 × 10 15 molecular / cm² 2 The following is more convenient 5x 10 14 molecular / cm² 2 The following is acceptable. Also, insulator 101A or insulation Body 101C may be formed using an insulator that releases oxygen upon heating.

[0111] Examples of insulators 101A to 101C include boron, carbon, nitrogen, oxygen, and f Electrolyte, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Manium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum Insulators containing silicon dioxide can be used in single-layer or multi-layer configurations. Also, for example, silicon dioxide Materials containing silicon oxide or silicon nitride can be used.

[0112] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials with a higher nitrogen content than oxygen content.

[0113] There are no particular limitations on the method for forming insulators 101A to 101C. For example, sputtering CVD method, CVD method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, A The film can be deposited using methods such as LD (laser-diode) and PLD (polyluminescent) deposition.

[0114] In the next step, as shown in Figure 8(B), resist mask formation and etching processes are performed. Therefore, an opening 191 is formed in the laminate 100 shown in Figure 8(A).

[0115] The resist mask can be formed using methods such as lithography, printing, or inkjet. It can be used as appropriate. When a resist mask is formed by the inkjet method, a photomask is formed. Since no carbide is used, manufacturing costs can be reduced. Also, for the etching process, Either the dry etching method or the wet etching method may be used, or both may be used.

[0116] Then, as shown in Figure 9(A), etching is used to remove the side surface of the opening 191. A portion of the conductors 132A and 132B located therein is removed, and the side surface Recesses 192A and 192B are formed. Here, conductors 132A and 132B In this configuration, the conductors 132A and 132B are selectively removed from the laminate 100. Materials like (for example, etched rather than insulators 101A, 101B, and 101C) It is assumed that high-grade materials are being used.

[0117] In the next step, as shown in Figure 9(B), the side of the opening 191 shown in Figure 9(A), and An insulator 102 is formed in the recesses 192A and 192B.

[0118] The insulator 102 functions as a gate insulating film for the cell transistor CTr.

[0119] For the insulator 102, it is preferable to use, for example, silicon oxide or silicon oxide-nitride. It seems. Also, as the insulator 102, for example, aluminum oxide, hafnium oxide, Alternatively, oxides containing aluminum and hafnium can be used. The edge 102 may be an insulator formed by laminating these elements.

[0120] For forming the insulator 102, it is preferable to use a film formation method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method (LPCVD (Low Pressure CVD) method, PCVD (Plasma Methods such as CVD may also be used. Alternatively, another film deposition method could be, for example, spat In some cases, methods such as taring can be used.

[0121] In the next step, as shown in Figure 10(A), the side of the opening 191 shown in Figure 9(B), and An insulator 111 is formed in the recess that is formed. In other words, on the surface on which the insulator 102 is formed An insulator 111 is formed.

[0122] In the region where the insulator 111 is formed, via the insulator 104 described later, the semiconductor described later The region superimposed on region 151a of body 151 is the charge storage layer of the cell transistor CTr. It works.

[0123] For the insulator 111, it is preferable to use, for example, silicon nitride or silicon nitride oxide. It seems so.

[0124] The method for forming the insulator 111 should be considered in relation to the description of the method for forming the insulator 102.

[0125] In the next step, as shown in Figure 10(B), the side of the opening 191 shown in Figure 10(A) And an insulator 104 is formed in the recessed area. In other words, the surface on which the insulator 111 is formed. An insulator 104 is formed thereon.

[0126] The insulator 104 functions as a tunnel insulating film for the cell transistor CTr.

[0127] For the insulator 104, for example, silicon oxide or silicon oxide-nitride is preferable. It seems so. Also, as the insulator 104, aluminum oxide, hafnium oxide, or aluminum Oxides containing nium and hafnium may also be used. In addition, as for the insulator 104 These may be laminated to form an insulator. And the insulator 104 is thicker than the insulator 102. Thin is preferable. By making the insulator 104 thinner than the insulator 102, the semiconductor described later can be made thinner. Charge transfer occurs from body 151 to insulator 111 via insulator 104 due to tunneling effect. It is possible to do so.

[0128] The method for forming the insulator 104 should be considered in relation to the description of the method for forming the insulator 102.

[0129] Next, as shown in Figure 11(A), the side view of the opening 191 shown in Figure 10(B), and the formation A semiconductor 151 is formed in the recessed area. In other words, a semiconductor is formed on the surface of the insulator 104. 151 is formed.

[0130] As the semiconductor 151, for example, a material containing a metal oxide as described in Embodiment 4. Materials can be applied. For example, materials containing silicon can be applied. This is possible. In particular, it is preferable that the silicon is polycrystalline.

[0131] By the way, if semiconductor 151 contains a metal oxide, the insulating material in contact with semiconductor 151 Body 104 has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is preferable to use an edge material. By forming such an insulator 104, the insulator 1 Impurities such as water or hydrogen enter through O4 and react with the oxygen contained in semiconductor 151. In some cases, this can prevent the formation of water. When water is generated within semiconductor 151, Oxygen vacancies may form within the conductor 151. Impurities such as hydrogen may fill these oxygen vacancies. When electrons enter, carrier electrons may be generated. Therefore, semiconductor 151 Within the molecule, if there is a region containing a large amount of hydrogen, that region is a channel-forming region. The transistors contained in this tend to exhibit normally-on characteristics. To prevent this, an insulator is used. As 104, it has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is desirable to use insulating materials.

[0132] Next, we will explain the process shown in Figure 11(B).

[0133] When a material having a metal oxide is applied as the semiconductor 151, the side of the opening 191 The formation surface of the semiconductor 151 located at this location may be subjected to a process of supplying oxygen. In summary, the supply process 10 shown in Figure 11(B) is considered as a process for supplying oxygen. Examples of such processes include plasma treatment containing oxygen under reduced pressure, and treatment in an oxygen atmosphere. Examples include heat treatment. In particular, plasma treatments containing oxygen include, for example, microwaves. It is preferable to use a device that has a power supply for generating the high-density plasma used. The supply process 10 described here may not always be necessary.

[0134] Furthermore, when a material containing silicon is used as the semiconductor 151, the aperture 191 An impurity supply process may be performed on the formation surface of the semiconductor 151 located on the side. In this case, the supply process 10 shown in Figure 11(B) is considered as a process for supplying impurities. It is preferable to perform heat treatment on the semiconductor device while the supply process 10 is being carried out. For example, p-type impurities (acceptors) can be used as impurities. For example, boron, aluminum, gallium, etc. can be used. Also, for example, impurities As for the material, n-type impurities (donors) can be used. Examples of n-type impurities include phosphorus, Arsenic and other substances can be used. Note that the supply process 10 described here is not necessarily required. There are times when it's not necessary.

[0135] For forming the semiconductor 151, it is preferable to use a film deposition method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0136] In the next step, as shown in Figure 12(A), the side of the opening 191 shown in Figure 11(B) And an insulator 109 is formed in the recessed area. In other words, the formation surface of the semiconductor 151 An insulator 109 is formed thereon.

[0137] The components contained in the insulator 109 include the interface with the previously formed semiconductor 151, and the interface In the vicinity, it is preferable that the components are not components that form compounds with components contained in semiconductor 151. Alternatively, even if the compound is formed, it is preferable that the compound be an insulator. It is not possible. Or, even if such a compound is formed, such a compound is not possible in semiconductor 151. Therefore, it is preferable that the compound does not contribute as a carrier.

[0138] For example, silicon oxide can be used as the insulator 109.

[0139] The method for forming the insulator 109 should be considered in relation to the description of the method for forming the insulator 102.

[0140] In the next step, as shown in Figure 12(B), resist mask formation and etching are performed, etc. As a result, the insulating material included in the opening 191 is such that the insulating material 109 remains only in the aforementioned recess. A portion of body 109 is removed. This forms insulators 109a and 109b. In this case, if the insulator 104 is not exposed to the opening 191, the semiconductor Part of 151 may be removed.

[0141] For details on the formation of the resist mask and the etching process, please refer to the explanation in Figure 8(B). To pour a drink.

[0142] By the way, when a material having a metal oxide is used as semiconductor 151, the formation The side surface of the opening 191 may be treated by supplying impurities such as hydrogen. In this case, the process for supplying impurities such as hydrogen is shown in the supply process 1 in Figure 13. Let's consider step 1 as a process for supplying impurities such as hydrogen. In Figure 13, the supply process 11 is an absolute process. This process is performed on the edge material 109a, the insulator 109b, and the semiconductor region 151b. Figure 13 shows the components contained in the semiconductor 151 and the impurities supplied by the supply process 11. Compound 161A (compound 161B, compound 161C) is described as a compound containing the above. This process reduces the resistance of region 151b of semiconductor 151. Yes, it is possible. However, the supply process 11 described here may not always be necessary.

[0143] Furthermore, when a material containing silicon is applied as the semiconductor 151, The side surface of the opening 191 may be treated to supply impurities. In this case, Regarding the process of supplying impurities, the supply process 11 shown in Figure 13 is referred to as the process of supplying impurities. Let's consider this. In Figure 13, the supply process 11 consists of insulator 109a, insulator 109b, and semiconductor. This is performed on region 151b of body 151. Note that while supply processing 11 is being performed, It is preferable to heat treat the laminate 100. Examples of impurities include phosphorus. n-type impurities (donors) such as arsenic can be used. Also, for example, as an impurity This allows the use of p-type impurities (acceptors) such as boron, aluminum, and gallium. This process allows the semiconductor 151 to be formed in region 151b of semiconductor 151. On the surface and near the surface, there are impurity regions 162A (impurity region 162B, impurity region 162C This allows for the formation of a region 151b of the semiconductor 151, thereby reducing its resistance. Oh, if the supply process 10 in Figure 11(B) explained earlier is being performed, then the supply process explained here Procedure 11 is not necessarily required.

[0144] Furthermore, the semiconductor 151 may be a material having either silicon or a metal oxide. When used, insulators 109a and 109b are formed on the formation surface of the semiconductor 151. In the region 151a, insulators 109a and 109b act as a mask to block impurities. Because it has a shielding role, no impurities are supplied to region 151a of semiconductor 151.

[0145] In the next step, as shown in Figure 14(A), insulation is applied to the side surface of the opening 191 shown in Figure 13. Body 105 is formed into a film.

[0146] If the semiconductor 151 is a material containing a metal oxide, the insulator 105 may be, for example, nitrogen It is preferable that silicon dioxide is included. The semiconductor 151 is in contact with the insulator 105. In the field where nitrogen, nitrides, and other components contained in the insulator 105 diffuse into the semiconductor 151 There is a possibility of heat treatment being performed on the laminate 100 at this time. Good. As a result, in Figure 14(A), the semiconductor 151 has an interface with the insulator 105, and And near the interface, nitrogen, nitrides, and other components diffused from the insulator 105 In some cases, compound 161A (compound 161B, compound 161C) may be formed. As a result, region 151b of semiconductor 151 has reduced resistance. In other words, adjacent cell transistors In the electrical connection of a CTr (radiosecond transformer), it may be possible to reduce the resistance.

[0147] Furthermore, if the semiconductor 151 is a material containing silicon, the insulator 105 may be, for example, It is preferable that the semiconductor 151 contains impurities (elements or ions) for diffusion. For example, n-type impurities (donors) such as phosphorus and arsenic can be used as the impurities in question. It is possible. Also, for example, such impurities include boron, aluminum, and gallium. Which p-type impurities (acceptors) can be used?

[0148] When semiconductor 151 comes into contact with insulator 105, impurities (elements, In some cases, ions may diffuse into the semiconductor 151. Also, at this time, the laminate 100 Heat treatment may or may not be performed on the semiconductor 151. The interface in contact with 05, and the vicinity of the interface, contain impurity regions 162A (impurity region 162B, impurity region In some cases, region 162C is formed, and region 151b of semiconductor 151 becomes less resistive.

[0149] The method for forming the insulator 105 should be considered in relation to the description of the method for forming the insulator 102.

[0150] Figures 13 and 14(A) show how to reduce the resistance of region 151b of semiconductor 151, respectively. This shows the process. In other words, Figures 13 and 14(A) show the region of semiconductor 151. Compound 161A (compound 161B, compound 161C) in 151b, or impurity region 162 This shows the process of forming A (impurity region 162B, impurity region 162C). In the process of manufacturing semiconductor devices, Figures 13 and 14(A) show either one of the processes. You can do either one. In some cases, you may also perform both steps.

[0151] In the next step, as shown in Figure 14(B), the remaining opening 191 is filled with insulation. An insulator 106 is formed on the surface of the body 105.

[0152] The insulator 106 has a function of suppressing the permeation of impurities such as water and hydrogen. It is preferable to use an insulating material. For example, as the insulator 106, aluminum oxide Materials such as M can be used. However, the materials that can be applied to the insulator 106 are not limited to those mentioned above. As the insulator 106, for example, as a film with reduced impurity concentrations such as water and hydrogen, Materials applicable to the insulators 101A to 101C described above can be used.

[0153] Furthermore, as an example of the insulator 106, an insulator having the function of suppressing oxygen permeation is used. It is preferable to use a suitable material. For example, as the insulator 106, silicon nitride, oxide nitride By using silicon, silicon oxide nitride, aluminum nitride, aluminum oxide nitride, etc. This is preferable. By forming such an insulator 106, the semiconductor 151 can form a metal oxide When the material contains oxygen, the oxygen contained in the semiconductor 151 is desorbed, and the insulator 105 , and / or via insulator 109a (insulator 109b), the oxygen spreads to insulator 106. In some cases, it is possible to prevent dispersion. This reduces the oxygen concentration of semiconductor 151. It can sometimes be prevented.

[0154] Furthermore, as an example of the insulator 106, an insulating material having the function of permeating oxygen may be used. It is preferable to use the following. For example, doping the insulator 106 with oxygen, and the insulator 105, and / or by diffusing oxygen through the insulator 109a (insulator 109b), In some cases, oxygen can be supplied to semiconductor 151. This allows the acid in semiconductor 151 to be supplied. In some cases, it is possible to increase the elementary concentration.

[0155] For example, aluminum oxide can be used as the insulator 106. When nium is deposited by sputtering, oxygen forms insulator 105 and / or insulator 109 It is supplied to a (insulator 109b). Insulator 105, and / or insulator 109a (insulator The oxygen supplied to 109b) is supplied to semiconductor 151. As a result, semiconductor 151 In some cases, it may be possible to increase the oxygen concentration.

[0156] The method for forming the insulator 106 should be considered in relation to the description of the method for forming the insulator 102.

[0157] By the way, conductor 132A (conductor 132B) is a cellulose tran shown in Figure 1(A)(B). It functions as the gate electrode of the zista CTr and the wiring WL. That is, as shown in Figure 14(B). In region 181A (region 181B), a cell transistor CTr is formed.

[0158] As described above, by performing the steps from Figure 8(A) to Figure 14(B), Figure 1(A) The semiconductor device shown can be fabricated.

[0159] Figures 15(A) and 15(B) show the dashed line B1-B of the semiconductor device shown in Figure 14(B), respectively. 2. The top view is shown along the dashed line B3-B4. Also, Figure 16 shows the structure shown in Figure 6. The example shows a top view of a semiconductor device with multiple openings 191. The top view in question is a top view of the semiconductor device shown in Figure 14(B) along the dashed line B1-B2. The diagram shows the case where multiple openings 191 are provided. The placement is not limited to the positions shown in Figure 16, and can be freely determined during the circuit design stage.

[0160] One aspect of the present invention is not limited to the semiconductor device configuration example shown in Figure 14(B). One embodiment of this configuration is one in which the semiconductor device shown in Figure 14(B) is modified as appropriate.

[0161] For example, a semiconductor device according to one aspect of the present invention is provided with a back gate for a cell transistor. A digit configuration is also possible. When a back gate is provided for the cell transistor, see Figure 14(B Instead of forming an insulator 106 in ), a conductor 1 is formed so that the opening 191 is filled. 34 can be deposited as a film. By changing the process in this way, the semiconductor device shown in Figure 17 can be formed. It is possible to configure the arrangement.

[0162] In this case, the conductor 134 functions as wiring BGL as shown in Figures 1(B) and 3.

[0163] The conductor 134 is a material that can be applied to the conductor 132A (conductor 132B) described above. You can use it.

[0164] For forming the conductive material 134, it is preferable to use a film formation method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0165] Note that in Figures 18(A) and (B), the dashed lines B1-B of the semiconductor device shown in Figure 17 are shown in the respective diagrams. 2. The top view is shown along the dashed line B3-B4. The semiconductor device shown in Figure 17 is conductive Since this is an example of a configuration in which body 134 is formed, the top view shown in Figure 18(A)(B) is the same as Figure 1 The configuration shown in 5(A)(B) has a conductor 134 formed in place of the insulator 106. ru.

[0166] The insulator 105 shown in Figure 17 may also be configured as a laminate consisting of multiple insulators. As an example of a laminated structure consisting of multiple insulators, the insulator described in the explanation of Figure 14(B) A laminated configuration of 105 and an insulator 106 may also be used (not shown).

[0167] Furthermore, for example, the semiconductor device according to one embodiment of the present invention may have some of its manufacturing processes modified. Figures 19(A), (B), and 20 show a region 151b of semiconductor 151 that differs from that in Figure 13. This shows the process of forming a low-resistance region. The process shown in Figure 19(A) is shown in Figure 12(B). The following step shows how to form a conductor 139 on the side surface of the opening 191 after the indicated step. In other words, the formation of the insulator 109a (insulator 109b) and the semiconductor region 151b. A conductive material 139 is formed on the surface.

[0168] Furthermore, if the semiconductor 151 has a material containing a metal oxide, the conductor 139 is, for example, For example, it has the role of reducing the resistance of the region 151b of the semiconductor 151 that is in contact with the conductor 139. It is preferable that the material is a conductor 139 with a resistance value of 2.4 × 10 3 [Ω / s q] Preferably 1.0 × 10 3 Metals and elements containing metallic atoms with a density of [Ω / sq] or less. An oxide containing an oxide or metallic element is used. For example, aluminum is used as the conductor 139. Metal films such as um, ruthenium, titanium, tantalum, tungsten, and chromium, Al-Ti Nitrides, nitride films containing metallic elements such as titanium nitride, or indium tin oxide, In- An oxide film containing a metallic element such as Ga-Zn oxide can be used.

[0169] If the semiconductor 151 has a material containing a metal oxide, the semiconductor 151 is in contact with the conductor 139. By performing heat treatment, the components contained in the conductor 139 and the semiconductor 151 are combined. Compound 161A (compound 161B, compound 161C) is formed by the components, In some cases, region 151b of semiconductor 151 may have its resistance reduced. Note that at least semiconductor 15 It is sufficient that the interface in contact with the conductor 139, and the area near the interface, have low resistance. Oxygen in semiconductor 151 located at the interface between semiconductor 151 and conductor 139, or near said interface A portion of it is absorbed by the conductor 139, and an oxygen vacancy is formed in the semiconductor 151, resulting in region 151b This is thought to be because the resistance is reduced.

[0170] Alternatively, in addition to the above, the semiconductor 151 and the conductor 139 are in contact with a nitrogen-containing Heat treatment may be performed under atmospheric conditions. Through this heat treatment, the conductor 139 is converted to a conductor The metal elements that make up component 139 become semiconductor 151, or the metal elements that make up semiconductor 151 The element diffuses into the conductor 139, and the semiconductor 151 and the conductor 139 form a metal compound. In some cases, the metallic elements of semiconductor 151 and the metallic elements of conductor 139 may be They may be alloyed. The metallic elements of semiconductor 151 and the metallic elements of conductor 139 are alloyed. This process allows the metal elements to enter a relatively stable state, thus providing highly reliable semiconductor devices. It is possible.

[0171] By the way, the hydrogen contained in semiconductor 151 is acid present in region 151b of semiconductor 151. Entering a primary defect results in a relatively stable state. Also, the acid present in region 151a Hydrogen in elementary defect escapes from oxygen vacancies through heat treatment at temperatures above 250°C, resulting in region 151. By diffusing into b and entering the oxygen deficiency present in region 151b, it becomes relatively stable. Therefore, through heat treatment, region 151b becomes less resistant, and region 151a becomes higher purity. The material is purified (impurities such as water and hydrogen are reduced), resulting in higher resistance.

[0172] Furthermore, if the semiconductor 151 is a silicon-containing material, the conductor 139 may be, for example, It is a material that can be applied to conductor 132A (conductor 132B), and conductor 132A (conductor Materials applicable to the electrochemical body 132B) include impurities (elements, or) for diffusion into the semiconductor 151. It is preferable that it contains (ions). Examples of such impurities include phosphorus, arsenic, etc. Any n-type impurity (donor) can be used. For example, boron, aluminum. In addition, p-type impurities (acceptors) such as gallium can be used. Depending on the circumstances, heat treatment may be performed on the laminate 100. The semiconductor 151 contains impurities. By contact with the conductive material 139, the interface of the semiconductor 151 that is in contact with the conductive material 139, And the impurity is diffused near the interface, impurity region 162A (impurity region 162B, impurity A pure matter region (162C) is formed.

[0173] If the impurity contained in the conductor 139 is an n-type impurity (donor), the domain of semiconductor 151 An n-type impurity region is formed in region 151b, or near the interface between semiconductor 151 and the conductor 139. This can occur. On the other hand, the impurities contained in the conductor 139 are p-type impurities (acceptors). In this case, region 151b of semiconductor 151, or near the interface of semiconductor 151 with conductor 139 In some cases, a p-type impurity region may be formed. This results in region 151b of semiconductor 151. Alternatively, carriers are formed near the interface between the semiconductor 151 and the conductor 139, and region 151b Resistance may be reduced.

[0174] Furthermore, the conductor 139, in combination with the silicon contained in the semiconductor 151, Any material that can form sides is also acceptable. For example, nickel, cobalt, molybdenum, etc. Sten, titanium, etc., are also acceptable. Alternatively, any material with high conductivity can be used as the conductor 139. That's fine. For example, aluminum, copper, silver, etc. would also be acceptable. Alternatively, as the conductor 139, Materials with high thermal properties are also acceptable. For example, titanium, molybdenum, tungsten, tantalum, etc. That's good too.

[0175] Furthermore, by performing heat treatment at this time, the conductive material contained in the conductor 139 and semiconductor 1 Depending on the components contained in 51, metal silica is present near the interface between the semiconductor 151 and the conductor 139. A silicide may be formed. In this case, as a metal silicide, compound 1 is shown in Figure 19(A). 61A (compound 161B, compound 161C) is shown in the diagram. Also, the chemical composition of semiconductor 151 is shown. An impurity region 162A is located near the interface with compound 161A (compound 161B, compound 161C). Impurity regions 162B and 162C may be formed.

[0176] In other words, by the above-described fabrication method, the region 151b of the semiconductor 151 is formed as a low-resistance region. This can be achieved, and the region 151a of the semiconductor 151 can be formed as a channel formation region. This is possible. Note that region 151b, which is a low-resistance region, is the third region in the cell transistor CTr. Since it corresponds to terminal 1 and / or terminal 2, by the manufacturing method described above, it is electrically connected in series. This can lower the electrical resistance between connected cell transistors.

[0177] For forming the conductive material 139, it is preferable to use a film formation method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0178] In the process shown in Figure 19(B), etching is used to create a lithography process on the side surface of the opening 191. The conductive material 139 is removed. At this time, the insulator 109a (insulator 1 The interface between the conductor 139 and the conductor 09b), and a portion of the area near the interface, may be removed. .

[0179] Next, as shown in the process in Figure 20, fill the remaining opening 191 in Figure 19(B), The insulator 106 is formed into a film. The manufacturing process described above differs from the process shown in Figure 13. In the manufacturing process, a semiconductor device is formed in which a low-resistance region is formed in region 151b of semiconductor 151. It can be manufactured.

[0180] Note that Figures 21(A) and (B) show the dashed line B1- of the semiconductor device shown in Figure 20, respectively. Figure 20 shows a top view of the area B2 and the dashed line B3-B4. This configuration example omits the formation of the edge 105, therefore the upper surface shown in Figures 21(A) and (B) The diagram shows a configuration in which the insulator 105 is omitted from Figures 15(A) and (B).

[0181] Furthermore, for example, in one aspect of the present invention, a material having a metal oxide is applied as the semiconductor 151. In this case, the semiconductor 151 can be made into a three-layer structure, as shown in Figure 22. The semiconductor device shown in Figure 22 has a three-layer structure of semiconductor 151, as shown in Figure 1(A In the process of manufacturing the semiconductor device, in the step shown in Figure 11(A), semiconductor 151 is made It is constructed by sequentially forming semiconductor 152A, semiconductor 152B, and semiconductor 152C. It is possible.

[0182] Note that in Figures 23(A) and (B), the dashed lines B1-B of the semiconductor device shown in Figure 22 are shown in the respective diagrams. 2. The top view is shown along the dashed line B3-B4. The semiconductor device shown in Figure 22 is a semiconductor The body consists of three layers, with semiconductor 152A, semiconductor 152B, and semiconductor 152C deposited in that order from the outside. Since this is an example of the structural configuration, the top view shown in Figures 23(A) and (B) is the same as Figure 15(A)( The semiconductor 151 shown in B) has a three-layer structure.

[0183] The semiconductor 152A is preferably provided in contact with the insulator 104, and the semiconductor 15 It is preferable that 2C is provided so as to be in contact with insulator 105 and insulator 109a. At that time, semiconductors 152A and 152C are relatively energy-efficient compared to semiconductor 152B. It is preferable to use an oxide with a wide energy gap. Here, the wide energy gap Oxides with a wide energy gap are called wide-gap oxides, and oxides with a narrow energy gap are called narrow-gap oxides. Sometimes.

[0184] Semiconductors 152A and 152C are narrow-gap, and semiconductor 152B is wide-gap. When a cap is used, the energy at the lower end of the conduction band of semiconductor 152A and semiconductor 152C is half It is preferable that the energy is higher than the energy at the lower end of the conduction band of conductor 152B. In other words, The electron affinity of semiconductors 152A and 152C is smaller than the electron affinity of semiconductor 152B. It is preferable to do so.

[0185] Furthermore, semiconductors 152A to 152C have different combinations of atomic ratios for each metal atom. It is preferable to do so. Specifically, the metal used in semiconductor 152A and semiconductor 152C In oxides, the atomic ratio of element M in the constituent elements is the metal oxide used in semiconductor 152B. It is preferable that the atomic ratio of element M in the constituent elements is greater than that of semiconductor 1. In metal oxides used in 52A and semiconductor 152C, the atomic ratio of element M to In However, the atomic ratio of element M to In in the metal oxide used in semiconductor 152B is larger It is preferable that it is high. Also, in the metal oxide used in semiconductor 152B, with respect to element M The atomic ratio of In is such that, in the metal oxide used in semiconductor 152A and semiconductor 152C, It is preferable that the atomic ratio of In to element M is greater than that of In.

[0186] Semiconductors 152A and 152C have, for example, In:Ga:Zn=1:3:4, In Compositions with Ga:Zn=1:3:2 or In:Ga:Zn=1:1:1 and their vicinity. A metal oxide having the following composition can be used. Furthermore, for semiconductor 152B, for example, I n:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In: Using metal oxides with a composition of Ga:Zn=5:1:6 or a similar composition. Yes, it is possible. These semiconductors 152A to 152C can be arranged to satisfy the above atomic ratio relationship. It is preferable to combine semiconductors 152A and 152C. Metal oxides and semiconductors having a composition of a:Zn=1:3:4 and nearby compositions, 152B metals having a composition of In:Ga:Zn = 4:2:3 to 4.1 and nearby compositions. It is preferable to use an oxide. The above composition is the atomic ratio in the oxide formed on the substrate. Alternatively, it indicates the atomic ratio in the sputtering target.

[0187] Furthermore, it is preferable to use CAAC-OS as semiconductor 152A and semiconductor 152C. It seems so. CAAC-OS will be explained in Embodiment 4. Semiconductor 152A and When CAAC-OS is used as the semiconductor 152C, the c-axis is shown in Figure 22 as the semiconductor The orientation of the body 152A and the semiconductor 152C is perpendicular to the formation surface. preferable.

[0188] Here, at the junction of semiconductor 152A (semiconductor 152C) and semiconductor 152B, conduction The lower edge of the band changes smoothly. In other words, semiconductor 152A (semiconductor 152C) and semiconductor The lower end of the conduction band at the junction of 152B can also be described as continuously changing or continuously junctioning. This can be done. In order to do this, semiconductor 152A (semiconductor 152C) and semiconductor 152 It is desirable to lower the defect level density of the mixed layer formed at the interface with B.

[0189] Specifically, semiconductor 152A (semiconductor 152C) and semiconductor 152B share a common element other than oxygen. By having (or being the main component of) this element, it is possible to form a mixed layer with a low defect level density. Yes. For example, if semiconductor 152B is In-Ga-Zn oxide, semiconductor 152A (semiconductor As a component of 152C, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. It is recommended to use this. This will create a boundary between semiconductor 152A (semiconductor 152C) and semiconductor 152B. The defect level density on the surface can be reduced. Therefore, carrier propagation by interfacial scattering is reduced. The impact on conductivity is reduced, and the cell transistor may be able to achieve a high on-current.

[0190] Furthermore, the semiconductor device shown in Figure 22 has a structure in which the semiconductor 151 in Figure 14(B) is made up of three layers. Although it is a structure, it may also be a two-story structure or a structure with four or more stories.

[0191] Furthermore, for example, in the semiconductor device shown in Figure 14(B), the insulator 111 is made of all insulators 10 Although the configuration is located on the formation surface of 2, one aspect of the present invention has a cell transistor CTr The insulator 111 can be divided into separate charge storage layers. In Figure 24(A), After the process shown in Figure 10(A), resist mask formation and etching are performed, The insulator 111 remains only on the forming surface of the insulator 102 in the aforementioned recesses 192A and 192B. This shows the step of removing the insulator 111 contained in the opening 191. Furthermore, an insulator 1 is formed on the surface of the insulator 102 contained in recess 192A and recess 192B, respectively. 11a and insulator 111b are formed. In another step, the opening 191 is In the process of removing the insulator 111, as shown in Figure 24(B), the insulator 101A (insulator Insulator 102 included in the opening 191 is exposed so that insulator 101B (insulator 101C) is exposed. The region may also be removed. In the next step after Figure 24(A), Figures 10(B) to 14(B) By performing the same steps as described above, the semiconductor device shown in Figure 25 can be constructed. .

[0192] Figure 26 shows a top view of the semiconductor device shown in Figure 25 along the dashed line B3-B4. The semiconductor device shown in Figure 25 has an insulator 102 through which insulator 101A (insulator In the region where it overlaps with insulator 101B (101C), insulator 111 is removed. Therefore, the top view shown in Figure 26 is an insulator in the top view shown in Figure 15(B). The configuration lacks the insulator 111 between 102 and the insulator 104. By the way, in Figure 25... The top view along the dashed line B1-B2 shown may have a configuration almost identical to that of Figure 15(A). be.

[0193] Furthermore, for example, one aspect of the present invention is for improving the reliability of a cell transistor CTr. Then, the configuration of the gate electrode of the cell transistor CTr was changed from the configuration shown in Figure 14(B). It is also permissible. Figures 27(A)(B) and 28(A)(B) show one method for manufacturing the semiconductor device. An example is shown.

[0194] In the process shown in Figure 27(A), as shown in Figure 8(B), etching is used to open A portion of the conductors 132A and 132B contained in the side surface of the opening 191 is removed, Recesses 196A and 196B are formed on the side surface. These recesses may be formed deeper than the recesses 192A and 192B shown in Figure 9(A).

[0195] As a subsequent step, in Figure 27(B), the side of the opening 191 in Figure 27(A) A semiconductor film 153 is formed in the recesses 196A and 196B.

[0196] As the semiconductor 153, for example, a material containing a metal oxide as described in Embodiment 4. The following rates shall apply. However, the materials applicable to semiconductor 153 are not limited to these. For example, materials other than metal oxides can be used as semiconductor 153. For example, conductors, insulators, etc., can be used as substitutes for semiconductor 153.

[0197] For forming the semiconductor 153, it is preferable to use a film deposition method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0198] In the next step, as shown in Figure 28(A), resist mask formation and etching processes are performed. As a result, semiconductor material 153 remains in a portion of the aforementioned recesses 196A and 196B, The semiconductor 153 of the remaining portion of part 196A and recess 196B, and the side surface of the opening 191 The semiconductor 153 and semiconductor 153b are removed. As a result, semiconductor 153a and semiconductor 153b are formed It will be accomplished.

[0199] After this, by performing the same steps as in Figures 9(B) to 14(B), Figure 28 The semiconductor device shown in (B) can be constructed.

[0200] Figure 29 shows the upper surface of the semiconductor device shown in Figure 28(B) along the dashed line B1-B2. The diagram is shown. The semiconductor device shown in Figure 28(B) is compared to the semiconductor device shown in Figure 14(B). In comparison, in region 151a, the relationship between the conductor 132A (conductor 132B) and the insulator 102 Because the configuration includes semiconductor 153a (semiconductor 153b) in between, Figure 29 shows The top view shown is a structure in which a semiconductor 153b is included between the conductor 132B and the insulator 102. It is complete. By the way, the top view along the dashed line B3-B4 shown in Figure 28(B) is The configuration may be almost identical to that shown in Figure 15(B).

[0201] By contacting the insulator 102, semiconductor 153a (semiconductor 153b) is incorporated into the insulator 102. Impurities such as hydrogen and water can diffuse into semiconductor 153a (semiconductor 153b). Furthermore, by the semiconductor 153a (semiconductor 153b) coming into contact with the insulator 102, the insulator 10 Through 2, hydrogen, water, and other insulators contained in the region superimposed with insulators 111 and 104 are released. The pure substance may diffuse into semiconductor 153a (semiconductor 153b). Also, semiconductor 153a (Semiconductor 153b) comes into contact with conductor 132A (conductor 132B), and conductor 132 Impurities such as hydrogen and water contained in A (conductor 132B) are semiconductor 153a (semiconductor 153 b) It may diffuse into. In other words, semiconductor 153a (semiconductor 153b) contains hydrogen, water, etc. It may have the role of collecting various impurities. As a result, semiconductor 153a (semiconductor 1 53b) can be made to have low resistance and function as the gate electrode of the cell transistor CTr. In other words, the semiconductor device shown in Figure 28(B) has semiconductor 153a (semiconductor 153b) Therefore, in order to collect surrounding impurities such as hydrogen and water, the reliability of the cell transistor CTr It can improve.

[0202] Furthermore, for example, in one aspect of the present invention, the insulator 111 used as a charge storage layer is replaced with A conductive material may also be used. Figures 30(A) and 30(B) show an example of the manufacturing method. In Figure 30(A), in Figure 9(B), parts of recess 192A and recess 192B are respectively Conductors 138a and 138b are formed. Conductors 138a and 138 As for the method of forming b, a conductor 138a is placed in the opening 191, recess 192A, and recess 192B. Then, a conductive material to become the conductive 138b is formed, followed by resist mask formation and etching. Through processing, etc., a conductive material 138a is placed in a portion of recess 192A and recess 192B, respectively. The conductive material should be removed so that body 138b remains. After that, as shown in Figure 10(B) The process from the film formation process of insulator 104 to the film formation process of insulator 106 shown in Figure 14(B) is the same. By performing the process, the semiconductor device shown in Figure 30(B) can be constructed.

[0203] For the formation of conductors 138a and 138b, a film deposition method with high coverage is used. It is preferable to use the ALD method as a film formation method that provides high film coverage. Alternatively, methods such as CVD may be used. Another film deposition method could be, for example, When sputtering, sol-gel, electrophoresis, spray, etc. can be used. There is.

[0204] Figure 31 shows the upper surface of the semiconductor device shown in Figure 30(B) along the dashed line B1-B2. A diagram is shown. The semiconductor device shown in Figure 30(B) is superimposed on region 151a of semiconductor 151. In the region, a conductor 138a (conductor 138) is placed between the insulator 102 and the insulator 104. Since the configuration includes b), the top view shown in Figure 31 shows the insulator 102 and the insulating The configuration includes a conductor 138b between the bodies 104. By the way, Figure 30(B The top view shown in the dashed line B3-B4 may have a configuration almost identical to that of Figure 26. ru.

[0205] Examples of conductors 138a and 138b include the aforementioned conductor 132A (conductive Materials applicable to body 132B) can be used. However, conductor 138a and conductor The materials applicable to 138b are not limited to those listed above. Conductors 138a and 138b As an alternative, insulators, semiconductors, etc., can sometimes be used.

[0206] <Circuit Configuration Example 2> Next, Figure 3 shows a semiconductor device configuration that differs from the one described in Circuit Configuration Example 1. Refer to 2(A) for explanation. Figure 32(A) shows n items (where n is an integer greater than or equal to 1). A circuit diagram of a memory cell is shown. That is, the circuit shown in Figure 32(A) is a memory cell. Memory cells MC[1] through memory cells MC[n] and wiring WW for controlling them L[1] or wiring WWL[n], wiring RWL[1] or wiring RWL[n], wiring WBL, It has wiring RBL. Wiring WWL functions as a write word line, and wiring RWL is Wired WBL functions as the read word line, and wired RB functions as the write bit line. L functions as a read bit line.

[0207] Each memory cell MC consists of a transistor WTr, a transistor RTr, and a capacitive element C. It has S. The transistor RTr shown in Figure 32(A) has a back gate. It is a transistor, and by applying a potential to the back gate, the transistor RTr The threshold voltage can be varied. Note that the wiring BGL shown in Figure 32(A) is Each of the memory cells MC[1] to MC[n] has a transistor RTr It is electrically connected to the back gate. Also, the semiconductor device shown in Figure 32(A) is Line BGL is the transistor RTr of memory cell MC[1] to memory cell MC[n] It is not configured to be electrically connected to each of the back gates, but rather to the back gates The components are then electrically connected independently, and a different potential is applied to each of them. That's fine.

[0208] The channel formation region of the transistor WTr is, for example, a metal oxide region as described in Embodiment 4. It is preferable to have a substance. In particular, indium, element M (for example, element M is aluminum It contains one or more elements selected from (such as ttrium, gallium, yttrium, and tin), and zinc. In the case of metal oxides, since the metal oxide functions as a wide-bandgap semiconductor, Transistors in which the metal oxide in question is included in the channel formation region have a very low off-current. It has certain characteristics. As a transistor WTr that holds data, a transistor with these characteristics is used. By applying a generator, data can be retained in the memory cell MC for a long period of time. This reduces the number of times the retained data needs to be refreshed, thus reducing the semiconductor The power consumption of the device can be reduced.

[0209] Furthermore, the channel formation region of transistor RTr is the field-effect transfer of the transistor. It is preferable to use a material that has a high degree of intensity. By using such a transistor, Semiconductor devices can operate faster. For example, the channel shape of the transistor RTr Materials included in the compounding region include, for example, silicon and metal oxides as described in Embodiment 4. It can have semiconductor materials such as the following.

[0210] The transistor WTr functions as a write transistor, and the transistor RTr is a read transistor. It functions as a diverter transistor. It switches the on and off states of transistor WTr. This is done by the potential applied to the wiring WWL. It is controlled by the wiring RWL. The other electrode of the capacitive element CS is the gateway of the transistor RTr. It is electrically connected to the node. The other electrode of the capacitive element CS can be referred to as the memory node. This is possible. Each memory cell MC's memory node has the transients that the memory cell MC possesses. It is electrically connected to the first terminal of the staWTr.

[0211] Furthermore, the second terminal of transistor WTr is connected to the transistor WT of the adjacent memory cell MC. It is electrically connected in series with the first terminal of r. Similarly, the first terminal of transistor RTr The child is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell. And the second terminal of the transistor WTr of the memory cell MC[n] is connected to the wiring WB. The second terminal of the transistor RTr, which is electrically connected to L, is , it is electrically connected to the wiring RBL. In this embodiment, the memory cell MC[n The connection point between the second terminal of transistor RTr and wiring RBL is called node N1. The first terminal of the transistor RTr in the memory cell MC[1] is referred to as node N2. Furthermore, in order to control the conduction state between node N1 and wiring RBL, transistor RT is used. A selection transistor may be connected in series with r. Similarly, the distribution connected to node N2 To control the conduction state between the line and node N2, a transistor RTr is connected in series with the selected A selector transistor may be connected.

[0212] One aspect of the present invention is not limited to the semiconductor device shown in Figure 32(A). The embodiment can be a circuit configuration in which the semiconductor device shown in Figure 32(A) is appropriately modified. Example For example, in one aspect of the present invention, as shown in Figure 32(B), the transistor WTr also has backgear A semiconductor device with a tread pattern may also be used. Note that the semiconductor device shown in Figure 32(B) is In addition to the semiconductor device configuration shown in Figure 32(A), the memory cell MC[1] to memory A back gate is provided to the transistor WTr in the recell MC[n], and the back gate Each of the components is electrically connected to the wiring BGL. Also, for example, the present invention One embodiment is shown in Figure 32(C), where transistor RTr and transistor WTr A semiconductor device without a back gate may also be used.

[0213] By the way, if you want to further increase the memory capacity of the semiconductor device shown in Figures 32(A), (B), and (C) In total, the semiconductor devices shown in Figures 32(A), (B), and (C) are arranged in a matrix. For example, the semiconductor devices shown in Figure 32(B) can be arranged in a matrix. When arranged, the circuit configuration will be as shown in Figure 33.

[0214] The semiconductor device shown in Figure 33 is arranged in m rows, with the semiconductor device shown in Figure 32(B) forming one row (m is It is an integer greater than or equal to 1.) Arranged side by side, with wiring RWL and wiring WWL on the same row. It is electrically connected to the memory cell MC. In other words, as shown in Figure 33 The semiconductor device shown is an n x m matrix semiconductor device, and the memory cell MC[1, 1] to memory cell MC[n,m] is present. Therefore, the semiconductor device shown in Figure 33 is Wire RWL[1] or wiring RWL[n], wiring WWL[1] or wiring WWL[n], and Wire RBL[1] or wiring RBL[m], wiring WBL[1] or WBL[m], and wiring B It is electrically connected by GL[1] or wiring BGL[m]. Specifically, Memory cell MC[j,i] (where j is an integer between 1 and n, and i is an integer between 1 and m) One electrode of the capacitive element CS is electrically connected to the wiring RWL[j], and the memory The gate of transistor WTr in cell MC[j,i] is electrically connected to wiring WWL[j]. The wiring WBL[i] is the first of the transistors WTr of the memory cell MC[n,i]. Electrically connected to terminal 2, wiring RBL[i] is the transient of memory cell MC[n,i] It is electrically connected to the second terminal of the STR.

[0215] Figure 33 shows memory cell MC[1,1], memory cell MC[1,i], and memory cell. MC[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell M C[j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC [n,m], Wiring RWL[1], Wiring RWL[j], Wiring RWL[n], Wiring WWL[1 ], Wiring WWL[j], Wiring WWL[n], Wiring RBL[1], Wiring RBL[i], Wiring RBL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[ 1], wiring BGL[i], wiring BGL[m], capacitive element CS, transistor WTr, tra Only the transistor RTr, node N1, and node N2 are shown in the diagram; other wiring, components, and markings are not shown. The numbers and symbols have been omitted.

[0216] Furthermore, the semiconductor devices shown in Figure 32(C) are arranged in m columns (where m is an integer greater than or equal to 1). Figure 34 shows the arrangement of the devices. Note that the semiconductor device shown in Figure 34 is a memo. The Ricell MC has a configuration in which each transistor does not have a back gate. Therefore, the semiconductor device shown in Figure 34 does not have wiring BGL. For the semiconductor devices shown, please refer to the description of the semiconductor device shown in Figure 33.

[0217] <Example of operation method 2> Next, an example of the operation method of the semiconductor device shown in Figures 32(A) to (C) will be described. Note that the terms "low-level potential" and "high-level potential" used in the following explanation refer to specific potentials. It's not just the object itself, but the wiring can also result in different specific potentials. For example, the wiring WWL The low-level potential and high-level potential applied to the wiring RWL are each the low-level potential applied to the wiring RWL. The potential may be different from the high-level potential.

[0218] Furthermore, in this example of operation method, the wiring BGL shown in Figures 32(A) and 32(B) has a transient The potentials applied beforehand are within the range in which the stRTr and transistor WTr operate normally. It is assumed that there are. Therefore, the operation of the semiconductor devices shown in Figures 32(A) to (C) is as follows: They can think about each other in the same way.

[0219] Figure 35(A) is a timing chart showing an example of the operation of writing data to a semiconductor device. Yes, Figure 35(B) shows an example of the operation of reading data from a semiconductor device using a timing channel. The timing charts in Figures 35(A) and 35(B) are based on the wiring WWL[1]. Wiring WWL[2], Wiring WWL[n], Wiring RWL[1], Wiring RWL[2], Wiring R This shows the change in the magnitude of the potentials at WL[n], node N1, and node N2. The line WBL indicates the data supplied to the wiring WBL.

[0220] Figure 35(A) shows that each of the data D[1] to data D[n] is stored in the memory cell MC[1 This shows an example of writing to memory cell MC[n]. Note that data D[1] to data Data D[n] can be binary, multi-level, analog, etc. Then, data D[1 Data D[n] is to be supplied from the wiring WBL. That is, Figure 32(A) In the semiconductor device circuit configuration shown in (C) to (F), data writing is performed by the memory cell MC [1] is performed sequentially on the memory cell MC[n].

[0221] Conversely, after writing data to memory cell MC[2], When attempting to write data, the system first reads the data already written to memory cell MC[2]. If you don't take it out and save it elsewhere, the data held in the memory cell MC[2] will be lost. The data is lost during the process of writing it to the Ricell MC[1].

[0222] In the circuit configuration of the semiconductor device shown in Figures 32(A) to (C), the memory cell MC[i] When writing data to a memory cell MC (where i is an integer between 2 and n, inclusive), [1] In order to prevent overwriting of data held in memory cell MC[i-1], By supplying a low-level potential to wiring WWL[1] or wiring WWL[i-1], the memory cell MC [1] Turn off each transistor WTr in memory cell MC[i-1] This is done so that the memory cells MC[1] to MC[i-1] are held Each piece of data can be protected.

[0223] Furthermore, when writing data to memory cell MC[i], the data is supplied from the wiring WBL. Therefore, a high-level potential is supplied to the wiring WWL[i] to the wiring WWL[n], and the memory Each transistor WTr in memory cell MC[i] to memory cell MC[n] is sufficient Turn it on. This will hold the data in the memory node of memory cell MC[i]. It is possible.

[0224] Furthermore, when writing data to the circuit configuration of the semiconductor device shown in Figures 32(A) to (C), Since the RBL wiring can be controlled independently of other wiring, it does not need to be at a specific potential, but for example... Therefore, the potential can be set to a low level. That is, the potential of node N1 is a low level potential. This is possible. In addition, the potential of node N2 can also be set to a low-level potential.

[0225] Based on the above, the example operation shown in the timing chart of Figure 35(A) will be explained. At time T10, wiring WWL[1] to wiring WWL[n], wiring RWL[1] The potentials of the wiring RWL[n], wiring WBL, node N1, and node N2 are low. It is at a level potential.

[0226] At time T11, a high-level potential is applied to wiring WWL[1] to wiring WWL[n]. It will start. This will cause the memory cell MC to start between time T11 and time T12. [1] Each transistor WTr in the memory cell MC[n] is in a sufficiently ON state This is the state. Then, data D[1] is supplied to the wiring WBL. Memory cell MC[1 Each transistor WTr in the memory cell MC[n] is in a sufficiently ON state Therefore, data D[1] reaches the memory node of memory cell MC[1] It will be written.

[0227] At time T12, the application of a low-level potential to wiring WWL[1] was initiated, and wiring WWL [2] or wiring WWL[n] continues to have a high potential applied. Furthermore, between time T12 and time T13, the transistors of the memory cell MC[1] The ZISTA WTr is turned off, and memory cells MC[2] to MC[n] have Each transistor WTr is sufficiently turned ON. Then, the wiring WBL is A -D[2] is supplied. The memory cell MC[2] to the memory cell MC[n] have Since each transistor WTr is sufficiently ON, data D[2] is The data reaches the memory node of the Morisel MC[2] and is written to it. [1] The transistor WTr is in the off state and therefore retained in the memory cell MC[1] The data D[1] is obtained by the write operation from time T12 to time T13. It will not be lost.

[0228] Between time T13 and time T14, the memory between time T11 and time T12 The operation of writing data D[1] to cell MC[1] and the time from T12 to T13 The operation of writing data D[2] to the memory cell MC[2] in between, and similarly to each of the following, Data D[3] is sequentially stored in each of the memory cells MC[3] through MC[n-1]. Data D[n-1] is written to it. Specifically, data has already been written to the memory space. MC[1] or memory cell MC[j-1] (where j is an integer between 3 and n-1) The transistor WTr of ( ) is turned off, and the memory does not have data written to it. The transistor WTr in cell MC[j] or memory cell MC[n] is brought to a sufficiently ON state. Then, data D[j] is supplied from the wiring WBL to the memory node of memory cell MC[j]. You just need to write it there. Then, the writing of data D[j] to memory cell MC[j] is complete. In this case, the transistor WTr of the memory cell MC[j] is turned off, and the wiring W Data D[j+1] is supplied from BL and written to the memory node of memory cell MC[j+1]. You just need to perform a write operation. In particular, the write operation when j is n-1 is as follows: This refers to the operation from time T14 to time T15.

[0229] At time T14, a low-level potential is imprinted on wiring WWL[1] to wiring WWL[n-1]. As a result, a high-level potential is continuously applied to the wiring WWL[n]. Between time T14 and time T15, memory cell MC[1] to memory cell M The transistor WTr in C[n-1] is turned off, and the memory cell MC[n] is The transistor WTr is then sufficiently turned ON. And the wiring WBL has data D[ n] is supplied. The transistor WTr in the memory cell MC[n] is in a sufficiently ON state. Therefore, the data D[n] reaches the memory node of the memory cell MC[n]. It is written in the transistors of memory cell MC[1] to memory cell MC[n-1]. Since the ZISTA WTr is in the off state, memory cell MC[1] to memory cell MC[ The data D[1] to data D[n-1] held in each of n-1 at this time The data will not be lost due to write operations between time T14 and time T15.

[0230] As a result of the above operation, in any one of the semiconductor devices shown in Figures 32(A) to (C) It is possible to write data to the memory cell MC of the semiconductor device.

[0231] Figure 35(B) shows that each of the data D[1] to data D[n] is stored in the memory cell MC[1 This shows an example of a timing chart for reading from ] or memory cell MC[n]. At this time, in order to maintain the data held in each memory cell MC, the transistor WTr It is required that the memory cell MC[1] or memory cell When reading data from MC[n], wiring WWL[1] to wiring WWL[n] The potential of ] is assumed to be a low-level potential.

[0232] In the semiconductor device circuit configuration shown in Figure 32, data from a specific memory cell MC is read out. In this case, after ensuring that the transistor RTr of the other memory cell MC is sufficiently turned ON, The transistor RTr of the specific memory cell MC is operated in the saturation region. Furthermore, the flow between the source and drain of the transistor RTr in the specific memory cell MC The current is determined by the source-drain voltage and the current held in the particular memory cell MC. It is determined according to the data.

[0233] For example, the memory cell MC[k] (where k is an integer between 1 and n) holds Let's consider the case of reading stored data. In this case, the memory cell MC[k] is excluded. Each transistor RTr in the recell MC[1] or memory cell MC[n] is 10 To turn it on, remove wiring RWL[k] and wires RWL[1] to RWL[ A high-level potential is supplied to [n].

[0234] On the other hand, the transistor RTr in the memory cell MC[k] is used to store the data. To enable the corresponding ON state, wiring RWL[k] transmits the data to memory cell MC[k]. The potential must be the same as the wiring RWL[k] when writing. During loading and reading operations, the potential of the wiring RWL[k] is considered as the low-level potential. El.

[0235] For example, apply a potential of +3V to node N1 and 0V to node N2. Floating the current, the potential of node N2 is measured. Excluding the wiring RWL[k] When the potential of the wiring RWL[1] to wiring RWL[n] is set to a high-level potential, memory The transients of memory cells MC[1] to MC[n], excluding MC[k] The transistor RTr is in a sufficiently ON state. Meanwhile, the transistor of the memory cell MC[k] The voltage between the first and second terminals of the RTr is equal to the potential of the gate of the transistor RTr. Since it is determined by the potential of node N1, the potential of node N2 is determined by the memory node of memory cell MC[k] It is determined by the data stored in the code.

[0236] In this way, the data held in the memory cell MC[k] can be read. ru.

[0237] Based on the above, the example operation shown in the timing chart of Figure 35(B) will be explained. At time T20, wiring WWL[1] to wiring WWL[n], wiring RWL[1] The potentials of the wiring RWL[n], wiring WBL, node N1, and node N2 are low. The level potential is such that node N2 is in a floating state. Then, each memory node of memory cell MC[1] to memory cell MC[n] contains data Assume that data D[1] through data D[n] are stored.

[0238] Between time T21 and time T22, a low-level potential was applied to the wiring RWL[1]. The process is initiated, and a high-level potential is applied to wiring RWL[2] through wiring RWL[n]. As a result, between time T21 and time T22, memory cell MC[2] Each transistor RTr in the memory cell MC[n] becomes sufficiently ON. Then, the transistor RTr of the memory cell MC[1] is the memory of the memory cell MC[1] The node will be turned ON according to the data D[1] held in the node. Also, the wiring RBL will be powered Place V R This supplies V. As a result, the potential at node N1 is V R Therefore, the potential at node N2 is, Potential V at node N1 R and the data held in the memory node of the memory cell MC[1] It is determined by V. Here, the potential of node N2 is V D[1] And then, node N2 Potential V D[1] By measuring the memory node of the memory cell MC[1], The data D[1] can be read.

[0239] Between time T22 and time T23, wiring RWL[1] to wiring RWL[n] The application of a low-level potential is initiated. Also, a low-level potential is supplied to node N2. Subsequently, node N2 enters a floating state. That is, from time T22 to time T23 Between these points, the potentials of wiring RWL[1] to wiring RWL[n] and node N2 are as follows: This will be the same as the situation between time T20 and time T21. Note that wiring RBL has Continued, potential V R It may be supplied, or a low-level potential may be supplied. In this example of operation The wiring RBL has a potential of V from time T21 onwards. R It is assumed that the supply will continue.

[0240] Between time T23 and time T24, a low-level potential was applied to the wiring RWL[2]. Then, a high-level potential is applied to the wiring RWL[1], wiring RWL[3] to wiring RWL[n]. This is initiated. As a result, between time T23 and time T24, memory cell M C[1], each of the transients present in memory cell MC[3] to memory cell MC[n] The transistor RTr is fully turned on. Then, the transistor RT of the memory cell MC[2] r is an O that corresponds to the data D[2] held in the memory node of the memory cell MC[2] This results in a state of [unclear]. Also, the wiring RBL has a potential of VR It continues to be supplied. As a result, The potential at node N2 is equal to the potential V at node N1. R and stored in the memory node of the memory cell MC[2] It is determined according to the data held. Here, the potential of node N2 is V D[2] Let's assume that. And the potential V of node N2 D[2] By measuring the memory cell MC[2] The data D[2] held in the memory node can be read.

[0241] Between time T24 and time T25, the memory between time T20 and time T22 The operation of reading data D[1] from cell MC[1] and from time T22 to time T24. The read operation of data D[2] from memory cell MC[2] between and respectively is similar to the read operation of each of the following. Then, data D[ from each of the memory cells MC[3] to MC[n-1] is sequentially extracted. 3) or data D[n-1] is read out. Specifically, memory cell MC[j] (here Let j be an integer between 3 and n-1 (inclusive). When reading data D[j] from the node After setting the potential of N2 to a low level potential and making node N2 floating, A high-level potential is supplied to wiring RWL[1] through wiring RWL[n], excluding line RWL[j]. Therefore, the memory cells MC[1] to MC[n] remain after removing memory cell MC[j]. The transistor RTr is brought to a sufficiently ON state, and the transistors that the memory cell MC[j] possess Turn on the stRTr according to the data D[j]. Next, set the potential of node N1 to V R to By doing so, the potential of node N2 becomes the potential corresponding to data D[j], and this potential is measured. By doing so, data D[j] can be read. Note that the memory cell MC[j] is stored After the reading of the data D[j] has finished, in preparation for the next reading operation, Start applying a low-level potential to line RWL[1] or wiring RWL[n], and then the power of node N2 The position is set to a low-level potential, and then node N2 is put into a floating state. In particular, when j is n When the value is -1, this preparation refers to the operation between time T25 and time T26.

[0242] Between time T25 and time T26, wiring RWL[1] to wiring RWL[n] The application of a low-level potential is initiated. Also, the application of a low-level potential is initiated at node N2. After the potential of node N2 becomes low, node N2 enters a floating state. That is, between time T25 and time T26, wiring RWL[1] to wiring RW The potentials of L[n] and node N2 are determined by the conditions between time T20 and time T21. It will be the same. Furthermore, the potential V will continue to be applied to the RBL wiring. R They may supply low-grade A bell potential may be applied. In this example, at time T21, a potential V is applied to the wiring RBL. R Application The process has started, and from time T22 onwards, the potential V is applied to the wiring RBL. R The applied force will continue to be applied. ru.

[0243] At time T26, a low-level potential is applied to wiring RWL[n], and wiring RWL[1] Alternatively, a high-level potential is supplied to wiring RWL[n-1]. As a result, at time T26 or Between time T27 and time T27, memory cell MC[1] to memory cell MC[n-1] Each transistor RTr is sufficiently turned ON. Then, the memory cell MC The transistor RTr of [n] is held in the memory node of the memory cell MC[n]. The ON state is determined according to data D[n]. Also, the potential V is present in the wiring RBL. R continued supply This is done. As a result, the potential of node N2 is the same as the potential of node N1, V R and memory cell MC It is determined by the data held in the memory node [n]. Here, the power of node N2 V D[n] Let's assume that the potential V of node N2 is... D[n] By measuring It is possible to read the data D[n] held in the memory node of the memory cell MC[n]. Cut.

[0244] The above operation enables each of the memory cells of the semiconductor device shown in Figures 32(A) to (C). Data can be read from the MC.

[0245] <Example of structure and example of manufacturing method 2> The following is an explanation of the structure of the semiconductor device having the circuit configurations shown in Figures 32 to 34 described above. To help, I will explain how to make it.

[0246] Figures 36(A), (B), and (C) are examples of schematic diagrams showing the semiconductor device shown in Figure 33 or Figure 34. Yes. Figure 36(A) shows a perspective view of the semiconductor device, and Figure 36(B) shows Figure 36( Figure 36(C) shows a top view of A). Furthermore, Figure 36(C) shows the dashed line A1-A2 in Figure 36(B). A corresponding cross-sectional view is shown.

[0247] The semiconductor device consists of wiring RWL, wiring WWL, and an insulator (hatched in Figure 36). It has a structure in which layers (areas not shown) are stacked.

[0248] In addition, the insulator, the RWL wiring, and the WWL wiring all pass through the structure together. An opening is formed such that the wiring RWL and wiring WWL pass through the area. In order to provide a memory cell MC in region AR, an insulator, a conductor, and a semiconductor are placed in the opening. A conductor is formed. The conductor is the transistor WTr of the memory cell MC, and / Alternatively, it functions as the source electrode or drain electrode of the transistor RTr, and the semiconductor is Functions as the channel formation region of transistor WTr and / or transistor RTr. Furthermore, without forming the conductor, the channel formation region and the low-resistance region in the semiconductor are Forms the low-resistance region of transistor WTr and / or transistor RTr. It may be applied as a drain electrode or a drain electrode. In Figures 36(A), (B), and (C), the opening The region where an insulator, a conductor, and a semiconductor are formed at the opening is shown as region HL. In particular, in Figure 36(A), the region HL contained within the structure is shown with a dashed line. In addition, if a back gate is provided for the transistors in the memory cell MC, In addition, the conductive material in area HL is connected to the back gate by wiring B. It can also function as a GL (Ground Level).

[0249] In other words, in Figure 36, the semiconductor device shown is one of the semiconductor devices shown in Figure 32(A),(B), or(C). The semiconductor device shown in Figure 33 or Figure 34 is configured in region SD1, and the semiconductor device shown in Figure 33 or Figure 34 is configured in region SD2. This indicates that it is being done.

[0250] By the way, the area TM where wiring RWL and wiring WWL are exposed is where wiring RWL and wiring WWL It functions as a connection terminal for applying potential to each of L. In other words, wiring to region TM By electrically connecting transistors WTr and RTr, It is possible to apply an electric potential to the gate.

[0251] The shape of region TM is not limited to the configuration example shown in Figure 36. The configuration of the conductor device is such that, for example, an insulator is formed on the region TM shown in Figure 36, and the insulator An opening may be provided, and a conductive material PG may be formed to fill the opening. (Figure 37(A)(B)(C)). Note that wiring ER is formed on the conductive material PG. This electrically connects wiring ER to wiring RWL or wiring WWL. Oh, in Figure 37(A), the conductive material PG contained inside the structure is shown with a dashed line. The dashed line in region HL has been omitted.

[0252] In the following example of a fabrication method 2, the memory cell MC shown in Figures 32 to 34 is formed in region AR. I will explain the methods for achieving this.

[0253] <<Example of manufacturing method 2>> Figures 38 to 43 are cross-sectional views illustrating an example of the fabrication of the semiconductor device shown in Figure 32(A). In particular, the cross-sectional view of transistors WTr and RTr in the channel length direction is This is shown. Also, in the cross-sectional views of Figures 38 to 43, some elements have been omitted for clarity. It is illustrated in the diagram.

[0254] As shown in Figure 38(A), the semiconductor device in Figure 32(A) is located on a substrate (not shown). An insulator 201A is arranged on one side, and a conductor 231 is arranged on the insulator 201A, and An insulator 201B placed on the body 231, and a conductor 232 placed on the insulator 201B It has an insulator 201C placed on the conductor 232. Furthermore, the combination of these will be described below. Laminate having several conductors and multiple insulators (depending on subsequent processes, other insulators may be used) This includes materials such as bodies and conductors.) is referred to as laminate 200.

[0255] For example, the substrate described in Manufacturing Method Example 1 can be used for this substrate. Cut.

[0256] Conductor 231 functions as the wiring WWL shown in Figure 32(A), and conductor 232 functions as shown in Figure 3 The wiring shown in 2(A) functions as RWL.

[0257] Examples of conductors 231 and 232 include conductor 132 as described in manufacturing method example 1. A, a material applicable to conductor 132B can be used. In addition, conductor 231, Each of the electrical components 232 may be a laminated structure formed by combining multiple of the material. As for the method of forming the electrolytic body 231 and the conductor 232, the conductor 132A described in Manufacturing Method Example 1 is used. The method for forming the conductor 132B can be used.

[0258] Examples of insulators 201A to 201C include the insulators described in Manufacturing Method Example 1. Materials applicable to 101A to insulator 101C can be used. In addition, insulator 2 Each of 01A to insulator 201C can also be used in a laminated structure by combining multiple of the said materials. Good. Furthermore, the method for forming insulators 201A to 201C is described in Manufacturing Method Example 1. The methods for forming insulators 101A to 101C described above can be used.

[0259] In the next step, as shown in Figure 38(B), for example, resist mask formation and etching are performed. Through processing, etc., an opening 291 is formed in the laminate 200 shown in Figure 38(A). ru.

[0260] Regarding the formation and etching of the resist mask performed in the manufacturing process shown in Figure 38(B): Refer to the description in Manufacturing Method Example 1. Also, the resist mass that is produced in the subsequent steps. Similarly, the formation of the cue and the etching process should be described in the same manner as in Manufacturing Method Example 1. do.

[0261] Then, as shown in Figure 39(A), etching treatment is used to remove the side of the opening 291. A portion of the conductor 231 located on the surface is removed, and a recess 292 is formed on the side surface. Here, the conductor 231 is selected from the laminate 200 in which the conductor 231 is selectively removed. Materials that can be etched (insulators 201A to 201C, conductors 232 are more etchable) It is assumed that high-quality materials are being used.

[0262] In the next step, as shown in Figure 39(B), the side of the opening 291 shown in Figure 39(A) An insulator 202 is formed in the recess 292.

[0263] The insulator 202 is an insulating film sandwiched between a pair of electrodes of the capacitive element CS, and transistor WT. It functions as a gate insulator for r.

[0264] For example, silicon oxide or silicon oxide-nitride can be used as the insulator 202. It can be done. Also, as the insulator 202, for example, aluminum oxide, hafnium oxide, and This can be an oxide containing aluminum and hafnium, etc. Body 202 may be an insulator formed by laminating these materials.

[0265] For forming the insulator 202, it is preferable to use a film formation method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD methods (LPCVD, PCVD, etc.) may also be used. Alternatively, other film deposition methods may be used. For example, sputtering may be used in some cases.

[0266] In the next step, as shown in Figure 40(A), the side of the opening 291 shown in Figure 39(B) And a semiconductor 251 is formed in the recessed area. In other words, the surface on which the insulator 202 is formed. A semiconductor 251 is formed thereon.

[0267] As the semiconductor 251, for example, a material containing a metal oxide as described in Embodiment 4. The fee can be applied. Alternatively, the semiconductor 251 may include, for example, silicon. The materials available can be applied.

[0268] As for the method of forming semiconductor 251, the method of forming semiconductor 151 described in Fabrication Method Example 1 is Please take the information into consideration.

[0269] In the next step, as shown in Figure 40(B), the side of the opening 291 shown in Figure 40(A) And an insulator 203 is formed in the recessed area. In other words, the formation surface of the semiconductor 251 An insulator 203 is formed thereon.

[0270] The components contained in the insulator 203 include the interface with the previously formed semiconductor 251, and the interface In the vicinity, it is preferable that the components are not compounds with components contained in semiconductor 251. Alternatively, even if the compound is formed, it is preferable that the compound be an insulator. It is not possible. Or, even if such a compound is formed, such a compound is not possible in semiconductor 251. Therefore, it is preferable that the compound does not contribute as a carrier.

[0271] For example, silicon oxide can be used as the insulator 203.

[0272] The method for forming the insulator 203 shall be based on the description of the method for forming the insulator 202.

[0273] In the next step, as shown in Figure 41(A), resist mask formation, etching, etc. As a result, the insulating material included in the opening 291 is such that the insulating material 203 remains only in the aforementioned recess. A portion of body 203 is removed. This forms the insulator 203a. In this case, if the insulator 202 is not exposed to the opening 291, a portion of the semiconductor 251 is removed It's okay if they're gone.

[0274] By the way, when a material having a metal oxide is applied as semiconductor 251, the formed The side surface of the opening 291 may be treated by supplying impurities such as hydrogen. In this case, the process for supplying impurities such as hydrogen is shown in Figure 41(B). Process 20 is considered as a process for supplying impurities such as hydrogen. The supply process in Figure 41(B) Procedure 20 is performed on the insulator 203a and the semiconductor region 251b of 251. For the process of supplying impurities such as elements, please refer to the explanation of supply process 11 shown in Figure 13. In Figure 41(B), the components contained in semiconductor 251 and the components supplied by supply processing 20 are shown. Compound 261A (Compound 261B) is listed as a compound containing the impurities that were found. This process makes it possible to reduce the resistance of region 251b of semiconductor 251. The supply process 20 described here may not always be necessary.

[0275] Furthermore, when a material containing silicon is applied as semiconductor 251, The side surface of the opening 291 may be treated to supply impurities. In this case, Regarding the process of supplying impurities, the supply process 20 shown in Figure 41(B) is used to supply impurities. This is considered as a process. In Figure 41(B), the impurity supply process 20 is performed in region 2 of the semiconductor 251. This shows the process performed on 51b and the insulator 203a. Note that the supply process 20 During this process, it is preferable to perform heat treatment on the semiconductor device. For example, n-type impurities (donors) such as phosphorus and arsenic can be used. For example, impurities include p-type impurities such as boron, aluminum, and gallium (acceptors). ) can be used. By performing this process, region 251b of semiconductor 251 can be used Then, an impurity region 262A (impurity region 262B) is located on the surface of semiconductor 251 and near the surface. This allows for the formation of a structure that reduces the resistance of region 251b of the semiconductor 251. The supply process 20 described here is not necessarily required.

[0276] Furthermore, the semiconductor 251 may be a material having either a metal oxide or silicon. When used, the region 251a on the formation surface of the semiconductor 251 is formed in the region 251a where the insulator 203a is formed. Therefore, since the insulator 203a acts as a mask to shield against impurities, semiconductor 251 No impurities are supplied to region 251a.

[0277] In the next step, as shown in Figure 42(A), the side surface of the opening 291 shown in Figure 41(B) Then, an insulator 204 is formed.

[0278] The insulator 204 has a function of suppressing the permeation of impurities such as water and hydrogen. It is preferable to use an insulating material. For example, as the insulator 204, aluminum oxide Materials such as M can be used. However, the materials that can be applied to the insulator 204 are not limited to those mentioned above. As the insulator 204, for example, a film in which the concentration of impurities such as water and hydrogen has been reduced, Use a material that is applicable to insulators 101A to 101C as described in Manufacturing Method Example 1. It is possible.

[0279] The method for forming the insulator 204 shall be based on the description of the method for forming the insulator 202.

[0280] In the next step, as shown in Figure 42(B), the side surface of the opening 291 shown in Figure 42(A) Then, the semiconductor 252 is formed. In other words, the semiconductor 252 is formed on the formation surface of the insulator 204. ru.

[0281] For semiconductor 252, for example, a material containing silicon can be used. As the semiconductor 252, a semiconductor material such as a metal oxide, as described in Embodiment 4, is used. It is possible.

[0282] The method for forming semiconductor 252 shall be based on the description of the method for forming semiconductor 251.

[0283] In the next step, as shown in Figure 43, an insulator 205 is formed on the formation surface of the semiconductor 252. Then, a conductive film 233 is formed so that the remaining opening 291 is filled.

[0284] As the insulator 205, for example, a material applicable to the insulator 202 described above can be used. This is possible. Furthermore, the insulator 205 may have a laminated structure consisting of multiple insulators.

[0285] The method for forming the insulator 205 shall be based on the description of the method for forming the insulator 202.

[0286] As for the conductor 233, for example, a material applicable to the conductors 231 and 232 described above. Materials can be used. In addition, the conductor 233 has a laminated structure consisting of multiple conductors. That is also acceptable.

[0287] For forming the conductive material 233, it is preferable to use a film formation method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0288] By the way, in region 281 shown in Figure 43, the transistor WTr shown in Figure 32(A) This is configured. Specifically, in region 281, the conductor 231 is a transistor WT The semiconductor 251 that functions as the gate electrode of r and is contained in each of the two regions 251b It functions as the source and drain electrodes of transistor WTr and is located in region 251a. Semiconductor 251 functions as the channel formation region of transistor WTr. In particular, semiconductor 2 When a material containing metal oxides is applied as 51, the transistor WTr is OS transistor This constitutes the ZISTA.

[0289] Furthermore, in region 282 shown in Figure 43, the capacitive element CS shown in Figure 32(A) is configured. Specifically, in region 282, the conductor 232 is one electrode of the capacitive element CS. The semiconductor 251, which functions as part of region 251b, is the other electric component of the capacitive element CS. It functions as a pole.

[0290] Furthermore, in region 283 shown in Figure 43, the transistor RTr shown in Figure 32(A) is configured This has been done. Specifically, in region 283, semiconductor 251 included in region 251b A portion of it functions as the gate electrode of transistor RTr, and semiconductor 252 is transistor R It functions as the channel-forming region of Tr, and conductor 233 is the backgear of transistor RTr. It functions as an electrode. In particular, a material containing a metal oxide is used as semiconductor 252. In this case, transistor RTr constitutes an OS transistor.

[0291] By performing the steps from Figure 38(A) to Figure 43, the semiconductor equipment shown in Figure 32(A) is obtained. A structure can be created.

[0292] Figures 44(A), (B), and (C) show the dashed lines C1-C of the semiconductor device shown in Figure 43, respectively. 2. The top view is shown along the dashed lines C3-C4 and C5-C6.

[0293] One aspect of the present invention is not limited to the semiconductor device configuration example shown in Figure 43. The configuration can be achieved by appropriately modifying the semiconductor device shown in Figure 43.

[0294] For example, one aspect of the present invention, as described above, is a transistor as shown in Figure 32(C). It is also possible to design a semiconductor device in which the WTr (Wing Transistor) does not have a back gate. Yes, it is possible. When fabricating the semiconductor device shown in Figure 32(C), the semiconductor device shown in Figure 32(A) can be fabricated. During the manufacturing process, after the step shown in Figure 42(B), insulation is applied so that the opening 291 is filled. The film should then be formed using body 205 (see Figure 45(A)).

[0295] Furthermore, multiple layers of the insulator 205 may be used. For example, as shown in Figure 45(B) For the insulator 205A that is in contact with the semiconductor 252, silicon oxide is used, and the insulator 205A is in contact with The insulator 205B uses aluminum oxide or hafnium oxide, etc. Multiple insulating materials can be combined.

[0296] The method for forming insulators 205A and 205B is described as the method for forming insulator 202. We will take that into consideration.

[0297] Note that Figures 46(A), (B), and (C) each show a point of the semiconductor device shown in Figure 45(A). The images show the top views along the dashed lines C1-C2, dotted-dash lines C3-C4, and dotted-dash lines C5-C6. The semiconductor device shown in Figure 45(A) is provided with a conductor 233, compared to the semiconductor device in Figure 43. Since this is an example of a configuration that has not been shown, the top view shown in Figure 46(A)(B)(C) is different from Figure 44( Compared to A)(B)(C), this configuration does not have a conductor 233 inside the insulator 205. It is.

[0298] Furthermore, for example, the semiconductor device according to one embodiment of the present invention may have some of its manufacturing processes modified. Figures 47(A) and 47(B) show a region 251 of semiconductor 251 that is different from that in Figure 41(B). This shows the process of forming a low-resistance region relative to b.

[0299] The process shown in Figure 47(A) is performed after the process shown in Figure 41(A) on the side surface of the opening 291. In contrast, the process of forming the conductor 239 is shown. That is, insulator 203a, semiconductor 2 Conductor 239 is formed on the formation surface of region 251b of 51. At this time, Figure 19(A), ( Similar to step B), the conductor 239 comes into contact with the semiconductor 251, thereby bringing the semiconductor 251 into contact with the semiconductor 251. In region 251b, compound 261A (compound 261B), or impurity region 262A An impurity region (262B) is formed. In other words, region 251b of semiconductor 251 becomes less resistive. This will be done. Regarding the reduction of resistance, please refer to the explanations in Figures 19(A) and (B).

[0300] As for the conductor 239, depending on the material of the semiconductor 251, as shown in Figures 19(A) and (B) Materials applicable to the conductor 139 described can be used.

[0301] By the above-described fabrication method, region 251b of semiconductor 251 is formed as a low-resistance region. This allows the region 251a of the semiconductor 251 to be formed as a channel formation region. Furthermore, region 251b, which is a low-resistance region, is the first terminal of transistor WTr, and / or it corresponds to the second terminal (gate of transistor RTr), therefore, by the manufacturing method described above This allows for lowering the electrical resistance between transistors WTr that are electrically connected in series.

[0302] For forming the conductive material 239, it is preferable to use a film deposition method that provides high coverage. For a highly efficient film deposition method, for example, the ALD method is preferred. Also, for example, C VD method may also be used. Alternatively, other film deposition methods include, for example, sputtering. Sol-gel method, electrophoresis method, spray method, etc. may be used in some cases.

[0303] In the next step, as shown in Figure 47(B), etching is used to remove the opening 291. The conductive material 239 located on the side is removed. At this time, region 251a overlaps The interface with the laminated insulator 203a, and a portion of the area near said interface, may be removed.

[0304] From here on, by performing the steps from Figure 42(A) to Figure 43, the result will be different from Figure 41(B). In a manufacturing process, a low-resistance region is formed in the semiconductor region 251b of semiconductor 251. It is possible to produce this.

[0305] Furthermore, we will explain another method for fabricating the low-resistance region, which differs from those shown in Figures 47(A) and (B). Figure 48(A) shows the process after the steps shown in Figure 41(A), with an insulating film applied to the side surface of the opening 291. This shows the process of forming the edge body 207.

[0306] If the semiconductor 251 is a material containing a metal oxide, the insulator 207 may be, for example, nitrogen It is preferable that silicon dioxide is included. The semiconductor 251 is in contact with the insulator 207. In the field where nitrogen, nitrides, and other components contained in the insulator 207 diffuse into the semiconductor 251 There is a possibility of heat treatment being performed on the laminate 200 at this time. Good. As a result, in Figure 48(A), the semiconductor 251 has an interface with the insulator 207, and And near the interface, nitrogen, nitrides, and other components diffused from the insulator 207 In some cases, compound 261A (compound 261B) may be formed. This results in the formation of a semiconductor. Region 251b of 251 is made low resistance. In other words, the source electrode of transistor WTr or In some cases, it is possible to reduce the resistance of one of the drain electrodes.

[0307] If the semiconductor 251 is a silicon-containing material, the insulator 207 may be, for example, a semiconductor It is preferable that the body 251 contains impurities (elements or ions) for diffusion. When using an n-type impurity (donor) as the impurity in question, for example, the n-type impurity may be: Phosphorus, arsenic, etc. can be used as impurities. In addition, p-type impurities (acceptors) can be used as such impurities. When using ), p-type impurities include, for example, boron, aluminum, gallium, etc. It can be used.

[0308] When semiconductor 251 comes into contact with insulator 207, impurities (elements, In some cases, ions may diffuse into the semiconductor 251. Also, at this time, the laminate 200 Heat treatment may or may not be performed. In other words, the semiconductor 251 and the insulator 207 Impurity regions may form at the interface in contact with the semiconductor and in the vicinity of the interface. This can cause semiconductors to be affected. A carrier is formed in region 251b of body 251, or near the interface of semiconductor 251 with insulator 207. As a result, region 251b may have reduced resistance.

[0309] The method for forming the insulator 207 shall be based on the description of the method for forming the insulator 202.

[0310] In the next step, an insulator 208 is deposited on the side surface of the opening 291, and then, from Figure 42(B) By performing the same steps as shown in Figure 43, the semiconductor device shown in Figure 48(B) can be constructed. can.

[0311] If semiconductor 252 has a metal oxide, the insulator 208 is, for example, included in insulator 207. An insulating material to prevent nitrogen, nitrides, and other components from diffusing into semiconductor 252. This is possible. In this case, the insulator 208 can be, for example, silicon oxide, aluminum oxide. Aluminum can be used. Furthermore, if semiconductor 252 contains silicon, insulation... Body 208 may or may not be formed.

[0312] The method for forming the insulator 208 should be considered in relation to the description of the method for forming the insulator 202.

[0313] Note that Figures 49(A), (B), and (C) each show a point of the semiconductor device shown in Figure 48(B). The images show the top views along the dashed lines C1-C2, dotted-dash lines C3-C4, and dotted-dash lines C5-C6. The semiconductor device shown in Figure 48(B) has an insulator 207 between semiconductor 251 and semiconductor 252. , and the configuration having an insulator 208, as shown in Figure 49(A)(B)(C) The view shows insulator 204 in Figures 44(A), (B), and (C), as well as insulator 207 and insulator 208. It has a layered structure.

[0314] Furthermore, for example, in one aspect of the present invention, a material having a metal oxide is applied as the semiconductor 251. In this case, the semiconductor 251 can be made into a three-layer structure, as shown in Figure 50. The semiconductor device shown in Figure 50 has a three-layer structure of semiconductor 251, as shown in Figure 32( In the process of manufacturing the semiconductor device A), in the step shown in Figure 40(A), semiconductor 251 and It is constructed by sequentially forming semiconductor 253A, semiconductor 253B, and semiconductor 253C. It is possible.

[0315] Note that in Figures 51(A), (B), and (C), the dashed-dotted line C of the semiconductor device shown in Figure 50 is shown in each. Figure 5 shows the top view at 1-C2, the dashed-dotted line C3-C4, and the dashed-dotted line C5-C6. The semiconductor device shown in 0 has a semiconductor 253A and a semiconductor on the outside of the surface where the insulator 202 is formed. Figure 5 shows an example of a three-layer structure in which the body 253B and semiconductor 253C are deposited in that order. The top view shown in 1(A)(B)(C) shows the semiconductor 251 shown in Figure 44(A)(B)(C). It has a three-layer structure.

[0316] For semiconductors 253A, 253B, and 253C, see Fabrication Method Example 1. Refer to the descriptions of semiconductors 152A, 152B, and 152C explained. Also, see Figure The effects of constructing the semiconductor device shown in 50 were also explained in Example 1 of the manufacturing method. Refer to the description in Figure 22.

[0317] Furthermore, for example, one aspect of the present invention is to improve the reliability of a transistor WTr. The gate electrode configuration of transistor WTr may be changed from the configuration shown in Figure 43. Figures 52(A)(B) and 53(A)(B) show an example of a method for manufacturing the semiconductor device. .

[0318] In the process shown in Figure 52(A), as shown in Figure 39(B), etching is performed, A portion of the conductor 231 contained in the side surface of the opening 291 is removed, and a recess 29 is formed in the side surface. 4 is formed. Note that recess 294 is formed deeper than recess 292 shown in Figure 39(A). It's fine if it is done.

[0319] As a subsequent step, in Figure 52(B), the side of the opening 291 in Figure 52(A) A semiconductor 254 is formed in the recess 294.

[0320] As for semiconductor 254, for example, a material that can be applied to semiconductor 153 as described in manufacturing method example 1. You can use the fee.

[0321] The method for forming semiconductor 254 shall be based on the description of the method for forming semiconductor 251.

[0322] In the next step, as shown in Figure 53(A), resist mask formation and etching processes are performed. As a result, the semiconductor 254 remains in a portion of the recess 294 as described above, and the remaining part of the recess 294 The semiconductor 254 in the section and the semiconductor 254 included on the side surface of the opening 291 are removed. This forms semiconductor 254a.

[0323] After this, by performing the same steps as in Figures 39(B) to 43, we can obtain Figure 53(B) A semiconductor device can be constructed as shown in Figure 53(B). The effects of this are explained in Figures 27(A)(B) and 28(A)( Refer to the description in B).

[0324] Note that the dashed line C1 of the semiconductor device shown in Figure 53(B) is shown in Figures 54(A), 54(B), and 54(C). Figure 53 shows the top view at -C2, the dashed-dotted lines C3-C4, and the dashed-dotted lines C5-C6. The semiconductor device shown in (B) differs from the semiconductor device shown in Figure 43 in that, in region 251a The configuration includes a semiconductor 254a between the conductor 231 and the insulator 202. Therefore, the top view shown in Figure 54(C) shows a semiconductor 254 between the conductor 231 and the insulator 202. The configuration includes a. By the way, the dashed line C1 shown in Figure 54(A)(B) -C2, the top view along the dashed line C3-C4 has a configuration almost identical to that of Figures 44(A) and (B). It can happen.

[0325] A semiconductor capable of holding a large amount of data can be produced by the above-described manufacturing method example 1 or manufacturing method example 2. The device can be manufactured.

[0326] Here, Figure 2 shows a cross-sectional view of the semiconductor device shown in Figure 14(B) (circuit configuration of Figure 1(A)). Figure 55 shows an example of a configuration when a cell array structure is used. Similarly, Figure 43 shows a semi- An example configuration when the cross-sectional view of the conductor device (circuit configuration in Figure 32(A)) is represented as a cell array structure. This is shown in Figure 56. Note that region SD1 corresponds to the memory cell MC. As shown in Figure 55, A structure is formed by laminating a conductive material (a linear WL) and an insulator, and providing an opening in the same location. By manufacturing as described in Example 1 of the manufacturing method above, the circuit configuration shown in Figure 1(A) can be realized. It is possible. Also, as shown in Figure 56, a conductor which is wiring RWL or wiring WWL, An opening is provided collectively in the structure formed by stacking an insulator and the above-mentioned manufacturing method example 2. By following the instructions, the circuit configuration shown in Figure 32(A) can be realized.

[0327] <Example of connection with peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit in its lower layer, Peripheral circuits of the memory cell array, such as a recharge circuit, may be formed. In this case, silico A Si transistor is formed on a substrate or the like to constitute the peripheral circuit, and then the manufacturing method If, in Example 1 or Manufacturing Method Example 2, a semiconductor device according to one aspect of the present invention is formed on the peripheral circuit, Good. Figure 57(A) shows the peripheral circuit composed of planar Si transistors, and its upper layer Figure 58(A) shows a cross-sectional view in which a semiconductor device according to one aspect of the present invention is formed. The circuit is constructed with FIN-type Si transistors, and a semiconductor device according to one aspect of the present invention is placed on top of it. This is a formed cross-sectional view. Note that the semiconductor device shown in Figures 57(A) and 58(A) is just one example. Therefore, the configuration shown in Figure 14(B) is applied.

[0328] In Figures 57(A) and 58(A), the Si transistors constituting the peripheral circuit are located on the substrate. It is formed on 1700. The element isolation layer 1701 is formed between multiple Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed extending in the channel width direction, and is connected to other Si transistors, or It is connected to the conductor 1712 (not shown).

[0329] The substrate 1700 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Conductor substrates, compound semiconductor substrates made of silicon germanium, and SOI substrates are used. It is possible.

[0330] Furthermore, the substrate 1700 can be, for example, a glass substrate, a quartz substrate, a plastic substrate, or a metal substrate. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Any of these may be used. Alternatively, a semiconductor element can be formed using one substrate, and then a semiconductor can be formed on another substrate. The conductive elements may be transposed. In Figures 57(A) and 58(A), as an example, substrate 170 An example using a single-crystal silicon wafer is shown in section 0.

[0331] Here, we will explain the details of Si transistors. The planar type is shown in Figure 57(A). The Si transistor shown here is a cross-sectional view in the channel length direction and is a planar type as shown in Figure 57(B). The Si transistor shown is a cross-sectional view in the channel width direction. Channel formation region 1793 provided in cellulose 1792, low-concentration impurity region 1794 and The high-concentration impurity region 1795 (these are collectively also simply called the impurity region), and the impurity region A conductive region 1796 provided in contact with the region, and a channel forming region 1793 provided A gate insulating film 1797 and a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has side wall insulating layers 1798 and 1799 provided on its side. In addition, metal silicide or the like may be used in the conductive region 1796.

[0332] Furthermore, the FIN-type Si transistor shown in Figure 58(A) has a cross-sectional view in the channel length direction. As shown, the FIN-type Si transistor shown in Figure 58(B) has a cross-sectional view in the channel width direction. The Si transistor shown in Figures 58(A) and 58(B) has a channel formation region 1793. It has a convex shape, and along its side and top surfaces are a gate insulating film 1797 and a gate electrode 1790 A is provided. In this embodiment, when a part of the semiconductor substrate is processed to form a protrusion, Although this has been shown, a semiconductor layer having a convex shape may also be formed by processing the SOI substrate.

[0333] A Si transistor, conductor 1712, conductor 1730, etc. are formed on the substrate 1700. An insulator 301 is formed on the upper layer of the constructed circuit. The conductors 311A ​​and 311B for electrical connection to the circuit are embedded in the structure. It has been done. By the way, the channel formation region of the cell transistor CTr contains a metal oxide. If present, the insulator 301, conductor 311A, and conductor 311B are used for hydrogen, etc. It is preferable to use a material that has barrier properties against the elements. This includes an insulator 301 and a conductor 3 11A, at least one of the conductors 311B, from the Si transistor to the cell This is to suppress the diffusion of hydrogen into the lunger CTr.

[0334] The insulator 301 is a material applicable to the insulators 101A to 101C described above. You can use it.

[0335] Examples of conductors 311A ​​and 311B include nitrogen, which has barrier properties against hydrogen. It is advisable to use tantalum nitride or similar materials. Alternatively, tantalum nitride and highly conductive tungsten can be laminated together. This suppresses the diffusion of hydrogen from Si transistors while maintaining the conductivity of the wiring. It can be controlled.

[0336] Note that the symbols shown in Figures 58(A) and 58(B) are the same as the symbols shown in Figures 57(A) and 58(B). .

[0337] Furthermore, the insulators, conductors, semiconductors, etc. disclosed in this specification are subject to PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, It can be formed by the Deposition method. For example, the PVD method is... Sputtering method, resistance heating deposition method, electron beam deposition method, PLD (Pulsed Laminate) Examples include the plasma deposition method. Furthermore, CVD methods include plasma deposition. Examples include CVD methods and thermal CVD methods. In particular, as a thermal CVD method, MOCV is an example. D(Metal Organic Chemical Vapor Depositio Examples include the n) method and the ALD (Atomic Layer Deposition) method. ru.

[0338] Thermal CVD is a film deposition method that does not use plasma, so defects can occur due to plasma damage. It has the advantage of never being accomplished.

[0339] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber is subjected to atmospheric pressure. Alternatively, by applying reduced pressure and reacting the film near or on the substrate, the film can be deposited on the substrate. You may go.

[0340] Furthermore, the ALD method maintains atmospheric pressure or reduced pressure inside the chamber, and the raw material gas for the reaction is The gases are introduced into the chamber sequentially, and film deposition can be performed by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), two types or less The above raw material gases are supplied to the chamber in order, and the first is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. A second raw material gas is introduced. If an inert gas is introduced at the same time, the inert gas is... It acts as a carrier gas, and also when introducing a second raw material gas, an inert gas is introduced at the same time. Good. Also, instead of introducing an inert gas, the first source gas was removed by vacuum evacuation. Later, a second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate and the first thin A thin layer is formed, and it reacts with a second raw material gas that is introduced later, so that a second thin layer is formed against the first thin layer. Thin films are formed by stacking layers. The order of gas introduction is controlled until the desired thickness is achieved. By repeating this process multiple times, a thin film with excellent step coverage can be formed. (Thickness of the thin film) This can be adjusted by the number of times the gas introduction sequence is repeated, allowing for precise film thickness control. It is possible and suitable for fabricating miniature FETs.

[0341] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-G When forming an α-Zn-O film, trimethylindium (In(CH3)3), tri Methyl gallium (Ga(CH3)3) and dimethyl zinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium can be substituted for trimethylgallium. It is also possible to use um(Ga(C2H5)3), and diethylzinc can be used instead of dimethylzinc. Zn(C2H5)2) can also be used.

[0342] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl Hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: a raw material gas that is vaporized, and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamide)hafnium.

[0343] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, A liquid containing a medium and an aluminum precursor compound (trimethylaluminum (TMA, Al(C)) Two types of gases are used: a raw material gas obtained by vaporizing H3, etc., and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum and triisobutylaluminum. Luminium, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedi Examples include Honor.

[0344] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Chlorodisilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are removed. It is supplied and reacted with the adsorbed material.

[0345] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 The initial tungsten film is formed by sequentially introducing gas and B2H6 gas, and then WF A tungsten film is formed by sequentially introducing 6 gas and H2 gas. SiH4 gas may be used instead of S.

[0346] For example, oxide semiconductor films, such as In-Ga-Zn-, can be deposited using an ALD-based film deposition system. When forming an O film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. - An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form a Ga An O layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced in sequence to form a Zn layer. An O layer is formed. Note that the order of these layers is not limited to this example. Also, these gases are used This forms mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is permissible to do so. Furthermore, the water obtained by bubbling it with an inert gas such as Ar instead of O3 gas. While H2O gas can be used, it is preferable to use O3 gas, which does not contain H. In(C2H5)3 gas may be used instead of (CH3)3 gas. Also, Ga(CH 3) Ga(C2H5)3 gas may be used instead of 3 gas. Also, Zn(CH3)2 You may use gas.

[0347] Note that the configuration examples of the semiconductor device described in this embodiment can be combined with each other as appropriate. It can be done.

[0348] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0349] (Embodiment 2) This embodiment describes a storage device having the semiconductor device described in the above embodiment. I will reveal it.

[0350] Figure 59 shows an example of the configuration of a storage device. The storage device 2600 is connected to peripheral circuit 2601, and It has a memory cell array 2610. Peripheral circuit 2601 includes a low decoder 2621, and a power D-line driver circuit 2622, bit-line driver circuit 2630, output circuit 2640, control It has a roll logic circuit 2660.

[0351] The semiconductor shown in Figures 1(A)(B) and 32(A)(B)(C) described in Embodiment 1 The device can be applied to the memory cell array 2610.

[0352] The bit line driver circuit 2630 includes a column decoder 2631 and a pre-charge circuit 263 2. It has a sense amplifier 2633 and a programming circuit 2634. Pre-charge circuit 26 32 is the wiring SL, wiring BL, wiring RBL, etc. described in Embodiment 1 (as shown in Figure 59) It has the function of pre-charging (not yet) to a predetermined potential. The sense amplifier 2633 is The potential (or current) read from the Morisel MC is acquired as a data signal, and the data It has the function of amplifying the data signal. The amplified data signal is output via the output circuit 2640. The data signal is output to the outside of the storage device 2600 as a digital data signal RDATA.

[0353] Furthermore, the storage device 2600 receives a low power supply voltage (VSS) from an external source as the power supply voltage, and peripheral circuits. High power supply voltage (VDD) for path 2601, high power supply voltage (VI) for memory cell array 2610 L) is supplied.

[0354] Furthermore, the storage device 2600 contains control signals (CE, WE, RE) and address signals ADDR. The data signal WDATA is input from an external source. The address signal ADDR is used by the raw decoder. The data signal WDATA is input to 2621 and column decoder 2631 and is written to the writing circuit It will be entered into 2634.

[0355] The control logic circuit 2660 processes external input signals (CE, WE, RE). Then, control signals are generated for the low decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read This is the enable signal. The signal processed by the control logic circuit 2660 is this It is not limited to this; other control signals can be input as needed.

[0356] Furthermore, the aforementioned circuits and signals can be selected or omitted as needed.

[0357] Furthermore, a p-channel Si transistor and an oxide semiconductor (preferably) according to the embodiment described later. A transistor is used that includes an oxide containing In, Ga, and Zn in the channel formation region. By applying this to the storage device 2600, a compact storage device 2600 can be provided. We can provide a storage device 2600 that can reduce power consumption. Furthermore, we can improve the operating speed. A memory device 2600 capable of doing so can be provided. In particular, the Si transistor is p-channel type. By doing so, manufacturing costs can be kept low.

[0358] Note that the configuration example of this embodiment is not limited to the configuration shown in Figure 59. For example, peripheral circuit 26 A portion of 01, for example, the pre-charge circuit 2632 and / or the sense amplifier 2633, is stored in memory. The configuration may be modified as appropriate, such as by placing it in a lower layer of the cell array 2610.

[0359] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0360] (Embodiment 3) In this embodiment, the semiconductor device described in the above embodiment is used as a memory device for electronic components An example of its application will be explained using Figure 60.

[0361] Figure 60(A) shows the semiconductor device described in the above embodiment as a memory device for electronic components. Examples of application will be explained. Note that electronic components are semiconductor packages or IC packages. Also called a "ji." This electronic component has multiple standards depending on the direction of terminal extraction and the shape of the terminals. A name exists for it. Therefore, in this embodiment, we will describe one example.

[0362] The semiconductor device, which is composed of transistors as shown in Embodiment 1 above, is assembled in the assembly process After subsequent processes, the printed circuit board is completed by combining multiple detachable components.

[0363] The subsequent processes can be completed by going through the steps shown in Figure 60(A). Specifically, after the element substrate obtained in the previous process is completed (step STP1), the back side of the substrate Grinding (Step STP2). By thinning the substrate at this stage, the substrate in the previous step This is to reduce warping and other distortions, and to make the component smaller.

[0364] The back surface of the substrate is ground down to perform a dicing process, which separates the substrate into multiple chips. (STP3). Then, the separated chips are picked up individually and mounted on the lead frame. The die bonding process is performed (step STP4) to attach and join the parts. The bonding of the chip and lead frame during the bonding process is done using resin bonding or tape bonding. The appropriate method will be selected according to the product, such as for bonding. - It may be mounted on a poser and joined together.

[0365] In this embodiment, when the element is formed on one side of the substrate, One side is designated as the front surface, and the other side of the substrate (the side on which the elements are not formed) is designated as the back surface. Let's assume that.

[0366] Next, the leads of the lead frame and the electrodes on the chip are electrically connected using a thin metal wire. Perform wire bonding to connect the wires (Step STP5). For thin metal wires, use silver Wire or gold wire can be used. Also, wire bonding is a type of ball bonding. Wedge bonding can be used.

[0367] The wire-bonded chips undergo a molding process in which they are sealed with epoxy resin or the like. (Step STP6). The molding process fills the inside of the electronic component with resin. This reduces damage to the internal circuitry and wires caused by mechanical external forces. This also reduces the deterioration of properties due to moisture and dust.

[0368] Next, the leads of the lead frame are plated. Then the leads are cut and shaped. (Step STP7). This plating process prevents the leads from rusting, and later the printed circuit board... This allows for more reliable soldering during implementation.

[0369] Next, the surface of the package is printed (marked) (step STP8). The electronic component is completed after going through the final inspection process (Step STP9) (Step STP1). 0).

[0370] The electronic components described above include the semiconductor device described in the above-described embodiment. This makes it possible to create highly reliable electronic components.

[0371] Furthermore, a schematic perspective view of the completed electronic component is shown in Figure 60(B). In Figure 60(B), the electronic... As an example of a component, a schematic perspective view of a QFP (Quad Flat Package) is shown. The electronic component 4700 shown in Figure 60(B) consists of a lead 4701 and a circuit section 4703. This is shown. The electronic component 4700 shown in Figure 60(B) is actually implemented on the printed circuit board 4702, for example. Multiple such electronic components 4700 are combined, and each is a printed circuit board. By being electrically connected on the 4702, it can be mounted inside electronic devices. The circuit board 4704 is installed inside electronic equipment, etc.

[0372] Furthermore, one aspect of the present invention is not limited to the above-mentioned electronic component 4700, and in step STP1... This also includes element substrates manufactured using the step method. Furthermore, an element substrate according to one aspect of the present invention is a step substrate. This also includes element substrates that have undergone grinding on the back surface of the STP2 substrate. The element substrates include those that have undergone the dicing process in step STP3. For example, the semiconductor wafer 4800 shown in Figure 60(C) corresponds to the element substrate. Multiple circuit sections 4802 are formed on the upper surface of wafer 4801 of wafer 4800. Furthermore, on the upper surface of wafer 4801, the portion without the circuit section 4802 is spaced. The spacing is 4803, and a portion of the 4803 spacing becomes the area for dicing.

[0373] Dicing is performed using scribe lines SCL1 and SC, indicated by the dashed lines. This is done along L2 (sometimes called the dicing line or cutting line). Spacing 4803 has multiple scribe lines to facilitate the dicing process. SCL1 is set so that it is parallel, and multiple scribe lines SCL2 are set so that they are parallel. Install them so that scribe line SCL1 and scribe line SCL2 are perpendicular to each other. It is preferable to do so.

[0374] By performing the dicing process, the chip 4800a shown in Figure 60(D) is divided into half It can be cut from the conductive wafer 4800. Chip 4800a is made from wafer 4801a It has a circuit section 4802 and a spacing 4803a. Note that spacing 48 It is preferable to make 03a as small as possible. In this case, adjacent circuit section 4802 The width of the spacing 4803 between them is the cut-off margin of the scribe line SCL1, or the scribe line. The length should be approximately the same as the cutting allowance of the Liveline SCL2.

[0375] The shape of the element substrate in one aspect of the present invention is shown in Figure 60(C) as a semiconductor wafer 48 The shape is not limited to 00. For example, a rectangular semiconductor wafer 48 as shown in Figure 60(E) It may be 10. The shape of the element substrate is determined by the element manufacturing process and the equipment for manufacturing the element. It can be modified as appropriate depending on the location.

[0376] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0377] (Embodiment 4) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is included This section will primarily explain metal oxides.

[0378] The metal oxide preferably contains at least indium or zinc. In particular, indium It is preferable to include aluminum and zinc. In addition to these, aluminum, gallium, It is preferable that it contains yttrium or tin, etc. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may contain one or more types.

[0379] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium or Examples include tin. Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Examples include odymium, hafnium, tantalum, tungsten, and magnesium. However, these are elements. In some cases, M may be a combination of multiple elements as mentioned above.

[0380] Next, using Figures 61(A), 61(B), and 61(C), the metal according to the present invention This section describes the preferred range of atomic ratios of indium, element M, and zinc in oxides. Figures 61(A), 61(B), and 61(C) show the atomic ratio of oxygen. It will not be listed. Also, the number of atoms of indium, element M, and zinc in the metal oxide. Let the terms of the ratio be [In], [M], and [Zn].

[0381] In Figures 61(A), 61(B), and 61(C), the dashed line represents [In]:[M The line where the atomic ratio of ]:[Zn]=(1+α):(1-α):1 (-1≦α≦1), [In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is, The line [I]:[M]:[Zn]=(1+α):(1-α):3 represents the atomic ratio. The line where the atomic ratio of n]:[M]:[Zn]=(1+α):(1-α):4, and The line represents the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):5. vinegar.

[0382] Furthermore, the dashed line represents the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0) The line where the atomic ratio is [In]:[M]:[Zn]=2:1:β, [In [In]:[M]:[Zn] = 1:1:β is the atomic ratio line, [In]:[M]:[Zn The line where the atomic ratio of [In]:[M]:[Zn]=1:3:β The line represents the ratio of the number of atoms, and the atomic ratio is [In]:[M]:[Zn]=1:4:β. It represents a line.

[0383] Also, as shown in Figures 61(A), 61(B), and 61(C), [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1, and values ​​near that, exhibit spinel-type crystal formation. It's easy to create a structure.

[0384] Furthermore, multiple phases may coexist within a metal oxide (e.g., two-phase coexistence, three-phase coexistence). Example For example, if the atomic ratio is in the vicinity of [In]:[M]:[Zn]=0:2:1, then spin Two phases, one with a crystalline structure and the other with a layered structure, tend to coexist. Also, the atomic ratio is [In]: When [M]:[Zn]=1:0:0, the crystal structure is of the Bixbyte type and layered. Two phases with the crystal structure tend to coexist. When multiple phases coexist in a metal oxide, different formations occur. Grain boundaries may form between crystal structures.

[0385] Region A shown in Figure 61(A) represents the indium, element M, and zinc present in the metal oxide. An example of a preferred range for the atomic ratio is shown.

[0386] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides can be improved. The electron mobility can be increased. Therefore, metal oxides with a high indium content Compared to metal oxides with a low indium content, it exhibits higher carrier mobility.

[0387] On the other hand, when the content of indium and zinc in the metal oxide decreases, the carrier mobility decreases. It becomes lower. Therefore, the atomic ratio is [In]:[M]:[Zn]=0:1:0, and close to that. When the value is an adjacent value (for example, region C shown in Figure 61(C)), the insulating properties are high.

[0388] Therefore, a metal oxide according to one aspect of the present invention has high carrier mobility and few grain boundaries. It is preferable to have the atomic ratio shown in region A of Figure 61(A), which tends to result in a layered structure. It seems so.

[0389] In particular, in region B shown in Figure 61(B), within region A, CAAC(c-axis a (ligned crystalline)-OS is likely to form, and has high carrier mobility. A metal oxide is obtained.

[0390] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It is a crystal structure that is linked and distorted. The distortion refers to the region where multiple nanocrystals are linked. In this context, the orientation of the grid arrangement between a region with aligned grid arrangements and another region with aligned grid arrangements This refers to the parts that have changed.

[0391] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. There are also cases where the distortion has a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bows) are present. It is not possible to confirm (also called 'ndary') crystal grains. In other words, due to the distortion of the lattice arrangement, It can be seen that the formation of the boundary is suppressed. This is because CAAC-OS is in the ab-plane direction. The oxygen atoms are not densely arranged, and the substitution of metal elements reduces the bond distance between atoms. This is thought to be because the distortion can be tolerated through changes and other processes.

[0392] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has a clear bond. Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries does not occur. It can be said that this is a problem. Also, the crystallinity of metal oxides decreases due to the inclusion of impurities and the formation of defects. Because this can occur, CAAC-OS is a metal oxide with few impurities or defects (such as oxygen deficiencies). It can be described as a substance. Therefore, metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0393] Furthermore, region B is 4.1 from [In]:[M]:[Zn]=4:2:3, and its vicinity Includes adjacent values. Neighboring values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Furthermore, region B is defined as [In]:[M]:[Zn]=5:1:6, and its neighboring values, and The values ​​include [In]:[M]:[Zn] = 5:1:7 and its neighbors.

[0394] Furthermore, the properties of metal oxides are not uniquely determined by the atomic ratio. Even with ratios, the properties of metal oxides can differ depending on the formation conditions. For example, metal acids When depositing a phosphate using a sputtering device, the atomic ratio deviates from the target atomic ratio. A film is formed. Also, depending on the substrate temperature during film formation, the amount of [Zn] may be greater than that of the target [Zn]. The [Zn] content of the film may decrease. Therefore, the region shown in the illustration is where the metal oxide exhibits specific characteristics. This region exhibits an atomic ratio that tends to have a certain property, and the boundary between region A and region C is not strictly defined. stomach.

[0395] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0396] (Embodiment 5) In this embodiment, the CPU that can be equipped with the semiconductor device of the above embodiment is described below. explain.

[0397] Figure 62 shows an example configuration of a CPU that uses the semiconductor device described in Embodiment 1 in part. This is a block diagram.

[0398] The CPU shown in Figure 62 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc., is used. ROM1199 and ROM interface1189 are, It may also be provided on a separate chip. Of course, the CPU shown in Figure 62 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. A configuration including the CPU or arithmetic circuit shown in Figure 62 is considered one core, and a configuration including multiple such cores is considered. Alternatively, a configuration where each core operates in parallel, such as a GPU, is also possible. Furthermore, the number of bits that a CPU can handle in its internal arithmetic circuits and data bus is, for example, 8 bits, 16 bits. It can be 12 bits, 32 bits, 64 bits, etc.

[0399] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0400] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0401] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0402] In the CPU shown in Figure 62, a memory cell is provided in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0403] In the CPU shown in Figure 62, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0404] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0405] (Embodiment 6) The storage device in the above embodiment is a memory card (e.g., an SD card), USB (Univ (Serial Bus) memory, SSD (Solid State Drive) It can be applied to various removable storage devices such as (ve). In this embodiment, Several configuration examples of movable storage devices will be explained using Figure 63.

[0406] Figure 63(A) is a schematic diagram of a USB memory device. USB memory 5100 is housed in enclosure 5101 It has a cap 5102, a USB connector 5103, and a circuit board 5104. Circuit board 5104 It is housed in the enclosure 5101. The circuit board 5104 contains a memory device and a drive for the memory device. A circuit is provided for this purpose. For example, the circuit board 5104 has a memory chip 5105, a controller A roller chip 5106 is attached. The memory chip 5105 is in Embodiment 2. The memory cell array 2610, word line driver circuit 2622, and raw decoder 26 described above 21. Sense amplifier 2633, pre-charge circuit 2632, column decoder 2631, etc. It is incorporated. The controller chip 5106 specifically includes the processor, work machine It incorporates a memory chip, ECC circuit, etc. Note that the memory chip 5105 and controller are also included. The circuit configurations for each of the 5106 models are not limited to those described above, and the circuit configurations may be modified as appropriate. It may also be possible to use a word line driver circuit 2622, a low decoder 2621, and a senser. The memory chip 510 contains the 2633 circuit, the pre-charge circuit 2632, and the column decoder 2631. Alternatively, it could be integrated into the controller chip 5106 instead of using chip 5. USB connector 5103 functions as an interface for connecting to external devices.

[0407] Figure 63(B) is a schematic diagram of the external appearance of an SD card, and Figure 63(C) shows the internal structure of an SD card. This is a schematic diagram of the structure. The SD card 5110 consists of a housing 5111, a connector 5112, and a circuit board. It has 5113. Connector 5112 serves as an interface for connecting to an external device. It functions. The circuit board 5113 is housed in the casing 5111. The circuit board 5113 has memory storage. Circuits for driving memory chips and storage devices are provided. For example, the circuit board 5113 has memory chips The chip 5114 and controller chip 5115 are installed. Memory chip 511 4 includes the memory cell array 2610 and the word line driver circuit 26 described in Embodiment 2. 22. Low decoder 2621, sense amplifier 2633, precharge circuit 2632, color It incorporates a 2631 decoder and other components. The controller chip 5115 contains a processor It incorporates a sasser, work memory, ECC circuit, etc. Note that the memory chip 5114 and The circuit configurations for each component with the controller chip 5115 are not limited to those described above, and may be modified as appropriate. The circuit configuration may be changed. For example, the word line driver circuit 2622 and the low decoder 262 1. Note down the sense amplifier 2633, precharge circuit 2632, and column decoder 2631. Alternatively, the configuration could be integrated into the controller chip 5115 instead of using the separate chip 5114.

[0408] By also providing a memory chip 5114 on the back side of the circuit board 5113, the SD card 5110 The capacity can be increased. Also, a wireless chip with wireless communication functionality can be placed on board 5113. It may be provided. This will enable wireless communication between the external device and the SD card 5110. This enables reading and writing data to the memory chip 5114.

[0409] Figure 63(D) is a schematic diagram of the external appearance of an SSD, and Figure 63(E) is a schematic diagram of the internal structure of an SSD. This is a diagram. The SSD5150 has a housing 5151, a connector 5152, and a circuit board 5153. Connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the casing 5151. The circuit board 5153 contains a storage device and a memory device. A circuit is provided to drive the device. For example, the circuit board 5153 has a memory chip 5154 Memory chip 5155 and controller chip 5156 are installed. The top 5154 includes the memory cell array 2610 described in Embodiment 2, and the word line dry Circuit 2622, Low Decoder 2621, Sense Amplifier 2633, Precharge Circuit 26 32. It incorporates a column decoder 2631, etc. There is also a memo on the back of circuit board 5153. By adding the Rechip 5154, the capacity of the SSD5150 can be increased. Chip 5155 has work memory built into it. For example, memory chip 5155 A DRAM chip can be used. The controller chip 5156 has a processor, E CC circuits and other components are incorporated. Note that memory chip 5154 and memory chip 515 The circuit configurations of 5 and the controller chip 5115 are not limited to those described above. The circuit configuration may be changed as appropriate. For example, the controller chip 5156 also has a workpiece Memory that functions as a mori (a type of storage device) may be provided.

[0410] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0411] (Embodiment 7) In this embodiment, the semiconductor device or storage device of the above embodiment can be applied. Let me explain an example of an electronic device.

[0412] <Notebook personal computer> A semiconductor device or storage device according to one aspect of the present invention is provided for a notebook personal computer. It is possible to do so. Figure 64(A) is a notebook personal computer, and the casing is 540 1. Having a display unit 5402, a keyboard 5403, a pointing device 5404, etc. .

[0413] <Smartwatch> A semiconductor device or storage device according to one aspect of the present invention can be provided in a wearable terminal. Figure 64(B) shows a smartwatch, a type of wearable device, with a housing 590 1. It has a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, etc. Furthermore, a display device is used in which the display unit 5902 has the added function of a position input device. It may also be done in this way. Furthermore, the function as a position input device can be achieved by providing a touch panel on the display device. This can be added by using a photosensor. Alternatively, the function as a position input device can be achieved by using a photosensor. This can also be added by providing a photoelectric conversion element, also known as a photoelectric converter, in the pixel section of the display device. Additionally, the operation button 5903 is a power switch to activate the smartwatch. The buttons for operating the application on the switch, the volume control buttons, or the display unit 5902 are illuminated. It can be equipped with either a light or a switch to turn it off. Also, see Figure 64(B In the smartwatch shown, the number of operation buttons 5903 is shown as 2, but The number of operation buttons on the Towatch is not limited to this. Also, the operator 5904 is It functions as a crown for setting the time on a smartwatch. Also, the control part 5904 is In addition to setting the time, it also has an input interface for operating smartwatch applications. It may also be used as a case. Note that the smartwatch shown in Figure 64(B) The configuration includes an operator 5904, but is not limited to this configuration, and includes an operator 5904. It is also acceptable to have a configuration that does not involve this.

[0414] <Video camera> A semiconductor device or storage device according to one aspect of the present invention can be provided in a video camera. Figure 64(C) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 58 03, it has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 580 4 and lens 5805 are provided in the first housing 5801, and the display unit 5803 is in the second housing It is located in 5802. And the first housing 5801 and the second housing 5802 are connected by a connection part. They are connected by 5806, and the angle between the first housing 5801 and the second housing 5802 is, The connection part 5806 can be modified. The video displayed in the display unit 5803 is connected to the connection part 5806. The configuration is such that it switches according to the angle between the first housing 5801 and the second housing 5802. That's fine.

[0415] <Mobile phone> A semiconductor device or storage device according to one aspect of the present invention can be provided in a mobile phone. Figure 6 4(D) is a mobile phone having the function of an information terminal, and comprises a housing 5501, a display unit 5502, It has a microphone 5503, a speaker 5504, and operation buttons 5505. It also has a display unit 550 In addition, a display device with the added function of a position input device may be used in step 2. The function as a position input device can be added by providing a touch panel on the display device. Yes, it is possible. Alternatively, the function as a position input device can be achieved using a photoelectric element, also known as a photosensor. It can also be added by providing the child in the pixel section of the display device. Also, the operation button 55 05 is the power switch to start the mobile phone and the buttons to operate the mobile phone's applications. , volume control buttons, or switches to turn the display unit 5502 on or off, It can be equipped with any of the following.

[0416] Furthermore, the mobile phone shown in Figure 64(D) has two operation buttons 5505. However, the number of control buttons on a mobile phone is not limited to this. Also, although not shown in the diagram... The mobile phone shown in Figure 64(D) is equipped with a light-emitting device for use as a flashlight or illumination. It may also be a configuration that includes a placement.

[0417] <Television equipment> A semiconductor device or storage device according to one aspect of the present invention can be applied to a television apparatus. Figure 64(E) is a perspective view showing a television system. The television system is enclosed in a casing. Body 9000, display unit 9001, speaker 9003, operation keys 9005 (power switch, etc.) (including the operating switch), connection terminal 9006, sensor 9007 (force, displacement, position, velocity) , acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, Measures electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation. A storage device according to one aspect of the present invention has functions such as (including the function of) a television device. It can be equipped with a television set, for example, 50 inches or larger, or 100 inches. It is possible to incorporate a display unit 9001 of the size of a 'C' or larger.

[0418] <Mobile> A semiconductor device or storage device according to one aspect of the present invention is suitable for use around the driver's seat of a mobile vehicle. It can also be used.

[0419] For example, Figure 64(F) is a diagram showing the area around the windshield inside a car. Figure 64(F) shows the display panel 5701 and display panel 5 mounted on the dashboard. In addition to display panel 5703 (702), a display panel 5704 mounted on the pillar is also shown. It is.

[0420] Display panels 5701 to 5703 display navigation information, speedometer - Various information such as tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It can provide information. Also, the display items and layout displayed on the display panel are It can be modified as needed to suit the user's preferences, and the design can be enhanced. Display panels 5701 to 5703 can also be used as lighting devices. be.

[0421] The display panel 5704 displays images from an imaging device installed on the vehicle body. This allows for the correction of the blind spot (view obstructed by the pillars). In other words, on the outside of the car... By displaying images from the provided imaging means, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed without any problems. The display panel 5704 can also be used as a lighting device. can.

[0422] A semiconductor device or storage device according to one aspect of the present invention includes, for example, a display panel 5701 to a display panel A frame used to temporarily store image data when displaying an image on panel 5704. Used in memory and storage devices that store programs that drive the systems of mobile devices. It is possible to be there.

[0423] Also, although not shown in the diagrams, the electronic devices shown in Figures 64(A), (B), (E), and (F) are The configuration may also include a microphone and a speaker. This configuration allows, for example, the above-mentioned Electronic devices can be equipped with voice input functionality.

[0424] Additionally, although not shown in the illustrations, the electronic devices are shown in Figures 64(A), (B), (D) through (F). This configuration may include a camera.

[0425] Also, although not shown in the illustrations, the electronic devices shown in Figures 64(A) to (F) are located inside the enclosure. Sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration It may also be a configuration that includes a function for measuring motion, odor, or infrared radiation. In addition, the mobile phone shown in Figure 64(D) has a tilt detection sensor such as a gyroscope and an accelerometer. By providing a detection device that has a s, the orientation of the mobile phone (the mobile phone is in the vertical direction) can be determined. The device determines the orientation of the mobile phone and displays the screen of the display unit 5502 accordingly. It can be configured to switch automatically depending on the situation.

[0426] Also, although not shown in the illustrations, the electronic devices shown in Figures 64(A) to (F) are fingerprint, vein, The configuration may include a device that acquires biological information such as iris scans or voiceprints. By using this technology, it is possible to realize electronic devices with biometric authentication capabilities.

[0427] Furthermore, as the display unit of the electronic device shown in Figures 64(A) to (F), a flexible substrate is used. It may also be used. Specifically, the display unit has a transistor and a capacitor on a flexible substrate. The configuration may include elements and display elements. By applying this configuration, This includes not only housings with flat surfaces, such as the electronic devices shown in Figures 64(A) to (F), but also curved housings. This makes it possible to realize electronic devices with enclosures that have surfaces.

[0428] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0429] (Notes regarding the descriptions in this specification, etc.) A description of each component in the above embodiment is provided below.

[0430] <Notes relating to one aspect of the present invention described in the embodiments> The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to represent the present invention. This can be one embodiment. Furthermore, multiple configuration examples may be shown within a single embodiment. The combination allows for appropriate combinations of the configuration examples.

[0431] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0432] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0433] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0434] <Notes regarding ordinal numbers> In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. This was added to avoid that. Therefore, it does not limit the number of components. This does not limit the order of the components. Also, for example, in one of the embodiments described herein In the first embodiment, the component referred to in the first embodiment may be used in other embodiments or claims. It may also be considered a component referred to in "Section 2". Furthermore, for example, in this specification, etc. In one embodiment of the application, the component referred to as "first" is used in other embodiments or patents. Some details may be omitted within the scope of the claim.

[0435] <Notes regarding descriptions of drawings> The embodiments are described with reference to the drawings. However, the embodiments are many different. It is possible to implement it in any manner, without deviating from its purpose and scope, in any form It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, the present invention The invention of the embodiment is not to be interpreted as being limited to the description of the embodiment. In the configuration, the same reference numeral is used for identical parts or parts with similar functions across different drawings. We will use it throughout, and omit the explanation of its repetition.

[0436] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the diagram. The positional relationships between the components are The arrangement changes appropriately depending on the direction in which each component is described. Therefore, the terminology used to indicate the arrangement is specified in the specification, etc. The descriptions provided are not limited to those explained above, and can be appropriately rephrased depending on the situation. For example, In the expression "insulator located on the upper surface of the conductor," rotate the orientation of the diagram shown by 180 degrees. Therefore, it can be rephrased as "an insulator located on the underside of a conductor."

[0437] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0438] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are made with clarity in mind. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings. For example... , variations in signals, voltages, or currents due to noise, or signals due to timing discrepancies This can include variations in voltage, current, and other parameters.

[0439] Furthermore, in drawings, in perspective views and other similar views, some structural elements are used to ensure clarity of the drawings. In some cases, the original description may be omitted.

[0440] Furthermore, in the drawings, identical elements or elements with similar functions, elements of the same material, and In some cases, elements formed simultaneously may be given the same symbol, and the explanation for this repetition is as follows: It may be omitted in some cases.

[0441] <Notes regarding paraphrasable descriptions> In this specification, when describing the connection relationships of transistors, the term "source or drain" is used. "One side" (or the first electrode, or the first terminal), "the other side of the source or drain" (or the second electrode) The notation , or (second terminal) is used. This is because the source and drain of a transistor are This is because it varies depending on the transistor's structure or operating conditions. Regarding the terminology for drain, it can also be referred to as source (drain) terminal or source (drain) electrode, etc. It can be appropriately rephrased depending on the situation. Also, in this specification, the two other than the gate These terminals may be referred to as the first terminal, the second terminal, or the third terminal, the fourth terminal, etc. In this specification, the channel formation region refers to the region where a channel is formed, and the gate By applying an electric potential, this region is formed, allowing current to flow between the source and drain. Cut.

[0442] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0443] Furthermore, when the transistor described herein has two or more gates (this configuration (This is sometimes called a dual-gate structure), and these gates are called the first gate, the second gate and It can be called by name, or it can be called the front gate or back gate. In particular, "front gate" The phrases " " can be replaced with the phrase "gate". Also, The term "backgate" can be interchanged with the term "gate." The bottom gate is a region in the transistor fabrication process that is larger than the channel formation region. It refers to the terminal that is formed first, and the term "top gate" is used when manufacturing a transistor. This refers to terminals that are formed after the channel formation region.

[0444] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0445] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from a reference potential; for example, the reference potential is the ground potential (earth potential). If we consider it as electric potential, then voltage can be rephrased as electric potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0446] In this specification, the terms "membrane," "layer," etc. may be used in some cases or in some situations. Depending on the context, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive layer". In some cases, the term can be changed to "electromagnetic film." Alternatively, for example, "insulating film" could be used. In some cases, the term may be changed to "insulating layer." Or, depending on the circumstances... Alternatively, depending on the situation, you can replace terms such as "membrane" or "layer" with other terms. It is possible to use the term "conductor" instead of "conductive layer" or "conductive film". In some cases, the terminology can be changed. For example, terms such as "insulating layer" or "insulating film" can be used. In some cases, it may be possible to change the term to "insulator."

[0447] In this specification, terms such as "wiring," "signal line," and "power line" may be used as appropriate. Depending on the situation, they can be interchanged. For example, "wiring" and In some cases, it may be possible to change the term "signal line" to "signal line." Also, for example, In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" should be changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" may be changed to terms such as "signal lines." This is sometimes possible. Conversely, terms like "signal line" can also be used for "power line," etc. In some cases, it may be possible to change the terminology. Also, the "potential" applied to the wiring Change the terminology to a term like "signal," depending on the circumstances or situation. This is sometimes possible. Conversely, terms like "signal" can also be used in the context of "electric potential." It may be possible to change it to a different word.

[0448] <Notes regarding the definition of terms> The following explains the definitions of terms used in the above embodiment.

[0449] <<Regarding impurities in semiconductors>> Impurities in semiconductors refer to components other than the main components that make up the semiconductor layer, for example. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The formation of Density of States (DOS) and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, for example, hydrogen (also found in water), lithium, sodium, silicon, boron, ri These include hydrogen, carbon, and nitrogen. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can cause problems. This can lead to the formation of oxygen vacancies. Furthermore, if the semiconductor is a silicon layer, the semiconductor properties... Impurities that alter the composition include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and Group 1 elements. These include Group 3 elements and Group 15 elements.

[0450] <<About the switch>> In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0451] For example, an electrical switch or a mechanical switch can be used. Furthermore, any switch that can control the current will suffice, and is not limited to any particular type.

[0452] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is.

[0453] Furthermore, when using a transistor as a switch, the "conductive state" of the transistor refers to: A state in which the source and drain electrodes of a transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of a transistor refers to the state where the source electrode and drain electrode of the transistor are connected. This refers to a state in which the poles can be considered electrically blocked. Note that a transistor is not simply a switch. When operating in this manner, the polarity (conductivity type) of the transistor is not particularly limited.

[0454] One example of a mechanical switch is a digital micromirror device (DMD). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are Yes, it exists. The switch has electrodes that can be moved mechanically, and when those electrodes move... Therefore, it operates by controlling the states of conduction and non-conductivity.

[0455] <<About Connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. When they are directly connected, when X and Y are functionally connected, and when X and Y are directly connected This includes cases where a connection is made. Therefore, a predetermined connection relationship, for example, in the diagram or This includes not only connections shown in text, but also connections other than those shown in diagrams or text. It shall be considered as such.

[0456] Here, X, Y, etc., refer to the object (e.g., device, element, circuit, wiring, electrode, terminal). (Conductive film, layer, etc.)

[0457] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not it is released.

[0458] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc. ), voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0459] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When functionally connected with another circuit in between) and when X and Y are directly connected (That is, the case where X and Y are connected without another element or circuit in between) It shall be assumed that they are electrically connected. In other words, when explicitly stating that they are electrically connected, simply, This is equivalent to the case where it is explicitly stated that it is "continued."

[0460] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (or Without an intermediary, X is electrically connected, and the drain of the transistor (or the second terminal, etc.) is connected. If Y is electrically connected via (or without) Z2, or if the transistor's saw A part of Z1 (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are indirectly connected, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When they are connected and another part of Z2 is directly connected to Y, the following table It can be expressed.

[0461] For example, "X and Y and the source (or first terminal, etc.) and drain (or the first terminal) of the transistor" Terminals 2, etc., are electrically connected to each other, and X is the source of the transistor (or The electrical components are connected in the following order: the first terminal (or the second terminal), the transistor's drain (or the second terminal), and Y. It can be expressed as "connected to the source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as, "X is the source (or first terminal, etc.) of the transistor." Alternatively, "X is the source (or first terminal, etc.) of the transistor." Y is electrically connected to X, and the transient is electrically connected to X via the drain (or second terminal, etc.) and the drain. The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) It can be expressed as, "Y is provided in this connection order." Similar to these examples... By using a method of representation to specify the order of connections in a circuit configuration, the transition Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the starter. This allows us to determine the technical scope. Note that these expressions are just examples, and this... The method of expression is not limited to these. Here, X, Y, Z1, Z2 are objects (e.g., devices, (Examples include elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0462] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0463] <<Regarding parallel and perpendicular lines>> In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. This refers to the case where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means This refers to a state where two straight lines are positioned at an angle between 60° and 120°. [Explanation of Symbols]

[0464] MC[1] Memory cell MC[2] Memory cell MC[n] Memory Cell CTr Cell Transistor STr transistor BTr transistor SSL wiring BSL wiring SL wiring BL wiring WL[1] Wiring WL[2] Wiring WL[n] Wiring BGL Wiring MC[1,1] memory cell MC[j,1] Memory cell MC[n,1] Memory cell MC[1,i] Memory cell MC[j,i] Memory cell MC[n,i] Memory cell MC[1,m] Memory Cell MC[j,m] Memory Cell MC[n,m] memory cell STr[1] Transistor STr[i] Transistor STr[m] Transistor BTr[1] Transistor BTr[i] Transistor BTr[m] Transistor SSL[1] Wiring SSL[i] wiring SSL[m] Wiring BSL[1] Wiring BSL[i] Wiring BSL[m] Wiring SL[1] Wiring SL[i] wiring SL[m] Wiring BL[1] Wiring BL[i] Wiring BL[m] Wiring WL[j] Wiring BGL[1] Wiring BGL[i] Wiring BGL[m] Wiring HL area AR area SD1 area SD2 area TM area ER wiring PG conductor WWL[1] Wiring WWL[2] Wiring WWL[n] wiring RWL[1] Wiring RWL[2] Wiring RWL[n] Wiring WBL Wiring RBL wiring WTr transistor RTr transistor CS capacitive element N1 node N2 node WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL[1] Wiring RBL[i] Wiring RBL[m] Wiring D[1] Data D[2] Data D[n] Data 10. Supply Processing 11. Supply Processing 20 Supply Processing 100-layer structure 101A Insulator 101B Insulator 101C insulator 102 Insulator 104 Insulator 105 Insulator 106 Insulator 109 Insulator 109a Insulator 109b Insulator 111 Insulator 111a Insulator 111b Insulator 132A Conductor 132B Conductor 134 Conductors 138a Conductor 138b Conductor 139 Conductors 151 Semiconductors 151a area 151b area 152A Semiconductor 152B Semiconductor 152C Semiconductor 153 Semiconductors 153a Semiconductor 153b Semiconductor 161A Compound 161B Compound 161C compound 162A Impurity region 162B Impurity region 162C impurity region 181A area 181B area 191 Opening 192A Recess 192B Recess 196A Recess 196B Recess 200-layer structure 201A Insulator 201B Insulator 201C insulator 202 Insulator 203 Insulator 203a Insulator 204 Insulator 205 Insulator 205A insulator 205B Insulator 207 Insulator 208 Insulator 231 Conductors 232 Conductors 233 Conductors 239 Conductors 251 Semiconductors 251a area 251b area 252 Semiconductors 253A Semiconductor 253B Semiconductor 253C Semiconductor 254 Semiconductors 254a Semiconductor 261A Compound 261B Compound 262A Impurity region 262B Impurity region 281 areas 282 areas 283 areas 291 Opening 292 recess 294 recess 301 Insulator 311A Conductor 311B Conductor 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1700 circuit boards 1701 Element Isolation Layer 1712 Conductors 1730 Conductor 1790 🙏 1792 Well 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Sidewall insulation layer 1799 Sidewall insulation layer 2600 storage device 2601 Peripheral Circuits 2610 memory cell array 2621 Low Decoder 2622 Word Line Driver Circuit 2630 bit line driver circuit 2631 Column Decoder 2632 Precharge Circuit 2633 SenseAmp 2634 Programming Circuit 2640 Output Circuit 2660 Control Logic Circuit 4700 Electronic Components 4701 Lead 4702 Printed circuit board 4703 Circuit section 4704 Circuit board 4800 semiconductor wafers 4800a chip 4801 wafer 4801a wafer 4802 Circuit section 4803 Spacing 4803a Spacing 4810 Semiconductor wafer 5100 USB flash drive 5101 enclosure 5102 Cap 5103 USB connector 5104 circuit board 5105 memory chip 5106 Controller Chip 5110 SD card 5111 enclosure 5112 connector 5113 circuit board 5114 memory chip 5115 Controller Chip 5150 SSD 5151 enclosure 5152 Connector 5153 circuit board 5154 memory chip 5155 memory chip 5156 Controller Chip 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5501 enclosure 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation Buttons 5701 Display Panel 5702 Display Panel 5703 Display Panel 5704 Display Panel 5801 First cabinet 5802 Second cabinet 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part 5901 enclosure 5902 Display section 5903 Operation Buttons 5904 Operator 5905 Band 9000 cabinets 9001 Display section 9003 Speaker 9005 Operation Keys 9006 Connection terminal 9007 Sensor

Claims

[Claim 1] A semiconductor device having a first to seventh insulator, a first conductor, and a first semiconductor, The first conductor is located on the first upper surface of the first insulator, The first conductor is located on the first lower surface of the second insulator, The third insulator is located in a region including the side surface of the first insulator, the second upper surface of the first insulator, the side surface of the first conductor, the second lower surface of the second insulator, and the side surface of the second insulator. The fourth insulator is located on the forming surface of the third insulator, The fifth insulator is located on the forming surface of the fourth insulator, The first semiconductor is located on the formation surface of the fifth insulator, The sixth insulator is located in a region of the formation surface of the first semiconductor that overlaps with the first conductor via the third to fifth insulators. The seventh insulator is The first semiconductor formation surface superimposed on the first insulator, The first semiconductor formation surface superimposed on the second insulator, A semiconductor device characterized by being located in a region including the formation surface of the sixth insulator.

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