Semiconductor memory device and method for initializing the same

Abstract

The present invention provides a semiconductor memory device and an initialization method thereof that refreshes initial data in a memory cell during initialization and stabilizes the charge amount of the memory cell. [Solution] The semiconductor memory device 100 includes a memory array, a refresh controller, and an initialization controller. The memory array has a plurality of equalization circuits and N memory cells. Each of the plurality of equalization circuits is connected to the N memory cells via a plurality of bit line pairs. The refresh controller sequentially refreshes the initial data in the N memory cells according to an automatic refresh command. The initialization controller performs an initialization operation according to an initialization start command. During the initialization operation, the initialization controller activates the equalization circuits and periodically generates automatic refresh commands.

Description

Technical Field

[0001] The present invention relates to an operation method of a memory, and particularly to a semiconductor memory device and an initialization method thereof.

Background Art

[0002] When performing initialization at the start-up of a dynamic random access memory (DRAM), since a turn-on voltage is not applied to the word line, the access transistors in the memory cells remain in an off state. At this time, the amount of charge possessed by each memory cell may not be constant due to the influence of connection, static electricity, or other effects. In this case, when sensing the memory cell, it is difficult for the voltage of the bit line to reach a stable state, the sensing speed becomes slow, the power consumption becomes high, and there is even a possibility of sensing failure.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a semiconductor memory device and an initialization method thereof that can stabilize the charge amount (voltage) of a memory cell during the initialization operation of the semiconductor memory device.

Means for Solving the Problems

[0004] The semiconductor memory device of the present invention includes a memory array, a refresh controller, and an initialization controller. The memory array has a plurality of equalization circuits and N memory cells. The plurality of equalization circuits are each connected to the N memory cells via a plurality of bit line pairs, and N is a positive integer greater than 1. The refresh controller is connected to the memory array and is configured to sequentially refresh the initial data to the N memory cells according to an auto-refresh command. The initialization controller is connected to the memory array and the refresh controller and is configured to perform an initialization operation according to an initialization start command. During the initialization operation, the initialization controller enables the equalization circuits and periodically generates an auto-refresh command.

[0005] The semiconductor memory device initialization method of the present invention is applicable to a semiconductor memory device including the memory array described above. The initialization method includes the steps of: performing an initialization operation in accordance with an initialization start command; enabling an equalization circuit and periodically generating an automatic refresh command during the initialization operation; and refreshing initial data in N memory cells in accordance with the automatic refresh command. [Effects of the Invention]

[0006] The semiconductor memory device and its initialization method of the present invention can refresh the memory cell with initial data during the initialization operation, thereby stabilizing the charge amount of the memory cell. When performing a later specified operation, the bit line voltage can be quickly stabilized, improving sensing speed, reducing power consumption, and effectively avoiding sensing failures. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic block diagram of a semiconductor memory device relating to one embodiment of the present invention is shown. [Figure 2] A schematic circuit diagram of a memory array according to one embodiment of the present invention is shown. [Figure 3] A schematic block diagram of an initialization controller relating to one embodiment of the present invention is shown. [Figure 4] A flowchart of the initialization method for one embodiment of the present invention is shown. [Modes for carrying out the invention]

[0008] Referring to Figure 1, the semiconductor memory device 100 of the present invention includes a memory array 110, a refresh controller 120, and an initialization controller 130. The memory array 110 is an array composed of, for example, dynamic random access memory. As shown in Figure 2, the memory array 110 includes equalization circuits 112_1, 112_2, sense amplifier circuits 114_1, 114_2, selection circuits 116_1, 116_2, and N memory cells 118, where N is a positive integer greater than 1.

[0009] Equalization circuits 112_1 and 112_2 are connected to N memory cells 118 via bit line pairs BLP1 and BLP2, respectively. More specifically, in Figure 2, bit line pair BLP1 is connected to the first bit line BLb <0> and the second bit line BLt <0> The bit line pair BLP2 includes the first bit line BLb <1> and the second bit line BLt <1> The equalization circuit 112_1 includes transistors M1_1 to M3_1. The first terminal of transistor M1_1 is connected to the first bit line BLb. <0> The second terminal of transistor M1_1 is connected to the second bit line BLt, and the second terminal of transistor M2_1 receives the equalization voltage VBLEQ, and the control terminal of transistor M1_1 receives the equalization signal EQL. The first terminal of transistor M2_1 is connected to the second terminal of transistor M1_1, and the second terminal of transistor M2_1 is connected to the second bit line BLt. <0> The control terminal of transistor M2_1 is connected to receive the equalization signal EQL. The first terminal of transistor M3_1 is connected to the first bit line BLb. <0> The second terminal of transistor M3_1 is connected to the second bit line BLt. <0> The control terminal of transistor M3_1 is connected to the equalization signal EQL. The equalization circuit 112_2 includes transistors M1_2 to M3_2, and its connection method is similar to that of transistors M1_1 to M3_1 in the equalization circuit 112_1. Transistors M1_1 to M3_1 and M1_2 to M3_2 may be realized by, for example, N-type metal-oxide-semiconductor field-effect transistors (PMOSFETs).

[0010] Each equalization circuit 112_1 and 112_2 can receive an equalization signal EQL from the initialization controller 130. When the equalization signal EQL is converted to an enable level (e.g., a high logic level), transistors M1_1 to M3_1 in equalization circuit 112_1 and transistors M1_2 to M3_2 in equalization circuit 112_2 are turned on. In this way, equalization circuit 112_1 uses the equalization voltage VBLEQ to control the first bit line BLb <0> The voltage of the second bit line BLt <0> The voltage can be controlled to match the first bit line BLb, and the equalization circuit 112_2 uses the equalization voltage VBLEQ to control the first bit line BLb. <1> The voltage of the second bit line BLt <1> It can be controlled to match the voltage.

[0011] Sense amplifier circuits 114_1 and 114_2 are similarly connected to N memory cells 118 via bit line pairs BLP1 and BLP2, respectively. Sense amplifier circuit 114_1 includes transistors M4_1 to M7_1. The first terminal of transistor M4_1 receives the first sensing control voltage NCS, and the second terminal of transistor M4_1 receives the first bit line BLb <0> The control terminal of transistor M4_1 is connected to the second bit line BLt. <0> The first terminal of transistor M5_1 is connected to the first bit line BLb. <0> The second terminal of transistor M5_1 receives the second sensing control voltage PCS, and the control terminal of transistor M5_1 receives the second bit line BLt. <0> The first terminal of transistor M6_1 receives the first sensing control voltage NCS, and the second terminal of transistor M6_1 receives the second bit line BLt. <0> The control terminal of transistor M6_1 is connected to the first bit line BLb. <0> The first end of transistor M7_1 is connected to the second bit line BLt. <0> The second terminal of transistor M7_1 receives the second sensing control voltage PCS, and the control terminal of transistor M7_1 is connected to the first bit line BLb. <0> The sense amplifier circuit 114_2 includes transistors M4_2 to M7_2, and its connection method is similar to that of transistors M4_1 to M7_1 in the sense amplifier circuit 114_1. Transistors M4_1, M6_1, M4_2, and M6_2 may be implemented by, for example, N-type metal-oxide-semiconductor field-effect transistors, and transistors M5_1, M7_1, M5_2, and M7_2 may be implemented by, for example, P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs).

[0012] When sense amplifier circuits 114_1 and 14_2 sense N memory cells 118, the first sensing control voltage NCS is set to a logic 0 voltage (e.g., a low logic level), and the second sensing control voltage PCS is set to a logic 1 voltage. In this way, sense amplifier circuits 114_1 and 14_2 can stabilize the voltages of the bit line pairs BLP1 and BLP2, respectively, using the first sensing control voltage NCS and the second sensing control voltage PCS.

[0013] The selection circuit 116_1 is connected between the bit line pair BLP1 and the data line pair DLP1. More specifically, the data line pair DLP1 is connected to the first data line DQb <0> and the second data line DQt <0> The selection circuit 116_1 includes transistors M8_1 and M9_1. The first terminal of transistor M8_1 is connected to the first bit line BLb. <0> The second terminal of transistor M8_1 is connected to the first data line DQb. <0> The control terminal of transistor M8_1 is connected to the row selection signal CSL. The first terminal of transistor M9_1 is connected to the second bit line BLt. <0> The second terminal of transistor M9_1 is connected to the second data line DQt. <0> The control terminal of transistor M9_1 is connected to receive the row selection signal CSL. When a memory cell 118 connected to the bit line pair BLP1 is selected and a specified operation (for example, a write operation or a read operation) is performed, the row selection signal CSL turns on transistors M8_1 and M9_1, making the transmission path between the bit line pair BLP1 and the data line pair DLP1 conductive. Transistors M8_1 and M9_1 may be implemented, for example, by N-type metal oxide semiconductor field-effect transistors.

[0014] The selection circuit 116_2 is connected between the bit line pair BLP2 and the data line pair DLP2. The data line pair DLP2 is the first data line DQb <1> and the second data line DQt <1> The selection circuit 116_2 includes transistors M8_2 and M9_2. The first terminal of transistor M8_2 is connected to the first bit line BLb. <1> The second terminal of transistor M8_2 is connected to the first data line DQb. <1> The control terminal of transistor M8_2 is connected to receive the row selection signal CSL. The first terminal of transistor M9_2 is connected to the second bit line BLt. <1> The second terminal of transistor M9_2 is connected to the second data line DQt. <1> The control terminal of transistor M9_2 is connected to receive the row selection signal CSL. When a memory cell 118 connected to the bit line pair BLP2 is selected and performs the specified operation, the row selection signal CSL turns on transistors M8_2 and M9_2, making the transmission path between the bit line pair BLP2 and the data line pair DLP2 conductive. Transistors M8_2 and M9_2 may be implemented, for example, by N-type metal oxide semiconductor field-effect transistors.

[0015] Returning to Figure 1, the refresh controller 120 is connected to the memory array 110. The refresh controller 120 is configured to sequentially refresh the initial data IData of the N memory cells 118 in the memory array 110 according to the automatic refresh command IC_AR. The initialization controller 130 is connected to the memory array 110 and the refresh controller 120. The initialization controller 130 is configured to output an initialization signal STM to the memory array 110 and start the initialization operation according to the initialization start command Init_on. The initialization start command Init_on is a command output by the memory controller to indicate that initialization should be performed, for example, when the semiconductor memory device 100 is started up. The initial data IData is, for example, data indicating a logical 0, and the voltage of the memory cell 118 that stores the initial data IData is, for example, the ground voltage (e.g., 0 volts). The advantage of this is that when the memory cell 118 is subsequently selected to perform a specified operation, the turn-on voltage Von applied to the corresponding word line WL does not need to be very high (theoretically, it just needs to be higher than the threshold voltage of the access transistor MA), thus improving the convenience of operation.

[0016] During the initialization process, the initialization controller 130 enables the equalization circuits 112_1 and 112_2 in the memory array 110, disables the sense amplifier circuits 114_1 and 114_2 in the memory array 110, and simultaneously generates a refresh command IC_AR periodically.

[0017] The initialization signal STM output by the initialization controller 130 includes at least the equalization signal EQL and equalization voltage VBLEQ used by each equalization circuit 112_1, 112_2, the first sensing control voltage NCS and second sensing control voltage PCS used by each sense amplifier circuit 114_1, 114_2, and the turn-on voltage Von for turning on the access transistor MA in the memory cell 118. During initialization, the initialization controller 130 maintains the equalization signal EQL at the enable level and sets the equalization voltage VBLEQ to be equal to the ground voltage. This enables the equalization circuits 112_1, 112_2.

[0018] Furthermore, during the initialization operation, the initialization controller 130 sets the first sensing control voltage NCS and the second sensing control voltage PCS to be equal to the ground voltage. This disables the sense amplifier circuits 114_1 and 114_2, thereby avoiding leakage current.

[0019] During initialization, the initialization controller 130 sets the initial value of K to 1. Each time the initialization controller 130 generates an automatic refresh command IC_AR, the initialization controller 130 simultaneously turns on multiple access transistors MA in memory cells from the Kth to the K+Jth among the N memory cells 118, and then increases K by J+1 (K=K+J+1) until K becomes greater than N or the initialization controller 130 receives the initialization completion command Init_done. J is a positive integer greater than or equal to 1. Furthermore, the refresh controller 120 may operate in conjunction with the initialization controller 130. Each time the refresh controller 120 receives an automatic refresh command IC_AR generated by the initialization controller 130, the refresh controller 120 can refresh the initial data IData in memory cells from the Kth to the K+Jth among the N memory cells 118.

[0020] Assuming J is equal to 3, when the auto-refresh command IC_AR is generated for the first time (K is equal to 1), the initialization controller 130 provides a turn-on voltage Von to the word line WL corresponding to the first memory cell 118 through the fourth memory cell 118 to be refreshed, thereby simultaneously turning on the access transistor MA in the first memory cell 118 through the fourth memory cell 118, and then increases K to 5. Furthermore, the refresh controller 120, having now received the auto-refresh command IC_AR, can simultaneously refresh the initial data IData in the first memory cell 118 through the fourth memory cell 118. When the auto-refresh command IC_AR is generated for the second time (K is equal to 5), the initialization controller 130 provides a turn-on voltage Von to the word line WL corresponding to the fifth memory cell 118 through the eighth memory cell 118 to be refreshed, thereby simultaneously turning on the access transistor MA in the fifth memory cell 118 through the eighth memory cell 118, and then increases K to 9. Furthermore, upon receiving the automatic refresh command IC_AR, the refresh controller 120 can simultaneously refresh the initial data IData from the fifth memory cell 118 to the eighth memory cell 118. This process continues until K accumulates to a value greater than N (indicating that all access transistors MA in the memory cell 118 have been turned on) or until the initialization controller 130 receives the initialization completion command Init_done. The initialization completion command Init_done is, for example, a command output by the memory controller indicating the completion of initialization.

[0021] In this embodiment, the value of J may correspond to the number of memory cells 118 that are refreshed simultaneously. Those skilled in the art can appropriately adjust the value of J according to their actual needs and by referring to the teachings of this embodiment.

[0022] By the above operation, when performing the initialization operation of the semiconductor memory device, the charge amounts of all memory cells can be stabilized as much as possible. In this way, even when the memory cells are sensed for the first time after the initialization is completed, unstable factors due to connection, static electricity or other effects can be eliminated, the voltage of the bit line can be quickly stabilized, the sensing speed can be improved, the power consumption can be reduced, and sensing failures can be effectively avoided.

[0023] The internal structure of the initialization controller 130 will be described below by way of example. Referring to FIG. 3, the initialization controller 130 includes a voltage division and oscillation circuit 132, a counting and control circuit 134, a signal generation circuit 136, and a refresh counter circuit 138. The voltage division and oscillation circuit 132 is configured to receive an initialization start command Init_on, starts up in response to the initialization start command Init_on, and generates a clock signal CLK. When receiving the initialization start command Init_on, the voltage division and oscillation circuit 132 starts generating the clock signal CLK at a predetermined period.

[0024] The counting and control circuit 134 is connected to the voltage division and oscillation circuit 132. The counting and control circuit 134 is configured to receive the initialization start command Init_on and the clock signal CLK. The counting and control circuit 134 can output a refresh start command IC_on in response to the initialization start command Init_on. When receiving the initialization start command Init_on, the counting and control circuit 134 outputs the refresh start command IC_on to the signal generation circuit 136.

[0025] The counting and control circuit 134 can count the clock signal CLK and accumulate a first count value. Each time the first count value is accumulated up to a first predetermined number of times, the counting and control circuit 134 can reset the first count value to zero and output an automatic refresh command IC_AR to the refresh controller 120 and the signal generation circuit 136. The magnitude of the first predetermined number of times may be determined by the delay time required for the refresh controller 120 to refresh the initial data IData from the Kth memory cell to the K+Jth memory cell among the N memory cells 118.

[0026] The signal generation circuit 136 is connected to the counting and control circuit 134. The signal generation circuit 136 is configured to receive the refresh start command IC_on and the automatic refresh command IC_AR. The signal generation circuit 136 can provide an initialization signal STM to the memory array 110 according to the refresh start command IC_on and the automatic refresh command IC_AR. Specifically, upon receiving the refresh start command IC_on, the signal generation circuit 136 can provide the equalization signal EQL of the enable level and the equalization voltage VBLEQ set to be equal to the ground voltage to the equalization circuits 112_1 and 112_2 in the memory array 110, and can provide the first sensing control voltage NCS and the second sensing control voltage PCS set to be equal to the ground voltage to the sense amplifier circuits 114_1 and 114_2 in the memory array 110. In addition, each time the automatic refresh command IC_AR is received, the signal generation circuit 136 can provide a turn-on voltage Von to the word line WL corresponding to the memory cell 118 to be refreshed.

[0027] The refresh counter circuit 138 is connected to the voltage divider and oscillation circuit 132 and the counting and control circuit 134. The refresh counter circuit 138 is configured to receive the clock signal CLK. The refresh counter circuit 138 counts the clock signal CLK and accumulates a second count value. When the second count value has accumulated up to a second predetermined number of times, it indicates that all memory cells 118 in the display memory array 110 have been refreshed. At this time, the refresh counter circuit 138 can output a refresh completion command IC_done to the counting and control circuit 134. The magnitude of the second predetermined number of times may be determined by the delay time required to refresh all memory cells 118 in the memory array 110.

[0028] When the counting and control circuit 134 receives the refresh completion command IC_done, it can respond to the refresh completion command IC_done by stopping the output of the automatic refresh command IC_AR. In this way, the refresh controller 120 stops refreshing the memory cells 118 in the memory array 110 with initial data IData and terminates the initialization operation.

[0029] When the refresh counter circuit 138 receives the initialization completion command Init_done, it outputs the refresh completion command IC_done to the counting and control circuit 134. In this way, even if there are memory cells 118 that have not been refreshed in the memory array 110, the initialization operation can be terminated immediately depending on the situation, thus avoiding interference with the startup process of the semiconductor memory device 100.

[0030] The refresh controller 120 and the initialization controller 130 may be implemented by digital circuits, and the associated hardware architecture is not particularly limited and can be generated by digital circuit design methods known to those skilled in the art.

[0031] Referring to Figure 4, the initialization method for the semiconductor memory device includes the following steps: Initialization operation is performed according to the initialization start command (step S400). During the initialization operation, the equalization circuit is activated and automatic refresh commands are generated periodically (step S402). Initial data is sequentially refreshed into N memory cells according to the automatic refresh commands (step S404). Details of the implementation of steps S400 to S404 can be explained by referring to the embodiments in Figures 1 to 3, so they will not be explained in detail here.

[0032] In summary, during the initialization process, the equalization voltage used by the equalization circuit and the sensing control voltage used by the sense amplifier circuit are adjusted, and the initial data is refreshed into the memory cell, thereby stabilizing the charge amount of the memory cell. When performing the specified operation later, unstable elements due to connections, static electricity, or other effects can be eliminated, the bit line voltage can be quickly stabilized, the sensing speed can be improved, power consumption can be reduced, and sensing failures can be effectively avoided. [Industrial applicability]

[0033] The semiconductor memory device and its initialization method of the present invention can be applied to perform memory initialization operations. [Explanation of symbols]

[0034] 100: Semiconductor memory 110: Memory Array 112_1, 112_2: Equalization circuit 114_1, 114_2: Sense amplifier circuit 116_1, 116_2: Selection Circuit 118: Memory Cell 120: Refresh Controller 130: Initialization Controller 132: Voltage divider and oscillator circuits 134: Counting and Control Circuits 136: Signal generation circuit 138: Refresh Counter Circuit BLP1, BLP2: Bit line pairs BLb <0> BLb <1> :1st bit line BLt <0> BLt <1> :2nd bit line CLK: Clock signal CSL: Row selection signal DLP1, DLP2: Data line pairs DQb <0> , DQb <1> : First data line DQt <0> , DQt <1> : Second data line EQL: Equalization signal IC_AR: Automatic refresh command IC_done, IC_on: Refresh completion command, refresh start command IData: Initial Data Init_done, Init_on: Initialization completion command, Initialization start command M1_1~M9_1, M1_2~M9_2: Transistors MA: Access transistor NCS, PCS: First sensing control voltage, Second sensing control voltage STM: Initialization signal VBLEQ: Equalizing Voltage Von: Turn-on voltage WL: Word line Process: S400~S404

Claims

1. A memory array having a plurality of equalization circuits and N memory cells, wherein each of the plurality of equalization circuits is connected to the N memory cells via a plurality of bit line pairs, and N is a positive integer greater than 1, and the memory array, A refresh controller connected to the memory array, which sequentially refreshes the N memory cells with initial data according to an automatic refresh command, An initialization controller connected to the memory array and the refresh controller, configured to perform initialization operations in accordance with an initialization start command, Equipped with, During the initialization operation, the initialization controller enables the plurality of equalization circuits and periodically generates the automatic refresh command. Semiconductor memory device.

2. During the initialization operation, the initialization controller sets the initial value of K to 1, and each time the automatic refresh command is generated, the initialization controller simultaneously turns on multiple access transistors in memory cells from the Kth to the K+Jth among the N memory cells, and then K increases by J+1 until K becomes greater than N or the initialization controller receives an initialization completion command, where J is a positive integer greater than or equal to 1. The semiconductor memory device according to claim 1.

3. Each time the automatic refresh command is received, the refresh controller refreshes the initial data from memory cell K to memory cell K+J among the N memory cells. The semiconductor memory device according to claim 2.

4. Each of the plurality of bit line pairs includes a first bit line and a second bit line, and each of the plurality of equalization circuits receives an equalization signal from the initialization controller, and when the equalization signal is converted to an enable level, each of the plurality of equalization circuits uses an equalization voltage to control the voltage of the corresponding first bit line and the voltage of the corresponding second bit line. The semiconductor memory device according to claim 1.

5. The memory array further comprises a plurality of sense amplifier circuits, each of which is connected to the N memory cells via the plurality of bit line pairs. During the initialization operation, the initialization controller disables the plurality of sense amplifier circuits. The semiconductor memory device according to claim 1.

6. When the plurality of sense amplifier circuits sense the N memory cells, each of the plurality of sense amplifier circuits uses a first sensing control voltage and a second sensing control voltage to stabilize the voltage of the corresponding bit line pair. During the initialization operation, the initialization controller sets the first sensing control voltage and the second sensing control voltage to be equal to the ground voltage. The semiconductor memory device according to claim 5.

7. The initialization controller is A voltage divider and oscillator circuit configured to receive the initialization start command, start up in response to the initialization start command, and generate a clock signal, A counting and control circuit connected to the voltage divider and oscillation circuit, configured to receive the initialization start command and the clock signal, output a refresh start command in response to the initialization start command, count the clock signal and accumulate a first count value, and each time the first count accumulates up to a first predetermined number of times, reset the first count value to zero and output the automatic refresh command, A signal generation circuit connected to the counting and control circuit, configured to receive the refresh start command and the automatic refresh command, and in accordance with the refresh start command, to provide the equalization signal and equalization voltage used by each of the plurality of equalization circuits and the first sensing control voltage and second sensing control voltage used by each of the plurality of sense amplifier circuits during the initialization operation period, and in accordance with the automatic refresh command, to provide a turn-on voltage to the plurality of word lines corresponding to the plurality of memory cells to be refreshed. The semiconductor memory device according to claim 5, including the above.

8. The initialization controller is A refresh counter circuit is connected to the aforementioned voltage divider and oscillation circuit and the aforementioned counting and control circuit, and is configured to receive the clock signal, count the clock signal to accumulate a second count value, and output a refresh completion command to the counting and control circuit when the second count value has accumulated up to a second predetermined number of times, It further includes, The counting and control circuit stop outputting the automatic refresh command in response to the refresh completion command. The semiconductor memory device according to claim 7.

9. A method for initializing a semiconductor memory device, which includes a memory array having multiple equalization circuits and N memory cells, wherein N is a positive integer greater than 1. The process involves performing initialization operations according to the initialization start command, During the initialization operation, the process includes enabling the multiple equalization circuits and periodically generating automatic refresh commands, A step of sequentially refreshing the initial data in the N memory cells according to an automatic refresh command, A method for initializing a semiconductor memory device, including [the specified part of the code].

10. During the initialization operation, the initial value of K is set to 1, Each time the aforementioned automatic refresh command is generated, multiple access transistors in memory cells K through K+J within the N memory cells are simultaneously turned on, and then K increases by J+1 until K becomes greater than N or an initialization completion command is received, where J is a positive integer greater than or equal to 1. The initialization method according to claim 9, further comprising:

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