Semiconductor equipment

Abstract

To provide a semiconductor device that has reduced power consumption and enables non-destructive readout. [Solution] A semiconductor device having first to fourth transistors and first and second FTJ elements. Each of the first and second FTJ elements has an input terminal, a tunnel insulating film, a dielectric, and an output terminal. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor, the gate of the fourth transistor, and the output terminal of the first FTJ element. Also, one of the source or drain of the second transistor is electrically connected to one of the source or drain of the fourth transistor, the gate of the third transistor, and the output terminal of the second FTJ element.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integrations), such as CPUs (Central Processing Units) and memory, are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] Furthermore, development is underway on semiconductor devices that incorporate ferroelectric capacitors, FTJ (Ferroelectric Tunnel Junction, or Ferroelectric Transportation Junction) elements, FeFETs (Ferroelectric FETs), and other elements using ferroelectric dielectrics into the aforementioned semiconductor integrated circuits. For example, Patent Document 1 discloses a semiconductor memory cell having a transistor with a ferroelectric film on the gate insulating film on the back gate side. Also, for example, Patent Document 2 discloses a memory in which a ferroelectric capacitor is electrically connected to the gate of a transistor. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2009-164473 [Patent Document 2] Japanese Patent Publication No. 2003-178577 [Overview of the project] [Problems that the invention aims to solve]

[0006] In recent years, the amount of data handled in electronic devices and other devices has been increasing, and attempts are being made to miniaturize memory devices, especially memory cells, in order to increase storage capacity. When the size of a memory cell is reduced through miniaturization, its capacitance value decreases, making it difficult to retain data for long periods of time. In addition, the number of refresh operations required to retain data increases, which can lead to higher power consumption. Therefore, it is preferable for memory devices to use memory cells that can retain data for long periods of time.

[0007] In particular, when using DRAM (Dynamic Random Access Memory) as a storage device, reading data from a memory cell can corrupt the stored data (destructive readout), making data rewriting essential. Therefore, DRAM may require a circuit to write the data back after reading it. Also, because data rewriting is performed, power consumption may increase.

[0008] One aspect of the present invention aims to provide a semiconductor device that does not require data rewriting (a semiconductor device that performs non-destructive reading). Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced circuit area. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide an electronic device having any of the above-described semiconductor devices.

[0009] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first FTJ element, and a second FTJ element. Preferably, each of the first FTJ element and the second FTJ element has an input terminal, a tunnel insulating film, a dielectric, and an output terminal. Preferably, one of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor, the gate of the fourth transistor, and the output terminal of the first FTJ element, and preferably, one of the source or drain of the second transistor is electrically connected to one of the source or drain of the fourth transistor, the gate of the third transistor, and the output terminal of the second FTJ element.

[0011] (2) Alternatively, in one aspect of the present invention, in (1) above, the gate of the first transistor may be electrically connected to the gate of the second transistor.

[0012] (3) Alternatively, in one aspect of the present invention, in (1) or (2) above, the input terminal of the first FTJ element may be connected to the input terminal of the second FTJ element.

[0013] (4) Alternatively, in one aspect of the present invention, in any one of (1) to (3) above, the tunnel insulating film may have silicon oxide or silicon nitride, and the dielectric may have an oxide containing one or both of hafnium and zirconium.

[0014] (5) Alternatively, one aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor. Preferably, one of the sources or drains of the first transistor is electrically connected to one of the sources or drains of the third transistor, the gate of the fourth transistor, and the first terminal of the first ferroelectric capacitor, and one of the sources or drains of the second transistor is electrically connected to one of the sources or drains of the fourth transistor, the gate of the third transistor, and the first terminal of the second ferroelectric capacitor.

[0015] (6) Alternatively, in one aspect of the present invention, in (5) above, the gate of the first transistor may be electrically connected to the gate of the second transistor.

[0016] (7) Alternatively, in one aspect of the present invention, in (5) or (6) above, the second terminal of the first ferroelectric capacitor may be connected to the second terminal of the second ferroelectric capacitor.

[0017] (8) Alternatively, in one aspect of the present invention, in any one of (5) to (7) above, the first ferroelectric capacitor and the second ferroelectric capacitor each have a dielectric, and the dielectric may have an oxide containing one or both of hafnium and zirconium.

[0018] (9) Alternatively, one aspect of the present invention is an electronic device having any one of the semiconductor devices described in (1) to (8) above, and a housing.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices or may contain semiconductor devices.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0021] One example of a case where X and Y are electrically connected is that one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. A switch has the function of controlling on / off states. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0022] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, etc., operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0023] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0024] Furthermore, it can be expressed as, for example, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0026] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element having a resistance value higher than 0Ω, or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" may be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0027] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Also, the term "pair of electrodes" in relation to "capacitance" can be replaced with terms such as "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0028] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0029] For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate structure can reduce off-current, improve the breakdown voltage of the transistor, and improve reliability. Alternatively, a multi-gate structure can be used to obtain a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes when operating in the saturation region. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0030] Furthermore, even if a single circuit element is depicted in a circuit diagram, that element may actually comprise multiple circuit elements. For example, if one resistor is shown in a circuit diagram, it includes cases where two or more resistors are electrically connected in series. Similarly, if one capacitor is shown in a circuit diagram, it includes cases where two or more capacitors are electrically connected in parallel. Similarly, if one transistor is shown in a circuit diagram, it includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Likewise, if one switch is shown in a circuit diagram, it includes cases where the switch has two or more transistors, and these two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0031] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration and device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0032] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0033] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0034] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., is the direction in which positively charged carriers move and is expressed as a positive current quantity. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, descriptions such as "current is input to element A" can be rephrased as "current is output from element A."

[0035] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0037] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0038] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0039] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" and "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," and "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0040] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0041] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (however, oxygen and hydrogen are not included).

[0042] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Therefore, a switch may have two or more terminals for conducting current in addition to control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where, for example, the source and drain electrodes of the transistor can be considered electrically short-circuited, or a state where current can flow between the source and drain electrodes. Conversely, the "non-conducting state" of the transistor refers to a state where the source and drain electrodes of the transistor can be considered electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0045] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one aspect of the present invention, a semiconductor device that does not require data rewriting (a semiconductor device that performs non-destructive reading) can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced circuit area can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, an electronic device having any of the above-described semiconductor devices can be provided.

[0047] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0048] [Figure 1] Figures 1A and 1B are circuit diagrams showing examples of memory cell configurations related to semiconductor devices. [Figure 2] Figure 2 is a timing chart illustrating an example of memory cell operation in a semiconductor device. [Figure 3] Figure 3 is a timing chart illustrating an example of the operation of a memory cell in a semiconductor device. [Figure 4] Figures 4A to 4C are circuit diagrams showing examples of memory cell configurations related to semiconductor devices. [Figure 5] Figures 5A and 5B are circuit diagrams showing examples of memory cell configurations related to semiconductor devices. [Figure 6] Figure 6 is a circuit diagram showing an example of the configuration of a memory cell related to a semiconductor device. [Figure 7]Figure 7 is a timing chart illustrating an example of the operation of a memory cell related to a semiconductor device. [Figure 8] Figure 8 is a block diagram showing an example of a storage device configuration. [Figure 9] Figure 9 is a timing chart illustrating an example of memory device operation. [Figure 10] Figure 10 is a timing chart illustrating an example of memory device operation. [Figure 11] Figure 11 is a timing chart illustrating an example of memory device operation. [Figure 12] Figure 12 is a timing chart illustrating an example of memory device operation. [Figure 13] Figure 13 is a timing chart illustrating an example of memory device operation. [Figure 14] Figure 14 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 15] Figure 15 is a block diagram showing an example of the configuration of an arithmetic circuit. [Figure 16] Figure 16 is a circuit diagram showing an example of the configuration of the circuits included in the arithmetic circuit. [Figure 17] Figure 17 is a block diagram showing an example of a storage device configuration. [Figure 18] Figure 18 is a timing chart illustrating an example of memory device operation. [Figure 19] Figure 19 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 20] Figures 20A to 20C are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 21] Figure 21 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 22] Figures 22A and 22B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 23] Figure 23 is a schematic cross-sectional diagram showing an example of a transistor configuration. [Figure 24] Figure 24 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 25]Figure 25 is a schematic cross-sectional diagram showing an example of a transistor configuration. [Figure 26] Figure 26 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 27] Figure 27A illustrates the classification of IGZO crystal structures, Figure 27B illustrates the XRD spectrum of crystalline IGZO, and Figure 27C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 28] Figure 28A is a perspective view showing an example of a semiconductor wafer, Figure 28B is a perspective view showing an example of a chip, and Figures 28C and 28D are perspective views showing examples of electronic components. [Figure 29] Figure 29 is a block diagram illustrating the CPU. [Figure 30] Figures 30A to 30I are perspective views or schematic diagrams illustrating an example of a product. [Figure 31] Figure 31 shows the current density-voltage characteristics of the FTJ element. [Modes for carrying out the invention]

[0049] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, if a metal oxide is included in the channel formation region of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, that metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0050] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0051] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0052] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0053] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0054] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0055] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0056] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0057] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0058] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0059] <Configuration Example 1> Figure 1A shows an example of the circuit configuration of a memory cell MC provided in a memory device, which is a semiconductor device according to one aspect of the present invention.

[0060] The memory cell MC includes transistor M1, transistor M1b, transistor M6, transistor M6b, FTJ element FJA, and FTJ element FJAb.

[0061] FTJ elements FJA and FJAb are tunnel junction elements comprising a pair of electrodes, a material capable of ferroelectricity, and an insulator that functions as a tunnel insulating film. Furthermore, the FTJ element has the function of changing its resistance value depending on the direction and intensity of polarization of the material capable of ferroelectricity.

[0062] The insulator is provided so as to be superimposed on a material that may have ferroelectric properties, and the insulator and the material that may have ferroelectric properties are provided between the pair of electrodes. Furthermore, the FTJ element has rectifying characteristics because the insulator, which functions as a tunnel insulating film, is provided so as to be superimposed on a material that may have ferroelectric properties. For example, when the FTJ element is configured such that one of the pair of electrodes, an insulator that functions as a tunnel insulating film, a material that may have ferroelectric properties, and the other of the pair of electrodes are stacked in that order, the forward direction of current flow in the FTJ element is from one of the pair of electrodes to the other of the pair of electrodes. In this specification, one of the pair of electrodes is described as the input terminal, and the other of the pair of electrodes is described as the output terminal.

[0063] For example, the FTJ element described herein can be formed by laminating a first conductor, a tunnel insulating film, a ferroelectric material, and a second conductor on a flat insulating film or conductive film in that order. The first conductor can be referred to as the lower electrode, and the second conductor can be referred to as the upper electrode. In this case, the first conductor and the second conductor are the pair of electrodes described above, and the first conductor (lower electrode) functions as an input terminal, for example, and the second conductor (upper electrode) functions as an output terminal, for example. Alternatively, the FTJ element described herein may be formed by laminating a first conductor (lower electrode), a ferroelectric material, a tunnel insulating film, and a second conductor (upper electrode) on a flat insulating film or conductive film in that order. In this case, the first conductor (lower electrode) functions as an output terminal, for example, and the second conductor (upper electrode) functions as an input terminal, for example.

[0064] Furthermore, as the tunnel insulating film, for example, silicon oxide, silicon nitride, or a laminate of silicon oxide and silicon nitride can be used.

[0065] As mentioned above, the resistance of an FTJ element changes depending on the direction and intensity of polarization of the ferroelectric material. For example, when the polarization direction of the ferroelectric material between the input and output terminals of an FTJ element is from the output terminal to the input terminal (in this case, the direction of the polarization vector is negative), the amount of current flowing from the input terminal to the output terminal in the FTJ element becomes large. On the other hand, when the polarization direction of the ferroelectric material between the input and output terminals of an FTJ element is from the input terminal to the output terminal (in this case, the direction of the polarization vector is positive), the amount of current flowing from the input terminal to the output terminal in the FTJ element becomes small. In other words, when the polarization direction of an FTJ element is from the input terminal to the output terminal, the resistance to the current flowing from the input terminal to the output terminal of the FTJ element becomes large, and when the polarization direction of an FTJ element is from the output terminal to the input terminal, the resistance to the current flowing from the input terminal to the output terminal of the FTJ element becomes small.

[0066] One way to induce polarization (change the direction of polarization) in a ferroelectric material of an FTJ element is to apply a high voltage between the input and output terminals of the FTJ element. For example, by applying a high-level potential to the input terminal side and a low-level potential to the output terminal side of the FTJ element, the polarization direction in the ferroelectric material of the FTJ element will be from the input terminal to the output terminal (positive direction). On the other hand, by applying a low-level potential to the input terminal side and a high-level potential to the output terminal side of the FTJ element, the polarization direction will be from the output terminal to the input terminal (negative direction). Note that FTJ elements exhibit hysteresis in terms of polarization intensity, so in order to induce polarization (change the direction of polarization), it is necessary to apply a voltage appropriate to the structure of the FTJ element. At voltages lower than this, polarization will not occur in the FTJ element (the direction of polarization will not change).

[0067] In the drawings of this specification, the FTJ element is represented by adding an arrow to the circuit symbol of a diode. Furthermore, in the drawings of this specification, the side of the triangle corresponding to the anode of the circuit symbol of the diode connected to the wiring is the input terminal of the FTJ element, and the vertex and line of the triangle corresponding to the cathode of the circuit symbol of the diode connected to the wiring are the output terminal of the FTJ element.

[0068] Furthermore, as a material that can possess ferroelectric properties, it is preferable to use, for example, hafnium oxide. When hafnium oxide is used as the material that can possess ferroelectric properties in the FTJ element, the thickness of the hafnium oxide film (or the distance between the pair of electrodes of the FTJ element) is preferably 10 nm or less, more preferably 5 nm or less, and even more preferably 2 nm or less.

[0069] Alternatively, materials that may possess ferroelectric properties include, in addition to hafnium oxide, zirconium oxide and zirconium hafnium oxide (HfZrO). XExamples include metal oxides such as (where X is a real number greater than 0), or sometimes written as HZO. Alternatively, materials that may possess ferroelectric properties include materials obtained by adding element J1 (where element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide. The ratio of hafnium atoms to element J1 atoms can be set as appropriate; for example, the ratio of hafnium atoms to element J1 atoms can be set to 1:1 or close to it. Note that close to it means a range of ±30% of the desired atomic ratio. Alternatively, materials that may possess ferroelectric properties include materials obtained by adding element J2 (where element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide. The ratio of zirconium atoms to element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. Another material that may possess ferroelectric properties is lead titanate (PbTiO2). X ), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate may also be used.

[0070] Furthermore, aluminum scandium nitride (Al) is an example of a material that may possess ferroelectric properties. 1-a Sc a N bExamples include Al-Ga-Sc nitrides and Ga-Sc nitrides (where a is a real number greater than 0 and less than 0.5, and b is 1 or a value in its vicinity). Furthermore, metal nitrides containing element M1, element M2, and nitrogen are examples of materials that may possess ferroelectric properties. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectric properties even without containing element M2. Another example of a material that may exhibit ferroelectric properties is a metal nitride to which element M3 is added. Element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, element M2, and element M3 can be set as appropriate. Since the above metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element, it may be referred to as a group III-V ferroelectric or a group III nitride ferroelectric.

[0071] Furthermore, materials that may possess ferroelectric properties include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0072] Furthermore, a material that may possess ferroelectricity can be, for example, a mixture or compound consisting of multiple materials selected from the materials listed above. Alternatively, a material that may possess ferroelectricity can be a laminated structure consisting of multiple materials selected from the materials listed above. Incidentally, the crystal structure and electrical properties of the materials listed above may change not only depending on the film deposition conditions but also on various processes, so in this specification, the materials mentioned above are not only called ferroelectrics but also called materials that may possess ferroelectricity. Furthermore, ferroelectrics include not only materials that exhibit ferroelectricity but also materials that may possess ferroelectricity.

[0073] Among the materials that can possess ferroelectric properties, hafnium oxide, or materials containing both hafnium oxide and zirconium oxide, are preferred because they can exhibit ferroelectric properties even when processed into thin films of a few nanometers. Here, the film thickness of the ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, a film thickness of 8 nm to 12 nm is preferred. By creating a thin ferroelectric layer, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, a layer of ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0074] Furthermore, HfZrO is a material that can possess ferroelectric properties. XWhen using this method, it is preferable to form a film by using the atomic layer deposition (ALD) method, particularly the thermal ALD method. Further, when forming a film of a material that may have ferroelectricity using the thermal ALD method, it is suitable to use a material that does not contain a hydrocarbon (also referred to as HC) as a precursor. When either one or both of hydrogen and carbon are contained in a material that may have ferroelectricity, it may inhibit the crystallization of the material that may have ferroelectricity. Therefore, as described above, by using a precursor that does not contain a hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that may have ferroelectricity. For example, a chlorine-based material can be given as a precursor that does not contain a hydrocarbon. In addition, as a material that may have ferroelectricity, a material having hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as a precursor.

[0075] In addition, when forming a film using a material that may have ferroelectricity, by thoroughly removing impurities in the film, here at least one or more of hydrogen, hydrocarbon, and carbon, a film having high-purity genuine ferroelectricity can be formed. Note that the film having high-purity genuine ferroelectricity and the high-purity genuine oxide semiconductor shown in the embodiments described later have very high manufacturing process compatibility. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0076] In addition, when using HfZrO as a material that may have ferroelectricity X it is preferable to alternately form hafnium oxide and zirconium oxide in a composition ratio of 1:1 by using the thermal ALD method.

[0077] In addition, when forming a film of a material that may have ferroelectricity using the thermal ALD method, H2O or O3 can be used as an oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0078] Furthermore, the crystal structure of a material that may possess ferroelectricity is not particularly limited. For example, the crystal structure of a material that may possess ferroelectricity may be one crystal structure selected from cubic, tetragonal, orthorhombic, and monoclinic systems, or a composite structure having multiple such crystal structures. In particular, a material that may possess ferroelectricity is preferred if it has an orthorhombic crystal structure, as this is because ferroelectricity is exhibited in such a case. Alternatively, a material that may possess ferroelectricity may have a composite structure having both an amorphous structure and a crystalline structure.

[0079] For example, an OS transistor can be used as each of the transistors M1, M1b, M6, and M6b. Furthermore, it is more preferable that the metal oxide included in the channel formation region of the OS transistor contains an oxide that includes at least one of indium, gallium, and zinc. Alternatively, the metal oxide may be an oxide that includes at least one of indium, element M (for example, one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. Furthermore, it is preferable that the transistors M1, M1b, M6, and M6b have the transistor structure described in Embodiment 5.

[0080] Furthermore, for transistors M1, M1b, M6, and M6b, in addition to OS transistors, transistors in which silicon is included in the channel formation region (hereinafter referred to as Si transistors) may be used. The silicon may also be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon.

[0081] Furthermore, for transistors M1, M1b, M6, and M6b, in addition to OS transistors and Si transistors, transistors containing Ge or similar materials in the channel formation region, transistors containing compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe in the channel formation region, transistors containing carbon nanotubes in the channel formation region, and transistors containing organic semiconductors in the channel formation region may also be used.

[0082] The channel-forming regions of transistors M1, M1b, M6, and M6b may contain the same material or different materials. For example, some of transistors M1, M1b, M6, and M6b may be OS transistors and the rest may be Si transistors.

[0083] Furthermore, the transistors M1, M1b, M6, and M6b shown in Figure 1A are, for example, transistors with a structure having gates above and below the channel, and each of transistors M1, M1b, M6, and M6b has a first gate and a second gate. For convenience, for example, the first gate is described as the gate (sometimes referred to as the front gate) and the second gate as the back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" can be replaced with the term "back gate". Similarly, the term "back gate" can be replaced with the term "gate". As a specific example, the connection configuration "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0084] Furthermore, the memory cell MC according to one embodiment of the present invention does not depend on the connection configuration of the transistor's back gate. Transistors M1, M1b, M6, and M6b shown in Figure 1A have back gates, and although the connection configuration of the back gate is not shown, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor M1 may be electrically connected. Also, for example, in a transistor having a back gate, wiring electrically connected to an external circuit may be provided to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, and a fixed potential or variable potential may be applied to the back gate of the transistor by the external circuit. This also applies to transistors described in other parts of the specification or other drawings, not just in Figure 1A.

[0085] Furthermore, the memory cell MC according to one embodiment of the present invention does not depend on the structure of the transistors included in the memory cell MC. For example, transistors M1, M1b, M6, and M6b shown in Figure 1A may each be configured without a back gate, as shown in Figure 1B, i.e., single-gate transistors. Alternatively, some transistors may have a back gate configuration, while others may not. This also applies to transistors described in other parts of the specification or illustrated in other drawings, not just in Figure 1A.

[0086] Furthermore, while the transistors M1, M1b, M6, and M6b shown in Figure 1A are shown as n-channel transistors as an example, they may all or part be replaced with p-channel transistors depending on the situation or circumstances. When n-channel transistors are replaced with p-channel transistors, it is necessary to appropriately change the potential input to the memory cell MC, etc., so that the memory cell MC operates correctly. The output from the memory cell MC may also change. This also applies to transistors described elsewhere in the specification or in other drawings, not just in Figure 1A. In this embodiment, the configuration and operation of the memory cell MC will be described assuming that transistors M1, M1b, M6, and M6b are n-channel transistors.

[0087] In the memory cell MC of Figure 1A, the first terminal of transistor M1 is electrically connected to wiring WRDL, and the gate of transistor M1 is electrically connected to wiring WRWL. The input terminal of FTJ element FJA is electrically connected to wiring FCA. The output terminal of FTJ element FJA is electrically connected to the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. The second terminal of transistor M6 is electrically connected to wiring FCB. The first terminal of transistor M1b is electrically connected to wiring WRDLb, and the gate of transistor M1b is electrically connected to wiring WRWL. The input terminal of FTJ element FJAb is electrically connected to wiring FCA. The output terminal of FTJ element FJAb is electrically connected to the second terminal of transistor M1b, the first terminal of transistor M6b, and the gate of transistor M6. The second terminal of transistor M6b is electrically connected to wiring FCB.

[0088] Wiring WRDL functions, for example, as wiring to transmit data written to the memory cell MC. Wiring WRDL also functions as wiring to transmit data read from the memory cell MC. In other words, wiring WRDL may function as both a write data line and a read data line. Similarly, wiring WRDLb functions, for example, as wiring to transmit data written to the memory cell MC. Wiring WRDLb also functions as wiring to transmit data read from the memory cell MC. In other words, wiring WRDLb may also function as both a write data line and a read data line.

[0089] The wiring WRWL can function, for example, as a wiring to select the memory cell MC to which data will be written. It can also function, for example, as a wiring to select the memory cell MC from which data will be read. In other words, the wiring WRWL may function as both a write word line and a read word line.

[0090] For example, the FCA wiring functions as a wiring that provides a variable potential sufficient to cause polarization in the ferroelectric material (dielectric) contained in the FTJ element FJA and FTJ element FJAb when writing data to the memory cell MC. Also, for example, the FCA wiring functions as a wiring that provides a potential that does not change the polarization of the said material (dielectric) when reading data from the memory cell MC.

[0091] By the way, a detailed example of operation will be described later, but the operation of the memory cell MC involves applying a voltage to the wiring FCA and applying that voltage to the input terminals of the FTJ element FJA and FTJ element FJAb. At this time, tunnel current may flow through each of the FTJ elements FJA and FTJ element FJAb. In this case, if it is desired to prevent leakage of tunnel current through transistor M1, it is preferable to use an OS transistor as transistor M1 and / or transistor M1b. Because the OS transistor has a very low off current, it can prevent leakage of tunnel current flowing through the FTJ element FJA and / or FTJ element FJAb to the wiring WRDL side.

[0092] <Example of operation> Next, we will explain examples of data writing and data reading operations in the memory cell MC shown in Figure 1A.

[0093] <<Example of data writing operation>> Figure 2 is a timing chart showing an example of data writing operation in the memory cell MC of Figure 1A. The timing chart in Figure 2 shows the changes in potential of wiring WRWL, wiring WRDL, wiring WRDLb, wiring FCA, and wiring FCB between time T11 and time T17, and in the vicinity of that time.

[0094] [From time T11 to time T12] Between time T11 and time T12, the potentials of wiring WRWL and wiring WRDL are at a low level (labeled "Low" in Figure 2). Therefore, a low level potential is input to the gates of transistors M1 and M1b. Consequently, transistors M1 and M1b are both in the OFF state.

[0095] Furthermore, no data has yet been entered into wiring WRDL and wiring WRDLb for writing to the memory cell MC. Therefore, in this example, between time T11 and time T12, the potentials of wiring WRDL and wiring WRDLb are set to, for example, the ground potential (labeled GND in Figure 2). In this example, it is preferable that the ground potential be 0V.

[0096] Furthermore, the potential supplied by wiring FCA and wiring FCB is V 0A , V 0B Let's assume that. V 0A , and V 0B This can be, for example, the reference potential or a value near the reference potential. Also, the reference potential V C For example, it is preferable to set the reference potential to 0[V] or the ground potential. As a value near the reference potential, for example, the reference potential is V C When V C -0.1[V] or more, V C -0.05[V] or higher, or V C It is preferable that the potential is -0.01[V] or higher, and V C +0.01[V] or less, V C +0.05[V] or less, or V C It is preferable that it be +0.1[V] or less. The lower and upper limits mentioned above can be combined. Also, V 0A , and V 0B It is even more preferable that they be at the same potential.

[0097] [From time T12 to time T13] Between time T12 and time T13, the potential supplied by the wiring WRWL changes from a low level potential to a high level potential (labeled "High" in Figure 2). As a result, a high level potential is input to the gates of transistors M1 and M1b, causing both transistors M1 and M1b to turn on. In other words, there is conduction between the wiring WRDL and the gate of transistor M6b and the first terminal of transistor M6 (the output terminal of FTJ element FJA), and there is conduction between the wiring WRDLb and the gate of transistor M6 and the first terminal of transistor M6b (the output terminal of FTJ element FJAb). Therefore, the gate of transistor M6b (the output terminal of FTJ element FJA) is supplied with the ground potential supplied by the wiring WRDL. As a result, the potential of the gate of transistor M6 (the output terminal of FTJ element FJA) is assumed to be the ground potential. Also, the gate of transistor M6 (the output terminal of FTJ element FJAb) is supplied with the ground potential supplied by the wiring WRDLb. Therefore, the potential of the gate of transistor M6 (the output terminal of FTJ element FJAb) is assumed to be at ground potential.

[0098] [From time T13 to time T14] Between time T13 and time T14, data for writing to the memory cell MC is transmitted from wiring WRDL and wiring WRDLb to the memory cell MC. Specifically, for example, wiring WRDL is given either V0 or V1 as a potential corresponding to the data, and wiring WRDLb is given either V0 or V1 as a potential corresponding to the data. Since transistors M1 and M1b have been ON since before time T13, the gate of transistor M6b (output terminal of FTJ element FJA) is given either V0 or V1 as a potential from wiring WRDL, and the gate of transistor M6 (output terminal of FTJ element FJAb) is given either V0 or V1 as a potential from wiring WRDLb.

[0099] Note that V0 and V1 are potentials that represent binary data (digital values). For example, when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V0, the memory cell MC holds either "0" or "1" as data, or when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V1, the memory cell MC holds the other of "0" or "1" as data. In this example of operation, as an example, it will be explained that when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V0, the memory cell MC holds "0" as data, or when the potential of the output terminal of the FTJ element FJA of the memory cell MC is V1, the memory cell MC holds "1" as data. Furthermore, the magnitudes of V0 and V1 can be set such that V1-V0 is a voltage that causes polarization of the FTJ element FJA and the FTJ element FJAb, respectively, or rewrites the direction of polarization. For example, if the voltage required to generate polarization (change the direction of polarization) in each of the FTJ elements FJA and FJAb is 3V, then V1 and V0 should be set so that V1-V0 is 3V or greater. Note that V0 is, for example, V 0A , and / or V 0B It is preferable that the potential is equal to that of V0. Specifically, V0 can be set to 0V as an example, and V1 to 3V as an example. Although this operation example describes the writing of binary data, memory cell MCs may be able to write multi-level data or analog potentials, for example.

[0100] Furthermore, after data for writing to the memory cell MC is transmitted from wiring WRDL and wiring WRDLb to the memory cell MC, the wiring FCA has a potential V 1A Given, the wiring FCB has a potential V 0B V is given. 1A For example, V 0A Assume that the potential is higher than V. 1AThis is set to a potential such that polarization occurs (the direction of polarization changes) in the FTJ element FJA when the output terminal of the FTJ element FJA is V0. In this case, the direction of the polarization is from the input terminal to the output terminal of the FTJ element FJA (positive direction). Similarly, V 1A This is assumed to be a potential such that polarization occurs (the direction of polarization changes) in the FTJ element FJAb when the output terminal of the FTJ element FJAb is V0. In this case, the direction of the polarization is from the input terminal to the output terminal of the FTJ element FJAb (positive direction).

[0101] Note that in this example, V 1A For example, it is preferable that this is equal to the potential of V1.

[0102] First, let's focus on the FTJ element FJA. When the potential at the output terminal of FTJ element FJA (the gate of transistor M6b) is V0, the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction). On the other hand, when the potential at the output terminal of FTJ element FJA (the gate of transistor M6b) is V1, the polarization in the ferroelectric dielectric contained in FTJ element FJA does not change.

[0103] Next, let's focus on the FTJ element FJAb. When the potential at the input terminal of the FTJ element FJAb (the gate of transistor M6) is V0, the polarization in the ferroelectric dielectric contained in the FTJ element FJAb does not change. On the other hand, when the potential at the input terminal of the FTJ element FJAb (the gate of transistor M6) is V1, the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction).

[0104] [From time T14 to time T15] Between time T14 and time T15, the potential V is present in wiring FCA. 0A Given, the wiring FCB continues to have a potential V 0B It is given.

[0105] First, let's focus on the FTJ element FJA. When the potential at the output terminal of the FTJ element FJA (the gate of transistor M6b) is V0, the direction of polarization in the ferroelectric dielectric contained in the FTJ element FJA does not change. On the other hand, when the potential at the output terminal of the FTJ element FJA (the gate of transistor M6b) is V1, the ferroelectric dielectric contained in the FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction).

[0106] Next, let's focus on the FTJ element FJAb. When the potential at the input terminal of the FTJ element FJAb (the gate of transistor M6) is V0, the ferroelectric dielectric contained in the FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). On the other hand, when the potential at the input terminal of the FTJ element FJAb (the gate of transistor M6) is V1, the direction of polarization in the ferroelectric dielectric contained in the FTJ element FJAb does not change.

[0107] Between time T13 and time T15, the potentials of wiring FCA and wiring FCB change as shown in the timing chart in Figure 2. Depending on the potential supplied from wiring WRDL and wiring WRDLb to the memory cell MC, the polarization direction of FTJ elements FJA and FTJ elements FJAb is determined as shown in the following table.

[0108] [Table 1]

[0109] Furthermore, from time T15 onward, the potentials supplied by wiring FCA and wiring FCB are V, respectively. 0A , V 0B Therefore, the potential supplied by wiring FCA and wiring FCB from time T15 onward is the same as the potential supplied by wiring FCA and wiring FCB before time T13.

[0110] [From time T15 to time T16] Between time T15 and time T16, the transmission of data from wiring WRDL and wiring WRDLb to memory cell MC is completed. Specifically, for example, wiring WRDL and wiring WRDLb are assumed to be supplied with ground potential. Transistor M1 has been in the ON state since before time T15, so the gate of transistor M6b (output terminal of FTJ element FJA) is supplied with ground potential from wiring WRDL. On the other hand, transistor M1b has also been in the ON state since before time T15, so the gate of transistor M6 (output terminal of FTJ element FJAb) is supplied with ground potential from wiring WRDLb.

[0111] Even if the potentials of the gates of transistor M6b (output terminal of FTJ element FJA) and transistor M6 (output terminal of FTJ element FJAb) become ground potential, the potential of wiring FCA remains V 0A Therefore, the polarization directions of FTJ element FJA and FTJ element FJAb, which were written between time T14 and time T16, do not change.

[0112] [From time T16 to time T17] Between time T16 and time T17, the potential of the wiring WRWL changes from a high-level potential to a low-level potential. As a result, a low-level potential is input to the gates of transistors M1 and M1b, causing both transistors M1 and M1b to turn off.

[0113] The operation described above, from time T11 to time T17, allows data to be written to the memory cell MC in Figure 1A.

[0114] <<Example of data retrieval operation>> Figure 3 is a timing chart showing an example of the data read operation in the memory cell MC of Figure 1A. The timing chart in Figure 3 shows the changes in the potentials of wiring WRWL, wiring WRDL, wiring WRDLb, wiring FCA, and wiring FCB between time T21 and time T27, and in the vicinity of that time.

[0115] [From time T21 to time T22] Between time T21 and time T22, the potential of the wiring WRWL is at a low level (labeled "Low" in Figure 3). Therefore, a low level potential is input to the gates of transistors M1 and M1b. Consequently, both transistors M1 and M1b are in the off state.

[0116] Furthermore, between time T21 and time T22, the potentials of wiring WRDL and wiring WRDLb are at ground potential (labeled GND in Figure 3).

[0117] Furthermore, between time T21 and time T22, the potentials provided by wiring FCA and wiring FCB are the same as the potentials provided by wiring FCA and wiring FCB between time T11 and time T12, V 0A , V 0B Let's assume that.

[0118] [From time T22 to time T23] Between time T22 and time T23, the potential V is applied to both wiring WRDL and wiring WRDLb, as an example. MD It is precharged. MD V 0B Higher than V (described later) M The potential is set to be lower than that.

[0119] [From time T23 to time T24] Between time T23 and time T24, the potential V is present in wiring FCA. M Given, the wiring FCB has a potential V 0B V is given. M V 0A and V 0B Higher than V 1A The potential should be lower than V. Also, the potential of the wiring FCB should be V 0B When V MThe potential is set such that no change in polarization occurs (the direction of polarization does not change) in FTJ element FJA and FTJ element FJAb.

[0120] First, consider the case where the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). In this case, the resistance to the current flowing from the input terminal to the output terminal of FTJ element FJA becomes high, while the resistance to the current flowing from the input terminal to the output terminal of FTJ element FJAb becomes low. Therefore, the potential at the output terminal of FTJ element FJAb is the potential V provided by the wiring FCA. M It becomes close to that. Also, the gate of transistor M6 has a potential V M Potential close to (V) 0B Since a higher potential (V) is applied, transistor M6 turns on, and the potential at the output terminal of FTJ element FJA becomes the potential V provided by wiring FCB. 0B It becomes close to that. Also, the gate of transistor M6b has a potential V 0B As a potential close to this is applied, transistor M6b turns off. Consequently, the potential at the output terminal of FTJ element FJAb becomes the potential V applied by wiring FCA. M It becomes closer.

[0121] Next, consider the case where the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction). In this case, the resistance of FTJ element FJAb to the current flowing from the input terminal to the output terminal becomes high, while the resistance of FTJ element FJA to the current flowing from the input terminal to the output terminal becomes low. Therefore, the potential at the output terminal of FTJ element FJA is the potential V provided by the wiring FCA. M It becomes close to that. Also, the gate of transistor M6b has a potential V M Potential close to (V) 0BSince a higher potential (V) is applied, transistor M6b turns on, and the potential at the output terminal of FTJ element FJAb becomes the potential V provided by the wiring FCB. 0B It becomes close to that. Also, the gate of transistor M6 has a potential V 0B As a potential close to this is applied, transistor M6 turns off. As a result, the potential at the output terminal of FTJ element FJA becomes the potential V applied by wiring FCA. M It becomes closer.

[0122] In this example, if, between time T23 and time T24, the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction), then for convenience, the potential of the output terminal of FTJ element FJA is V 0B Therefore, the potential at the output terminal of the FTJ element FJAb is V M It shall be assumed that the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction), then for convenience, the potential of the output terminal of FTJ element FJA is V M Therefore, the potential at the output terminal of the FTJ element FJAb is V 0B This shall be the case.

[0123] [From time T24 to time T25] Between time T24 and time T25, the potential supplied by the wiring WRWL changes from a low level potential to a high level potential (labeled High in Figure 3). As a result, a high level potential is input to the gates of transistors M1 and M1b, causing both transistors M1 and M1b to turn on.

[0124] First, consider the case where the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction). In this case, the potential at the output terminal of FTJ element FJA is V 0B Therefore, the potential at the output terminal of the FTJ element FJAb is V M As a result, the charge pre-charged in wiring WRDL flows to wiring FCB via transistors M1 and M6, and the potential of wiring WRDL is V MD The voltage is reduced from there. Also, since charge flows from wiring FCA to wiring WRDLb via FTJ element FJAb and transistor M1b, the potential of wiring WRDLb is V MD The voltage is boosted from there. At this time, the potential of the wiring WRDL is V 0R Therefore, the potential of wiring WRDLB is V MR This shall be the case.

[0125] Note V 0R For example, V 0B It is preferable that V MR For example, V M It is preferable that this be the case.

[0126] Next, consider the case where the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction). In this case, the potential at the output terminal of FTJ element FJA is V M Therefore, the potential at the output terminal of the FTJ element FJAb is V 0B As a result, the charge pre-charged in wiring WRDLb flows to wiring FCB via transistors M1b and M6b, and the potential of wiring WRDLb is V MD The voltage is stepped down from there. Also, since charge flows from wiring FCA to wiring WRDL via FTJ element FJA and transistor M1, the potential of wiring WRDL is V MDThe voltage is boosted from there. At this time, the potential of the wiring WRDL is V M Therefore, the potential of wiring WRDLB is V 0R This shall be the case.

[0127] Here, by reading the potentials of wiring WRDL and wiring WRDLb, the data held in the memory cell MC can be read. For example, if the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the input terminal to the output terminal (positive direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the output terminal to the input terminal (negative direction), the data "0" written to the memory cell MC can be read by reading the potentials of wiring WRDL and wiring WRDLb. Also, for example, if the ferroelectric dielectric contained in FTJ element FJA is polarized in the direction from the output terminal to the input terminal (negative direction), and the ferroelectric dielectric contained in FTJ element FJAb is polarized in the direction from the input terminal to the output terminal (positive direction), the data "0" written to the memory cell MC can be read by reading the potentials of wiring WRDL and wiring WRDLb.

[0128] Furthermore, when reading the potentials of wiring WRDL and wiring WRDLb, a sense amplifier or similar device can be used.

[0129] Furthermore, from time T25 onward, the potentials supplied by wiring FCA and wiring FCB are V, respectively. 0A , V 0B Therefore, the potential supplied by wiring FCA and wiring FCB from time T25 onward is the same as the potential supplied by wiring FCA and wiring FCB before time T23.

[0130] [From time T25 to time T26] Between time T25 and time T26, ground potential is input to both wiring WRDL and wiring WRDLb. Meanwhile, since transistor M1 has been ON since before time T25, the gate of transistor M6b (the output terminal of FTJ element FJA) is supplied with ground potential from wiring WRDL. On the other hand, since transistor M1b has also been ON since before time T125, the gate of transistor M6 (the output terminal of FTJ element FJAb) is supplied with ground potential from wiring WRDLb.

[0131] Even if the potentials of the gates of transistor M6b (output terminal of FTJ element FJA) and transistor M6 (output terminal of FTJ element FJAb) become ground potential, the potential of wiring FCA remains V 0A Therefore, the polarization directions of FTJ element FJA and FTJ element FJAb do not change.

[0132] [From time T26 to time T27] Between time T26 and time T27, the potential of the wiring WRWL changes from a high-level potential to a low-level potential. As a result, a low-level potential is input to the gates of transistors M1 and M1b, causing both transistors M1 and M1b to turn off.

[0133] The operation example described above, between time T21 and time T27, allows for the reading of data written to the memory cell MC in Figure 1A. Furthermore, when data is read from the memory cell MC in Figure 1A, the polarization directions of the FTJ element FJA and FTJ element FJAb do not change; therefore, the data reading operation example described above does not result in destructive reading. In other words, the data written to the memory cell MC can be read from the memory cell MC while retaining its original state.

[0134] In the read operation example of the timing chart in FIG. 3, a method of reading data from the memory cell MC that does not result in destructive readout was described. However, the data readout from the memory cell MC in FIG. 1 may be destructive readout. In this case, as the potential input to the wiring FCA between time T23 and time T24, for example, V 1A is preferably used. Further, as the read circuit electrically connected to the wiring WRDL and the wiring WRDLb, an integration circuit (QV circuit) is preferably used.

[0135] Note that the operations of the timing charts in FIGS. 2 and 3 described in this embodiment are merely examples, and the operations can be changed according to the situation or case. For example, between time T12 and time T16 of the timing chart in FIG. 2, a high-level potential is applied to the wiring WRWL, between time T13 and time T15, one of V0 and V1 is applied to the wiring WRDL, and the other of V0 and V1 is applied to the wiring WRDLb. However, during the period in which one of V0 and V1 is applied to the wiring WRDL and the other of V0 and V1 is applied to the wiring WRDLb, a high-level potential may be applied to the wiring WRWL. Also, during the period in which the potential V 1A is applied to the wiring FCA and the potential V 0B is applied to the wiring FCB, and during the period in which the potential V 0A is applied to the wiring FCA and the potential V 0B is applied to the wiring FCB, as long as it is within the period in which a high-level potential is applied to the wiring WRWL, one of V0 and V1 is applied to the wiring WRDL, and the other of V0 and V1 is applied to the wiring WRDLb, it may be performed at any timing. Also, during the period in which the potential V 0A is applied to the wiring FCA and the potential V 0B is applied to the wiring FCB between time T14 and time T15, the period in which the potential V 1A is applied to the wiring FCA and the potential V 0B is applied to the wiring FCB between time T13 and time T14 may be performed earlier.

[0136] <Configuration Example 2> A memory cell MC provided in a memory device, which is a semiconductor device according to one aspect of the present invention, is not limited to the circuit configuration shown in Figure 1A. The circuit configuration of the memory cell MC provided in the memory device may be changed depending on the circumstances. In this example configuration, a memory cell MC is described in which one of the FTJ elements FJA and FJAb provided in the memory cell MC of Figure 1A is replaced with another circuit element.

[0137] For example, the memory cell MC may be configured such that the FTJ element FJA is replaced with a ferroelectric capacitor FEA, and the FTJ element FJAb is replaced with a ferroelectric capacitor FEAb, as shown in Figure 4A.

[0138] In the drawings of this specification, the circuit symbol for a ferroelectric capacitor (e.g., ferroelectric capacitor FEA, ferroelectric capacitor FEAb, etc.) is shown in Figure 4A, with a diagonal line added to the capacitance circuit symbol. Alternatively, as shown in Figure 4B, the capacitance circuit symbol may be represented by adding multiple diagonal lines between two parallel lines.

[0139] In Figures 4A and 4B, the first terminal of the ferroelectric capacitor FEA is electrically connected to the wiring FCA, and the second terminal of the ferroelectric capacitor FEA is electrically connected to the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. Furthermore, the first terminal of the ferroelectric capacitor FEAb is electrically connected to the wiring FCA, and the second terminal of the ferroelectric capacitor FEAb is electrically connected to the second terminal of transistor M1b, the first terminal of transistor M6b, and the gate of transistor M6.

[0140] As shown in the memory cells MC of FIGS. 4A and 4B, even if each of the FTJ elements FJA and FTJAb of the memory cell of FIG. 1A is replaced with the ferroelectric capacitors FEA and FEAb, respectively, the memory cells MC of FIGS. 4A and 4B can hold the write data transmitted from the wirings WRDL and WRDLb and output the written data. Also, at this time, the read circuit electrically connected to the wirings WRDL and WRDLb may be, for example, an integration circuit that converts the amount of charge flowing through the wiring into a voltage.

[0141] For the data writing method in the memory cells MC of FIGS. 4A and 4B, for example, the data writing method shown in FIG. 2 is taken into consideration.

[0142] Also, for the data reading method in the memory cells MC of FIGS. 4A and 4B, for example, each of the transistors M1 and M1b is turned on, and the potentials of the wirings WRDL and WRDLb are set to the ground potential. Then, a predetermined potential is input to the wiring FCA. Note that the potential is such that when the second terminals of the ferroelectric capacitors FEA and FEAb are at the ground potential, it changes the direction of polarization of the material that can have ferroelectricity included in each of the ferroelectric capacitors FEA and FEAb. Therefore, the potential may be a negative potential or a positive potential as long as it is a potential that can change the direction of polarization of the material that can have ferroelectricity.

[0143] By applying a ground potential to the second terminals of both ferroelectric capacitors FEA and FEAb, and by applying the same potential to the wiring FCA, the polarization direction of the ferroelectric materials in FEA and FEAb is changed. Specifically, the polarization direction of the dielectrics in FEA and FEAb changes from the first terminal to the second terminal. Before reading the data, one dielectric of FEA and FEAb is polarized from the first terminal to the second terminal, and the other dielectric of FEA and FEAb is polarized from the second terminal to the first terminal. Therefore, when reading the data, the polarization direction of the other dielectric of FEA and FEAb will change.

[0144] At this time, the direction of polarization of the other dielectric of ferroelectric capacitor FEA and ferroelectric capacitor FEAb changes, causing a change in the charge of the other dielectric of ferroelectric capacitor FEA and ferroelectric capacitor FEAb. Therefore, by reading the amount of this change in charge using an integrating circuit electrically connected to wiring WRDL or wiring WRDLb, the data held in memory cell MC can be read.

[0145] Furthermore, the read operation described above is a destructive read operation because it changes the polarization direction of the other dielectric of the ferroelectric capacitor FEA and the ferroelectric capacitor FEAb. Therefore, after reading the data held in the memory cell MC, it is necessary to write the same data back to the memory cell MC.

[0146] Furthermore, while Figures 4A and 4B show an example in which the FTJ elements FJA and FJAb of the memory cell MC in Figure 1A are replaced with ferroelectric capacitors FEA and FEAb, the FTJ elements FJA and FJAb of the memory cell MC in Figure 1A may be replaced with circuit elements other than ferroelectric capacitors. For example, the FTJ elements FJA and FJAb of the memory cell MC in Figure 1A may be replaced with circuit elements ANA and ANAb, whose resistance can be changed, as shown in Figure 4C. Specifically, the input terminal of circuit element ANA is electrically connected to wiring FCA, and the output terminal of circuit element ANA is electrically connected to the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. Also, the input terminal of circuit element ANAb is electrically connected to wiring FCA, and the output terminal of circuit element ANAb is electrically connected to the second terminal of transistor M1b, the first terminal of transistor M6b, and the gate of transistor M6. Examples of circuit elements ANA and ANAb include resistive random access elements used in ReRAM (Resistive Random Access Memory), MTJ (Magnetic Tunnel Junction, or Magnetic Transportation Junction) elements used in MRAM (Magnetoresistive Random Access Memory), and phase-change memory (PCM) elements.

[0147] As shown in the memory cell MC of Figure 4C, even if the FTJ elements FJA and FJAb of the memory cell in Figure 1A are replaced with circuit elements ANA and ANAb, respectively, the resistance values ​​of circuit elements ANA and ANAb can be changed in the same way as the FTJ elements FJA and FJAb of the memory cell MC in Figure 1A. Therefore, the memory cell MC of Figure 4C, like the memory cell MC of Figure 1A, may allow data to be written to the memory cell MC and read out the stored data without destroying it.

[0148] <Configuration Example 3> In this configuration example, we will describe a memory cell that can be provided in a memory device, which is a semiconductor device according to one aspect of the present invention, different from the memory cell MC shown in Figure 1A.

[0149] The memory cell MC shown in Figure 5A is a modified version of the memory cell MC in Figure 1A, and is configured in which transistors M7 and M8 are further provided in addition to the memory cell MC in Figure 1A.

[0150] The first terminal of transistor M7 is electrically connected to wiring VCE, the second terminal of transistor M7 is electrically connected to the first terminal of transistor M8, and the gate of transistor M7 is electrically connected to the output terminal of FTJ element FJA, the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. The second terminal of transistor M8 is electrically connected to wiring RDL, and the gate of transistor M8 is electrically connected to wiring RWLA.

[0151] Wiring VCE functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential.

[0152] One example of a wiring RDL is a wiring that transmits data read from a memory cell MC.

[0153] The wiring RWLA, as an example, functions as wiring for selecting the memory cell MC from which to read data.

[0154] Furthermore, for the example of data writing operation to the memory cell MC in Figure 5A, refer to the timing chart in Figure 2. In addition, when writing data to the memory cell MC in Figure 5A, it is preferable that the potential supplied by wiring RWLA and wiring RDL be, for example, a low-level potential or ground potential.

[0155] Furthermore, for an example of data reading operation from the memory cell MC in Figure 5A, refer to the timing chart in Figure 3. However, it is assumed that the wiring VCE is given a ground potential as an example. In the memory cell MC of Figure 5A, for example, between time T24 and time T25 in the timing chart of Figure 3, it is preferable that a high-level potential is applied to the wiring RWLA, turning on transistor M8, and that a high-level potential is also applied to the wiring RDL. As a result, the first terminal of transistor M7 is given a ground potential and the second terminal of transistor M7 is given a high-level potential, so the amount of current flowing between the first and second terminals of transistor M7 is determined by the potential of the gate of transistor M7 (the output terminal of the FTJ element FJAb). In other words, since this current flows through the wiring RDL, the amount of this current can be converted to a voltage by a current-voltage conversion circuit electrically connected to the wiring RDL, thereby enabling data reading from the memory cell MC of Figure 5A.

[0156] Next, we will describe a memory cell that can be provided in a memory device, which is a semiconductor device according to one embodiment of the present invention, and which is different from the memory cell MC shown in Figures 1A, 1B, and 5A.

[0157] The memory cell MC shown in Figure 5B is a modified example of the memory cell MC in Figure 5A, and differs from the memory cell MC in Figure 5A in that it has a transistor M9 and a capacitor CS, and that the gate of transistor M7 and the output terminal of the FTJ element FJA are electrically connected via the capacitor CS.

[0158] The memory cell MC in Figure 5B has the function of correcting the threshold voltage of transistor M7, in addition to the function of the memory cell MC in Figure 5A. By correcting the threshold voltage of transistor M7, the amount of current flowing between the first and second terminals of transistor M7 may no longer depend on the threshold voltage of transistor M7. As a result, for example, when considering a memory cell array in which multiple memory cell MCs of Figure 5B are arranged, it is possible to reduce the variation in the threshold voltage of transistor M7 contained in each of the multiple memory cell MCs, thereby preventing the reading of incorrect data in multiple memory cell MCs.

[0159] The gate of transistor M7 is electrically connected to the first terminal of capacitor CS and the first terminal of transistor M9. The second terminal of capacitor CS is electrically connected to the output terminal of FTJ element FJA, the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. The second terminal of transistor M9 is electrically connected to the second terminal of transistor M7 and the first terminal of transistor M8. The gate of transistor M9 is electrically connected to wiring WCL. In Figure 5B, the electrical connection point between the gate of transistor M7, the first terminal of capacitor CS, and the first terminal of transistor M9 is shown as node ND.

[0160] Wiring WCL functions, for example, as a control wire that switches the on and off states of transistor M9. Specifically, for instance, wiring WCL has the function of turning transistor M9 on or off by inputting a high-level potential or a low-level potential when correcting the threshold voltage of transistor M7.

[0161] <<Example of threshold voltage correction operation>> Next, we will describe the operation of correcting the threshold voltage of transistor M7. This operation can be performed, for example, before or after writing data to the memory cell MC in Figure 5B.

[0162] FIG. 7 is a timing chart showing an operation example of correcting the threshold voltage of transistor M7 in memory cell MC of FIG. 5B. The timing chart shown in FIG. 7 shows changes in the potentials of wiring WRWL, wiring RWL, wiring WCL, wiring WRDL, wiring RDL, and node ND from time T31 to time T36 and at times in the vicinity thereof.

[0163] [From time T31 to time T32] Between time T31 and time T32, the potentials of wiring WRWL, wiring RWL, and wiring WCL are, as an example, at a low level potential (described as Low in FIG. 7). Therefore, a low level potential is input to the gates of transistors M1 and M1b respectively. Accordingly, each of transistors M1, M1b, M8, and M9 is in an off state.

[0164] Also, between time T31 and time T32, the potentials of wiring WRDL and wiring RDL are, as an example, at a ground potential (described as GND in FIG. 7).

[0165] Also, between time T31 and time T32, the potential of node ND is, as an example, at a ground potential.

[0166] [From time T32 to time T33] Between time T32 and time T33, the potentials provided by wiring WRWL, wiring RWL, and wiring WCL each change from a low-level potential to a high-level potential (described as High in FIG. 7). Therefore, a high-level potential is input to the gates of transistors M1, M1b, M8, and M9, and transistors M1, M1b, M8, and M9 each enter an on state. That is, conduction is established between wiring WRDLb and the second terminal of capacitor CS, and conduction is established between wiring RDL and the first terminal of capacitor CS. As a result, the potential of the output terminal of FTJ element FJAb and the potential of node ND become the ground potential, and the voltage between the first terminal and the second terminal of capacitor CS becomes approximately 0V.

[0167] [From time T33 to time T34] Between time T33 and time T34, a potential V D is applied to wiring RDL. The potential V D is, for example, a potential greater than the threshold voltage of transistor M7. At this time, the potential of the first terminal (node ND) of capacitor CS is the potential V D from wiring RDL via transistors M8 and M9.

[0168] [From time T34 to time T35] Between time T34 and time T35, the potential provided by wiring RWL changes from a high-level potential to a low-level potential. Therefore, a low-level potential is input to the gate of transistor M8, and transistor M8 enters an off state.

[0169] Incidentally, since transistor M9 is in an on state, conduction is established between the second terminal and the gate of transistor M7. Also, since transistor M8 is in an off state, the potential of the first terminal (node ND) of capacitor CS decreases due to current flowing between the first terminal and the second terminal of transistor M7. Note that the decrease in the potential of the first terminal (node ND) of capacitor CS is such that the gate-source voltage of transistor M7 is the threshold voltage (Vth This continues until it becomes equal to (assuming). Therefore, the potential of the gate of transistor M7 (the first terminal of capacitance CS, node ND) is V D From V th It will decrease to that point.

[0170] [From time T35 to time T36] Between time T35 and time T36, the potential supplied by wiring WCL changes from a high-level potential to a low-level potential. Therefore, a low-level potential is input to the gate of transistor M9, causing transistor M9 to turn off. This maintains the voltage between the first and second terminals of capacitor CS. Also, at this time, the potential at the gate of transistor M7 (the first terminal of capacitor CS, node ND) is V th As a result, the gate-source voltage of transistor M7 is equal to the threshold voltage.

[0171] Here, for example, the potential of the second terminal of capacitance CS is a potential V from the ground potential. MR When it changes to this, the gate potential of transistor M7 is V MR +V th This is the result. Also, the difference between the gate-source voltage and the threshold voltage of transistor M7 at this time is (V MR +V th )-V th =V MR This is the result. By applying a potential higher than ground potential to the second terminal of transistor M7, a current flows between the source and drain of transistor M7, corresponding to the difference between the gate-source voltage of transistor M7 and the threshold voltage, and the source-drain voltage. The difference between the gate-source voltage and the threshold voltage is V MR Therefore, the current flowing between the source and drain of transistor M7 no longer depends on the threshold voltage of transistor M7. In this way, by correcting the threshold voltage of transistor M7, it is possible to flow a current between the source and drain of transistor M7 that does not depend on the threshold voltage of transistor M7.

[0172] As described above, the threshold voltage of transistor M7 can be corrected by the example operation between time T31 and time T36 shown in Figure 7.

[0173] <Configuration Example 4> The memory cell MC shown in Figure 6 is an example of a memory cell circuit configuration applicable to a memory device according to one embodiment of the present invention. The memory cell MC in Figure 6 is a modified version of the memory cell MC in Figure 5A, and is configured in which transistors M7b and M8b are further provided in addition to the memory cell MC in Figure 5A.

[0174] The first terminal of transistor M7b is electrically connected to wiring VCE, the second terminal of transistor M7b is electrically connected to the first terminal of transistor M8b, and the gate of transistor M7b is electrically connected to the output terminal of FTJ element FJA, the second terminal of transistor M1, the first terminal of transistor M6, and the gate of transistor M6b. The second terminal of transistor M8b is electrically connected to wiring RDLb, and the gates of transistors M8 and M8b are electrically connected to wiring RWLA.

[0175] For example, wiring RDLb functions as a wiring that transmits data read from the memory cell MC, similar to wiring RDL. Furthermore, wiring RDL and wiring RDLb function as a wiring pair that transmits complementary data.

[0176] Furthermore, the timing chart in Figure 2 should be considered when illustrating the example of data writing operation to the memory cell MC in Figure 6. In addition, during the data writing operation to the memory cell MC in Figure 6, it is preferable that the potential supplied by wiring RWLA, wiring RDL, and wiring RDLb be, for example, a low-level potential or ground potential.

[0177] Furthermore, for an example of data reading operation from the memory cell MC in Figure 6, refer to the timing chart in Figure 3. However, it is assumed that the wiring VCE is given a ground potential as an example. In the memory cell MC of Figure 6, for example, between time T24 and time T25 in the timing chart of Figure 3, it is preferable that a high-level potential is applied to the wiring RWLA, turning on transistors M8 and M8b, and that a high-level potential is also applied to the wiring RDL and RDLb. As a result, the first terminal of transistor M7 is given a ground potential and the second terminal of transistor M7 is given a high-level potential, so the amount of current flowing between the first and second terminals of transistor M7 is determined by the potential of the gate of transistor M7 (the output terminal of FTJ element FJAb). At the same time, the first terminal of transistor M7b is given a ground potential and the second terminal of transistor M7b is given a high-level potential, so the amount of current flowing between the first and second terminals of transistor M7b is determined by the potential of the gate of transistor M7b (the output terminal of FTJ element FJA). In other words, current flows through wiring RDL and wiring RDLb, respectively, corresponding to the source-drain voltages of transistors M7 and M7b. Therefore, by converting the amount of current flowing through wiring RDL and wiring RDLb into a voltage value using a current-to-voltage conversion circuit, for example, data can be read from the memory cell MC shown in Figure 7.

[0178] As described in this embodiment, by applying memory cell MCs to a semiconductor device, it is possible to configure a semiconductor device that does not require data rewriting (a semiconductor device that performs non-destructive reading). Furthermore, by applying memory cell MCs to a semiconductor device, data rewriting becomes unnecessary, thus reducing the power consumption required for rewriting. In addition, by applying memory cell MCs to a semiconductor device, it becomes unnecessary to provide a circuit for data rewriting, thus reducing the circuit area of ​​the semiconductor device.

[0179] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0180] (Embodiment 2) This embodiment describes a storage device that can be equipped with the memory cell MC described in the above embodiment.

[0181] <Example of storage device configuration> Figure 8 shows an example of the circuit configuration of the memory device. The memory device 100 includes a memory cell array MCA, a circuit WDD, a circuit WRWD, a circuit RDD, and a circuit FECD. The memory cell MC applicable to the memory device 100 in Figure 8 is, for example, the memory cell MC shown in Figure 1A (Figure 1B).

[0182] A memory cell array (MCA) has multiple memory cells (MCs). In the memory cell array (MCA), the multiple memory cells (MCs) are arranged in a matrix of m rows and n columns (where m and n are integers greater than or equal to 1). In Figure 8, for example, a memory cell (MC) located in row i and column j (where i is an integer between 1 and m, and j is an integer between 1 and n) is shown as memory cell (MC)[i,j].

[0183] Furthermore, wirings WRDL[1] to WRDL[n] and wirings WRDLb[1] to WRDLb[n] extend in the column direction to the memory cell array MCA of the storage device 100. Note that [j] attached to wiring WRDL and wiring WRDLb indicates that it is the wiring in the j-th column. Also, wirings WRWL[1] to WRWL[m], wiring FCA[1] to wiring FCA[m], and wiring FCB[1] to wiring FCB[m] extend in the row direction. Note that [i] attached to wiring WRWL, wiring FCA, and wiring FCB indicates that it is the wiring in the i-th row.

[0184] Wirings WRDL[1] to WRDL[n] correspond to wiring WRDL in the memory cell MC in Figure 1A (Figure 1B). Also, wirings WRWL[1] to WRWL[m] correspond to wiring WRDL in the memory cell MC in Figure 1A (Figure 1B), wirings FCA[1] to FCA[m] correspond to wiring FCA in the memory cell MC in Figure 1A (Figure 1B), and wirings FCB[1] to FCB[m] correspond to wiring FCB in the memory cell MC in Figure 1A (Figure 1B).

[0185] Circuit WDD is electrically connected to wiring WRDL[1] through WRDL[n] and wiring WRDLb[1] through WRDLb[n]. Circuit RDD is electrically connected to wiring WRDL[1] through WRDL[n] and wiring WRDLb[1] through WRDLb[n]. Circuit FECD is electrically connected to wiring FCA[1] through FCA[m] and wiring FCB[1] through FCB[m].

[0186] Circuit WRWD functions, for example, as a write word line driver circuit. For instance, circuit WRWD can select multiple memory cells MCs to perform a write operation in a memory cell array MCA by sending a selection signal to one of the wirings WRWL[1] to WRWL[m] and a deselection signal to the remaining wirings. Specifically, for example, in the case of the memory cell MC in Figure 1A, a high-level potential can be used as the selection signal and a low-level potential as the deselection signal. In the memory cell MC of Figure 1A, if a high-level potential is applied to wiring WRWL, transistor M1 turns ON, allowing wiring WRDL and WRDLb to send data for writing to the memory cell MC. On the other hand, in the memory cell MC of Figure 1A (Figure 1B), if a low-level potential is applied to wiring WRWL, transistor M1 turns OFF. Therefore, even if data for writing to another memory cell MC is sent from wiring WRDL and WRDLb, that data will not be written to the memory cell MC to which wiring WRWL is applying a low-level potential.

[0187] Furthermore, the WRWD circuit can also function as a read word line driver circuit, for example. For instance, the WRWD circuit can select multiple memory cells MCs to perform a read operation in the memory cell array MCA by sending a selection signal to one of the wirings RWL[1] to RWL[m] and a deselection signal to the remaining wirings. Specifically, for example, in the case of the memory cell MC in Figure 1A, a high-level potential can be used as the selection signal and a low-level potential as the deselection signal. In the memory cell MC of Figure 1A, when a high-level potential is applied to wiring WRWL, transistor M1 is turned ON, allowing data held in the memory cell MC to be transmitted from the memory cell MC to wiring WRDL and wiring WRDLb. On the other hand, in the memory cell MC of Figure 1A, when a low-level potential is applied to wiring WRWL, transistors M1 and M1b are turned OFF, so data held in the memory cell MC is not transmitted from the memory cell MC to wiring WRDL and wiring WRDLb.

[0188] The FECD circuit, as an example, has the function of applying potential to wiring FCA and wiring FCB, respectively. Specifically, for example, when writing data to a memory cell MC, the FECD circuit can generate polarization (change the direction of polarization) in the FTJ elements FJA and FJAb provided in each of the multiple memory cell MCs by applying potential to wiring FCA and wiring FCB, respectively. Alternatively, when reading data from a memory cell MC, the FECD circuit can determine the potential of the output terminals of the FTJ elements FJA and FJAb, respectively, according to the direction of polarization of the FTJ elements FJA and FJAb, respectively, by applying potential to wiring FCA and wiring FCB, respectively.

[0189] Circuit WDD functions, for example, as a write data line driver circuit. For instance, circuit WDD can write data (e.g., voltage) to multiple memory cells MC located in a specific row selected by circuit WRWD by transmitting write data (e.g., voltage) to each of the wirings WRDL[1] through WRDL[n].

[0190] Circuit RDD functions, for example, as a read circuit. For instance, circuit RDD can retrieve data (e.g., voltage, current, etc.) output from multiple memory cells MC located in a specific row selected by circuit WRWD from wiring WRDL[1] to wiring WRDL[n] and wiring WRDLb[1] to wiring WRDLb[n], and read the data. Circuit WDD has, for example, one or more selected from a pre-charge circuit, a sense amplifier circuit, a current-voltage conversion circuit, etc.

[0191] <Example of storage device operation> Next, an example of the operation of the storage device 100 will be described.

[0192] <<Example of writing operation 1>> Figure 9 is a timing chart showing an example of the data writing operation to the memory cell MC of the storage device 100. Note that the timing chart in Figure 2 described in the above embodiment shows an example of operation for one memory cell MC, while the timing chart in Figure 9 shows an example of data writing operation to multiple memory cell MCs included in the memory cell array MCA.

[0193] The timing chart in Figure 9 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], wiring WRDLb[n], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], and wiring FCB[m] between time U1 and time U10, and in the vicinity of that time.

[0194] Between time U1 and time U2, for example, circuit WRWD applies a low-level potential (labeled "Low" in Figure 9) as an initial potential to wiring WRWL[1] through wiring WRWL[m]. Therefore, a low-level potential is applied to the gate of each transistor M1 of all memory cells MC included in memory cell array MCA, causing transistor M1 to be in the off state.

[0195] Furthermore, between time U1 and time U2, circuit WDD does not transmit data for writing to wiring WRDL[1] through wiring WRDL[n] and wiring WRDLb[1] through wiring WRDLb[n]. Therefore, between time U1 and time U2, circuit WDD provides, for example, a ground potential to wiring WRDL[1] through wiring WRDL[n] and wiring WRDLb[1] through wiring WRDLb[n].

[0196] Furthermore, between time U1 and time U2, the circuit RDD may be made non-conductive between the circuit RDD and the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n], respectively, by a switch included in the circuit RDD, etc. By making the circuit RDD and the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n], respectively, non-conductive, the write data sent from the circuit WDD to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n] will not be input to the circuit RDD, and in some cases, the power consumption required to transmit write data from the circuit WDD to the wirings WRDL[1] to WRDL[n] and WRDLb[1] to WRDLb[n] may be reduced.

[0197] Furthermore, between time U1 and time U2, circuit FECD has a potential V in each of the wirings FCA[1] to FCA[m] and FCB[1] to FCB[m]. 0A , and potential V 0B It gives the potential V. 0A , and potential V 0B For further information, please refer to the explanation of the timing chart in Figure 2.

[0198] Between time U2 and time U4, circuit WRWD provides a high-level potential (labeled High in Figure 9) to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through wiring WRWL[m]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in memory cells MC[1,1] through MC[1,n] located in the first row, causing transistors M1 and M1b in memory cells MC[1,1] through MC[1,n] to be in the ON state. Also, in the memory cell array MCA, a low-level potential is applied to the gates of transistors M1 and M1b contained in memory cells MC[2,1] through MC[m,n] located in the second through m rows, causing transistors M1 and M1b in memory cells MC[2,1] through MC[m,n] to be in the OFF state. In other words, circuit WRWD can select memory cell MC located in the first row of memory cell array MCA as the write destination by applying a high-level potential to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through wiring WRWL[m].

[0199] Furthermore, between time U2 and time U4, the circuit WDD provides each of the wirings WRDL[1] to WRDL[n] with Da[1,1] to Da[1,n], as an example, part of the data to be rewritten. The circuit WDD also provides each of the wirings WRDLb[1] to WRDLb[n] with Db[1,1] to Db[1,n], as an example, data to be written. For example, if Da[1,j] and Db[1,j] (where j is an integer between 1 and n) are digital values, it is preferable that Da[1,j] and Db[1,j] are logically inverted data of each other. Specifically, when the potential corresponding to Da[1,j] is V0, it is preferable that the potential corresponding to Db[1,j] is V1, or when the potential corresponding to Da[1,j] is V1, it is preferable that the potential corresponding to Db[1,j] is V0. Furthermore, V0 and V1 are explained in the operation example of the timing chart in Figure 2. In addition, because the circuit WRWD selects the memory cell MC located in the first row of the memory cell array MCA as the write destination, a potential corresponding to Da[1,1] to Da[1,n] is applied to the second terminal of transistor M1 of each memory cell MC[1,1] to memory cell MC[1,n], and a potential corresponding to Db[1,1] to Db[1,n] is applied to the second terminal of transistor M1b of each memory cell MC[1,1] to memory cell MC[1,n].

[0200] Furthermore, between time U2 and time U3, circuit FECD has a potential V on wiring FCA[1]. 1A This gives a potential V to the wiring FCB[1]. 0B This provides a potential V. Note that circuit FECD provides a potential V to each of the wires FCA[2] through FCA[m]. 0A This provides a potential V to each of the wiring FCB[2] to wiring FCB[m]. 0B Give.

[0201] Furthermore, between time U3 and time U4, circuit FECD has a potential V on wiring FCA[1]. 0A This gives a potential V to the wiring FCB[1]. 0BThis provides the potential V. Furthermore, circuit FECD continues to provide the potential V to each of the wires FCA[2] through FCA[m]. 0A This provides a potential V to each of the wiring FCB[2] to wiring FCB[m]. 0B Give.

[0202] Note that potential V 1A , and potential V 1B For further information, please refer to the explanation of the timing chart in Figure 2.

[0203] The operation between time U2 and time U4 determines the direction of polarization generated in the FTJ elements FJA and FJAb contained in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA, according to Da[1,1] to Da[1,n] sent from wiring WRDL[1] to wiring WRDL[n] and Db[1,1] to Db[1,n] sent from wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on column j, the operation between time U2 and time U4 involves writing Da[1,j] and Db[1,j] to memory cell MC[1,j].

[0204] Between time U4 and time U6, circuit WRWD provides a high-level potential to wiring WRWL[2] and a low-level potential to wiring WRWL[1] and wiring WRWL[3] through wiring WRWL[m]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[2,1] through MC[2,n] located in the second row, causing transistors M1 and M1b contained in each of the memory cells MC[2,1] through MC[2,n] to be in the ON state. Furthermore, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in memory cells MC[1,1] to MC[1,n] and memory cells MC[3,1] to MC[m,n], which are located in the first row and rows 3 through m. As a result, transistors M1 and M1b contained in memory cells MC[1,1] to MC[1,n] and memory cells MC[3,1] to MC[m,n] are turned off. In other words, the circuit WRWD can select a memory cell MC located in the second row of the memory cell array MCA as the write destination by applying a high-level potential to wiring WRWL[2] and a low-level potential to wiring WRWL[1] and wiring WRWL[3] to WRWL[m].

[0205] Furthermore, between time U4 and time U6, the circuit WDD assigns Da[2,1] to Da[2,n], as an example, to each of the wirings WRDL[1] to WRDL[n], which are part of the data to be written. The circuit WDD also assigns Db[2,1] to Db[2,n], as an example, to each of the wirings WRDLb[1] to WRDLb[n], which are data to be written. For example, if Da[2,j] and Db[2,j] are both digital values, it is preferable that Da[2,j] and Db[2,j] are logically inverted data of each other. Specifically, when the potential corresponding to Da[2,j] is V0, it is preferable that the potential corresponding to Db[2,j] is V1, or when the potential corresponding to Da[2,j] is V1, it is preferable that the potential corresponding to Db[2,j] is V0. Furthermore, V0 and V1 are explained in the operation example of the timing chart in Figure 2. In addition, because the circuit WRWD selects the memory cell MC located in the second row of the memory cell array MCA as the write destination, a potential corresponding to Da[2,1] to Da[2,n] is applied to the second terminal of transistor M1 of each memory cell MC[2,1] to memory cell MC[2,n], and a potential corresponding to Db[2,1] to Db[2,n] is applied to the second terminal of transistor M1b of each memory cell MC[2,1] to memory cell MC[2,n].

[0206] Furthermore, between time U4 and time U5, circuit FECD has a potential V on wiring FCA[2]. 1A This gives a potential V to the wiring FCB[2]. 0B This provides a potential V. Note that circuit FECD provides a potential V to each of the wires FCA[1] and FCA[3] through FCA[m]. 0A This provides a potential V to each of the wiring FCB[1], wiring FCB[3] through wiring FCB[m]. 0B Give.

[0207] Furthermore, between time U5 and time U6, circuit FECD has a potential V on wiring FCA[2]. 0A This gives a potential V to the wiring FCB[2]. 0BThe circuit FECD then applies a potential V to each of the wires FCA[1] and FCA[3] through FCA[m]. 0A This provides a potential V to each of the wiring FCB[1] and wiring FCB[3] through wiring FCB[m]. 0B Give.

[0208] The operation between time U4 and time U6 determines the direction of polarization generated in the FTJ elements FJA and FJAb contained in each of the memory cells MC[2,1] to MC[2,n] in the second row of the memory cell array MCA, according to Da[2,1] to Da[2,n] sent from wiring WRDL[1] to wiring WRDL[n] and Db[2,1] to Db[2,n] sent from wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on column j, the operation between time U4 and time U6 involves writing Da[2,j] and Db[2,j] to memory cell MC[2,j].

[0209] Between time U6 and time U7, data writing operations are performed to memory cells MC located in the third row to the (m-1)th row of the memory cell array MCA, similar to the data writing operations performed to the memory cells MC located in the first row of the memory cell array MCA between time U2 and time U4, and to the memory cells MC located in the second row of the memory cell array MCA between time U4 and time U6.

[0210] Between time U7 and time U9, circuit WRWD provides a high-level potential to wiring WRWL[m] and a low-level potential to wiring WRWL[1] through wiring WRWL[m-1]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[m,1] through MC[m,n] located in row m, causing transistors M1 and M1b in each of the memory cells MC[m,1] through MC[m,n] to be in the ON state. Also, in the memory cell array MCA, a low-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[1,1] through MC[m-1,n] located from row 1 to row m-1, causing transistors M1 and M1b in each of the memory cells MC[1,1] through MC[m-1,n] to be in the OFF state. In other words, circuit WRWD can select memory cell MC located in the first row of memory cell array MCA as the write destination by applying a high-level potential to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through wiring WRWL[m].

[0211] Furthermore, between time U7 and time U9, circuit WDD provides each of the wirings WRDL[1] to WRDL[n] with Da[m,1] to Da[m,n], as an example, part of the data to be rewritten. Also, circuit WDD provides each of the wirings WRDLb[1] to WRDLb[n] with Db[m,1] to Db[m,n], as an example, data to be written. Note that, for example, if Da[m,j] and Db[m,j] are both digital values, it is preferable that Da[m,j] and Db[m,j] are logically inverted data of each other. Specifically, when the potential corresponding to Da[m,j] is V0, it is preferable that the potential corresponding to Db[m,j] is V1, or when the potential corresponding to Da[m,j] is V1, it is preferable that the potential corresponding to Db[m,j] is V0. Note that V0 and V1 are explained in the operation example of the timing chart in Figure 2. Furthermore, because the circuit WRWD selects the memory cell MC located in the first row of the memory cell array MCA as the write destination, a potential corresponding to Da[m,1] to Da[m,n] is applied to the second terminal of transistor M1 of each memory cell MC[m,1] to memory cell MC[m,n], and a potential corresponding to Db[m,1] to Db[m,n] is applied to the second terminal of transistor M1b of each memory cell MC[m,1] to memory cell MC[m,n].

[0212] Furthermore, between time U7 and time U8, the circuit FECD has a potential V at wiring FCA[m]. 1A Give a potential V to the wiring FCB[m]. 0B This provides a potential V. Note that circuit FECD has a potential V in each of the wires FCA[1] to FCA[m-1]. 0A This provides a potential V to each of the wiring FCB[1] to wiring FCB[m-1]. 0B Give.

[0213] Furthermore, between time U8 and time U9, circuit FECD has a potential V on wiring FCA[m]. 0A Give a potential V to the wiring FCB[m]. 0BThis provides the potential V. Furthermore, circuit FECD continues to provide the potential V to each of the wires FCA[1] through FCA[m-1]. 0A This provides a potential V to each of the wiring FCB[1] to wiring FCB[m-1]. 0B Give.

[0214] Between time U7 and time U9, the direction of polarization generated in the FTJ elements FJA and FJAb contained in each of the memory cells MC[m,1] to MC[m,n] in the mth row of the memory cell array MCA is determined according to the Da[m,1] to Da[m,n] sent from wiring WRDL[1] to wiring WRDL[n] and the Db[m,1] to Db[m,n] sent from wiring WRDLb[1] to wiring WRDLb[n]. In other words, focusing on the jth column, the Da[m,j] and Db[m,j] are written to the memory cell MC[m,j] during the operation between time U7 and time U8.

[0215] The operations performed from time U1 to time U10 allow D[1,1] to D[m,n] to be written to each of the memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA.

[0216] In the timing chart of Figure 9, as an example of the operation after the completion of the data writing operation to memory cells MC[1,1] to MC[m,n] (operation between time U9 and time U10), circuit WRWD applies a low-level potential to wiring WRWL[1] to wiring WRWL[m]. Also, as an example, circuit WDD applies a ground potential to wiring WRDL[1] to wiring WRDL[n]. Also, as an example, circuit FECD applies a potential V to wiring FCA[1] to wiring FCA[m] and wiring FCB[1] to wiring FCB[m]. 0A , and potential V 0B It is giving.

[0217] Note that the operation of the timing chart in Figure 9 is just one example, and its operation may be changed depending on the situation or circumstances. For example, in the operation between time U2 and time U4 of the timing chart in Figure 9, a high-level potential is applied to wiring WRWL[1], Da[1,1] to Da[1,n] is applied to wiring WRDL[1] to wiring WRDL[n], and Db[1,1] to Db[1,n] is applied to wiring WRDLb[1] to wiring WRDLb[n]. However, during the period when a high-level potential is applied to wiring WRWL[1], Da[1,1] to Da[1,n] may be applied to wiring WRDL[1] to wiring WRDL[n], and Db[1,1] to Db[1,n] may be applied to wiring WRDLb[1] to wiring WRDLb[n]. Alternatively, a high-level potential may be applied to wiring WRWL[1] during the period when Da[1,1] to Da[1,n] is applied to wiring WRDL[1] to WRDL[n], and Db[1,1] to Db[1,n] is applied to wiring WRDLb[1] to WRDLb[n]. Also, a potential V may be applied to wiring FCA[1]. 1A A potential V is given, and the wiring FCB[1] has a potential V 0B During the period given, and with a potential V in wiring FCA[1] 0A Given and a potential V in wiring FCB[1] 0B The period during which a high-level potential is applied to wiring WRWL[1], Da[1,1] to Da[1,n] is applied to wiring WRDL[1] to wiring WRDL[n], and Db[1,1] to Db[1,n] is applied to wiring WRDLb[1] to wiring WRDLb[n]. This can be done at any time within this period. Also, the potential V is applied to wiring FCA[1]. 0A Given and a potential V in wiring FCB[1] 0B During the period given, the potential V is applied to wiring FCA[1]. 1A A potential V is given, and the wiring FCB[1] has a potential V 0B It may be performed before the given period.

[0218] <<Example of writing operation 2>> Next, we will describe an example of data writing operation to the memory cell MC of the storage device 100, which differs from the timing chart in Figure 9.

[0219] The timing chart shown in Figure 10 shows an example of a write operation, which differs from the write operation example in the timing chart of Figure 9. Similar to the timing chart in Figure 9, the timing chart in Figure 10 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], wiring WRDLb[n], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], and wiring FCB[m] between time U1 and time U10, and in the vicinity of that time.

[0220] The writing operation of the timing chart in Figure 10 differs from the writing operation of the timing chart in Figure 9 in that a high-level potential is input to each of the wirings WRWL[1] to WRWL[m] between time U2 and time U9, and in terms of the potential fluctuation of each of the wirings FCA[1] to FCA[m] between time U1 and time U9.

[0221] Between time U2 and time U9 in the timing chart of Figure 10, a high-level potential is input to each of the wirings WRWL[1] to WRWL[m]. Therefore, between time U2 and time U9, a high-level potential is input to the gates of each transistor M1 and transistor M1b of each memory cell MC[1,1] to MC[m,n] included in the memory cell array MCA. As a result, each transistor M1 and transistor M1b of each memory cell MC[1,1] to MC[m,n] is turned ON. In other words, focusing on column j, there is conduction between wiring WRDL[j] and the second terminal of each transistor M1 of each memory cell MC[1,j] to MC[m,j], and there is conduction between wiring WRDLb[j] and the second terminal of each transistor M1b of each memory cell MC[1,j] to MC[m,j].

[0222] Furthermore, in the timing chart of Figure 10, between time U1 and time U2, the potential V is present in wiring FCA[1] to wiring FCA[m]. NA It is given

[0223] Note V NA The potential is such that no polarization occurs (no change) in the FTJ element FJA for all data (potential) input from wiring WRDL to the second terminal of transistor M1, and the potential is such that no polarization occurs (no change) in the FTJ element FJAb for all data (potential) input from wiring WRDLb to the second terminal of transistor M1b. For example, V NA V 0A Higher than V 1A It can be set to a lower potential than that.

[0224] Furthermore, between time U2 and time U3 in the timing chart of Figure 10, there is a potential V in wiring FCA[1]. 1A Given, the potential V is applied to the wiring FCB[1]. 0B The following is given. Furthermore, the potential V continues to be applied to each of the wirings FCA[2] through FCA[m]. NAA potential V is given, and each of the wiring FCB[2] to wiring FCB[m] continues to have a potential V 0B It is given

[0225] Furthermore, in the timing chart of Figure 10, between time U3 and time U4, there is a potential V in wiring FCA[1]. 0A Given, the potential V is applied to the wiring FCB[1]. 0B The following is given. Furthermore, the potential V continues to be applied to each of the wirings FCA[2] through FCA[m]. NA A potential V is given, and each of the wiring FCB[2] to wiring FCB[m] continues to have a potential V 0B It is given

[0226] The operation between time U2 and time U4 in the timing chart of Figure 10 determines the direction of polarization generated in the FTJ element FJA contained in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA, according to Da[1,1] to Da[1,n] sent from wiring WRDL[1] to wiring WRDL[n], and the direction of polarization generated in the FTJ element FJAb contained in each of the memory cells MC[1,1] to MC[1,n] in the first row of the memory cell array MCA, according to Db[1,1] to Db[1,n] sent from wiring WRDL[1] to wiring WRDL[n]. Meanwhile, between time U2 and time U4, each of wiring FCA[2] to wiring FCA[m] has a potential V NA A potential V is given, and each of the wiring FCB[2] to wiring FCB[m] has a potential V 0B Because of the given conditions, even if each transistor M1 of memory cell MC[2,1] to memory cell MC[m,n] is turned on, Da[1,1] to Da[1,n] and Db[1,1] to Db[1,n] will not be written to the memory cell MC of each column.

[0227] In other words, in the operation of the timing chart in Figure 10, each of the wires FCA[1] to FCA[m] and FCB[1] to FCB[m] can function not only as wiring for controlling the polarization of the FTJ elements FJA and FJAb, but also as selection signal lines for data writing.

[0228] In the timing chart of Figure 10, even after time U4, by selecting memory cells MC from the second to the mth row of the memory cell array MCA using wiring FCA[1] to wiring FCA[m] and wiring FCB[1] to wiring FCB[m] in accordance with the data transmitted from wiring WRDL[1] to wiring WRDL[n] and wiring WRDLb[1] to wiring WRDLb[n] respectively, D[1,1] to D[m,n] can be written to each of the memory cells MC[1,1] to memory cells MC[m,n] included in the memory cell array MCA, similar to the operation example of the timing chart in Figure 9.

[0229] <<Example of reading operation 1>> Figure 11 is a timing chart showing an example of data reading operation from memory cells MC of the storage device 100. Note that the timing chart in Figure 3 described in the above embodiment shows an example of operation for one memory cell MC, while the timing chart in Figure 11 shows an example of data writing operation to multiple memory cells MC included in the memory cell array MCA.

[0230] The timing chart in Figure 11 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33, and in the vicinity of that time.

[0231] Between time U21 and time U22, for example, circuit WRWD applies a low-level potential (labeled "Low" in Figure 11) as an initial potential to wiring WRWL[1] through wiring WRWL[m]. As a result, the gates of transistors M1 and M1b of all memory cells MC included in memory cell array MCA are supplied with a low-level potential, causing transistors M1 and M1b to be in an off state.

[0232] Furthermore, between time U21 and time U22, circuit FECD has a potential V across wiring FCA[1] to wiring FCA[m] and wiring FCB[1] to wiring FCB[m], respectively. 0A , and potential V 0B It gives the potential V. 0A , and potential V 0B For further details, please refer to the explanations of the timing charts in Figures 2 and 3.

[0233] Furthermore, between time U21 and time U22, the wiring WRDL[1] to WRDL[n] and wiring WRDLb[1] to WRDLb[n] have, for example, a potential V MD V is given. MD For further details, please refer to the explanation of the timing chart, such as in Figure 3.

[0234] Between time U22 and time U25, circuit FECD has a potential V on wiring FCA[1]. M This gives a potential V to the wiring FCB[1]. 0B This provides a potential V. Furthermore, circuit FECD provides a potential V to wiring FCA[2] through wiring FCA[m]. 0A This provides a potential V to the wiring FCB[2] to the wiring FCB[m]. 0B This is given. At this time, between wiring FCA[1] and wiring FCB[1], V M -V 0BBecause a voltage is applied, a divided voltage of this voltage is applied to each of the FTJ elements FJA and transistor M6 of the first row of memory cells MC[1,1] to MC[1,n] in the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to each of the FTJ elements FJAb and transistor M6b of the first row of memory cells MC[1,1] to MC[1,n] in the memory cell array MCA. Furthermore, the divided voltage applied to FTJ element FJA is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJA, and the divided voltage applied to FTJ element FJAb is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJAb. In other words, the divided voltage applied to each of the FTJ elements FJA and FTJ elements FJAb is determined by the data written to their respective memory cells MC.

[0235] Between time U23 and time U24, circuit WRWD provides a high-level potential (labeled High in Figure 11) to wiring WRWL[1]. Circuit WRWD also provides a low-level potential to wiring WRWL[2] through wiring WRWL[m]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in memory cells MC[1,1] through MC[1,n] located in the first row, causing transistors M1 and M1b in each of the memory cells MC[1,1] through MC[1,n] to be in the ON state. Furthermore, in the memory cell array MCA, a low-level potential is applied to the gates of transistors M1 and M1b contained in memory cells MC[2,1] through MC[m,n] located in rows 2 through m, causing transistors M1 and M1b in each of the memory cells MC[2,1] through MC[m,n] to be in the OFF state.

[0236] In other words, the circuit FECD has a potential V in the wiring FCA[1] M This gives a potential V to the wiring FCB[1]. 0BThis provides a potential V to wiring FCA[2] to wiring FCA[m]. 0A This provides a potential V to the wiring FCB[2] to the wiring FCB[m]. 0B By providing this, and with circuit WRWD providing a high-level potential to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through wiring WRWL[m], the memory cell MC located in the first row of the memory cell array MCA can be selected as the read source.

[0237] Furthermore, between time U23 and time U24, focusing on the first row, column j of the memory cell array MCA, a conductive state is established between the second terminal of transistor M1 of memory cell MC[1,j] and the wiring WRDL[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJA of memory cell MC[1,j] flows to the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes according to the voltage division applied to the FTJ element FJA of memory cell MC[1,j]. In other words, information corresponding to Da[1,j] (e.g., current or voltage) is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of memory cell MC[1,j].

[0238] Furthermore, between time U23 and time U24, focusing on the first row, column j of the memory cell array MCA, a conductive state is established between the second terminal of transistor M1b of memory cell MC[1,j] and the wiring WRDLb[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJAb of memory cell MC[1,j] flows through the wiring WRDLb[j]. Alternatively, the potential of the wiring WRDLb[j] changes according to the voltage division applied to the FTJ element FJAb of memory cell MC[1,j]. In other words, information corresponding to Db[1,j] (e.g., current or voltage) is transmitted to the wiring WRDLb[j] as data held in the FTJ element FJAb of memory cell MC[1,j].

[0239] Furthermore, between time U23 and time U24, data held by memory cells MC[1,1] through MC[1,n] located in the first row of the memory cell array MCA is transmitted for memory cells MC other than column j, in the same manner as described above.

[0240] Specifically, for example, data Da[1,1] and Db[1,1] are read from memory cell MC[1,1], and data Da[1,n] and Db[1,n] are read from memory cell MC[1,n]. At this time, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD, the data Da[1,1] and Db[1,1] held in memory cell MC[1,1] can be read. On the other hand, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD, the data Da[1,n] and Db[1,n] held in memory cell MC[1,n] can be read.

[0241] Between time U25 and time U27, circuit FECD has a potential V on wiring FCA[2]. M This gives a potential V to the wiring FCB[2]. 0B This provides a potential V. Furthermore, circuit FECD provides a potential V to wiring FCA[1] and wiring FCA[3] through wiring FCA[m]. 0A This provides a potential V to wiring FCB[1] and wiring FCB[3] through wiring FCB[m]. 0B This is given. At this time, between wiring FCA[2] and wiring FCB[2], V M -V 0BBecause a voltage is applied, a divided voltage of this voltage is applied to each of the FTJ elements FJA and transistor M6 of the second row of memory cells MC[2,1] to MC[2,n] in the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to each of the FTJ elements FJAb and transistor M6b of the second row of memory cells MC[2,1] to MC[2,n] in the memory cell array MCA. Furthermore, the divided voltage applied to FTJ element FJA is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJA, and the divided voltage applied to FTJ element FJAb is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJAb. In other words, the divided voltage applied to each of the FTJ elements FJA and FTJ elements FJAb is determined by the data written to their respective memory cells MC.

[0242] Between time U26 and time U27, circuit WRWD provides a high-level potential to wiring RWL[2]. Circuit WRWD also provides a low-level potential to wiring WRWL[1] and wiring WRWL[3] through wiring WRWL[m]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[2,1] through MC[2,n] located in the second row, so that transistors M1 and M1b contained in each of the memory cells MC[2,1] through MC[2,n] are turned ON. Also, in the memory cell array MCA, a low-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC located in the first row and rows 3 through m, so that transistors M1 and M1b contained in each of the memory cells MC located in the first row and rows 3 through m are turned OFF.

[0243] In other words, the circuit FECD has a potential V in the wiring FCA[2] M This gives a potential V to the wiring FCB[2]. 0BThis provides a potential V to wiring FCA[1] and wiring FCA[3] through wiring FCA[m]. 0A This provides a potential V to wiring FCB[1] and wiring FCB[3] through wiring FCB[m]. 0B By providing this, and by having circuit WRWD provide a high-level potential to wiring WRWL[2] and a low-level potential to wiring WRWL[1] and wiring WRWL[3] through wiring WRWL[m], the memory cell MC located in the second row of the memory cell array MCA can be selected as the read source.

[0244] Furthermore, between time U26 and time U27, focusing on the second row, column j of the memory cell array MCA, a conductive state is established between the second terminal of transistor M1 of memory cell MC[2,j] and the wiring WRDL[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJA of memory cell MC[2,j] flows to the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes according to the voltage division applied to the FTJ element FJA of memory cell MC[2,j]. In other words, information corresponding to Da[2,j] (e.g., current or voltage) is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of memory cell MC[2,j].

[0245] Furthermore, between time U26 and time U27, focusing on the second row, column j of the memory cell array MCA, a conductive state is established between the second terminal of transistor M1b of memory cell MC[2,j] and the wiring WRDLb[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJAb of memory cell MC[2,j] flows through the wiring WRDLb[j]. Alternatively, the potential of the wiring WRDLb[j] changes according to the voltage division applied to the FTJ element FJAb of memory cell MC[2,j]. In other words, information corresponding to Db[2,j] (e.g., current or voltage) is transmitted to the wiring WRDLb[j] as data held in the FTJ element FJAb of memory cell MC[2,j].

[0246] Furthermore, between time U23 and time U24, data held by memory cells MC[2,1] through MC[2,n] located in the second row of the memory cell array MCA is transmitted for memory cells MC other than column j, in the same manner as described above.

[0247] Specifically, for example, data Da[2,1] and Db[2,1] are read from memory cell MC[2,1], and data Da[2,n] and Db[2,n] are read from memory cell MC[2,n]. At this time, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD, Da[2,1] and Db[2,1] held in memory cell MC[2,1] can be read. On the other hand, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD, Da[2,n] and Db[2,n] held in memory cell MC[2,n] can be read.

[0248] Between time U28 and time U29, data read operations are performed from memory cells MC located in the third row to the (m-1)th row of the memory cell array MCA, similar to the data read operations performed from the first row of the memory cell array MCA between time U22 and time U25, and from the second row of the memory cell array MCA between time U25 and time U28.

[0249] Between time U29 and time U32, circuit FECD has a potential V on wiring FCA[m]. M Give a potential V to the wiring FCB[m]. 0B This provides a potential V. Furthermore, circuit FECD provides a potential V to wiring FCA[1] through wiring FCA[m-1]. 0A This provides a potential V to wiring FCB[1] to wiring FCB[m-1]. 0B This is given. At this time, between wiring FCA[m] and wiring FCB[m], V M-V 0B Because a voltage is applied, a voltage divide of this voltage is applied to each of the FTJ elements FJA and transistor M6 of the first row of memory cells MC[m,1] to MC[m,n] in the memory cell array MCA. Similarly, a voltage divide of this voltage is applied to each of the FTJ elements FJAb and transistor M6b of the m row of memory cells MC[m,1] to MC[m,n] in the memory cell array MCA. Furthermore, the voltage divide applied to FTJ element FJA is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJA, and the voltage divide applied to FTJ element FJAb is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJAb. In other words, the voltage divide applied to each of the FTJ elements FJA and FTJ elements FJAb is determined by the data written to their respective memory cells MC.

[0250] Between time U30 and time U31, circuit WRWD provides a high-level potential to wiring WRWL[m]. Circuit WRWD also provides a low-level potential to wiring WRWL[1] through wiring WRWL[m-1]. As a result, in the memory cell array MCA, a high-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[m,1] through MC[m,n] located in row m, causing transistors M1 and M1b in each of the memory cells MC[m,1] through MC[m,n] to be in the ON state. Furthermore, in the memory cell array MCA, a low-level potential is applied to the gates of transistors M1 and M1b contained in each of the memory cells MC[1,1] through MC[m-1,n] located from row 1 to row m-1, causing transistors M1 and M1b in each of the memory cells MC[1,1] through MC[m-1,n] to be in the OFF state.

[0251] In other words, the circuit FECD has a potential V on the wiring FCA[m]. M Give a potential V to the wiring FCB[m]. 0BThis provides a potential V to wiring FCA[1] to wiring FCA[m-1]. 0A This provides a potential V to wiring FCB[1] to wiring FCB[m-1]. 0B By providing this, and by having circuit WRWD provide a high-level potential to wiring WRWL[m] and a low-level potential to wiring WRWL[1] to wiring WRWL[m-1], it is possible to select memory cell MC located in the m-th row of memory cell array MCA as the read source.

[0252] Furthermore, focusing on the m-th row and j-th column of the memory cell array MCA between time U30 and time U31, a conductive state is established between the second terminal of transistor M1 of memory cell MC[m,j] and the wiring WRDL[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJA of memory cell MC[m,j] flows to the wiring WRDL[j]. Alternatively, the potential of the wiring WRDL[j] changes according to the voltage division applied to the FTJ element FJA of memory cell MC[m,j]. In other words, information corresponding to Da[m,j] (e.g., current or voltage) is transmitted to the wiring WRDL[j] as data held in the FTJ element FJA of memory cell MC[m,j].

[0253] Furthermore, focusing on the m-th row and j-th column of the memory cell array MCA between time U30 and time U31, a conductive state is established between the second terminal of transistor M1b of memory cell MC[m,j] and the wiring WRDLb[j]. As a result, a current corresponding to the voltage division applied to the FTJ element FJAb of memory cell MC[m,j] flows through the wiring WRDLb[j]. Alternatively, the potential of the wiring WRDLb[j] changes according to the voltage division applied to the FTJ element FJAb of memory cell MC[m,j]. In other words, information corresponding to Db[m,j] (e.g., current or voltage) is transmitted to the wiring WRDLb[j] as data held in the FTJ element FJAb of memory cell MC[m,j].

[0254] Furthermore, between time U30 and time U31, data held by memory cells MC[m,1] through MC[m,n] located in the m-th row of the memory cell array MCA is transmitted for memory cells MC other than column j, in the same manner as described above.

[0255] Specifically, for example, data Da[m,1] and Db[m,1] are read from memory cell MC[m,1], and data Da[m,n] and Db[m,n] are read from memory cell MC[m,n]. At this time, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[1] and wiring WRDLb[1] using a circuit RDD, the Da[m,1] and Db[m,1] held in memory cell MC[m,1] can be read. On the other hand, by acquiring information (e.g., current or voltage) transmitted to wiring WRDL[n] and wiring WRDLb[n] using a circuit RDD, the Da[m,n] and Db[m,n] held in memory cell MC[m,n] can be read.

[0256] The operations performed from time U21 to time U32 allow D[1,1] to D[m,n] to be read from each of the memory cells MC[1,1] to MC[m,n] included in the memory cell array MCA.

[0257] In the timing chart of Figure 11, as an operation after the completion of the data read operation from memory cells MC[1,1] to MC[m,n] (operation between time U32 and time U33), circuit WRWD applies a low-level potential to wiring WRWL[1] to wiring WRWL[m] as an example. Also, circuit FECD applies a potential V to wiring FCA[1] to wiring FCA[m] and wiring FCB[1] to wiring FCB[m] as an example. 0A , and potential V 0B This is provided. In addition, each of the wirings WRDL[1] through WRDL[n] is given a ground potential as an example.

[0258] <<Example of reading operation 2>> Next, we will describe an example of data reading operation from the memory cell MC of the storage device 100, which differs from the timing chart in Figure 11.

[0259] The timing chart shown in Figure 12 shows an example of a read operation that differs from the read operation example in the timing chart of Figure 11. Similar to the timing chart of Figure 11, the timing chart of Figure 12 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33, and in the vicinity of that time.

[0260] The timing chart readout operation in Figure 12 is performed when each of the wirings FCA[1] to FCA[m] between time U22 and time U32 is at potential V M This differs from the timing chart reading operation in Figure 11.

[0261] In the timing chart of Figure 12, between time U22 and time U32, V is applied to each of the wiring FCA[1] to wiring FCA[m]. M The input is made, and V is input to each of the wiring FCB[1] to wiring FCB[m]. 0BBecause this is input, between time U22 and time U32, the potential of the second terminal of each transistor M1 in memory cell MC[1,1] to memory cell MC[m,n] is determined by the polarization direction of the ferroelectric material contained in the FTJ element FJA of that memory cell MC. Similarly, the potential of the second terminal of each transistor M1b in memory cell MC[1,1] to memory cell MC[m,n] is determined by the polarization direction of the ferroelectric material contained in the FTJ element FJAb of that memory cell MC. In other words, the potential of the second terminals of transistors M1 and M1b will be the potential corresponding to the data held in each memory cell MC.

[0262] Furthermore, in this example of operation, when selecting a memory cell MC to read from the memory cell array MCA, a high-level potential can be input from circuit WRWD to one of the wirings WRWL[1] to WRWL[m], and a low-level potential can be input to the remaining wirings. For example, as shown in the timing chart of Figure 12, between time U23 and time U24, a high-level potential can be applied to wiring WRWL[1] and a low-level potential can be applied to wirings WRWL[2] to WRWL[m], thereby allowing the data held in the memory cell MC located in the first row of the memory cell array MCA to be read. Similarly, between time U26 and time U27, by applying a high-level potential to wiring WRWL[2] and a low-level potential to wiring WRWL[1] and wiring WRWL[3] through wiring WRWL[m], the data held in the memory cell MC located in the second row of the memory cell array MCA can be read. Between time U30 and time U31, by applying a high-level potential to wiring WRWL[m] and a low-level potential to wiring WRWL[1] through wiring WRWL[m-1], the data held in the memory cell MC located in the m-th row of the memory cell array MCA can be read.

[0263] In other words, in the example of timing chart operation in Figure 12, the potential fluctuations of wiring WRWL[1] to wiring WRWL[m] can be the same as in the example of timing chart operation in Figure 11.

[0264] In the operation of the timing chart in Figure 12, when reading multiple memory cells MC included in the memory cell array MCA, it is not necessary to change the potential of the wiring FCA[1] to wiring FCA[m] and the wiring FCB[1] to wiring FCB[m] for each memory cell MC being read. In other words, by applying the example operation of the timing chart in Figure 12, the circuit FECD can be configured without a circuit that selects the wiring to which signals are transmitted, such as a selector.

[0265] <<Example of reading operation 3>> Next, we will describe an example of data reading operation from the memory cell MC of the storage device 100, which differs from the timing charts in Figures 11 and 12.

[0266] The timing chart shown in Figure 13 illustrates an example of a write operation that differs from the write operation examples in the timing charts of Figures 11 and 12. Similar to the timing charts of Figures 11 and 12, the timing chart in Figure 13 shows the changes in potential of wiring WRWL[1], wiring WRWL[2], wiring WRWL[m], wiring FCA[1], wiring FCB[1], wiring FCA[2], wiring FCB[2], wiring FCA[m], wiring FCB[m], wiring WRDL[1], wiring WRDLb[1], wiring WRDL[2], wiring WRDLb[2], wiring WRDL[n], and wiring WRDLb[n] between time U21 and time U33, and in the vicinity of that time.

[0267] The timing chart readout operation in Figure 13 differs from the timing chart readout operation in Figure 11 in that, between time U22 and time U32, each of the wiring WRWL[1] to wiring WRWL[m] is at a high potential level, and the potential fluctuations of each of the wiring FCA[1] to wiring FCA[m] and wiring FCB[1] to wiring FCB[m] occur between time U22 and time U32.

[0268] Between time U22 and time U32 in the timing chart of Figure 13, a high-level potential is input to each of the wirings WRWL[1] to WRWL[m]. Therefore, between time U22 and time U32, a high-level potential is input to the gates of transistors M1 and M1b of memory cells MC[1,1] to MC[m,n]. As a result, transistors M1 and M1b of memory cells MC[1,1] to MC[m,n] are turned ON.

[0269] Furthermore, between time U23 and time U24 in the timing chart of Figure 13, there is a potential V in wiring FCA[1]. M Given, the potential V is applied to the wiring FCB[1]. 0B A potential V is given. Also, the potential V is given to wiring FCA[2] to wiring FCA[m]. 0A A potential V is given, and the wiring FCB[2] to wiring FCB[m] is given 0B Given that, V M -V 0BBecause a voltage is applied, a divided voltage of this voltage is applied to each of the FTJ elements FJA and transistor M6 of the first row of memory cells MC[1,1] to MC[1,n] in the memory cell array MCA. Similarly, a divided voltage of this voltage is applied to each of the FTJ elements FJAb and transistor M6b of the first row of memory cells MC[1,1] to MC[1,n] in the memory cell array MCA. Furthermore, the divided voltage applied to FTJ element FJA is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJA, and the divided voltage applied to FTJ element FJAb is determined by the polarization direction of the ferroelectric dielectric contained in FTJ element FJAb. In other words, the divided voltage applied to each of the FTJ elements FJA and FTJ elements FJAb is determined by the data written to their respective memory cells MC.

[0270] Furthermore, since the transistor M1 of each memory cell MC[1,1] to MC[1,n] is in the ON state, the potential of each wiring WRDL[1] to WRDL[n] is determined according to the voltage division applied to each FTJ element FJA of each memory cell MC[1,1] to MC[1,n]. Similarly, since the transistor M1b of each memory cell MC[1,1] to MC[1,n] is in the ON state, the potential of each wiring WRDL[1] to WRDL[n] is determined according to the voltage division applied to each FTJ element FJAb of each memory cell MC[1,1] to MC[1,n]. For this reason, information corresponding to Da[1,1] to Da[1,n] (e.g., current or voltage) is transmitted to each wiring WRDL[1] to WRDL[n] as data held in the memory cell MC[1,1] to MC[1,n]. Furthermore, information corresponding to Db[1,1] to Db[1,n] (for example, current or voltage) is transmitted to each of the wirings WRDLb[1] to WRDLb[n] as data held in the memory cells MC[1,1] to MC[1,n].

[0271] On the other hand, the potential V is present in wiring FCA[2] to wiring FCA[m]. 0AA potential V is given, and the wiring FCB[2] to wiring FCB[m] is given 0B Given that, V is given for each of the FTJ elements FJA and transistor M6 of the memory cells MC from the 2nd row to the mth row of the memory cell array MCA. 0A -V 0B A partial pressure is applied. V 0A -V 0B When the threshold voltage is set to 0V or near 0V, the potential of the second terminal of transistor M1 in each of the memory cells MC[1,1] to MC[1,n] can also be set to 0V or near 0V. In other words, if the threshold voltage of transistor M1 is at an appropriate value, transistor M1 will be in the off state, and therefore, in the memory cells MC from the second row to the m row of the memory cell array MCA, there will be no conduction between the second terminal of transistor M1 and the wiring WRDL[1] to WRDL[n], and information corresponding to the data held in the memory cells MC (e.g., current, voltage, etc.) will not flow to the wiring WRDL[1] to WRDL[n]. Also, similarly, V 0A -V 0B When the threshold voltage is set to 0V or near 0V, the potential of the second terminal of transistor M1b in each of the memory cells MC[1,1] to MC[1,n] can also be set to 0V or near 0V. Therefore, if the threshold voltage of transistor M1b is at an appropriate value, transistor M1 will be in the off state, and in the memory cells MC from the second row to the mth row of the memory cell array MCA, there will be no conduction between the second terminal of transistor M1b and the wiring WRDLb[1] to WRDLb[n]. For this reason, information corresponding to the data held in the memory cells MC (e.g., current, voltage, etc.) will not flow to the wiring WRDLb[1] to WRDLb[n].

[0272] Furthermore, in this example of operation, when reading data from the second row of memory cell MC in the memory cell array MCA, a potential V is applied to the wiring FCA[2] as shown between time U26 and time U27. M This gives a potential V to the wiring FCB[2]. 0BYou should provide the following. Also, when reading data from the m-th memory cell MC of the memory cell array MCA, the potential V should be applied to the wiring FCA[m] as shown between time U30 and time U31. M Give a potential V to the wiring FCB[m]. 0B You should give it to them.

[0273] In other words, in the example timing chart shown in Figure 13, wiring FCA[1] to wiring FCA[m] functions as a selection signal line for selecting the memory cell MC to be read from the memory cell array MCA. Therefore, in the example timing chart shown in Figure 13, it is not necessary to change the potential for each memory cell MC to be read in each of the wirings WRWL[1] to wiring WRWL[m]. For this reason, by applying the example timing chart shown in Figure 13, the RDD circuit can be configured without a circuit for selecting wiring that transmits signals, such as a selector.

[0274] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0275] (Embodiment 3) This embodiment describes a case where the memory device described in the above embodiment is treated as an arithmetic circuit.

[0276] <Arithmetic circuit 1> As an example, consider the memory device 100A in Figure 14 to which the memory cell MC in Figure 5A is applied. In this case, the memory device 100A, which functions as an arithmetic circuit, can perform a sum-of-products operation on multiple first data and multiple second data. Each of the multiple first data is either "0" or "1", and each of the multiple second data is either "0" or "1".

[0277] The memory device 100A shown in Figure 14 is configured by adding the circuit RWDA to the memory device 100 in Figure 8. The circuit RWDA functions, for example, as a read word line driver circuit. The circuit RWDA also functions as a circuit that transmits second data to the memory cell MC included in the memory cell array MCA. In other words, in this case, the wiring RWLA[1] to RWLA[m] (corresponding to the wiring RWLA in Figure 5A) functions as wiring that transmits the second data. The operation of the memory cell MC, which performs the product calculation between the first data and the second data, will be described later.

[0278] The first data is, for example, held in multiple memory cells MC included in the memory cell array MCA of the storage device 100A. That is, the multiple memory cells MC included in the memory cell array MCA hold either "0" or "1" as data. Specifically, for example, as described in the description of the data writing operation of Embodiment 1, the value of the first data can be determined by the direction of polarization generated in each of the FTJ elements FJA and FJAb included in the memory cell MC.

[0279] Here, as an example, the relationship between the value of the first data written to multiple memory cells MC included in the memory cell array MCA of the storage device 100 and the direction of polarization generated in each of the FTJ elements FJA and FJAb is defined as shown in the table below.

[0280] [Table 2]

[0281] In other words, for example, when writing the first data "1" to the memory cell MC, as shown in the data writing operation example of Embodiment 1, a potential V1 is input to the memory cell MC from the circuit WDD via the wiring WRDL, and a potential V0 is input to the memory cell MC via the wiring WRDLb, thereby generating (rewriting) the polarization of the FTJ elements FJA and FJAb contained in the memory cell MC in a predetermined direction. Also, for example, when writing the first data "0" to the memory cell MC, as shown in the data writing operation example of Embodiment 1, a potential V0 is input to the memory cell MC from the circuit WDD via the wiring WRDL, and a potential V1 is input to the memory cell MC via the wiring WRDLb, thereby generating (rewriting) the polarization of the FTJ elements FJA and FJAb contained in the memory cell MC in a predetermined direction.

[0282] Furthermore, when the first data "1" is written to the memory cell MC, the operation between time T23 and time T25 in the timing chart of Figure 3 of the data read operation example of Embodiment 1 is performed, and the potential of the output terminal of the FTJ element FJA is V 0B Therefore, the potential at the output terminal of the FTJ element FJAb is V M Therefore, the gate potential of transistor M7 included in the memory cell MC is V M This results in the following: At this time, a low-level potential is applied to the first terminal of transistor M7, for example, from wiring VCE, and a high-level potential is applied to the second terminal of transistor M7, for example, from wiring RDL via transistor M8, so that a gate-source voltage (V) is applied between the source and drain of transistor M7. M A current flows in accordance with the potential difference between the low-level potential and the high-level potential. Also, when the first data "0" is written to the memory cell MC, the operation between time T23 and time T25 in the timing chart of Figure 3 of the data read operation example of Embodiment 1 is performed, and the potential of the output terminal of the FTJ element FJA is V M Therefore, the potential at the output terminal of the FTJ element FJAb is V 0BTherefore, the gate potential of transistor M7 included in the memory cell MC is V 0B This results in the following: At this time, a low-level potential is applied to the first terminal of transistor M7, for example, from wiring VCE, and a high-level potential is applied to the second terminal of transistor M7, for example, from wiring RDL via transistor M8, so that a gate-source voltage (V) is applied between the source and drain of transistor M7. 0B A current flows according to the potential difference between the low-level potential and the high-level potential. In this embodiment, when the first data "0" is written to the memory cell MC, that is, when the potential of the output terminal (gate of transistor M7) of the FTJ element FJAb is V 0B In this case, we will explain it as if no current flows between the first and second terminals of transistor M7 (sometimes rephrased as transistor M7 being in the off state, or a current of 0 flowing between the first and second terminals of transistor M7).

[0283] The second data can be, for example, a value corresponding to the potential applied to the wiring RWLA. For example, when the second data is "0", the wiring RWLA is given a low potential by the circuit WRWD, and when the second data is "1", the wiring RWLA is given a high potential by the circuit WRWD.

[0284] Here, we will explain an example of the operation of the memory cell MC in response to the first data held in the memory cell MC and the second data input to the memory cell MC.

[0285] When the first data held in the memory cell MC is "1", as described above, the gate-source voltage (V) of transistor M7 is present between the first and second terminals of transistor M7. M A current flows in an amount corresponding to the potential difference between the current and the low-level potential. ut Let's assume that when the first data held in the memory cell MC is "0", as described above, no current flows between the first and second terminals of transistor M7 (a current of 0 flows).

[0286] Furthermore, when the second data is "0," that is, when a low-level potential is input from the wiring RWLA to the memory cell MC, transistor M1 included in the memory cell MC is in the OFF state. On the other hand, when the second data is "1," that is, when a high-level potential is input from the wiring RWLA to the memory cell MC, transistor M1 included in the memory cell MC is in the ON state.

[0287] From the above, when the first data is "1" and the second data is "1", there is a conductive state between wiring VCE and wiring RDL, and therefore the current I ut A current flows. Also, when at least one of the first data and the second data is "0", transistor M7 is in the off state and / or transistor M8 is in the off state, so no current flows between the memory cell MC and the wiring RDL.

[0288] In other words, the amount of current flowing through the wiring RDL and circuit RDD is determined by the value of the first data and the value of the second data, as shown in the table below.

[0289] [Table 3]

[0290] In other words, when the product of the first data and the second data is "1", the result of that calculation is that a current I is transmitted from the memory cell MC to the circuit RDD via the wiring RDL. ut When a current flows and the product of the first data and the second data is "0", a current of 0 flows between the memory cell MC and the circuit RDD as a result of the calculation (no current flows between the memory cell MC and the circuit RDD). In this way, the memory cell MC can calculate the product of the first data and the second data by holding the first data in the memory cell MC and then inputting the second data into the memory cell MC.

[0291] Next, consider the case where, with each of the multiple memory cells MC included in the memory cell array MCA holding first data, multiple second data are supplied simultaneously to each of the wiring RWLA[1] through RWLA[m]. Let W[i,j] be the first data held in the memory cell MC[i,j] (where i is an integer between 1 and m, and j is an integer between 1 and n), and let X[i] be the second data supplied to the wiring RWLA[i].

[0292] For example, in the j-th column, when X[1] to X[m] is input as second data from wiring RWLA[1] to wiring RWLA[m] to each of the memory cells MC[1,j] to MC[m,j], the calculation W[1,j] × X[1] to W[m,j] × X[m] is performed in each of the memory cells MC[1,j] to MC[m,j].

[0293] For example, when the product of the first data and the second data is "1", the amount of current flowing from the memory cell MC to the wiring RDL[j] is I ut This is the result. Also, for example, when the product of the first data and the second data is "0", the amount of current flowing between the memory cell MC and the wiring WRDL[j] is 0 (no current flows between the memory cell MC and the wiring WRDL[j]).

[0294] Here, let p be the number of memory cells MC[1,j] through MC[m,j] whose product of the first data and the second data is "1", and let q be the number of memory cells MC[1,j] whose product of the first data and the second data is "0". Then the total current flowing from the wiring RDL to the circuit RDD is p × I ut +q × 0 = p × I ut This is the result. However, p and q are positive integers satisfying p+q=m.

[0295] Here, the RDD circuit, by having functions such as a current-voltage conversion circuit, can, for example, convert the sum of the currents flowing through wiring RDL[j] into a voltage value. In other words, the current p × I is the result of the sum-of-products performed in the j-th column memory cell MC[1,j] to memory cell MC[m,j] of the memory cell array MCA. ut It can output this as a voltage value.

[0296] Furthermore, the RDD circuit may have a function to perform further function operations using the sum-of-products result. For example, the RDD circuit can perform operations on an artificial neural network by performing activation function operations using the sum-of-products result. Examples of such activation functions include the sigmoid function, tanh function, softmax function, ReLU function, and threshold function.

[0297] Furthermore, while the above describes the result of a sum-of-accumulate operation between multiple first data and multiple second data in memory cells MC[1,j] to MC[m,j] located in column j, the multiple second data are transmitted by wiring RWLA[1] to RWLA[m] that extends in the row direction, so sum-of-accumulate operations can also be performed in columns other than column j. In other words, when the memory device 100A is used as a circuit to perform sum-of-accumulate operations, it is possible to perform sum-of-accumulate operations simultaneously for the number of columns (n ​​in Figure 14).

[0298] <Arithmetic circuit 2> In the above-described arithmetic circuit, the calculation when the first data is binary ("0" or "1") and the second data is binary ("0" or "1") was explained as an example. However, in one aspect of the present invention, by changing the configuration of the arithmetic circuit, calculations can be performed that handle multi-level values, analog values, and so on.

[0299] Figure 15 shows an example of a circuit configuration that can perform a sum-of-products operation on multiple first data points that can take either "-1", "0", or "1", and multiple second data points that can take either "-1", "0", or "1".

[0300] The arithmetic circuit 110 includes a memory cell array MCA, a circuit WDD, a circuit RDD, a circuit RWDA, a circuit WRWD, and a circuit FECD.

[0301] A memory cell array (MCA) has multiple memory cells (MCs). In the memory cell array (MCA), the multiple memory cells (MCs) are arranged in a matrix of m rows and n columns (where m and n are integers greater than or equal to 1). In Figure 15, the memory cell (MC) located in row i and column j (where i is an integer between 1 and m, and j is an integer between 1 and n) is shown as memory cell (MC)[i,j]. Figure 15 also shows memory cell (MC)[1,j] and memory cell (MC)[m,j] as examples.

[0302] The memory cell MC has a circuit MP and a circuit MPr. The circuit configurations of the MP and MPr will be described later.

[0303] Furthermore, the memory cell array MCA of the arithmetic circuit 110 has wirings WRDL[1] to WRDL[n], WRDLb[1] to WRDLb[n], WRDLr[1] to WRDLr[n], and WRDLbr[1] to WRDLbr[n] extending in the column direction. Note that the [j] attached to wiring WRDL, wiring WRDLb, wiring WRDLr, and wiring WRDLbr indicates that it is the wiring in the j-th column. In addition, wirings WRWL[1] to WRWL[m], RWLAa[1] to RWLAa[m], RWLAb[1] to RWLAb[m], FCA[1] to FCA[m], and FCB[1] to FCB[m] extending in the row direction. Note that the [i] attached to wiring WRWL, RWLAa, RWLAb, FCA, and FCB indicates that it is the i-th wiring.

[0304] In memory cell MC[1,j], circuit MP[1,j] is electrically connected to wiring WRDL[j], wiring WRDLb[j], wiring WRWL[1], wiring FCA[1], wiring FCB[1], wiring RWLAa[1], and wiring RWLAb[1]. Also, circuit MPr[1,j] is electrically connected to wiring WRDLr[j], wiring WRDLbr[j], wiring WRWL[1], wiring FCA[1], wiring FCB[1], wiring RWLAa[1], and wiring RWLAb[1].

[0305] Furthermore, in memory cell MC[m,j], circuit MP[m,j] is electrically connected to wiring WRDL[j], wiring WRDLB[j], wiring WRWL[m], wiring FCA[m], wiring FCB[m], wiring RWLAa[m], and wiring RWLAb[m]. Also, circuit MPr[m,j] is electrically connected to wiring WRDLR[j], wiring WRDLbr[j], wiring WRWL[m], wiring FCA[m], wiring FCB[m], wiring RWLAa[m], and wiring RWLAb[m].

[0306] Next, we will describe an example configuration of the circuit MP and circuit MPr included in the memory cell MC.

[0307] Figure 16 shows an example of a circuit configuration that can be applied to memory cells MC included in the memory cell array MCA of the arithmetic circuit 110 in Figure 15.

[0308] The circuit MP shown in Figure 16 is a modified version of the memory cell MC in Figure 5A described in Embodiment 1, with the addition of a transistor M8m to the memory cell MC in Figure 5A.

[0309] The first terminal of transistor M8m is electrically connected to the second terminal of transistor M7 and the first terminal of transistor M8, and the second terminal of transistor M8m is electrically connected to wiring RDLr[j]. In addition, the gate of transistor M8 is electrically connected to wiring RWLAa, and the gate of transistor M8m is electrically connected to wiring RWLAb.

[0310] Furthermore, the circuit MPr shown in Figure 16 has the same configuration as the circuit MP. Therefore, the circuit elements of circuit MPr are denoted with "r" to distinguish them from those of circuit MP.

[0311] In circuit MPr, the first terminal of transistor M1r is electrically connected to wiring WRLr, and the gate of transistor M1r is electrically connected to wiring WRWL. The input terminal of FTJ element FJAr is electrically connected to wiring FCA. The output terminal of FTJ element FJAr is electrically connected to the second terminal of transistor M1r, the first terminal of transistor M6r, and the gate of transistor M6br. The second terminal of transistor M6r is electrically connected to wiring FCB. The first terminal of transistor M1br is electrically connected to wiring WRDLbr, and the gate of transistor M1br is electrically connected to wiring WRWL. The input terminal of FTJ element FJAbr is electrically connected to wiring FCA. The output terminal of FTJ element FJAbr is electrically connected to the second terminal of transistor M1br, the first terminal of transistor M6br, the gate of transistor M6r, and the gate of transistor M7r. The second terminal of transistor M6br is electrically connected to wiring FCB. Furthermore, the first terminal of transistor M7r is electrically connected to wiring VCEr. The first terminal of transistor M8r is electrically connected to the second terminal of transistor M7 and the first terminal of transistor M8mr. Additionally, the second terminal of transistor M8r is electrically connected to wiring RDLr, and the second terminal of transistor M8mr is electrically connected to wiring RDL[j]. Furthermore, the gate of transistor M8m is electrically connected to wiring RWLAa, and the gate of transistor M8mr is electrically connected to wiring RWLAb.

[0312] Wiring WRDL and wiring WRDLr each function, for example, as wiring for transmitting first data to be written to circuit MP and circuit MPr of the memory cell MC. This first data is represented by a set of signals transmitted to wiring WRDL and wiring WRDLr.

[0313] Furthermore, wiring RWLAa and wiring RWLAb function, for example, as wiring for transmitting second data. This second data is represented by a set of signals transmitted to wiring RWLAa and wiring RWLAb.

[0314] Furthermore, the wiring RDL and wiring RDLr function, for example, as wiring that transmits the calculation results of the memory cell MC's circuit MP and circuit MPr as data.

[0315] Furthermore, the WRWL wiring may function, for example, as a wiring for selecting the memory cell MC to which the first data will be written. In other words, the WRWL wiring may also function as a write word line.

[0316] Each of the wirings FCA and FCB functions, for example, as a wiring that provides a potential sufficient to cause polarization in the ferroelectric material contained in each of the FTJ elements FJA, FJAb, FJAr, and FJAbr when writing the first data to the circuit MP and circuit MPr, similar to the memory cell MC in Figure 1 described in Embodiment 1. Furthermore, each of the wirings FCA and FCB also functions, for example, as a wiring that provides a potential sufficient to not change the polarization of the dielectric when calculating the product of the first data and the second data in the memory cell MC. This potential may also be a pulse voltage.

[0317] Each of the wirings VCE and VCEr functions, for example, as wiring that provides a constant voltage, similar to the memory cell MC in Figure 5A described in Embodiment 1. This constant voltage can be, for example, a low-level potential or ground potential. The voltages provided by wirings VCE and VCEr may also be pulse voltages.

[0318] Circuit WDD is electrically connected to wiring WRDL[1] through WRDL[n], wiring WRDLb[1] through WRDLb[n], wiring WRDLR[1] through WRDLr[n], and wiring WRDLbr[1] through WRDLbr[n]. Circuit WRWD is electrically connected to wiring WRWL[1] through WRWL[m]. Circuit RWDA is electrically connected to wiring RWLAa[1] through RWLAa[m], and wiring RWLAb[1] through RWLAb[m]. Circuit FECD is electrically connected to wiring FCA[1] through FCA[m] and wiring FCB[1] through FCB[m]. Circuit RDD is electrically connected to wiring RDL[1] through RDL[n] and wiring RDLr[1] through RDLr[1].

[0319] For the FECD circuit, refer to the FECD circuit of the storage device 100 shown in Figure 8, which was described in Embodiment 2.

[0320] As an example, the circuit WDD functions as a circuit that supplies first data to wiring WRDL[j], wiring WRDLb[j], wiring WRDLr[j], and wiring WRDLbr[j] in the j-th column. Alternatively, the circuit WDD may be configured to supply first data to wiring WRDL[1] through wiring WRDL[n], wiring WRDLb[1] through wiring WRDLb[n], wiring WRDLr[1] through wiring WRDLr[n], and wiring WRDLbr[1] through wiring WRDLbr[n] all at once.

[0321] Circuit WRWD functions, for example, as wiring to select the memory cell MC to which the first data will be written. In other words, in the configuration shown in Figure 15, circuit WRWD functions as a circuit to select the word line during writing.

[0322] As an example, circuit RWDA functions as a circuit that supplies second data to wiring RWLAa[i] and wiring RWLAb[i] in row i. Alternatively, circuit RWDA may be configured to supply second data to wiring RWLAa[1] through wiring RWLAa[m] and wiring RWLAb[1] through wiring RWLAb[m] all at once.

[0323] Here, as the first data, the potential supplied to the circuit MP and circuit MPr of the memory cell MC are defined as follows.

[0324] When the memory cell MC holds "1" as the first data, potential is supplied to circuit MP from circuit WDD via wiring WRDL and wiring WRDLb respectively, so that the polarization direction of FTJ element FJA included in circuit MP is positive and the polarization direction of FTJ element FJAb is negative. At the same time, potential is supplied to circuit MPr from circuit WDD via wiring WRDLr and wiring WRDLbr respectively, so that the polarization direction of FTJ element FJAr included in circuit MPr is negative and the polarization direction of FTJ element FJAbr included in circuit MPr is positive. Furthermore, when the memory cell MC holds "-1" as the first data, potential is supplied to circuit MP from circuit WDD via wiring WRDL and wiring WRDLb respectively so that the polarization direction of FTJ element FJA included in circuit MP is negative and the polarization direction of FTJ element FJAb is positive. Additionally, potential is supplied to circuit MPr from circuit WDD via wiring WRDLr and wiring WRDLbr respectively so that the polarization direction of FTJ element FJAr included in circuit MPr is positive and the polarization direction of FTJ element FJAbr is negative. Furthermore, when the memory cell MC holds "0" as the first data, potential is supplied from the circuit WDD to the circuit MP via wiring WRDL and wiring WRDLb respectively, so that the polarization direction of the FTJ element FJA included in the circuit MP is negative and the polarization direction of the FTJ element FJAb is positive. Additionally, potential is supplied from the circuit WDD to the circuit MPr via wiring WRDLr and wiring WRDLbr respectively, so that the polarization direction of the FTJ element FJAr included in the circuit MPr is negative and the polarization direction of the FTJ element FJAbr is positive.

[0325] Furthermore, as a second data set, the potentials supplied to wiring RWLAa and wiring RWLAb are defined as follows.

[0326] When "1" is input as the second data to the memory cell MC, a high-level potential is supplied from wiring RWLAa to circuit MP and circuit MPr, and a low-level potential is supplied from wiring RWLAb to circuit MP and circuit MPr. When "-1" is input as the second data to the memory cell MC, a low-level potential is supplied from wiring RWLAa to circuit MP and circuit MPr, and a high-level potential is supplied from wiring RWLAb to circuit MP and circuit MPr. When "0" is input as the second data to the memory cell MC, a low-level potential is supplied from wiring RWLAa to circuit MP and circuit MPr, and a low-level potential is supplied from wiring RWLAb to circuit MP and circuit MPr.

[0327] In other words, when the memory cell MC receives "1" as the second data, in circuit MP, transistor M8 is ON and transistor M8m is OFF, and in circuit MPr, transistor M8r is ON and transistor M8mr is OFF. As a result, there is conduction between circuit MP and wiring RDL[j], conduction between circuit MPr and wiring RDLr[j], non-conduction between circuit MP and wiring RDLr[j], and non-conduction between circuit MPr and wiring RDL[j]. Furthermore, when "-1" is input as the second data to the memory cell MC, in circuit MP, transistor M8 is in the off state and transistor M8m is in the on state, and in circuit MPr, transistor M8r is in the off state and transistor M8mr is in the on state. As a result, there is no conduction between circuit MP and wiring RDL[j], there is no conduction between circuit MPr and wiring RDLr[j], there is conduction between circuit MP and wiring RDLr[j], and there is conduction between circuit MPr and wiring RDL[j]. Furthermore, when "0" is input as the second data to the memory cell MC, in circuit MP, transistor M8 and transistor M8m are in the off state, and in circuit MPr, transistor M8r and transistor M8mr are in the off state. As a result, there is no conduction between circuit MP and wiring RDL[j], there is no conduction between circuit MPr and wiring RDLr[j], there is no conduction between circuit MP and wiring RDLr[j], and there is no conduction between circuit MPr and wiring RDL[j].

[0328] As described above, by defining the first data held in the memory cell MC and the second data input to the memory cell MC, the current flowing between the memory cell MC and the wiring RDL, or wiring RDLr, is as shown in the table below.

[0329] [Table 4]

[0330] In other words, when the product of the first data and the second data is "1", the result of that calculation is a current I between circuit MP or circuit MPr and wiring RDL. ut When a current flows and the product of the first data and the second data is "-1", the result of the calculation is that a current I flows between circuit MP or circuit MPr and wiring RDLr. ut When a current flows and the product of the first data and the second data is "0", as a result of the calculation, a current of 0 flows between circuit MP or circuit MPr and wiring RDL, and between circuit MP or circuit MPr and wiring RDLr (no current flows between circuit MP or circuit MPr and wiring RDL, and between circuit MP or circuit MPr and wiring RDLr). In this way, the memory cell MC can calculate the product of the first data and the second data by holding the first data in the memory cell MC and then inputting the second data into the memory cell MC.

[0331] Next, consider the case where, with each of the multiple memory cells MC included in the memory cell array MCA holding first data, multiple second data are supplied simultaneously to each of the wirings RWLAa[1] to RWLAa[m] and RWLAb[1] to RWLAb[m]. Let W[i,j] be the first data held in the memory cell MC[i,j] (where i is an integer between 1 and m, and j is an integer between 1 and n), and let X[i] be the second data supplied to the wirings RWLAa[i] and RWLAb[i].

[0332] For example, in the j-th column, when X[1] to X[m] is input as second data from wiring RWLAa[1] to wiring RWLAa[m] and wiring RWLAb[1] to wiring RWLAb[m] to each of the memory cells MC[1,j] to MC[m,j], the calculation W[1,j] × X[1] to W[m,j] × X[m] is performed in each of the memory cells MC[1,j] to MC[m,j].

[0333] Furthermore, since the product of the first data and the second data can be "1", "-1", or "0", let P be the number of memory cells MC[1,j] through MC[m,j] whose product of the first data and the second data is "1", Q be the number of memory cells MC whose product of the first data and the second data is "-1", and R be the number of memory cells MC whose product of the first data and the second data is "0" (P, Q, and R are all integers greater than or equal to 0 and satisfying P+Q+R=m). In this case, the sum of the currents flowing through wiring RDL[j] is P×I ut Therefore, the total amount of current flowing through the wiring RDLr[j] is Q × I ut This is the result.

[0334] Here, the circuit RDD is, for example, the current P × I flowing through the wiring RDL[j]. ut The current Q × I flowing through the wiring RDLr[j] ut By having a function to obtain the difference and convert that difference into a voltage value, the result of the sum-of-products operation between multiple first data and multiple second data in memory cell MC[1,j] to memory cell MC[m,j] can be output as the voltage value.

[0335] Furthermore, the RDD circuit may have a function to perform further function operations using the sum-of-products result. For example, the RDD circuit can perform operations on an artificial neural network by performing activation function operations using the sum-of-products result. Examples of such activation functions include the sigmoid function, tanh function, softmax function, ReLU function, and threshold function.

[0336] Furthermore, while the above describes the result of a sum-of-products operation between multiple first data and multiple second data in memory cells MC[1,j] to MC[m,j] located in column j, the multiple second data are transmitted by wiring RWLAa[1] to RWLAa[m] and wiring RWLAb[1] to RWLAb[m] which extend in the row direction. Therefore, sum-of-products operations can also be performed in columns other than column j. In other words, when performing a sum-of-products operation with the arithmetic circuit 110, it is possible to perform as many sum-of-products operations simultaneously as there are columns in the memory cell array MCA.

[0337] Furthermore, while the above explanation described the case where the first data is a trivalent value of "1", "0", and "-1", it may be possible to treat the first data as a binary, quadruple, or analog value by changing the operating method or circuit configuration.

[0338] Furthermore, while the above explanation described the case where the second data is a trivalent value of "1", "0", and "-1", by changing the operating method, circuit configuration, etc., the second data can be treated as a binary value, a quadruple or more value, or an analog value.

[0339] For example, in the operation of the above arithmetic circuit, the potential corresponding to the second data supplied to each of the wirings RWLAa and RWLAb is defined as a pulse voltage. In this case, when the pulse voltage input to either wiring RWLAa or RWLAb is a high-level potential, either transistor M8 and transistor M8r, or transistor M8m and transistor M8mr, will be in the ON state for the duration of the pulse voltage input.

[0340] Here, when the polarization direction of the FTJ element FJA included in circuit MP is positive, the polarization direction of the FTJ element FJAb is negative, and the polarization direction of the FTJ element FJAr included in circuit MPr is negative, and the polarization direction of the FTJ element FJAbr is positive (i.e., when the first data held in memory cell MC is "1"), current flows from circuit MP to either wiring RDL or wiring RDLr for the duration of the input time.

[0341] For example, consider the case where the memory cell MC holds "1" as the first data. Also, when the second data is "1", the input time T ut However, a high-level potential is applied to wiring RWLAa and a low-level potential is applied to wiring RWLAb. In this case, the amount of charge flowing between the memory cell MC circuit MP and wiring RDL is T. ut ×I MP As a result, the amount of charge flowing between the memory cell MC's circuit MPr and wiring RDL becomes 0, the amount of charge flowing between the memory cell MC's circuit MP and wiring RDLr becomes 0, and the amount of charge flowing between the memory cell MC's circuit MPr and wiring RDLr becomes 0.

[0342] Also, when the second data is "2", the input time is 2 × T. ut However, a high-level potential is applied to wiring RWLAa and a low-level potential is applied to wiring RWLAb. In this case, the amount of charge flowing between the memory cell MC circuit MP and wiring RDL is 2 × T. ut ×I MP As a result, the amount of charge flowing between the memory cell MC's circuit MPr and wiring RDL becomes 0, the amount of charge flowing between the memory cell MC's circuit MP and wiring RDLr becomes 0, and the amount of charge flowing between the memory cell MC's circuit MPr and wiring RDLr becomes 0.

[0343] Also, when the second data is "-2", the input time is 2 × T. ut However, a low-level potential is applied to wiring RWLAa and a high-level potential is applied to wiring RWLAb. In this case, the amount of charge flowing between the memory cell MC circuit MP and wiring RDL is 0, the amount of charge flowing between the memory cell MC circuit MPr and wiring RDL is 0, and the amount of charge flowing between the memory cell MC circuit MP and wiring RDLr is 2 × T ut ×I MP Therefore, the amount of charge flowing between the memory cell MC's circuit MPr and the wiring RDLr becomes 0.

[0344] As described above, by increasing or decreasing the input time of the pulse voltage applied to wiring RWLAa and wiring RWLAb, the amount of charge flowing between circuit MP or circuit MPr of the memory cell MC and wiring RDL, and the amount of charge flowing between circuit MP or circuit MPr of the memory cell MC and wiring RDLr can be changed. Specifically, since the amount of charge flowing through wiring RDL and wiring RDLr is proportional to the input time of the pulse voltage, by determining the input time according to the value of the second data, the memory cell MC can flow an amount of charge to wiring RDL or wiring RDLr corresponding to the result of the product of the first data and the second data, with the second data being a binary, quadrivalent, or analog value.

[0345] Furthermore, by configuring the RDD circuit to include a circuit (e.g., a QV conversion circuit, an integrating circuit, etc.) that converts the amount of charge flowing through wiring RDL and the amount of charge flowing through wiring RDLr into voltage values, the RDD circuit can obtain the amount of charge flowing through wiring RDL and the amount of charge flowing through wiring RDLr as voltage values.

[0346] Furthermore, by configuring the RDD circuit to have a circuit that compares, for example, a voltage value corresponding to the amount of charge flowing through wiring RDL and a voltage value corresponding to the amount of charge flowing through wiring RDLr, and outputs the comparison result as a voltage value, the RDD circuit can output the result of the sum-of-products operation between multiple first data and multiple second data in memory cell MC[1,j] to memory cell MC[m,j] as the said voltage value.

[0347] Furthermore, while the above example described the operation of supplying pulse voltages to wiring RWLAa and wiring RWLAb, the multiply-accumulate operation may also be an operation in which the pulse voltage is supplied to at least one of the wirings, such as wiring FCA and wiring FCB. For example, a predetermined voltage can be input as a pulse voltage to wiring FCA and wiring FCB at the timing when charge is flowed between the memory cell MC and wiring RDL and wiring RDLr. Alternatively, the multiply-accumulate operation may also be an operation in which the pulse voltage is supplied to at least one of the wirings, such as wiring VCE and wiring VCEr. For example, a predetermined voltage can be input as a pulse voltage to wiring VCE and wiring VCEr at the timing when charge is flowed between the memory cell MC and wiring RDL and wiring RDLr.

[0348] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0349] (Embodiment 4) This embodiment describes a memory cell different from the memory cell MC described in the above embodiment. This memory cell can be applied to a memory device, which is a semiconductor device according to one aspect of the present invention.

[0350] <Example Configuration> Figure 17 shows an example configuration of the storage device 200. The storage device 200 includes, as an example, a memory cell array MCA, a circuit WDD, a circuit RDD, a circuit WRWD, and a circuit FECD.

[0351] The memory cell array (MCA) shown in Figure 17 has multiple memory cells (MCs). Specifically, the memory cell array (MCA) has multiple memory cells (MCs) arranged in a matrix. As an example, the memory cell array (MCA) shown in Figure 17 has m rows of memory cells (MCs). Furthermore, Figure 17 illustrates only one of the multiple columns of the memory cell array (MCA).

[0352] Therefore, the symbols for circuit elements, wiring, etc., included in the memory cell array MCA in Figure 17 are enclosed in square brackets [ ] to indicate their addresses. For example, in Figure 17, the memory cell MC located in the first row is written as memory cell MC[1], and the memory cell MC located in the mth row is written as memory cell MC[m].

[0353] Each of the multiple memory cells MC includes, for example, a transistor M1d and an FTJ element FJC.

[0354] For example, the transistor M1d can be the same transistor that can be applied to the transistor M1 described in Embodiment 1.

[0355] As the FTJ element FJC, for example, an FTJ element applicable to the FTJ elements FJA and FJAb described in Embodiment 1 can be used.

[0356] In the memory cell MC[1] shown in Figure 17, the first terminal of transistor M1d is electrically connected to wiring WRDL, the second terminal of transistor M1d is electrically connected to the input terminal of FTJ element FJC, and the gate of transistor M1d is electrically connected to wiring WRWL[1]. The output terminal of FTJ element FJC is electrically connected to wiring FCL[1].

[0357] In the memory cell MC[m] shown in Figure 17, the first terminal of transistor M1d is electrically connected to wiring WRDL, the second terminal of transistor M1d is electrically connected to the input terminal of FTJ element FJC, and the gate of transistor M1d is electrically connected to wiring WRWL[m]. In addition, the output terminal of FTJ element FJC is electrically connected to wiring FCL[m].

[0358] The circuit WDD is electrically connected to the wiring WRDL. For example, the circuit WDD has the function of supplying a potential corresponding to the data to be written to one of the memory cells MC[1] to MC[m] via the wiring WRDL. The circuit WDD also has the function of supplying a potential corresponding to the data read from one of the memory cells MC[1] to MC[m] to the read circuit, etc.

[0359] Circuit WRWD is electrically connected to each of the wirings WRWL[1] to WRWL[m]. For example, when performing a write operation or a read operation, circuit WRWD has the function of sending a selection signal to one of the wirings WRWL[1] to WRWL[m] and a deselection signal to the remaining wirings in order to select the target memory cell MC[1] to MC[m].

[0360] Circuit FECD is electrically connected to each of the wirings FCL[1] to FCL[m]. For example, when writing data to a memory cell MC selected by circuit WRWD, or when reading data from a memory cell MC, circuit FECD has the function of applying a predetermined potential to the wiring FCL on the same row as the selected memory cell and MC.

[0361] The RDD circuit shown in Figure 17 includes a switch SW, a transistor M10, and a buffer circuit BUF.

[0362] A circuit RDD, for example, has the function of reading data held in one of the multiple memory cells MC included in a memory cell array MCA by acquiring the current flowing from that memory cell MC and converting that current into a voltage.

[0363] In the RDD circuit shown in Figure 17, the wiring WRDL is electrically connected to the first terminal of switch SW, and the second terminal of switch SW is electrically connected to the first terminal of transistor M10 and the input terminal of buffer circuit BUF. The second terminal of transistor M10 is electrically connected to wiring VDL, and the gate of transistor M10 is electrically connected to wiring BSL. The output terminal of buffer circuit BUF is electrically connected to wiring OL.

[0364] As an example, the switch SW functions to be in the OFF state when a write operation is being performed on any one of the memory cells MC[1] to MC[m] electrically connected to the wiring WRDL. It also functions to be in the ON state when a write operation is being performed on any one of the memory cells MC[1] to MC[m] electrically connected to the wiring WRDL.

[0365] Furthermore, as the switch SW, for example, an analog switch or an electrical switch such as a transistor can be used. If a transistor is used as the switch SW, it can be a transistor with the same structure as transistor M1. In addition to electrical switches, mechanical switches may also be used.

[0366] Transistor M10 functions, for example, as a load to convert the current flowing through wiring WRDL into a voltage. For instance, by applying a bias voltage from wiring BSL to the gate of transistor M10 and a high-level potential from wiring VDL to the second terminal of transistor M10, the potential of the first terminal of transistor M10 is determined according to the current flowing from wiring WRDL to the first terminal of transistor M10 via switch SW.

[0367] The buffer circuit BUF included in the RDD circuit functions as a circuit to stably output a potential equal to the potential of the first terminal of transistor M10 to the wiring OL.

[0368] In other words, the RDD circuit uses transistor M10 to convert the current flowing through the WRDL wiring, corresponding to the data read from the memory cell MC, into a voltage, and outputs that voltage to the OL wiring. By obtaining the voltage of the OL wiring, the data read from the memory cell MC can be retrieved.

[0369] <Example of operation> First, we will explain the data writing operation to the memory cell MC shown in Figure 17. Here, we will explain the data writing operation to memory cell MC[1] as an example.

[0370] When data is written to memory cell MC[1], the circuit WRWD selects the memory cell MC[1] to which the data will be written. Specifically, the circuit WRWD applies a high-level potential to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through wiring WRWL[m]. At this time, a high-level potential is input to the gate of transistor M1d of memory cell MC[1], so transistor M1d of memory cell MC[1] is turned ON. On the other hand, a low-level potential is input to the gates of each transistor M1d of memory cell MC[2] through memory cell MC[m], so each transistor M1d of memory cell MC[2] through memory cell MC[m] is turned OFF.

[0371] Furthermore, when a write operation is performed on the storage device 200, the switch SW on the circuit RDD is in the OFF state to prevent the transmission of data for writing from the wiring WRDL to the circuit RDD.

[0372] Furthermore, a reference potential is supplied to the wiring FCL[1] from the circuit FECD, for example. The reference potential may be, for example, the ground potential or the low-level potential.

[0373] Furthermore, a potential V0 or V1 is provided to the wiring WRDL from the circuit WDD as data for writing. Note that V0 is a potential lower than the reference potential provided to the wiring FCL[1]. Also, the V0 provided to the input terminal of the FTJ element FJC is a potential that will cause polarization (change the direction of polarization) in the ferroelectric material contained in the FTJ element FJC when a reference potential is provided to the output terminal of the FTJ element FJC. Note that since V0 is a potential lower than the reference potential, the direction of polarization written to the FTJ element FJC will be from the output terminal to the input terminal (negative direction). Also, V1 is a potential higher than the reference potential provided to the wiring FCL[1]. Also, the V1 provided to the input terminal of the FTJ element FJC is a potential that will cause polarization (change the direction of polarization) in the ferroelectric material contained in the FTJ element FJC when a reference potential is provided to the output terminal of the FTJ element FJC. Since V1 is at a higher potential than the reference potential, the direction of polarization written to the FTJ element FJC will be from the input terminal to the output terminal (positive direction).

[0374] After the data for writing is provided from circuit WDD to wiring WRDL, a low-level potential is applied to wiring WRWL[1] by circuit WRWD. At this time, a low-level potential is input to the gate of transistor M1d of memory cell MC[1], so transistor M1d of memory cell MC[1] is turned off.

[0375] The above operation allows data to be written to the memory cell MC[1] of the storage device 200.

[0376] Next, we will explain the data reading operation from the memory cell MC shown in Figure 17. Here, we will describe the operation of reading data from the memory cell MC[1] as an example.

[0377] When reading data from memory cell MC[1], the circuit WRWD selects the memory cell MC[1] from which the data will be read. Specifically, the circuit WRWD applies a high-level potential to wiring WRWL[1] and a low-level potential to wiring WRWL[2] through WRWL[m]. At this time, a high-level potential is input to the gate of transistor M1d of memory cell MC[1], so transistor M1d of memory cell MC[1] is turned ON. On the other hand, a low-level potential is input to the gates of each transistor M1d of memory cell MC[2] through MC[m], so each transistor M1d of memory cell MC[2] through MC[m] is turned OFF.

[0378] Furthermore, when a read operation is performed on the storage device 200, the switch SW of the RDD circuit is in the ON state.

[0379] Additionally, a reference potential is supplied to the wiring FCL[1] from the circuit FECD, for example.

[0380] Furthermore, the wiring VDL is given a potential higher than the reference potential, as an example.

[0381] At this time, there is conduction between the input terminal of the FTJ element FJC of the memory cell MC[1] and the first terminal of the transistor M10 of the circuit RDD. Also, a tunnel current flows between the input and output terminals of the FTJ element FJC of the memory cell MC[1]. The magnitude of the tunnel current is determined by the polarization direction (positive or negative direction) of the ferroelectric material of the FTJ element FJC.

[0382] In the RDD circuit, the potential of the first terminal of transistor M10 is determined by the amount of current flowing from the wiring WRDL to the input terminal of the FTJ element FJC of the memory cell MC[1]. As a result, a potential approximately equal to that of the first terminal of transistor M10 is output to the output terminal of the buffer circuit BUF. By obtaining this potential from the wiring OL, the data held in the memory cell MC[1] can be read.

[0383] Incidentally, during the read operation of the memory device 200, as described above, a tunnel current flows between the input and output terminals of the FTJ element FJC contained in each of the memory cells MC[1] to MC[m]. The amount of this tunnel current is determined by the polarization direction of the ferroelectric material contained in the FTJ element FJC, the material itself, the voltage between the input and output terminals, etc., but is approximately 1 × 10⁻⁶. -8 A / cm 2 The above is 1 x 10 -7 A / cm 2 The following may occur:

[0384] Here, assuming that the transistor M1d contained in each of the memory cells MC[1] to MC[m] is a Si transistor, even if transistor M1d is in the off state, for example, approximately 1 × 10 -10 Currents below A may flow as off-current (leakage current). This is also true when transistor M10 in the RDD circuit is a Si transistor.

[0385] In particular, if the tunnel current flowing between the input and output terminals of the FTJ element FJC is the amount of current flowing in the operating region where the off-current flows in transistor M10, then the potential of the first terminal of transistor M10 will be approximately the same as the potential of the second terminal of transistor M10, i.e., the potential supplied by the wiring VDL. In other words, even if the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC changes, the potential of the first terminal of transistor M10 will hardly change. Therefore, it is difficult to read the data held in the memory cell MC from the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC of the memory cell MC.

[0386] When transistors M1d, M10, etc., are Si transistors, it is preferable to increase the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC in order to read the data held in the memory cell MC. Specifically, for example, the amount of said tunnel current should be the amount of current flowing in the subthreshold region, saturation region, etc., of transistors M1d, M10, etc. To increase the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC, for example, the area of ​​the pair of electrodes of the FTJ element FJC should be increased.

[0387] Furthermore, when each of the memory cells MC[1] to MC[m] contains an OS transistor, transistor M1d has a voltage of 1 × 10⁻¹⁶ in the region where the gate-source voltage is lower than the threshold voltage. -20 Less than A, 1 x 10 -22 Less than A, or 1 × 10 -24 In some cases, it is possible to pass a drain current per 1 μm of channel width, such as less than A. Also, in the region where the gate-source voltage of transistor M1d is near the threshold voltage of transistor M1d, it is 1.0 × 10 -8 A or less, 1.0×10 -12 A or less, or 1.0 × 10 -15 In some cases, a drain current of less than A per 1 μm of channel width can be passed.

[0388] Figure 18 shows an overview of the source-drain current (Ids) and gate-source voltage (Vgs) characteristics of Si transistors (Si FETs) and OS transistors (OS FETs), respectively. Note that in the characteristics of Figure 18, the threshold voltage (Vgs) of Si FETs and OS FETs are shown. th ) are assumed to be equal. Also, for example, each transistor has Vgs and source-drain voltage Vds and V th If it is greater than the sum of Vgs, it behaves as a linear region, and Vgs is V th Larger than source-drain voltage Vds and V thIf the sum is less than or equal to V, it operates as a saturation region, and Vgs is V th It operates as a subthreshold area if the following conditions are met:

[0389] As shown in Figure 18, OS transistors can operate in a wider gate voltage range in the subthreshold region compared to Si transistors. Specifically, the threshold voltage of the OS transistor can be set to V th In that case, in the subthreshold region, V th -1.0V or more V th The following, or V th -0.5V or more V th The circuit can be operated using gate voltages within the following voltage range.

[0390] Therefore, if transistors M1d and M10 are OS transistors, and the tunnel current flowing between the input and output terminals of the FTJ element FJC is the amount of current flowing in the subthreshold region of transistor M10, the potential of the first terminal of transistor M10 is determined according to the amount of this tunnel current. Therefore, the data held in the memory cell MC can be read from the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC of the memory cell MC.

[0391] Furthermore, by using an OS transistor for transistor M10, the amount of current flowing in the subthreshold region of transistor M10 can be read out as a potential. Therefore, as long as transistor M10 operates within the subthreshold region, the tunnel current flowing between the input and output terminals of the FTJ element FJC can be reduced. To reduce the amount of tunnel current flowing between the input and output terminals of the FTJ element FJC, for example, the area of ​​the pair of electrodes of the FTJ element FJC can be reduced.

[0392] In other words, by applying OS transistors to transistors M1d, M10, etc., in the memory device 200, the circuit area required for the FTJ element FJC can be reduced, and the memory cell MC of the memory device 200 can be miniaturized. In addition, by reducing the amount of tunnel current flowing through the FTJ element FJC, the power consumption required for the read operation of the memory device 200 can be reduced.

[0393] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0394] (Embodiment 5) This embodiment describes an example of the configuration of a semiconductor device as described in the above embodiment, and an example of the configuration of a transistor that can be applied to the semiconductor device as described in the above embodiment.

[0395] <Example 1 of semiconductor device configuration> Figure 19 shows a semiconductor device having a memory cell including a capacitive element, the semiconductor device comprising a transistor 300, a transistor 500, and a capacitive element 600. Figure 20A shows a cross-sectional view of transistor 500 in the channel length direction, Figure 20B shows a cross-sectional view of transistor 500 in the channel width direction, and Figure 20C shows a cross-sectional view of transistor 300 in the channel width direction.

[0396] Transistor 500 is an OS transistor (OS transistor) having a metal oxide in its channel formation region. Transistor 500 has a low off-current and its field-effect mobility does not change easily even at high temperatures. By applying transistor 500 to a semiconductor device, such as transistors M1 and M1b included in the memory cell MC described in the above embodiment, a semiconductor device can be realized that does not experience a decrease in operating capability even at high temperatures. In particular, by utilizing the low off-current characteristic and applying transistor 500 to, for example, transistors M1 and M1b, the potential written to the capacity of the memory cell MC can be maintained for a long time.

[0397] Transistor 500 is provided, for example, above transistor 300, and capacitive element 600 is provided, for example, above transistors 300 and 500. Capacitive element 600 can be, for example, a capacitive element that holds a potential corresponding to the data written to the memory cell. Depending on the circuit configuration, the capacitive element 600 shown in Figure 19 does not necessarily have to be provided.

[0398] The transistor 300 is provided on a substrate 310 and has an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 310, a low-resistance region 314a that functions as a source region or drain region, and a low-resistance region 314b. The transistor 300 can be applied to, for example, the transistor M6, transistor M6b, etc. described in the above embodiment. In Figure 19, the gate of transistor 300 is shown to be electrically connected to either the source or drain of transistor 500 via a pair of electrodes of the capacitive element 600. However, in one embodiment of the present invention, the semiconductor device can be configured such that either the source or drain of transistor 300 is electrically connected to either the source or drain of transistor 500 via one of the pair of electrodes of the capacitive element 600, or either the source or drain of transistor 300 is electrically connected to the gate of transistor 500 via one of the pair of electrodes of the capacitive element 600, or each terminal of transistor 300 is not electrically connected to each terminal of transistor 500 or each terminal of the capacitive element 600.

[0399] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 310.

[0400] As shown in Figure 20C, the transistor 300 has its semiconductor region 313's upper surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0401] Note that transistor 300 can be either a p-channel or n-channel type.

[0402] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0403] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0404] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0405] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metal materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0406] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer can be formed using methods such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0407] Note that the transistor 300 shown in Figure 19 is just one example, and its structure is not limited to this example. Any appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of the FIN type shown in Figure 20C. Also, for example, if the semiconductor device is a unipolar circuit consisting only of OS transistors, the configuration of transistor 300 may be the same as that of transistor 500, which uses an oxide semiconductor, as shown in Figure 21. Details of transistor 500 will be described later. In this specification, a unipolar circuit refers to a circuit that includes a transistor with only one polarity, such as an n-channel transistor or a p-channel transistor.

[0408] In Figure 21, the transistor 300 is mounted on a substrate 310A. In this case, the substrate 310A may be a semiconductor substrate, similar to the substrate 310 of the semiconductor device in Figure 19. The substrate 310A can be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic may be used. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper.

[0409] In the transistor 300 shown in Figure 19, insulators 320, 322, 324, and 326 are stacked in order from the substrate 310 side.

[0410] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0411] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0412] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using a chemical mechanical polishing (CMP) method or the like to improve its flatness.

[0413] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen, impurities, etc. from diffusing from the substrate 310 or the transistor 300 to the region where the transistor 500 is provided.

[0414] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0415] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm2 The following is acceptable.

[0416] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0417] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors 328 and 330, which connect to the capacitive element 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. In this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0418] The plugs and wiring (conductor 328, conductor 330, etc.) can be made of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, which can be used in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce the wiring resistance.

[0419] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 19, insulators 350, 352, and 354 are sequentially stacked on top of insulators 326 and conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring for connecting to transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0420] For example, it is preferable that the insulator 350, like the insulator 324, is an insulator that has barrier properties against impurities such as hydrogen and water. Also, as insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants, like the insulator 326, in order to reduce parasitic capacitance that occurs between the wiring. Furthermore, it is preferable that the conductor 356 contains a conductor that has barrier properties against impurities such as hydrogen and water. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistors 300 and 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0421] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0422] Furthermore, insulator 360, insulator 362, and insulator 364 are stacked in order on insulator 354 and conductor 356.

[0423] It is preferable that the insulator 360, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 360, for example, a material that can be used for the insulator 324 can be used.

[0424] Insulators 362 and 364 function as interlayer insulating films and planarizing films, respectively. Furthermore, it is preferable that insulators 362 and 364, like insulator 324, be insulators that have barrier properties against impurities such as water and hydrogen. Therefore, materials applicable to insulator 324 can be used for insulators 362 and / or insulator 364.

[0425] Furthermore, openings are formed in the regions of insulators 360, 362, and 364 that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill these openings. The conductor 366 is also formed on insulator 362. The conductor 366 functions, for example, as a plug or wiring for connecting to transistor 300. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0426] Insulators 510, 512, 514, and 516 are sequentially layered on the insulator 364 and the conductor 366. Preferably, one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0427] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, the same material as for insulator 324 can be used.

[0428] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0429] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulators 510 and 514.

[0430] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0431] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films, silicon oxynitride films, etc., can be used as insulators 512 and insulator 516.

[0432] Furthermore, the insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503 shown in Figures 20A and 20B) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0433] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0434] A transistor 500 is provided above the insulator 516.

[0435] As shown in Figures 20A and 20B, the transistor 500 comprises an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) arranged to be embedded in the insulator 514 or insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide The structure includes a conductor 542b on 530b, an insulator 571b on the conductor 542b, an insulator 552 on the oxide 530b, an insulator 550 on the insulator 552, an insulator 554 on the insulator 550, a conductor 560 (conductor 560a and conductor 560b) located on the insulator 554 and overlapping with a portion of the oxide 530b, and an insulator 544 arranged on the insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 544 on the insulator 571b. Here, as shown in Figures 20A and 20B, insulator 552 is in contact with the top surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and top surface of oxide 530b, the side surface of conductor 542 (conductor 542a and conductor 542b), the side surface of insulator 571 (insulator 571a and insulator 571b), the side surface of insulator 544, the side surface of insulator 580, and the bottom surface of insulator 550. The top surface of conductor 560 is positioned so as to be roughly the same height as the top of insulator 554, the top of insulator 550, the top of insulator 552, and the top surface of insulator 580. Insulator 574 is in contact with at least a portion of the top surface of conductor 560, the top of insulator 552, the top of insulator 550, the top of insulator 554, and the top surface of insulator 580.

[0436] Insulators 580 and 544 are provided with openings that reach oxide 530b. Insulators 552, 550, 554, and 560 are arranged within these openings. In addition, in the channel length direction of transistor 500, conductors 560, 552, 550, and 554 are provided between insulators 571a and conductor 542a, and between insulators 571b and conductor 542b. Insulator 554 has a region in contact with the side surface of conductor 560 and a region in contact with the bottom surface of conductor 560.

[0437] Preferably, the oxide 530 has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on top of the oxide 530a. By having the oxide 530a below the oxide 530b, the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed.

[0438] Although the transistor 500 is shown as having a configuration in which oxide 530 consists of two layers, oxide 530a and oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of oxide 530b or a stacked structure of three or more layers. Alternatively, the oxide 530a and oxide 530b can each have a stacked structure.

[0439] Conductor 560 functions as the first gate (also called the top gate) electrode, and conductor 503 functions as the second gate (also called the back gate) electrode. Insulators 552, 550, and 554 function as the first gate insulators, and insulators 522 and 524 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 542a functions as either the source or the drain, and conductor 542b functions as either the source or the drain. At least a portion of the region of oxide 530 that overlaps with conductor 560 functions as a channel-forming region.

[0440] Here, an enlarged view of the vicinity of the channel formation region in Figure 20A is shown in Figure 22A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in Figure 22A, the oxide 530b has a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich region 530bc and function as the source region or drain region. At least a portion of region 530bc is superimposed on the conductor 560. In other words, region 530bc is provided in the region between the conductor 542a and the conductor 542b. Region 530ba is provided superimposed on the conductor 542a, and region 530bb is provided superimposed on the conductor 542b.

[0441] Region 530bc, which functions as a channel-forming region, has more oxygen vacancies than regions 530ba and 530bb (in this specification, oxygen vacancies in metal oxides are defined as V O This region is sometimes referred to as (oxygen vacancy). Because the amount of (oxygen) is small or the impurity concentration is low, it is a high-resistance region with a low carrier concentration. Therefore, region 530bc can be said to be type i (intrinsic) or substantially type i.

[0442] In transistors using metal oxides, impurities or oxygen vacancies (V) can be found in the region where the channel is formed within the metal oxide. O The presence of oxygen deficiency (V) can cause fluctuations in electrical properties and reduce reliability. O ) Nearby hydrogen, oxygen vacancy (V O A defect in which hydrogen has entered (hereinafter referred to as V O Sometimes referred to as H, it can form a channel and generate electrons that become carriers. For this reason, if the region in the oxide semiconductor where the channel is formed contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region in the oxide semiconductor where the channel is formed, impurities, oxygen vacancies, and V OIt is preferable that H be reduced as much as possible.

[0443] Furthermore, regions 530ba and 530bb, which function as source or drain regions, are oxygen-deficient (V O This region has a high concentration of ) or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, which increases the carrier concentration and lowers the resistance. In other words, regions 530ba and 530bb are n-type regions with higher carrier concentrations and lower resistance compared to region 530bc.

[0444] Here, the carrier concentration in region 530bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 530bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0445] Furthermore, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. In other words, this region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in this junction region may be equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 530ba and region 530bb, and equal to or greater than that of region 530bc.

[0446] Although Figure 22A shows an example in which regions 530ba, 530bb, and 530bc are formed in oxide 530b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0447] Furthermore, in oxide 530, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0448] In transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 530 (oxide 530a and oxide 530b) which includes the channel formation region.

[0449] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0450] As oxide 530, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0451] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0452] In this way, by placing oxide 530a below oxide 530b, the diffusion of impurities and oxygen from structures formed below oxide 530a to oxide 530b can be suppressed.

[0453] Furthermore, because oxides 530a and 530b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 530a and oxide 530b can be reduced. Because the defect level density at the interface between oxide 530a and oxide 530b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0454] The oxide 530b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0455] CAAC-OS has a highly crystalline, dense structure and is free from impurities and defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (such as). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0456] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat resistant and reliable.

[0457] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0458] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 500 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0459] Therefore, in an oxide semiconductor, the region 530bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 530ba and 530bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 530bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 530ba and 530bb.

[0460] Therefore, in this embodiment, with the conductor 542a and conductor 542b placed on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 530bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0461] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 530bc. Due to the action of plasma, microwaves, etc., the V of region 530bc O By cleaving H, hydrogen H is removed from region 530bc, and oxygen is lost V. OIt can be supplemented with oxygen. In other words, in region 530bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 530bc. Therefore, the oxygen deficiency in region 530bc, and V O This can reduce H and lower the carrier concentration.

[0462] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 542a and 542b and do not reach regions 530ba and 530bb. In addition, the effects of oxygen plasma can be reduced by insulators 571 and 580, which are provided covering oxide 530b and conductor 542. As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0463] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 552, or after the deposition of the insulating film that will become the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 552 or insulator 550 in this way, oxygen can be efficiently injected into region 530bc. In addition, by arranging the insulator 552 in contact with the side surface of the conductor 542 and the surface of region 530bc, the injection of more oxygen than necessary into region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed when the insulating film that will become the insulator 550 is deposited.

[0464] Furthermore, the oxygen injected into region 530bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). It is preferable that the oxygen injected into region 530bc be one or more of the above forms, and particularly preferable that it be oxygen radicals. Additionally, the film quality of insulators 552 and 550 can be improved, thereby increasing the reliability of transistor 500.

[0465] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 530bc, and V O By removing H, region 530bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 530ba and 530bb, which function as source or drain regions, while maintaining conductivity. This suppresses variations in the electrical characteristics of transistor 500 and reduces variations in the electrical characteristics of transistor 500 within the substrate plane.

[0466] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0467] Furthermore, as shown in Figure 20B, in a cross-sectional view of the transistor 500 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 530b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0468] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 530b by the insulator 552, insulator 550, insulator 554, and conductor 560 can be improved.

[0469] The oxide 530 preferably has a laminated structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0470] Furthermore, it is preferable that the oxide 530b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, and the transistor 500 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0471] Here, at the junction of oxide 530a and oxide 530b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 530a and oxide 530b can be said to change continuously or to be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0472] Specifically, by having oxides 530a and 530b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 530b is In-M-Zn oxide, oxide 530a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0473] Specifically, for oxide 530a, a metal oxide with an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, may be used. Similarly, for oxide 530b, a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, may be used. Note that "similar composition" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0474] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0475] Furthermore, as shown in Figure 20A and other figures, by providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530, the indium contained in the oxide 530 may be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. As a result, the atomic ratio near the surface of the oxide 530 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 530, particularly oxide 530b, the field-effect mobility of the transistor 500 can be improved.

[0476] By configuring oxides 530a and 530b as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a large on-current and high frequency characteristics.

[0477] It is preferable that at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 function as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable that at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 be an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate through it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen does not easily permeate through it).

[0478] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0479] For insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 512, 544, and 576, it is preferable to use silicon nitride or the like, which has higher hydrogen barrier properties. Also, for example, for insulators 514, 571, 574, and 581, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side via insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 581 towards the transistor 500. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 524, etc., towards the substrate side via the insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 580, etc., upward from the transistor 500 via the insulator 574, etc. Thus, it is preferable to have a structure in which the transistor 500 is surrounded by insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0480] Here, it is preferable to use oxides having an amorphous structure as insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, hydrogen contained in the transistor 500, or hydrogen present around the transistor 500, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, it is possible to manufacture a transistor 500 and a semiconductor device that have good characteristics and are highly reliable.

[0481] Furthermore, while insulators 512, 514, 544, 571, 574, 576, and 581 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer may also be possible.

[0482] The insulators 512, 514, 544, 571, 574, 576, and 581 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 512, 514, 544, 571, 574, 576, and 581 can be reduced. Note that the deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0483] Furthermore, it may be preferable to lower the resistivity of insulators 512, 544, and 576. For example, the resistivity of insulators 512, 544, and 576 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 512, 544, and 576 can mitigate charge-up of conductors 503, 542, and 560 in processes using plasma in semiconductor device manufacturing. The resistivity of insulators 512, 544, and 576 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0484] Furthermore, it is preferable that insulators 516, 574, 580, and 581 have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 516, 580, and 581 as appropriate.

[0485] Furthermore, it is preferable that the insulator 581 functions as an insulator, for example, an interlayer film, a planarization film, or the like.

[0486] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Here, it is preferable that the conductor 503 is embedded in an opening formed in the insulator 516. In some cases, a portion of the conductor 503 may be embedded in the insulator 514.

[0487] The conductor 503 comprises a conductor 503a and a conductor 503b. Conductor 503a is provided in contact with the bottom surface and side wall of the opening. Conductor 503b is provided so as to be embedded in a recess formed in conductor 503a. Here, the upper height of conductor 503b is approximately equal to the upper height of conductor 503a and the upper height of insulator 516.

[0488] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0489] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the resulting decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 503a. For example, titanium nitride can be used for the conductor 503a.

[0490] Furthermore, it is preferable that the conductor 503b be a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 503b.

[0491] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, rather than in conjunction with it. In particular, by applying a negative potential to conductor 503, it is possible to increase the Vth of transistor 500 and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0492] Furthermore, if the oxide 530 is made of high-purity intrinsic material and impurities are removed from the oxide 530 as much as possible, it may be possible to normally turn off the transistor 500 (set the threshold voltage of the transistor 500 to greater than 0V) without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that they are given the same potential.

[0493] Furthermore, the electrical resistivity of the conductor 503 is designed considering the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the limits permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of these impurities into the oxide 530.

[0494] Furthermore, the conductor 503 should be provided in a size larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in Figure 20B, it is preferable that the conductor 503 extends to the area outside the edges of the oxide 530a and oxide 530b in the channel width direction. That is, it is preferable that the conductor 503 and the conductor 560 are superimposed on the outside of the side surface of the oxide 530 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 which functions as the first gate electrode and the electric field of the conductor 503 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0495] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0496] By setting transistor 500 to normally off and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, transistor 500 can also be considered as a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making transistor 500 an S-Channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between oxide 530 and the gate insulating film can be the entire bulk of oxide 530. In other words, by making transistor 500 an S-Channel, GAA, or LGAA structure, it can be made into a so-called bulk-flow type, where the carrier path is used as the entire bulk. By adopting a bulk-flow type transistor structure, it is possible to improve the current density flowing through the transistor, and thus an improvement in the transistor's on-current or an increase in the transistor's field-effect mobility can be expected.

[0497] Furthermore, as shown in Figure 20B, the conductor 503 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 503. Also, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0498] In the transistor 500, the conductor 503 is shown as a stacked structure of conductor 503a and conductor 503b, but the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked structure of three or more layers.

[0499] Insulators 522 and 524 function as gate insulators.

[0500] Preferably, the insulator 522 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 522 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 522 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 524.

[0501] The insulator 522 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and suppress the generation of oxygen vacancies in the oxide 530. In addition, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 or the oxide 530.

[0502] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 522 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0503] Furthermore, the insulator 522 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 522.

[0504] The insulator 524 in contact with the oxide 530 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0505] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0506] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen deficiencies in oxide 530 are repaired by the supplied oxygen, or in other words, "V OThis can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0507] Furthermore, the insulators 522 and 524 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 524 may be superimposed with the oxide 530a to form an island-like structure. In this case, the insulator 544 will be in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.

[0508] Conductors 542a and 542b are provided in contact with the upper surface of oxide 530b. Conductors 542a and 542b function as the source electrode or drain electrode of transistor 500, respectively.

[0509] As the conductor 542 (conductor 542a and conductor 542b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0510] Furthermore, hydrogen contained in oxide 530b, etc., may diffuse into conductor 542a or conductor 542b. In particular, by using tantalum-containing nitrides for conductor 542a and conductor 542b, hydrogen contained in oxide 530b, etc., is more likely to diffuse into conductor 542a or conductor 542b, and the diffused hydrogen may combine with nitrogen present in conductor 542a or conductor 542b. In other words, hydrogen contained in oxide 530b, etc., may be absorbed by conductor 542a or conductor 542b.

[0511] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 542 and the top surface of the conductor 542. By using a conductor 542 without such a curved surface, the cross-sectional area of ​​the conductor 542 in the channel width direction can be increased. This increases the conductivity of the conductor 542 and increases the on-current of the transistor 500.

[0512] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. Preferably, the insulator 571 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen more effectively than the insulator 580. As the insulator 571, for example, a silicon-containing nitride such as silicon nitride may be used. Furthermore, it is preferable that the insulator 571 has a function to capture impurities such as hydrogen. In that case, as the insulator 571, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, it is preferable to use amorphous aluminum oxide or amorphous aluminum oxide as the insulator 571 because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and semiconductor device with good characteristics and high reliability.

[0513] The insulator 544 is provided so as to cover the insulator 524, oxide 530a, oxide 530b, conductor 542, and insulator 571. Preferably, the insulator 544 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 544 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 544.

[0514] By providing the insulators 571 and 544 as described above, the conductor 542 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in insulators 524 and 580 can be prevented from diffusing into the conductor 542. This prevents the conductor 542 from being directly oxidized by the oxygen contained in insulators 524 and 580, which would increase its resistivity and reduce the on-current.

[0515] The insulator 552 functions as part of the gate insulator. Preferably, the insulator 552 is a barrier insulating film against oxygen. The insulator 552 can be any insulator that can be used for the insulator 574 described above. The insulator 552 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 is an insulator containing at least oxygen and aluminum.

[0516] As shown in Figure 20B, the insulator 552 is provided in contact with the top and side surfaces of oxide 530b, the side surface of oxide 530a, the side surface of insulator 524, and the top surface of insulator 522. In other words, the regions of oxide 530a, oxide 530b, and insulator 524 that overlap with the conductor 560 are covered by the insulator 552 in the cross-section in the channel width direction. This allows the insulator 552, which has an oxygen barrier property, to block the desorption of oxygen from oxide 530a and oxide 530b during heat treatment, etc. Thus, the formation of oxygen vacancies (Vo) in oxide 530a and oxide 530b can be reduced. O This allows for a reduction in H. Therefore, the electrical characteristics of transistor 500 can be improved, and its reliability can be enhanced.

[0517] Conversely, even if an excess amount of oxygen is present in the insulator 580 and insulator 550, it is possible to suppress the excessive supply of such oxygen to oxides 530a and 530b. Therefore, it is possible to suppress the excessive oxidation of regions 530ba and 530bb via region 530bc, which would otherwise cause a decrease in the on-current of transistor 500 or a decrease in field-effect mobility.

[0518] Furthermore, as shown in Figure 20A, the insulator 552 is provided in contact with the sides of the conductor 542, insulator 544, insulator 571, and insulator 580. Therefore, oxidation of the side surface of the conductor 542 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0519] Furthermore, the insulator 552, along with the insulator 554, the insulator 550, and the conductor 560, must be provided in the opening formed in the insulator 580 or the like. When miniaturizing the transistor 500, it is preferable that the film thickness of the insulator 552 be thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 552 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 552 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 552 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0520] To deposit the insulator 552 with a thin film thickness as described above, it is preferable to use the ALD method. The ALD method is a method of film deposition in which a first raw material gas (also called a precursor, metal precursor, or metal precursor) and a second raw material gas (also called a reactant, reactant, oxidizing agent, or nonmetal precursor) are alternately introduced into a chamber, and the introduction of these raw material gases is repeated to deposit the film. There are various types of ALD methods, including the thermal ALD method, in which the reaction of the precursor and reactant is carried out using only thermal energy, and the PEALD (Plasma Enhanced ALD) method, which uses a plasma-excited reactant. In the PEALD method, the use of plasma allows for film deposition at lower temperatures, which is sometimes preferable.

[0521] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 552 can be deposited with good coverage on the sides of openings formed in the insulator 580, etc., with the thin film thickness described above.

[0522] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0523] The insulator 550 functions as part of the gate insulator. It is preferable that the insulator 550 is placed in contact with the upper surface of the insulator 552. The insulator 550 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat. In this case, the insulator 550 will be an insulator having at least oxygen and silicon.

[0524] Similar to the insulator 524, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. The lower and upper limits mentioned above can be combined. In this case, it is sufficient that the insulator 550 has a region with the above-mentioned film thickness in at least a part of it.

[0525] Figures 20A and 20B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 22B, the insulator 550 may be a laminated structure of two layers: an insulator 550a and an insulator 550b on top of the insulator 550a.

[0526] As shown in Figure 22B, when the insulator 550 has a two-layer laminated structure, it is preferable that the lower insulator 550a is formed using an insulator that is permeable to oxygen, and the upper insulator 550b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 550a to the conductor 560. In other words, it is possible to suppress the reduction in the amount of oxygen supplied to the oxide 530. Furthermore, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be made using a material that can be used for the insulator 550 as described above, and the insulator 550b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b is an insulator having at least oxygen and hafnium. Furthermore, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0527] Furthermore, when silicon oxide, silicon oxynitride, or the like is used for insulator 550a, insulator 550b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 550a and insulator 550b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 550 can be increased.

[0528] The insulator 554 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 554. This prevents impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and oxide 530b. The insulator 554 can be any insulator that can be used for the insulator 576 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 554. In this case, the insulator 554 will be an insulator containing at least nitrogen and silicon.

[0529] Furthermore, the insulator 554 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 550 into the conductor 560.

[0530] Furthermore, the insulator 554, along with the insulator 552, the insulator 550, and the conductor 560, must be provided in an opening formed in the insulator 580 or the like. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 554 be thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 554 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 554 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 554 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0531] The conductor 560 functions as the first gate electrode of the transistor 500. Preferably, the conductor 560 has a conductor 560a and a conductor 560b disposed on top of the conductor 560a. For example, it is preferable that the conductor 560a is arranged to enclose the bottom and sides of the conductor 560b. Also, as shown in Figures 20A and 20B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. In Figures 20A and 20B, the conductor 560 is shown as a two-layer structure of conductor 560a and conductor 560b, but the conductor 560 can also be a single-layer structure or a stacked structure of three or more layers.

[0532] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0533] Furthermore, because the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0534] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 560b can also be in a laminated structure. Specifically, for example, the conductor 560b can be a laminated structure of titanium, or titanium nitride, and the above conductive material.

[0535] Furthermore, in transistor 500, the conductor 560 is formed self-aligningly to fill the openings formed in the insulator 580 and the like. By forming the conductor 560 in this way, the conductor 560 can be reliably positioned in the region between the conductors 542a and 542b without the need for alignment.

[0536] Furthermore, as shown in Figure 20B, in the channel width direction of transistor 500, it is preferable that the height of the bottom surface of the region of conductor 560 where conductor 560 and oxide 530b do not overlap, with reference to the bottom surface of insulator 522, is lower than the height of the bottom surface of oxide 530b. By configuring conductor 560, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 530b via insulator 550 or the like, it becomes easier to apply the electric field of conductor 560 to the entire channel formation region of oxide 530b. Therefore, the on-current of transistor 500 can be increased and the frequency characteristics can be improved. With respect to the bottom surface of the insulator 522, the difference between the height of the bottom surface of the conductor 560 and the height of the bottom surface of oxide 530b in the region where the oxides 530a and 530b and the conductor 560 do not overlap is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less. The above-mentioned lower and upper limits can be combined.

[0537] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are provided. The upper surface of the insulator 580 may also be flattened.

[0538] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced. The insulator 580 is preferably made of the same material as the insulator 516, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0539] Preferably, the insulator 580 has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 580 may be made of silicon oxide such as silicon oxide or silicon oxynitride.

[0540] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 580 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 574 will be an insulator having at least oxygen and aluminum. By providing an insulator 574 in the region sandwiched between the insulator 512 and the insulator 580, in contact with the insulator 580, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 580 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 574 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and a semiconductor device with good characteristics and high reliability.

[0541] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is placed on top of the insulator 574. Preferably, the insulator 576 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 576. By depositing the insulator 576 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 576, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0542] Furthermore, one of the first or second terminals of transistor 500 is electrically connected to conductor 540a, which functions as a plug, and the other of the first or second terminal of transistor 500 is electrically connected to conductor 540b. In this specification, conductors 540a and conductor 540b are collectively referred to as conductor 540.

[0543] As an example, the conductor 540a is provided in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 20A, as well as insulators 582 and 586 shown in Figure 19, and the conductor 540a is provided inside these openings. Furthermore, as an example, the conductor 540b is provided in a region that overlaps with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 20A, as well as insulators 582 and 586 shown in Figure 19, and the conductor 540b is provided inside these openings. Insulators 582 and 586 will be described later.

[0544] Furthermore, as shown in Figure 20A, an insulator 541a may be provided between the side surface of the opening in the region overlapping with the conductor 542a and the conductor 540a, as an insulator that provides a barrier against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening in the region overlapping with the conductor 542b and the conductor 540b, as an insulator that provides a barrier against impurities. In this specification, insulators 541a and 541b will be collectively referred to as insulator 541.

[0545] It is preferable that the conductors 540a and 540b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 540a and 540b may be arranged in a laminated structure.

[0546] Furthermore, when the conductor 540 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 574, 576, 581, 580, 544, and 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above insulator 576 into the oxide 530 through conductors 540a and 540b.

[0547] As insulators 541a and 541b, any barrier insulating film that can be used for insulator 544 and the like may be used. For example, as insulators 541a and 541b, insulators such as silicon nitride, aluminum oxide, and silicon oxide nitride may be used. S...

Claims

[Claim 1] It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first FTJ element, and a second FTJ element. Each of the first FTJ element and the second FTJ element has an input terminal, a tunnel insulating film, a dielectric, and an output terminal. Either the source or drain of the first transistor is electrically connected to either the source or drain of the third transistor, the gate of the fourth transistor, and the output terminal of the first FTJ element. Either the source or drain of the second transistor is electrically connected to either the source or drain of the fourth transistor, the gate of the third transistor, and the output terminal of the second FTJ element. Semiconductor equipment.

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