Semiconductor packages

Abstract

To improve the signal quality of semiconductor packages. [Solution] The semiconductor package according to the present invention includes a wiring substrate including a plurality of wiring layers, the wiring layers including a first wiring layer and a second wiring layer on the first wiring layer, the first wiring layer including a first conductive line including two first ground wires spaced apart along a first direction and two first signal wires interposed between them, the first conductive line extending along a second direction perpendicular to the first direction, the second wiring layer including a second conductive line including a second signal wire adjacent to any one of the first signal wires in the first signal wires in a third direction perpendicular to the first and second directions, and a second ground wire adjacent to another first signal wire in the first signal wires in the third direction, the second conductive line extending along the second direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] In response to the rapid development of the electronics industry and user requirements, electronic devices have become smaller, more multifunctional, and have larger capacities. Accordingly, semiconductor packages containing multiple semiconductor chips are required. As the multiple semiconductor chips included in the semiconductor package become more highly integrated, it frequently occurs that a printed circuit board cannot accept such a high degree of integration. To solve this problem, semiconductor packages that connect between multiple semiconductor chips using an interposer have been developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to improve the signal quality of a semiconductor package. Another object of the present invention is to embody a semiconductor package in which the density of signal wiring is increased in the same area.

Means for Solving the Problems

[0005] To achieve the above objective, a semiconductor package according to one aspect of the present invention includes a wiring substrate comprising a plurality of wiring layers, the wiring layers comprising a first wiring layer and a second wiring layer on the first wiring layer, the first wiring layer comprising a first conductive line comprising two first ground wires spaced apart along a first direction and two first signal wires interposed between them, the first conductive line extending along a second direction perpendicular to the first direction, the second wiring layer comprising a second conductive line comprising a second signal wire adjacent to any one of the first signal wires in the first signal wires in a third direction perpendicular to the first and second directions, and a second ground wire adjacent to another first signal wire in the first signal wires in the third direction, the second conductive line may extend along the second direction.

[0006] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising a wiring substrate including a plurality of wiring layers, wherein the wiring layers include a first wiring layer and a second wiring layer on the first wiring layer, the first wiring layer comprising a first pad spaced apart in a first direction and a first conductive line arranged between the first pads, the second wiring layer comprising a second pad spaced apart in a first direction and a second conductive line arranged between the second pads, the first conductive line and the second conductive line each extending along a second direction perpendicular to the first direction, the first conductive line comprising a first ground wire and a first signal wire arranged along a first arrangement pattern, the second conductive line comprising a second ground wire and a second signal wire arranged along a second arrangement pattern, the first arrangement pattern comprising a pattern in which a first ground wire, a first signal wire, a first signal wire, and a first ground wire are repeatedly arranged in the first direction, and preferably the number of second signal wires in the second wiring layer is different from the number of first signal wires in the first wiring layer.

[0007] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes a package substrate, an interposer on the package substrate, and a first semiconductor chip and a second semiconductor chip on the interposer, wherein the interposer includes a wiring substrate including a plurality of wiring layers, the wiring layers including a first wiring layer and a second wiring layer on the first wiring layer, the first wiring layer including a first conductive line including two first ground wires spaced apart in a first direction and two first signal wires interposed between them, the first conductive line extending in a second direction perpendicular to the first direction, the second wiring layer including a second conductive line including a second signal wire adjacent to any one of the first signal wires in the first signal wires in a third direction perpendicular to the first and second directions, and a second ground wire adjacent in the third direction to another first signal wire in the first signal wires, the second conductive line extending in a second direction, and the first semiconductor chip and the second semiconductor chip may be spaced apart from each other in the second direction. [Effects of the Invention]

[0008] According to the present invention, in a first wiring layer and a second wiring layer that are alternately stacked and adjacent to each other, the first wiring layer includes a first grounding wire, a first signal wire, a first signal wire, and a first grounding wire arranged in a repeating pattern, and by adjusting the arrangement of the signal wires in the second wiring layer, signal interference between the first and second wiring layers can be reduced and signal quality can be improved. Furthermore, by including multiple signal wires arranged within the grounding wire in the first wiring layer, the density of signal wires within the same area can be increased. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. [Figure 2] This is an enlarged view of the EG1 portion in Figure 1. [Figure 3] This is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. [Figure 4]It is an enlarged view of the EG2 part in FIG. 3. [Figure 5] It is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. [Figure 6] It is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. [Figure 7] It is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. [Figure 8] It is an enlarged view corresponding to the EG1 part in FIG. 1. [Figure 9] It is an enlarged view corresponding to the EG1 part in FIG. 1. [Figure 10] It is an enlarged view corresponding to the EG2 part in FIG. 3. [Figure 11] It is an enlarged view corresponding to the EG2 part in FIG. 3. [Figure 12] It is an enlarged view corresponding to the EG1 part in FIG. 1. [Figure 13] It is an enlarged view corresponding to the EG2 part in FIG. 3. [Figure 14] It is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. [Figure 15] It is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. [Figure 16] It is a cross-sectional view of a semiconductor package according to some embodiments of the present invention.

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the drawings.

[0011] [[ID=四十八]]In this specification, the term "on" indicates a relative position and is defined to include all cases where the described structure is located above or below the reference structure. That is, "on" includes not only the ordinary meaning of "on" but also the case of being located "below".

[0012] In this specification, the meaning that the first wiring and the second wiring are "adjacent" means that no other wiring intervenes between them, and it means that the first wiring and the second wiring are directly adjacent or in a proximate state.

[0013] In this specification, "arrangement" and "array" are used with similar meanings. However, "arrangement" is used to place emphasis on the specific position of the configuration rather than "array", and "array" is used separately to place emphasis on the order in which a plurality of configurations are arranged rather than "arrangement".

[0014] FIG. 1 is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. FIG. 2 is an enlarged view of the EG1 portion of FIG. 1.

[0015] Referring to FIG. 1, a semiconductor package according to some embodiments of the present invention includes a wiring substrate 100. The wiring substrate 100 is a substrate on which a semiconductor chip is mounted. In this specification, the first direction D1, the second direction D2, and the third direction D3 are directions perpendicular to each other. The first direction D1 and the second direction D2 are directions parallel to the upper surface of the wiring substrate 100. The third direction D3 is a direction perpendicular to the upper surface of the wiring substrate 100. In this specification, the horizontal direction means the first direction D1 and / or the second direction D2. The vertical direction means the third direction D3.

[0016] The wiring substrate 100 includes a plurality of wiring layers 100M, 110M. The plurality of wiring layers 100M, 110M includes a first wiring layer 100M and a second wiring layer 110M on the first wiring layer 100M. The first wiring layer 100M and the second wiring layer 110M are layers arranged at different positions from each other in the third direction D3 and are layers adjacent to each other in the third direction D3.

[0017] Referring to Figure 1, the first wiring layer 100M includes a plurality of first conductive lines CL1. The first conductive line CL1 includes a plurality of first ground lines 102 and first signal lines 104 arranged in the first wiring layer 100M. The first conductive line CL1 includes two first ground lines 102 spaced apart in a first direction D1, and two first signal lines 104 interposed between them. The first conductive line CL1 is arranged along a first array pattern GR1. The first array pattern GR1 is a pattern in which the first ground lines 102, first signal lines 104, first signal lines 104, and first ground lines 102 are repeatedly arranged along the first direction D1. The first conductive line CL1 extends in a second direction D2. The first wiring layer 100M further includes first pads 101 spaced apart from each other in the first direction D1 with the first conductive line CL1 in between. The first conductive line CL1 closest to each of the first pads 101 is, for example, the first ground wire 102.

[0018] The second wiring layer 110M includes a plurality of second conductive lines CL2. The second conductive lines CL2 include a plurality of second ground lines 112 and second signal lines 114 arranged in the second wiring layer 110M. The second conductive lines CL2 include two second ground lines 112 spaced apart in a first direction D1 and a second signal line 114 interposed between them. The second conductive lines CL2 are arranged along a second array pattern GR2. The second array pattern GR2 is different from the first array pattern GR1. The second array pattern GR2 is a pattern in which the second ground lines 112, the second signal lines 114, and the second ground lines 112 are repeatedly arranged along the first direction D1. The second conductive lines CL2 extend in a second direction D2. The second wiring layer 110M further includes second pads 111 spaced apart from each other in the first direction D1 via the second conductive lines CL2. The second conductive line CL2 closest to each of the second pads 111 is, for example, the second ground wire 112. The distance between any one of the second pads 111 and the adjacent second ground wire 112 is smaller than the distance between any other second pad 111 and the second ground wire 112.

[0019] A via 108 is interposed between the first pad 101 and the second pad 111. The first pad 101 and the second pad 111 are electrically connected through the via 108.

[0020] The number of second signal lines 114 interposed between second pads 111 arranged adjacent to the first direction D1 is less than the number of first signal lines 104 interposed between first pads 101 arranged adjacent to the first direction D1. In other words, within the same area, the number of second signal lines 114 is less than the number of first signal lines 104.

[0021] The first wiring layer 100M and the second wiring layer 110M contain metals. The first wiring layer 100M and the second wiring layer 110M contain metals such as copper, aluminum, and gold.

[0022] The first wiring layer 100M and the second wiring layer 110M are arranged on the insulating layer 109. Although the insulating layer 109 is shown as a single layer, it can actually consist of multiple insulating layers. Depending on the type of wiring substrate 100, the insulating layer 109 may contain an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN), or a polymer insulating material such as polyimide.

[0023] Referring to Figures 1 and 2, the first grounding wire 102a has a first width 102W along the first direction D1, and the first signal wire 104a has a second width 104W along the first direction D1. The first width 102W and the second width 104W are substantially identical. The thickness of the first width 102W and the second width 104W is, for example, 0.5 μm to 5 μm. The thickness of each of the first signal wires 104a, 104b and the first grounding wires 102a, 102b along the third direction D3 is substantially identical, for example, 1 μm to 5 μm. The distance L1 along the third direction D3 between the first wiring layer 100M and the second wiring layer 110M is greater than the first width 102W and the second width 104W. The first separation distance X1 along the first direction D1 between the first grounding wire 102 and the first signal wire 104 adjacent to the first direction D1 is substantially the same as the second separation distance X2 along the first direction D1 between two adjacent first signal wires 104. The first separation distance X1 and the second separation distance X2 are, for example, 0.5 μm to 5 μm.

[0024] One of the first signal wires 104a, 104b, is adjacent to the second signal wire 114 in the third direction D3. The other first signal wire 104b, 104b, is adjacent to the second ground wire 112b, 112a, 112b, in the third direction D3.

[0025] Figure 3 is a cross-sectional view showing a portion of a semiconductor package according to some embodiments of the present invention. Figure 4 is an enlarged view of the EG2 portion of Figure 3. Details that overlap with those described in Figures 1 and 2 are omitted.

[0026] Referring to Figures 3 and 4, the first wiring layer 100M includes a first conductive line CL1 arranged along the first array pattern GR1 and a second conductive line CL2 arranged along the third array pattern GR3. The third array pattern GR3 is identical to the first array pattern GR1 and has an offset shape from the first array pattern GR1. The first array pattern GR1 is a pattern in which the first ground wire 102, the first signal wire 104, the first signal wire 104, and the first ground wire 102 are repeatedly arranged along the first direction D1. The second conductive line CL2 includes two second ground wires 112 and two second signal wires 114 interposed between them. The third array pattern GR3 is a configuration in which the second ground wire 112, the second signal wire 114, the second signal wire 114, and the second ground wire 112 are repeatedly arranged along the first direction D1. The second conductive line CL2 closest to each of the second pads 111 is the second ground wire 112.

[0027] Specifically, two second signal lines 114a and 114b adjacent to the first direction D1 have an arrangement that is offset in the first direction D1 with respect to the first signal lines 104a and 104b adjacent to the first direction D1. Specifically, the second signal lines 114a and 114b have an arrangement that is offset from the first signal lines 104a and 104b by an offset distance O1 equal to the sum of the second separation distance X2 between the first signal lines 104a and 104b and the second width 104W of the first signal line 104a.

[0028] One of the first signal wires 104a and 104b is adjacent to one of the second signal wires 114a and 114b in the third direction D3. The other first signal wire 104a is adjacent to one of the second ground wires 112a and 112b in the third direction D3.

[0029] According to the concept of the present invention, the first wiring layer 100M includes a first conductive line CL1 which is arranged along a first array pattern GR1, with two first signal lines 104 placed between first ground lines 102, and these are repeated along a first direction D1. When the first conductive line CL1 is arranged along the first array pattern GR1, the number of signal lines per unit area is greater than when one first signal line 104 is placed between first ground lines 102 and these are arranged along the first direction D1, thereby increasing the number of signals that can be routed. The second wiring layer 110M adjacent to the first wiring layer 100M is identical to the second array pattern GR2 which is different from the first array pattern GR1, and includes a second conductive line CL2 which is repeatedly arranged along a third array pattern GR3 which is offset from the first array pattern GR1 in the first direction D1. The second and third array patterns GR2 and GR3 are arranged such that they do not have two first signal lines 104 adjacent to the first direction D1 and two second signal lines 114 adjacent to the third direction D3. The second array pattern GR2 is arranged to include one of the two first signal lines 104 and a second ground line 112 adjacent to the third direction D3. As a result, signal interference (crosstalk) between the first wiring layer 100M and the second wiring layer 110M can be prevented.

[0030] Figure 5 is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. Some aspects that overlap with those described in Figure 1 will be omitted.

[0031] Referring to Figures 1 and 5, the wiring board 100 further includes a third wiring layer 120M and a fourth wiring layer 130M. The third wiring layer 120M and the fourth wiring layer 130M are arranged sequentially on the second wiring layer 110M. The third wiring layer 120M includes a third pad 121 spaced apart in a first direction D1 and a third conductive line CL3 interposed between them. The fourth wiring layer 130M includes a fourth pad 131 spaced apart in a first direction D1 and a fourth conductive line CL4 interposed between them.

[0032] The third conductive line CL3 includes a third ground wire 122 and a third signal wire 124 having the same arrangement as the first ground wire 102 and the first signal wire 104. The third conductive line CL3 includes a third signal wire 124 interposed between the third ground wires 122 that are spaced apart in the first direction D1. The third conductive line CL3 includes a third ground wire 122, a third signal wire 124, a third signal wire 124, and a third ground wire 122, arranged along the first arrangement pattern GR1. The fourth conductive line CL4 includes a fourth ground wire 132 and a fourth signal wire 134 having the same arrangement as the second ground wire 112 and the second signal wire 114. The fourth conductive line CL4 includes a fourth ground wire 132 that are spaced apart along the first direction D1 and a fourth signal wire 134 interposed between them. The fourth conductive line CL4 includes a fourth ground wire 132, a fourth signal wire 134, and a fourth ground wire 132, which are arranged along the second array pattern GR2.

[0033] The relationship between the second conductive line CL2, the first conductive line CL1, and the third conductive line CL3 is the same as that previously described in Figures 1 and 2. The relationship between the fourth conductive line CL4 and the third conductive line CL3 is the same as that previously described in Figures 1 and 2. The third wiring layer 120M corresponds to the first wiring layer 100M, and the fourth wiring layer 130M corresponds to the second wiring layer 110M. That is, the wiring substrate 100 includes a plurality of wiring layers in which the first wiring layer 100M and the second wiring layer 110M are repeatedly stacked along the third direction D3.

[0034] According to some embodiments, the wiring board 100 further includes a fifth wiring layer and a sixth wiring layer arranged sequentially on the fourth wiring layer 130M. The fifth wiring layer corresponds to the first wiring layer 100M, and the sixth wiring layer corresponds to the second wiring layer 110M. That is, the wiring board 100 includes a plurality of wiring layers in which the first wiring layer 100M and the second wiring layer 110M are repeatedly stacked along the third direction D3, and the number of times the layers are repeatedly stacked is also adjustable.

[0035] Figure 6 is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. Some aspects that overlap with those described in Figure 3 will be omitted.

[0036] Referring to Figures 3 and 6, the wiring board 100 further includes a third wiring layer 120M and a fourth wiring layer 130M. The third wiring layer 120M and the fourth wiring layer 130M are arranged sequentially on the second wiring layer 110M. The first conductive line CL1 is arranged along the first array pattern GR1, and the second conductive line CL2 is arranged along the third array pattern GR3.

[0037] The third conductive line CL3 includes a third ground wire 122, a third signal wire 124, a third signal wire 124, and a third ground wire 122, all arranged along the first array pattern GR1. The fourth conductive line CL4 includes a fourth ground wire 132, a fourth signal wire 134, a fourth signal wire 134, and a fourth ground wire 132, all arranged along the third array pattern GR3.

[0038] The relationship between the second conductive line CL2, the first conductive line CL1, and the third conductive line CL3 is the same as that previously described in Figures 3 and 4. The relationship between the fourth conductive line CL4 and the third conductive line CL3 is the same as that previously described in Figures 3 and 4. The third wiring layer 120M corresponds to the first wiring layer 100M, and the fourth wiring layer 130M corresponds to the second wiring layer 110M. According to some embodiments, the wiring board 100 may further include a fifth wiring layer and a sixth wiring layer arranged sequentially on the fourth wiring layer 130M. The fifth wiring layer corresponds to the first wiring layer 100M, and the sixth wiring layer corresponds to the second wiring layer 110M. That is, the wiring board 100 includes a plurality of wiring layers in which the first wiring layer 100M and the second wiring layer 110M are repeatedly stacked along the third direction D3.

[0039] Figure 7 is a cross-sectional view showing a part of a semiconductor package according to some embodiments of the present invention. Some aspects that overlap with those described in Figures 1 and 2 will be omitted from this explanation.

[0040] Referring to Figure 7, the wiring board 100 includes a first wiring layer 100M, a second wiring layer 110M, a third wiring layer 120M, and a fourth wiring layer 130M, which are arranged in order in the third direction D3. The first wiring layer 100M includes a first conductive line CL1, the second wiring layer 110M includes a second conductive line CL2, the third wiring layer 120M includes a third conductive line CL3, and the fourth wiring layer 130M includes a fourth conductive line CL4. The first conductive line CL1 and the third conductive line CL3 are arranged along the first arrangement pattern GR1. The arrangement of the first conductive line CL1 and the arrangement of the third conductive line CL3 are substantially the same. The second conductive line CL2 is arranged along the second arrangement pattern GR2, and the fourth conductive line CL4 is arranged along the third arrangement pattern GR3. The relationship between the second conductive line CL2 and the first conductive line CL1 and the third conductive line CL3 is the same as that previously described in Figures 1 and 2. The relationship between the fourth conductive line CL4 and the third conductive line CL3 is the same as that previously explained in Figures 3 and 4.

[0041] Figure 8 is an enlarged view corresponding to the EG1 portion of Figure 1. Explanations that overlap with those explained in Figure 2 are omitted.

[0042] Referring to Figures 1 and 8, the first ground wire 102 has a first width 102W along the first direction D1, the first signal wire 104 has a second width 104W along the first direction D1, the second ground wire 112 has a third width 112W along the first direction D1, and the second signal wire 114 has a fourth width 114W along the first direction D1. The first width 102W is smaller than the second width 104W. The first separation distance X1 along the first direction D1 between the first ground wire 102 and the first signal wire 104 adjacent to the first direction D1 is smaller than the second separation distance X2 along the first direction D1 between two adjacent first signal wires 104.

[0043] According to some embodiments, the first width 102W is smaller than the third width 112W and the fourth width 114W. According to some embodiments, the third separation distance Y1 along the first direction D1 between the second ground wire 112 and the adjacent second signal wire 114 is substantially the same as the first separation distance X1 and smaller than the second separation distance X2.

[0044] According to the concept of the present invention, the inter-signal interference effect can be reduced by increasing the separation distance X2 between first signal wires 104 in the first wiring layer 100M, which contains relatively more signal wires than the second wiring layer 110M. Instead of increasing the separation distance X2 between first signal wires 104, the inter-signal interference effect can be reduced by decreasing the width 102W of each first ground wire 102, without reducing the number of first signal wires 104 within the same area.

[0045] Figure 9 is an enlarged view corresponding to the EG1 portion of Figure 1.

[0046] Explanations that overlap with those described in Figure 2 will be omitted. Referring to Figures 1 and 9, the first separation distance X1 along the first direction D1 between the first ground wire 102 and the adjacent first signal wire 104 is substantially the same as the second separation distance X2 along the first direction D1 between two adjacent first signal wires 104. The first width 102W is smaller than the second width 104W.

[0047] According to some embodiments, the third separation distance Y1 along the first direction D1 between the second grounding wire 112 and the adjacent second signal wire 114 is substantially the same as the first separation distance X1 and the second separation distance X2. According to some embodiments, the first width 102W is smaller than the third width 112W and the fourth width 114W. According to some embodiments, the second width 104W is larger than the third width 112W and the fourth width 114W.

[0048] According to the concept of the present invention, signal quality can be improved by increasing the width 104W of each first signal wire 104 in the first wiring layer 100M, which contains relatively more signal wires than the second wiring layer 110M, and reducing the inductance. Instead of increasing the width 104W of each first signal wire 104, the width 102W of each first ground wire 102 can be decreased, thereby improving signal quality without reducing the number of first signal wires 104 within the same area.

[0049] Figure 10 is an enlarged view corresponding to the EG2 portion of Figure 3. Explanations that overlap with those explained in Figure 4 are omitted.

[0050] Referring to Figures 3 and 10, the first width 102W is smaller than the second width 104W. The third width 112W is smaller than the fourth width 114W. The first separation distance X1 is smaller than the second separation distance X2. The third separation distance Y1 is smaller than the fourth separation distance Y2 along the first direction D1 between adjacent second signal wires 114.

[0051] According to some embodiments, the first separation distance X1 is smaller than the fourth separation distance Y2. According to some embodiments, the third separation distance Y1 is smaller than the second separation distance X2.

[0052] Figure 11 is an enlarged view corresponding to the EG2 portion of Figure 3. Explanations that overlap with those explained in Figure 4 are omitted.

[0053] Referring to Figures 3 and 11, the first width 102W is smaller than the second width 104W.

[0054] The third width 112W is smaller than the fourth width 114W. The first separation distance X1 is substantially the same as the second separation distance X2. The third separation distance Y1 is substantially the same as the fourth separation distance Y2. According to some embodiments, the first to fourth separation distances X1, X2, X3, and X4 are substantially the same. According to some embodiments, the first width 102W is smaller than the fourth width 114W. According to some embodiments, the third width 112W is smaller than the second width 104W.

[0055] Figure 12 is an enlarged view corresponding to the EG1 portion of Figure 1. Explanations that overlap with those described in Figure 2 are omitted. Referring to Figures 1 and 12, the second width 104W of the first signal wiring 104 is smaller than the first width 102W of the first ground wiring 102. The first separation distance X1 along the first direction D1 between the first ground wiring 102 and the first signal wiring 104 adjacent to the first direction D1 is smaller than the second separation distance X2 along the first direction D1 between two adjacent first signal wirings 104. According to some embodiments, the fourth width 114W of the second signal wiring is larger than or substantially the same as the second width 104W. According to some embodiments, the third separation distance Y1 along the first direction D1 between the second ground wiring 112 and the adjacent second signal wiring 114 is substantially the same as or smaller than the first separation distance X1. According to some embodiments, the third separation distance Y1 is smaller than the second separation distance X2.

[0056] Figure 13 is an enlarged view corresponding to the EG2 portion of Figure 3. Explanations that overlap with those explained in Figure 4 are omitted. Referring to Figures 3 and 13, the second width 104W is smaller than the first width 102W. The first separation distance X1 is smaller than the second separation distance X2. The fourth width 114W is smaller than the third width 112W. The fourth separation distance Y2 is smaller than the third separation distance Y1. According to some embodiments, the first separation distance X1 is substantially the same as the third separation distance Y1, and the second separation distance X2 is substantially the same as the fourth separation distance Y2.

[0057] According to the concept of the present invention, the width of the first signal wiring is reduced compared to the width of the first ground wiring, and the spacing between the first signal wirings is greater than the distance between one first signal wiring and an adjacent first ground wiring. By using wider ground wiring to reduce resistance and power consumption, and by arranging the first signal wirings with wider spacing, signal interference can be reduced. Furthermore, by reducing the width of the first signal wiring, the number of first signal wirings within the same area can be maintained even if the spacing between the first signal wirings is increased.

[0058] Figure 14 shows a semiconductor package according to some embodiments.

[0059] Referring to Figure 14, the semiconductor package 1000 includes a package substrate 500, an interposer IP, a first semiconductor chip 600, and a second semiconductor chip 700.

[0060] The package substrate 500 is, for example, a printed circuit board (PCB). The package substrate 500 includes an upper substrate pad 510 and a lower substrate pad 520. The upper substrate pad 510 is located on the upper surface of the package substrate 500, and the lower substrate pad 520 is located on the lower surface of the package substrate 500. An external connection terminal 580 is located on the lower substrate pad 520. The external connection terminal 580 includes, for example, solder.

[0061] An interposer IP is placed on the package substrate 500. The interposer IP is, for example, a redistribution interposer. The redistribution interposer is a substrate that includes a photosensitive insulating material (e.g., polyimide) and metal wiring. The metal wiring includes seed patterns and conductive patterns on the seed patterns. The metal wiring includes vias and lines. The interposer IP corresponds to the wiring board 100 described in Figures 1 to 13. The interposer IP includes an insulating layer 190 and a wiring layer 170 on the insulating layer. Internal connecting terminals 180 are interposed between the interposer IP and the package substrate 500. The internal connecting terminals 180 include, for example, solder.

[0062] A first semiconductor chip 600 and a second semiconductor chip 700 are arranged on an interposer IP. The first semiconductor chip 600 and the second semiconductor chip 700 are spaced apart from each other along a second direction D2. The first semiconductor chip 600 and the second semiconductor chip 700 are either the same type of semiconductor chip or different types of semiconductor chips. For example, the first semiconductor chip 600 is a memory chip (e.g., DRAM), and the second semiconductor chip 700 is a logic chip (e.g., ASIC). The first semiconductor chip 600 includes a first chip pad 610, and a first connection terminal 680 is interposed between the first semiconductor chip 600 and the interposer IP. The second semiconductor chip 700 includes a second chip pad 710, and a second connection terminal 780 is interposed between the second semiconductor chip 700 and the interposer IP. The first semiconductor chip 600 is electrically connected to the interposer IP through the first connection terminal 680, and the second semiconductor chip 700 is electrically connected to the interposer IP through the second connection terminal 780. As previously described, the interposer IP includes multiple wiring layers 170. The wiring layers 170 include first wiring layers 100M and second wiring layers 110M that are alternately stacked in a third direction D3. The first semiconductor chip 600 and the second semiconductor chip 700 are electrically connected through first conductive lines CL1 of the first wiring layer 100M and second conductive lines CL2 of the second wiring layer 110M, which extend in a second direction D2.

[0063] According to the concept of the present invention, the interposer IP includes the wiring board 100 described earlier in Figures 1 to 13, thereby improving the quality of the signals transmitted during the signal transmission process between the first semiconductor chip 600 and the second semiconductor chip 700. Furthermore, the wiring board 100 allows for increased signal wiring density within the same area, enabling the transmission of more signals without increasing the thickness of the wiring board 100.

[0064] Figure 15 shows a semiconductor package according to some embodiments. Except for what is explained below, it overlaps with what was explained in Figure 14, so the redundant explanations will be omitted.

[0065] Referring to Figure 15, the semiconductor package 1100 includes a chip stacking structure ST and a second semiconductor chip 700. The chip stacking structure ST and the second semiconductor chip 700 are separated from each other in the second direction D2. The chip stacking structure ST and the second semiconductor chip 700 are placed on an interposer IP.

[0066] The chip stack structure ST includes a third semiconductor chip 800 and a plurality of fourth semiconductor chips 900. The third semiconductor chip 800 is, for example, a buffer chip. The fourth semiconductor chip 900 is, for example, a memory chip (e.g., DRAM). The second semiconductor chip 700 is, for example, a logic chip (e.g., an ASIC). The third semiconductor chip 800 and the fourth semiconductor chip 900 each include a semiconductor substrate and through-vias penetrating it. The chip stack structure ST is, for example, a high-bandwidth memory (HBM). Microbumps are placed between the third semiconductor chip 800 and the fourth semiconductor chip 900, and between the fourth semiconductor chips 900. An adhesive layer is interposed between the third semiconductor chip 800 and the fourth semiconductor chip 900, and between the fourth semiconductor chips 900, and the adhesive layer fills the spaces between the microbumps. A molding film 870 covers the top surface of the third semiconductor chip 800, the side surfaces of the fourth semiconductor chip 900, and the side surfaces of the adhesive layer. The molding film 870 includes a polymeric insulating material, such as an epoxy molding compound.

[0067] Figure 16 is a cross-sectional view showing a semiconductor package according to some embodiments. Except for what is described below, it overlaps with what was described in Figure 14, so the redundant explanations are omitted.

[0068] Referring to Figure 16, the semiconductor package 1200 includes an interposer IP comprising a semiconductor substrate 106, through-vias 116 penetrating the semiconductor substrate 106, and a wiring board 100. The interposer IP is, for example, a silicon interposer. The semiconductor substrate 106 is, for example, a silicon substrate, and the through-vias 116 are, for example, through-silicon vias (TSVs). The wiring board 100 is substantially identical to the wiring board 100 described earlier in Figures 1 to 13. The wiring board 100 is electrically connected to the package substrate 500 through the through-vias 116.

[0069] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, and the invention can be used in various different combinations, modifications, and environments without departing from the spirit of the invention. [Explanation of Symbols]

[0070] 100 Wiring boards 100M 1st wiring layer 101 First Pad 102 1st ground wiring 104 First signal wiring 106 Semiconductor substrates 108, 118 Beer 109, 190 Insulating layer 110M 2nd wiring layer 111 Second pad 112 2nd ground wiring 114 Second signal wiring 116 Through vias 122 3rd ground wiring 124 Third signal wiring 121 Third Pad 131 Pad 4 132 4th ground wiring 134 Fourth signal wiring 170 wiring layer CL1 First conductive line CL2 Second conductive line GR1 First Sequence Pattern GR2 Second Array Pattern IP(100) Interposer 500 Package Substrates 510 Upper circuit board pad 520 Lower circuit board pad 580 External connection terminal 600 First Semiconductor Chip 610 First tip pad 680 1st connection terminal 700 Second Semiconductor Chip 710 Second chip pad 780 Second connecting terminal 800 Third Semiconductor Chips 870 Molding film 900 Fourth Semiconductor Chip 1000, 1100, 1200 semiconductor packages

Claims

1. Includes a wiring board containing multiple wiring layers, The aforementioned wiring layer comprises a first wiring layer and The first wiring layer includes a second wiring layer on the first wiring layer, The first wiring layer includes a first conductive line comprising two first ground wires spaced apart along a first direction and two first signal wires interposed between them, the first conductive line extending along a second direction perpendicular to the first direction, The second wiring layer includes a second conductive line which includes a second signal line adjacent to any one of the first signal lines in the first signal line in a third direction perpendicular to the first and second directions, and a second ground line which is adjacent to another of the first signal lines in the first signal line in the third direction. A semiconductor package characterized in that the second conductive line extends along the second direction.

2. The semiconductor package according to claim 1, characterized in that the two first grounding wires and the two first signaling wires are arranged adjacent to each other along the first direction in the order of first grounding wire, first signaling wire, first signaling wire, and first grounding wire.

3. The second conductive line includes two second grounding wires spaced apart along the first direction and one second signal wire interposed between them. The semiconductor package according to claim 1, characterized in that the one second signal line and the two second ground lines are adjacent to each other.

4. The second conductive line includes two second ground wires and two second signal wires interposed between them, along the first direction. The semiconductor package according to claim 1, characterized in that the two second signal lines are adjacent to each other.

5. The first conductive line is arranged along the first arrangement pattern, The second conductive line is arranged along the second arrangement pattern, The semiconductor package according to claim 1, characterized in that the first array pattern and the second array pattern are different from each other.

6. The first conductive line is arranged along the first arrangement pattern, The second conductive line is arranged along the second arrangement pattern, The first sequence pattern and the second sequence pattern are identical to each other. The semiconductor package according to claim 1, characterized in that the second conductive line has an array pattern offset in a first direction with respect to the first conductive line.

7. The semiconductor package according to claim 6, characterized in that the second conductive line is offset with respect to the first conductive line by a distance equal to the sum of the width of the first signal wiring along the first direction and the separation distance between the two first signal wirings along the first direction.

8. The semiconductor package according to claim 1, characterized in that the distance between the first wiring layer and the second wiring layer along the third direction is greater than the separation distance between the first signal wirings along the first direction.

9. The semiconductor package according to claim 1, characterized in that the separation distance between adjacent first grounding wires and first signal wires is the same as the separation distance between adjacent first signal wires.

10. The semiconductor package according to claim 1, characterized in that the separation distance between adjacent first grounding wires and first signal wires is smaller than the separation distance between adjacent first signal wires.

11. The semiconductor package according to claim 10, characterized in that the width of the first grounding wire along the first direction is smaller than the width of the first signal wire along the first direction.

12. The semiconductor package according to claim 10, characterized in that the width of the first grounding wire along the first direction is greater than the width of the first signal wire along the first direction.

13. The first wiring layer further includes first pads spaced apart from each other along the first direction via the first conductive line, The second wiring layer further includes second pads spaced apart from each other along the first direction via the second conductive line, The semiconductor package according to claim 1, further comprising vias that directly connect the first pad and the second pad.

14. Includes a wiring board containing multiple wiring layers, The aforementioned wiring layer comprises a first wiring layer and The first wiring layer includes a second wiring layer on the first wiring layer, The first wiring layer includes first pads spaced apart in a first direction and first conductive lines arranged between the first pads in the first direction. The second wiring layer includes a second conductive line arranged in the first direction, which is positioned between the second pads and separated in the first direction. The first conductive line and the second conductive line each extend along a second direction perpendicular to the first direction, The first conductive line includes a first ground wire and a first signal wire arranged along a first array pattern, The second conductive line includes a second ground wire and a second signal wire arranged along a second array pattern, The first array pattern is a pattern in which a first ground wire, a first signal wire, a first signal wire, and a first ground wire are repeatedly arranged in the first direction. A semiconductor package characterized in that the number of second signal lines in the second wiring layer is different from the number of first signal lines in the first wiring layer.

15. The second sequence pattern differs from the first sequence pattern, The semiconductor package according to claim 14, characterized in that the second array pattern is a pattern in which the second ground wire, the second signal wire, and the second ground wire are repeatedly arranged in the first direction.

16. The second sequence pattern is identical to the first sequence pattern. The semiconductor package according to claim 14, characterized in that the second array pattern is a pattern in which a second ground wire, a second signal wire, a second signal wire, and a second ground wire are repeatedly arranged in the first direction.

17. The aforementioned wiring board further includes a third wiring layer and a fourth wiring layer on the second wiring layer, The fourth wiring layer is separated from the second wiring layer via the third wiring layer, The semiconductor package according to claim 14, characterized in that the third wiring layer includes third conductive lines arranged along the first array pattern.

18. The semiconductor package according to claim 17, characterized in that the fourth wiring layer is arranged along the second arrangement pattern.

19. The semiconductor package according to claim 17, characterized in that the fourth wiring layer is arranged along a third array pattern different from the first and second array patterns.

20. Package substrate and The interposer on the aforementioned package substrate, The interposer includes a first semiconductor chip and a second semiconductor chip, The aforementioned interposer is Includes a wiring board containing multiple wiring layers, The aforementioned wiring layer comprises a first wiring layer and The first wiring layer includes a second wiring layer on the first wiring layer, The first wiring layer includes a first conductive line comprising two first ground wires spaced apart along a first direction and two first signal wires interposed between them, the first conductive line extending along a second direction perpendicular to the first direction, The second wiring layer includes a second conductive line which includes a second signal line adjacent to any one of the first signal lines in the first signal line in a third direction perpendicular to the first and second directions, and a second ground line which is adjacent to another of the first signal lines in the first signal line in the third direction. The second conductive line extends along the second direction, A semiconductor package characterized in that the first semiconductor chip and the second semiconductor chip are spaced apart from each other along the second direction.

Images