Processing system

Abstract

The objective is to achieve at least one of the following: higher accuracy or higher speed compared to conventional calculations using the Ising model. [Solution] The processing system comprises a plurality of array modules, each having a spin block that stores a spin value for each spin in a plurality of spins, an interaction block that stores partial interaction values ​​obtained by dividing the interaction value between each spin in the plurality of spins, and a calculation block that outputs a calculation result calculated based on the spin value and the partial interaction value; and a control module that controls the state of the spins in the plurality of spins based on an integrated result obtained by integrating the calculation results output from the plurality of array modules.

Description

[Technical Field]

[0001] This disclosure relates to a processing system. [Background technology]

[0002] Patent Document 1 describes a semiconductor device that constitutes an Ising model for calculating the state of each spin using the interaction between all spins, comprising a plurality of chips and a controller connected to the plurality of chips, each of which has a spin block, an interaction block and an arithmetic block controlled by a control circuit, which outputs a partial calculation result for i on the chip to the controller, and when the controller receives the partial calculation result for i calculated on each of the plurality of chips, it integrates each of the partial calculation results regardless of the adjacency of each of the plurality of chips and performs an integrated calculation, which outputs the integrated result to each of the plurality of chips, and for each chip that receives the integrated result, the arithmetic block makes a decision to update the spin state for i based on the integrated result and updates the spin state. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-139789 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Patent Document 1 describes the integrated result ΔE i When updating the spin state based on this, the controller integrates the calculation results performed by each of the multiple chips to obtain the integrated result ΔE i This technology demonstrates how to achieve higher capacity and lower power consumption. However, the conventional technology shown in Patent Document 1 still had room for improvement in terms of high accuracy and high speed, which are among the basic performance improvements.

[0005] This disclosure is made in view of these circumstances and aims to provide a system that can achieve at least one of the following: higher accuracy or higher speed compared to conventional calculations using the Ising model. [Means for solving the problem]

[0006] A processing system according to a first aspect of this disclosure comprises a plurality of array modules, each having a spin block that stores a spin value indicating the state of a spin for each spin in a plurality of spins, an interaction block that stores partial interaction values ​​obtained by dividing an interaction value indicating the coupling weight between each spin in the plurality of spins, and a calculation block that outputs a calculation result relating to the energy of a model including the plurality of spins, calculated based on the spin value and the partial interaction value; and a control module that controls the state of the spins in the plurality of spins based on an integrated result obtained by integrating the calculation results output from the plurality of array modules, wherein the plurality of array modules each store the partial interaction values, which include different bits in the interaction value, in the interaction block.

[0007] In the processing system according to the second aspect of this disclosure, the control module, in the processing system according to the first aspect, performs a bit shift on the calculation results when adding the calculation results output from the plurality of array modules.

[0008] A processing system according to a third aspect of this disclosure, in a processing system according to a second aspect, the control module stores the number of bits corresponding to each of the plurality of array modules, and the calculation results output from the plurality of array modules are bit-shifted according to the number of bits.

[0009] A processing system according to a fourth aspect of this disclosure includes: a spin block that stores spin values ​​indicating the state of each spin in a plurality of spins with a plurality of bit widths; an interaction block that stores interaction values ​​indicating the coupling weights between each spin in the plurality of spins; an operation block that outputs an operation result relating to the energy of a model including the plurality of spins, calculated based on the spin values ​​and the interaction values; and a control module that simultaneously controls the updating of the spin states in the plurality of spins based on the operation result.

[0010] A processing system according to a fifth aspect of the present disclosure is a processing system according to any one of the first to fourth aspects, wherein the spin block stores the spin values ​​for each spin in matrix form, the interaction block stores the interaction values ​​between each spin in matrix form, and the arithmetic block includes a plurality of multipliers that calculate each component of the product of the matrix of the spin values ​​and the interaction values, and an adder that adds the outputs of the plurality of multipliers.

[0011] A processing system according to a sixth aspect of the present disclosure is a processing system according to any one of the first to fifth aspects, wherein each of the plurality of multipliers includes a bit expander for expanding the number of bits of the interaction value, a bit shifter for right bit-shifting the expanded interaction value based on some bits of the spin value, and a selector for selecting whether to invert the output of the bit shifter based on other bits of the spin value.

[0012] A processing system according to a seventh aspect of this disclosure comprises a plurality of array modules, each having the spin block, the interaction block, and the calculation block, in a processing system according to any one of the first to sixth aspects, wherein the control module controls the updating of the spin state in the plurality of spins based on an integrated result obtained by integrating the calculation results output from each of the plurality of array modules.

[0013] The processing system described herein can achieve at least one of the following: higher accuracy or higher speed compared to conventional calculations using the Ising model. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic diagram illustrating a combinatorial optimization problem. [Figure 2] This diagram schematically illustrates the fully connected Ising model. [Figure 3] This figure shows a schematic configuration of the processing system 10 according to this embodiment. [Figure 4] This figure shows a schematic configuration of the array module 100 according to this embodiment. [Figure 5] This diagram shows the basic structure of an annealing processor. [Figure 6] This figure shows the basic structure of an annealing processor with a higher capacity than that shown in Figure 5. [Figure 7] This is a diagram showing the scalable structure of Figure 6. [Figure 8] This figure shows the high-bit representation of interactions. [Figure 9] This figure shows an example of a block diagram of the ΔE block according to the first embodiment. [Figure 10] This figure shows an example of a block diagram of a control block according to the first embodiment. [Figure 11] This diagram shows the internal structure of the ΔE block, which is a combination of the conventional structure and the structure of the first embodiment. [Figure 12] This figure shows an example of a block diagram of a processing system 10 employing a high-capacity and high-precision structure. [Figure 13] This diagram shows addition in a control block, focusing on the bit levels. [Figure 14] This diagram conceptually illustrates the possible states of spin. [Figure 15] This diagram schematically illustrates the state transitions of spin. [Figure 16]This figure shows an example of a circuit that realizes the storage of multistate spins. [Figure 17] This figure shows an example of a block diagram of the modified multiplier. [Figure 18] This figure shows an example of a block diagram of the array module 100 in the second embodiment. [Modes for carrying out the invention]

[0015] Hereinafter, an example of an embodiment of this disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios.

[0016] Figure 1 schematically illustrates a combinatorial optimization problem. A combinatorial optimization problem is the problem of finding the best combination for a certain value from among many selectable combinations that satisfy given conditions, in the shortest possible time. For example, there are many combinatorial optimization problems in our daily lives, such as route searching for delivery, floor plans, circuit board layout (vertex coverage), optimization of sorting quantities of delivered goods, scheduling of shifts for multiple part-time workers, finding the cheapest and fastest wireless communication channels, or optimizing combinations of financial stocks.

[0017] Solving combinatorial optimization problems requires significant computational resources. However, combinatorial optimization problems can be solved quickly using the fully coupled Ising model, an extended magnetic material model.

[0018] Figure 2 schematically shows a fully connected Ising model. The Ising model is a model in which spins that take two states are arranged at lattice points and the coupling between spins is considered. A method based on the Ising model representing the properties of ferromagnetic materials is expected as a new computational method that can solve the problem of requiring a large amount of computational resources. Such a method is an attempt to apply the property that spins in a disordered orientation of a ferromagnetic material where magnetization is not present at high temperatures align with each other according to their mutual connection and magnetization appears naturally without trying all possibilities (i.e., not by brute force) as the temperature decreases, to the solution of combinatorial optimization problems. Such a method is known as the annealing method.

[0019] Here, the evaluation value f of the optimization problem shown in FIG. 1 is expressed, for example, by the following equation.

Equation

[0020] Further, the energy E of the system of the Ising model shown in FIG. 2 is expressed, for example, by the following equation.

Equation

[0021] As shown in Equation (2), the energy E of the Ising model is represented by the interaction J i between spins σ j , spins σ i , spins σ j and spins σ ij , and the external field h i . Here, updating the spin σ i so that the energy E becomes small is the solution method using the Ising model. The update of σ i is performed by referring to the following equation, which is the local energy focusing on σ i in Equation (2).

Equation

[0022] Figure 3 is a diagram showing the schematic configuration of the processing system 10 according to this embodiment. When there is no need to distinguish between the first and second embodiments described later, they will be collectively referred to as "this embodiment." The processing system 10 according to this embodiment includes a plurality of array modules 100_1 to 100_n (collectively referred to as "array modules 100"), a control module 200, and an interface 300. The array modules 100 are configured, for example, as follows.

[0023] Figure 4 shows a schematic configuration of the array module 100 according to this embodiment. The array module 100 includes a spin block 110, an interaction block 120, and an arithmetic block 130.

[0024] The spin block 110 stores a spin value for each spin in a group of spins, which indicates the state of the spin.

[0025] The interaction block 120 stores interaction values ​​(also called "interaction values") that indicate the coupling weights between each of the multiple spins.

[0026] The calculation block 130 outputs the calculation result regarding the energy of a model containing multiple spins, calculated based on the spin values ​​and interaction values.

[0027] The control module 200 integrates the calculation results output from multiple array modules 100_1 to 100_n to obtain the integrated result E. i Based on this, the spin state of multiple spins is controlled.

[0028] Interface 300 exchanges data necessary for such processing and data obtained from such processing with other devices.

[0029] In processing system 10, E i Based on spin σ iWe will update ΔE here. i Let's assume that we define it as follows:

number

[0030] In this case, σ i is, E i It is always in the negative direction, i.e., ΔE i +h i It can be updated with the same sign. Furthermore, by employing pseudo-annealing to avoid local optima traps and introducing a temperature random value T, the spin update equation can be expressed as follows: ΔE i Based on spin σ i When updating, the processing system 10 is configured, for example, as follows:

number

[0031] Figure 5 shows the basic structure of an annealing processor. In this figure, the case where there are four spins, σ1 to σ4, is shown as an example. As shown in this figure, the annealing processor can be divided into a ΔE block and a control block.

[0032] Figure 6 shows the basic structure of a higher-capacity annealing processor than that shown in Figure 5. In this figure, the case where there are eight spins, σ1 to σ8, is shown as an example.

[0033] Figure 7 shows the scalable structure of Figure 6. Figure 7 shows a high-capacity structure equipped with four ΔE blocks capable of performing calculations similar to those of the basic structure of the annealing processor in Figure 5. The advantage of such a scalable structure is that the number of spins can be expanded simply by adding ΔE blocks, provided that all ΔE blocks are composed of the same module. Such a schematic configuration is described in Patent Document 1. Where necessary, the disclosures of Patent Document 1 may be incorporated herein by reference in their entirety.

[0034] This disclosure relates to techniques for further improving the basic performance of such a processing system 10. In particular, in the first embodiment, high precision is achieved by bit partitioning the interaction. In the second embodiment, high speed is achieved by making the spin multi-valued (three or more values). Hereafter, the first embodiment that achieves high precision and the second embodiment that achieves high speed will be described as separate embodiments. However, the first and second embodiments do not necessarily have to be implemented independently and may be implemented in combination with each other.

[0035] (First Embodiment) In the first embodiment, the bit representation of the interaction is divided into multiple parts such as upper and lower, or upper, middle and lower, and so on, ΔE i This makes it possible to perform calculations with high accuracy. This will be explained in detail.

[0036] In the first embodiment, expansion is possible not only in the capacity direction by a high-capacity structure, but also in the accuracy direction by a high-precision structure.

[0037] Figure 8 shows the high-bit representation of the interaction. In such cases, ΔE i As shown in the following equation, each ΔE i l This can be calculated by bit-shifting and adding the values.

number

[0038] That is, for example, a high bit width interaction J ij high Let's assume that = 0 001 101 111. In this case, the high bit width interaction J ij high The interaction of the higher bits J ij tоp =0 001, Interaction of the middle bit J ij mid =0 101, and interaction of the lower bits Jij bоt Let's assume we bitwise divide the interaction into three parts: 0, 111, and 111. Here, we define the divided interaction values ​​as partial interaction values.

[0039] In this case, ΔE i =2 6 ×ΔE i tоp +2 3 ×ΔE i mid +ΔE i bоt ΔE i High bit width interaction J ij high The same applies when the bit is divided into four or more parts. A detailed explanation of the configuration that achieves this level of high precision will be provided below.

[0040] Figure 9 shows an example of a block diagram of a ΔE block according to the first embodiment. This figure shows a high-precision structure comprising four ΔE blocks. As shown in this figure, all four ΔE blocks have the same numbered interaction J 1,1 ~J 4,4 This is stored there. However, each of the four ΔE blocks stores a different bit digit.

[0041] Here, ΔE blocks 1 to 4 correspond to array modules 100_1 to 100_4, respectively. Also, in each of ΔE blocks 1 to 4, the block that stores spins σ1 to σ4 corresponds to spin block 110. Furthermore, interaction J 1,1 ~J 4,4 The block that stores the data corresponds to interaction block 120. Additionally, the four multipliers and four adders correspond to arithmetic block 130.

[0042] Therefore, the processing system 10 comprises multiple array modules 100, each having a spin block 110 that stores a spin value indicating the state of each spin in a plurality of spins, an interaction block 120 that stores partial interaction values ​​obtained by dividing the interaction value indicating the coupling weight between each spin in the plurality of spins, and an operation block 130 that outputs the calculation result regarding the energy of a model including multiple spins, calculated based on the spin value and partial interaction value. In this case, each of the multiple array modules 100 stores partial interaction values ​​containing different bits in the interaction value in the interaction block 120.

[0043] Figure 10 shows an example of a block diagram of a control block according to the first embodiment. In the control block, the spin is updated by bit shift addition, as shown in this figure.

[0044] Here, the control block corresponds to the control module 200. Therefore, the processing system 10 receives the calculation results (in this figure, ΔE) output from the multiple array modules 100. i 1 ~ΔE i 4 ) Integrated result E i Based on this, the spin states of multiple spins are controlled. In this case, the control module 200 may bit-shift the calculation results when adding the calculation results output from the multiple array modules 100.

[0045] More specifically, the control module 200 outputs the calculation result ΔE from ΔE block 1. i 1 2 0 You may multiply by it. Similarly, the control module 200 outputs the calculation result ΔE from block 2. i 2 2 N-1 You may multiply by it. Similarly, the control module 200 outputs the calculation result ΔE from ΔE block 3. i 3 22(N-1) You may multiply by it. Similarly, the control module 200 outputs the calculation result ΔE from ΔE block 4. i 4 2 3(N-1) Multiplication is permitted. The control module 200 stores, for example, the number of bits corresponding to each of the multiple array modules 100, and may bit-shift the calculation results output from the multiple array modules 100 according to the number of bits.

[0046] Then, the control module 200 adds these multiplied results to obtain the integrated result ΔE i You may calculate this. As a result, the control module 200 will have MSB(ΔE i +h i Due to ±T), spin σ i It can be updated.

[0047] Figure 11 shows the internal structure of a ΔE block that combines the conventional structure and the structure of the first embodiment. In this figure, for the sake of explanation, only ΔE block 1 is shown, but ΔE blocks 2 to 4 may be configured in the same way as ΔE block 1.

[0048] Figure 12 shows an example of a block diagram of a processing system 10 employing a high-capacity structure and a high-precision structure. In this figure, interaction J ij This shows the case where the data is divided into three high-capacity structures (ΔE block groups A to C) and stored.

[0049] Figure 13 shows the addition in the control block, focusing on the bit levels. In the implementation, it is provided as a 22-bit calculation box (10-bit J). ij ×2048 spins → 2 9+11 (21 bits: bits + sign bit). However, it is possible to have 22 bits or more by performing bit shifts and sign padding.

[0050] According to the processing system 10 of the first embodiment, for example, the interaction J which was previously 4 to 6 bitsij It becomes easy to make the bit width 10 bits or more, and ΔE i This makes it possible to perform calculations with high accuracy. As a result, the processing system 10 according to the first embodiment can achieve higher accuracy compared to conventional calculations using the Ising model.

[0051] (Second embodiment) In the second embodiment, speed is achieved by introducing a multi-state spin that transitions between multiple values ​​considering intermediate states, instead of the conventional binary spin. This will be explained in detail.

[0052] Conventional annealing processors are computers that solve combinatorial optimization problems by reducing them to the form of the Ising model. Therefore, the spins handled internally were represented as binary values. In contrast, in the second embodiment, instead of the Ising model, discrete multi-valued values ​​inspired by the Heisenberg model are used for the spin values.

[0053] Figure 14 is a conceptual diagram illustrating the possible states of spin. The top of the figure shows a conceptual diagram of the possible states of spin in the Ising model. The bottom of the figure shows a conceptual diagram of the possible states of spin in the Heisenberg model. As shown in the bottom of the figure, in the Heisenberg model, spin can take on intermediate states between ±1.

[0054] In the second embodiment, the possible states of the spin are represented by 2K natural numbers K, as shown in the following equation. This is called a multistate spin. The actual value that each state can take can be freely set within the range of ±1. Here, for example, 2K is 2 n By setting it to the value of ΔE, as will be described later, the integration can be replaced with a right bit shift, i This can suppress the increase in the size of the calculation circuit.

number

[0055] Figure 15 schematically illustrates the state transitions of a spin. The top of the figure shows the state transitions in a binary spin. The bottom of the figure shows the state transitions in a multi-state spin, i.e., an 8-state multi-state spin, when K=4.

[0056] The introduction of multi-state spins is expected to enable simultaneous updating of multiple spins while maintaining solution accuracy. This means that the maximum change in spin value per update will increase from 2 to 1-S. -1 Therefore, ΔE due to simultaneous updates i This is because it helps to minimize discrepancies in the calculation results.

[0057] Furthermore, the Ising model and the Heisenberg model are identical except for the possible spin values, so J ij ya h i Other computational algorithms, such as the derivation of [the formula], can be used as they are.

[0058] Next, the circuit modification according to the second embodiment will be described. First, in order to distinguish each state of a multi-state spin, a log 22K bit register is required for each spin. For example, if K=4, the spin block 110 is expanded to 3 bits per spin. In this way, the spin block 110 stores a spin value indicating the state of each spin in a multi-spin configuration, with a width of multiple bits.

[0059] Figure 16 shows an example of a circuit that implements the storage of a multistate spin. This figure shows an example of a circuit for implementing an 8-state multistate spin on an FPGA. Here, since the 8-state multistate spin is represented by 3 bits, three DFFs are used.

[0060] The circuit shown in this figure utilizes the spin_out[2:0] of the preceding stage connected in series with the spin_in[2:0] of the succeeding stage, and operates as follows: During writing, when the clock enable en_write is 1, the spin_write[2:0] obtained from the spin update circuit is written. During reading, when the read address en_read is 0, the spin_out[2:0] of the preceding stage is passed directly to the succeeding stage. When the read address en_read is 1, the output Q of the DFF is output from spin_out[2:0].

[0061] If, for example, 16 such circuits are connected in series, en_read will be a 16-bit wide signal. By setting any one bit of this signal to 1, the output of the corresponding spin register can be taken from the last stage's spin_out[2:0].

[0062] Furthermore, the multiplier in arithmetic block 130 calculates the product of the spin value and the interaction value. Therefore, directly using multistate spin in the calculation may increase the circuit size. To this end, the calculation is simplified by using a right bit shift in the multiplier. Here, S1=2 -3 , S2=2 -2 , and S3=2 -1 That is what they say.

[0063] Figure 17 shows an example of a modified block diagram of the multiplier. The bit expander expands the number of bits in the interaction value. The bit shifter right-shifts the expanded interaction value based on some bits in the spin value. The selector chooses whether to invert the output of the bit shifter based on other bits in the spin value. Each of the multiple multipliers in the arithmetic block 130 is modified to include such a bit expander, bit shifter, and selector.

[0064] Furthermore, when using multi-state spin, ΔE occurs during spin update. iIn addition to the most significant bit, it is necessary to refer to the current spin value. Therefore, the current spin value is added to the input of the spin updater. Furthermore, the conditional branch based on the current spin value is also changed according to the pseudocode.

[0065] Next, circuit changes for simultaneous update will be described. To effectively use the idle array module 100, multi-spin threads are introduced. For example, four array modules 100 are grouped into a set to calculate four solutions in parallel. This corresponds to being able to calculate four ΔE i in parallel across the entire processing system 10. Therefore, by sharing a set of spin blocks 110 across the entire processing system 10, simultaneous update of four spins can be achieved.

[0066] Also, by increasing the number of product-sum units implemented in one array module 100 to X, the number of ΔE i calculated in parallel is further increased. By combining this with multi-spin threads, the total number of simultaneous updates across the entire processing system 10 can be made 4 × X. Along with this, the pseudo-random number generator and spin updater in the control module 200 are also increased to 4 × X.

[0067] With such changes made, a 1024-spin 16-parallel system composed of 16 array modules 100 and 1 control module 200 was implemented.

[0068] FIG. 18 is a diagram showing an example of a block diagram of the array module 100 in the second embodiment. In this figure, four array modules 100 in the row direction are grouped into a set. Specifically, the four array modules 100 are σ1 to σ 256 σ 257 to σ 512 σ 513 to σ 768 σ 769 to σ 1024Each of them is stored. And, it has a structure in which one spin block 110 is shared by four array modules 100 in the column direction.

[0069] In this figure, the spin block 110 is composed of a 3-bit × 256 spin register. More specifically, the spin block 110 stores spins σ1 to σ 256 in 32 rows × 8 columns. Thus, the spin block 110 stores the spin values for each spin σ in a matrix form.

[0070] Also, in this figure, the interaction block 120 is composed of four 8-bit × 16384 RAMs grouped into one set. More specifically, in the array module 100_1, the interactions J 1,1 ~J 64,256 are stored in the RAM in 512 rows × 32 columns. Similarly, in the array module 100_2, the interactions J 65,1 ~J 128,256 are stored in the RAM in 512 rows × 32 columns. Similarly, in the array module 100_3, the interactions J 129,1 ~J 192,256 are stored in the RAM in 512 rows × 32 columns. Similarly, in the array module 100_4, the interactions J 193,1 ~J 256,256 are stored in the RAM in 512 rows × 32 columns. And these four RAMs are grouped into one set. Thus, the interaction block 120 stores the interaction values between each spin in a matrix form.

[0071] And, the operation block 130 has a plurality of multipliers that calculate each component of the matrix product of the spin values and the interaction values, and an adder that adds the outputs of the plurality of multipliers. More specifically, in one array module 100, X × 32 multipliers and X accumulators are implemented. In this figure, X = 4, and a group of four array modules 100 enables the simultaneous update of 4 × 4 spins.

[0072] In this case, each of the multiple multipliers in the arithmetic block 130 includes, as described above, a bit expander for expanding the number of bits in the interaction value, a bit shifter for right-shifting the expanded interaction value based on some bits in the spin value, and a selector for choosing whether or not to invert the output of the bit shifter based on other bits in the spin value.

[0073] The control module 200 then integrates the partial sum of energy from each array module 100 as shown in the following equation.

number

[0074] Therefore, 16 calculation results can be obtained simultaneously. The control module 200 then integrates the calculation results output from each of the multiple array modules 100 to obtain the integrated result ΔE. i Based on this, the updating of the spin state in multiple spins is controlled simultaneously.

[0075] According to the processing system 10 of the second embodiment, by introducing multi-state spins that take intermediate states into consideration, the maximum change in spin value with each update can be reduced. This improves tolerance to simultaneous updates, so that multiple spins σ can be updated simultaneously. Therefore, according to the processing system of the second embodiment, a speed increase (for example, by more than an order of magnitude) can be achieved compared to conventional calculations using the Ising model.

[0076] This disclosure is not limited to the foregoing, and it goes without saying that it can be implemented in various modified forms without departing from its intent. [Explanation of Symbols]

[0077] 10 Processing System 100 Array Modules 110 Spin Blocks 120 Interaction Blocks 130 arithmetic blocks 200 control modules 300 interfaces

Claims

1. Each of the spin blocks stores a spin value that indicates the state of each spin in a set of multiple spins, An interaction block stores partial interaction values ​​obtained by dividing the interaction values ​​representing the coupling weights between each of the multiple spins, A plurality of array modules, each having a calculation block that outputs a calculation result regarding the energy of a model including the plurality of spins, calculated based on the spin value and the partial interaction value, The system includes a control module that controls the state of the spins in the plurality of spins based on an integrated result obtained by integrating the calculation results output from the plurality of array modules, Each of the array modules stores the partial interaction values, which include different bits in the interaction value, in the interaction block. Processing system.

2. The control module, in adding the calculation results output from the plurality of array modules, performs a bit shift on the calculation results. The processing system according to claim 1.

3. The control module is Each of the aforementioned array modules stores the number of bits corresponding to it, and the calculation results output from the aforementioned array modules are bit-shifted according to the number of bits. The processing system according to claim 2.

4. A spin block stores a spin value indicating the spin state for each of the multiple spins, with each spin having a different bit width. An interaction block that stores interaction values ​​representing the coupling weights between each of the multiple spins, A calculation block that outputs calculation results regarding the energy of the model including the multiple spins, calculated based on the spin values ​​and interaction values, The system includes a control module that simultaneously controls the updating of the spin states in the plurality of spins based on the calculation results, Processing system.

5. The spin block stores the spin values ​​for each spin in the form of a matrix, The interaction block stores the interaction values ​​for each spin in the form of a matrix, The Z operation block is, A plurality of multipliers that calculate each component of the product of the matrix of the spin value and the interaction value, An adder that adds the outputs of the plurality of multipliers, The processing system according to claim 4.

6. Each of the aforementioned multipliers is A bit expander for expanding the number of bits in the interaction value, A bit shifter that right-shifts the interaction value, whose number of bits has been expanded, based on some bits in the spin value, A selector that selects whether to invert the output of the bit shifter based on other bits in the spin value, The processing system according to claim 5.

7. The array comprises a plurality of array modules, each having the spin block, the interaction block, and the calculation block, The control module controls the updating of the spin state in the plurality of spins based on the integrated result obtained by integrating the calculation results output from each of the plurality of array modules. The processing system according to any one of claims 4 to 6.

Images