Simulated annealing acceleration method and related equipment

Abstract

The invention relates to a simulated annealing acceleration method and related equipment, and the method comprises the steps: receiving simulated annealing parameters needed for executing an annealing task for a plurality of annealing examples of an Isin model problem, and storing the vector information of main solution vectors of the plurality of annealing examples in a first storage module, the vector information comprises an M-bit spinning state value and record information; in the process of executing the annealing task on the plurality of annealing examples based on the simulated annealing parameters, reading and adjusting the vector information in the first storage module; and after the annealing tasks of the plurality of annealing instances are executed, reading vector information corresponding to the plurality of annealing instances from the first storage module, reconstructing candidate solution vectors based on the M-bit state values and the recorded information, and then taking the candidate solution vector with the lowest energy value as a global optimal solution. The problem that long and uncertain memory access delay is caused by frequent and high-bandwidth global solution vector synchronization operation of a traditional simulated annealing acceleration scheme is solved.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a simulated annealing acceleration method and related equipment. Background Technology

[0002] In cutting-edge computing scenarios such as quantum computing, simulated annealing algorithms are often used to provide high-quality initial solutions for subsequent precise calculations (such as the Coherent Ising Machine (CIM) physical machine calculation) or to benchmark algorithm performance. However, the slow computation speed of software-implemented simulated annealing algorithms has become a bottleneck in the entire simulated annealing computation process.

[0003] Although existing simulated annealing acceleration schemes based on Field-Programmable Gate Arrays (FPGAs) offer speed improvements over software-implemented simulated annealing, their performance is limited by inefficient solution vector management mechanisms. The specific problems and root causes are as follows: The large and uncertain iteration delay limits the speed of a single annealing cycle. This is because, after each iteration produces a better solution and triggers an update of the optimal solution state, traditional simulated annealing acceleration schemes need to write the solution vector (i.e., the entire spin configuration) of the currently iterated better solution back to external RAM (Random Access Memory) for "archiving." This frequent, high-bandwidth global solution vector synchronization operation in traditional simulated annealing acceleration schemes results in long and uncertain memory access delays, severely lengthening the algorithm's core "generate-evaluate-accept" iterative loop, leaving the computational unit in a waiting state for a significant amount of time. Summary of the Invention

[0004] The simulated annealing acceleration method and related equipment provided in this application at least solve the problem of long and uncertain memory access latency caused by the frequent, high-bandwidth global solution vector synchronization operation in traditional simulated annealing acceleration schemes.

[0005] According to one aspect of this application, a simulated annealing acceleration method is provided, the simulated annealing acceleration method being implemented at least through a field-programmable gate array (FPGA) chip, the FPGA chip including a first memory module, the method comprising: The system receives simulated annealing parameters required to perform annealing tasks on multiple annealing instances of the Ising model problem, and stores the vector information of the principal solution vectors of the multiple annealing instances in the first storage module. The vector information includes the state values ​​of the M spins in the principal solution vector, and recording information for recording which of the M state values ​​has been flipped. During the process of executing the annealing task on multiple annealing instances based on the simulated annealing parameters, the vector information is read and adjusted in the first storage module; After the annealing tasks of multiple annealing instances have been completed, the vector information corresponding to the multiple annealing instances is read from the first storage module, and the candidate solution vector of each annealing instance is reconstructed based on the M-bit state value and the record information. After calculating the energy values ​​of the candidate solution vectors corresponding to multiple annealing instances, the candidate solution vector with the lowest energy value is taken as the global optimal solution of the Ising model problem.

[0006] Further, the step of storing the vector information in the first storage module includes: The first storage module is divided into multiple storage areas, each of which includes a vector storage area and an incremental bitmap storage area. Multiple storage regions are allocated one-to-one to multiple annealing instances, with the vector storage region storing the M-bit state value corresponding to the annealing instance and the incremental bitmap storage region storing the record information. Both the vector storage region and the incremental bitmap storage region have the same depth and bit width, where the depth is the number of storage rows and the bit width is the number of bits per storage row. The step of reading the vector information corresponding to multiple annealing instances from the first storage module includes: Read the M-bit state value from the vector storage area and read the record information from the incremental bitmap storage area.

[0007] Furthermore, the step of adjusting the vector information in the first storage module includes: During the execution of the annealing task for each annealing instance, if the state value at bit pos in the vector storage area is flipped, the value of the storage bit at bit pos in the incremental bitmap storage area is set to "1", otherwise it is set to "0", and the record information composed of the values ​​of all the storage bits is obtained. Then, based on the M-bit state values ​​and the recorded information, the steps for reconstructing the candidate solution vectors for each annealing instance include: Perform a bitwise XOR operation on the M-bit state value and the recorded information to obtain the candidate solution vector.

[0008] Furthermore, the storage area also includes a row dirty flag storage area, which includes flag bits set one-to-one with the storage rows. The step of adjusting the vector information in the first storage module further includes: All flag bits in the initial state of the dirty flag storage area are set to the valid state, and when the value of the storage bit at the pos-th bit in the incremental bitmap storage area is flipped, the flag bit corresponding to the storage row to which the storage bit at the pos-th bit belongs is set from the valid state to the invalid state.

[0009] The method further includes: Before reconstructing the candidate solution vectors of each annealing instance based on the M-bit state value and the record information, if the record information is determined to be valid based on the invalid state in the row dirty flag storage area, then the value of the record information stored in the incremental bitmap storage area is read from the incremental bitmap storage area to reconstruct the candidate solution vectors.

[0010] Furthermore, after the annealing task of each annealing instance is completed, the method further includes: Set all the flag bits in the row dirty flag storage area of ​​the annealing instance to the valid state, so as to logically clear all the storage bits in the incremental bitmap storage area.

[0011] Furthermore, the annealing task includes multiple rounds of annealing iterations, and the field-programmable gate array chip also includes a computing core array with at least C+3 computing cores. The step of executing the annealing task on multiple annealing instances based on the simulated annealing parameters includes: Obtain the temperature value required for each annealing iteration based on the simulated annealing parameters, and divide the process of each round of annealing iteration into C sub-stages including a first stage, a second stage, a third stage, and a fourth stage (C+3 processing stages), where M is a multiple of N and C is an integer, where: The C sub-stages are respectively used to calculate the energy change component generated after the state value at position pos in the C spin sets is flipped. The spin sets are divided into sets according to the N state values. The first stage is used to obtain the parameter items required by the C sub-stages to calculate the energy change component. The parameter items include the coupling data in the pos row of the coupling matrix and the N state values ​​corresponding to the spin sets stored in the first storage module. The third stage is used to sum the energy change components to obtain the total energy change ΔE, and then determine whether to accept the flip based on the total energy change ΔE, the generated random number, and the temperature value. The fourth stage is used to perform the adjustment operation on the vector information in the first storage module when the third stage determines that the flip is accepted. According to a predetermined pipeline scheduling sequence, the computing core array is controlled to process multiple annealing instances sequentially in a time-division multiplexing manner, so that C+3 computing cores process C+3 processing stages in a one-to-one correspondence, so that in each clock cycle, different computing cores process different processing stages of different annealing instances. The pipeline scheduling sequence is used to determine the start clock cycle of each processing stage of each annealing instance.

[0012] Furthermore, the step of determining the pipeline scheduling sequence includes: Obtain a predetermined fixed number of clock cycles C, and based on C, obtain the number of iteration cycles C+3 required to perform a single round of the annealing iteration for each annealing instance; Based on the iteration cycle number C+3, the start clock cycle of each processing stage of the plurality of annealing instances is set.

[0013] Furthermore, during the process of sequentially processing multiple annealing instances using time-division multiplexing, the method further includes: During each clock cycle, the computing core array reads multiple copies of the coupling data in parallel from the second storage module storing the coupling matrix, and each copy of the coupling data is processed by the computing core array for the first stage of the annealing instance.

[0014] Furthermore, the step of reading multiple copies of the coupling data in parallel from the second storage module storing the coupling matrix through the computing core array includes: Multiple copies of the coupled data can be read simultaneously through multiple access ports configured for the second storage module; or, Multiple copies of the coupled data are read simultaneously by accessing multiple repository banks logically divided by the second storage module, where each repository bank is a storage area that stores multiple copies of the coupled data in a one-to-one correspondence.

[0015] According to another aspect of this application, a simulated annealing accelerator is also provided, the simulated annealing accelerator comprising: A field-programmable gate array (FPGA) chip includes a control and scheduling module, a computing core array, and a first storage module. The control and scheduling module is connected between the computing core array and the first storage module. The first storage module is used to store vector information of the master solution vectors of multiple annealing instances. When the method is executed, the control and scheduling module controls the computing core array to perform the annealing task on the multiple annealing instances based on the simulated annealing parameters.

[0016] Furthermore, the first storage module includes multiple storage areas, each of which includes a vector storage area, an incremental bitmap storage area, and a row dirty flag storage area. The vector storage area is used to store the M-bit state value corresponding to the annealing instance, and the incremental bitmap storage area is used to store record information. The vector storage area and the incremental bitmap storage area have the same depth and bit width. The row dirty flag storage area includes flag bits that correspond one-to-one with the storage rows of the incremental bitmap storage area.

[0017] Furthermore, the simulated annealing accelerator also includes: The second storage module is connected to the control and scheduling module and is used to store the coupling matrix.

[0018] Furthermore, the second storage module is provided with multiple access ports, so that the control scheduling module can simultaneously read multiple sets of coupled data through the multiple access ports; or, The second storage module is divided into multiple storage banks, so that the control and scheduling module can simultaneously read multiple sets of coupled data through the multiple storage banks. The multiple storage banks are storage areas that store multiple sets of coupled data in a one-to-one correspondence.

[0019] According to another aspect of this application, a quantum computer is also provided, the quantum computer including the simulated annealing accelerator described above, or the quantum computer being connected to the simulated annealing accelerator described above.

[0020] According to another aspect of this application, an electronic device is also provided, comprising: a processor, and a memory storing a program, the program including instructions that, when executed by the processor, cause the processor to perform the simulated annealing acceleration method.

[0021] According to another aspect of this application, a non-transitory machine-readable medium storing computer instructions for causing the computer to perform the simulated annealing acceleration method is also provided.

[0022] The beneficial effects of the embodiments of this application are as follows: The simulated annealing acceleration method provided in this application, when implemented using a field-programmable gate array (FPGA), stores the vector information of the master solution vector of the annealing instance in a first storage module. During the execution of annealing tasks on multiple annealing instances, the state value of the master solution vector for the current iteration remains entirely resident in the first storage module. In each iteration, all read and adjust operations on the master solution vector can be performed directly on the vector information in the first storage module. In other words, by utilizing the first storage module on the FPGA to reside the master solution vector, this application reduces memory access latency and eliminates the significant latency and performance uncertainty caused by frequent data exchange with the memory storing the optimal solution in traditional schemes. This improves the energy efficiency of the FPGA and the solution speed for simulated annealing. The FPGA can then complete a large number of high-precision simulated annealing calculations within a very short latency to meet the real-time requirements of the overall system.

[0023] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of the simulated annealing acceleration method provided in the embodiments of this application.

[0026] Figure 2 This is a schematic diagram of the data stored in the first storage module in this embodiment.

[0027] Figure 3 This is a schematic diagram of the computing core array in this embodiment.

[0028] Figure 4 This is a schematic diagram illustrating the execution of annealing tasks on multiple annealing instances based on simulated annealing parameters in this embodiment.

[0029] Figure 5 This is a schematic diagram of the structure of a simulated annealing accelerator provided in one embodiment of this application.

[0030] In the picture: 10. Field Programmable Gate Array (FPGA) chip; 11. Control and scheduling module; 12. First storage module; 13. Computing core array; 14. External interface module; 20. Second storage module. Detailed Implementation

[0031] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that embodiments of this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the embodiments of this application. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0032] As mentioned earlier, the frequent, high-bandwidth global solution vector synchronization operations performed by traditional simulated annealing acceleration schemes lead to long and uncertain memory access latency. Furthermore, through in-depth research, the inventors of this invention have discovered that traditional simulated annealing acceleration schemes also struggle to achieve efficient pipelined parallelism, limiting system throughput. This is because, given the aforementioned uncertain iteration latency and the time conflicts and scheduling complexities that arise when multiple parallel annealing instances access RAM to update their solution vectors, traditional architectures struggle to organize multiple independent annealing processes into a regular pipeline. This results in the FPGA's abundant parallel computing resources not being fully utilized, and the overall system throughput failing to increase linearly with resource investment.

[0033] To address the aforementioned problems, the first embodiment of this application provides a simulated annealing acceleration method. This simulated annealing acceleration method is implemented at least through a field-programmable gate array (FPGA) chip 10, which includes a first memory module 12. Please refer to... Figure 1 The simulated annealing acceleration method includes the following steps: Step S11: Receive the simulated annealing parameters required to perform the annealing task on multiple annealing instances of the Ising model problem, and store the vector information of the principal solution vectors of the multiple annealing instances in the first storage module 12. The vector information includes the state values ​​of the M spins in the principal solution vector, and the recording information used to record which state value among the M state values ​​has been flipped. M is an integer.

[0034] The annealing task involves gradually cooling the Ising model problem according to a preset annealing curve, driving the problem to converge to the global optimum. The preset annealing curve is obtained from a temperature scheduling table composed of temperature values ​​generated from simulated annealing parameters. This table stores the temperature values ​​required for each annealing iteration. During the iteration, the corresponding temperature value is retrieved to determine whether the spin state value of the corresponding bit in the principal solution vector needs to be updated or adjusted. The principal solution vector is the spin configuration of the annealed instance of the Ising model problem at a certain moment, such as S={ , ,…, }, each of which (That is, the i-th spin) can only be +1 or -1. The goal of the annealing task is to evolve the random initial state into the spin with the lowest energy through the cooling process, thereby obtaining the global optimal solution.

[0035] Step S12: During the annealing task execution for multiple annealing instances based on simulated annealing parameters, vector information is read and adjusted in the first storage module 12. This method of storing the master solution vector-related vector information on-chip means that storage, adjustment, and reading are all implemented in the first storage module 12 (such as the vector storage area and incremental bitmap storage area mentioned later). Therefore, during each annealing iteration of the annealing task, there is no need to frequently exchange data with the memory storing the optimal solution, eliminating the resulting significant latency and performance uncertainty. The adjustment operation here includes determining whether the state value of a specific bit (such as the pos-th bit mentioned later) needs to be flipped after each annealing iteration.

[0036] Step S13: After the annealing tasks of multiple annealing instances have been completed, the vector information corresponding to the multiple annealing instances is read from the first storage module 12. Based on the M-bit state values ​​and record information, the candidate solution vectors of each annealing instance are reconstructed. The reconstructed candidate solution vectors are the energy of the latest state of the current annealing instance, which is the basis for comparison in selecting the globally optimal solution. The record information can determine which state value has been flipped, thereby accurately reconstructing the candidate solution vectors.

[0037] Step S14: After calculating the energy values ​​of candidate solution vectors corresponding to multiple annealing instances, the candidate solution vector with the lowest energy value is taken as the global optimal solution to the Ising model problem. The global optimal solution and its energy value can then be output to the host computer, which may include a quantum computer, to improve the speed and energy efficiency of solving the Ising model problem.

[0038] Through the above-described scheme, when the simulated annealing acceleration method provided in this application embodiment is implemented by the field-programmable gate array (FPGA) chip 10, since the vector information of the master solution vector of the annealing instance is stored in the first storage module 12, the state value of the master solution vector of the current iteration can be fully resided in the first storage module 12 during the annealing task execution for multiple annealing instances. During each iteration, all reading and adjustment operations for the master solution vector are completed within the FPGA chip 10, allowing direct reading and adjustment of vector information in the first storage module 12. In other words, this application reduces memory access latency by utilizing the first storage module 12 on the FPGA chip 10 to reside the master solution vector, eliminating the significant latency and performance uncertainty caused by frequent data exchange with the memory storing the optimal solution in traditional schemes. This improves the energy efficiency of the FPGA chip 10 and the solution speed for simulated annealing processing, enabling the FPGA chip 10 to complete a large number of high-precision simulated annealing calculations within a very short delay to meet the real-time requirements of the overall system.

[0039] To facilitate the storage of the master solution vector and the recording of its state updates after each annealing iteration, the vector information in this application also includes recording information for recording which bit of the M-bit state value has been flipped. The step of storing the vector information in the first storage module 12 includes: The first storage module 12 is divided into multiple storage areas, each of which includes a vector storage area and an incremental bitmap storage area.

[0040] Multiple storage areas are allocated one-to-one to multiple annealing instances, with the M-bit state value of the corresponding annealing instance stored in the vector storage area and the record information stored in the incremental bitmap storage area.

[0041] In this application, the incremental bitmap storage area is a storage area with the same capacity as the vector storage area. That is, each storage bit in the incremental bitmap storage area corresponds one-to-one with the storage bit in the vector storage area that stores the spin state value. For example, as shown... Figure 2 As shown, the vector storage area and the incremental bitmap storage area have the same depth and bit width. The depth is the number of rows in the vector storage area and the incremental bitmap storage area, and the bit width is the number of bits per row.

[0042] The vector storage area stores and resides the state values ​​of the master solution vector, which are continuously updated from the start to the end of the current annealing instance. This vector storage area loads the initial solution of each state value of the corresponding master solution vector when the annealing instance starts, and is directly read and written as the unique master copy of the solution vector throughout the entire iteration process. The incremental bitmap storage area records which bits in the master solution vector have undergone state flips since the last "logical snapshot" (i.e., after a certain annealing instance has completed all annealing iterations). This enables direct storage, adjustment, and retrieval of the corresponding vector information in both the vector storage area and the incremental bitmap storage area.

[0043] The step of reading vector information corresponding to multiple annealing instances from the first storage module 12 includes: The application reads M-bit state values ​​from the vector storage area and record information from the incremental bitmap storage area to reconstruct the candidate solution vector based on the read M-bit state values ​​and record information. In other words, this application can store the state values ​​of the main solution vector in the vector storage area and record the flipping of state values ​​in the incremental bitmap storage area, thereby providing a basis for reconstructing the candidate solution vector.

[0044] like Figure 2 As shown, the steps of adjusting vector information in the first storage module 12 of this application include: During the annealing process for each annealing instance, if the state value of the pos-th bit in the vector storage area is flipped, the value of the pos-th bit in the incremental bitmap storage area is set to "1", otherwise it is set to "0", thus obtaining the record information composed of the values ​​of all storage bits.

[0045] Therefore, based on the M-bit state values ​​and record information, the steps for reconstructing the candidate solution vectors for each annealing instance include: Perform a bitwise XOR operation on the M-bit state values ​​and the recorded information to obtain the candidate solution vector.

[0046] If the recorded information obtained here is [0,1,0,0], it indicates that the state value at the position corresponding to the storage bit in the vector storage area that is "1" in the incremental bitmap storage area has been flipped. When the vector storage area stores the state value of the corresponding spin, if the spin is +1, the value of the corresponding storage bit in the vector storage area is set to "1", and if the spin is -1, the value of the corresponding storage bit in the vector storage area is set to "0", thus storing the main solution vector as a binary vector. During the XOR operation, if the main solution vector is [1,0,1,0,1,1,0,0], and the recorded information is [0,1, 0,1, 0, 0,1,0], the bitwise XOR operation (XOR) rules are: 0 XOR 0 = 0, 0 XOR 1 = 1, 1 XOR 0 = 1, 1 XOR 1 = 0. Then the candidate solution vector obtained is: [1,1,1, 1,1,1, 1,0].

[0047] This application efficiently generates candidate solution vectors by performing a bitwise XOR operation between the values ​​stored in the vector storage area and the incremental bitmap storage area, without directly modifying the main solution vector. This method is highly efficient in hardware implementation, suitable for parallel processing, and provides a foundation for the implementation of subsequent parallel pipelines.

[0048] The storage area in this application also includes a row dirty flag storage area. Multiple row dirty flag storage areas are allocated one-to-one to multiple annealing instances. Each row dirty flag storage area includes flag bits set one-to-one with a storage row. The step of adjusting vector information in the first storage module 12 further includes: All flag bits in the initial dirty flag storage area are set to valid. When the value of the pos-th bit in the incremental bitmap storage area is flipped (e.g., set to "1"), the flag bit corresponding to the storage row to which the pos-th bit belongs is set from valid to invalid. Therefore, when reconstructing candidate solution vectors, the invalidity of each flag bit in the dirty flag storage area can determine whether the physical storage data stored in the incremental bitmap storage area is valid (i.e., physical storage data cannot be considered logic 0), allowing the reconstruction of candidate solution vectors to be performed using the record information indicating valid physical data. In some implementations, flag bits in the valid state are set to "1", and flag bits in the invalid state are set to "0".

[0049] The simulation acceleration method provided in this application also includes the following steps: Before reconstructing the candidate solution vectors of each annealing instance based on the state value and the record information of the M bits, if the record information is determined to be valid based on the invalid state in the row dirty flag storage area, the value (i.e., physical storage data) of the record information stored in the incremental bitmap storage area is read out from the incremental bitmap storage area to reconstruct the candidate solution vectors, thereby achieving accurate reconstruction of the candidate solution vectors.

[0050] After the annealing task of each annealing instance is completed, the simulated annealing acceleration method provided in this application further includes the following steps: All flag bits in the row dirty flag storage area of ​​the annealing instance are set to a valid state, logically clearing all storage bits in the incremental bitmap storage area. This step is the "logical snapshot" generation step. This operation logically and instantaneously clears the values ​​of each storage bit in the incremental bitmap storage area, marking that the state value stored in the current vector storage area is officially locked as the final solution at the end of the annealing task of this annealing instance, and the time consumption is strictly fixed to one clock cycle. When the simulated annealing acceleration method of this application is executed by the control scheduling module 11 of the simulated annealing accelerator, the control scheduling module 11 performs a single-cycle, deterministic logical clearing operation: setting all flag bits in the entire row dirty flag storage area corresponding to the annealing instance to a valid state (e.g., setting all to "1").

[0051] This application reduces the time required to generate a solution vector snapshot from O(N) to O(1) by logically and instantaneously clearing the incremental bitmap storage area through the row dirty flag storage area, thus eliminating the nondeterminism and performance bottleneck caused by traditional copying operations.

[0052] Secondly, this application can also mark the status information of the storage area of ​​the annealing instance through the control scheduling module 11. The status information includes information to indicate that the storage area stores the final solution, such as marking "calculation completed, holding a valid solution", freezing the contents of the vector storage area, and waiting to enter step S14 to perform a global comparison.

[0053] The annealing task includes multiple rounds of annealing iterations. In each round, the temperature value required for the current iteration is read from the temperature schedule table to determine whether the spin of the corresponding bit in the principal solution vector needs to be flipped. The field-programmable gate array chip 10 also includes a computing core array 13 with at least C+3 computing cores.

[0054] The steps for performing annealing tasks on multiple annealing instances based on simulated annealing parameters include: Step S21: Obtain the temperature value required for each annealing iteration based on the simulated annealing parameters, and divide the process of each annealing iteration into a first stage, C sub-stages of the second stage, a third stage, and C+3 processing stages of the fourth stage, where M is a multiple of N and C is an integer. Where: The C sub-stages are used to calculate the energy change component generated after the state value at position pos in the C spin sets is flipped. The spin sets are divided into sets based on N state values. The first stage is used to obtain the parameter items required for calculating the energy change component in the C sub-stages. The parameter items include the coupling data in the pos row of the coupling matrix and the N state values ​​corresponding to the spin sets stored in the first storage module 12. The third stage is used to sum the energy change components to obtain the total energy change ΔE, and then determine whether to accept the flip based on the total energy change ΔE, the generated random number, and the temperature value (i.e., probability acceptance decision - Metropolis criterion decision). The fourth stage is used to adjust the vector information in the first storage module 12 when the third stage determines that the flip is accepted. This adjustment operation includes: performing a flip operation on the state value at position pos in the vector storage area, such as flipping the spin at position pos from +1 to -1 after the flip.

[0055] Step S22: According to the predetermined pipeline scheduling sequence, control the computing core array 13 to process multiple annealing instances sequentially using time-division multiplexing, so that C+3 computing cores process C+3 processing stages one-to-one, so that in each clock cycle, different computing cores process different processing stages of different annealing instances. The pipeline scheduling sequence is used to determine the start clock cycle of each processing stage of each annealing instance. Figure 3 As shown, the C+3 computational cores are interconnected, and the connection order of each computational core is consistent with the order in which the C+3 processing stages are processed, so as to ensure that after one of the processing stages of an annealing instance is completed, it immediately enters the next computational core for the next stage of processing.

[0056] For example, a sub-stage includes four phases (where C equals 4). Computation core 1 processes the first phase, computation core 2 calculates the energy change component of the first sub-stage of the second phase, computation core 3 calculates the energy change component of the second sub-stage, computation core 4 processes the energy change component of the third sub-stage, computation core 5 calculates the energy change component of the fourth sub-stage, computation core 6 processes the third phase, and computation core 7 processes the fourth phase. Therefore, according to the pipelined scheduling sequence, the first phase of annealing instance 0 can be started in the first clock cycle and processed by computation core 1. In the second clock cycle, the first phase of annealing instance 1 can be started and processed by computation core 1, while annealing instance 0 enters its first sub-stage and is processed by computation core 2. In the third clock cycle, the first stage of annealing instance 2 is initiated and handled by extreme core 1. Simultaneously, computation core 2 processes the first sub-stage of annealing instance 1, computation core 3 processes the second sub-stage of annealing instance 0, and so on. In the seventh clock cycle, computation core 4 completes the fourth stage of annealing instance 0 and outputs the result of this iteration (i.e., accepting or rejecting the flip). Then, computation core 4 continues processing the fourth stage of annealing instance 1, computation core 6 processes the third stage of annealing instance 2, and computation core 1 processes the first stage of annealing instance 6. Thereafter, each clock cycle completes the iterative computation of one annealing instance and initiates the first stage of a new annealing instance.

[0057] Through the pipelined parallel processing in steps S21 to S22 described above, the method provided in this application can fully utilize the hardware resources of the computing core array 13 already present in the field-programmable gate array chip 10, arranging multiple independent annealing iterations into a highly efficient "computing pipeline." Different annealing instances, like products on a factory assembly line, sequentially enter the processing stage. At any given time, hardware resources are simultaneously processing multiple instances at different stages of computation, achieving 100% utilization of hardware computing resources and increasing throughput to several times that of traditional batch processing.

[0058] In this application, the steps for determining the pipeline scheduling sequence include: A predetermined fixed number of clock cycles C is obtained, and the number of iteration cycles C+3 required for a single round of annealing iteration for each annealing instance is obtained based on C. The fixed number of clock cycles C is the ratio between M and N, representing the number of cycles required for the computational cores of the processing sub-stage to update M state values. This fixed number of clock cycles C is pre-calculated by the control scheduling module 11 based on the number of spins M of the main solution vector and the fixed parameters of the hardware design (i.e., the number of spins N processed in parallel per clock cycle for each computational core). Then, the control scheduling module 11 adds the fixed number of clock cycles C to the three clock cycles required for processing the first, third, and fourth stages to obtain the number of iteration cycles C+3 required for a single round of annealing iteration for each annealing instance. The control scheduling module 11 can set the start clock cycle for each processing stage of multiple annealing instances based on the number of iteration cycles C+3.

[0059] To make the above pipeline process clearer, for example, for a single annealing iteration functional pipeline (C=4), a task with a duration of (C+3) cycles is broken down into subtasks executed in series by (C+3) dedicated hardware modules (computing cores 1 to 7). The responsibilities of these seven computing cores and their correspondence with each stage in step S21 are shown in the table below: Table 1 Table 1 and Figure 4 This demonstrates how multiple annealing instances can utilize the fixed hardware resource of the compute core array 13 in a time-staggered manner to achieve high-throughput parallelism. Hardware utilization is also visually illustrated from the perspective of the compute cores (hardware modules).

[0060] In the process of sequentially processing multiple annealing instances using time-division multiplexing, the method provided in this application further includes the following steps: Within each clock cycle, the compute core array 13 reads multiple sets of coupled data in parallel from the second storage module 20 storing the coupling matrix. Each set of coupled data is used by the compute core array 13 to process the first stage of the corresponding annealing instance. The number of sets of coupled data read each time can be equal to the number of annealing instances. This parallel data reading method ensures that the pipeline scheduling process runs conflict-free and efficiently.

[0061] The steps of reading multiple sets of coupled data in parallel from the second storage module 20 storing the coupling matrix using the computational core array 13 include: simultaneously reading multiple sets of coupled data through multiple access ports configured for the second storage module 20; or simultaneously reading multiple sets of coupled data by accessing multiple repository banks logically divided by the second storage module 20, where each repository bank is a storage area that stores multiple sets of coupled data in a one-to-one correspondence. Thus, by using a multi-port design or by interleaved access to the repository banks, multiple sets of coupled data can be read in parallel, solving the concurrent access bottleneck in the annealing instance execution process, improving parallel read / write capabilities, and thereby improving the processing efficiency of annealing iterations.

[0062] The second storage module 20 in this application is connected to the control and scheduling module 11 of the field-programmable gate array (FPGA) chip 10, enabling the control and scheduling module 11 to read the corresponding coupled data for use by the computing core array 13. The second storage module 20 may include off-chip memory (such as Double Data Rate SDRAM), which is located outside the FPGA chip 10 and connected to the control and scheduling module 11. Alternatively, the second storage module 20 may include a large-capacity on-chip memory configured within the FPGA chip 10. The on-chip memory may include High Bandwidth Memory (HBM) or Unified Random Access Memory (URAM).

[0063] A second embodiment of this application also provides a simulated annealing accelerator, which includes a field-programmable gate array (FPGA) chip 10. The FPGA chip 10 includes a control and scheduling module 11, a computing core array 13, and a first storage module 12. The control and scheduling module 11 is connected between the computing core array 13 and the first storage module 12. The first storage module 12 is used to store vector information of the master solution vectors of multiple annealing instances. When the control and scheduling module 11 executes the simulated annealing acceleration method provided in the first embodiment of this application, it controls the computing core array 13 to perform annealing tasks on multiple annealing instances based on simulated annealing parameters. For details of the simulated annealing acceleration method, please refer to the content provided in the first embodiment of this application, which will not be repeated here.

[0064] As can be seen, the entire simulated annealing accelerator provided in this application is driven by a central control and scheduling module 11. The control and scheduling module 11 can pre-calculate the precise clock rhythm of all operations (such as C+3 mentioned above) based on the spin number scale of the Ixin model problem and the hardware parameters of the computational core array 13. From data loading and annealing iteration calculation to result writing back, each step is completed within a defined period, making the entire calculation process completely predictable and controllable, thereby supporting the stable operation of the deep pipeline in the first embodiment of this application.

[0065] Ultimately, this application transforms the simulated annealing algorithm from a slow-iterating, serially dependent software algorithm into a fast-iterating, highly parallel hardware acceleration engine, which is particularly suitable for solving combinatorial optimization problems such as large-scale Ising models, achieving orders of magnitude improvements in throughput and energy efficiency.

[0066] The first storage module 12 in this application includes multiple storage areas, each including a vector storage area, an incremental bitmap storage area, and a row dirty flag storage area. The vector storage area stores the M-bit status value of the corresponding annealing instance. The incremental bitmap storage area stores record information. Both the vector storage area and the incremental bitmap storage area have the same depth and bit width. The row dirty flag storage area includes flag bits that correspond one-to-one with the storage rows of the incremental bitmap storage area. For details on the functions and roles of each storage area, please refer to the content provided in the first embodiment of this application. The multiple storage areas in this application provide an efficient read / write hardware foundation for supporting the execution of multiple simultaneously active annealing instances at pipeline depth.

[0067] The simulated annealing accelerator in this application also includes a second storage module 20, which is connected to the control and scheduling module 11 and is used to store the coupling matrix.

[0068] The second storage module 20 is provided with multiple access ports, so that the control and scheduling module 11 can simultaneously read multiple sets of coupled data through multiple access ports. Alternatively, the second storage module 20 is divided into multiple storage banks, so that the control and scheduling module 11 can simultaneously read multiple sets of coupled data through multiple storage banks, and the multiple storage banks are storage areas that store multiple sets of coupled data in a one-to-one correspondence.

[0069] The first storage module 12 in this application may include a memory BRAM (short for block random access memory, which is a dedicated static memory module integrated into the FPGA).

[0070] The second storage module 20 in this application may include off-chip memory (such as Double Data Rate SDRAM), which is located outside the field-programmable gate array (FPGA) chip 10 and connected to the control and scheduling module 11 of the FPGA chip 10. Alternatively, the second storage module 20 may include a large-capacity on-chip memory configured within the FPGA chip 10. The on-chip memory may include High Bandwidth Memory (HBM) or Unified Random Access Memory (URAM).

[0071] Based on the simulated annealing method provided in the first embodiment and the simulated annealing accelerator provided in the second embodiment of this application, to make this application clearer, the third embodiment of this application provides a simulated annealing accelerator based on solution vector full residency and deterministic pipeline, and an acceleration method for its implementation. Figure 5 As shown in the system architecture diagram of the simulated annealing accelerator, the simulated annealing accelerator mainly includes a control and scheduling module 11 of a field-programmable gate array chip 10, a computing core array 13, an on-chip memory architecture (a first memory module 12 or a first memory module 12 and a second memory module 20), and an external interface module 14. The external interface module 14 is connected to the control and scheduling module 11 and is used to receive the parameters required for computation. The complete workflow and technical details of the simulated annealing accelerator are as follows: Step S1: Receiving and Verifying Problem Parameters The host computer (such as the host software of a quantum computer) sends the parameters of the Ising model problem to be solved (including the coupling matrix J and the external field h) and the simulated annealing parameters (including the initial temperature T0, the termination temperature Tend, the cooling coefficient α, the Markov chain length L, and the number of independent annealings K) to the field-programmable gate array (FPGA) chip 10 via the PCIe interface. The external interface module 14 on the FPGA side receives the data stream, and the control scheduling module 11 performs compliance checks on the dimension, numerical range, and format of each parameter. After the compliance check is passed, the parameters (coupling matrix J and external field h) are stored in the second storage module 20. The second storage module 20 includes off-chip memory (such as DDR) or high-capacity on-chip memory (such as HBM / URAM). At the same time, the control scheduling module 11 loads the simulated annealing parameters into the internal control register of the FPGA chip 10.

[0072] Step S2: Pre-configuration of calculation parameters and initialization of resources The control and scheduling module 11 pre-calculates key operating parameters and allocates on-chip memory resources based on the problem size of the Ising model (total number of spins M) and fixed hardware design parameters (such as the number of spins N processed in parallel per cycle per computation core). Calculate the fixed number of clock cycles: Determine the fixed number of clock cycles C = (M / N) required to complete one full solution vector update. This parameter C is the reference clock cycle for building subsequent deterministic pipelines.

[0073] Generate a temperature scheduling table: based on the initial temperature Termination temperature The temperature coefficient α and the Markov chain length L are pre-calculated to determine the temperature value corresponding to each round of Markov chain iteration and stored in a temperature lookup table composed of on-chip RAM, ensuring that all computing cores can read the same temperature value in real time and synchronously during the iteration process.

[0074] The calculation of the temperature value required for the k-th annealing iteration is as follows: k takes the value (0, 1, 2, ..., L-1), or k is the number of iterations to the termination temperature.

[0075] To allocate private storage space for multiple annealing instances: To support D simultaneously active annealing instances at pipeline depth D, three independent storage areas are allocated for each annealing instance in the first storage module 12: Vector storage area: Used to store and reside the state values ​​of the M spins of the main solution vector that are continuously updated from the start to the end of this annealing instance. This vector storage area is loaded with the initial solution of the M spins when the annealing instance starts, and is directly read and written as the unique main copy of the solution vector throughout the entire iteration process.

[0076] Incremental Bitmap Storage Area: A storage area with the same capacity as the vector storage area. Each storage bit in the incremental bitmap storage area corresponds one-to-one with a storage bit in the master solution vector. The incremental bitmap storage area is used to record which spin bits in the master solution vector have had their state values ​​flipped since the last "logical snapshot". During initialization, all storage bits in the incremental bitmap storage area are set to "0".

[0077] Dirty Row Flag Storage Area: A register group with a width equal to the depth of the incremental bitmap storage area. Each flag bit in the dirty row flag storage area corresponds to a row in the incremental bitmap storage area. This dirty row flag storage area is used to implement "logical zeroing": when the flag bit corresponding to a certain row in the incremental bitmap storage area is in a valid state (e.g., set to '1'), it indicates that logically, the data in that row in the incremental bitmap storage area should be treated as all 0s, ignoring its actual physical value. During initialization, the flag bits of all rows are set to a valid state.

[0078] Step S3: Deterministic pipeline scheduling of parallel annealing instances The control scheduling module 11 employs a deep pipeline scheduling strategy, dividing the single annealing iteration cycle (C+3 iteration cycles) of each annealing instance into multiple overlapping pipeline stages. The pipeline scheduling sequence should be adjusted as follows: Based on the pipeline stage division shown in Table 1 above, each annealing iteration (S4.1-S4.4) of a single annealing instance is divided into 4 pipeline processing stages: Phase 1: Flip bit generation and data prefetching (1 cycle).

[0079] The second stage: calculate the energy change components in blocks (C cycles, which can be further divided into C sub-stages).

[0080] Phase 3: Summarize the energy change components and make a probabilistic acceptance decision (1 cycle).

[0081] Phase 4: Adjustments are made directly based on incremental solution vectors to update the stored data in each storage area (1 cycle).

[0082] Production line startup and scheduling: Cycle 1: Initiating the first phase of annealing instance 0; Phase 2: Start the first phase of annealing instance 1, while annealing instance 0 enters the first sub-phase of the second phase; Phase 3: Start the first phase of annealing instance 2, annealing instance 1 enters the first sub-phase of the second phase, and annealing instance 0 enters the second sub-phase of the second phase; ... In cycle (C+3): Annealing instance 0 completes the fourth stage and outputs the result of this iteration; at the same time, annealing instance 1 enters the fourth stage, annealing instance 2 enters the third stage, and annealing instance C+2 enters the first stage.

[0083] Each subsequent clock cycle completes the annealing iteration calculation for one annealing instance and initiates the first phase of a new annealing instance.

[0084] Pipeline Steady State: Once the pipeline is full (after starting C+3 instances), the system enters steady state. In steady state: Each clock cycle, the C+3 different annealing instances are in different pipeline processing stages. Each clock cycle, the compute core array 13 processes data from different annealing instances. Each clock cycle completes one annealing iteration calculation for one annealing instance. All compute cores in the compute core array 13 operate at full capacity.

[0085] To ensure conflict - free, in resource access scheduling, the computing core array 13 processes multiple annealing instances sequentially in a time - division multiplexing manner, and processes the block calculations of different annealing instances in each clock cycle.

[0086] The second storage module 20 adopts a multi - port design or interleaved access to memory banks, and supports the control scheduling module 11 to read the coupled data of multiple annealing instances simultaneously in each clock cycle.

[0087] Shared resources such as the temperature look - up table and control logic achieve resource sharing for multiple annealing instances through pipeline registers.

[0088] Step S4: The core loop of a single - round annealing iteration for each annealing instance For any active annealing instance in the pipeline, its L annealing iterations at each temperature follow a deterministic operation sequence with a fixed length of C + 3 clock cycles (where C is the number of cycles required for block calculation): S4.1, Flip bit generation and data pre - fetching (1st cycle): Generate a random spin - flip position pos for the current annealing iteration. According to pos, pre - fetch the coupled data of the pos - th row of the coupling matrix J (or the data block corresponding to the coupled data of this row) from the second storage module 20 to the cache location of this annealing instance (this cache location can be within the first storage module 12). At the same time, read the state value of the current main solution vector from the vector storage area.

[0089] S4.2, Block energy difference calculation (2nd to C + 1 cycles): The computing core array 13 calculates the total energy change ΔE of the system caused by flipping the spin of the pos - th bit in a pipelined manner with a parallel granularity of processing N spins per cycle for C consecutive cycles, and calculates each energy change component ΔH of ΔE.

[0090] ΔH = 4 , is the coupled data of the pos - th row of the coupling matrix J.

[0091] S4.3, Energy summation and probability acceptance decision (C + 2nd cycle): Sum up the energy change components ΔH calculated in C cycles to obtain the total energy change ΔE. At the same time, read the current temperature value T and generate a random number rand. Complete the Metropolis criterion decision within one cycle: If ΔE < 0 or rand < exp(-ΔE / T), then decide to accept this flip.

[0092] S4.4, Direct update of the solution vector based on increment (C + 3rd cycle): If the decision result is to accept the flip, then perform the following atomic operations in parallel within this cycle: Update the main solution vector: directly perform a flip operation on the state value of the pos - th bit in the vector storage area.

[0093] Record Increment: Perform a flip operation (change 0 to 1 or 1 to 0) on bit pos in the incremental bitmap storage area to mark that the state of the bit has changed since the last logical snapshot (i.e., after all rounds of annealing iterations of a certain annealing instance have ended).

[0094] Clear dirty flags: In the dirty flag storage area, set the flag position corresponding to the storage row of the incremental bitmap storage area to an invalid state (e.g., clear to zero), indicating that the physical data of that row in the incremental bitmap storage area is valid and cannot be regarded as logical zero.

[0095] Step S5: Instance Completion and Logical Snapshot Generation After an annealing instance completes all annealing iterations across the entire temperature chain: First, a logical snapshot is generated: the control scheduling module 11 executes a single-cycle, deterministic "logical zeroing" operation: the entire row dirty flag storage area corresponding to the annealing instance is set to a valid state (e.g., all '1'). This operation logically and instantaneously clears the values ​​of each storage bit in the incremental bitmap storage area, marking that the state value in the current vector storage area is officially locked as the final solution of this annealing task, and the time taken is strictly fixed to one clock cycle.

[0096] Resource status marking: The storage resources (vector storage area, incremental bitmap storage area, and row dirty flag storage area) of this annealing instance are marked as "computation completed, holding a valid solution", and their contents are frozen, waiting for global comparison.

[0097] Step S6: Global Optimal Solution Selection and Output After all K annealing iterations have been completed, the control scheduling module 11 starts a comparison tree module to select the globally optimal solution from the K annealing instances: Candidate solution vector reconstruction: For each annealing instance, its candidate solution vector for comparison is reconstructed by reading its vector storage area and querying the incremental bitmap storage area in parallel (the validity of the flipped data is determined based on the state of the row dirty flag storage area during the query). Specifically, the state value of the vector storage area is XORed with the logically valid record information in the incremental bitmap storage area.

[0098] Energy calculation and comparison: Quickly calculate the corresponding energy value for each reconstructed candidate solution vector, and quickly select the global optimal solution with the lowest energy value and its energy value through a multi-level comparator (comparison tree).

[0099] Output: Finally, the global optimal solution and the corresponding energy value are returned to the host through the external interface module 14, completing a complete accelerated calculation task.

[0100] As can be seen from the above, this scheme completely eliminates the nondeterminism and performance bottleneck caused by large-scale data movement between solution vector replicas in traditional schemes through the "master solution vector full-resident update" and "incremental bitmap logical snapshot" mechanisms. It ensures that every step of the operation from iteration, instance completion to global comparison has strict periodic determinism, thus laying a key foundation for realizing a high-throughput, deep-pipeline hardware accelerator.

[0101] This application transforms the simulated annealing algorithm from one with uncertain iteration cycles and strong serial dependencies into a hardware-friendly algorithm with fixed iteration cycles and high pipelined parallelism through two core designs: "full resident master solution vector" and "deterministic delay-based deep pipeline". Its technical contributions are as follows: 11) Solution vector update mechanism based on incremental bitmap storage area: The flip change of the main solution vector is recorded in an independent incremental bitmap storage area, instead of directly updating multiple copies, avoiding large-scale data migration and realizing deterministic single-cycle update.

[0102] 12) Row Dirty Flag Logical Snapshot: By logically clearing the incremental bitmap storage area instantly through the row dirty flag storage area, the time taken to generate solution vector snapshot is reduced from O(N) to O(1), eliminating the nondeterminism and performance bottleneck caused by traditional copying operations.

[0103] 13) Deterministic deep pipeline scheduling: By splitting the annealing iteration process of each annealing instance into pipeline processing stages with a fixed cycle (C+3), and starting new annealing instances at strict cycle (1 cycle) intervals, high-throughput, conflict-free parallel computing is achieved, making hardware behavior completely predictable.

[0104] 14) Block-parallel energy difference calculation: The computing unit performs pipelined block processing on the solution vector with a fixed granularity (N bits / cycle). The energy difference calculation is decomposed into a certain number of cycles (C), realizing full utilization of computing resources and precise control of computing time.

[0105] This application accelerates the multiple annealing process and the multiple iterations within a single annealing process simultaneously through hardware parallelization and pipeline design, achieving coordinated hardware acceleration of the "exploration breadth" and "iteration depth" of the simulated annealing algorithm, and significantly improving the throughput and energy efficiency of solving optimization problems such as the Ising model problem.

[0106] In conclusion, the fundamental innovation of this application lies in the design of a novel on-chip storage-based solution vector iterative management algorithm and hardware architecture.

[0107] Eliminating global synchronization and achieving deterministic delay iteration: By keeping the complete solution vector of each annealing instance always residing in the first storage module 12, all state transitions, energy change calculations, and acceptance judgments are completed without using an additional optimal solution memory. The final optimal solution is only written back to the optimal solution memory RAM when a complete annealing process is finished. This completely avoids frequent external accesses to the optimal solution memory RAM during iteration, making the delay of a single iteration extremely short and completely deterministic.

[0108] Deterministic pipelined parallelism: Because the iteration process of each annealing instance has a deterministic and short clock cycle, this application can orchestrate a large number of annealing instances into a deep, well-organized pipeline. Different annealing instances are at different temperature stages of annealing, but they move forward synchronously like a factory assembly line. This achieves a qualitative leap from "multi-instance batch processing" to "multi-instance pipeline," enabling hardware computing resource utilization to approach 100%, thereby completing orders of magnitude more annealing calculations per unit time and greatly improving system throughput.

[0109] The fourth embodiment of this application also provides a quantum computer, which includes a simulated annealing accelerator. The simulated annealing accelerator is configured within the quantum computer and can send the output global optimal solution and its energy value to the host computer software of the quantum computer. Alternatively, the quantum computer is connected to the simulated annealing accelerator, which is used as an independent device and can send the output global optimal solution and its energy value to the host computer software of the quantum computer. For details on the simulated annealing accelerator, please refer to the second and third embodiments of this application, which will not be repeated here.

[0110] The fifth embodiment of this application also provides an electronic device, including: a processor, and a memory storing a program, the program including instructions that, when executed by the processor, cause the processor to perform the simulated annealing acceleration method provided in the first embodiment of this application.

[0111] The sixth embodiment of this application also provides a non-transitory machine-readable medium storing computer instructions for causing a computer to execute the simulated annealing acceleration method provided in the first embodiment of this application.

[0112] Computer programs used to implement the methods of the embodiments of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of embodiments of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0114] It should be noted that the term "comprising" and its variations used in the embodiments of this application are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; and the term "some embodiments" means "at least some embodiments". The modifications of "one" and "multiple" mentioned in the embodiments of this application are illustrative and not restrictive. Those skilled in the art should understand that, unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0115] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0116] The steps described in the method embodiments provided in this application can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of this application is not limited in this respect.

[0117] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence from or alternative to other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A simulated annealing acceleration method, characterized in that, The simulated annealing acceleration method is implemented at least through a field-programmable gate array (FPGA) chip (10), which includes a first memory module (12). The method includes: Receive the simulated annealing parameters required to perform annealing tasks on multiple annealing instances of the Ising model problem, and store the vector information of the principal solution vectors of the multiple annealing instances in the first storage module (12). The vector information includes the state value of the M spins in the principal solution vector, and the recording information used to record which of the M state values ​​has been flipped. During the process of executing the annealing task on multiple annealing instances based on the simulated annealing parameters, the vector information is read and adjusted in the first storage module (12); After the annealing tasks of multiple annealing instances are completed, the vector information corresponding to multiple annealing instances is read from the first storage module (12), and the candidate solution vector of each annealing instance is reconstructed based on the M-bit state value and the record information. After calculating the energy values ​​of the candidate solution vectors corresponding to multiple annealing instances, the candidate solution vector with the lowest energy value is taken as the global optimal solution of the Ising model problem.

2. The method according to claim 1, characterized in that, The step of storing the vector information in the first storage module (12) includes: The first storage module (12) is divided into multiple storage areas, each of which includes a vector storage area and an incremental bitmap storage area; Multiple storage regions are allocated one-to-one to multiple annealing instances, with the vector storage region storing the M-bit state value corresponding to the annealing instance and the incremental bitmap storage region storing the record information. Both the vector storage region and the incremental bitmap storage region have the same depth and bit width, where the depth is the number of storage rows and the bit width is the number of bits per storage row. The step of reading the vector information corresponding to the plurality of annealing instances from the first storage module (12) includes: Read the M-bit state value from the vector storage area and read the record information from the incremental bitmap storage area.

3. The method according to claim 2, characterized in that, The steps of adjusting the vector information in the first storage module (12) include: During the execution of the annealing task for each annealing instance, if the state value at bit pos in the vector storage area is flipped, the value of the storage bit at bit pos in the incremental bitmap storage area is set to "1", otherwise it is set to "0", thus obtaining the record information composed of the values ​​of all the storage bits; Then, based on the M-bit state values ​​and the recorded information, the steps for reconstructing the candidate solution vectors for each annealing instance include: Perform a bitwise XOR operation on the M-bit state value and the recorded information to obtain the candidate solution vector.

4. The method according to claim 3, characterized in that, The storage area further includes a row dirt flag storage area, which includes flag bits set one-to-one with the storage rows. The step of adjusting the vector information in the first storage module (12) further includes: All the flag bits in the row dirty flag storage area in the initial state are set to the valid state, and when the value of the storage bit at the pos-th bit in the incremental bitmap storage area is flipped, the flag bit corresponding to the storage row to which the storage bit at the pos-th bit belongs is set from the valid state to the invalid state. The method further includes: Before reconstructing the candidate solution vectors of each annealing instance based on the M-bit state value and the record information, if the record information is determined to be valid based on the invalid state in the row dirty flag storage area, then the value of the record information stored in the incremental bitmap storage area is read from the incremental bitmap storage area to reconstruct the candidate solution vectors.

5. The method according to claim 4, characterized in that, After the annealing task of each annealing instance is completed, the method further includes: Set all the flag bits in the row dirty flag storage area of ​​the annealing instance to the valid state, so as to logically clear all the storage bits in the incremental bitmap storage area.

6. The method according to any one of claims 1 to 5, characterized in that, The annealing task includes multiple rounds of annealing iterations, and the field-programmable gate array chip (10) also includes a computing core array (13) with at least C+3 computing cores. The steps of executing the annealing task on multiple annealing instances based on the simulated annealing parameters include: Obtain the temperature value required for each annealing iteration based on the simulated annealing parameters, and divide the process of each round of annealing iteration into C sub-stages including a first stage, a second stage, a third stage, and a fourth stage (C+3 processing stages), where M is a multiple of N and C is an integer, where: The C sub-stages are respectively used to calculate the energy change component generated after the state value at position pos in the C spin sets is flipped. The spin sets are divided into sets according to the N state values. The first stage is used to obtain the parameter items required by the C sub-stages to calculate the energy change component. The parameter items include the coupling data in the pos row of the coupling matrix and the N state values ​​corresponding to the spin sets stored in the first storage module (12). The third stage is used to sum the energy change components to obtain the total energy change ΔE, and then determine whether to accept the flip based on the total energy change ΔE, the generated random number and the temperature value. The fourth stage is used to perform the adjustment operation on the vector information in the first storage module (12) when the third stage determines that the flip is accepted. According to the predetermined pipeline scheduling sequence, the computing core array (13) is controlled to process multiple annealing instances sequentially in a time-division multiplexing manner, so that C+3 computing cores process C+3 processing stages in a one-to-one correspondence, so that in each clock cycle, different computing cores process different processing stages of different annealing instances. The pipeline scheduling sequence is used to determine the start clock cycle of each processing stage of each annealing instance.

7. The method according to claim 6, characterized in that, The steps for determining the pipeline scheduling sequence include: Obtain a predetermined fixed number of clock cycles C, and based on C, obtain the number of iteration cycles C+3 required to perform a single round of the annealing iteration for each annealing instance; Based on the iteration cycle number C+3, the start clock cycle of each processing stage of the plurality of annealing instances is set.

8. The method according to claim 6, characterized in that, During the process of sequentially processing multiple annealing instances using time-division multiplexing in the computing core array (13), the method further includes: In each clock cycle, multiple copies of the coupling data are read in parallel from the second storage module (20) storing the coupling matrix by the computing core array (13), and each copy of the coupling data is processed by the computing core array (13) for the first stage of the corresponding annealing instance.

9. The method according to claim 8, characterized in that, The steps of reading multiple copies of the coupling data in parallel from the second storage module (20) storing the coupling matrix using the computing core array (13) include: Multiple copies of the coupled data can be read simultaneously through multiple access ports configured for the second storage module (20); or, Multiple copies of the coupled data are read simultaneously by accessing multiple repository banks logically divided by the second storage module (20), where each repository bank is a storage area that stores multiple copies of the coupled data in a one-to-one correspondence.

10. A simulated annealing accelerator, characterized in that, include: A field-programmable gate array (10) chip, the field-programmable gate array chip (10) includes a control scheduling module (11), a computing core array (13) and a first storage module (12), the control scheduling module (11) is connected between the computing core array (13) and the first storage module (12), the first storage module (12) is used to store vector information of the master solution vector of multiple annealing instances, and the control scheduling module (11) is used to control the computing core array (13) to perform the annealing task on multiple annealing instances based on the simulated annealing parameters when executing the method described in any one of claims 1 to 9.

11. The simulated annealing accelerator according to claim 10, characterized in that, The first storage module (12) includes multiple storage areas. Each storage area includes a vector storage area, an incremental bitmap storage area, and a row dirty flag storage area. The vector storage area is used to store the M-bit state value corresponding to the annealing instance. The incremental bitmap storage area is used to store record information. The vector storage area and the incremental bitmap storage area have the same depth and bit width. The row dirty flag storage area includes flag bits that correspond one-to-one with the storage rows of the incremental bitmap storage area.

12. The simulated annealing accelerator according to claim 10, characterized in that, The simulated annealing accelerator also includes: The second storage module (20) is connected to the control and scheduling module (11) and is used to store the coupling matrix.

13. The simulated annealing accelerator according to claim 12, characterized in that, The second storage module (20) is provided with multiple access ports, so that the control scheduling module (11) can simultaneously read multiple sets of coupled data through the multiple access ports; or, The second storage module (20) is divided into multiple storage banks, so that the control and scheduling module (11) can read multiple sets of coupled data simultaneously through the multiple storage banks. The multiple storage banks are storage areas that store multiple sets of coupled data in a one-to-one correspondence.

14. A quantum computer, characterized in that, The quantum computer includes the simulated annealing accelerator as described in any one of claims 10 to 13, or the quantum computer is connected to the simulated annealing accelerator as described in any one of claims 10 to 13.

15. An electronic device comprising: A processor and a memory storing a program, characterized in that the program includes instructions that, when executed by the processor, cause the processor to perform the simulated annealing acceleration method according to any one of claims 1 to 9.

16. A non-transitory machine-readable medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the simulated annealing acceleration method according to any one of claims 1 to 9.

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