System, computer implementation method, and computer program product (quantum circuit synthesis using a layered Clifford skeleton)

Abstract

The present invention provides a computer implementation method and / or computer program product for obtaining an output quantum circuit that can be executed in a quantum system. [Solution] In system 100, the quantum circuit synthesis system has a memory for storing computer-executable components and a processor for executing the computer-executable components stored in the memory. Here, the computer-executable components include an identification component that identifies an input sequence including an initial entanglement depth of Pauli rotations, and a circuit generation component that generates a hierarchical Clifford skeleton with a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

Description

Technical Field

[0001] The present disclosure relates to a quantum computing system, and more specifically, to the synthesis of quantum circuits for execution in a quantum computing system. The quantum circuit is based on an initial set of Pauli rotations and includes a hierarchical Clifford skeleton generated based on the initial set of Pauli rotations, providing a reduced entanglement depth compared to the initial set of Pauli rotations.

Summary of the Invention

[0002] In the following, an overview is presented to provide a basic understanding of one or more embodiments described herein. This overview is not intended to identify key or important elements, and / or to define the scope or claims of a particular embodiment. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that will be presented later. In one or more embodiments, the systems, computer-implemented methods, devices, and / or computer program products described herein can implement, for example, the quantum circuit synthesis of a Hamiltonian circuit that includes an initial set of Pauli rotations and has an initial undesirable entanglement depth. One or more embodiments described herein generally can generate a hierarchical Clifford skeleton that provides a reduced entanglement depth compared to an initial set of Pauli rotations, based on the initial set of Pauli rotations.

[0003] According to one embodiment, the system may include a memory for storing computer executable components, and a processor for executing the computer executable components stored in the memory, wherein the computer executable components include an identification component for identifying an input sequence including an initial entanglement depth of Pauli rotations, and a circuit generation component for generating a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

[0004] In another embodiment, a computer implementation method may include the steps of: identifying an input sequence of Pauli rotations, including an initial entanglement depth, using a system operably coupled to a processor; and generating a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

[0005] In yet another embodiment, the computer program product may include a computer-readable storage medium having program instructions that facilitate the quantum circuit compilation process and are executable by a processor, the program instructions causing the processor to identify an input sequence including an initial entanglement depth of Pauli rotations, and causing the processor to generate a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

[0006] The advantages of this system, computer implementation method, and / or computer program product include the ability to compile a quantum circuit based on an initial set of Pauli rotations, ranging from tens to hundreds or more rotations, thereby obtaining an output quantum circuit that may be executable in a quantum system. That is, the entanglement depth and / or number of rotations of the output quantum circuit is reduced compared to the initial entanglement depth and / or number of rotations corresponding to the initial set of Pauli rotations. In one or more cases, this compilation may enable the execution of a sequence of Pauli rotations in a quantum system that would otherwise be impossible and / or undesirably inefficient without using one or more embodiments described herein. For example, the compilation performed by one or more embodiments described herein may address one or more hardware constraints of the quantum system used to implement the sequence of Pauli rotations.

[0007] Another advantage of this system, computer implementation method, and / or computer program product is that it allows for the compilation of output quantum circuits based on a sequence of Pauli rotations using a hierarchical Clifford skeleton and without full connectivity. [Brief explanation of the drawing]

[0008] [Figure 1] The following are block diagrams of exemplary, non-limiting systems that can provide a process for compiling quantum circuits based on a sequence of Pauli rotations, according to one or more embodiments described herein.

[0009] [Figure 2] The following is a block diagram of another exemplary, non-limiting system that can provide a process for compiling a quantum circuit based on a sequence of Pauli rotations, according to one or more embodiments described herein.

[0010] [Figure 3] This specification shows a block diagram of a quantum system that may be used in connection with the systems shown in Figures 1 and 2, which are not limited to this specification, according to one or more embodiments described herein.

[0011] [Figure 4] This specification provides a schematic flowchart of the process for determining which gates to compile in a hierarchical Clifford skeleton in order to implement a sequence of Pauli rotations, as may be used in Figure 2, according to one or more embodiments described herein.

[0012] [Figure 5] This specification provides illustrations of directed acyclic graphs (DAGs), Steiner trees, and sequences of Steiner trees, as may be used in the embodiment shown in Figure 2, according to one or more embodiments described herein.

[0013] [Figure 6] This specification provides a schematic flowchart of a process that uses gates determined in relation to Figure 4 in a hierarchical Clifford skeleton to implement a series of Pauli rotations, such as those used in Figure 2, according to one or more embodiments described herein.

[0014] [Figure 7] To provide a process for compiling a quantum circuit based on a sequence of Pauli rotations according to one or more embodiments described herein, a flowchart of one or more processes that may be performed by the system shown in Figure 1 (not limited to this specification) is shown.

[0015] [Figure 8] To provide a process for compiling a quantum circuit based on a sequence of Pauli rotations according to one or more embodiments described herein, a flowchart of one or more processes that may be performed by the not-so-limited system shown in Figure 2 is provided.

[0016] [Figure 9]Continuation of the flowchart of FIG. 8 of one or more processes that may be executed by the non-limiting system of FIG. 2, according to one or more embodiments described herein.

[0017] [Figure 10] Continuation of the flowcharts of FIGS. 8 and 9 of one or more processes that may be executed by the non-limiting system of FIG. 2, according to one or more embodiments described herein.

[0018] [Figure 11] Shows a block diagram of an exemplary non-limiting computer environment according to one or more embodiments described herein. **DETAILED DESCRIPTION OF THE INVENTION**

[0019] The following detailed description is illustrative only and is not intended to limit embodiments and / or the use or application of embodiments. Further, there is no intention to be bound by any explicit or implicit information presented in the foregoing Summary of the Invention section or the Detailed Description of the Invention section. Here, reference is made to the drawings in which like reference numerals are used throughout to refer to like elements, and one or more embodiments will be described. In the following description, numerous specific details are set forth for the purpose of providing a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various cases without these specific details.

[0020] As a simple overview, in practice, the operation of quantum circuits in a quantum computer can be a time-intensive, memory-intensive, and / or power-intensive process, and these intensities can be at least partially based on the number of entanglements and / or entanglement depth of the quantum circuit during operation. In one or more cases, due to the very large number of entanglements and / or entanglement depth of the quantum circuit, the corresponding quantum computer may not be able to operate the quantum circuit, may error-stop, and / or may require an undesirable amount of time to completion.

[0021] In one or more other cases, due to the number of entanglements and / or entanglement depth, the operation of such a quantum circuit may introduce an undesirable level of noise and / or other errors into the system. Noise may be essentially caused by the operation of gates in the quantum computer and / or due to the hardware and / or software framework being used. Noise may manifest as errors in the quantum circuit output of the quantum computer (e.g., affecting the accuracy and / or precision of such a quantum circuit output compared to an ideal quantum circuit output).

[0022] Particularly in relation to quantum circuits (e.g., Hamiltonian circuits) based on input sequences of Pauli rotations, the corresponding number of entanglements, entanglement depth, operation time, and / or amount of noise resulting may be inefficient, undesirable, and / or may cause a state where the quantum circuit cannot be used (e.g., due to error-stopping, reduced accuracy, operation time, etc.).

[0023] In fact, existing frameworks for compiling quantum circuits based on sequences of Pauli rotations cannot scale to the increasingly large Pauli rotations for which implementation in quantum systems is being sought. In one or more cases, such sequences can correspond to various chemical and / or physical applications. Manipulating such sequences of increasingly large Pauli rotations is desirable but impossible using existing frameworks.

[0024] To address one or more defects, the cost of operating a quantum circuit based on a sequence of Pauli rotations (e.g., power, bandwidth, memory, time, etc.) can be reduced using one or more frameworks discovered by the inventors and discussed herein. As a result, an output quantum circuit can be obtained with a reduced entanglement depth (which may also refer to a reduced overall entanglement cost) compared to the initial entanglement depth corresponding to the sequence of Pauli rotations, based on a hierarchical Clifford skeleton and a sequence of Pauli rotations.

[0025] In one or more cases, but not limited to, a sequence of Pauli rotations can be a microcosm of a Hamiltonian simulation problem, for example, specified as a sparse combination of weighted Pauli operators. The time evolution of this sparse combination can be approximated by product formulas such as the first product formula and / or Trotter expansion. The resulting quantum circuit can be represented, for example, directly, as a sequence of Pauli rotations implemented on hardware (e.g., a quantum computer and / or quantum simulator with physical qubits).

[0026] In other words, given a sequence of Pauli rotations based on the intended application (e.g., chemical and / or physical applications, but not limited to those described below), the synthesis of a quantum circuit based on that sequence of Pauli rotations may be desirable. By minimizing the entanglement depth using one or more embodiments described herein, the quantum circuit can be made inexpensive enough to operate on available quantum system architectures (e.g., due to the costs described above).

[0027] In general, the initial entanglement depth of a sequence of Pauli rotations can be reduced by generating the corresponding output quantum circuits based on the Clifford skeleton. Using one or more embodiments described herein, a Clifford skeleton can be generated layer by layer using one or more selected Clifford circuits (e.g., a CNOT Clifford circuit including a CNOT quantum gate) that include quantum gates identified to reduce the initial entanglement depth. One or more selected Clifford circuits may be identified using one or more directed acyclic graphs corresponding to the sequence of Pauli rotations, Steiner trees corresponding to the Pauli rotations, and a cost function based on the Steiner tree.

[0028] As used herein, Clifford skeleton refers to a quantum circuit having a set of one or more Clifford circuits, each containing one or more Clifford gates.

[0029] In this specification, a Clifford gate refers to an element of a Clifford group or Clifford circuit.

[0030] As used herein, a Clifford circuit refers to a set of quantum operations that may include one or more Clifford gates that map an n-fold Pauli group product to itself.

[0031] The resulting hierarchical Clifford skeleton can be used to conjugate a sequence of Pauli rotations, thereby obtaining an output quantum circuit. That is, a Pauli rotation rotates around a Pauli axis and may contain multiple qubits. For example, the Clifford gates of the Clifford skeleton can be used to conjugate Pauli rotations. Generally, by applying Clifford gates to the left and right of a Pauli rotation in the Clifford skeleton, a new Pauli rotation with a different axis, rotating around a different Pauli operator, can be obtained. Those skilled in the art can track this transpilation process by conjugation with Clifford gates. In short, the Pauli rotations in this sequence can be iteratively conjugated through Clifford gates (e.g., from left to right along the Clifford skeleton) until the Pauli rotation becomes trivial. As used herein, the term “trivial” may refer, where possible, to an operation with a single qubit gate.

[0032] This transpilation process is based on the assumption that most quantum circuits can be efficiently transpiled as a sequence of Pauli rotations followed by a final Clifford operator. This is generally achieved by "attracting" all Clifford gates to the ends of the circuit and making them weakly commutating with the Pauli rotations.

[0033] As used herein, the term "data" may include metadata.

[0034] As used herein, the terms “entity,” “requesting entity,” “user entity,” and “managing entity” may refer to machines, devices, components, hardware, software, smart devices, stakeholders, organizations, individuals, and / or human beings.

[0035] Herein, one or more embodiments are described with reference to the drawings. Throughout, similar reference numerals are used to refer to similar elements. The following description includes numerous specific details to provide a more complete understanding of one or more embodiments for illustrative purposes. However, it is evident that in various cases one or more embodiments can be practiced without these specific details.

[0036] Furthermore, it should be understood that the embodiments shown in one or more figures described herein are for illustrative purposes only, and therefore the architecture of the embodiments is not limited to the systems, devices, and / or components shown therein, nor to any particular order, connection, and / or combination of the systems, devices, and / or components shown therein.

[0037] For example, in one or more embodiments, the systems 100 and / or 200 shown in Figures 1 and 2, and / or those systems may further include one or more computers and / or computing-based elements described herein in relation to a computing environment such as the computing environment 1000 shown in Figure 10. In one or more of the described embodiments, the computers and / or computing-based elements may be used in relation to implementing one or more of the systems, devices, components, and / or computer implementation operations illustrated and / or described in relation to Figures 1 and / or 2, and / or one or more other figures described herein.

[0038] Here, we will consider one or more figures in particular, and first, regarding Figure 1, this figure shows a block diagram of an exemplary, not-limited system 100 that can provide a process for compiling a quantum circuit based on a sequence of Pauli rotations using a classical quantum circuit synthesis system 102, and the output quantum circuit obtained by the quantum circuit compilation can be executed in quantum system 301 (Figure 3).

[0039] In other words, the unlimited system 100 may include the quantum circuit synthesis system 102 and quantum system 301, which are described in detail below. The quantum circuit synthesis system 102 is only briefly described in relation to Figure 1, in order to provide a mere prelude to the description of a more complex and / or more extended quantum circuit synthesis system 202, as shown in Figure 2. Further details regarding the processes that may be carried out by one or more embodiments described herein are provided below in relation to the unlimited system 200 in Figure 2.

[0040] Referring further to Figure 1, the quantum circuit synthesis system 102 may include at least a memory 104, a bus 105, a processor 106, an identification component 112, and / or a circuit generation component 128. Using these components, and optionally one or more inputs based on the quantum system 301 (e.g., qubit mapping and / or other hardware graphs relating thereto), the quantum circuit synthesis system 102 can realize the generation of a hierarchical Clifford skeleton 182 based on a sequence of Pauli rotations 152 inputs 150, and ultimately the generation of an output quantum circuit 188 based on the hierarchical Clifford skeleton 182.

[0041] Generally, the identification component 112 can identify the input column 150, which includes the initial entanglement depth 154 of the Pauli rotation 152.

[0042] The circuit generation component 128 can use the output 172 of the directed acyclic graph (DAG) 170 based on the input sequence 150 to generate a hierarchical Clifford skeleton 182 with a reduced entanglement depth 184 based on the input sequence 150.

[0043] In one or more embodiments, the identification component 112 and / or the decoding component 128 can be implemented independently without using the other of the identification component 112 and / or the decoding component 128. Additionally and / or alternatively, the identification component 112 and / or the decoding component 128 may be included in the analysis component 103, the analysis component 103 may perform one or more of the functions of the identification component 112 and / or the decoding component 128 described above, and / or the identification component 112 and / or the decoding component 128 may be omitted, in which case the analysis component 103 will perform one or more of the functions of the omitted identification component 112 and / or the decoding component 128 described above.

[0044] In general, an unspecified system 100 can bring about communication between a classical system 102 and a quantum system 301 using any suitable communication method (e.g., electronic, telecommunicative, internet, infrared, fiber, etc.).

[0045] In summary, referring briefly to Figure 7, a flowchart of an exemplary method 700, not limited to the present invention, is shown, which can provide a process for compiling a quantum circuit based on a sequence of Pauli rotations, according to one or more embodiments described herein, such as the system 100 not limited to the present invention of Figure 1. For simplicity, a description of similar elements and / or repetitions of the process used in each embodiment is omitted.

[0046] In 702, a method 700, which is not limited thereto, may include the step of identifying an input sequence (e.g., input sequence 150) including an initial entanglement depth (e.g., initial entanglement depth 154) of a Pauli rotation (e.g., Pauli rotation 152) by a system operably coupled to a processor (e.g., an identification component 112 coupled to processor 106).

[0047] Method 700, which is not limited to 704, may include the step of a system (e.g., circuit generation component 128) generating a hierarchical Clifford skeleton (e.g., hierarchical Clifford skeleton 182) having a reduced entanglement depth (e.g., reduced entanglement depth 184) based on the input sequence, using the output (e.g., output 172) of a directed acyclic graph (DAG) (e.g., DAG 170) based on the input sequence.

[0048] In 706, the non-limited method 700 may include a step in which the system (e.g., the circuit generation component 128) determines whether all Pauli (e.g., all Pauli rotations 152 of column 150) have been combined. If YES, the non-limited method 700 can proceed to termination. If NO, the non-limited method 700 can return to step 704.

[0049] Next, we consider Figure 2, which shows an unspecified system 200 that may include a quantum circuit synthesis system 202. For simplicity, descriptions of similar elements and / or repetitions of processes used in each embodiment are omitted. Descriptions relating to the embodiment in Figure 1 may also apply to the embodiment in Figure 2. Similarly, descriptions relating to the embodiment in Figure 2 may also apply to the embodiment in Figure 1.

[0050] In general, an unspecified system 200 can use a classical quantum circuit synthesis system 202 to facilitate the process of quantum circuit compilation based on a sequence of Pauli rotations, and the output quantum circuit obtained by quantum circuit compilation can be executed in quantum system 301 (Figure 3).

[0051] First, considering the quantum circuit synthesis system 202, one or more communications between one or more components of the system 200 (not limited to) may be provided by wired and / or wireless means, including, but not limited to, using a cellular network, a wide area network (WAN) (e.g., the Internet), and / or a local area network (LAN). Suitable wired or wireless technologies for supporting communications include, but not limited to, Wireless Fidelity (Wi-Fi®), Global System for Mobile Communications (GSM®), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX®), Enhanced General-Purpose Packet Radio Service (Enhanced GPRS), Third Generation Partnership Project (3GPP®) Long-Term Evolution (LTE), Third Generation Partnership Project 2 (3GPP2) WUT This may include Mobile Broadcast (UMB), High-Speed ​​Packet Access (HSPA), Zigbee® and other 802.XX radio technologies, and / or legacy telecommunications technologies, Bluetooth®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, Wireless HART protocol, 6LoWPAN (IPv6 on Low Power Wireless Area Networks), Z-Wave, Advanced and / or Adaptive Network Technology (ANT), Ultra-Wideband (UWB) standards protocols, and / or other proprietary and / or non-proprietary communication protocols.

[0052] The quantum circuit synthesis system 202 may be associated with (for example, accessible through) a cloud computing environment.

[0053] The quantum circuit synthesis system 202 may include multiple components. These components may include a memory 204, a processor 206, a bus 205, an identification component 212, a construction component 214, a tree generation component 216, a tree update component 218, a cost calculation component 220, a decision component 222, a compilation component 224, a conjugate component 226, a circuit generation component 228, a reduction component 240, an iterative component 232, and / or an output component 234. Using these components, and optionally one or more inputs based on the quantum system 301, the system 200, not limited to these components, can generally achieve the generation of a hierarchical Clifford skeleton 282 based on a sequence of Pauli rotations 252 inputs 250, and ultimately the generation of an output quantum circuit 288 based on the hierarchical Clifford skeleton 282.

[0054] That is, the identification component 212, the construction component 214, the tree generation component 216, the tree update component 218, the cost calculation component 220, the decision component 222, the compilation component 224, the conjugate component 226, the circuit generation component 228, the reduction component 240, the iteration component 232, and / or the output component 234 can operate in a classical system 202 of system 200, not limited to system 200. In one or more other embodiments, one or more processes performed by any one or more of the identification component 212, the construction component 214, the tree generation component 216, the tree update component 218, the cost calculation component 220, the decision component 222, the compilation component 224, the conjugate component 226, the circuit generation component 228, the reduction component 240, the iteration component 232, and / or the output component 234 can be performed in a quantum system 301.

[0055] First, we will briefly discuss the processor 206, memory 204, and bus 205 of the quantum circuit synthesis system 202. For example, in one or more embodiments, the quantum circuit synthesis system 202 may include a processor 206 (e.g., a computer processing unit, a microprocessor, a classical processor, a quantum processor, and / or a similar processor). In one or more embodiments, the components associated with the quantum circuit synthesis system 202, as described herein with or without reference to one or more figures of one or more embodiments, may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that can be executed by the processor 206 to result in the execution of one or more processes defined by such components and / or instructions. In one or more embodiments, the processor 206 may include an identification component 212, a construction component 214, a tree generation component 216, a tree update component 218, a cost calculation component 220, a decision component 222, a compilation component 224, a conjugate component 226, a circuit generation component 228, a reduction component 240, an iterative component 232, and / or an output component 234.

[0056] In one or more embodiments, the quantum circuit synthesis system 202 may include a computer-readable memory 204 which can be connected in an operable manner to a processor 206. The memory 204 can store computer-executable instructions that, when executed by the processor 206, cause the processor 206 and / or one or more other components of the quantum circuit synthesis system 202 (e.g., an identification component 212, a construction component 214, a tree generation component 216, a tree update component 218, a cost calculation component 220, a decision component 222, a compilation component 224, a conjugate component 226, a circuit generation component 228, a reduction component 240, an iteration component 232, and / or an output component 234) to perform one or more actions. In one or more embodiments, the memory 204 can store computer executable components (e.g., an identification component 212, a construction component 214, a tree generation component 216, a tree update component 218, a cost calculation component 220, a decision component 222, a compilation component 224, a conjugate component 226, a circuit generation component 228, a reduction component 240, an iteration component 232, and / or an output component 234).

[0057] The quantum circuit synthesis system 202 and / or its components as described herein may be coupled to each other electrically, electrically, operably, optically, and / or otherwise via a bus 205 so as to be able to communicate with each other. Bus 205 may include one or more of the following bus architectures: a memory bus, a memory controller, a peripheral bus, an external bus, a local bus, a quantum bus, and / or other types of buses. One or more of these examples of bus 205 may be used.

[0058] In one or more embodiments, the quantum circuit synthesis system 202 may be coupled (e.g., via a network) to one or more external systems (e.g., an electrical output generation system, one or more output targets, and / or output target controllers), sources, and / or devices (e.g., classical and / or quantum computing devices, communication devices, and / or similar devices) (e.g., communicatively, electrically, operationally, optically, and / or similarly). In one or more embodiments, one or more components of the quantum circuit synthesis system 202 and / or system 200 (not limited to) may reside in the cloud and / or locally in a local computing environment (e.g., at a specified location).

[0059] In general, the system 200, which is not limited to this, can provide communication between the quantum circuit synthesis system 202 and the quantum system 301 using any suitable communication method (e.g., electronic, telecommunicative, internet, infrared, fiber, etc.).

[0060] In addition to the processor 206 and / or memory 204 described above, the quantum circuit synthesis system 202 may include one or more components and / or instructions that are readable, writable, and / or executable by a computer and / or machine, and such components and / or instructions, when executed by the processor 206, may result in the execution of one or more operations defined by such components and / or instructions.

[0061] Next, we discuss further components of the quantum circuit synthesis system 202 (e.g., the identification component 212, the construction component 214, the tree generation component 216, the tree update component 218, the cost calculation component 220, the decision component 222, the compilation component 224, the conjugate component 226, the circuit generation component 228, the reduction component 240, the iteration component 232, and / or the output component 234).

[0062] First, in one or more embodiments, the identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234 can be implemented independently without using one or more other components among the identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234.Additionally and / or alternatively, the identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234 may be included in the analysis component 203, and one or more of the following functions of the identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234 may be performed by the analysis component 203. Good, and / or, the identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234 may be omitted, in which case the analysis component 203 will perform one or more of the functions described below of one or more of the omitted identification component 212, construction component 214, tree generation component 216, tree update component 218, cost calculation component 220, decision component 222, compilation component 224, conjugate component 226, circuit generation component 228, reduction component 240, iteration component 232, and / or output component 234.

[0063] First, considering the identification component 212, this component can generally search, locate, select, receive, download, upload, and / or otherwise identify an input sequence 250 containing the initial entanglement depth 254 of the Pauli rotation 252. In one or more cases, the identification component 212 can generally search, locate, select, receive, download, upload, and / or otherwise identify a quantum job request 324 that may contain and / or point to the input sequence 250. In one or more cases, the quantum job request 324 may be intercepted and / or acquired from the quantum system 301.

[0064] Pauli rotation 252 of column 250 is (P1, a1)···(P k ,a k Each of these can be explained using its corresponding axis and angle, where P is the axis, a is the angle, and k is the number of rotations.

[0065] In one or more embodiments, additionally and / or alternatively, the identification component 212 can generally search, locate, select, receive, download, upload, and / or otherwise identify the underlying Clifford skeleton 280 used by the quantum circuit synthesis system 202. For example, a layered Clifford skeleton 282 can be built from the underlying Clifford skeleton 280 by modifying it through the injection of selected Clifford circuits and the conjugation of Pauli rotations therein, as detailed below.

[0066] Additionally and / or alternatively, the circuit generation component 228 can generally generate a basic Clifford skeleton 280 based on, for example, the input sequence 250 of the Pauli rotation 252.

[0067] Next, the quantum circuit synthesis system 202 synthesizes the input sequence 250 of Pauli gates 252 using the input sequence 250 and the underlying Clifford skeleton 280, ultimately outputting an output quantum circuit 288 that is based on Pauli gates 252 but has a reduced entanglement depth 254, which can be run in quantum system 301 and / or other quantum systems and / or quantum simulation systems. In fact, the compilation performed by the quantum circuit synthesis system 202 ultimately yields an output quantum circuit 288 that may be applicable to quantum devices including physical qubits and / or quantum simulators that simulate qubits and qubit interactions.

[0068] Briefly considering the schematic flowchart 400 in Figure 4 as a roadmap, the modification of the base Clifford skeleton 280, also referred herein as the generation of a hierarchical Clifford skeleton 282, may include the generation of one or more directed acyclic graphs (DAGs) 270, the generation of one or more Steiner trees 290, the determination of one or more Steiner costs 292 associated with the Steiner trees, and the determination of a minimum-cost selected Clifford circuit 298 to be used for each of the multiple layers generated for the hierarchical Clifford skeleton 282. In this way, the hierarchical Clifford skeleton 282 can be iteratively constructed to reduce the Steiner cost of an input Pauli rotation (e.g., a Pauli rotation 252 of an input sequence 250).

[0069] As used herein, a selected Clifford circuit refers to a portion of an overall quantum circuit containing one or more CNOT gates (e.g., the basic Clifford skeleton 280 and / or the layered Clifford skeleton 282). In one or more cases, a selected Clifford circuit may also contain one or more further single-qubit Clifford gates. In one or more cases, a selected Clifford circuit may be called a selected CNOT Clifford circuit because it contains one or more CNOT gates.

[0070] As used herein, minimum cost refers to the cost of the degree of entanglement depth and / or entanglement gate, but is not limited to the following:

[0071] First, considering the construction component 214, this component can generally generate one or more DAGs 270 based on a column of Pauli rotations 252. That is, a DAG may be generated to represent a part or all of a column of Pauli rotations 252, where the connections (e.g., edges) between the nodes 502 of the DAG 270 represent Pauli rotations 252. In other words, the input column 250 can be stored as a DAG 270 that describes the anticommutative relations of rotations in the column 250, based on providing edges 504 between the nodes 502, each representing one Pauli rotation 252.

[0072] A brief look at the exemplary DAG diagram 500 in Figure 5 shows that, generally, edge 504 extends from the first node a (502A) to the second node b (502B) only when the axes of rotation of the Pauli rotations represented by nodes a and b are anticommutative, and when b follows a in the Pauli rotation sequence.

[0073] Accordingly, the order of the Pauli rotation sequence 250 is determined by the construction component 214 as it was initially obtained, and according to that order, the quantum circuit synthesis system 202 synthesizes the Pauli rotations 252 one by one in the same order using the DAG 270. This synthesis is schematically illustrated in Figures 4 to 6 (each of which will be described in detail later).

[0074] The quantum circuit synthesis system 202 (e.g., reduction component 230 and / or cost calculation component 220) can, in part, use the DAG 270 to identify whether a Pauli rotation 252 has a successor in the synthesis order being used and / or whether the remaining Pauli rotation 252 can be removed from the DAG 270 (e.g., by reduction component 230), synthesize such a Pauli rotation 252, and proceed to the next Pauli rotation 252 in that synthesis order. Alternatively, if a Pauli rotation 252 has a successor, it remains in the DAG 270 (e.g., maintained by reduction component 230 and / or cost calculation component 220), and further reduction of entanglement is performed using the synthesis schematically shown in Figures 4 to 6 (each of which will be described in detail later).

[0075] In one or more cases, it may be possible to relax the rotation ordering constraint (i.e., the composition of rotations 252 in a given order of column 250) by instead generating a trivial rotation DAG without edges. This may be useful when synthesizing circuits for applications where rotation ordering does not affect the circuit's performance.

[0076] However, before further discussing DAG270, Steiner tree 290, Steiner cost 292, and / or cost function 296, let us first focus on the quantum system in Figure 3, which is a system from which a qubit mapping (e.g., a hardware graph H) can be obtained by, for example, the identification component 212, and an output quantum circuit 288 can be executed (e.g., a system from which an implementation of a sequence 250 of Pauli rotations 252 is desired). For example, at least the tree generation component 220 can generate one or more Steiner trees 290 using qubit mapping.

[0077] Considering Figure 3, one or more embodiments described herein may include one or more devices, systems, and / or apparatus that can provide a process for generating one or more waveforms or pulses for quantum-based operations (e.g., using quantum devices), for example, for operating one or more qubits of a quantum device. Accordingly, Figure 3 shows a block diagram of an exemplary, not-limited system 300 that can at least partially facilitate such a process. Hereinafter, we refer to one or more processes, facilitations, and / or uses of the not-limited system 200, but the above and below descriptions provided herein may also apply to one or more other, not-limited systems described herein, e.g., not-limited systems 100 and / or 200.

[0078] As shown in Figure 2, the system 200, which is not limited to this, may include a quantum system 301 that can be used together with or separately from the classical systems 102 / 202. For example, as described above, one or more quantum circuit outputs 288 may be acquired and / or generated by a quantum circuit synthesis system 202 (e.g., a processor 206) based on one or more quantum measurement readouts 320 from the quantum system 301, where one or more quantum measurement readouts 320 have one or more errors on which quantum error correction should be performed.

[0079] In general, a quantum system 301 (e.g., a quantum computer system, a superconducting quantum computer system, and / or similar) can perform quantum operations and / or functions on input data using quantum algorithms and / or quantum circuit configurations, including computing components and / or devices, and generate results that can be output to an entity. A quantum circuit configuration may include qubits (qubits) such as multibit qubits, physical circuit-level components, high-level components and / or functions. A quantum circuit configuration can generate physical pulses that can be structured (e.g., arrays and / or designed) to perform desired quantum functions and / or computing on data (e.g., input data and / or intermediate data derived from input data) and produce one or more quantum results as outputs. A quantum result, e.g., a quantum measurement readout 320, can respond to a quantum job request 324 and associated input data, which can be at least partially based on the input data, quantum functions, and / or quantum computing.

[0080] In one or more embodiments, the quantum system 301 may include components such as an orchestrator component 303, a quantum processor 306, a pulse component (e.g., a waveform generator 310), and / or a readout electronic device 312 (e.g., a readout component).

[0081] The quantum processor 306 may include one or more, for example, multiple, qubits 307. Each qubit 307A, 307B, and 307C may be, for example, a fixed-frequency and / or single-junction qubit, such as a transmon qubit.

[0082] In one or more embodiments, the readout resonator can be associated with the physical hardware that defines the qubit 307, for example, by being positioned together with it.

[0083] In one or more embodiments, memory 316 and / or processor 314 may be associated with the orchestrator component 303 as needed. Processor 314 may be any suitable processor. Processor 314 may generate one or more instructions for controlling one or more processes of the orchestrator component 303, for example, for controlling one or more dependent controllers (e.g., qubit control electronics 308).

[0084] The orchestrator component 303 can acquire (e.g., download, receive, retrieve, and / or similar) quantum job requests 324 that request the execution of one or more quantum programs and / or physical qubit layouts. The quantum job requests 324 may be provided in any preferred format, such as text format, binary format, and / or another preferred format. In one or more embodiments, the quantum job requests 324 may be acquired by components other than those of the quantum system 301, for example, components of a classical system 102 / 202.

[0085] The orchestrator component 303 can determine the mapping of one or more quantum logic circuits for executing a quantum program based on the quantum job request 324. In one or more embodiments, the orchestrator component 303 and / or the quantum processor 306 can, for example, control the waveform generator 310 to generate one or more pulses, tones, waveforms, and / or similar to affect one or more qubits 307 in response to the quantum job request 324.

[0086] In one or more embodiments, more than one orchestrator component 303 may be included in the quantum system 301. One or more orchestrator components 303 may be used to control one or more qubit control electronic devices 308. This allows one or more qubit control electronic devices 308A, 308B and / or 308C to be communicatively coupled to one or more orchestrator components 303.

[0087] The qubit control electronic device 308 is used by the quantum processor 306 and may be located in a room temperature environment outside the cryogenic environment 317, as shown. In one or more embodiments, one or more aspects of one or more qubit control electronic devices may be located within the cryogenic environment 317.

[0088] In one or more embodiments, a qubit control electronic device 308 may be provided for each qubit 307. In one or more embodiments, the qubit control electronic device 308 may be provided to communicate with one or more qubits 307 for each qubit control electronic device 308.

[0089] In one or more embodiments, the qubit control electronic device 308 may be a qubit drive card (e.g., a waveform generator 310) and / or a qubit acquisition card (e.g., a readout electronic device 312), and / or may include both. In one or more embodiments, the qubit control electronic device 308 may be only one of the qubit drive card or the qubit acquisition card, and / or may include only one of them. In one or more embodiments, the qubit control electronic device 308 may include one or more qubit drive cards and / or one or more qubit acquisition cards.

[0090] The waveform generator 310 can generally cause at least one qubit 307 of the quantum processor 306 to perform one or more quantum processes, calculations, and / or measurements by creating a suitable electromagnetic signal. For example, the waveform generator 310 can operate one or more qubit effectors, such as qubit oscillators, harmonic oscillators, pulse generators, and / or similar, to generate one or more pulses, thereby stimulating and / or manipulating the state of one or more qubits 307 included in the quantum system 301. In fact, the waveform generator 310 can generate signals to affect one or more of the multiple qubits 307.

[0091] In one or more embodiments, the waveform generator 310 can control the application of such electromagnetic signals using various qubit-controlled electronic devices 308.

[0092] The quantum processor 306 may be housed in an cryogenic environment, such as one generated by a cryogenic environment 317, which can be realized by a dilution refrigerator. If one or more of the qubits 307 are superconducting qubits, these one or more physical qubits 307 can be made functional using extremely low temperatures, such as about 4K or lower.

[0093] The read electronic device 312 may include and / or be included in the acquisition card. The read electronic device 312 and / or the acquisition card may include an analog-to-digital converter (ADC) 315 which can be used in the read path of one or more qubits 307. The read electronic device 312 or at least a part thereof may be housed in a room temperature environment or a cryogenic environment 317 to read, for example, the excited, decayed, or other qubit state, frequency, and / or other characteristics. Accordingly, one or more elements of the read electronic device 312 may be constructed to operate at such cryogenic temperatures.

[0094] In one or more embodiments, more than one cryogenic environment, such as one or more dilution refrigerators, may be included in the quantum system 301.

[0095] Note that one or more aspects of the above description may refer to the operation of a single set of instructions executed on a single qubit controller or set of qubit-controlled electronic devices. However, scaling can be achieved. For example, instructions can be computed, transmitted, used, and / or otherwise used in relation to one or more parallel qubits (e.g., non-adjacent qubits), one or more parallel quantum circuits, and / or one or more parallel qubit mappings.

[0096] Now, returning to Figures 2 and 4, we discuss iterative step loops that can be used to generate multiple layers 286 of a hierarchical Clifford skeleton 282 while synthesizing Pauli rotations 252 and reducing the entanglement cost compared to the initial entanglement depth 254 (for example, thereby reducing the entanglement depth 284).

[0097] An exemplary process AA that may include the step is provided below, and / or the step may be included in one or more other logical processes, steps, methods, etc. These steps are further shown in Figures 4 and 6, and the resulting reduction of the Pauli rotation 252 is shown in Figure 5.

[0098] That is, by performing iterations of process AA, the Pauli rotations 252 of column 250 can be synthesized, for example, one by one, or at least partially. In one or more cases, the preservation of the rotation column 250 may be made possible by making the order of synthesis the order of column 250. That is, the hierarchical Clifford skeleton 282 can be built with layers 286 intended to be implemented in an order corresponding to the order of synthesis of the Pauli rotations 252. In general, to implement the order of synthesis based on the initial and / or underlying Steiner tree 290, the cost calculation component 220 can use one or more, for example, multiple, interaction-related cost functions that can be executed to implement the Pauli rotations 252 selected by the cost calculation component 220 based on the order of column 250. Thus, the output quantum circuit 288 can be functionally equivalent to the input column 250 after the synthesis of all the Pauli rotations 252 of column 250.

[0099] In one or more other cases, the cost calculation component 220 may be instructed, for example, by input to the quantum circuit synthesis system 202 by one or more management entities to generally relax a given ordering of the input sequence 250. For example, one or more rotations may be synthesized in a different synthesis order than the given ordering if it is known that changing the given ordering of the input sequence 250 does not affect the performance of the output circuit 288 based on the input sequence 250.

[0100] In other words, the ordering can be relaxed based on the determination that the order of the Pauli rotations 252 does not affect the final result of the final output quantum circuit 288. Allowing reordering can provide further flexibility to process AA and potentially generate lower-cost circuits.

[0101] An unspecified example of the use of sorting may be when some Pauli rotations 252 are commutative rather than anticommutative. Commutative Pauli rotations 252 can be sorted. Another unspecified example of the use of sorting may be when a hierarchical Clifford skeleton 282 contains a heuristic wave function. By instructing the cost calculation component 220 to sort, it may be possible for the cost calculation component 220 to select a less expensive Clifford skeleton and / or a selected Clifford circuit 298.

[0102] Now, considering the details of process AA, in which at least one step can be based on the order of synthesis, that step can be described as a series of logical steps as shown below.

[0103] Process AA: While the DAG is not empty: All cubits were originally unmarked. While available interactions exist (both qubits are unmarked): Regarding each remaining interaction: For each 1-CNOT Clifford circuit for the pair of qubits: Calculate the cost Choose the 1-CNOT Clifford circuit for the greatest cost reduction. Mark the two qubits in the interaction. Removes any Pauli rotations that have no subsequent rotations within the DAG and have been reduced.

[0104] As mentioned above, in relation to Figure 5, DAG270 functions as an input to process AA.

[0105] In the first iteration, the qubits of DAG270 may already be unmarked. That is, one or more data flags corresponding to the qubits of DAG270 may be down in the dataset (e.g., graph, list, matrix, etc.) corresponding to the hardware graph H (e.g., qubit mapping) in the target hardware where the implementation of input column 250 is desired.

[0106] Next, in addition to preparing DAG270 for the current iteration, Steiner tree 290 may also be prepared.

[0107] As used herein, Steiner tree 290 may refer to a computed subtree corresponding to the hardware graph H (e.g., qubit mapping) of the quantum system to which the input sequence 250 is being implemented. That is, given a multi-qubit Pauli rotation of axis P and the hardware graph H, a Steiner tree can be generated.

[0108] As shown in Figure 5, in the exemplary Steiner tree 520, each square unit 307X individually represents a qubit of the quantum system 301 based on its qubit mapping (e.g., hardware graph H). Note that the circular unit 307Y in the Steiner tree 290 represents a qubit that is not involved in rotation, as modeled by the Steiner tree 290, but is intermittently coupled to qubits that are involved in rotation (e.g., square units 307X). Lines 521 between units (e.g., circular and / or square) may represent communicative connections in the hardware graph H.

[0109] Accordingly, in step 404, the construction component 214 or the tree generation component 216 can determine the set of available (e.g., possible) interactions for implementing the set of Pauli rotations 252. For each Pauli rotation 252 represented in DAG 270, there may be one or more available interactions that can be performed with qubits in the quantum system 301, as represented by DAG 270. It is found that two or more interactions may overlap and / or cancel each other out, and / or there may be one or more interactions and / or interaction paths that can be used to implement any one Pauli rotation 252. These interactions may include gates, rotations, etc. Available interactions may refer to interactions between qubits a and b in the hardware targeted for implementation of column 250, where Pauli rotations 252 using these qubits a and b have a successor and / or have not yet been trivialized, as described above and below.

[0110] In step 406, for each available interaction, a Steiner tree 290 may be generated by the tree generation component 216 for each Pauli rotation 252. That is, the tree generation component 216 may generate a set of underlying Steiner trees 290 that represent all available interactions corresponding to all Pauli rotations 252. In one or more cases, this step may be performed at least partially in parallel with the generation of the DAG 270. As a result, the complete set of Steiner trees 290 may contain one or more Steiner trees 290 for each Pauli rotation of 252.

[0111] In step 408, based on the order of composition of the Pauli rotations 252, the cost calculation component 220 can identify a set of Steiner trees 290 corresponding to the available interactions for implementing the current Pauli rotation 252 being composed. Note that while individual Steiner trees 290 can be identified by the cost calculation component 220, one or more Steiner trees 290 can be processed by the cost calculation component 220 at least partially in parallel with each other.

[0112] Based on the identified Steiner trees 290, the cost calculation component 220 can generate each Steiner cost 292 in step 410. For each Steiner tree 290, one Steiner cost 292 may be generated.

[0113] As used herein, Steiner cost 292 may refer to the defined cost of a Steiner tree T given a Pauli operator P and a set of non-trivial qubits in a hardware graph H.

[0114] Each Steiner cost of 292 is given by Equation 1, i.e.,

number

[0115] Based on a set of Steiner costs 292 determined for a partial set, or more specifically, a complete set, of all remaining available (e.g., possible) interactions for a given pair of qubits corresponding to the currently synthesized Pauli rotations 252, the cost calculation component can apply the Steiner costs 292 to the hierarchical Clifford skeleton 282 using one or more cost estimation functions.

[0116] In one or more cases, the cost calculation component 220 is given by Equation 2:

number

[0117] In one or more other cases, the cost calculation component 220 is given by Equation 3:

number

[0118] In one or more other cases, the cost calculation component 220 can apply the Steiner cost 292 beyond the latest (e.g., the earliest) layer 286 of the layered Clifford skeleton 282 to, for example, one or more deeper rotations within the DAG 270. This lookahead approach can be used in a SWAP insertion algorithm to determine which of two actions (e.g., moves) have similar and / or identical costs.

[0119] In one or more other cases, it may be possible to remove the layer-by-layer constraints on the cost calculation component 220 and adopt a more general approach in which each entangled chunk of the Clifford circuit (e.g., in a layered Clifford skeleton 282) is scored by a combination of several different subscores, such as increasing depth or reducing Steiner cost.

[0120] For example, at the direction of the management entity, regardless of the formula or approach used by the cost calculation component 220, based on a set of Steiner costs 292 determined for a partial set, or more specifically, a complete set, of all remaining available (e.g., possible) interactions for a given pair of qubits corresponding to the current Pauli rotation 252 being synthesized, and / or the output of the corresponding cost estimation formula, the determination component 222 can determine a single Steiner cost 292 corresponding to a single rotation 252, each corresponding to one or more Clifford circuits to be injected into the layered Clifford skeleton 282 in order to reduce the entanglement depth of the implementation of the single rotation 252 relative to the hardware graph H.

[0121] As stated above, and again hereby for reference, as used herein, a selected Clifford circuit refers to a portion of an overall quantum circuit containing one or more CNOT gates (e.g., the basic Clifford skeleton 280 and / or the layered Clifford skeleton 282). In one or more cases, a selected Clifford circuit may also contain one or more further single-qubit Clifford gates. In one or more cases, a selected Clifford circuit may be called a selected CNOT Clifford circuit because it contains one or more CNOT gates. As used herein, minimum cost refers to the cost associated with the degree of entanglement depth and / or the amount of entanglement gates, but is not limited to the following.

[0122] In one or more cases, this decision by the decision component 222 may include determining a single lowest Steiner cost 292, and thus one or more Clifford circuits 298 that have the lowest cost compared to the other Steiner cost 292 / Clifford circuit 298 correspondences corresponding to one or more Clifford circuits 298, and injecting it into the hierarchical Clifford skeleton 282 (step 412).

[0123] Considering that in one or more iterations of process AA, none of the Pauli rotations 252 have been reduced below a threshold, it will be found that none of the Clifford circuits 298 can be injected into the hierarchical Clifford skeleton 282. For example, the triviality threshold used by the decision component 222 may require that the implementation of the Pauli rotation 252 be reduced to a single qubit quantum gate, e.g., a CNOT gate designated as the Clifford circuit 298 selected in that iteration and / or contained within the Clifford circuit 298, which is injected into the hierarchical Clifford skeleton 282.

[0124] Additionally and / or alternatively, it will be found that the Steiner cost 292 can result in various outcomes, such as reducing the cost of implementing the corresponding Pauli rotation 252, increasing the cost of implementing the corresponding Pauli rotation 252, or not changing the cost of implementing the corresponding Pauli rotation 252. This overall cost can be defined as the number of modified rotation and / or entangle gates used to implement the corresponding Pauli rotation 252, compared to the number of basic rotation and / or entangle gates that would have been used to implement the corresponding Pauli rotation 252.

[0125] Refer to the diagram 550 in Figure 5 to further define the decisions made by the decision component 222. As shown, based on a single initial Steiner tree 520, a reduction in rotation support 552 is shown. Through one or more iterations of process AA, the Steiner tree 520 is updated, which results in a reduction in entanglement depth and, consequently, a reduction in the number of qubits and / or rotations that should be used to finally implement the Pauli rotations referenced by the Steiner tree 520 552. As shown in Figure 5, the initial Steiner tree 520 may be reduced through at least six iterations of process AA.

[0126] That is, as shown, the initial Steiner tree 520 may be updated to the updated Steiner tree 294 (522, 524, 526, 528, 530, and 532), with each update resulting in the use of qubits and / or rotation reductions. A single update may be performed at each iteration of process AA, for example, near the end of that iteration.

[0127] In the final updated Steiner tree 532, a single qubit gate remains, which may be considered trivial enough to be injected into the hierarchical Clifford skeleton 282 based on the triviality threshold used by the decision component 222. That is, in an iteration of process AA, the single qubit CNOT quantum gate in the updated Steiner tree 532 may be designated as and / or included in the selected Clifford circuit 298 to be injected into the hierarchical Clifford skeleton 282.

[0128] In one or more other embodiments, different trivia thresholds can be used, for example, a pair of 1-qubit gates or fewer 1-qubit gates (e.g., corresponding to Steiner trees 530 or 532) can be used instead as the final composition of the Pauli rotation 252.

[0129] Now, considering alternative cost estimation, in one or more embodiments, the cost calculation component 220 can:

[0130] In step 414 of schematic diagram 400, if it is determined that the Steiner cost 292 (e.g., the lowest Steiner cost 292 determined by the decision component 222) satisfies the triviality threshold, then in step 414, the compile component 224 may inject one or more selected Clifford circuits 298 into the current (e.g., topmost) layer 286 of the layered Clifford skeleton 282, and / or generate a new layer 286 and inject the selected Clifford circuits 298 into this new layer 286. In particular, in the first iteration loop of process AA, the compile component 224 may inject the selected Clifford circuits 298 into the first layer 286, the base layer 286, and / or the layer 286 generated by the build component 214 in the base Clifford skeleton 280.

[0131] Next, to further explain the single iteration of process AA, we will discuss Figure 6.

[0132] In step 604 of schematic diagram 600, using the layered Clifford skeleton 282, the conjugate component 226 can direct the conjugation of an entire column 250 of Pauli rotations 252 through the gates of the latest (e.g., new or top-level) layer 286 of the layered Clifford skeleton 282. These gates through which the Pauli rotations 252 can be conjugated will include one or more CNOT gates contained in one or more selected Clifford circuits 298 that were most recently injected into the latest (e.g., new or top-level) layer 286 of the layered Clifford skeleton 282 in step 414.

[0133] Schematic Figure 600 shows the output of multiple iterations of process AA after the injection of the first selected Clifford circuit 298A, the second selected Clifford circuit 298A, and the Nth selected Clifford circuit 298N. After each injection, the corresponding conjugate step 604 of process AA is performed.

[0134] Based on the conjugation in a single iteration of process AA, the circuit generation component 228 may, in step 606, output the resulting layered Clifford skeleton 282. This output may include an intermediate output in which further Pauli rotations 252 remain unprocessed / uncombined. This output may include a final output quantum circuit 288 in which no Pauli rotations remain unprocessed / uncombined.

[0135] In step 610, if one or more Pauli rotations 252 remain unprocessed / unsynthesized, one or more components of the quantum circuit synthesis system 202 may perform one or more processes to complete the current iteration of process AA.

[0136] In step 610A, the quantum circuit synthesis system 202 (e.g., reduction component 230) may use DAG 270 to determine whether the remaining Pauli rotations 252 can be removed from DAG 270 (e.g., by reduction component 230), synthesize such Pauli rotations 252, and proceed to the next Pauli rotation 252 in the order of synthesis.

[0137] In other words, the reduction component 230 can determine whether or not there are trivial Pauli rotations in the DAG 270 that have no successors. As described herein and above, this may mean reducing the Pauli rotation 252 to a single qubit gate implementation in the quantum system 301 (the reduction of this rotation will be described later). Once the reduction of the Pauli rotation 252 is complete, the reduction component 230 can remove the Pauli rotation 252.

[0138] Alternatively, if the Pauli rotation 252 has a successor, it remains in the DAG 270 (e.g., maintained by the reduction component 230), and in another iteration of process AA, further reduction of entanglement is performed using the synthesis schematically shown in Figures 4 to 6.

[0139] In step 610B, the tree update component 218 can determine whether a change in the rotation sequence has occurred due to the injection of one or more Clifford circuits 298 into the hierarchical Clifford skeleton 282 and / or due to the conjugation of Pauli rotations 252 through the hierarchical Clifford skeleton 282.

[0140] In one or more cases, if it is determined that a change will result in a change to a Steiner tree 290, one or more Steiner trees 290 may be updated. For example, after each iteration of process AA by the tree update component 218, all Steiner trees 290 may be updated.

[0141] Alternatively, although it would be more costly (e.g., in terms of time, computing power, memory, and bandwidth), a complete set of Steiner trees 290 could be regenerated by the tree generation component 216. The decision of which path to take could be made by a management entity, for example, through communication with the quantum circuit synthesis system 202.

[0142] While updating the Steiner tree 290 can reduce the immediate cost, in one or more cases it may lead to a suboptimal overestimation of the cost of composing one or more rotations 252. For example, more CNOT gates may be injected into the hierarchical Clifford skeleton 282 than would have been if the Steiner tree 290 had been regenerated instead. This may be, but is not limited to, because updating the Steiner tree allows branches to loop back and come into contact with other branches in one or more cases.

[0143] In one or more cases, the same decision may be made after each iteration of process AA. In one or more other cases, different decisions may be made after different iterations of process AA. That is, as shown in Figure 6, after step 12, depending on the decision made regarding updating and / or reprocessing of the Steiner tree 290, step 612 may return to step 402 or step 404 for the next iteration of process AA.

[0144] In step 610C, after the first iteration and each subsequent iteration, the reduction component 230 may enable reprocessing of the DAG 270 for the next iteration of process AA by, for example, unmarking all qubits (e.g., nodes) in the qubit mapping.

[0145] In step 612, the iteration component 232 can determine whether all Pauli rotations 252 in column 250 have been combined. If no, the iteration component 232 can instruct one or more further iterations of process AA.

[0146] Alternatively, in step 607, if the iterative component 232 determines that there are no further Pauli rotations 252 to be synthesized in column 250, the output component 234 may output the final output quantum circuit 288 in step 606 based on the last conjugated and layered Clifford skeleton 282.

[0147] In one or more embodiments, in step 609, the output component 232 and / or processor 206 may, for example, communicate with the quantum processor 306 and / or orchestrator component 303 to instruct the execution of the output quantum circuit 288 in the quantum system 301. In one or more cases, this may involve the generation of a quantum job request 324 by the output component 234.

[0148] As an overview of the process described above, a flowchart is shown next with reference to Figures 8 and 9. The flowchart provides an exemplary, non-limited method 800 that can provide a quantum error correction process using a probabilistic propagation method with context-independent synthesis, according to one or more embodiments described herein, such as the non-limited system 200 in Figure 2. Although the non-limited method 800 is described in relation to the non-limited system 200 in Figure 2, the non-limited method 800 may also be applicable to other systems described herein, such as the non-limited system 100 in Figure 1. For simplicity, descriptions of similar elements and / or repetitions of processes used in each embodiment are omitted.

[0149] In 802, a method 800, which is not limited thereto, may include the step of identifying an input sequence (e.g., input sequence 250) of Pauli rotations (e.g., Pauli rotation 252), including an initial entanglement depth (e.g., initial entanglement depth 264), by a system operably coupled to a processor (e.g., an identification component 212 coupled to processor 206). In one or more embodiments, the sequence 250 of Pauli rotations 252 may be obtained from a quantum job request (e.g., quantum job request 324).

[0150] In 804, a method 800, which is not limited thereto, may include the step of obtaining a base Clifford skeleton (e.g., base Clifford skeleton 280) based on an input sequence of Pauli rotations by a system (e.g., an identification component 212).

[0151] In 806, the method 800, which is not limited thereto, may include a step in which a system (e.g., a construction component 214) generates a DAG based on the anticommutative relations of Pauli rotations of an input sequence of Pauli rotations, wherein the construction component uses one node of the DAG for each Pauli rotation, and generates an edge between a pair of nodes if the pair of Pauli rotations corresponding to the pair of nodes contain anticommutative rotation axes.

[0152] In 808, the method 800, which is not limited thereto, may include the step of generating edges by the system (e.g., a construction component 214) if and only if the direction of the edges follows an input sequence of Pauli rotations.

[0153] In 810, the lesser-defined method 800 may include a step in which a system (e.g., a tree generation component 216) generates a set of Steiner trees representing the Pauli rotations of an input sequence of Pauli rotations, using qubit mapping of the quantum system.

[0154] In 812, the method 800, which is not limited thereto, may include a step of updating a previously generated Steiner tree by a system (e.g., a tree update component 218) based on the conjugation of Pauli rotations in the most recently generated layer of a hierarchical Clifford skeleton.

[0155] In 814, a method 800, which is not limited thereto, may include the step of evaluating a cost function, including Steiner tree costs, by the system (e.g., cost calculation component 220) for a proposed qubit interaction, which involves implementing a CNOT Clifford circuit in the qubits of a quantum system, wherein the proposed qubit interaction is for manipulating Pauli rotations of an input sequence of Pauli rotations.

[0156] In 816, the method 800, which is not limited thereto, may include a step in which the system (e.g., the cost calculation component 220) separately evaluates all possible interactions between qubits of qubit mappings that could be used to implement each of the remaining Pauli rotations of the input sequence of Pauli rotations.

[0157] In 818, a method 800, which is not limited thereto, may include a step in which a system (e.g., a decision component 222) determines, based on a cost function that includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations, which includes a rotation smaller than one or more other Pauli rotations in the input sequence of Pauli rotations.

[0158] In 820, the method 800, which is not limited thereto, may include the step of having a system (e.g., a compile component 224) inject a selected CNOT Clifford circuit, which is one CNOT Clifford circuit or another CNOT Clifford circuit, into layers of the Clifford skeleton, thereby obtaining a layered Clifford skeleton.

[0159] In 822, a method 1000, which is not limited thereto, may include a step in which a system (e.g., a conjugate component 226) performs conjugation of Pauli rotations of a set of input sequences of Pauli rotations through a hierarchical Clifford skeleton.

[0160] In 824, the method 800, which is not limited thereto, may include the step of removing selected nodes of a DAG by the system (e.g., a reduction component 230) based on the reduction of the corresponding Pauli rotations caused by the conjugate of the input sequence of Pauli rotations, the corresponding Pauli rotations being those of the selected nodes.

[0161] In 826, the method 800, which is not limited thereto, may include the step of having the system (e.g., circuit generation component 228) generate a hierarchical Clifford skeleton with reduced entanglement depth based on the input sequence, using the output of a DAG based on the input sequence.

[0162] In 828, the non-limited method 800 may include a step in which the system (e.g., the circuit generation component 228) determines whether all Pauli (e.g., all Pauli rotations 252 in column 250) have been combined. If NO, the non-limited method 800 may proceed to the next step 830. If YES, the non-limited method 700 may bypass steps 828 and 830 and proceed to step 834.

[0163] In step 830, the non-limiting method 800 may include a step in which the system (e.g., iteration component 232) determines whether another iteration should be completed based on whether the Pauli rotations in the input sequence of Pauli rotations remain trivialized (e.g., reduced to smaller rotations, e.g., down to a single qubit quantum gate). Accordingly, if the decision in step 828 is YES, a decision will be made to proceed with another iteration.

[0164] In 832, the method 800, which is not limited thereto, may include a step in which the system (e.g., the iterative component 232) instructs to perform a further evaluation of the cost function based on the remaining Pauli rotations of the input sequence of Pauli rotations.

[0165] In 834, a method 800, which is not limited thereto, may include the step of generating an output quantum circuit by the system (e.g., output component 234) based on a hierarchical Clifford skeleton, on which the hierarchical Clifford skeleton includes a CNOT Clifford circuit based on the initial sequence of Pauli rotations, and by injecting the CNOT Clifford circuit into the Clifford skeleton, the hierarchical Clifford skeleton is obtained, thereby obtaining a reduced entanglement depth.

[0166] In 836, the method 800, which is not limited thereto, may include a step of directing the system (e.g., output component 234) to perform the execution of an output quantum circuit in the quantum system. [Further Overview]

[0167] For the sake of simplicity, the computer implementation and non-computer implementation methodologies provided herein are presented and / or described as a series of actions. It should be understood that the innovations of the subject matter are not limited by the order of the actions presented. For example, actions may occur in one or more sequences and / or simultaneously, along with other actions not presented and described herein. Furthermore, not all presented actions can be used to implement computer implementation and non-computer implementation methodologies in accordance with the described subject matter. In addition, computer implementation and non-computer implementation methodologies may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, the computer implementation methodologies described below and throughout this specification may be stored in a product for carrying and transferring the computer implementation methodologies to a computer. The term "product," as used herein, is intended to encompass computer programs accessible from any computer-readable device or storage medium.

[0168] This specification has described (and / or further described) systems and / or devices in terms of the interactions between one or more components. Such systems and / or components may include one or more of those components or subcomponents designated therein, designated components and / or subcomponents, and / or further components. Subcomponents may be implemented as components that are not included in a parent component but are communicatively coupled to other components. One or more components and / or subcomponents may be combined into a single component that provides aggregated functionality. For simplicity, components may interact with one or more other components that are not specifically described herein but are known to those skilled in the art.

[0169] In summary, one or more embodiments described herein can provide a system having memories 104, 204 for storing computer executable components, and processors 106, 206 for executing computer executable components stored in memories 104, 204, where the computer executable components include identification components 112, 212 for identifying input sequences 150, 250 including an initial entanglement depth 154, 254 of Pauli rotations 152, 252, and circuit generation components 128, 228 for generating a hierarchical Clifford skeleton 182, 282 having a reduced entanglement depth 184, 284 based on the input sequences 150, 250, using the outputs 172, 272 of directed acyclic graphs (DAGs) 170, 270 based on the input sequences 150, 250.

[0170] Considering one or more embodiments described herein, a practical application of one or more systems, computer implementations, and / or computer program products described herein may be a reduction in the time, energy, power, bandwidth, memory, qubit usage, and / or user entity effort used to synthesize and execute quantum circuits based on a sequence of Pauli rotations. That is, while it is not possible to synthesize large sequences of Pauli rotations (e.g., tens to hundreds or more) using existing frameworks, this is possible according to one or more embodiments described herein. Based on its output, an output quantum circuit with a reduced entanglement depth is provided, thereby enabling operation in a quantum system in less time and / or with less complexity than with existing frameworks, or enabling operation at all. That is, circuits with a greater entanglement depth may fail to operate in a quantum system and / or require undesirable time due to one or more hardware constraints of the quantum system, for example, and therefore, as the operation of increasingly larger sequences of Pauli rotations becomes desirable, the advantages of the reduced entanglement depth provided herein may increase.

[0171] In this regard, one or more embodiments described herein provide a useful and practical application of computers, thereby resulting in enhanced (e.g., improved and / or optimized) quantum circuit synthesis compared to existing frameworks for quantum circuit synthesis, particularly corresponding to the synthesis of a sequence of Pauli rotations into an operable quantum circuit. Overall, such computerized tools can constitute a concrete and tangible technological improvement in the field of quantum circuit synthesis. That is, one or more embodiments described herein provide identification and synthesis processes involving deformation, transformation, and / or conjugation of Pauli rotations, thereby obtaining an output quantum circuit with a reduced entanglement depth and, consequently, a reduced overall cost compared to the initial entanglement depth and / or overall cost corresponding to the sequence of Pauli rotations initially.

[0172] One or more embodiments described herein can be used scalably to perform, for example, two or more processes at least partially in parallel with one another. For example, one or more sequences of Pauli rotations can be combined simultaneously using one or more embodiments described herein. In one or more cases, one or more of the same and / or different processes can be performed simultaneously with one another, but are not limited to, updating Steiner trees, updating DAGs, estimating Steiner costs, injecting selected Clifford circuits into Clifford skeletons, and / or conjugating Pauli rotations. Furthermore, two or more of these processes described above can be operated at least partially with one another simultaneously.

[0173] This specification has described (and / or further described) systems and / or devices in terms of the interactions between one or more components. Such systems and / or components may include one or more of those components or subcomponents designated therein, designated components and / or subcomponents, and / or further components. Subcomponents may be implemented as components that are not included in a parent component but are communicatively coupled to other components. One or more components and / or subcomponents may be combined into a single component that provides aggregated functionality. For simplicity, components may interact with one or more other components that are not specifically described herein but are known to those skilled in the art.

[0174] One or more embodiments described herein may, in one or more embodiments, be essentially and / or closely tied to computer technology and cannot be implemented outside of a computing environment. For example, one or more processes performed by one or more embodiments described herein, for example, in relation to synthesizing a sequence of Pauli rotations into a quantum circuit using a hierarchical Clifford skeleton, can result in the execution of programs and / or program instructions in a more efficient, and even more feasible, manner than can be provided by existing systems and / or methods. The systems, computer implementations, and / or computer program products that result in the execution of these processes are extremely useful in the field of quantum circuit synthesis and cannot be implemented outside of a computing environment in a practically equivalent and executable manner.

[0175] One or more embodiments described herein may utilize hardware and / or software to solve problems that cannot be performed as a set of highly technical, non-abstract, human mental acts. For example, neither one person nor thousands of people can efficiently, accurately, and / or effectively automatically or even partially automatically generate decoder matrices, access information outputs from quantum systems related to check qubits and / or other measurement readouts, and / or manipulate decoder matrices (e.g., Tanner graphs) in the way that one or more embodiments described herein can provide these processes. Nor can human thought, nor a person with a pen and paper, perform these processes as performed by one or more embodiments described herein.

[0176] In one or more embodiments, one or more of the processes described herein may be performed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, specialized hybrid classical / quantum systems, and / or other types of specialized computers) to perform defined tasks relating to one or more of the technologies described above. One or more embodiments and / or components thereof described herein may be used to solve new problems arising through the development of the technologies mentioned above, quantum computing systems, cloud computing systems, computer architectures, and / or the use of other technologies.

[0177] One or more embodiments described herein may also be fully usable for performing one or more other functions (e.g., fully powered on, fully executed, and / or other functions) while performing one or more of the operations described herein.

[0178] To provide a further overview, a list of embodiments and their features is provided.

[0179] A system comprising: memory for storing computer executable components; and a processor for executing the computer executable components stored in the memory, wherein the computer executable components include an identification component for identifying an input sequence including an initial entanglement depth of Pauli rotations; and a circuit generation component for generating a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

[0180] The computer-executable component further includes a cost calculation component that evaluates a cost function including Steiner tree costs for a proposed qubit interaction, which involves implementing a CNOT Clifford circuit in the qubit of a quantum system, wherein the proposed qubit interaction is for manipulating the Pauli rotation of the input sequence of the Pauli rotations, as described in the preceding paragraph.

[0181] The computer-executable component further includes a tree update component that updates a previously generated Steiner tree based on the conjugation of Pauli rotations in the most recently generated layer of the hierarchical Clifford skeleton, according to any of the preceding paragraphs.

[0182] The computer-executable component further includes a construction component that generates the DAG based on the anticommutative relationship of the Pauli rotations of the input sequence of Pauli rotations, the construction component using one node of the DAG for each Pauli rotation, and generating an edge between the pair of nodes if the pair of Pauli rotations corresponding to the pair of nodes include anticommutative rotation axes.

[0183] The system of any of the preceding paragraphs, further comprising a computer-executable component that determines the lowest cost CNOT Clifford circuit implementable for a selected pair of qubits of the quantum system based on the cost function, which includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations that includes rotations smaller than one or more other Pauli rotations in the input sequence of Pauli rotations.

[0184] The computer executable component further includes a compilation component that injects a selected CNOT Clifford circuit, which is the CNOT Clifford circuit or another CNOT Clifford circuit, into layers of the Clifford skeleton, thereby obtaining the layered Clifford skeleton, according to any of the preceding paragraphs.

[0185] The system of any of the preceding paragraphs, wherein the computer executable component further includes a conjugation component that performs conjugation of the Pauli rotations of a set of input sequences of the Pauli rotations through the hierarchical Clifford skeleton.

[0186] The computer-executable component further includes a reduction component that removes selected nodes of the DAG based on the reduction of the corresponding Pauli rotations caused by the conjugate of the input sequence of Pauli rotations, the corresponding Pauli rotations being the system of any of the preceding paragraphs.

[0187] The system of any of the preceding paragraphs further includes an iterative component that instructs the computer-executable component to perform a further evaluation of the cost function based on the remaining Pauli rotations of the input sequence of Pauli rotations.

[0188] The computer-executable component further includes an output component that uses a qubit mapping of a given quantum system to generate an output quantum circuit corresponding to a modified set of Pauli rotations compared to the sequence of Pauli rotations, obtained by conjugating the sequence of Pauli rotations through the layered Clifford skeleton, based on the layered Clifford skeleton, wherein the layered Clifford skeleton includes a CNOT Clifford circuit based on the sequence of Pauli rotations, and the layered Clifford skeleton is obtained by injecting the CNOT Clifford circuit into the Clifford skeleton, thereby obtaining the reduced entanglement depth, the system of any of the preceding paragraphs.

[0189] A computer implementation method comprising: a step of identifying an input sequence of Pauli rotations, including an initial entanglement depth, using a system operablely coupled to a processor; and a step of generating a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence using the output of a directed acyclic graph (DAG) based on the input sequence.

[0190] A computer implementation method according to the preceding paragraph, further comprising the steps of evaluating a cost function including Steiner tree costs by the system for a proposed qubit interaction, which includes implementing a CNOT Clifford circuit in the qubit of a quantum system, wherein the proposed qubit interaction is for manipulating the Pauli rotation of the input sequence of Pauli rotations.

[0191] A computer implementation method according to any of the preceding paragraphs, further comprising: a step of generating the DAG based on the anticommutative relationship of the Pauli rotations of the input sequence of Pauli rotations using the system; a step of using one node of the DAG for each Pauli rotation using the system; and a step of generating an edge between the pair of nodes if the pair of Pauli rotations corresponding to the pair of nodes include an anticommutative axis of rotation using the system.

[0192] The computer implementation method according to any of the preceding paragraphs, further comprising the step of determining by the system a lowest-cost CNOT Clifford circuit implementable for a selected pair of qubits of the quantum system, based on the cost function which includes a modified Steiner cost and is configured to determine the lowest-cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations, which includes a rotation smaller than one or more other Pauli rotations in the input sequence of Pauli rotations.

[0193] A computer implementation method according to any of the preceding paragraphs, further comprising: the step of injecting a selected CNOT Clifford circuit, which is the CNOT Clifford circuit or another CNOT Clifford circuit, into layers of a Clifford skeleton by the system to obtain the layered Clifford skeleton; and the step of performing conjugates of Pauli rotations of a set of input sequences of Pauli rotations through the layered Clifford skeleton by the system.

[0194] A computer program product for facilitating the quantum circuit compilation process, the computer program product comprising a computer-readable storage medium in which program instructions are embodied, the program instructions being executable by a processor, the computer program product causing the processor to identify an input sequence including the initial entanglement depth of Pauli rotations; and the computer program product causing the processor to generate a hierarchical Clifford skeleton having a reduced entanglement depth based on the input sequence, using the output of a directed acyclic graph (DAG) based on the input sequence.

[0195] The computer program product described in the preceding paragraph, wherein the program instructions are further executable by the processor, causing the processor to evaluate a cost function including Steiner tree costs for a proposed qubit interaction, which includes implementing a CNOT Clifford circuit in the qubits of a quantum system, the proposed qubit interaction being for manipulating the Pauli rotation of the input sequence of Pauli rotations.

[0196] The computer program product described in any of the preceding paragraphs, wherein the program instructions are further executable by the processor, causing the processor to generate the DAG based on the anticommutative relationship of the Pauli rotations of the input sequence of Pauli rotations; to use one node of the DAG for each Pauli rotation; and to generate an edge between the pair of nodes if the pair of Pauli rotations corresponding to the pair of nodes include an anticommutative axis of rotation.

[0197] The computer program product described in any of the preceding paragraphs, wherein the program instructions are further executable by the processor and cause the processor to determine the lowest cost CNOT Clifford circuit implementable for a selected pair of qubits of the quantum system, based on the cost function which includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations that includes a rotation smaller than one or more other Pauli rotations in the input sequence of Pauli rotations.

[0198] The computer program product according to any of the preceding paragraphs, wherein the program instructions are further executable by the processor, causing the processor to inject selected CNOT Clifford circuits, which are the CNOT Clifford circuits or another CNOT Clifford circuit, into layers of the Clifford skeleton, thereby obtaining the layered Clifford skeleton; and causing the processor to perform conjugates of the Pauli rotations of a set of input sequences of the Pauli rotations through the layered Clifford skeleton. [Description of the computing environment]

[0199] Next, regarding Figure 10, Figures 1-9 provide a further contextual and detailed explanation of one or more embodiments described herein.

[0200] Figure 10 and the following discussion are intended to provide a brief and general description of a preferred computing environment 1000 in which one or more embodiments described herein may be implemented in Figures 1-9. For example, various aspects of this disclosure are illustrated by explanatory text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of computer program products (CPPs). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again, depending on the technology involved, two operations shown in consecutive blocks of a flowchart may be performed in reverse order, as a single integrated step, simultaneously, or at least partially in overlapping time.

[0201] Embodiments of a computer program product ("CPP Embodiment" or "CPP") are terms used in this disclosure to describe any set of one or more storage media ("mediums") that are collectively comprised of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. "Storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may, but are not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any preferred combination thereof. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as pits / lands formed on the main surface of a punch card or disk), or any preferred combination of the above. When the term "computer-readable storage medium" is used in this disclosure, it shall not be interpreted as storage in the form of a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, electrical signals communicated through wires, and / or other transmission media.As those skilled in the art will understand, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection; however, data is not transient while it is stored, and therefore the storage device is not transient.

[0202] The computing environment 1000 includes an example of an environment for executing at least a portion of the computer code involved in carrying out the method of the present invention, for example, for transforming the original source code based on the configuration of the quantum circuit synthesis code 1080. In addition to block 1080, the computing environment 1000 includes, for example, a computer 1001, a wide area network (WAN) 1002, an end user device (EUD) 1003, a remote server 1004, a public cloud 1005, and a private cloud 1006. In this embodiment, the computer 1001 includes a processor set 1010 (including a processing circuit configuration 1020 and a cache 1021), a communication fabric 1011, volatile memory 1012, persistent storage 1013 (including an operating system 1022 and blocks 1080 as identified above), a peripheral device set 1014 (including a user interface (UI) device set 1023, storage 1024, and an Internet of Things (IoT) sensor set 1025), and a network module 1015. The remote server 1004 includes a remote database 1030. The public cloud 1005 includes a gateway 1040, a cloud orchestration module 1041, a host physical machine set 1042, a virtual machine set 1043, and a container set 1044.

[0203] Computer 1001 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum system, or any other form of computer or mobile device currently known or to be developed in the future that is capable of executing programs, accessing networks, or querying databases such as remote database 1030. As is well understood in the field of computer technology, and depending on the technology, the execution of a computer implementation method may be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of the computing environment 1000, in order to keep the presentation as simple as possible, the detailed discussion focuses on a single computer, specifically computer 1001. Computer 1001 may be located in the cloud, although it is not shown in the cloud in Figure 10. On the other hand, computer 1001 is not required to be in the cloud, except to any extent that may be definitively shown.

[0204] The processor set 1010 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuit configuration 1020 may be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. The processing circuit configuration 1020 may implement multiple processor threads and / or multiple processor cores. The cache 1021 is memory located within the processor chip package and is typically used for data or code that should be quickly accessible from threads or cores running on the processor set 1010. The cache memory is typically organized into multiple levels depending on its relative proximity to the processing circuit configuration. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 1010 may be designed for qubit processing and the execution of quantum computing.

[0205] Computer-readable program instructions are typically loaded onto computer 1001, causing the processor set 1010 of computer 1001 to execute a series of operational steps, thereby realizing a computer implementation method. As a result, the instructions thus executed instantiate the methods specified in the flowcharts and / or descriptions of the computer implementation methods contained herein (collectively referred to as the "Methods of the Invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 1021 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 1010 to control and direct the execution of the Methods of the Invention. In computing environment 1000, one or more instructions for executing the Methods of the Invention may be stored in block 1080 in persistent storage 1013.

[0206] The communication fabric 1011 is a signal conduction path that enables various components of the computer 1001 to communicate with one another. Typically, this fabric is made up of switches and conductive paths, such as buses, bridges, physical input / output ports, and similar components. Other types of signal communication paths, such as optical fiber communication paths and / or wireless communication paths, may be used.

[0207] The volatile memory 1012 is any type of volatile memory currently known or to be developed in the future. Examples include dynamic random-access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, but this is not required unless explicitly stated. In computer 1001, the volatile memory 1012 is located in a single package and resides inside computer 1001, but alternatively or additionally, the volatile memory may be distributed across multiple packages and / or located externally to computer 1001.

[0208] The persistent storage 1013 is any form of non-volatile storage for a computer, currently known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether the computer 1001 and / or the persistent storage 1013 are directly powered. The persistent storage 1013 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 1022 can take several forms, such as various known proprietary operating systems using a kernel or open-source portable operating system interface type operating systems. The code contained in block 1080 typically includes at least a portion of computer code involved in performing the method of the present invention.

[0209] The peripheral device set 1014 includes a set of peripheral devices for the computer 1001. Data communication connections between the peripheral devices and other components of the computer 1001 may be implemented in various ways, such as Bluetooth, near-field communication (NFC), cable (e.g., Universal Serial Bus (USB) type cable), insertable connection (e.g., Secure Digital (SD) card), connection via a local area communication network, or connection via a wide area network such as the Internet. In various embodiments, the UI device set 1023 may include components such as a display screen, speaker, microphone, wearable devices (e.g., goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic device. Storage 1024 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 1024 may be persistent and / or volatile. In some embodiments, storage 1024 may take the form of a quantum computing memory device for storing data in the form of qubits. In embodiments where computer 1001 needs to have a large amount of storage (for example, if computer 1001 locally stores and manages a large database), this storage may be provided by peripheral storage devices designed to store large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 1025 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0210] The network module 1015 is a collection of computer software, hardware, and firmware that enables computer 1001 to communicate with other computers via the WAN 1002. The network module 1015 may include hardware such as a modem or Wi-Fi® signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of the network module 1015 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 1015 are performed on physically separate devices, thereby allowing the control function to manage multiple different network hardware devices. Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 1001 via a network adapter card or network interface included in the network module 1015.

[0211] WAN1002 is any wide area network (e.g., the Internet) that can transmit computer data over non-local distances using any currently known or future-developed technology for transmitting computer data. In some embodiments, the WAN may be replaced and / or complemented by a local area network (LAN), such as a Wi-Fi® network, designed to transmit data between devices located in a local area. The WAN and / or LAN typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0212] An end-user device (EUD) 1003 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 1001) and can take any of the forms discussed above in relation to computer 1001. EUD 1003 typically receives useful and beneficial data from the operation of computer 1001. For example, in a hypothetical scenario where computer 1001 is designed to provide recommendations to an end-user, these recommendations would typically be communicated from computer 1001's network module 1015 to EUD 1003 via WAN 1002. In this way, EUD 1003 can display or otherwise present the recommendations to the end-user. In some embodiments, EUD 1003 may be a client device such as a thin client, heavy client, mainframe computer, or desktop computer.

[0213] The remote server 1004 is any computer system that provides at least some data and / or functionality to computer 1001. The remote server 1004 may be controlled and used by the same entity that operates computer 1001. The remote server 1004 represents a machine that collects and stores data that is useful and beneficial for use by other computers, such as computer 1001. For example, in a hypothetical case where computer 1001 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 1001 from the remote database 1030 of the remote server 1004.

[0214] Public Cloud 1005 is any computer system available for use by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct active management by scale. Direct active management of Public Cloud 1005's computing resources is performed by the computer hardware and / or software of Cloud Orchestration Module 1041. The computing resources provided by Public Cloud 1005 are typically implemented by virtual computing environments running on various computers that make up the host physical machine set 1042, which is the universe of physical computers available in and / or to Public Cloud 1005. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 1043 and / or containers from container set 1044. These VCEs may be stored as images and may be transferred either as images or after instantiation of VCEs, among and between various physical machine hosts. The cloud orchestration module 1041 manages the transfer and storage of images, deploys new instances of VCE, and manages active instances of VCE deployments. The gateway 1040 is a collection of computer software, hardware, and firmware that enables the public cloud 1005 to communicate over the WAN 1002.

[0215] Here, some further explanation of virtualized computing environments (VCEs) is provided. A VCE can be stored as an "image." From this image, a new active instance of the VCE can be instantiated. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature in which the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave like actual computers in terms of the programs running within them. Computer programs running on a normal operating system can utilize all of that computer's resources, including connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container, which is a known feature of containerization.

[0216] Private Cloud 1006 is similar to Public Cloud 1005, except that its computing resources are available only for use by a single enterprise. Although Private Cloud 1006 is shown as communicating with WAN 1002, in other embodiments, the private cloud may be completely isolated from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate discrete entity, but the larger hybrid cloud architecture is coupled by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple configuration clouds. In this embodiment, both Public Cloud 1005 and Private Cloud 1006 are part of a larger hybrid cloud. [Further information to conclude]

[0217] The embodiments described herein may cover one or more systems, methods, apparatus, and / or computer program products at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium (or more media) having computer-readable program instructions for causing a processor to execute aspects of one or more embodiments described herein. The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a superconducting storage device, and / or any preferred combination thereof. A non-exclusive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved structures on which instructions are recorded, and / or any suitable combination of the above. Computer-readable storage media, when used herein, shall not be construed as transient signals themselves, such as radio waves and / or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides and / or other transmission media (e.g., optical pulses passing through fiber optic cables), and / or electrical signals transmitted through wires.

[0218] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device and / or to an external computer or external storage device via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device. Computer-readable program instructions for performing the operation of one or more embodiments described herein may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuit configurations, and / or source code and / or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, or similar, and / or procedural programming languages ​​such as the "C" programming language and / or similar programming languages. Computer-readable program instructions may be executed as a whole on a computer, partially on a computer, as a standalone software package, partially on a computer and / or partially on a remote computer, or entirely on a remote computer and / or server.In the latter scenario, the remote computer may be connected to the computer through any type of network, including a local area network (LAN) and / or a wide area network (WAN), and / or may be connected to an external computer (for example, via the Internet using an Internet service provider). In one or more embodiments, an electronic circuit configuration, for example, including a programmable logic circuit configuration, a field-programmable gate array (FPGA), and / or a programmable logic array (PLA), may execute computer-readable program instructions by personalizing the electronic circuit configuration using state information of computer-readable program instructions in order to perform an aspect of one or more embodiments described herein.

[0219] Aspects of one or more embodiments described herein will be described with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to one or more embodiments described herein. It will be understood that each block in a flowchart and / or block diagram, and combinations of blocks in a flowchart and / or block diagram, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to the processors of general-purpose computers, dedicated computers, and / or other programmable data processing devices for generating machines. As a result, instructions executed via the processor of a computer or other programmable data processing device may create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in computer-readable storage media that can instruct computers, programmable data processing devices, and / or other devices to function in a particular manner, thereby the computer-readable storage media in which the instructions are stored may have a product containing instructions that can implement the functions / actions specified in one or more blocks of a flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing devices, and / or other devices to perform a series of actions on the computer, other programmable devices, and / or other devices to generate a computer implementation process, thereby enabling the instructions executed on the computer, other programmable devices, and / or other devices to implement the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0220] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and / or operation of possible implementations of systems, computer-implementable methods, and / or computer program products according to one or more embodiments described herein. In this regard, each block in the flowchart or block diagram may represent a module, segment, and / or portion of instructions containing one or more executable instructions for implementing a specified logical function. In one or more alternative implementations, the functions described in a block may occur in an order different from that shown in the figure. For example, two consecutively shown blocks may be executed substantially simultaneously, depending on the functionality involved, and / or blocks may, in some cases, be executed in reverse order. It should also be noted that each block in the block diagram and / or flowchart, and / or combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system capable of performing a specified function and / or action, and / or one or more combinations of dedicated hardware and / or computer instructions.

[0221] While the subject matter has been described above in the general context of computer executable instructions for computer program products running on a computer and / or multiple computers, those skilled in the art will recognize that one or more embodiments described herein may be implemented in parallel with at least partially one or more other program modules. Generally, a program module includes routines, programs, components, and / or data structures that perform a particular task and / or implement a particular abstract data type. Furthermore, the computer implementation methods described above may be practiced in single-processor and / or multi-processor computer systems, minicomputing devices, mainframe computers, and other computer system configurations including computers, handheld computing devices (e.g., PDAs®, telephones), and / or microprocessor-based or programmable consumer electronics and / or industrial electronics. The embodiments shown may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked over a communication network. However, one or more, but not all, embodiments of one or more embodiments described herein may be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0222] As used herein, the terms “component,” “system,” “platform,” and / or “interface” may refer to and / or include computer-related entities or entities relating to operating machines having one or more specific functionalities. Entities described herein may be hardware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. Exemplarily, an application running on a server and both the application and the server may be components. One or more components may reside within a process and / or thread of execution, and components may be localized on one computer and / or distributed across two or more computers. In another example, each component may be executed from various computer-readable media storing various data structures. Components may communicate via local and / or remote processes according to signals, etc., having one or more data packets (e.g., data from one component interacting with another component in a network such as the Internet with a local system, a distributed system, and / or other systems via signals). As another example, a component may be a device having a specific functionality, provided by mechanical parts operating through an electrical or electronic circuit configuration that operates through software and / or firmware applications executed by a processor. In such a case, the processor may reside inside and / or outside the device and may execute at least part of the software and / or firmware application.As yet another example, a component may be a device that provides certain functionality through an electronic component without involving mechanical parts, and such electronic component may include a processor and / or other means for running software and / or firmware that at least partially provides the functionality of the electronic component. In one embodiment, the component may emulate the electronic component via, for example, a virtual machine in a cloud computing system.

[0223] In addition, the term “or” is intended to mean an inclusive “or,” not an exclusive “or.” That is, unless otherwise specified or it is clear from the context, “X uses A or B” is intended to mean either of the natural inclusive substitutions. That is, if X uses A; if X uses B; or if X uses both A and B, “X uses A or B” is satisfied in any of the examples above. Also, the articles “a” and “an” used herein and in the accompanying drawings should generally be interpreted as meaning “one or plural,” unless otherwise specified or it is clear from the context that they refer to a singular noun. When used herein, the terms “example” and / or “exemplary” are used to mean that they serve as examples, examples, or illustrations. To avoid misunderstanding, the subject matter described herein is not limited to such examples. In addition, any embodiment or design described herein as “example” and / or “exemplary” is not necessarily construed as being preferable or advantageous to other embodiments or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0224] As used herein, the term “processor” may refer to substantially any computing processing unit and / or device, including, but not limited to, a single-core processor; a single processor with software multithreading capability; a multi-core processor; a multi-core processor with software multithreading capability; a multi-core processor with hardware multithreading technology; a parallel platform; and / or a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex-programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, and / or any combination thereof designed to perform the functions described herein. Furthermore, a processor may leverage nanoscale architectures such as molecular and quantum dot-based transistors, switches, and / or gates, but not limited to, to optimize space use and / or enhance the performance of associated equipment. A processor may be implemented as a combination of computing processing units.

[0225] In this specification, terms such as “memory,” “storage,” “data memory,” “data storage,” “database,” and substantially any other information storage component relating to the operation and functionality of a component are used to refer to “memory” or the “memory component” entity embodied in a component containing memory. The memory and / or memory components described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may include, but not limit, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, and / or non-volatile random-access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can function as external cache memory. As examples, not limitations, RAM may be available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and / or Rambus dynamic RAM (RDRAM). Additionally, the memory components described herein for systems and / or computer implementations are intended to include, but are not limited to, these and / or any other suitable types of memory.

[0226] The foregoing only includes examples of systems and computer implementations. Naturally, for the purpose of describing one or more embodiments, it is impossible to describe every conceivable combination of components and / or computer implementations; however, those skilled in the art will recognize that many further combinations and / or substitutions of one or more embodiments are possible. Furthermore, wherever terms such as “includes,” “has,” and “possesses” are used in the detailed description, claims, appendices, and / or drawings, such terms are intended to be inclusive in the same manner as the term “equips” is interpreted when used as a transitional clause in a claim.

[0227] While descriptions of various embodiments have been presented for illustrative purposes, they are not intended to be exhaustive or to limit the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best illustrate the principles, practical applications, and / or technical improvements to the technologies available on the market of the embodiments, and / or to enable other those skilled in the art to understand the embodiments described herein.

Claims

1. Memory for storing computer executable components; and A processor that executes the computer executable component stored in the memory, wherein the computer executable component is An identification component that identifies the input column including the initial entanglement depth for Pauli rotation; and A circuit generation component that uses the output of a directed acyclic graph (DAG) based on the input sequence to generate a hierarchical Clifford skeleton with reduced entanglement depth based on the input sequence. including, A system equipped with these features.

2. The aforementioned computer executable component further: A proposed qubit interaction, which includes implementing a CNOT Clifford circuit in the qubit of a quantum system, is provided with a cost calculation component that evaluates a cost function including Steiner tree costs, the proposed qubit interaction is for manipulating a certain Pauli rotation of the input sequence of Pauli rotations, The system according to claim 1, including the following:

3. The aforementioned computer executable component further: A tree update component that updates a previously generated Steiner tree based on the conjugation of Pauli rotations in the most recently generated layer of the aforementioned hierarchical Clifford skeleton. The system according to claim 1, including the following:

4. The aforementioned computer executable component further: A construction component that generates the DAG based on the anticommutative relationship of the Pauli rotations in the input sequence of the Pauli rotations. Includes, With the aforementioned construction component, one node of the DAG is used for each Pauli rotation. When a pair of Pauli rotations corresponding to a pair of nodes include anticommutative rotation axes, the construction component generates an edge between the pair of nodes. The system according to claim 1.

5. The aforementioned computer executable component further: A decision component determined based on the cost function, which includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations that includes rotations smaller than one or more other Pauli rotations in the input sequence of Pauli rotations. The system according to claim 2, including the above.

6. The aforementioned computer executable component further: A compilation component that injects a selected CNOT Clifford circuit, which is either the aforementioned CNOT Clifford circuit or another CNOT Clifford circuit, into the layers of the Clifford skeleton, thereby obtaining the layered Clifford skeleton. The system according to claim 2, including the above.

7. The aforementioned computer executable component further: A conjugate component that performs conjugation of the Pauli rotations of a set of input sequences of the Pauli rotations through the aforementioned hierarchical Clifford skeleton. The system according to claim 6, including the system described in claim 6.

8. The aforementioned computer executable component further: A reduction component that removes selected nodes of the DAG based on the reduction of the corresponding Pauli rotation caused by the conjugate of the input sequence of Pauli rotations, the corresponding Pauli rotations corresponding to the selected nodes, The system according to claim 7, including the system described in claim 7.

9. The aforementioned computer executable component further: An iterative component that instructs the execution of a further evaluation of the cost function based on the remaining Pauli rotations of the input sequence of the aforementioned Pauli rotations. The system according to claim 8, including the above.

10. The aforementioned computer executable component further: An output component that uses a qubit mapping of a specified quantum system to generate an output quantum circuit corresponding to a set of modified Pauli rotations compared to the initial sequence of Pauli rotations, obtained by the conjugate of the initial sequence of Pauli rotations through the hierarchical Clifford skeleton, based on the hierarchical Clifford skeleton. Includes, The hierarchical Clifford skeleton includes a CNOT Clifford circuit based on the sequence of the initial Pauli rotations, By injecting the CNOT Clifford circuit into the Clifford skeleton, the layered Clifford skeleton is obtained, thereby achieving the reduced entanglement depth. The system according to any one of claims 1 to 9.

11. A system operablely coupled to the processor identifies an input sequence of Pauli rotations, including the initial entanglement depth; and The step of generating a hierarchical Clifford skeleton with reduced entanglement depth by the system using the output of a directed acyclic graph (DAG) based on the input sequence. A computer implementation method comprising the following:

12. Regarding a proposed qubit interaction, which involves implementing a CNOT Clifford circuit in the qubit of a quantum system, the system evaluates a cost function including Steiner tree costs, wherein the proposed qubit interaction is for manipulating the Pauli rotation of the input sequence of Pauli rotations. The computer implementation method according to claim 11, further comprising the above.

13. The system generates the DAG based on the anticommutative relationship of the Pauli rotations in the input sequence of Pauli rotations; The system involves the step of using one node of the DAG for each Pauli rotation; and The system generates an edge between a pair of nodes when a pair of Pauli rotations corresponding to a pair of nodes include anticommutative rotation axes. The computer implementation method according to claim 11 or 12, further comprising the above.

14. The step of determining the lowest cost CNOT Clifford circuit implementable for a selected pair of qubits of the quantum system, based on the cost function which includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations that includes a rotation smaller than one or more other Pauli rotations in the input sequence of Pauli rotations. The computer implementation method according to claim 12, further comprising the above.

15. The system involves injecting a selected CNOT Clifford circuit, which is the CNOT Clifford circuit or another CNOT Clifford circuit, into the layers of the Clifford skeleton, thereby obtaining the layered Clifford skeleton; and The system performs the conjugation of the Pauli rotations of a group of input sequences of the Pauli rotations through the hierarchical Clifford skeleton. The computer implementation method according to claim 12, further comprising the above.

16. In the processor, A procedure for identifying an input sequence including the initial entanglement depth of a Pauli rotation; and Using the output of a directed acyclic graph (DAG) based on the aforementioned input sequence, a procedure is performed to generate a hierarchical Clifford skeleton with reduced entanglement depth based on the aforementioned input sequence. A computer program that simplifies the quantum circuit compilation process.

17. The aforementioned processor, Regarding the proposed qubit interaction, which involves implementing a CNOT Clifford circuit in the qubit of a quantum system, a procedure is further performed to evaluate the cost function, including the Steiner tree cost, and the proposed qubit interaction is for manipulating the Pauli rotation of the input sequence of the Pauli rotation. The computer program according to claim 16.

18. The aforementioned processor, A procedure for generating the DAG based on the anticommutative relationship of the Pauli rotations in the input sequence of the Pauli rotations; A procedure using one node of the DAG for each Pauli rotation; and To further perform the procedure for generating an edge between a pair of nodes when a pair of Pauli rotations corresponding to a pair of nodes include anticommutative rotation axes, The computer program according to claim 16 or 17.

19. The aforementioned processor, A procedure for determining the lowest cost CNOT Clifford circuit implementable for a selected pair of qubits of the quantum system, which includes a modified Steiner cost and is configured to determine the lowest cost CNOT Clifford circuit for the first Pauli rotation in the input sequence of Pauli rotations that includes rotations smaller than one or more other Pauli rotations in the input sequence of Pauli rotations, The computer program according to claim 17.

20. The aforementioned processor, A procedure for injecting a selected CNOT Clifford circuit, which is the aforementioned CNOT Clifford circuit or another CNOT Clifford circuit, into layers of a Clifford skeleton, thereby obtaining the layered Clifford skeleton; and To perform a procedure for performing the conjugate of the Pauli rotations of a group of input sequences of the Pauli rotations through the aforementioned hierarchical Clifford skeleton, The computer program according to claim 17.

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