Time tagging measurement device

Abstract

This provides an FPGA including a TDC (Time-to-Digital Converter) that provides a function to time-tag the occurrence time of a single signal representing a single event, a clock generation unit, a tag counter, and a processing unit. [Solution] In FPGA1, an arbitrary TDC includes an input signal generation unit that generates an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the TDC, and a delay line unit to which the generated input pulse is input. After the rising edge of the start signal input to the TDC occurs, the processing unit calculates a first value by multiplying the tag count value observed at the time of the first newly generated clock pulse by the clock pulse period, and subtracts the thermometer code or the converted code obtained by converting the thermometer code output by the delay line unit at the rising edge of the clock pulse from the first value to calculate the time of generation of the first start signal.

Description

Technical Field

[0001] The present invention relates to TDC technology, and particularly to TDC technology capable of tagging the generation time of a pulse signal.

Background Art

[0002] TDC (Time-to-Digital Converter) plays an important role in many scientific and industrial application fields where precise timing measurement is required. It is widely used in application fields that require high-precision timing measurement, such as time-of-arrival (TOF) measurement in particle physics, medical imaging, radar systems, and laser distance measurement. A TDC can convert the time interval between two events into a digital output. A TDC designed to measure the time difference between two events generally uses a counter to count the number of clock cycles between the two events. Then, the count number is converted into a digital output indicating the time interval. There are various types of TDCs, such as leading-edge TDC, trailing-edge TDC, and interpolation TDC. The leading-edge TDC measures the time between the leading edge of the start signal and the leading edge of the stop signal, and the trailing-edge TDC measures the time between the trailing edge of the start signal and the trailing edge of the stop signal. The interpolation TDC uses interpolation technology to estimate the time interval between two clock cycles and increases the resolution of the TDC.

[0003] To provide the above-described functions, as a prerequisite for determining the measured value, depending on the application using the TDC, instead of the interval between two pulses generated in one existing channel, one or two or more independent signals need to be time-tagged based on a specific time. For this purpose, it is necessary to provide a technology for inputting only one signal indicating one event into the TDC for each channel and tagging and storing the generation time of the input signal digitally.

Summary of the Invention

[0004] The present invention aims to provide a TDC (Time Tag Controller) that provides a function for time-tagging the occurrence time of a single signal representing a single event. [Means for solving the problem]

[0005] TDC can be implemented using ASICs (Application-Specific Integrated Circuits), MCUs (Microcontrollers), PSoCs (Programmable System-on-Chip), DSPs (Digital Signal Processors), FPAAs (Field Programmable Analog Arrays), TACs (Time-to-Amplitude Converters), TFCs (Time-to-Frequency Converters), and FPGAs (Field Programmable Gate Arrays), among others.

[0006] When implementing TDC using an FPGA, the following problems may arise: Firstly, the resources provided to the FPGA, including logic cells, lookup tables (LUTs), and routing channels, are limited, which can restrict the resolution and accuracy of the TDC implemented in the FPGA. Secondly, at high clock frequencies, jitter can introduce errors in TDC measurements. Here, jitter refers to fluctuations in the timing of the clock signal due to factors such as noise and temperature. Thirdly, due to factors such as voltage drop, temperature changes, and manufacturing process variations, the TDC may exhibit nonlinear behavior, which can introduce errors in TDC measurements at high resolutions. Fourthly, FPGAs experience delays through signal processing and routing, and such delays can introduce errors in TDC measurements at small time intervals.

[0007] Routing in FPGAs refers to the process of connecting programmable logic elements (e.g., lookup tables, flip-flops, and multiplexers) to a chip to form a desired logic circuit. Routing determines how signals propagate through the chip and can significantly impact the overall performance of the design. One of the main factors that can cause delay in FPGA routing is the capacitance of the interconnect wires that connect the logic elements. As the number of logic elements and the distance between them increases, the capacitance of the interconnect wires also increases. This capacitance can delay signal propagation through the wires, increasing the overall design delay. Another factor that can cause delay in FPGA routing is routing congestion. Routing congestion occurs when the FPGA's routing resources are limited and there are many logic elements that need to be connected. Routing congestion can cause delay because it increases the distance between logic elements and increases the capacitance of the interconnect wires.

[0008] A tapped delay line is a digital signal processing technique used to implement thermometer codes. In a thermometer code, each bit of a binary number is represented by a separate signal line, with the line corresponding to the "on" bit representing what the binary value indicates. To implement a thermometer code using a tapped delay line, a series of delay elements are used to represent each bit. The input binary number is converted into a series of pulses, each pulse representing one bit of the binary number. These pulses are delayed by a different amount depending on the position of each bit before being fed into the tapped delay line. At the output of the tapped delay line, each output signal line represents a bit of the binary number, with the "on" line representing the binary value. This technique is commonly used in digital-to-analog converters (DACs) to convert digital signals to analog signals.

[0009] An FPGA carry chain block is a hardware block used to perform high-speed arithmetic operations, particularly addition and subtraction. Adding and subtracting multi-bit numbers in digital circuits requires the calculation of carry bits, which can become a bottleneck in high-speed operations. Carry chain blocks efficiently handle these carry bit calculations, enabling faster and more efficient arithmetic operations. A carry chain block typically consists of a sequence of full adder circuits interconnected in a specific way to form a carry chain. Each full adder circuit calculates one bit of its output and the carry bit to be propagated to the next stage in the chain. By connecting these full adder circuits in a chain, the carry bits propagate through the chain during one clock cycle, enabling high-speed addition and subtraction of multi-bit numbers. In addition to providing high-speed arithmetic operations, carry chain blocks can also be used to implement counters and other sequential circuits that require the calculation of carry bits.

[0010] A timing report tool is a software tool used to analyze the timing performance of a design implemented on an FPGA. This tool generates a report that provides information about the design's timing characteristics. This report includes information about the design's timing characteristics, including data path delay, critical path, setup and hold times, clock skew, and maximum operating frequency. The data path delay is the time it takes for a data signal to propagate through the logic elements of the FPGA.

[0011] A multiplexer, abbreviated as "MUX," is an electronic circuit that selects one of several input signals and transmits the selected input to an output line. The input-output structure of a multiplexer typically consists of multiple input lines, a selection line, and one or more output lines. The number of input lines corresponds to the number of input signals the multiplexer can select, and the selection line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a selection line that determines which of the four input signals to transmit as output. The selection line is controlled by a binary code indicating the selected input line. Multiplexers are often used in digital systems to reduce the number of wires required to transmit data and control signals. They can be used to embody functions such as data selectors, memory address decoders, and bus assignment circuits. According to one aspect of the present invention, the provided FPGA(1) is programmed to include a first delay line section(20) to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section(30) that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section(60) that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops (FFs) included in the first delay line section.

[0012] In this case, the FPGA(1) is programmed to further include a second delay line section to which the input pulse is input, and the code conversion unit aligns and combines the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, the predetermined second criterion may be the data path delay from the output node of the input pulse to the output node of each of the multiple flip-flops included in the first delay line section and the second delay line section.

[0013] In this case, the FPGA(1) may be programmed to further include an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal, a clock pulse counting unit (40) that counts the number of clock pulses that occur during the duration of the input pulse, and a calculation unit that determines the value of the time difference using a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses, and the number of counted clock pulses.

[0014] According to another aspect of the present invention, the provided FPGA is programmed to include a plurality of delay line sections to which input pulses having a width equal to the time difference between the occurrence of a start signal and an end signal are input, a code conversion section that combines a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code, and a calculation section that uses the conversion code to determine the occurrence time difference, wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

[0015] In this case, the FPGA may be programmed to further include an input signal generation unit that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal, a clock pulse counting unit that counts the number of clock pulses that occur during the duration of the input pulse, a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses, and a calculation unit that determines the value of the generation time difference using the number of counted clock pulses.

[0016] According to one aspect of the present invention, a non-volatile recording medium readable by a provided electronic device may contain a binary file containing configuration data that programmed the FPGA to implement a digital circuit comprising: a first delay line section (20) to which an input pulse having the time difference between a start signal and an end signal as its width is input; a code conversion section (30) that converts and outputs the order of elements of a thermometer code output by the first delay line section; and a calculation section (60) that determines the time difference using the converted code output by the code conversion section. In this case, the converted code is an arrangement of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops (FFs) included in the first delay line section.

[0017] In this case, the digital circuit further includes a second delay line section to which the input pulse is input, and the code conversion section aligns and combines the elements of the thermometer code output by the first delay line section and the elements of the thermometer code output by the second delay line section according to a predetermined second criterion to generate the conversion code, wherein the predetermined second criterion may be the data path delay from the output node of the input pulse to the output node of each of the multiple flip-flops included in the first delay line section and the second delay line section.

[0018] In this case, the digital unit may further include an input signal generation unit (10) that generates an input pulse having a width equal to the time difference between the rising edge of the start signal and the rising edge of the end signal, a clock pulse counting unit (40) that counts the number of clock pulses that occur during the maintenance period of the input pulse, and a calculation unit that determines the value of the occurrence time difference using a first thermometer code (TC1) output by the code conversion unit at the rising edge of the first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code conversion unit at the rising edge of the clock pulse that occurs immediately after the last clock pulse among the generated clock pulses, and the number of counted clock pulses.

[0019] According to another aspect of the present invention, a non-volatile recording medium readable by a provided electronic device may record a binary file containing configuration data that programmed the FPGA to implement a digital circuit comprising: a plurality of delay line sections to which input pulses having the time difference between a start signal and an end signal as a width are input; a code conversion section that combines a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that determines the time difference using the conversion code. In this case, the conversion code is an arrangement of the elements of the plurality of thermometer codes according to a predetermined criterion, the predetermined criterion may be the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections. According to one aspect of the present invention, the provided TDC system may include a PCB board (100) including the FPGA (1) described above, and a computing device (200) that acquires the time difference from the PCB board.

[0020] According to one aspect of the present invention, an electronically readable non-volatile recording medium is provided, which contains a binary file containing configuration data that programs the FPGA to implement a digital circuit including a group of TDCs, a clock generation unit that generates a clock and provides it to the group of TDCs in common, a tag counter that generates a second count which is a value obtained by counting the clocks and provides it to the group of TDCs in common, and a processing unit. Any TDC among the group of TDCs includes an input signal generation unit that generates an input pulse having a rising edge that occurs at the same time as the rising edge of a start signal input to the arbitrary TDC, and a delay line unit to which the generated input pulse is input. At this time, the processing unit calculates a first value by multiplying the value of the second count (TC) observed at the time of the first newly generated clock pulse of the clock, after the rising edge of the start signal input to the arbitrary TDC has occurred, by the pulse period (CP) of the clock, and then subtracts the thermometer code output by the delay line section at the rising edge of the first newly generated clock pulse or the converted code obtained by converting the thermometer code from the first value to calculate the time of generation of the first start signal.

[0021] In this case, the arbitrary TDC operates in either a first mode or a second mode, generates the input pulse in both the first and second modes, and the arbitrary TDC may receive an end signal in the first mode. When the end signal is input to the arbitrary TDC, the input signal generation unit may generate the input pulse such that the width of the input pulse is the same as the time difference between the rising edge of the start signal and the rising edge of the end signal. When the arbitrary TDC operates in the first mode, the processing unit calculates the generation time difference between the start signal and the end signal using the thermometer code output by the delay line portion of the arbitrary TDC at the rising edge of the first newly generated clock pulse, and when the arbitrary TDC operates in the second mode, it may calculate the generation time of the start signal.

[0022] In this case, the arbitrary TDC may further include a clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. When the arbitrary TDC operates in the first mode, the processing unit may determine the value of the occurrence time difference using the thermometer code output by the delay line unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the thermometer code output by the delay line unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse counting unit.

[0023] In this case, the arbitrary TDC may further include a code conversion unit that outputs a converted code generated by converting the order of elements of the thermometer code output by the delay line unit, and a clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. When the arbitrary TDC operates in the first mode, the processing unit may determine the value of the occurrence time difference using the first thermometer code output by the code conversion unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the second thermometer code output by the code conversion unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse counting unit.

[0024] In this case, the processing unit may determine the relationship between a first occurrence time, which is the time the start signal is input to any TDC among the group of TDCs, and a second occurrence time, which is the time the second start signal is input to another TDC among the group of TDCs. Furthermore, on the FPGA circuit, the tag counter may be located inside a region that connects the regions occupied by the group of TDCs.

[0025] According to one aspect of the present invention, a group of TDCs (100) having identical configurations, a clock generation unit (140) that generates a clock and provides the generated clock to the group of TDCs in common, a tag counter (130) that generates a second count which is the value obtained by counting the clock and provides the generated second count to the group of TDCs in common, and a processing unit (160) are programmed to include, the first TDC among the group of TDCs, an input signal generation unit (10) that generates a first input pulse (P1) having a rising edge that occurs at the same time as the rising edge of a first start signal (S1) input to the first TDC, An FPGA may be provided which includes a delay line section (20) to which the generated first input pulse is input, and the processing unit calculates a first value by multiplying the value of the second count (TC) observed at the time of the first newly generated clock pulse of the clock, after the rising edge of the first start signal input to the first TDC has occurred, by the pulse period (CP) of the clock, and then calculates the time of generation of the first start signal by subtracting the thermometer code output by the delay line section of the first TDC or a conversion code obtained by converting the thermometer code from the first value at the rising edge of the first newly generated clock pulse.

[0026] At this time, the first TDC is configured to operate in one of the first mode and the second mode. The first TDC is configured to generate the first input pulse in both the first mode and the second mode. The first TDC may be configured to receive a first end signal in the first mode. When the first end signal is input to the first TDC, the input signal generation unit may be configured to generate the first input pulse such that the width of the first input pulse is the same as the time difference between the rising edge of the first start signal and the rising edge of the first end signal. When the first TDC operates in the first mode, the processing unit may be configured to calculate the occurrence time difference between the first start signal and the first end signal using the thermometer code output by the delay line unit at the rising edge of the first clock pulse newly generated first. When the first TDC operates in the second mode, the processing unit may be configured to calculate the occurrence time of the first start signal.

[0027] At this time, the first TDC may further include a clock pulse counting unit (40) that counts the number of clock pulses of the clock generated during the maintenance period of the first input pulse. When the first TDC operates in the first mode, the processing unit may use the thermometer code output by the delay line unit at the rising edge of the first clock pulse among the clock pulses generated during the maintenance period of the first input pulse, the thermometer code output by the delay line unit at the rising edge of the clock pulse generated immediately after the last clock pulse among the clock pulses generated during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse counting unit to determine the value of the occurrence time difference.

[0028] At this time, the first TDC may further include a code conversion unit (30) that outputs a conversion code generated by converting the order of elements of the thermocouple code output by the delay line unit, and a clock pulse counting unit (40) that counts the number of clock pulses of the clock generated during the maintenance period of the first input pulse. When the first TDC operates in the first mode, the processing unit uses the first thermocouple code output by the code conversion unit at the rising edge of the first clock pulse among the clock pulses generated during the maintenance period of the first input pulse, the second thermocouple code output by the code conversion unit at the rising edge of the clock pulse generated immediately after the last clock pulse among the clock pulses generated during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse counting unit to determine the value of the generation time difference.

[0029] At this time, the conversion code aligns the order of elements of the thermocouple code output by the delay line unit according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the first input pulse to the output nodes of each of the plurality of flip-flops (FFs) included in the delay line unit.

[0030] At this time, the processing unit may be configured to determine the relationship between a first generation time, which is the generation time of the first start signal input to the first TDC among the group of TDCs, and a second generation time, which is the generation time of the second start signal input to the second TDC among the group of TDCs. On the circuit of the FPGA, the tag counter may be arranged inside an area (1000) that connects the areas occupied by the group of TDCs to each other.

[0031] In this case, the first TDC may further include a clock pulse count unit (40) that outputs a first count which is the result of counting the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, and a count selection unit (60) that in the first mode selects and outputs the first count from the first count and the second count, and in the second mode selects and outputs the second count from the first count and the second count.

[0032] In this case, if the first termination signal is not input to the first TDC operating in the first mode, the processing unit may be configured to cancel the first input pulse once it has finished calculating the generation time of the first start signal.

[0033] According to another aspect of the present invention, a non-volatile recording medium is provided on which program instructions executable by an electronic device are stored. The electronic device includes a group of TDCs having the same configuration, a clock generation unit that commonly provides a clock to the group of TDCs, a tag counter that generates a second count, which is a value obtained by counting the clocks, and provides it commonly to the group of TDCs, and a processing unit. Each of the TDCs includes an input signal generation unit and a delay line unit. When the program instruction is executed by the electronic device, the following steps are performed: an input signal generation unit of any TDC among the group of TDCs generates an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the arbitrary TDC; a delay line unit of the arbitrary TDC outputs one of the thermometer code of the input pulse and a converted code obtained by converting the thermometer code at the rising edge of the first newly generated clock pulse of the clock after the rising edge of the start signal has occurred; and the processing unit calculates a first value by multiplying the value of the second count observed at the time of the first newly generated clock pulse of the clock by the pulse period of the clock, and then subtracts one of the output codes from the first value to calculate the time of generation of the first start signal.

[0034] At this time, when the program instruction is executed by the electronic device, the arbitrary TDC operates in one of the first mode and the second mode, the arbitrary TDC generates the input pulse in both the first mode and the second mode, the arbitrary TDC receives an end signal in the first mode, and when the end signal is input to the arbitrary TDC, the input signal generation unit generates the input pulse such that the width of the input pulse is the same as the time difference between the rising edge of the start signal and the rising edge of the end signal, the processing unit calculates the generation time difference between the start signal and the end signal using one of the codes output by the delay line portion of the arbitrary TDC at the rising edge of the first newly generated clock pulse, and conversely, when the arbitrary TDC operates in the second mode, it may calculate the generation time of the start signal.

[0035] In this case, each TDC may further include a clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. When the program instruction is executed in the electronic device, if any TDC is operating in the first mode, the processing unit may perform a step of determining the value of the occurrence time difference using one of the codes output by the delay line unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, one of the codes output by the delay line unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse counting unit.

[0036] In this case, each TDC may further include a code conversion unit that outputs a converted code generated by converting the order of elements of the thermometer code output by the delay line unit, and a clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse. When the program instruction is executed by the electronic device, if any TDC operates in the first mode, the processing unit may further perform the step of determining the value of the occurrence time difference using the first thermometer code output by the code conversion unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, the second thermometer code output by the code conversion unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse counting unit.

[0037] In this case, when the program instruction is executed by the electronic device, the processing unit may further perform the step of determining the relationship between a first occurrence time, which is the time the start signal is input to any TDC among the group of TDCs, and a second occurrence time, which is the time the second start signal is input to another TDC among the group of TDCs. On the FPGA circuit, the tag counter may be located inside a region that connects the regions occupied by the group of TDCs. In this case, the electronic device may be an FPGA. According to another aspect of the present invention, a TDC system may be provided that includes a PCB board (100) including the FPGA described above, and a computing device (200) that acquires the occurrence time difference from the PCB board. [Effects of the Invention]

[0038] According to the present invention, it is possible to provide a TDC that provides a function for time-tagging the occurrence time of a single signal that indicates a single event. [Brief explanation of the drawing]

[0039] [Figure 1] Figure 1 shows a diagram of the FPGA configuration according to one embodiment of the present invention. [Figure 2] Figure 2 is a diagram illustrating an input pulse input to the first delay line section according to one embodiment of the present invention. [Figure 3] Figure 3 shows the configuration of the first delay line section according to one embodiment of the present invention. [Figure 4] Figure 4 is a diagram illustrating the buffer index in Figure 3. [Figure 5] Figure 5 shows a table illustrating data path delay according to one embodiment of the present invention. [Figures 6a-6b] Figures 6a and 6b show a configuration in which multiple delay line sections are arranged in parallel according to one embodiment of the present invention. [Figure 7a] Figure 7a shows the configuration of the first delay line section and the second delay line section of Figure 6b. [Figure 7b] Figure 7b shows the change in the FPGA configuration of Figure 1 when a second delay line is added in addition to the first delay line. [Figure 7c] Figure 7c illustrates the operation of the code conversion unit when two delay line sections are used according to one embodiment of the present invention. [Figure 8] Figure 8 shows a graph of delays with and without the application of the code conversion unit according to one embodiment of the present invention. [Figure 9] Figure 9 is a diagram illustrating, according to one embodiment of the present invention, the arrangement criteria for flip-flop output values ​​and the increase in the number of taps in Figure 8, depending on whether or not the code conversion unit is applied. [Figure 10] Figure 10 shows the configuration of an FPGA provided by a preferred embodiment of the present invention. [Figures 11a-11c] Figures 11a to 11c illustrate the configuration and operation method of any one of the multiple TDCs shown in Figure 10. [Figure 12]Figure 12 is a diagram illustrating an input pulse input to the delay line section according to one embodiment of the present invention. [Figure 13a] Figure 13a shows the relative positions of the multiple TDCs, tag counters, and input multiplexers shown in Figure 10 on the surface of the actual circuitry implemented on the FPGA, in an FPGA provided according to one embodiment of the present invention. [Figures 13b-13c] Figures 13b and 13c conceptually represent the features of the present invention shown in Figure 13a. [Figure 14] Figure 14 is a flowchart showing a signal generation time calculation method provided by one embodiment of the present invention, which calculates the generation time of a predetermined input signal. [Figure 15] Figure 15 is a flowchart illustrating a method for calculating the time difference between a predetermined input start signal and an end signal, as provided by one embodiment of the present invention. [Figure 16] Figure 16 is a block diagram of a TDC system provided according to one embodiment of the present invention. [Modes for carrying out the invention]

[0040] Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and can be embodied in various other forms. The terms used herein are for the purpose of aiding the understanding of the embodiments and are not intended to limit the scope of the present invention. Furthermore, the singular form used herein also includes the plural form unless the context clearly indicates the opposite.

[0041] <Configuration for measuring the time difference between two events> Figure 1 shows a diagram of the FPGA configuration according to one embodiment of the present invention.

[0042] Figure 2 is a diagram illustrating an input pulse input to the first delay line section according to one embodiment of the present invention.

[0043] The following explanation will refer to both Figure 1 and Figure 2.

[0044] The FPGA(1) may include an input signal generation unit (10), a first delay line unit (20), a code conversion unit (30), a clock pulse count unit (40), a priority encoder unit (50), and an arithmetic unit (60).

[0045] Specifically, the FPGA(1) configuration described above could be a TDC (Time to Digital converter) configuration.

[0046] As shown in Figure 2, the input signal generation unit (10) can generate an input pulse (P1) whose width is the time difference (T) between the rising edge (E1) of a predetermined given start signal (S1) and the rising edge (E2) of a predetermined given end signal (S2). The input signal generation unit (10) can be composed of logic gates necessary for the above generation.

[0047] The first delay line section (20) can receive an input pulse (P1) having a width equal to the time difference (T) between the start signal (S1) and the end signal (S2). The first delay line section (20) can output a thermometer code (O1). In this case, the thermometer code is composed of the output values ​​of the flip-flops included in the first delay line section (20), and for example, an 8-bit value, where the output values ​​of each flip-flop can be referred to as elements of the thermometer code.

[0048] Figure 3 shows the configuration of the first delay line section according to one embodiment of the present invention.

[0049] Figure 4 is a diagram illustrating the buffer index in Figure 3.

[0050] The first delay line section (20) may include a delay line (D_L) containing a plurality of buffers (delay elements) (B), and D-flip-flops (FF) tapped to the output terminals of each buffer (B) of the delay line.

[0051] Multiple buffers can be connected using a cascade delay scheme. That is, multiple buffers can be arranged according to the order in which the input pulses (P1) flow.

[0052] The waveform (Signal) of the input pulse (P1) in Figure 3 can be output at the output terminals of each buffer (B) with a predetermined delay. That is, the output value of the first buffer (B1) is output at the output terminal of the first buffer (B1) with a predetermined delay, and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value of the first buffer (B1) (for example, "1") can also be input to the first flip-flop (FF1).

[0053] That is, a signal entering the input terminal of the [k]th buffer may be output at the output terminal of the [k]th buffer with a predetermined delay. The output terminal of the [k]th buffer may then be connected to the input terminal of the [k+1]th buffer. The output value of the [k]th buffer (e.g., "1" or "0") may also be input to the [k]th flip-flop. In this case, data path delays may occur between each buffer (B) and through the flip-flops (FF). For example, a delay of d1 may occur before the input value ("1") of the first buffer (B1) is transmitted to the second buffer (B2), and a delay of d11 may occur before the output value ("1") of the first buffer (B1) is transmitted to the first flip-flop (FF1). Similarly, a delay may occur each time data is transmitted from the previous buffer to the next buffer, and each time data is transmitted from any buffer to a flip-flop connected to that buffer.

[0054] Figure 4 is a diagram illustrating the buffer index according to one embodiment of the present invention.

[0055] Each field in the table in Figure 4 represents the buffer name, index, and output value for each buffer.

[0056] Each buffer may be assigned an index that defines the connection order of each buffer. For example, the first buffer (B1) may be assigned index "1", the second buffer (B2) may be assigned index "2", and similarly the eighth buffer (B8) may be assigned index "8". In this way, if each buffer (B) is arranged according to the order in which the input pulses (P1) flow, and the indices are arranged according to that order, then for example, 1000 buffers may each be assigned an index ranging from 1 to 1000.

[0057] Figure 5 shows a table illustrating the data path delay considered in one embodiment of the present invention.

[0058] Referring to Figures 1 and 5, the code conversion unit (30) can convert and output the order of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line unit (20). At this time, the code output by the code conversion unit (30) (e.g., 11010000) (the order of the indices in the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) can be called the "converted code (CO1)".

[0059] The conversion code (CO1) output by the code conversion unit (30) may be an arrangement of the elements of the thermometer code (O1) according to a predetermined criterion. In this case, the predetermined criterion may be the data path delay from the output node (N1) of the input pulse (P1) to the output node (N2) of each of the multiple flip-flops (FF) included in the first delay line unit (20). This will be explained in detail with reference to Figure 5.

[0060] Each field in the table can represent the buffer index number, the value of the first delay, the value of the second delay, and the added value (rank). In this case, the rank can represent the rank relative to the total added value. In this case, the buffer with the smallest added value can have rank 1, and the buffer with the highest added value can have the last rank. Alternatively, in other embodiments, the reverse is also possible.

[0061] As described above in Figure 3, the sum value may represent the time it takes for data to be transmitted from the node (N1) where the input pulse (P1) is output to any flip-flop (e.g., FF4).

[0062] A first delay may occur, which is the time it takes for the input value of any buffer to be transmitted to another buffer adjacent to the arbitrary buffer, and a second delay may occur, which is the time it takes for the output value of the arbitrary buffer to be transmitted as the input to a flip-flop connected to the arbitrary buffer.

[0063] In this case, the sum of the first delay value and the second delay value for each buffer can be called the data path delay.

[0064] Referring to both Figures 3 and 5, when the indices of each buffer are arranged in order, the rank of the sum of the first delay value and the second delay value may differ from the rank of the index numbers of each buffer. For example, in the case of the third buffer, the buffer array rank is 3, so the index number is "3", but the rank of the sum value may be "5". Looking at it in more detail, in order for data to be transmitted to the third flip-flop (FF3), it must pass through the first buffer (B1), the second buffer, and the third buffer. At this time, predetermined delays (d1, d2, d3) occur each time the data passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur before the data output from the third buffer (B3) is output as the output value of the third flip-flop (FF3). In other words, the delay from the output node (N1) of the input pulse (P1) to the output nodes (N2, N23) of the third flip-flop (FF3) can be the sum of d1, d2, d3, and d13.

[0065] In this way, the delay (i.e., the sum) until data is transmitted to the output node of each flip-flop (FF3) can be calculated.

[0066] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3, and the buffer index for the fourth flip-flop (FF4) is 4. That is, the fourth flip-flop (FF3) must pass through one more buffer than the third flip-flop (FF4), but nevertheless, the delay sum to the output node of the third flip-flop, which has a buffer index of 3, may be greater.

[0067] The code conversion unit (30) can convert the order of the elements of the thermometer code (O1) based on the calculated delay (addition value) (for example, in ascending order of addition value).

[0068] The converted code (CO1) output by the code conversion unit (30) can be provided to the priority encoder unit (50).

[0069] The priority encoder unit (50) can digitize long thermometer codes. For example, the priority encoder unit (50) can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if there are 5200 buffers (delay elements) (B) and 5200 flip-flops (FFs) connected to the buffer as shown in Figure 3, a sequence of 5200 consecutive binary numbers will be output, which can be represented as a 13-bit binary number.

[0070] In other words, the priority encoder unit (50) can represent a 5200-bit first thermometer code (TC1) and a second thermometer code (TC2) as 13-bit binary numbers, respectively, as output values ​​(CO1) corresponding to the time of the code conversion unit (30).

[0071] Referring to Figure 2, the first thermometer code (TC1) may be the code output by the code conversion unit (30) in relation to the rising edge of the input pulse (P1) at the rising edge (E4) of the first clock pulse (CK2) that occurred after the rising edge (E1) of the input pulse (P1). The first thermometer code (TC1), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0072] The second thermometer code (TC2) may be the code output by the code conversion unit (30) in relation to the falling edge (E2) of the input pulse (P1) at the rising edge (E6) of the first clock pulse (CK4) that occurred after the falling edge (E2) of the input pulse (P1). The second thermometer code (TC2), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0073] In this case, the timing of the first thermometer code (TC1) and the timing of the second thermometer code (TC2) may be shorter than the period of the clock pulse (CK).

[0074] Referring again to Figures 1 and 2, the clock pulse counting unit (40) can receive an input pulse (P1) from the input signal generation unit (10).

[0075] The clock pulse counting unit (40) can count the number of clock pulses (CK) that occur during the duration (T) of the input pulse (P1). For example, in Figure 2, since there are two rising edges of the clock pulses that occur during the period when the input pulse (P1) is ON, such as edges (E4, E5), the counted value may be two. The clock pulses may refer to pulses that constitute a clock generated inside or outside the TDC. The output value (coarse count) of the clock pulse counting unit (40), i.e., the counted value, can be provided to the calculation unit (60).

[0076] Referring to Figures 1 and 2, the calculation unit (60) can determine the value of the occurrence time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses.

[0077] In other words, the time difference in occurrence can be calculated as shown in Equation 1. [Equation 1] T = CP * CC + TC1 - TC2

[0078] In Equation 1, T is the time difference between the start signal and the end signal, CP is the clock pulse generation period, CC is the number of clock pulses counted by the clock pulse counting unit (40), TC1 is the first thermometer code, and TC2 is the second thermometer code.

[0079] For example, in the example shown in Figure 2, the time difference in occurrence may be 2 * Period + TC1 - TC2.

[0080] Figures 6a and 6b show a configuration in which multiple delay line sections are arranged in parallel according to one embodiment of the present invention.

[0081] As shown in Figure 6a, two or more delay line sections (20) can be connected in parallel. In this case, the input pulse (P1) output from the input signal generation unit (10) can be input to the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24), respectively. The first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24) can then be input to the code conversion unit (30).

[0082] Let's consider the case where, as shown in Figure 6b, two delay line sections (20) are connected in parallel in another embodiment.

[0083] For example, the input pulse (P1) output from the input signal generation unit (10) can be provided along a first path (path1) in which the output terminal of the input signal generation unit (10) and the input terminal of the first delay line unit (21) are connected to each other, and along a second path (path2) in which the output terminal of the input signal generation unit (10) and the input terminal of the second delay line unit (22) are connected to each other.

[0084] In this case, the time it takes for the input pulse (P1) output from the input signal generation unit (10) to reach the input terminal of the first delay line unit (21) and the input terminal of the second delay line unit (22) may be different. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path). In the embodiment shown in Figure 6a, since the length of the first path (path1) is shorter than the length of the second path (path2), it can be seen that the input timing of the input pulse (path1) via the first path (path1) is earlier than the input timing of the input pulse (path2) via the second path (path2).

[0085] Figure 7a shows the configuration of the first delay line section and the second delay line section of Figure 6b.

[0086] Figure 7b shows the change in the FPGA configuration of Figure 1 when a second delay line is added in addition to the first delay line.

[0087] Figure 7c illustrates the operation of the code conversion unit when two delay line sections are used according to one embodiment of the present invention.

[0088] For the sake of explanation, Figure 7a shows each delay line section as containing four buffers and four flip-flops.

[0089] In Figure 7c, each field in the table can represent the delay line section number, buffer index number, first delay value, second delay value, first increment value (first rank), and first increment value (overall rank). In this case, the first rank can represent the rank of each increment value relative to the buffer index of the buffer in each delay line section. The overall rank can represent the rank of each increment value relative to the buffer index of all buffers in the first and second delay line sections. In this case, the buffer with the smallest increment value can have the first rank, and the buffer with the highest increment value can have the last rank. Alternatively, in other embodiments, the reverse is also possible. The method for determining the increment value is as described in Figure 5.

[0090] The code conversion unit (30) may sort and combine the elements of a first set (for example, {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) which is obtained by sorting pairs of the sum of elements of the thermometer code output by the first delay line unit (21) and buffer indices in ascending order of sum, and the elements of a second set (for example, {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) which is obtained by sorting pairs of elements of the thermometer code output by the second delay line unit (22) and indexes in ascending order of sum, to generate a single conversion code.

[0091] In other words, each element of the first set and each element of the second set can be sorted in ascending order of their summation value.

[0092] For example, the output values ​​based on the buffer index in the first delay line section (21) may be {1, 2, 3, 4}, and the output values ​​based on the buffer index in the second delay line section (22) may be {5, 6, 7, 8}. Furthermore, in the embodiments of Figures 6b and 7a, delay (d1) may be smaller than delay (d5). Therefore, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output values ​​of the flip-flops for each buffer index can be sorted according to the sorted order. For example, the sorted values ​​(buffer indices) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0093] As described above, when multiple delay line sections (20) are used, they may have slightly different input delays depending on their arrangement. Figure 8, described below, shows the delays depending on the arrangement when multiple delay line sections are used.

[0094] Figure 8 shows a graph of delays with and without the application of the code conversion unit according to one embodiment of the present invention.

[0095] Figure 9 is a diagram illustrating, according to one embodiment of the present invention, the arrangement criteria for flip-flop output values ​​and the increase in the number of taps in Figure 8, depending on whether or not the code conversion unit is applied.

[0096] Figure 8(a) shows a delay graph based on the number of taps when the code conversion unit (30) is not applied, and Figure 8(b) shows a delay graph based on the number of taps when the code conversion unit (30) is applied.

[0097] The fields in the table in Figure 9 include the sorting order, the sorting criteria for the flip-flop output values, and the sorting order of the total delay sum.

[0098] The following explanation will refer to both Figures 8 and 9.

[0099] The horizontal axis of graph (g1, g2) represents the number of taps. Referring to Figure 7c, one tap may represent a pair of buffers (delay elements) (e.g., B1) and the flip-flops (FF1) connected to them. For example, if the total number of buffer and flip-flop pairs is 1000, the total number of taps may be 1000. The vertical axis of graph (g1, g2) represents the delay time (ns). This delay time may represent the sum of the delays required for data to be transmitted to the output nodes of the flip-flops tapped to each buffer as described in Figure 5.

[0100] Referring to both FIGS. 7a to 9, an increase in the number of taps in graph (g1) may, for example, mean an increase in the buffer index. For example, when the number of taps on the horizontal axis of graph (g1) is 4, it may mean buffer index 4. At this time, the delay value on the vertical axis of graph (g1) may be D4 (= d1 + d2 + d3 + d4 + d14) as shown in FIG. 7c. For example, when the number of taps is 5, it may mean buffer index 5. At this time, the delay value on the vertical axis of graph (g1) may be D5 (= d5 + d15) as shown in FIG. 7c. At this time, referring to FIG. 9, D4 > D5 may be possible. Here, it can be seen that the delay observed in the flip-flop of each tap does not increase as the index of the tap (for example, index 4 -> index 5) increases, but may locally decrease even when the index of the tap increases.

[0101] On the other hand, an increase in the number of taps in graph (g2) does not mean an increase in the buffer index, but may mean an increase in the position according to the alignment order in a state where the output values of each flip-flop are aligned by the code conversion unit (30). For example, when the number of taps on the horizontal axis of graph (g2) is 4, the position order of the aligned buffer index may be 1, 2, 5, 3, which may mean buffer index 3. And the delay value on the vertical axis of graph (g2) in this case may be D3 (= d1 + d2 + d3 + d13). For example, when the number of taps is 5, the position order of the aligned buffer index may be 1, 2, 5, 3, 6, which may mean buffer index 6. And the delay value in this case may be D6 (= d5 + d6 + d16). At this time, referring to FIG. 9, D3 < D6 may be possible. That is, it can be seen that when the code conversion unit (30) of the present invention is not applied as shown in (a) of FIG. 8, the graph (g1) regarding the delay accompanying an increase in the number of taps does not have the property of monotonically increasing. On the other hand, when the code conversion unit (30) of the present invention is applied as shown in (b) of FIG. 8, it can be seen that the graph (g2) regarding the delay accompanying an increase in the number of taps exhibits an increasing phenomenon that does not decrease.

[0102] For example, unlike ASICs, which are custom semiconductors, FPGAs can be directly designed through programming, allowing the chip's functionality to be changed through programming. Therefore, unlike ASICs, the functionality of each component included in an FPGA can change (or depending on the arrangement of the components), so the delay does not always increase with each increase in the number of taps; it may decrease, and it may not always be possible to see a phenomenon where the delay does not decrease.

[0103] However, as explained, it can be seen through graph (g2) that the code conversion unit (30) can compensate for the monotonically increasing nature of the first delay line unit (20).

[0104] As described above, when multiple delay line sections (20) are used, delay alignment can be provided through the code conversion section. As a result, errors due to jitter can be corrected, and a TDC with high time resolution can be provided. For example, when four delay line sections are configured in parallel to have a total of 9600 taps, a TDC with a resolution of 0.8 ps per tap can be provided.

[0105] <Configuration for tagging the occurrence time of a single event> Figure 10 shows the configuration of an FPGA provided by a preferred embodiment of the present invention.

[0106] The FPGA(1) configuration shown in Figure 10 can be implemented by a binary file containing configuration data that programs FPGA(1) to implement a digital circuit having the configuration shown in Figure 10. FPGA(1) shown in Figure 10 can contain one or more TDCs. A TDC may be represented by reference number 100, but different TDCs can be represented by TDCx (e.g., TDC1(101), TDC2(102), TDC3(103), TDC4(104), ...).

[0107] The one or more TDCs may all have identical internal configurations, that is, they can all operate in the same manner.

[0108] The FPGA(1) may include an input multiplexer(150) that provides start and end signals to each TDC(100). The input multiplexer(150) may receive an event pulse indicating an event that the FPGA(1) is trying to detect, and may output the event pulse as the start or end signal for each TDC(100) according to a predetermined set of rules.

[0109] FPGA(1) may include a tag counter(130).

[0110] The FPGA(1) may include a clock generation unit (140). Part or all of the TDC(100) included in the FPGA(1), and the tag counter(130), can receive the clock generated by the clock generation unit (140) as input. Therefore, the clock generated by the TDC(100) can also be referred to as a common clock.

[0111] The tag counter (130) can provide a second count, which is the result of counting the number of times the input clock has been generated, to some or all of the TDC (100) included in the FPGA (1). The second count may also be called the "tag count" or "global count".

[0112] Each TDC(100) may be configured to operate in one of two modes. The mode selection signal, which determines the operating mode of each TDC(100), is shown as "Mode Sel" in Figure 10. The operating mode of each TDC(100) can be determined by an external device. The two modes will be described in more detail later in this specification.

[0113] As described above, each TDC (100) can receive start and end signals from the input multiplexer (150), a clock from the clock generator (140), and a second count from the tag counter (130).

[0114] Each TDC(100) can output three output signals, which are denoted as TC1, TC2, and CNT in Figure 10. The meanings of these three symbols will be explained in more detail later in this specification.

[0115] FPGA(1) may contain one or more DMA sections. A DMA section may be represented by reference number 110, but different DMAs can be represented by DMAx (e.g., DMA1(111), DMA2(112), DMA3(113), DMA4(114), ...). DMAx corresponds to TDCx.

[0116] The three output signals output by each TDC(100) are provided to the corresponding DMA(110).

[0117] The input signal generation unit (10) may further include a processing unit (160). The processing unit (160) receives signals from the DMA (110) output by the TDC (100) and can process them using a predetermined algorithm.

[0118] Figure 11 illustrates the configuration and operation method of any one of the multiple TDCs shown in Figure 10.

[0119] The TDC(100) may include an input signal generation unit (10), a delay line unit (20), a data sampling unit (70), and a priority encoder unit (50).

[0120] The data sampling unit (70) may include a code conversion unit (30), a clock pulse counting unit (40), and a count selection unit (60).

[0121] The count selection unit (60) may receive a first count output by the clock pulse count unit (40) and a second count output by the tag counter (130) shown in Figure 10. The count selection unit (60) may be configured to select and output either the first count or the second count according to the mode selection signal (Mode Sel) input to the TDC (100).

[0122] The configuration and functions of the input signal generation unit (10), delay line unit (20), code conversion unit (30), clock pulse count unit (40), and priority encoder unit (50) are the same as those of the components with the same reference numbers shown in Figures 1 and 7b, and therefore the above description will suffice. Figure 11b shows the TDC of Figure 11a operating in the first mode, and Figure 11c shows the TDC of Figure 11a operating in the second mode.

[0123] The following explanation will refer to Figure 11b.

[0124] The following describes the case where the mode selection signal (Mode Sel) is a value indicating the first mode. In this case, the input multiplexer (150) in Figure 10 can provide the start signal and end signal to the TDC (100). At this time, the count selection unit (60) may be configured to select and output the first count output by the tag counter (130). In this case, the code conversion unit (30) can output a first thermometer code (TC1) corresponding to the start signal and a second thermometer code (TC2) corresponding to the end signal.

[0125] As a result, TDC(100) can output the first thermometer code (TC1), the second thermometer code (TC2), and the first count (CNT).

[0126] The following explanation will refer to Figure 11c.

[0127] The following describes the case where the mode selection signal (Mode Sel) is a value indicating the second mode. In this case, the input multiplexer (150) in Figure 10 can provide the start signal to the TDC (100). At this time, the count selection unit (60) may be configured to select and output the second count output by the tag counter (130). In this case, it is not necessarily prohibited for the input multiplexer (150) in Figure 10 to provide the end signal to the TDC (100), but in a preferred embodiment, the input multiplexer (150) may not provide the end signal to the TDC (100). If the input multiplexer (150) does not provide the end signal to the TDC (100), the code conversion unit (30) may not output the second thermometer code (TC2). However, even in this case, since the input multiplexer (150) provides the start signal to the TDC (100), the code conversion unit (30) outputs the first thermometer code (TC1).

[0128] As a result, the TDC(100) can output the first thermometer code (TC1) and the second count (CNT). As shown in Figure 10, each DMA(110) can provide the corresponding signal output from the TDC(100) to the processing unit (160).

[0129] When a TDC(100) connected to any DMA(110) operates in the first mode, the DMA(110) can transmit the first thermometer code (TC1), the second thermometer code (TC2), and the first count (CNT) output by the TDC(100) to the processing unit (160).

[0130] In contrast, when a TDC(100) connected to any DMA(110) operates in the second mode, the arbitrary DMA(110) can transmit the first thermometer code (TC1) and the second count (CNT) output by the TDC(100) to the processing unit (160).

[0131] The processing unit (160) can use information provided by an arbitrary DMA (110) to determine the time difference between two consecutive events associated with the arbitrary DMA (110), or to determine the time of occurrence of a single event associated with the arbitrary DMA (110).

[0132] The processing unit (160) may be able to determine whether the TDC (100) connected to any DMA (110) operated in the first mode or the second mode.

[0133] In one embodiment, the entity that determines the value of the mode selection signal (Mode Sel) input to the TDC(100) may be another functional unit not shown in Figure 10, in which case the value of the mode selection signal (Mode Sel) input to the TDC(100) may be provided to the processing unit (160).

[0134] In other embodiments, the processing unit (160) may be the main entity that determines the value of the mode selection signal (Mode Sel).

[0135] When the TDC(100) connected to the arbitrary DMA(110) operates in the first mode, the processing unit(160) can determine the time difference between two consecutive events associated with the arbitrary DMA(110). That is, the processing unit(160) can perform the function of the arithmetic unit(60) in Figure 1. The occurrence times of the two events can be determined by the start signal and end signal input to the TDC(100), respectively.

[0136] When a TDC(100) connected to any DMA(110) operates in the second mode, the processing unit (160) can determine the occurrence time of a consecutive single event associated with the arbitrary DMA(110). Here, the occurrence time of the single event can be determined by a start signal input to the TDC(100). At this time, the processing unit (160) knows that the TDC(100) is operating in the second mode, and therefore can ignore information regarding an end signal that may or may not be input to the TDC(100) without waiting. In other words, the processing unit (160) can execute a predetermined routine regardless of whether or not a second thermometer code (TC2) is generated, which may be output by the TDC(100) operating in the second mode.

[0137] When the TDC(100) that provided the data that the processing unit (160) must process operates in the first mode, the processing method of the processing unit (160) is shown in Equation 1 and Figure 2 above. Now, when the TDC(100) that provided the data that the processing unit (160) must process operates in the second mode, the processing method of the processing unit (160) will be explained using Equation 2 and Figure 12. [Equation 2] T0 = CP * TC - TC1 In Equation 2, T0 is the time of the start signal generation, CP is the clock pulse generation period, TC is the number of clock pulses counted by the tag counter (130) in Figure 10, and TC1 is the first thermometer code.

[0138] Figure 12 is a diagram illustrating an input pulse input to the delay line section according to one embodiment of the present invention.

[0139] As shown in Figure 12, the input signal generation unit (10) can generate an input pulse (P1) that starts from the rising edge of a predetermined given start signal (S1). In other words, the rising edge of the input pulse (P1) occurs at the rising edge of the start signal (S1).

[0140] The operating principle of the input signal generation unit (10) shown in Figure 11a is the same as that of the input signal generation unit (10) shown in Figure 1. Therefore, if an termination signal is provided to the input signal generation unit (10), a falling edge may occur in the input pulse (P1), causing the input pulse (P1) to disappear. However, Figure 12 shows an example where no termination signal is provided to the input signal generation unit (10), resulting in a state where no falling edge occurs in the input pulse (P1).

[0141] If the termination signal is not generated, the input pulse (P1) may persist semi-permanently. To eliminate the input pulse (P1), the processing unit (160) can also reset the TDC (100) operating in the second mode after processing all the data provided by the TDC (100) operating in the second mode according to a predetermined algorithm. In this way, the input pulse (P1) output by the input signal generation unit (10) may disappear. The input pulse (P1) can also be eliminated by the above configuration and other design methods. For example, the processing unit (160) can provide the TDC (100) operating in the second mode with a dummy pulse that is not the target of measurement as the termination signal at an appropriate time.

[0142] In one embodiment, the TC in Equation 2 may be the generation sequence of the clock pulses first recorded in the tag counter (130) after the rising edge of the input pulse has occurred (e.g., 247). The TC in Equation 2 may be the same as the second count shown in Figure 10.

[0143] Furthermore, TC1 in the above equation 2 may be the first thermometer code (TC1) output by the code conversion unit (30) at the rising edge of the first recorded clock pulse.

[0144] The processing unit (160) can determine the generation time of the start signal input to the TDC (100) operating in the second mode by applying the second count (TC), the first thermometer code (TC1), and the clock period (CP) of the clock output by the clock generation unit (140) to Equation 2.

[0145] The multiple TDCs shown in Figure 10 can each operate independently. To aid understanding, the following example is provided.

[0146] In other words, two signals selected by the input multiplexer (150) can be provided as a start signal and an end signal for the first TDC (101), respectively. In this case, the mode selection signal (Model Sel 1) input to the first TDC (101) can have a value indicating the first mode, and the processing unit (160) can analyze the data output by the first TDC (101) to calculate the time difference between the occurrence of the two signals.

[0147] The input multiplexer (150) may, at the same time as, or with a time delay from, providing the start signal or end signal for the first TDC (101), provide the second start signal for the second TDC (102) to the second TDC (102). In this case, the mode selection signal (Model Sel 2) input to the second TDC (102) may have a value indicating the second mode, and the processing unit (160) may analyze the data output by the second TDC (102) to determine the generation time of the second start signal.

[0148] Figure 13a shows the relative positions of the multiple TDCs, tag counters, and input multiplexers shown in Figure 10 on the surface of the actual circuitry implemented on the FPGA, in an FPGA provided according to one embodiment of the present invention.

[0149] The values ​​regarding the occurrence time of the start or end signal measured by each TDC may have a large error depending on the length of the line through which the start or end signal travels. Therefore, the location where the start or end signal is provided needs to be optimized.

[0150] Furthermore, the process of determining the generation time of the start signal measured by each TDC in the second mode involves a clock provided in common to the multiple TDCs by the clock generation unit (140). If there is a large difference in the time it takes for the clocks generated by the clock generation unit (140) to reach the input terminals of different TDCs (100), there is a problem that the generation time values ​​calculated by each of the multiple TDCs will include a time axis bias. The difference in the time it takes for the clocks to reach the input terminals of different TDCs (100) may be proportional to the distance between the clock generation unit (140) and the input terminals of the different TDCs (100). Therefore, the design must minimize the difference in the distance between the clock generation unit (140) and the input terminals of the different TDCs (100). For this reason, as shown in Figure 13a, one embodiment of the present invention is characterized by being arranged inside the region surrounded by the multiple TDCs.

[0151] Each TDC includes a delay line portion (20), but in one embodiment of the present invention, the delay line portion (20) will have a form that extends long in one direction on the actual circuit of the FPGA. Therefore, one TDC will have a form that extends long in one direction.

[0152] Figures 13b and 13c conceptually represent the features of the present invention shown in Figure 13a.

[0153] Each TDC formed on FPGA(1) has a unidirectional elongated shape, and both ends can be defined along the extension direction of each TDC. For example, in Figure 13b, the ends of the first TDC(101) are indicated by reference numbers 1011 and 1012, the ends of the second TDC(102) are indicated by reference numbers 1021 and 1022, the ends of the third TDC(103) are indicated by reference numbers 1031 and 1032, and the ends of the fourth TDC(104) are indicated by reference numbers 1041 and 1042.

[0154] Figure 13c shows the case where there are only two TDCs that receive the common clock provided by the clock generation unit (140) in Figure 10.

[0155] As illustrated in Figures 13b and 13c, in a preferred embodiment of the present invention, the tag counter (130) is positioned inside a region (1000) that can be formed by connecting the ends of a plurality of TDCs. The configuration data used to program the FPGA (1) described above may include data that causes the tag counter (130) to be positioned inside the region (1000).

[0156] Figure 14 is a flowchart showing a signal generation time calculation method provided by one embodiment of the present invention, which calculates the generation time of a predetermined input signal.

[0157] The method shown in Figure 14 can be performed using a predetermined electronic device. In one preferred embodiment, the electronic device may be an FPGA, but is not limited to an FPGA. The electronic device may include a group of TDCs having the same configuration, a clock generation unit that provides a common clock to the group of TDCs, a tag counter that generates a second count, which is a value obtained by counting the clocks, and provides it to the group of TDCs in common, and a processing unit. Each of the TDCs may include an input signal generation unit and a delay line unit.

[0158] The signal generation time calculation method may include the following steps (S110), (S120), and (S130).

[0159] In step (S110), the input signal generation unit for any TDC among the group of TDCs can generate an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the arbitrary TDC.

[0160] In step (S120), the delay line portion of the arbitrary TDC can output one of the following codes at the rising edge of the first newly generated clock pulse of the clock after the rising edge of the start signal has occurred: the thermometer code of the input pulse and the converted code obtained by converting the thermometer code.

[0161] In step (S130), the processing unit calculates a first value by multiplying the value of the second count observed at the time of the first newly generated clock pulse by the pulse period of the clock, and then subtracts one of the output codes from the first value to calculate the time of generation of the first start signal.

[0162] One embodiment of the present invention may further include a step (S140) described later, after the step (S130) described above.

[0163] In step (S140), the processing unit can determine the relationship between a first occurrence time, which is the time the start signal is input to any TDC among the group of TDCs, and a second occurrence time, which is the time the second start signal is input to another TDC among the group of TDCs. For example, it can determine the value of the difference between the first occurrence time and the second occurrence time. In this case, in order to determine the second occurrence time, steps (S110), (S120), and (S130) can be executed independently of the second start signal.

[0164] In this case, the arbitrary TDC may be configured to operate in either the first mode or the second mode.

[0165] In this case, the arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode, and the arbitrary TDC may be configured to receive the termination signal in the first mode.

[0166] In this case, when the termination signal is input to any TDC, the input signal generation unit may generate the input pulse such that the width of the input pulse is the same as the time difference between the rising edge of the start signal and the rising edge of the termination signal.

[0167] In this case, when the arbitrary TDC operates in the first mode, the processing unit calculates the time difference between the start signal and the end signal using one of the codes output by the delay line portion of the arbitrary TDC at the rising edge of the first newly generated clock pulse. Conversely, when the arbitrary TDC operates in the second mode, the processing unit may calculate the time of generation of the start signal.

[0168] Figure 15 is a flowchart illustrating a method for calculating the time difference between a predetermined input start signal and an end signal, as provided by one embodiment of the present invention.

[0169] The method shown in Figure 15 can be performed using a predetermined electronic device. In one preferred embodiment, the electronic device may be an FPGA, but is not limited to an FPGA.

[0170] The electronic device may include a group of TDCs having the same configuration, a clock generation unit that provides a common clock to the group of TDCs, a tag counter that generates a second count, which is a value obtained by counting the clocks, and provides it to the group of TDCs in common, and a processing unit. Each of the TDCs may include an input signal generation unit and a delay line unit.

[0171] The method for calculating the time difference between the start signal and the end signal may include the following steps (S210), (S220), and (S230).

[0172] In step (S210), the input signal generation unit for any TDC among the group of TDCs can generate an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the arbitrary TDC, and a falling edge that occurs at the same time as the end signal input to the arbitrary TDC.

[0173] In step (S220), the delay line portion of the arbitrary TDC can output one of the following codes: the thermometer code of the input pulse and the converted code obtained by converting the thermometer code.

[0174] In step (S230), the processing unit can determine the value of the occurrence time difference by using one of the codes output by the delay line unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, one of the codes output by the delay line unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count unit.

[0175] Figure 16 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0176] The TDC system (1000) may include a PCB board (600) and a computing device (700).

[0177] The PCB board (600) is a device capable of digital signal processing and may include the FPGA (1), data interface (601), signal interface (602), clock generation unit (603), and power supply unit (604) described above.

[0178] The data interface (601) is a device that enables data exchange between the PCB board (600) and the computing device (700), and may consist of, but is not limited to, USB, Ethernet, or UART. The signal interface (602) has the function of receiving signals from an external source that are intended to measure a time difference using the FPGA (1) and transmitting them to the FPGA (1).

[0179] The clock generation unit (603) can provide a train of clock pulses that the FPGA (1) counts.

[0180] The time difference value of the two selected signals calculated by FPGA(1) may be output from FPGA(1) and provided to the data interface (601). The data interface (601) may provide the time difference value of the two signals to the computing device (700).

[0181] The power supply unit (104) supplies power to the PCB board (600).

[0182] The computing device (700) may include a data interface (701), a CPU (702), and memory (703).

[0183] The computing device (700) may be configured to execute a predetermined algorithm based on the time difference between two selected signals received from the PCB board (600). The time difference between the two received signals may be processed by a process executed by the CPU (702). A program consisting of instructions for executing the process may be stored in memory (703). The program may be loaded from memory (703) into the CPU (702) and executed. The memory (703) may be non-volatile memory.

[0184] By utilizing the embodiments of the present invention described above, persons in the art of the present invention will be able to easily implement a variety of changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other unreferenced claims to the extent that can be understood herein.

Claims

1. A group of TDC(100) having the same configuration as each other, A clock generation unit (140) generates a clock and provides the generated clock to the group of TDCs in common, A tag counter (130) generates a second count, which is the value obtained by counting the aforementioned clocks, and provides the generated second count to the group of TDCs in common, Processing unit (160), It is programmed to include, Of the aforementioned group of TDCs, the first TDC is An input signal generation unit (10) generates a first input pulse (P1) having a rising edge that occurs at the same time as the rising edge of the first start signal (S1) input to the first TDC, The delay line section (20) to which the generated first input pulse is input, Includes, The aforementioned processing unit, After the rising edge of the first start signal input to the first TDC occurs, a first value is calculated by multiplying the value of the second count (TC) observed at the time of the first newly generated clock pulse of the clock by the pulse period (CP) of the clock. The FPGA is configured to calculate the generation time of the first start signal by subtracting from the first value the thermometer code output by the delay line portion of the first TDC or a conversion code obtained by converting the thermometer code at the rising edge of the first newly generated clock pulse.

2. The FPGA according to claim 1, The first TDC is configured to operate in either the first mode or the second mode. The first TDC is configured to generate the first input pulse in both the first and second modes. The first TDC is configured to receive the first termination signal in the first mode. When the first termination signal is input to the first TDC, the input signal generation unit generates the first input pulse such that the width of the first input pulse is the same as the time difference between the rising edge of the first start signal and the rising edge of the first termination signal. The aforementioned processing unit, When the first TDC operates in the first mode, the thermometer code output by the delay line portion of the first TDC at the rising edge of the first newly generated clock pulse is used to calculate the time difference between the first start signal and the first end signal. The FPGA is configured to calculate the generation time of the first start signal when the first TDC is operating in the second mode.

3. The FPGA according to claim 2, The first TDC further includes a clock pulse counting unit (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, When the first TDC operates in the first mode, the processing unit shall An FPGA that determines the value of the occurrence time difference by utilizing the thermometer code output by the delay line section at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, the thermometer code output by the delay line section at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count section.

4. The FPGA according to claim 2, Guard1TDC is, A code conversion unit (30) outputs a converted code generated by converting the order of elements of the thermometer code output by the delay line unit, The system further includes a clock pulse counting unit (40) that counts the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, When the first TDC operates in the first mode, the processing unit shall An FPGA that determines the value of the occurrence time difference by utilizing a first thermometer code output by the code conversion unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, a second thermometer code output by the code conversion unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the first input pulse, and the number of clock pulses counted by the clock pulse count unit.

5. The FPGA according to claim 4, The aforementioned conversion code is obtained by arranging the order of the elements of the thermometer code output by the delay line section according to a predetermined standard. The predetermined criterion is the data path delay from the output node of the first input pulse to the output node of each of the multiple flip-flops (FFs) included in the delay line portion of the FPGA.

6. The FPGA according to claim 1, The aforementioned processing unit, The relationship between the first occurrence time, which is the time the first start signal is input to the first TDC among the group of TDCs, and the second occurrence time, which is the time the second start signal is input to the second TDC among the group of TDCs, is determined. An FPGA characterized in that, on the circuit of the FPGA, the tag counter is arranged inside a region (1000) formed by connecting the regions occupied by the group of TDCs.

7. The FPGA according to claim 2, Guard1TDC is, A clock pulse count unit (40) outputs a first count, which is the result of counting the number of clock pulses of the clock that occurred during the maintenance period of the first input pulse, A count selection unit (60) is configured to select and output the first count from the first count and the second count in the first mode, and to select and output the second count from the first count and the second count in the second mode, FPGAs, which further include FPGAs.

8. The FPGA according to claim 2, An FPGA configured such that, if the first termination signal is not input to the first TDC operating in the first mode, the processing unit cancels the first input pulse once it has finished calculating the generation time of the first start signal.

9. A non-volatile recording medium on which program instructions executable by an electronic device are stored, The aforementioned electronic device is The system includes a group of TDCs having the same configuration, a clock generation unit that provides a common clock to the group of TDCs, a tag counter that generates a second count, which is a value obtained by counting the clocks, and provides it to the group of TDCs in common, and a processing unit. Each of the aforementioned TDCs includes an input signal generation unit and a delay line unit, When the aforementioned program instruction is executed by the electronic device, The step of an input signal generation unit for any TDC among the group of TDCs generates an input pulse having a rising edge that occurs at the same time as the rising edge of the start signal input to the arbitrary TDC, The delay line portion of the arbitrary TDC outputs one of the following codes at the rising edge of the first newly generated clock pulse of the clock after the rising edge of the start signal has occurred: the thermometer code of the input pulse and the converted code obtained by converting the thermometer code. The processing unit calculates a first value by multiplying the value of the second count observed at the time of the first newly generated clock pulse of the clock by the pulse period of the clock, and then subtracts one of the output codes from the first value to calculate the generation time of the first start signal. A non-volatile recording medium characterized by the execution of a certain action.

10. A non-volatile recording medium according to claim 9, When the aforementioned program instruction is executed by the electronic device, The aforementioned arbitrary TDC is configured to operate in either the first mode or the second mode. The arbitrary TDC is configured to generate the input pulse in both the first mode and the second mode. The aforementioned arbitrary TDC is configured to receive the termination signal in the first mode. When the termination signal is input to any of the aforementioned TDCs, the input signal generation unit shall The input pulse is generated such that the width of the input pulse is the same as the time difference between the rising edge of the start signal and the rising edge of the end signal. The aforementioned processing unit, When any TDC operates in the first mode, the time difference between the start signal and the end signal is calculated using one of the codes output by the delay line portion of the any TDC at the rising edge of the first newly generated clock pulse. In contrast, a non-volatile recording medium is configured to calculate the time of generation of the start signal when any TDC is operating in the second mode.

11. A non-volatile recording medium according to claim 10, Each of the aforementioned TDCs is, The system further includes a clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse, When the aforementioned program instruction is executed by the electronic device, A non-volatile recording medium, wherein when any TDC operates in the first mode, the processing unit performs the step of determining the value of the occurrence time difference by using one of the codes output by the delay line section at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, one of the codes output by the delay line section at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count section.

12. A non-volatile recording medium according to claim 9, Each of the aforementioned TDCs is, A code conversion unit outputs a converted code generated by converting the order of elements of the thermometer code output by the delay line unit, A clock pulse counting unit that counts the number of clock pulses of the clock that occurred during the maintenance period of the input pulse, It further includes, When the aforementioned program instruction is executed by the electronic device, Non-volatile recording medium, wherein when any TDC operates in the first mode, the processing unit further performs the step of determining the value of the occurrence time difference by using a first thermometer code output by the code conversion unit at the rising edge of the first clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, a second thermometer code output by the code conversion unit at the rising edge of the clock pulse that occurred immediately after the last clock pulse among the clock pulses that occurred during the maintenance period of the input pulse, and the number of clock pulses counted by the clock pulse count unit.

13. A non-volatile recording medium according to claim 9, When the aforementioned program instruction is executed by the electronic device, The processing unit further performs the step of determining the relationship between a first occurrence time, which is the time when the start signal is input to any TDC among the group of TDCs, and a second occurrence time, which is the time when the second start signal is input to another TDC among the group of TDCs. A non-volatile recording medium characterized in that, on the FPGA circuit, the tag counter is arranged within a region formed by connecting the regions occupied by the group of TDCs.

14. A non-volatile recording medium according to claim 9, characterized in that the electronic device is an FPGA.

15. A PCB board (100) including an FPGA (1) according to any one of claims 1 to 8, A computing device (200) that acquires the time difference from the PCB board, The TDC system, including the TDC system.

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