Video wall, driver circuit, drive control circuit, and method relating thereto

Abstract

The objective is to further develop the drive control of a lighting unit equipped with LEDs for changing brightness, so that the brightness of the light emitted by the LEDs can be changed relatively easily, accurately, and reliably. [Solution] The present invention relates to various driver circuits, drive control circuits and arrangement structures for supplying current to loads, particularly light-emitting diodes, display devices and video walls.

Description

[Technical Field]

[0001] This patent application claims priority to the following German applications: German Patent Application Publication No. 102019102509.5 dated January 31, 2019, German Patent Application Publication No. 102019110497.1 dated April 23, 2019, German Patent Application Publication No. 102019115479.0 dated June 7, 2019, and German Patent Application Publication No. 102019112124.8 dated May 9, 2019, the disclosures of which are incorporated herein by reference, and Danish Patent Invention No. 201970061 dated January 29, 2019 (DK This invention claims priority to PA201970061), the disclosure of which is incorporated herein by reference, and also claims priority to International Application PCT / EP2020 / 052191 dated 29 January 2020, the disclosure of which is incorporated herein by reference.

[0002] Background technology Ongoing developments in the fields of the Internet of Things and communications are opening up a variety of new applications and concepts. These concepts and applications enhance effectiveness and efficiency for development, service, and manufacturing purposes.

[0003] The new concept is based on considerations regarding the supply of current or voltage and the driving control of various loads. In many cases, a power source is not secured on the network side, and instead, current is typically supplied by energy storage devices such as batteries, rechargeable batteries, or supercapacitors.

[0004] In the field of display devices or displays, energy supply may not be a major issue at first, but even in this case, minimizing the load on the drive control elements is extremely important. In addition, as large displays themselves become thinner, available space is decreasing, and the waste heat generated must be removed. This applies not only to display devices such as displays or video walls, but also to many other loads.

[0005] overview The following overview describes various methods for driving and controlling large or extra-large displays or screens, particularly video walls. Control circuits and current supply circuits for such devices are described using various embodiments. It should be emphasized that while many embodiments refer to display devices or display arrangement structures, they are not limited to these and are applicable to other loads as well.

[0006] To explore the following solutions, it is necessary to explain several terms and expressions in order to define a common and equivalent understanding. In this document, the terms described are used generally based on this understanding. However, interpretations may differ in individual cases, and in such cases, these differences are made recognizable.

[0007] "Active Matrix Display" The term "active matrix display" was originally used for liquid crystal monitors in which thin-film transistors used to control LCD pixels are arranged in a matrix. Each pixel has a circuit with an active component (mainly a transistor) and a current supply terminal. However, this technology is now applied not only to liquid crystals but also to the drive control circuits of LEDs, displays, or video walls in particular.

[0008] "Active matrix carrier substrate" "Active matrix carrier substrate" or "active matrix backplane" refers to the drive control unit of the light-emitting diodes of a display equipped with a thin-film transistor circuit. In this case, the circuit may be incorporated into the backplane or applied to the backplane. The active matrix carrier substrate has one or more interface contacts that form electrical terminals to the LED display structure. Therefore, an "active matrix carrier substrate" can be a component of an active matrix display or hold an active matrix display.

[0009] "Augmented Reality (AR)" Augmented Reality (AR) is an interactive experience of the real environment, where the visual objects of the real environment are in the real world and are augmented by computer-generated perceptible information. Augmented Reality precisely means the computer-aided augmentation of real perception using this computer-generated perceptible information. This information can correspond to all human sensory modalities. However, Augmented Reality is often understood to be only the visual representation of information, that is, the supplementation of computer-generated additional information or virtual objects to images or videos by fade-in / overlay.

[0010] "Automotive" Automotive generally means the automobile or motor vehicle industry. Therefore, this term should cover not only this sector but also all other industrial sectors including displays or generally very high-resolution light displays and LEDs.

[0011] "Flip-flop" A flip-flop is an electronic circuit in which the output signal has two stable states and is sometimes also called a bistable flip-flop or a bistable multivibrator. In this case, the current state depends not only on the input signal present at that time but also on the state prior to the target time. There is no dependence on time, only dependence on events. Due to this bistability, a flip-flop can store 1 bit of data amount for an unlimited time. However, unlike other storage devices, the power supply circuit must be continuously guaranteed. As a basic component of sequential circuits, flip-flops are essential structural elements in digital technology and thus are basic components of many electronic circuits, from crystal clocks to microprocessors. In particular, as a basic 1-bit memory, it is a basic element of a computer's static memory chip. In some configurations, various types of flip-flops and other buffer circuits can be used to store state information. Each input and output signal is digital, that is, logically "false" and logically "true" alternate repeatedly. These values are also called "low" 0 and "high" 1.

[0012] "Head-up display" A head-up display is a display system or projection device that projects information into the user's field of vision so that the user can maintain the position of the head and the direction of the line of sight. A head-up display is an augmented reality system. A head-up display may be equipped with sensors for determining the direction of the line of sight and the orientation in space.

[0013] "Display" A display, or LED array, is a matrix in which numerous pixels are arranged in defined rows and columns. Functionally, LED arrays often consist of a matrix of LEDs of the same type and color, thus providing a larger illumination area. On the other hand, the purpose of a display is primarily to transmit information, often requiring different colors and addressable drive controls for individual pixels or subpixels. A display can be formed by arranging multiple LED arrays on a backplane or other carrier. However, LED arrays can also form displays.

[0014] A display or LED array can be formed from the same material, i.e., from a single workpiece. The LEDs in an LED array may be formed monolithically. Such a display or LED array is called a monolithic LED array or display.

[0015] Alternatively, two assemblies can be formed by individually growing LEDs on a substrate and then using a so-called pick-and-place process to position them individually or in groups on a carrier at desired intervals from each other. Such displays or LED arrays are called non-monolithic. In non-monolithic displays or LED arrays, other spacings can be provided between individual LEDs. These spacings can be flexibly selected depending on the application and design. Therefore, such displays or LED arrays can also be called pitch-expanded displays or LED arrays. In pitch-expanded displays or LED arrays, this means that when transferred to the carrier, the LEDs are spaced further apart than they were on the growth substrate. In non-monolithic displays or LED arrays, individual pixels may each contain a blue-emitting LED, a green-emitting LED, and a red-emitting LED.

[0016] To leverage the different advantages of monolithic and non-monolithic LED arrays in a single module, displays can be configured by combining monolithic and non-monolithic LED arrays. This allows the display to implement different functions and / or applications. Such displays are called hybrid displays.

[0017] "Photoelectronic structure elements" Optoelectronic structures are semiconductor bodies that generate and emit light through the recombination of charge carriers during operation. The generated light can range from infrared to ultraviolet, and its wavelength depends on various parameters, particularly the material system and doping used. Optoelectronic structures are also known as light-emitting diodes (LEDs).

[0018] For the purposes of this disclosure, the terms optoelectronic structure and light-emitting structure are used synonymously. Therefore, an LED is a special optoelectronic structure in terms of its geometric shape. In displays or video walls, optoelectronic structures typically exist monolithically or as individual elements arranged in a matrix.

[0019] "Passive matrix backplane" or "Passive matrix carrier substrate" A passive matrix display is a matrix display in which individual pixels are passively driven and controlled (without using additional electronic components for each pixel). Light-emitting diodes in a display or video wall can be driven and controlled using IC circuits. In contrast, monitors in which pixels are actively driven and controlled by transistors are called "active matrix displays." A passive matrix carrier substrate is a component of a passive matrix display and holds it in place.

[0020] "Pixels" A pixel, image cell, or image element refers to an area element necessary for acquiring or displaying color values ​​on a screen via an image sensor or raster-driven control, in addition to the individual color values ​​of digital raster graphics. Therefore, a pixel is an addressable element of a display device and has at least one light-emitting device. Pixels have a fixed size, and adjacent pixels are separated by a defined interval (pixel space). In displays or, for example, video walls, a single pixel is often formed by combining three (or four or more, if there is additional redundancy) subpixels of different colors.

[0021] "Prana Array" A planar array is essentially a flat surface. Often, it is smooth and lacks protruding structures. Typically, surface roughness is undesirable and does not provide the desired functionality. A planar array is, for example, a monolithic planar array with several optoelectronic structural elements.

[0022] "Pulse width modulation" Pulse width modulation (PWM) is a type of modulation used to drive and control devices, in this case, LEDs. In this case, the PWM signal controls switches configured to turn the current flowing through each LED on or off, resulting in either the LED emitting light or not. PWM outputs a square wave signal with a constant frequency f. The brightness of the light emitted by the LED is determined by the relative amount of the switch-on time to the switch-off time in each period T (=1 / f). The longer the switch-on time, the brighter the light.

[0023] "Refreshment time" "Refresh time" refers to the time period during which it is necessary to rewrite the information in a display or other display cell to prevent loss of data, or to ensure that the cell is rewritten as required by the external environment.

[0024] "Subpixels" A subpixel (or subpixel) represents the internal structure of a pixel. Typically, the term subpixel is associated with a higher resolution than what might be expected based on an individual pixel. A single pixel can consist of multiple smaller subpixels, each emitting a single color. The overall color impression of a pixel is created by the mixing of individual subpixels. Therefore, a subpixel is the smallest addressable unit in a display device. Similarly, a subpixel contains a fixed size that is smaller than the size of the pixel to which it is assigned.

[0025] "Virtual reality" Virtual reality (VR) is the representation and simultaneous perception of reality and its physical characteristics within a computer-generated, interactive virtual environment. Virtual reality can replace the operator's real environment with an environment that perfectly simulates it.

[0026] From one perspective, this involves the drive control of the light-emitting elements of a display or video wall. Here, on the one hand, it is desirable that the drive control module or supply module used is not too large. On the other hand, in the case of a display or video wall, it is also important to utilize existing space as efficiently as possible without significantly reducing output. Scalability can reduce technical requirements.

[0027] Conventional approaches and technologies may be limited in scope for various reasons. Therefore, the following aspects and various concepts address the challenges mentioned.

[0028] For example, a driver circuit providing a frame rate of 60Hz to 240Hz may also be appropriate. In this regard, particularly in video walls or other display devices, it is necessary to achieve, or at least to meet the purpose, a large luminance dynamic range (1:100,000) or 100dB per individual pixel. This range is necessary, for example, in areas of a video wall affected by ambient light, to ensure sufficient image contrast and brightness even when the effects of ambient light vary. The same applies to the automotive sector.

[0029] In the case of monolithic arrays, digitally generated pulse width modulation (PWM) is considered suitable. Accordingly, it is desirable that this technique be scalable with respect to both the size of the pixel array and the process node of the CMOS technology. Furthermore, digitally generated PWM can compensate for non-uniformity in both the pixel array and the pixel current. Since digital nonlinear PWM can process digital codes, the pulse width can be generated by a nonlinear transfer function of the code to the pulse width. Various concepts are presented below, which are suitable for implementation in monolithic displays or pixelated arrays with LEDs due to their scalability.

[0030] Typically, in pulse-width modulation (PWM) implementations, a standard pixel cell circuit is switched between "off" and "rated current" very quickly. For this reason, conventional circuits have employed a so-called 2T1C circuit. However, especially in displays with a large number of rows and columns, programming becomes very frequent to ensure a sufficient "refresh rate" for the display. Traditionally, this problem was solved with a second transistor, but this adds space, generates more heat, or increases the risk of failure. Space can be particularly limited in the video wall or "below" LED space presented herein. Furthermore, depending on the wiring (i.e., the position of the LED within the current path), accuracy can be higher and intensity can vary. Therefore, a back-gated LED current driver element that mitigates these problems is presented below.

[0031] According to embodiments described herein, a device for electronically driving and controlling an LED is proposed, having a data signal line, a threshold line, and a select signal line. Furthermore, an LED is intended to be electrically connected in series with a dual-gate transistor and connected together between a first potential terminal and a second potential terminal. The threshold line is connected to the first control gate of the dual-gate transistor. Similarly, the device has a select-hold circuit with a charge storage unit, which is connected to the second control gate of the dual-gate transistor and to a control transistor having a control terminal connected to the current line contacts of the dual-gate transistor and also connected to the select signal line.

[0032] Therefore, instead of adding a transistor for pulse width modulation (PWM), it is possible to modulate the control gate of the additional dual-gate transistor with the PWM signal using the existing drive transistor.

[0033] Similarly, according to a second embodiment, a device is proposed in which an LED and a dual-gate transistor are arranged in series in the current path. Through a select-hold circuit, the LED's color is controlled by applying an analog data-driven control signal to one side of the dual-gate transistor using the select signal. The brightness of the LED is controlled by taking in a pulse-width modulated signal on the other side of the dual-gate transistor.

[0034] Advantageously, back-gate transistors can be used as dual-gate transistors.

[0035] Similarly, by using the modulation of the back gate of the drive transistor as an actuator for the current control path and feeding back a feedback signal, such as the forward voltage of the light-emitting diode, negative current feedback against the temperature drift of the light-emitting diode can be achieved. By modulating the voltage of the back gate of the drive transistor, the current of the light-emitting diode can be easily and compactly pulse-width modulated, especially in TFT (thin-film transistor) pixel cells. In the case of an RGB cell, three power transistors can be saved.

[0036] By applying low modulation to the back gate voltage, the current flowing through the LED can be made independent of the LED temperature. This is particularly effective when using an NMOS cell, where the cathode is shared and the LED is on the low side of the driver transistor. Since such cells inherently have poor current accuracy, the concept of this invention can significantly improve such cells.

[0037] This allows pulse width modulation to be performed via the back gate of the main transistor, instead of through an additional transistor in addition to the main transistor. On the other hand, using a back gate transistor in a display or video wall allows for temperature stabilization by operating the back gate with an analog voltage rather than "digitally" with pulse width modulation. This is because the forward voltage V of the light-emitting diode f This is derived from the following and is used as a feedback loop for regulation. This temperature stabilization improves the color accuracy and stability of the LEDs.

[0038] In some embodiments, the dual-gate transistor includes a back-gate transistor, in which case the back-gate forms the first control gate. This is a compact configuration. The dual-gate transistor can be formed as a thin-film transistor having two opposing control gates. This allows for reliable and compact manufacturing. The first control gate of the dual-gate transistor may be configured to adjust the threshold voltage. Modulation can be performed in this way. Alternatively, a switching signal (PWM signal) can be applied to the operating first control gate. In this way, simple brightness control can be performed.

[0039] In another embodiment, the LED may have its first terminal connected to a first potential terminal, and the dual-gate transistor may have its current line contacts positioned between the LED's second terminal and the second potential terminal. The select-hold circuit may include a charge storage unit connected to the LED's second terminal in addition to the second control gate of the dual-gate transistor. This configuration can be easily manufactured using NMOS technology.

[0040] In another embodiment, the LED may have its first terminal connected to the second current line contact of the dual-gate transistor, and its second terminal may be connected to the second potential terminal. The dual-gate transistor's current line contact is connected between the LED's first terminal and the first potential terminal. The charge storage unit of the select-hold circuit is connected to the first potential terminal in addition to the second control gate of the dual-gate transistor. Therefore, the forward voltage of the light-emitting diode does not affect the gate-source voltage of the dual-gate transistor.

[0041] In another embodiment, the realization of P-Mos technology is involved. In this, the LED has its first terminal connected to a first potential terminal, and the dual-gate transistor has its current line contacts connected between the LED's second terminal and the second potential terminal. The select-hold circuit may be connected to the second potential terminal in addition to the charge storage section with the second control gate of the dual-gate transistor.

[0042] In a further embodiment, the select-hold circuit may include an additional control transistor connected in parallel with the LED, the control terminal of which may be connected to the select signal line.

[0043] In a further configuration, the charge storage unit may be connected not only to the second control gate of the dual-gate transistor but also to the first potential terminal, and further, a temperature compensation circuit that provides negative feedback based on the detection of the forward voltage by an LED may be included, and this temperature compensation circuit may form the threshold line on the output side. In this way, a low modulation can be applied to the back-gate transistor.

[0044] In some embodiments, the temperature compensation circuit may include a control path which may be juxtaposed with the dual-gate transistor and may have two paths connected in series. This is a simple configuration. In a further configuration, a threshold line may be connected to the first control gate of the dual-gate transistor from a node between the two controlled paths provided by a third control transistor and a fourth control transistor. This node can be used to effectively drive and control the back gate. In a further configuration, the control terminal of the fourth control transistor may be connected to a second potential terminal. In this way, the gate of the transistor is stably set to the high potential of the second potential terminal.

[0045] In other embodiments, the temperature compensation circuit may include a second charge storage unit which may be connected to a first potential terminal and to a control terminal of one of the control transistors providing two paths. This allows the gate voltage of the third transistor to be buffered.

[0046] A second data signal line is coupled to a second charge storage unit and a third control transistor. The signal on this line may be configured to program the negative feedback coefficient. Therefore, the second data signal line can also be used to fine-tune the temperature compensation. This fine-tuning can be switched on or off using a further control transistor, depending on the application.

[0047] In another advantageous configuration, the control terminal of the third control transistor may be connected to the second potential terminal in the temperature compensation circuit. In this way, the gate voltage of the third control transistor is advantageously defined clearly and stably.

[0048] In a more advantageous configuration, a fifth control transistor may be connected in parallel with the LED, and a switching signal (PWM signal) is applied to its control terminal during operation. In this way, the light-emitting diode can be turned on / off directly, particularly by pulse width modulation, without a charge storage unit. This dual-gate transistor operates as a temperature-regulated current source.

[0049] Drive control for adjusting pixel brightness or dimming is also important. Such dimming may be necessary, for example, to allow a video wall to switch between daytime and nighttime viewing. In principle, such dimming can be convenient and advantageous when contrast needs to be adjusted, or when it is necessary to regulate the brightness of a display or video wall to prevent external light from dazzling the user's eyes or to display information safely.

[0050] For the reasons mentioned above, various technical solutions are known for driving and controlling lighting units equipped with LEDs, particularly to operate displays or video walls at different brightness levels. For example, control circuits are known for controlling matrix displays that specifically drive and control a series of individual pixels formed in multiple rows and columns. Similarly, drive control means are known for specifically reducing or attenuating the current to LEDs. This so-called current dimming is used, for example, in liquid crystal displays or OLED displays.

[0051] Implementing a solution with a large number of components in the limited space behind an LED is difficult. This can, in some cases, make the circuit extremely complex. Based on this, the following embodiments aim to further develop the drive control of a lighting unit equipped with an LED for changing brightness, so that the brightness of the light emitted by the LED can be changed relatively easily, accurately, and reliably. In particular, the aim is to enable operation in the aforementioned dimming, or in stages of brightness and contrast.

[0052] Therefore, a control circuit for changing the brightness of a lighting unit has been proposed, comprising a voltage source for supplying electrical energy to the lighting unit and at least one energy storage medium. The latter sets the current for the lighting means of the lighting unit. Furthermore, a control element is provided that temporarily changes the voltage of the voltage signal generated by the voltage source, thereby adjusting the LED current flowing to at least one LED. According to the proposed principle, the control circuit is further set so that the control element transmits first and second voltage signals having different voltages to the lighting unit during one cycle, i.e., during the repeating period, and adjusts the brightness level according to the voltage of the first voltage signal, thereby causing the lighting unit to operate at at least two different brightness levels.

[0053] Therefore, in this concept, it is important that a pulsed voltage signal is applied to the lighting unit, and that current flows to at least one LED in the lighting unit in response to the voltage signal, causing the LED to emit light. In this regard, during one cycle, a first voltage signal, in particular a turn-on voltage signal, and a second voltage signal, in particular a turn-off voltage signal, are provided in an advantageous manner, and at least one LED in the lighting unit is supplied with a current proportional to the voltage, or a current proportional to the voltage flows through it, while the first voltage signal is applied. In principle, it is irrelevant here whether the lighting unit has one LED or multiple LEDs. In one embodiment, the switching element has a transistor, through which electrical energy is supplied to at least one LED in the lighting unit in response to the respective voltage signals, causing a current to flow through the LED, which advantageously emits visible light.

[0054] According to the concept, the lighting unit is driven and controlled so that, during one cycle, a first voltage signal is first transmitted to the lighting unit at the first stage of that period, followed by a second voltage signal at the second stage of that period, and the current flow through at least one LED of the lighting unit acts according to the voltage of each voltage signal. Crucially, the voltage or value of the second voltage signal is significantly lower than the voltage of the first voltage signal. Advantageously, the voltage of the second voltage signal is at least close to zero.

[0055] The proposed concept allows for setting different brightness ranges depending on the application, and the brightness itself can be adjusted within each range. This makes it possible to adapt to changing lighting conditions, for example, in video walls or the automotive field, without requiring significant additional circuitry work.

[0056] During the first stage of the period in which a first voltage signal is transmitted to the lighting unit, the energy storage medium of the lighting unit is charged. At the same time, a current with a magnitude proportional to the voltage of the voltage signal flows through the LED, and as a result, the LED emits visible light. During the second stage of the period, while a second voltage signal is transmitted to the lighting unit, the potential of the energy storage medium, preferably a capacitor, is maintained, so that a current based on this flows through the LED until the start of the next period, and as a result, the LED emits further light. Theoretically, the magnitude of the current flowing through the LED during the first stage of the period should be equal to the magnitude of the current flowing through the LED during the second period, but in practice this is not the case. This is because the control circuit usually has a second capacitance in addition to the capacitance of the energy storage medium, especially a capacitor, and thus a capacitive voltage divider is created such that the voltage across the energy storage medium during the second stage of the period is lower than the voltage during the first stage of the period. Such a second capacitance is provided, for example, by the capacitance of a transistor, especially the gate-source capacitance.

[0057] In this regard, it is crucial that the magnitude of the current flowing through the LED during the first phase of the period when the first voltage signal is transmitted to the lighting unit is different from, or smaller than, the magnitude of the current flowing through the LED during the second phase of the period when the second voltage signal is transmitted to the lighting unit. However, the viewer does not perceive this difference, which is the difference in the maximum brightness of the LED during one cycle, but only perceives the light output averaged over the period.

[0058] To effectively utilize this effect, for example, in the drive control of a lighting unit used in a display, it is advantageous to repeat the first and second voltage signals at a frequency of 60 Hz, which corresponds to the normal refresh rate of the display. In other words, the first and second voltage signals are each transmitted to the lighting unit 60 times within one second, and LED current flows to at least one LED in the lighting unit according to the voltage of each voltage signal.

[0059] In another embodiment, it is provided that while a second voltage signal is being transmitted to the lighting unit, the electrical energy necessary to excite light emission is supplied to the LED from an energy storage medium formed as a capacitor. Because the voltage across the capacitor is lower than in the first stage during that period, a smaller current flows through the LED in this operating state compared to the first stage during that period, resulting in a weaker LED brightness.

[0060] Furthermore, in this method, the control element is set to generate the first voltage signal with a duty cycle of 0.0025 to 0.003, where this duty cycle corresponds to the ratio of the duration of the first voltage signal to the duration of the period. Thus, the duty cycle represents the ratio of the duration of the first voltage signal to the duration of the period. Since the refresh rates of the first and second voltage signals are 60 Hz, this means that the control element in this configuration is set so that the period during which the first and second voltage signals are transmitted to the lighting unit is 0.0166 seconds or 16.6 milliseconds. In a preferred evolution, the first voltage signal is transmitted to the lighting unit for a period of up to 0.050 milliseconds, which corresponds to a duty cycle of approximately 0.003 or 1:333. In this case, the second voltage signal is transmitted to the lighting unit for a period of 16.6 milliseconds. Therefore, the duty cycle for this signal is approximately 1.

[0061] The brightness of an LED perceived by a viewer depends on the average luminance or light output emitted during one cycle. Therefore, the current flowing through the LED during the second stage of a cycle, and consequently the proportion of light emitted by at least one LED during the second relatively long stage of that period, will have a large and disproportionately strong effect on the average light output of the LEDs in the lighting unit.

[0062] In some embodiments, the control circuit may be configured to operate the lighting unit at a first dim brightness level by adjusting the voltage of a first voltage signal to a voltage value within a first voltage interval, and to operate the lighting unit at at least a second bright brightness level by adjusting the voltage of the first voltage signal to a voltage value within at least a second voltage interval that is higher than the voltage of the first voltage interval. Thus, according to this configuration, two voltage intervals or voltage ranges are provided for the drive control of the lighting unit, each of which has a different voltage that generates the first voltage signal and is at a different voltage level. In this way, depending on the voltage level of the first voltage signal, the lighting unit operates at either a first dim brightness level or a second bright brightness level. If it is desired to operate the lighting unit at a brighter brightness level, the drive control of the lighting unit is performed based on the first voltage signal, the voltage of which is in the second voltage interval, and by extension, a voltage interval with a higher value.

[0063] In other embodiments, the control element is set to operate the lighting unit at the same brightness level when the voltage of a first voltage signal is specifically changed within one of at least two predetermined voltage intervals. That is, in an advantageous manner, the first voltage signal, and in particular its voltage, ensures that the lighting unit operates at the same brightness level even if the corresponding voltage changes only to a certain extent within the same voltage interval between two consecutive periods, and the brightness changes only slightly. Thus, it is possible to dim the lighting unit, and in particular at least one LED provided within the lighting unit, at at least two different brightness levels, that is, to provide at least a largely stepless range in which the brightness of at least one LED of the lighting unit is specifically changed in each of at least two different brightness levels.

[0064] In a further configuration, the first voltage interval or first voltage range is intended to have voltage values ​​in the range of at least 1.3V to 3.0V. Furthermore, preferably, the second voltage interval or second voltage range is intended to have voltage values ​​in the range of at least 4.0V to 10.0V. In this way, two ranges with different levels of brightness are realized, and the brightness of the lighting unit can again be specifically and continuously changed or dimmed within that range.

[0065] Regarding the configuration described above, as soon as a relatively small first voltage signal is applied to the lighting unit, we can reconsider the idea that the total current flowing through the LED during one cycle is deterministically determined by the current flowing through the LED during the first stage of the period in which the first voltage signal is applied to the lighting unit. In this case, the lighting unit operates at a relatively low brightness, and in this operating state, the light emission due to the current flowing through the LED by the second voltage signal applied to the lighting unit during the second stage of that period can be ignored.

[0066] On the other hand, when a relatively high voltage first voltage signal is transmitted to the lighting unit, the total current flowing through the LED during one cycle is deterministically determined by the current flowing through the LED during the second stage, i.e., while the second voltage signal is applied to the lighting unit. In this case, the lighting unit operates at a high brightness level, and dimming is possible within this range by specifically changing the first voltage signal.

[0067] The presented control circuit can be used in displays, monitors, or, for example, video walls for generating images. These could be part of a larger screen or display device, for example, in an automobile. Implementation in AR or VR glasses or other devices is also conceivable. Here again, a drive control means capable of operating the display, monitor, or, for example, video wall at at least two different brightness levels is important.

[0068] In addition to specially formed drive control circuits, several embodiments relate to a method for specifically changing the brightness of a lighting unit, wherein a voltage source supplies electrical energy to the lighting unit, and at least temporarily electrical energy is supplied from the energy storage medium of the lighting unit to at least one LED as a means of illumination of the lighting unit. Furthermore, this method involves transmitting a voltage signal to the lighting unit at least temporarily and adjusting the LED current flowing to at least one LED based on that voltage signal.

[0069] This method is characterized by operating the lighting unit at at least two different brightness levels by transmitting first and second voltage signals having different voltages to the lighting unit during one cycle and adjusting the brightness level according to the voltage of the first voltage signal. Furthermore, in this invention, it is possible to specifically change the brightness of an LED, which is deterministically determined by the total current flowing through at least one LED during one cycle, by transmitting a first voltage signal to the lighting unit at the first stage of that period. Since the first voltage signal is applied to the lighting unit at the first stage of that period for driving control of the lighting unit, first, while the first voltage signal is applied to the lighting unit, the energy storage means of the lighting unit is charged and a current proportional to the voltage of the voltage signal flows through at least one LED of the lighting unit. At the second stage of that period, a second voltage signal having a voltage significantly lower than the voltage of the first voltage signal, preferably close to zero, is transmitted to the lighting unit. As a result, the potential of the energy storage means, particularly the capacitor, decreases, and consequently, the magnitude of the current flowing through the LED also decreases.

[0070] Therefore, the brightness of the LED weakens in the second stage compared to the first stage of the period, but it continues to glow for a relatively long period. Here, depending on the voltage level of the first voltage signal, the lighting unit can be operated at a high brightness level with a relatively high average light output, or at a low brightness level with a relatively low average light output. In this regard, it is necessary to consider that in the case of a first voltage signal with a relatively low voltage value, the first stage of the period has a relatively large impact on the average light output of the LED, and in the case of a first voltage signal with a high voltage value, the second stage of the period in which the second voltage signal is applied to the lighting unit is critically important for the average light output of the LED.

[0071] In this way, while the second voltage signal is applied to the lighting unit, the LEDs of the lighting unit are provided with electrical energy from an energy storage means configured as a capacitor. In other words, it is advantageous to set the voltage of the first voltage signal to a voltage value within a first voltage interval to operate the lighting unit at least temporarily at a first dim brightness level, and to set the voltage of the first voltage signal to a voltage value within a second voltage interval that is higher than the voltage of the first voltage interval to operate the lighting unit at least temporarily at a second bright brightness level.

[0072] In one configuration, the voltage of a first voltage signal is varied between two consecutive periods without changing the brightness level at which the lighting unit operates. Thus, even when the LED operates at a constant brightness, variations occur in the average light output. As a result, between two consecutive periods, the voltage of the first voltage signal varies within a voltage interval or range provided for the corresponding brightness level.

[0073] In addition to temperature stability and drift in the input voltage or current to the diode due to process variations, the pulse modulation used must also be considered. In current displays, light-emitting diodes (LEDs) typically operate using pulse width modulation, meaning they are switched on and off in rapid succession for contrast and brightness adjustment. The frequency used is in the range of several hundred kHz to MHz. This switching process has a negative effect on the current source, which can impair its accuracy and stability. If a control loop is used within the current source, the switching process can cause spikes and other behaviors, causing the control loop to fall outside its control range.

[0074] Based on these considerations, a tuned current source for LEDs is proposed that controls the current source so that the output current maintains a controlled state and follows a setpoint during PWM modulation, particularly during the switching process. This current source, and especially the feedback loop, is suitable for all types of loads and is not limited to those disclosed herein.

[0075] For this purpose, the output current or a signal derived therefrom is supplied to the control loop, which compares it to a setpoint. Furthermore, when the current source is turned off or operated in on / off mode (intermittent operation), a backup signal is supplied to the control loop while the output current is off. The backup signal maintains the control loop within the modulation range (Aussteuerbereich). It is preferable that the backup signal corresponds to or is similar to the expected output current or a signal derived therefrom. In general, this allows for continuous regulation of the modulation range, independent of the switching state of the current source. The accuracy and stability of the supply circuit are maintained.

[0076] One configuration proposes a supply circuit equipped with an error correction detector having a reference signal input, an error signal input, and a correction signal output. Furthermore, a controllable current source having a current output and a control signal terminal is provided. The control signal terminal is connected to the correction signal output to form a control loop for the controllable current source. In other words, the error correction detector controls the output current of the current source within a certain range. Thus, the current source is configured to supply current to the current output in response to a signal at the control signal terminal.

[0077] According to the proposed principle, the supply circuit includes a backup source having an output configured to supply a backup signal. Finally, a switching device is operably connected to a controllable current source and an error correction detector, and the switching device is configured to supply to the error signal input either a signal derived from the current at the current output or a backup signal further isolated from the current output of the current source, depending on the switching signal. In other words, the switching device is coupled to the controllable current source and the error correction detector and is adapted to supply either a signal derived from the current at the current output or a backup signal at the error signal input. Furthermore, the switching device is configured to de-energize the current output in the latter case.

[0078] This creates a configuration that keeps the control loop within the modulation range, regardless of the operating state of the current source. As a result, the current source can operate in intermittent modes such as PWM, in addition to regulation by the control loop and error correction detector.

[0079] It is advantageous that the backup signal substantially corresponds to the signal derived from the current signal. In this way, the control loop and especially the error correction detector are supplied with a signal that is almost identical to the signal from the current source, so that regulation and modulation are maintained.

[0080] In one embodiment, a controllable current source has a current mirror having a switchable output branch, which is connected to or forms a current output. The output branch may include one or more output transistors having a control terminal or gate connected to the control terminal of a current mirror transistor located on the input side.

[0081] In another embodiment, the output transistor of an output branch has its control terminal connected to a switching device. The switching device is configured to either connect to a fixed potential to open the output transistor, or connect its control terminal to the control terminal of a current mirror transistor located on the input side, depending on the switching signal of the output transistor. When the control terminal is at the fixed potential, the output transistor is opened or closed, i.e., no longer conducts current, and the output of the load and supply circuit is de-energized.

[0082] In other embodiments, the switching device is located in the output branch and configured to isolate the current output or output transistor from the load. In this embodiment, a tap for the error signal input of an error correction detector is located between the switching device and the load.

[0083] In another embodiment, the controllable current source has an input branch. A reference current signal can be supplied to the input branch, and the current source provides an output current dependent on it. The input branch of the controllable current source further includes a node connected to the reference signal input of an error correction detector. Thus, for example, the reference current supplied to the current source to draw the output current also functions as the reference signal for the error correction detector.

[0084] Furthermore, the controllable current source may include a current mirror, and the control signal terminal is connected to the control terminal of the current mirror's output transistor. This allows the current flowing through the output transistor to be changed by the control signal, thereby performing regulation. The coupling between the control terminal of the current mirror's output transistor and the current mirror transistor of the current mirror is performed by positive feedback using a capacitor. This capacitor is used for frequency compensation and improves the stability of the regulation.

[0085] Another embodiment relates to a differential amplifier, which may include a differential amplifier in which two branches are connected to a supply potential via a current mirror. Optionally, the two branches of the differential amplifier may each contain an input transistor having different geometric parameters. In conjunction with the current mirror, different fixed coefficients between the reference signal and the error signal can be taken into account.

[0086] In another embodiment, the backup source includes a voltage generating element coupled to its output such that the backup signal substantially corresponds to a signal derived from the current signal. This allows the backup signal to simulate the current flowing through the load during normal operation, keeping the control loop in the modulation region.

[0087] The backup source may have a series circuit consisting of a current supply element and a voltage supply element, with the output located between the two elements. Similarly, in another embodiment, the backup source may include a transistor having a control terminal connected to the control terminal of a current mirror transistor of the current source.

[0088] Another embodiment relates to a switching device having one or more transmission gates. The supply circuit may include a reference current mirror configured to supply a current defined on the input side to an error correction detector on the output side and to a current source.

[0089] Another aspect concerns the use of a supply circuit for supplying current to an LED. This is operated by a supply circuit, specifically in an on / off manner; that is, the LED is operated with a pulse-width modulated signal of the current supply circuit. While this operation is not uncommon in optoelectronic devices, the supply circuit generates a stable and accurate output current during this pulse-width modulation operation.

[0090] Another aspect relates to a method of supplying power to an LED. Here, the supply current is detected by the load. This can be done by detecting the current flowing through the LED. Alternatively, a signal can be derived from a current that has a known relationship with the current flowing through the load. The supply current or the signal derived therefrom is compared with a reference signal, and a corrected signal is generated from the comparison result. If necessary, the corrected signal is used to adjust the supply current flowing through the load to a target value.

[0091] Furthermore, the system is provided with the option to turn off the load at regular intervals, i.e., disconnect it from the supply current. In such cases, a backup signal is generated and used in the comparison step instead of the signal derived from the supply current. In other words, instead of the supply current or the signal derived therefrom, the backup signal is compared with the reference signal, and a corrected signal is generated from this comparison. This allows for regulation, for the time being, regardless of whether current is being supplied to the load. In this case, the backup signal substantially corresponds to the supply current flowing through the load or the signal derived therefrom.

[0092] Another aspect involves realizing a driver circuit that can drive a large number of optoelectronic structural elements, particularly LEDs, with low self-power consumption.

[0093] In a first aspect of the present application, a driver circuit is provided for driving or controlling a plurality of optoelectronic structural elements. The optoelectronic structural elements are configured as LEDs and arranged in an array having rows and columns to form, for example, a video wall. Each LED represents one pixel. Alternatively, if each pixel includes a plurality of subpixels, for example three subpixels, each LED may form one of the subpixels.

[0094] The driver circuit includes multiple first memory cells, each of which is assigned to one of the LEDs. Furthermore, each memory cell has two inputs, called a set input and a reset input, and one output. The first memory cells may be latches or may be configured as 1-bit memory. Each first memory cell may have two distinct states at its output, a first state and a second state, where the first state is high and the second state is low.

[0095] A set signal received from one of the first memory cells via the set input triggers the first memory cell at the output to a first state. The first memory cell retains the first state until it is reset to a second state by a reset signal received at the reset input. The output of each first memory cell, in particular the output signal provided to the output, is configured to control or drive one of the respective LEDs. Specifically, the output signal determines whether the LED is turned on and emits light, or turned off and does not emit light.

[0096] CMOS technology is particularly suitable for manufacturing the driver circuit, the first memory cell, and its associated circuits. The driver circuit according to the first embodiment is a digital driver circuit, which has lower power consumption and a smaller area compared to conventional driver circuits. Furthermore, the driver circuit according to the first embodiment provides better linearity. Each first memory cell can be supplied with a pulse-width modulation (PWM) signal to its output.

[0097] In one configuration, each first memory cell contains two cross-coupled NOR gates or two cross-coupled NAND gates. Each NOR gate or NAND gate has two inputs and one output. The output of each NOR gate or NAND gate is coupled to one input of the other NOR gate or NAND gate. One input of the NOR gate or NAND gate receives a set signal, and the other input of the NOR gate or NAND gate receives a reset signal.

[0098] In an alternative configuration, each first memory cell includes an N-type metal oxide semiconductor transistor (NMOS transistor) and a P-type metal oxide semiconductor transistor (PMOS transistor) connected in series, meaning the channels of the two transistors are connected in series. Furthermore, an inverter input is connected between the NMOS and PMOS transistors, and the inverter output is connected to the gates of the NMOS and PMOS transistors. The driver circuit may include multiple readable counters, each configured to activate a set signal to turn on the current flowing through its respective LED when data such as a pulse width value is read into it. The counters count until the current value reaches the loaded data value. The counters then activate a reset signal, turning off the current flowing through its respective LED.

[0099] If the LED array is arranged in N columns of pixels, the driver circuit may include N counters that simultaneously generate PWM signals for N columns of pixels for each selected row. Furthermore, the driver circuit may include a single common counter configured to generate a common or global dimming signal for multiple LEDs.

[0100] To gate dark pixels, the driver circuit may include multiple second memory cells. Each second memory cell may be coupled to its respective first memory cell and configured to override the output signal of its respective first memory cell as needed, so that its respective LED remains off. In other words, the second memory cells prevent each first memory cell from turning on its respective LED when these optoelectronic structures display dark pixels in a frame.

[0101] An optoelectronic device, display, or video wall according to a second aspect of the present application includes, as described above, a plurality of LEDs and a driver circuit for driving the plurality of LEDs according to the first aspect. The LEDs may be arranged in an array to form a display or a part of a display. Each LED may form a pixel of the array, or each LED may form a sub-pixel. For example, in the case of an RGB pixel array, one pixel includes three optoelectronic elements or LEDs that emit red, green, or blue light. Alternatively, at least two of the three LEDs may emit light of the same color, and a conversion material may be intended to convert that light.

[0102] The LED may be placed on top of an integrated circuit (IC) located beneath it. The circuit may be formed from different material systems.

[0103] A third aspect provides a method for operating an optoelectronic device, display, or video wall according to the second aspect. At the start of a frame, a global reset is performed, the pixel current is turned off, and all optoelectronic elements are turned off. Next, dark pixels are read out one row at a time. In this way, the optoelectronic elements that darken during a frame are controlled by the second memory cell. Subsequently, a line-by-line content-dependent PWM, such as a grayscale PWM, is performed. In this way, the current flowing through the optoelectronic elements is controlled by the first memory cell.

[0104] Furthermore, after a global reset at the start of a frame, the pixel current may remain off until common or global dimming begins. Common dimming of the photoelectronic structure elements may be performed before the current flowing through the photoelectronic structure elements is controlled by the first memory cell. The global dimming data may be combined with grayscale data in the video / image signal processing IC or LED driver IC so as to update only the grayscale data row by row without requiring a separate global dimming pulse. The photoelectronic device according to the second embodiment and the method according to the third embodiment may include the configurations disclosed above in relation to the driver circuit according to the first embodiment.

[0105] For example, a novel concept for driving and controlling loads for pixels, particularly light-emitting diodes, is based on analog lamps for controlling light. In control circuits of display matrices, such as video walls, where multiple optoelectronic structures are arranged in rows and columns, pulse width modulation can be used to set the on / off operation of each pixel. The principle appears similar to conventional pulse width modulation methods, but the implementation is different.

[0106] The control circuitry of a matrix display, particularly an LED matrix display such as a video wall, includes a row select input for row select signals, a column data input for data signals, a ramp signal input for ramp signals, and a trigger input for trigger signals. For illustrative purposes, a ramp signal is a signal that changes over time from a first value to a second value. Typically, ramp signals are periodic. The circuit includes a column data buffer configured to buffer the data signals in response to the row select signals. In some variations, the level of the column data signals may correspond to the brightness of the light-emitting devices. A pulse generator is coupled to the column data buffer and the ramp signal input and configured to supply a buffered output signal for controlling the on / off ratio of at least one of the multiple light-emitting devices in response to the trigger signal, data signal, and ramp signal.

[0107] The proposed principle implements an analog pulse generator. Since the ramp signal can be multiplexed both spatially and temporally, artifacts caused by the activation of different pixels can be suppressed. Furthermore, due to temporal multiplexing, when a ramp signal is used, the switching behavior of the pixels differs. In other words, the LEDs corresponding to the pixels switch at different timings, resulting in a more uniform power distribution and preventing current peaks.

[0108] In some variations, the pulse generator includes a comparator device that compares a buffered data signal with a ramp signal. The result is fed into an output buffer coupled to the comparator's output and trigger input, and in such a configuration, the column data buffer can function as an input buffer. Combined with the pulse generator's output buffer, this achieves double buffering, which allows the circuit to be implemented in displays using longer duty cycles, reducing refresh rates, etc. Generally, this concept further reduces power consumption, which is preferred in augmented reality applications.

[0109] The output buffer may include a single memory stage, such as a flip-flop. In some modifications, the buffer may include an RS flip-flop with an input coupled to the output of a comparator device and, correspondingly, to a trigger input. In this regard, depending on the current implementation and the sign (positive or negative) of the corresponding data and trigger signals, the inverting input of the corresponding flip-flop may also be used. In some modifications, the column data buffer includes a capacitor that stores the data signal and a switch placed between the capacitor and the column data input. The capacitor has a small capacitance such that the input buffer is subjected to a voltage signal on the order of a few volts, and the comparator device has a very high input impedance. The comparator may be implemented using a differential amplifier. For example, the inverting input of the comparator may be coupled to the data column buffer, and its non-inverting input may be coupled to the ramp signal input.

[0110] Depending on the implementation, LEDs coupled to a control circuit may only operate for short periods. In some modifications, LEDs may operate for only about 50% of a normal cycle. In such cases, it is useful to be able to deactivate parts of the control circuit that are not needed. For this purpose, the comparator device may have a power control input coupled to the trigger input to adjust its power consumption based on a trigger signal. Alternatively, the comparator device may be coupled to an output buffer, and its power consumption may be controlled based on the output state of the output buffer. In this regard, the output buffer may be configured to maintain its output state independently of the input coupled to the comparator device until it is reset or triggered by a trigger signal.

[0111] Another aspect relates to the generation of ramp signals. In some modifications, the control circuit includes a ramp generator that supplies ramp signals to a ramp signal input, and the ramp generator is configured to generate a signal that fluctuates between a start value and an end value in response to a trigger signal. The ramp generator may be implemented as a global ramp generator that sends ramp signals common to various other control circuits. Alternatively, multiple ramp generators can be provided, with each ramp generator driving and controlling multiple rows and their respective pixels. Such an implementation allows for temporary multiplexing of ramp signals, thereby reducing artifacts. Furthermore, the ramp signals supplied from the ramp generators can be multiplexed before being applied to the ramp signal input.

[0112] Another aspect relates to a method for controlling the illumination of light-emitting devices in a matrix display having multiple light-emitting devices arranged in addressable rows and columns. According to the proposed principle, the method includes supplying a trigger signal and a data signal to a selected column and at least one light-emitting device. In this case, the level of the data signal is converted into a pulse with respect to the trigger signal. More specifically, in some modifications, the level of the data signal is converted into a pulse width relative to the trigger signal. This pulse is used to pulsely control the on / off state of the light-emitting device.

[0113] In some embodiments, converting the level of a data signal involves generating a ramp signal between a first value and a second value. The data signal is compared to the ramp signal to generate a state signal. The state signal may be a digital signal. In this case, the pulse signal is based on a trigger signal and a change in the state signal. In effect, the pulse signal is set or reset from HIGH to LOW in response to a change in the state signal between LOW and HIGH. Of course, this principle of "setting the value" and "resetting the value" is interchangeable.

[0114] The ramp signal can be generated or initiated in response to a trigger signal. In some modifications, both signals may be derived from a common signal. The supply of the data signal may, in some modifications, include pre-buffering of the data signal. For example, the data signal may be pre-buffered in a memory device such as a capacitor.

[0115] In other embodiments, redundant LED branches with select fuses are used to correct LED defects that occur during the fabrication of displays, particularly video walls, or display modules.

[0116] In displays, especially video walls, LEDs can fail during manufacturing. This can be caused by improper installation or, in the case of monolithic display modules, defects in one of the layers. There are essentially two variations of such defects: one where the contacts are exposed (called "Open"), and another where the anode and cathode are short-circuited (called "Short"). Both lead to failure of the LED cell.

[0117] To reduce the probability of subpixel or pixel failure, a redundant LED is provided for each subpixel. If a defect occurs, appropriate circuit-related measures are taken to prevent the cell from failing; that is, the defective light-emitting diode can be isolated from the current source. However, in some variations, when there are no errors, two LEDs, specifically the typical LED and the redundant LED, may be supplied from the same current source. Therefore, the current per light-emitting diode is almost halved. This also leads to a color shift resulting from the dependency between the cross-current and the occupied wavelength. In addition, due to the process technology of displays, especially video walls, or modules thereof, it is often possible to implement only one common cathode for all light-emitting diodes. Depending on the structure of the backplane (e.g., TFT backplane), it may be possible to use only NMOS transistors (N-type metal-oxide-semiconductor transistors) in the structure of the pixel cell. In conventional 2T1C (two transistors and one capacitor) cells, there is a clear dependency between the cross-current of the light-emitting diode and its forward voltage.

[0118] Several approaches exist to solve these problems, but most require additional effort and space. The principle proposed herein provides a solution that ensures redundancy while not halving the current flowing through the light-emitting diodes. Furthermore, the use of PMOS transistors offers greater flexibility.

[0119] A device is created that electronically drives and controls multiple LEDs as pixel cells or subpixels, particularly 2T1C cells. A first transistor and embossed electronic elements assigned to the LEDs generate a current that triggers a fuse connected in series with these LEDs.

[0120] Therefore, a device for electronically driving and controlling multiple LEDs in a pixel cell or subpixel includes a first branch and at least one second branch, each to which the LEDs are internally connected, and an electronic fuse placed in series with the LEDs. One side of the first branch and at least one second branch is connected to a potential terminal. Furthermore, a driver circuit is provided having a data signal input, a select signal input, and a drive output. The drive output is connected to the other side of the first branch and at least one second branch. Finally, the device includes an embossed component assigned to at least one second branch, which is configured to generate a current flow that triggers the electronic fuse placed in series.

[0121] Thus, a distinctive feature is the introduction of a combination of additional embossed signal lines and additional electronically embossed structural elements, which may be configured as transistors or diodes. This ensures that after end-of-line (EOL) testing, only one light-emitting diode is active per color and per pixel, specifically, even for pixels without errors. In other words, if a defect occurs, the still-functioning LED is selected. On the other hand, if there is no defect, i.e., even if both LEDs on one branch are functioning, one of the two is permanently turned off.

[0122] In this method of electronically configuring multiple LEDs, the functionality of the LEDs in the first and second branches is first tested. If both the LEDs in the first and second branches are functioning, an embossing signal is applied to the electronic embossing element. Subsequently, a current flow is applied to the second branch, triggering a fuse connected in series with the LEDs in the second branch. For this purpose, the fuse is usually configured as a blown fuse.

[0123] In one configuration, the embossed element may have an embossed transistor, the current line contact of which is electrically connected in parallel to the LED to which the embossed element is assigned, and the control contact of which is connected to the embossed signal line. Alternatively, the embossed element may also have an embossed diode, the terminal of which is connected to the second terminal of the LED to which the embossed element is assigned, and the other terminal of the embossed diode is connected to the embossed signal line.

[0124] The proposed arrangement allows the LEDs to be formed as so-called common anodes or common cathodes. That is, depending on the configuration, the LEDs of each branch are connected either between the supply potential and the current source or between the current source and the reference potential terminal. Thus, in one case, the LEDs are connected between the supply potential terminal and the electronic fuse. In the other case, the LEDs are connected between the fuse and the reference potential terminal. The current source is always connected to the electronic fuse of each branch. The charge storage means of the 2T1C cell is connected to the gate of the current source transistor and the fixed potential, i.e., the potential terminal to which the current source transistor is also connected.

[0125] In another embodiment, a display having the above-described plurality of devices is presented, in particular a video wall, or a display module, in particular a module of a video wall, wherein the pixel cells of the display are electrically connected to common embossed signal lines along rows and / or columns. Each pixel cell in a column is electrically connected at a supply potential terminal to a switching transistor located on a common carrier outside the display by a common supply lead.

[0126] In addition to various concepts for preparing drive control and redundant circuits, further consideration is being given to connecting carriers containing LEDs or monolithic arrays to carriers containing drive control units. There is a concept that attempts to realize both LEDs and IC circuits with the exact same material system. This in itself is recommended and at least partially feasible. However, the material system for LEDs has drawbacks and is only conditionally suitable for IC circuits.

[0127] Another approach involves constructing different material systems to generate a drive control circuit on the one hand and matrix-arranged LEDs on the other. There are essentially two possibilities for this. First, structural elements can be fabricated starting from one material system, then a transition section can be created to the other material system, providing further structural elements. Leads passing through the material systems and the transition section connect the structural elements. In this approach, one challenge is selecting and adjusting different process parameters so that the fabrication of one "surface" is possible without damaging the other "surface." For example, process temperatures (e.g., diffusion process or injection process) can be very different, resulting in either no diffusion or undesirable diffusion depending on the temperature. Thus, structural elements may be damaged. In some embodiments, it is proposed to fabricate the drive control circuit using a single silicon-based technique, and then subsequently grow different material systems, such as rods.

[0128] Another approach proposes fabricating the drive control unit and pixel array separately and connecting them electrically and mechanically. This allows for optimization of fabrication to suit specific needs and requirements. Alternatively, using digital drive control technology can reduce the number of contact pads required between carriers without limiting functionality. Thus, the development of novel digital and analog concepts enables the manufacture of displays such as video walls, as well as display devices and matrices.

[0129] One embodiment for constructing an LED display relates to the control of light-emitting elements or LEDs within a display or video wall. In this embodiment, the display has multiple LEDs arranged in rows and columns. In some embodiments, the LEDs can be grouped into subunits, which facilitates fabrication, testing, and processing.

[0130] One configuration provides a display having multiple pixels arranged in rows and columns. The first substrate structure is fabricated from a first material system and has multiple LEDs. The LEDs are individually addressable by leads in and / or on the first substrate structure. Multiple contacts are arranged on the surface of the first substrate structure that does not face the main radiation direction.

[0131] Furthermore, the display has a second substrate structure that includes multiple digital circuits for addressing LEDs. The second substrate structure is made of a different material system than the first substrate structure. The second substrate structure has multiple contacts on its surface that correspond to the contacts of the first substrate structure. Here, according to the proposed principle, the first and second substrate structures are mechanically and electrically connected to each other, so that their contact areas correspond to each other. According to this concept, it is proposed to fabricate the digital and analog elements of the display separately using different material systems and then connect them to each other. In this way, the optimal technology can be used in each case.

[0132] In this regard, the first substrate structure having the LEDs may be configured as a monolithic module. Alternatively, a modular structure can be used. As a result, the first substrate structure itself becomes a carrier for a module consisting of various LEDs. In some embodiments, the first substrate structure includes analog circuits such as current sources for each pixel. Similarly, redundant circuits and driver circuits provided herein are also conceivable. While such circuits can be implemented using thin-film technology, it is necessary to avoid excessive demands on current carrying capability. Where possible, in some embodiments, it may be advantageous to provide a multiplexer or other circuit in the first substrate structure. This reduces the number of contact areas between the first and second substrate structures. For a simple switch that selects one of two LEDs in each case, the required contact area is reduced by approximately half. In other embodiments, for example, by using a common cathode layer for the LEDs, it may be possible to combine contacts in some cases.

[0133] Regarding material systems, each technology and material system has its own advantages and challenges, allowing for flexible selection. The second substrate structure is based particularly on single-crystal, polycrystalline, or amorphous silicon. The implementation of digital circuits with these material systems is well understood and can be sized as needed. Similarly, indium gallium zinc oxide, GaN, or GaAs are also suitable material systems for the second substrate structure. For the first substrate structure, at least one of the following compounds can be used: GaN, GaP, GaInP, InAlP, GaAlP, GaAlInP, GaAs, or AlGaAs. In one embodiment, the thermal expansion coefficient and crystallographic parameters may differ depending on the material system used. Therefore, the two substrate structures are often connected not directly, but through several intermediate layers.

[0134] The second board structure, which includes digital circuits, may include, in addition to supply leads, multiple digital circuits for generating PWM-like signals from the clock signal and data word of each pixel. Furthermore, it is possible to connect shift registers in series, each having a length corresponding to the data word of a pixel, and connect each shift register to a buffer for temporary storage.

[0135] To reduce the aforementioned contact area, the second substrate structure may include one or more multiplexers electrically coupled to the demultiplexer of the first substrate structure for driving and controlling multiple LEDs. [Brief explanation of the drawing]

[0136] The following sections will provide a more detailed explanation of some of the aspects mentioned and summarized above, using various structures and examples. [Figure 1] Figure 1A is a cross-sectional view of one example configuration of a dual-gate transistor, Figure 1B is a plan view of two dual-gate transistors, and Figure 1C is a diagram showing the dependency of the threshold voltage on the top-gate voltage. [Figure 2] This figure shows a first configuration example of a drive control circuit for LEDs having several aspects based on the presented concept. [Figure 3] This figure shows a second configuration example of a drive control circuit for LEDs having further embodiments. [Figure 4] This figure shows a third configuration example of a drive control circuit for LEDs, according to several aspects of the concept proposal. [Figure 5] This figure shows further configuration examples of a drive control circuit for LEDs having further embodiments. [Figure 6] This figure shows further configuration examples of a drive control circuit for LEDs according to several aspects of the concept proposal. [Figure 7] This figure shows a further example configuration that supplements the previous figure. [Figure 8] This figure shows a fifth configuration example of a drive control circuit for LEDs according to several embodiments. [Figure 9] This is a circuit diagram of an SRAM 6T cell used to illustrate its configuration. [Figure 10] This is a circuit diagram of a driver circuit to illustrate several embodiments. [Figure 11] This is a schematic diagram of a display comprising digital elements and a pixel array according to several proposed embodiments. [Figure 12] This is a circuit diagram illustrating the clock flow of dark pixels. [Figure 13] This figure shows the global bias of the pixel stream according to several different configurations. [Figure 14] This is a signal timing diagram using several signals according to the configuration shown in Figure 13. [Figure 15] This figure shows a further configuration of a space-saving driver circuit. [Figure 16] This figure shows a configuration of a further driver circuit that is similarly space-saving. [Figure 17] This is a schematic diagram of a driver circuit for two LEDs to illustrate several aspects of dimming drive control according to several embodiments. [Figure 18] This diagram shows the LED current flowing through an LED as a function of different capacitor voltages. [Figure 19] This is a schematic diagram showing the brightness of an LED-equipped lighting unit when driven and controlled with a relatively high first voltage signal. [Figure 20] This is a further schematic diagram showing the brightness of an LED-equipped lighting unit when driven and controlled with a relatively low first voltage signal. [Figure 21] This figure shows the average light output of an LED lighting unit as a function of the voltage selected for the capacitor voltage, according to some aspects of the concept presented herein. [Figure 22] This is a block diagram showing the main configuration of a PWM supply circuit for LEDs. [Figure 23] This figure shows an example configuration of a PWM supply circuit for LEDs based on the proposed principle. [Figure 24] This diagram shows the configuration of Figure 23 in its operating state, along with additional information regarding the signal flow. [Figure 25] This is a schematic diagram of two simple switching devices. [Figure 26] Figure 23 is a signal timing diagram of the proposed configuration having the signal points shown. [Figure 27] This figure shows an exemplary configuration of an analog lamp-based control circuit suitable for controlling the on / off ratio of the light-emitting device in an LED display. [Figure 28] This is a signal timing diagram for various signals based on the concept shown in Figure 23. [Figure 29] This is a circuit diagram of a pixel cell equipped with redundant LEDs and a fuse to isolate the LEDs. [Figure 30] This figure shows a further configuration of a circuit with redundant LEDs that can compensate for LED defects. [Figure 31] This figure shows a third configuration example of a circuit with redundant LEDs, following several aspects of the presented concept. [Figure 32] This figure shows a fourth configuration example of a circuit with redundant LEDs, allowing for the replacement of a defective LED. [Figure 33] This is a fifth example of a circuit configuration with redundant LEDs. [Figure 34] This figure shows a sixth example configuration of a circuit with redundant LEDs to compensate for LED defects. [Figure 35] This figure shows one configuration of a method for testing and configuring a pixel cell driven and controlled by one of the circuits presented above. [Figure 36A] A schematic diagram of an alternative control circuit configuration for one or more LEDs, taking shape and size requirements into consideration, is shown. [Figure 36B] A schematic diagram of an alternative configuration for a driver circuit for multiple LEDs, taking into account shape and size requirements, is shown. [Figure 36C]This figure shows one configuration of a comparator circuit that can be used, for example, as a comparator instead of the OR gate used in Figure 36A. [Figure 36D] This diagram shows the timing of the various counterwords 1D to 3D and memory registers used to generate the output signal. [Figure 37A] This is a side view of the LED display unit's layout structure. [Figure 37B] This figure shows various examples of interconnections of different sections according to the configurations of Figures 36A and 37A. [Figure 38] This figure shows an example of an offset inverting transistor using amorphous silicon, which is used in the analog section of an LED driver. [Figure 39] This figure shows some examples of polysilicon transistors suitable for LED driver circuits. [Figure 40] This is a circuit diagram of an LED or LED display unit. [Figure 41] This is a circuit diagram of an LED display unit divided into various sub-matrices. [Figure 42] This diagram shows a conventional approach to the driver circuit for LEDs within the pixels of the display unit. [Figure 43] This diagram shows one configuration of a conventional column driver suitable for use with displays. [Figure 44] This diagram shows one configuration of a conventional row driver suitable for use with displays.

[0137] Detailed explanation In the case of a display or video wall, each pixel can be individually driven and controlled separately from a second pixel, allowing for flexible visualization of all kinds of information as needed. Simply put, it requires the separate driving and control of a 1920 x 1080 pixel matrix, similar to conventional televisions and monitors with approximately 2 million pixels.

[0138] Therefore, a new concept is needed, which can be broadly divided into two areas. The first area concerns the new design of components such as transistors and capacitors. The second area concerns the circuit technology and principles for driving and controlling LED pixels. Simply put, the digital transmission path for addressing pixels by row and column takes up space, as does the corresponding decoding of rows and columns. The same can be said for the implementation of current sources and buffers for supplying the necessary current to each individual LED. Whether LEDs are assembled monolithically or individually, a variety of concepts can be envisioned that will yield a good visual impression through a new approach to dealing with LEDs in a display.

[0139] Figure 1A shows an example configuration of an LED current driver using back-gate or dual-gate transistors formed with NMOS technology. This configuration can be implemented with a small number of components.

[0140] Such back-gate transistors are frequently used as current driver transistors or current sources. In particular, they are assembled using TFT (thin film technology) and have a second control terminal, also called a back gate, in addition to the standard control terminal and gate. Adding this back gate allows for the modification of the transistor's conductive channel, as described below. Instead of adding a separate transistor for pulse-width modulation (PWM), the back gate of an existing dual-gate transistor can be modulated with a PWM signal.

[0141] Figure 1A shows a cross-section of a back-gate controlled NMOS field-effect transistor. The source region S is on the left, and the drain region D is on the right, with a current-conducting channel between the two regions. In a typical field-effect transistor, a single gate changes the resistance of the channel, i.e., the channel's ability to conduct current. In a dual-gate transistor, the channel is changed by a first bottom gate B and a second top gate T. In this case, the gates are located on opposite sides of the channel. In this configuration example, the top gate (upper gate) provides an additional back-side contact or back-gate contact.

[0142] Figure 1B shows two planar views of the dual-gate transistor described in Figure 1A. As shown in the left-hand view, the source region S on the left and the drain region D on the right can be controlled by current lines using the top gate T and / or bottom gate B. The right-hand view of Figure 1B shows a portion of the arrangement according to Figure 1A.

[0143] Figure 1C shows the top gate voltage V at the threshold voltage. TG Dependence on, and consequently on the back contact and threshold voltage V TH This represents the interaction with the threshold voltage V. TH V is the gate-source voltage at which a field-effect transistor becomes conductive. GS In Figure 1C, the x-axis represents the voltage V applied to the top gate T. TG This shows the following. In this function, the y-axis represents the threshold voltage V when the conductivity of the channel of the controlled NMOS field-effect transistor changes. TH This shows that, for example, when the top gate voltage is 0V, the threshold voltage required for current to flow is 0.5V. By adding a top gate to an insulated-gate-ZO-NMOS transistor, the threshold voltage of the transistor V TH It can be shifted almost linearly over a wide range.

[0144] Figure 2 shows a first configuration example of a device for electronically driving and controlling an LED, particularly a pixel or sub-pixel for a display or video wall. The LED is connected in series with a dual-gate transistor between a first potential GND and a second potential Vdd. This arrangement has a threshold line PWM connected to the first control gate or back gate BG of the dual-gate transistor T2. The threshold line PWM additionally has a control electrode. This back gate BG with a back contact is shown in FIGS. 1A and 1B. According to the graph in FIG. 1C, the threshold voltage can be significantly shifted via the back contact, i.e., the voltage U GS between the gate G and the source S remains constant, and the output current can be modulated by the additional gate BG. In principle, it is also possible to use the gate G and the back gate BG in reverse. That is, current setting can be performed at the first control terminal BG, and pulse width modulation can be performed at the second gate G. Due to the wide dynamic range provided by this circuit, the threshold voltage can be shifted to a range that results in a safe off state of the second transistor T2.

[0145] This enables PWM (pulse width modulation) operation.

[0146] A further advantage is the speed increase of the circuit design using the dual-gate transistor T2. High-speed switching is possible. Different from modulation using the "data" line, since no memory capacity is used, higher-speed modulation is possible with the same driver output.

[0147] Furthermore, this arrangement includes a data signal line data and a select signal line sel. Finally, this arrangement further includes a select hold circuit with a charge storage means Cs and a control transistor T1. The charge storage means is arranged between the second control gate G of the dual-gate transistor T2 and the terminal of the LED. The control terminal of the control transistor T1 is joined to the select signal line Sel. During operation, data is applied to the data signal line via the select signal line to the gate G of the dual-gate transistor T2. The voltage UGS The voltage is stored in capacitor Cs and remains applied even after select transistor T1 is turned off. The voltage is specified by the data signal, and the address is specified by the select signal Sel.

[0148] Thus, gate G generates a fixed channel, and consequently, a constant current flows through the current path. In this way, transistor T2 provides a constant current source, which is further pulse-width modulated by a PWM signal at the back gate of transistor T2. Therefore, the LED switches between a current specified by the data of the charge storage means and an "off" state via the PWM signal. In some configurations, the color of the LED changes slightly depending on the applied current, so the color can be slightly changed by the data signal and the luminosity by the PWM signal. If the color dependence is low, the luminosity can also be set via data with a fixed PWM.

[0149] The configuration in Figure 2 shows pulse width modulation of a constant current source adjustable using an NMOS-TFT (thin film) transistor T2 without GND-based programming. However, this configuration is not temperature stable. This temperature instability is due to the temperature dependence of the voltage drop across the light-emitting diode, affecting the charge storage means C S This is due to slight fluctuations in the voltage applied to it.

[0150] Figure 3 shows a second configuration example of a device for electronically driving and controlling an LED pixel cell provided by NMOS technology. Similar to the previously described configuration, the current path includes an LED and a dual-gate transistor T2 connected in series between a first potential terminal GND and a second terminal Vdd. The charge storage means Cs of the select signal hold circuit has one terminal connected to the gate G of transistor T2 and the other terminal connected between the source S and the first potential GND. As a result, the voltage across the charge storage means Cs is constant and independent of the forward voltage of the light-emitting diode, and therefore also independent of temperature. The select signal hold circuit is programmed to GND.

[0151] On the other hand, the LED is connected between the drain terminal D and the supply potential Vdd. Therefore, the LED is positioned on the side of the second potential terminal Vdd, which supplies an electrically higher potential. This arrangement corresponds to that in Figure 2, but the light-emitting diode is not positioned on the low side, meaning its cathode is not connected to GND (ground (Masse)), but rather on the high side or upper circuit of transistor T2. Therefore, the cathode of the light-emitting diode is connected to the drain of transistor T2, and its anode is connected to the second potential terminal V dd It is connected to the LED. Accordingly, the LED shows a common anode topology instead of the conventional "common cathode."

[0152] Figure 4 shows a third configuration example of the device, i.e., the configuration described in Figure 2, but using PMOS thin-film transistors instead of NMOS thin-film transistors (TFTs). Therefore, only PMOS transistors are used. In this configuration, the charge storage means is connected between the source of the dual-gate transistor T2 and the first potential Vdd.

[0153] In the configuration shown in Figures 2-4, classical drive control of the pixel matrix is ​​possible. Here, voltage value data is written to the "front gate" (normal) gate G of transistor T2, and the hold capacitor Cs stores this voltage value and controls the second transistor T2 accordingly. This is used, for example, to set the color mixing of RGB pixels. Then, a pulse-width modulation (PWM) voltage is applied to the second transistor T2 via the back gate BG, and this voltage modulates the current of the light-emitting diode in time by pulse-width modulation (PWM), and is used, for example, to change the general brightness of the pixels for a pre-programmed color. This color is pre-programmed by the first transistor T1 and capacitor Cs. For example, it is also possible to apply the same pulse-width modulation signal to the back gate of each transistor in a single display row. In this way, the entire row is "dimmed".

[0154] All backgates of the entire display—that is, all columns and rows—are driven and controlled by a common pulse-width modulation (PWM) signal, making it possible to "dimm" the entire display or video wall without changing the image content. This can be used, for example, in the day / night mode of automotive displays or in video walls. In this way, brightness can be dynamically and continuously adjusted to match the ambient light. In the field of video walls, it may be possible to individually drive and control parts of the video wall in this way to brighten dark areas or dim bright areas.

[0155] Figure 5 shows a third configuration example of the device, namely a further configuration of the drive control device design. In addition to the display and device shown in Figure 2, a third transistor T3 is connected in parallel with the LED, and the control terminal of the third transistor T3 is joined to the select signal line Sel. Transistor T2, acting as a constant current source, consists only of a gate here. This arrangement allows programming to be performed independently of the LED's anode potential. The device shown here is obtained by combining an NMOS-based IGZO process with the common cathode requirement from process engineering for LED assembly. Based on this, it is possible to implement a 2T1C (two transistors and one capacitor) current source.

[0156] High potential V on the select signal line Sel dd When the voltage is applied, the first transistor T1 is connected to the data signal line V data As it is connected to the third transistor T3, and furthermore, current is conducted, the light-emitting diode is bypassed, and capacitor C is connected to the reference potential (GND). In this way, the capacitor is connected to a voltage V referenced to the reference potential GND of the lower first potential terminal, rather than the anode potential of the LED. data It is programmed as follows: If the potential of the select signal line Sel is the reference potential (GND), the first transistor T1 and the third transistor T3 are disconnected, and the voltage of capacitor C is blocked by the gate-source voltage U of the second transistor T2. gs It will be held as a pre-programmed value corresponding to the anode potential. When the anode potential shifts, V data Disconnecting the first transistor also shifts the gate potential to the second transistor T2, thus shifting the gate-source voltage of transistor T2 U gs This will be kept constant. In this way, the second transistor T2 can operate as a current source.

[0157] Figure 6 shows a fourth configuration example of the device, namely, a configuration of a subpixel cell. Figure 6 shows the arrangement structure described in Figure 5, but differs in that the second transistor T2 is formed as a dual-gate transistor and its additional gate terminal BG is connected to a threshold line PWM for the application of pulse width modulation. The front gate G is connected to the charge storage means C, and the back gate BG is supplied with a pulse width modulated signal.

[0158] Transistors T1 to T3, together with the hold capacitor C1, form an NMOS-type 3T1C cell. The 2T1C cell, composed of transistors T1 and T2, may be configured as a PMOS type. In this case, for example, a third transistor T3 is not necessary. Transistor T2 is configured as a so-called "dual-gate transistor".

[0159] Figure 7 shows an example configuration of a device with additional temperature stabilization. Transistors T1 and T2, together with the hold capacitor C1, provide an NMOS type 2T1C cell. The light-emitting diode is located on the low side of transistor T2 because, for process reasons, it has a "common cathode," i.e., a common cathode. T2 is configured as a "dual-gate transistor" and therefore has two control electrodes. As in some of the examples mentioned above, in this configuration as well, the gate of the dual-gate transistor T2 (corresponding to the bottom gate in Figure 1A) is part of the topology of the 2T1C cell and sets the LED color and general brightness by ground-related programming of the charge storage means C1 and the signal on the Data1 line. A PWM signal can be applied to transistor T2, which acts as a current source, via the back gate BG (front gate in Figure 1A).

[0160] Therefore, the gate-source voltage of transistor T2 depends on the forward voltage of the LED. Since the voltage drop across the light-emitting diode depends not only on the cross-current but also on the temperature, the resulting output current will differ significantly from the actual expected value in the programming. This can be expressed by the following equation 1: I LED =K(U data -U LED (T,I)-U th ) 2 (Equation 1) In the above formula, U data This is the voltage across the charge storage means C1. When the LED self-heats, its forward voltage decreases, and the current flowing through transistor T2 increases. Because there is no negative feedback, changing the LED's operating parameters will have a significant impact on the current and, consequently, on the LED's brightness and color.

[0161] Therefore, a negative feedback mechanism is proposed that can compensate for such effects by utilizing the dual-gate transistor function of transistor T2. The negative feedback includes a hold capacitor C2 connected between the reference potential AVSS and the control terminal of transistor T3. The first terminal of capacitor C2 forms the control of the back gate BG of dual-gate transistor T2, and the other terminal of capacitor C2 is connected to the source S of dual-gate transistor T2. The negative feedback includes a further transistor T4, whose control terminal and drain terminal are connected to the supply potential AVDD. The source terminal of transistor T4 is connected to the back gate BG and the drain of transistor T3. Finally, a fifth transistor T5 is provided for the arbitrary programming of the compensation, which causes the hold capacitor C2 to store the compensation value on the Data2 line using a select signal Set2.

[0162] The gate-source voltage of transistor T3 corresponds to the value obtained by subtracting the forward voltage of the light-emitting diode from the voltage across the hold capacitor C2. This forward voltage V fAs the LED rises, the charge stored in capacitor C2 remains unchanged, and therefore the gate-source voltage U of the third transistor T3 is... GS The voltage drops. Therefore, the current flowing through the third transistor T3 decreases. Since this current also flows through transistor T4, and the gate of the fourth transistor T4 is coupled to the supply potential, the voltage drop U across the fourth transistor T4 decreases. DS This becomes smaller. Therefore, a higher voltage is generated at the node to the back gate of transistor T2. As a result, the threshold voltage of transistor T2 becomes lower. The corresponding design of transistors T3 and T4 according to Equation 2 below can compensate as much as possible for the forward voltage response of the light-emitting diode:

number

[0163] The fifth transistor T5 and capacitor C2 allow for fine-tuning of the Data2 of the pixel cell, including negative feedback. In the configuration shown in Figure 7, current stability is significantly improved without the need for complex pre-calculations. Current instability is corrected with minimal components without complex pre-calculations of the "data" signal. This allows for compensation of temperature changes during operation. Furthermore, by adding a control input Data2, particularly via Sel2, the quiescent current by the third transistor T3 can be reduced.

[0164] Figure 8 shows a fifth configuration of the LED drive control device. As in the example above, the LEDs may be part of a display or, for example, a video wall module. In addition to the configuration shown in Figure 2, further improvements have been made to take into account temperature compensation and the effects of forward voltage applied to the LEDs.

[0165] This configuration includes a third electronic switch T3 having a first current line contact connected to the second terminal of the LED, the second current line contact of the third electronic switch T3 being connected to the first control terminal BG of the second electronic switch T2. Furthermore, this device includes a fourth electronic switch T4. The control terminal of the third electronic switch T3 is connected to the second current line contact of the fourth electronic switch T4, and together these are connected to the supply potential AVDD. The control terminal of the fourth electronic switch T4 is also connected to the supply potential AVDD. Finally, the first current line contact of the fourth electronic switch T4 is connected to the second current line contact of the third electronic switch T3.

[0166] A fifth electronic switch T5 is provided to control the second electronic switch T2 via the first control terminal BG. This is connected in parallel with the LED. Furthermore, the second current line contact of the fifth electronic switch T5 is connected to the first current line contact of the third electronic switch T3. The control terminal of the fifth electronic switch T5 is electrically connected to a terminal for supplying a pulse width modulation signal (PWM).

[0167] The behavior and function of the device shown in Figure 8 are similar to those of the device described in Figure 7. However, unlike in Figure 7, the gate of the third transistor T3 is electrically connected to a fixed potential Vdd. Optionally, an additional fifth transistor T5 can be provided to safely turn off the light-emitting diode without cross-current from the third transistor T3. The fifth transistor T5 is not necessary if the cross-current from the third transistor T3 to the LED is not a concern. According to the device presented here, pulse-width modulation (PWM) control is performed without a hold capacitor. In this way, the possible resolution of pulse-width modulation can be increased with the same cycle time. Similarly, recharging of the storage capacitor is not always necessary, and the switching speed can be improved.

[0168] Further aspects of this concern control for adjusting or dimming the brightness of pixels or associated LEDs. Such dimming is frequently used not only in the automotive sector, for example, to switch between daytime and nighttime visibility, but also in video walls. In principle, such dimming can be advantageous when it is necessary to adjust contrast, or to regulate the brightness of a display in accordance with ambient light to prevent dazzling the user's eyes and to display information safely.

[0169] Conventional methods address this problem with PWM control and current dimming, but complex compensation circuits are required because the external parameters of the LED change frequently. Alternatively, a so-called 2T1C circuit can be used to supply control signals for driver drive control to the circuit and store them in a capacitor. In this case, the brightness is adjusted by the voltage applied to the capacitor. Thus, the present invention utilizes an aspect that often occurs as a parasitic and undesirable effect, namely the gate-source capacitance of the driver transistor. This creates a capacitive voltage divider by the capacitance of the capacitor, which lowers the voltage at the gate of the transistor. By appropriately selecting the gate-source capacitance, brightness can be adjusted over a wider range.

[0170] In one embodiment, a control circuit for adjusting the brightness of at least one LED comprises a current driver element having a control terminal. This element is connected in series with the LED and has a first terminal connected to a first potential. A charge storage means is positioned between the control terminal and the first potential and forms a capacitive voltage divider with a capacitance defined between the control terminal and the first terminal.

[0171] Furthermore, according to the present invention, a control element is provided that supplies a control signal to a control terminal during a first period, and based on this, sets the current flowing through at least one LED during the first period. During a second period following the first period, the current flowing through the LED is determined by a reduced control signal obtained from the control signal during the first period and a capacitive voltage divider.

[0172] Thus, by selecting a control signal using a control element, the brightness of the LED can be adjusted to depend substantially on either the current during the first period or the current flowing through the LED during the subsequent second period.

[0173] In other words, the control signal determines the total current flowing through the LED during the first and second periods, and if the control signal is appropriately selected, it substantially depends on the current flowing through the LED during the first period or the current flowing through the LED during the second period.

[0174] Thus, the control element is configured to supply a first or second control signal during a first period in order to operate the LED at at least two different brightness levels throughout the entire period. For example, the second control signal is greater than the first control signal, and the reduced control signal derived from the second control signal is sufficient to drive and control the current driver to supply enough current to operate the LED.

[0175] As mentioned above, the current driver element may include a field-effect transistor, the gate of which forms a control terminal, and which has a gate-source capacitance determined by design. Therefore, the signal, which is a reduced control signal applied to the control terminal of the transistor or current driver during the second period, is obtained based on the control signal during the first period, as well as the capacitance of the charge storage means and the ratio of the sum of the capacitance of the charge storage means and a defined capacitance.

[0176] Such a circuit is operated at a certain frequency such that the first period and the second period occur periodically in succession. This frequency may be 60 Hz, often 100 Hz or 120 Hz, or in the range of 60 Hz to 150 Hz. In one embodiment, the control element is configured to allow adjustment of the ratio between the second period and the first period, which may be in the range of 300:1 to 100:1, particularly in the range of 100:1. For this purpose, the control element includes a control transistor, at which the first and second periods and thus the duty cycle can be adjusted by signal.

[0177] In this way, the brightness level can be selected by various control signals during a first period of a cycle. To this end, in one embodiment, the LED is operated at a first dim brightness level when the voltage of the first control signal is within a first voltage interval, and the LED is operated at at least a second bright brightness level when the voltage of the second voltage signal is within a second voltage interval that is at least partially higher than the first voltage interval.

[0178] In this regard, brightness is determined by the current flowing through the LED over the entire period. With a control signal within the first voltage interval, the total current is substantially determined by the current during the first period. This is because, due to the capacitive voltage division and the resulting reduction in the voltage of the control signal during the second period, the current flowing through the LED during this period is very low and limited, insufficient or irrelevant for operation. During this period, the current driver is either not driven or only slightly driven, and the LED is barely lit or not lit at all.

[0179] On the other hand, if the control signal is within the second voltage interval during the first period, the total current for one cycle is substantially determined by the current during the second period. In this case, despite the capacitive voltage division and the resulting reduction in the voltage of the control signal during the second period, the current driver is still adequately driven and controlled, and a sufficient amount of current flows through the LED to operate it. The value of the first voltage interval is in the range of 1.3V to 4.5V. The second voltage interval is in the range of 4.0V to 10.0V.

[0180] A further embodiment relates to a method for adjusting the brightness of at least one LED connected to a current driver element having a control terminal, wherein a first terminal of the control terminal is connected to a first potential, and a charge storage means is connected between the control terminal and the first potential, so that the charge storage means forms a capacitive voltage divider with a capacitance defined between the control terminal and the first terminal. In this method, the current flowing through at least one LED during a first period is adjusted by applying a control signal to the control terminal during a first period. During a second period following the first period, the control signal is turned off, so that the current flowing through the LED is determined by a reduced control signal obtained from the control signal during the first period and the capacitive voltage divider. Turning off the control signal is understood as disconnecting the control signal from the control terminal so that only the reduced signal obtained from the control signal during the first period and the capacitive voltage divider acts on the control terminal thereafter.

[0181] Therefore, this reduced control signal is lower than the control signal by the ratio of the capacitance division voltage due to the voltage division. In particular, from one perspective, the reduced signal applied to the control terminal during the second period is obtained based on the control signal during the first period, as well as the ratio of the capacity of the charge storage means to the sum of the capacity of the charge storage means and the defined capacity.

[0182] In another embodiment, the ratio of the second period to the first period is in the range of 300:1 to 100:1, particularly in the range of 100:1. In yet another embodiment, it is proposed that the LED be operated at a first dim brightness level when the voltage of the first control signal is within a first voltage interval, and the LED be operated at at least a second bright brightness level when the voltage of the second voltage signal is within a second voltage interval that is at least partially higher than the first voltage interval.

[0183] In this regard, in this proposed method, the brightness is determined by the current flowing through the LED throughout the entire period. With a control signal within the first voltage interval, the current flowing through the LED during this period is very small due to the capacitive voltage division and the resulting voltage drop during the second period, so the total current is substantially determined by the current during the first period. During this period, the current driver is either not driven or is driven only very slightly.

[0184] On the other hand, when the control signal is within the second voltage interval during the first period, the total current is substantially determined by the current during the second period. In this case, despite the capacitive voltage division and the resulting voltage drop of the control signal during the second period, the current driver will still be sufficiently triggered, and enough current will flow to operate the LED. The value of the first voltage interval is in the range of 1.3V to 4.5V. The second voltage interval has a range of 4.0V to 10.0V.

[0185] The first or second control signal required for drive control is obtained by digital / analog conversion from a digital control word. For this purpose, the digital control word has a bit number n. Here, the least significant m bits (M < n, for example, m = n - 2 bits) correspond to the first control signal, that is, the most significant bit number is 0. In other words, n bits correspond to the second control signal. Also, the most significant bit number is used for coarse brightness adjustment, and the least significant bit number is used for more precise range adjustment.

[0186] FIG. 17 shows a control circuit of a lighting unit 1 having two LEDs 4 as lighting means. As a basic structure, as shown here, the control circuit can be realized with a 2T1C architecture. However, other architectures are also conceivable.

[0187] In order to ensure redundancy regarding light generation, according to the illustrated configuration, even when two LEDs 4 are provided, whether one LED 4 or a plurality of LEDs 4 are used as the lighting unit is generally irrelevant to the implementation of the present invention. The lighting unit 1 or the LED 4 may be, for example, an LED of one color of one pixel.

[0188] In the configuration example shown in FIG. 17, electrical energy necessary for exciting light emission is supplied to each of the two parallel-connected LEDs 4 via a current driver transistor 6. In addition to the transistor 6 for each LED, a current source common to both LEDs 4 may be provided. The current driver transistor 6 is connected in series with the LED 4 between a supply potential terminal 2 and a reference potential terminal 2a. The supply potential terminal 2 supplies the electrical energy or voltage necessary for the operation of the lighting unit 1.

[0189] A capacitor that stores the brightness value is connected between the gate of the current driver transistor 6 and the reference potential terminal 2a. This capacitor, together with the control transistor 7, forms a 2T1C cell. When a pulse signal is applied to its gate, a control signal 8 is applied from the other terminal of transistor 7 to the control terminal of the current driver transistor 6.

[0190] Then, in order to operate the circuit shown in Figure 17A according to the concept, a pulse signal is applied to the gate of transistor 7. The On / Off duty cycle can be, for example, 200:1. That is, if the repetition frequency is 60Hz, the On pulse duration is approximately 50μs and the Off pulse duration is approximately 16.6ms.

[0191] During this cycle, the control transistor is closed via a pulse signal during the first period (ON pulse duration), and reopened during the second period (OFF pulse duration). Therefore, during the first period, the control signal 8 is applied to the control terminal of the current driver transistor 6 via the capacitor 3. This control signal controls the current driver transistor 6, and the current generated by the control signal 8 flows through the LED. Simultaneously, charge is applied to the capacitor until the voltage of the control signal is generated through the capacitor (see the potential at terminal 2a).

[0192] After the first period, the control transistor 7 is opened again. At this point, it is desirable that the voltage of the control signal 8 is stored in the capacitor and further drive the current driver transistor. However, this does not happen in actual use. This is because, in the second period, a capacitive voltage divider is formed, consisting of the capacitance of the storage capacitor 3 and the capacitance formed from the gate and source of transistor 7. This often causes the effective voltage 9 of capacitor 3 to decrease by a discrete value. The reduced effective voltage 9 is the voltage of the control signal multiplied by C1 / C1+Cp, where C1 is the capacitance of the capacitor and Cp is the gate-source capacitance. In other words, a slightly smaller control signal 9 (or a slightly smaller voltage) is applied to the driver transistor 6 compared to the first period, so a lower intensity current flows through the LED 4. Therefore, the brightness of the LED 4 decreases slightly during the second period of one cycle. However, this is not noticeable to the viewer. This is because only the average light output, which exists in relation to the period, is extremely important for the perception of brightness.

[0193] Thus, throughout the entire cycle, control signal 8 is applied to the control terminal during the first period, and a reduced control signal 9 is applied during the second period. When the frequency is 60Hz, the duration is 0.05ms to 0.06ms in the first period and approximately 16.6ms in the second period. In relation to the average light output of the LED, this means that the light emitted by the LED during the second period accounts for a relatively high proportion of the average light output of the LED during one cycle.

[0194] This corresponds to the average current flowing through the LED. The current flowing through the LED during the second period is relatively high in proportion to the average current over the entire cycle.

[0195] As a result, when a low voltage is selected for the control signal 8, the total current flowing through the LED 4 during one cycle, and therefore the average light output, is definitively determined by the strength of the current flowing through the LED 4 while the control signal 8 is applied during the first period. Therefore, when a low voltage value is selected for the control signal 8, the lighting unit 1 can be operated at a low brightness level, and the brightness can be adjusted as needed within this low brightness range.

[0196] In contrast, if a high voltage, for example 8V, is selected for the first voltage signal 8, the total current flowing through the LED during one cycle is deterministically determined by the current during the second period of the cycle in which the reduced control signal 9 is applied to the current driver transistor 6. When a high control signal 8, i.e., a higher voltage, is selected, the lighting unit 1 operates at a high brightness level and can be dimmed at this brightness level as needed. During the second period of the cycle in which the reduced control signal 9 is applied to the lighting unit, a current of more than 1μA still flows through the LED even in this operating state, enabling particularly effective operation of the LED 4.

[0197] Furthermore, a photonic crystal 32 is incorporated into the LED module. This crystal extends just above the active layer 20, and in that region, for example, it can alter the light emission pattern in the area above the active layer, thereby resulting in a light emission enhancement effect in that region.

[0198] Figure 18 is a graph showing the strength of the current flowing through LED4 as a function of the voltages of control signal 8 and the reduced control signal 9. When control signal 8 with a voltage value of approximately 1V to 3V is applied during the first period, it can be clearly seen that the current flowing through LED4 is deterministically determined by the first voltage signal 8 applied during the first period of this cycle. On the other hand, during the second period of this cycle, the applied control signal 9 is reduced by capacitive voltage division, so the current flowing through LED4 becomes almost zero.

[0199] Only after the voltage of the control signal during the first period reaches approximately 3.0V does the voltage of the reduced control signal 9 also increase, and consequently, the strength of the current flowing through LED4 during the second stage also increases.

[0200] In this regard, it must be considered in each case that the influence of the second period on the average light output of the LED4 becomes significantly larger due to the different lengths of the two stages in one cycle: a short first stage in which the control signal 8 is applied to the lighting unit 1, and a longer second stage in which the reduced control signal 9 is applied to the current driver transistor 6. Therefore, it can be seen that when the voltage of the control signal 8 exceeds 3.0V, the total current flowing through the LED during one cycle increases significantly. From this fact, with control signals using relatively high voltages of 3.0V or above 3.5V, the proportion of the total current flowing through the LED4 during one cycle is definitively determined by the proportion of current during the second period.

[0201] Furthermore, Figure 19 schematically shows the temporal progression of control signals 8 and 9 and the resulting light spot 10 when control signal 8 is applied using a relatively high voltage. In the illustrated configuration example, control signal 8 transmitted to the lighting unit has a voltage of 10V. In other respects, although the voltage of the reduced control signal 9 applied to the lighting unit during the second stage is certainly lower, it is still significantly above 0V. This voltage progression of control signals 8 and 9 forms a bright light spot 10, and thus the lighting unit is operated at a high brightness level.

[0202] In contrast, Figure 20 shows an operating state in which a relatively low voltage (2.0V in this case) control signal 8 is applied to the lighting unit. In this case, the reduced control signal 9 has a voltage of at least approximately 0V. The brightness of the light spot 10, which is determined by the average light output of the lighting unit 10 during one cycle, is significantly lower compared to the operating state shown in Figure 19. Thus, the lighting unit and the LEDs used in it can operate at relatively low brightness levels and can be dimmed as needed at this level.

[0203] Finally, Figure 21 graphs how the electrical energy transmitted to the LED during one cycle, sometimes called current, behaves as a function of the voltage signal applied to the lighting unit during the first and second periods of one cycle. The x-axis represents the voltage during the first period, and the y-axis represents the current during one cycle.

[0204] When a control signal is applied at a relatively low voltage, especially up to around 3V, the total current flowing through the LED can be seen to be due to this control signal. Only when a control signal is applied at a voltage greater than 3V does the reduced control signal voltage also increase. In particular, under this operating condition, current flows through the LEDs of the lighting unit, and this current significantly affects the amount of total current flowing through the LEDs during that period, and thus the average light output or brightness of a lighting unit with at least one LED, based on the length of the second period of that cycle.

[0205] In other respects, Figure 21 shows that the lighting unit driven and controlled in this manner can operate at two different brightness levels depending on the voltage selected for the control signal. Even at these two brightness levels, the brightness of the lighting unit can be continuously varied within a dimming range limited by the lower and upper voltage limits of the control signal. The transitions of the two characteristic curves shown in Figure 21 can be adjusted as needed using appropriate circuit design, particularly by clearly defining the capacitance and gate-source capacitance of the transistors used as switching elements. Furthermore, the voltage levels of the control signal and the reduced control signal can be defined by the appropriate selection and sizing of the electronic components used.

[0206] As the described configuration example illustrates, the control circuit configured according to the present invention can operate a lighting unit having at least one μLED at at least two brightness levels in a relatively simple manner. In particular, it is considered here that the current flowing through the LED during a first or second period of a cycle, depending on the voltage level of the control signal, has a decisive effect on the total current flowing through the LED, as well as the average light output and the brightness of the LED that is perceptible to the viewer.

[0207] Another aspect relates to the question of how the response of the current source to regulation can be reduced by PWM regulation. In pulse width modulation schemes, the current source is switched on and off in rapid succession for contrast and brightness adjustment. The frequency in this case is in the range of several hundred kHz to MHz. When a control loop is used within the current source, the switching process can cause behaviors such as spikes, which can cause the control loop to fall outside its control range.

[0208] Figure 22 shows a schematic block diagram of a regulated current source for LEDs that maintains a stable state during the switching process. This current source can be used in displays or other display devices, such as video walls.

[0209] The supply circuit includes a reference branch 10 that supplies a reference signal, particularly a reference current, or, if necessary, a reference voltage. From the reference signal, all further supply currents and, if necessary, voltages are subsequently derived. Further reference signals can also be generated from the reference signal. The reference signal, i.e., the reference current, is characterized by high temperature stability as well as stability against process variations during manufacturing. The reference branch may optionally include one or more correction circuits that provide accurate and stable reference signals, such as reference currents.

[0210] In this example, the reference branch 10 is connected to the reference input 22 of the error correction detector 20 and to a controllable source 30. In addition to the reference input, the error correction detector 20 includes an error signal input 23 and a correction signal output 21. The detector 20 is configured to compare the error signal of input 23 with the reference signal of input 22 or a signal derived therefrom, and generate a correction signal at its output 21 based on this comparison.

[0211] The controllable power source 30 has a controllable current source, which is not precisely shown in this block diagram. Furthermore, the power source includes a second backup source 40 that supplies a feedback signal to the error detector when the circuit is operating. For this purpose, a switching device 70 is provided that, depending on the operating state, i.e., the operating signal of input 74, switches the current source to the load or disconnects it from the load and connects the backup source 40. As a result, either the signal from the current source to the load or the signal from the backup source is detected by the detector 50.

[0212] For detection, a current-to-voltage converter or a voltage drop detector can be used. The detector 50 can be used to detect voltage, voltage drop, or current. The detected signal is then fed back to the error correction detector 20, where it is compared with a reference signal or a signal derived from it. The resulting error correction signal is used to adjust the controllable current source. When the current source 30 is supplied to the load 60, the error correction detector 20 adjusts the current flowing through the load to a value defined by the reference signal. In the case of an LED, the current flowing through the diode can be precisely adjusted. If the voltage drop or current flowing through the load changes due to temperature, the error correction detector readjusts the current accordingly. This part of the circuit and its operation constitutes a control loop.

[0213] Next, when the load is disconnected from the current, for example when the light-emitting diode is turned off in the case of PWM modulation, the control loop first attempts to readjust, but then falls out of the control range. Therefore, according to the present invention, a backup signal is intended to be supplied to the error correction detector 20. This is substantially the same as, or at least very similar to, the nominal signal when the load is turned on. As a result, the error correction detector 20 operates within an optimal range regardless of the operating state of the load, and the control loop does not fall out of its modulation range. This enables very fast regulation and prevents the detector 20 from going outside its regulation range.

[0214] Thus, the proposed power supply circuit includes a backup source in addition to a compensation circuit as part of a control loop for highly accurate driving control of current and voltage sources. The compensation circuit is selectively supplied with signals derived from the current or voltage source or from the backup source. This signal supply makes it possible to turn off the current source without the control loop going outside its control range.

[0215] Figure 23 shows a specific configuration for driving and controlling the current source supplying power to the light-emitting diode 60. The light-emitting diode 60 is part of a pixel matrix (not shown here) and is found in applications such as displays, video walls, or other applications requiring high-precision current supply. In the case of light-emitting diodes, changes in temperature also change the current flowing through the diode, potentially leading to changes not only in brightness but also in color temperature. This effect is compensated for by regulating the current source. Displays and pixel matrices used to display images or videos often operate using pulse-width modulation, which switches the light-emitting diodes on and off at high frequencies. The ratio of these two states determines the brightness of each light-emitting diode.

[0216] The power supply circuit shown below is assembled using virtually MOS circuit technology. Field-effect transistors (FIELD-EVERYS) come in n-type and p-type forms, as illustrated. In this case, the power supply circuit is connected between the supply potential VDD and the load. Alternative configurations can be created by changing the channel type of the FIELD-EVERYS transistors and altering their placement between the load and the reference potential or ground potential VG. Individual transistors can also be replaced with bipolar transistors, or assemblies such as current mirrors can be formed using such transistors. A bandgap reference can be used to generate an accurate voltage, from which current can then be supplied by a converter.

[0217] The supply circuit includes a composite reference branch 10 consisting of two parts 10a and 10b that supply a reference current. These parts form part of a current mirror. The reference branch 10a for the first reference current includes two transistors connected in series, an n-type field-effect transistor 12a and a p-type field-effect transistor 11a. The former transistor is connected to the power supply terminal, and the latter transistor is connected to the reference potential. The gate of transistor 12a is connected to the drain terminal so that a constant current can be applied. Transistor 11a copies the current flowing through the reference branch to four transistors connected in series 24 that form a current source with a fixed current for the differential amplifier. The differential amplifier forms a component of the error correction detector 20, and in addition to the current source from transistor 24, it includes an inverting input transistor and a non-inverting input transistor in one branch each, which is connected to the supply potential VDD via a further current mirror 26 consisting of two p-type transistors. The non-inverting input transistor 27 forms the reference signal input 22, and the inverting transistor 28 is connected to the error signal input 21. These two transistors have the same dimensions as the transistor in Miller 26 of this example configuration. However, in each configuration, different gain coefficients may already be provided by geometric dimensions such as channel width and length. This may be necessary when there are also inherent coefficients between the error signal and the reference signal, as will be described later. Such inherent coefficients are obtained from the configuration of the signals (error signal and reference signal) tapped for the current source 30 and the detector 20, as will be described later.

[0218] The controllable current source 30 has a current mirror with an output branch and a reference branch, which simultaneously forms a backup source 40. The reference source 10b is connected to the reference branch input 32. Similarly, this input 32 is connected to a non-inverting transistor 27 and to the reference signal input of the error correction detector 20. In this way, a precise current is applied to the reference branch of the current mirror, and a defined voltage drop is led through the center tap to the input 22 of the error detector. The reference branch 10b includes two transistors connected in series to regulate the current flow through the reference branch of the current mirror of the current source 30 and define a reference voltage or reference signal to the input 22. The gate of transistor 101 is connected to the gate of transistor 11a (not shown here), and thus forms part of the current mirror of the reference source 10. The controllable current source 30 has a supply input to which the supply potential VDD is applied, and a p-type current mirror transistor 34. This transistor is located between the supply input and terminal 32. A capacitor 35 is connected between the gate and terminal 32, so that the voltage of the reference branch is coupled to the gate. This voltage also forms the reference signal for the error detector.

[0219] The reason for using a positive feedback capacitor instead of the normal leads of the current mirror is, in particular, due to the additional frequency compensation for the additional control signal terminal 31 that connects the gate of transistor 35 to the error correction output 21 of detector 20. Therefore, the error correction signal is also supplied to the gate.

[0220] Furthermore, the gate of the transistor is connected to the gate of the output transistor 36 via a switching device 70. This gate is positioned between the supply potential VDD and the output. This copies the current from the reference branch to the output branch 37 of the current source. By appropriately sizing the two transistors 34 and 36, the ratio of the output current to the current flowing through the branch with transistor 34 can be adjusted as needed. For example, if the channel width of the output transistor 36 is 10 times that of transistor 34, the current can be increased by the same multiple, simply by approximation. In the illustration in Figure 23, the output transistor 36 is a single transistor. However, it may be configured with multiple transistors arranged side by side.

[0221] The switching device 70 of the current source 30 is configured to either connect the gate of the output transistor 36 to a fixed potential (in this case, the supply potential) or to the gate of the current mirror transistor 34, depending on the signal. In the first case, the potential VDD blocks the gate of the p-type transistor, so the output transistor 36 is switched without current. In this case, the transistor does not conduct current, so it can be said that the transistor 36 is open. In the second case, the output transistor 36 is closed, and the current is copied to the output via the current mirror transistor 34 with the coefficient described above, and led to the light-emitting diode 60.

[0222] The output of the current source 30 is connected to both the load 60 or the light-emitting diode and a second switching device 70. This switching device 70 applies the voltage of the output of the current source to the error signal input of the error detector 20, or applies a backup signal. This is provided by a backup source 40, which is formed by a p-type output transistor 41 and a transistor 43 connected in series with it. The series connection of the two transistors 41 and 43 is located between the supply potential VDD and the ground potential VG. A central node 42 forms the output for the backup signal. The gate of transistor 43 is led to its drain terminal, thereby connecting to node 42. The gate of the p-type output transistor 41 is connected to the gate of transistor 34. Thus, a current mirror is also formed from transistors 34 and 41. However, here, different coefficients are selected so that the current flowing through this branch is significantly lower than the current flowing through the output branch, by appropriately sizing the output transistor 41.

[0223] The two switching devices 70 operate substantially synchronously, and are configured such that when the gate of transistor 36 switches to the gate of transistor 34, the output of the current source 30 is connected to the error signal input 23 of the detector 20. On the other hand, when the output transistor of the current mirror is switched without current, a backup signal from the backup source is applied to the error signal input, i.e., tap 42 is connected to input 23.

[0224] In the configuration shown here, the backup source is always running; that is, the output transistor always forms a current mirror with transistor 34, allowing current to flow to the backup source branch. In an alternative configuration, a switch operating in the opposite direction to the switching device 70 may also be provided; that is, this switch switches the backup source with no current when, for example, a voltage is applied to the load or current is supplied by the current source 30.

[0225] Here, in the operation of the supply circuit, the switching device 70 is connected such that node 71 is connected to node 72, and at the same time the gates of transistors 34 and 36 are connected to each other. In this case, the current source provides output current for the load. This causes a voltage drop of several volts, for example, 2 to 3 volts, across the light-emitting diode 60. This voltage drop is detected as an error signal by the differential amplifier of the detector 20 and compared with a reference signal. If the current flowing through the light-emitting diode changes, for example due to a temperature change, the error signal also changes, and the detector generates a correction signal for the current mirror at the correction signal output 21 and supplies this to the control signal terminal 31.

[0226] In this way, a correction signal is also applied to the gate of the output transistor 36, and the current is adjusted accordingly. The error detector 20 adjusts the output current mirror so that the saturation voltages of both the inverting transistor 27 and the non-inverting transistor 28 are the same. Using the error correction detector 20 and the current mirror connected to the output, a load-independent current source is formed.

[0227] Light-emitting diodes (LEDs) are often operated using pulse width modulation, so the current flowing through the diode changes at defined intervals, meaning the diode is switched on and off at high frequencies. This pulse width determines the brightness of the diode 60. For this purpose, a current mirror switching device 70 is used. However, when the current is turned off, the error detector 20 resists it for the first time. Therefore, it often falls outside the optimal modulation range. The same thing happens when the current is turned on. Here, the differential amplifier needs a little time to return to its normal control range. Furthermore, oscillations or overshoots may occur, which not only shorten the diode's lifespan but can also be noticeable to the user. A second switching device 70 prevents this by maintaining the error detector within its modulation range via a backup source.

[0228] In this regard, Figure 24 shows the main signal flow. When the diode is off, the gate of the p-type field-effect transistor 36 in the output branch is directly connected to the supply potential VDD. The lower switching device 70 connects the tap 42 of the backup source 40 to the error signal input 23 of the detector 20. The backup source copies the current at a low ratio, and a second transistor connected in series is used to generate the required voltage. This is selected to be close to the expected voltage drop of the load in normal operation. Thus, the error detector is maintained within its modulation range, and the control loop maintains its steady state.

[0229] Figure 25 is a schematic diagram of two simple switching devices. Various other switches can be used. Furthermore, this device can be easily operated using a PWM signal, which may be provided to adjust the brightness of a light-emitting diode, and other suitable switches can be used for other applications. The switching device 70 has a structure similar to a known inverter, but differs in that the transistors shown here again represent transmission gates. Output 71 is connected to an error signal input. Input 74 forms a switching input to which a switching signal, such as a PWM signal, is supplied. Two different types of transmission gates are arranged in series, with output 71 placed between these two transmission gates. The p-type gate 73 has its terminal 73 forming a connection to a backup source. Terminal 72 of the second transmission gate forms a voltage signal terminal.

[0230] Figure 26 shows the signal time diagrams for various signals in the supply circuit under different operating conditions. PWMThis describes a pulse-width modulated signal for operating the light-emitting diode 60. This signal is also applied to the circuit device 70. This is a logic signal that alternates between two states: "High" and "Low". The light-emitting diode is on during the High state for approximately 8μs to 18μs and then for 26μs to 44μs, and off at all other times. The current flowing through the light-emitting diode is I LED As can be seen from the bottom curve represented by this, it follows this switching time.

[0231] In contrast, voltage V LED The voltage changes only slightly between the on and off states. The voltage continues to decrease, and when it eventually reaches a threshold voltage of approximately 1.4V, the current stops flowing, i.e., the light-emitting diode turns off. When the light-emitting diode is turned on, i.e., in a time of 8μs, the voltage drop across the light-emitting diode is essentially the backup voltage or backup signal V H It supports this. When switched on, a small voltage drop is observed in the backup signal, which may be process-dependent, for example, depending on the parameters of the field-effect transistor used. Because different types (p-type or n-type MOS) are used, their switching behavior is not always the same, and residual current may flow during switching time.

[0232] V in This shows the signal transition of the inverting input, i.e., the error signal input 23. Before the switching time of 8 μs, the voltage V is due to the position of the switching device 70. H The voltage is equal to the error signal input voltage, and after turning it on, the voltage is V LED This corresponds to the symbol "=" in Figure 26. H The voltage is selected to be as close as possible to the LED voltage VLED expected during normal operation.

[0233] The error correction detector 20 receives the voltage V of the error signal input 23. in and the voltage V of reference input 22 ipThese are compared with each other, thereby generating a corrected signal Vo. With a switching time of 8 μs, the voltage of the non-inverting input V ip A small dip exists, which increases the small peak in the correction signal. This could be a simulation artifact, but it could also be caused by a sudden change in load at the current source branch. In any case, the correction signal is very small and fast, so it has no effect.

[0234] At the second switching time of 18 μs, no behavior is observed, or if any behavior is observed, it is extremely low. However, under ON regulation, the modulation behavior of the error detector is not significantly impaired, and accurate correction signals are supplied by high-speed feedback, so the output current and voltage are quickly controlled to the desired values ​​and then kept constant. In this regard, the simulation in Figure 26 shows regulation of less than 0.5 μs.

[0235] This proposed power supply circuit provides a high-precision current source, which is particularly suitable for accurate and color-accurate drive control in light-emitting diode (LED) applications. In this regard, known PWM can also be used for contrast adjustment of individual LEDs in pixel matrices and displays. The impact of the switching process on the current source during pulse width modulation is reduced by the proposed measures. As a result, small fluctuations in the operating current of a few percent below the nominal value of the input voltage can be achieved without the switching process affecting stability.

[0236] In some implementations, it is suitable to spatially arrange the current source transistors closely together and strongly thermally couple them to one another. For the backup branch, it is suitable to approximate the backup signal to the voltage drop across the load during operation by providing other means such as Si pn diodes or amplifiers.

[0237] To drive and control the LEDs and pixels of a display or video wall, it is possible to digitally control not only the current flowing to the LEDs but also the switching ratio. Low-power digital driver circuits can drive many optoelectronic elements, especially LEDs, despite their low power consumption.

[0238] Figure 9 shows a schematic circuit diagram of one configuration of a static random access memory, a 6T memory cell, SRAM-6T memory cell 1, which implements two cross-coupled inverters 2 as 1-bit memory. The SRAM-6T memory cell 1 is made of 1.08 μm per bit using 65 nm CMOS technology. 2 ~1.7μm 2 It features a compact memory size in the range of [specify range] and low power consumption in the range of 0.26 μW to 0.37 μW per bit.

[0239] Figure 10 shows a schematic circuit diagram of one configuration of a driver circuit 10 configured to drive an optoelectronic element, which is an LED 11. The driver circuit 10 is fully digital and manufactured using CMOS technology. In this regard, Figure 10 shows only the circuit diagram. The LED 11 is made of a material system suitable for generating light of a desired wavelength, and the circuit may be made of a different material system. In the illustrated function, both elements are in electrical contact. A method for achieving this is disclosed herein.

[0240] The driver circuit 10 implements two cross-coupled NOR gates 12 and 13, which form a first memory cell or latch for controlling the current flowing through the LED 11. The driver circuit 10 includes an additional first memory cell not shown in Figure 10. This additional first memory cell has the same structure as the first memory cell shown in Figure 9 and is used to control the current flowing through further LEDs.

[0241] Each NOR gate 12, 13 has two inputs and one output. The output of each NOR gate 12, 13 is coupled to one of the inputs of the other NOR gate 12, 13. The other input of NOR gate 12 receives the set signal S_i, and the other input of NOR gate 13 receives the reset signal R_i. NOR gate 13 generates a signal Q at its output, and this signal controls the gate of transistor 14. This circuit composed of the inputs R_i, S_i and the output Q of the two NOR gates 12 and 13 corresponds to an RS flip-flop. Therefore, the NOR gates connected in this way can be replaced with the illustrated circuit.

[0242] Transistor 14 turns on / off the current flowing through LED11 according to its gate voltage. This current is generated by transistor 15. The channels of LED11 and transistors 14, 15 are connected in series between the power supply voltage VDD and the ground GND. The driver circuit 10 further implements two pull-up PMOS transistors 16, 17 respectively coupled to transistors 18, 19. Transistors 16, 17 receive the not-S_i signal and the not-R_i signal at their gate terminals respectively.

[0243] LED11 is arranged in a pixel array together with other LEDs. As shown in FIG. 10, each LED is connected to a driver circuit. To enable the selection of row i, transistors 18, 19 are respectively coupled to NOR gates 12, ......

[0244] Figure 11 shows a schematic circuit diagram of one configuration form of the optoelectronic device 30. As shown in Figure 10, the optoelectronic device 30 implements a pixel circuit array 31 including an array of LED driver circuits 10. The array implements, as an example, 2K rows and 2K columns. Each driver circuit 10 is connected to a respective LED. Further, the LED array is made of chips of different III / IV group materials, and each LED in the array is connected to each pixel driver circuit at the drain of the transistor 14 in Figure 10.

[0245] The row decoder and driver 32 sequentially selects rows of row_1 to row_2K. The PWM signal for controlling the current flowing through the LEDs is generated by N readable 8-bit counters 33, where N is 2K in this example. The N counters 33 generate set signals S_i and reset signals R_i (or backup signals of not-S_i and not-R_i) for N columns of pixels simultaneously for each selected row. When the value of the pixel pulse width, that is, 8-bit pixel gray data, is read into the counter 33, the set signal S_i is activated and the pixel stream is turned on, and the counter 33 starts at a pixel clock frequency, for example, between 40 MHz and 100 MHz. When the counter 33 reaches the pixel data value, the reset signal R_i is activated to turn off the pixel stream.

[0246] Further, there is a 9-bit (MSB) counter 34 for generating global or common dimming of the pixel array. In this way, the 9-bit pixel dimming dimming data read into the counter 34 determines the luminance of the background of the pixel array. When the dimming pulse width is 0, row scanning is performed so that the pixels of the row light up. Otherwise, first global pixel illumination is performed, and then row-by-row scanning is performed. The set signal S_i and reset signal R_i generated by the counter 33 and the global or common dimming signal generated by the counter 34 are supplied to N buffers and multiplexers 35 to transmit these signals to the columns of the pixel circuit array 31.

[0247] By combining global dimming data with grayscale data using a video / image signal processor IC or LED driver IC, a separate global dimming pulse is not required, and it is possible to update only the grayscale data row by row. Counters 33 and 34 are controlled by the read_counter signal. In addition, counter 33 receives the clock signal clk. Counter 34 receives the clock signal clk-MSB.

[0248] To gate-control dark pixels, the driver circuit may implement a second memory cell or latch for each LED. Figure 12 shows a schematic circuit diagram of one configuration of the driver circuit 40 based on the driver circuit 10 shown in Figure 10. The driver circuit 40 implements a first memory cell 41 and a second memory cell 42. Both the first memory cell 41 and the second memory cell 42 have a set input S, a reset input R, and an output Q. Furthermore, the reset input R of the first memory cell 41 is connected to the set input S of the second memory cell 42. The outputs Q of the first and second memory cells 41 and 42 are connected to the input of an AND gate 43. The output of the AND gate 43 is connected to the gate of transistor 14.

[0249] As can be seen from the functional timing diagram shown in Figure 12, a global reset is performed at the beginning of each frame, darkening all pixels. Then, a global set signal S_d is applied to the set input S of the second memory cell 42 to make all pixels "normal pixels". Subsequently, the second memory cell 42 of the pixel circuit array is read or reset row by row to implement selectively dark pixels. One configuration of the optoelectronic device implements a spatially averaged pixel bias current. This optoelectronic device implements a global N-bit digital-to-analog converter (DAC) that covers a pixel current range of, for example, 22nA to 1μA. As shown in Figure 13, the spatially averaged bias is generated by adding the same bias currents of the surrounding area.

[0250] The on / off state of the pixel current is controlled by the state of a second memory cell or latch for dark pixels, and by a PWM signal for normal active pixels. Figure 14 shows the timing diagram of the optoelectronic device. Line 1 in the timing diagram indicates the length of one frame. Between frames, content, such as a video sequence, is displayed on the display.

[0251] A global reset is performed at the start of each frame, causing all pixels on the display to darken (see line 2). The dark pixels are then read row by row, ensuring that these pixels remain dark throughout the frame (see lines 3-4). Global dimming is then applied to ensure the background maintains the same brightness (see line 5). Grayscale data is then read, generating a PWM signal that starts at row 1 and ends at row 2K (see lines 6-7). Finally, line 8 shows the state when the pixels are turned on. When the frame ends, the next frame begins. Figure 15 shows a schematic diagram of a further configuration of the driver circuit 50 configured to drive the LED 11. The driver circuit 50 is fully digital and requires even less area than the driver circuit 10 shown in Figure 10.

[0252] In the driver circuit 50, the first memory cell implements an NMOS transistor 51 and a PMOS transistor 52 connected in series between the power supply voltage VDD and ground GND, meaning that the channels of the two transistors 51 and 52 are connected in series. Furthermore, the input of an inverter 53 is connected between transistors 51 and 52. The output of the inverter 53 is connected to the gates of transistors 51 and 52.

[0253] Furthermore, an NMOS transistor 54 and a PMOS transistor 55 are connected in series between the power supply voltage VDD and ground GND. Transistors 54 and 55 receive a set signal S1 and a reset signal not-R1, respectively, at their gate terminals. To gate control dark pixels, the driver circuit 50 implements a second memory cell or latch, which has the same structure as the first memory cell and is also shown in Figure 15. The second memory cell implements an NMOS transistor 56 and a PMOS transistor 57 connected in series, an inverter 58, and an NMOS transistor 59 and a PMOS transistor 60 connected in series.

[0254] Transistors 59 and 60 receive a set signal S2 and a reset signal not-R2, respectively, at their gate terminals. The output of inverter 53 of the first memory cell generates signal Q1, and the output of inverter 58 of the second memory cell generates signal Q2. Signals Q1 and Q2 are supplied to the input of NAND gate 61. Downstream of NAND gate 61 is inverter 62, whose output is coupled to the gate of transistor 14, which turns the current flowing through LED 11 on or off according to its gate voltage.

[0255] From the timing diagram in Figure 15 shown above, it can be seen that a global reset is first performed by applying the reset signal not-R1 to the first memory cell. Next, the set signal S1 is applied to trigger the first memory cell to a High state with output Q1. The first memory cell maintains the High state until it is reset to a Low state by the reset signal not-R1. The timing diagram in the lower part of Figure 15 shows the function of the second memory cell when reading dark pixels. First, the global set signal is applied by signal S2. Next, the pixels in the dark area are read row by row by the reset signal not-R2.

[0256] Figure 16 shows a schematic circuit diagram of a further configuration of driver circuit 70, which is a modification of driver circuit 50 shown in Figure 15. Driver circuit 70 includes the same first and second memory cells as driver circuit 50, but driver circuit 70 does not include a NAND gate for coupling the output signals of the first and second memory cells. Instead, driver circuit 70 includes an additional NMOS transistor 71 connected in series with transistor 54. In particular, transistor 71 is located between transistor 54 and ground GND. The gate of transistor 71 is controlled by the output signal Q2 of the second memory cell.

[0257] Figure 27 shows one configuration of an analog lamp for current control in the form of a control circuit 2500 including a pixel driver. This is made of semiconductor material and utilizes various technologies described herein. Such a concept is based on an analog lamp for light control, implemented with a small number of structural elements, reducing noise through hysteresis during operation, and enabling double buffering. Double buffering allows for longer duty cycles, reducing overall power consumption. This configuration can be particularly advantageous when combined with other power-saving features.

[0258] This control circuit has a pixel driver consisting of a pulse generator 2530 and a column data buffer as an input stage. In this configuration, a common lamp generator 2502, which can also be used for multiple pixels 2506 in a row or column, is part of the control circuit. This control circuit couples its output 2521 to the control input of an adjustable current source for the LED pixel. Based on a pulse signal DW applied to the control input of the adjustable current source, the current source can be selectively activated and deactivated. In response to the pulse signal DW, the LED is turned on or off. In an alternative configuration, the current source may be replaced with a switch or similar element to selectively turn the LED on or off. The pulse length of signal DW corresponds to the brightness of the LED element in the pixel.

[0259] The control circuit 2500 has a row select input 2503 for the row select signal RS and a column data input 2504 for the data signal AV. These inputs are similar to those in conventional approaches and can be used in a similar manner in practice. The control circuit also has a trigger input 2501 for the trigger or "ramp start" signal RaS and a ramp signal input 2505 for the ramp signal.

[0260] Similar to the conventional cell shown in Figure 42, the column data input is connected to the capacitor 2509 via the switch 2510, and data information corresponding to the brightness of the LED is stored in the capacitor 2509.

[0261] Switch 2510 is implemented as a field-effect transistor using Si technology, as described here, but it can also be implemented as a field-effect transistor using Ga or In technology. The gate or control input of switch 2510 is connected to the row select input to obtain the row select signal RS. However, while the conventional approach used the charge stored in the capacitor to directly control the current flowing through the light-emitting device, capacitor 2509 is used as an input buffer together with switch 2510. The output 2511 of the input buffer, in particular the capacitor and switch, is connected to the pulse generator 2530 to generate pulses.

[0262] The pulse generator 2530 has a comparator 2508 which includes, for example, a differential amplifier and an output buffer stage 2507 implemented as an RS flip-flop, and whose operation can be represented by NOR gates and NAND gates. The differential amplifier is implemented using the same technique as the switch 2510. For this purpose, the differential amplifier may include, for example, a transistor as described herein. The inverting input 2511 of the comparator is connected to a capacitor 2509, and the non-inverting input 2512 is connected to a ramp input signal 2505. The comparator 2508 can be selectively turned off to reduce power consumption, as will be described in detail later.

[0263] Comparator 2508 provides a status signal or a comparison result CS at its output. The output of the comparator is directly connected to the reset input R of the RS flip-flop 2507. The set input S is connected to the trigger input 2501.

[0264] The operation of the control circuit will be described in more detail by referring to the various signals shown over time in FIG. 28. For this purpose, assume that a row select signal RS is applied and a certain charge is accumulated in the capacitor 2509. A constant signal IS is applied to the non-inverting input of the comparator (corresponding to reference number 2512). The signal IS corresponds to the brightness of the LED associated with the control circuit.

[0265] At time T1, the trigger signal RaS changes from LOW level LOW to HIGH level HIGH, and subsequently the set input S of the RS flip-flop 2507 also becomes HIGH. At time T3, the trigger signal RaS changes back to the LOW level. The lamp signal Rsig is applied simultaneously with T1. The lamp signal Rsig increases linearly over the time when the trigger is HIGH. That is, the lamp signal Rsig starts from a first value corresponding to LOW and rises to a second level, that is, the HIGH level. The lamp signal Rsig is also applied to the non-inverting input of the comparator. During the period from T1 to T2, the comparator compares the buffered signal IS in the capacitor 2509 with the lamp signal Rsig. While the signal at the non-inverting input is smaller than the inverting input, the output signal applied to the reset input R of the RS flip-flop remains LOW. At time T2, the reset input R receives the rising edge of the result signal CS when the output of the comparator changes from LOW to HIGH. At that time, the lamp signal becomes higher than the buffered signal IS.

[0266] As a result of this transition, the output Q of the RS flip-flop resets the current source control signal DW to a LOW value from time T2. Thus, the time T2 at which the output signal DW turns off the current source again depends on the charge accumulated in capacitor 2509, assuming a uniformly rising ramp Rsig. In this way, the pulse is defined by the ramp signal RSig and the signal IS, and its length essentially corresponds to the period from T0 to T2.

[0267] At time T3, the trigger signal changes from HIGH to LOW.

[0268] Simultaneously, the ramp signal is turned off, and the comparator outputs a "LOW" signal. As a result, both the R and S input signals become LOW. Due to the small hysteresis of the comparator, the transition of the trigger signal for input S is slightly faster, and the flip-flop keeps the output signal DW LOW, regardless of the transition of the signal CS for input R. At time T5, the trigger signal RaS is repeated at input S, and similarly, the ramp signal Rsig is also restarted at its initial value.

[0269] The period from time T3 to time T5 is blanking time for reprogramming the corresponding columns of each row. For this purpose, the row select signal is triggered at time T7, and the column data lines are connected to the capacitor via switch 2510. Capacitor 2509 is charged or discharged to a new value. In this example, capacitor 2509 is discharged to a much smaller value corresponding to a different (lower) brightness. Charging begins at time T7 and ends at time T4, at which point the row select signal RS becomes LOW again and the switch opens. While the cycle of the current row restarts at time T5, another row can be addressed and reprogrammed.

[0270] Because the level of signal IS is relatively low, comparator 2508 quickly changes its output at time T6 of the new cycle. As a result, output Q becomes "LOW" at time T6, which is a much shorter time period than the time period before the trigger signal RaS. Output Q, with control signal DW, controls the current of the LED coupled to that output. The longer output signal DW remains HIGH, the more current flows to the LED, and the higher the brightness of the corresponding color. Comparator 2508, and possibly RS flip-flop as well, may be turned off during reprogramming and blanking times to reduce power consumption. For this purpose, at least the comparator has a power control unit 2520 connected to the trigger input. As long as the trigger signal Rsig is HIGH, comparator 2508 is supplied with current and performs its operation. The comparator turns off in response to the trigger signal during the blanking time.

[0271] In some cases, the blanking time may be significantly longer than the actual duration of the trigger signal, so the entire pulse generator may be turned off.

[0272] In an alternative configuration, referring again to time T2 in Figure 28, the comparator switches its output signal CS from LOW to HIGH as soon as the ramp signal reaches the threshold of the buffered signal IS. Since the trigger signal S is still HIGH, the RS flip-flop switches its output signal to LOW. Thus, regardless of the level of the reset input R, the output Q remains LOW. Therefore, after a reset, the signal of input R may transition and the comparator may turn off. In some modifications, the power control unit 2520 can also be coupled to output Q to control the current supply to the comparator based on the state of output Q.

[0273] When addressing different rows, segmentation or additional ramps can be used. This enables the implementation of spatiotemporal multiplexing, reducing the occurrence of current spikes and minimizing power consumption fluctuations. In this example, a signal is applied to a specific input of the comparator, but those skilled in the art will recognize that the configuration of this principle can be modified. For example, the inverting and non-inverting inputs can be swapped to produce the opposite operation. An RS flip-flop requires two transistors and a resistor, and a small asymmetry can be implemented in the RS flip-flop during design (for example, by adjusting the value of one resistor) to adjust the switching behavior and prevent undefined states.

[0274] In some displays or video walls, individual pixel defects can occur that damage LEDs. Such defects are unavoidable. However, displays or video walls are extremely difficult to repair. Therefore, it has been proposed to design subpixels redundantly, that is, to provide not only multiple subpixels of the same color, but also redundant LED branches through failover. Furthermore, these redundant pixels can also be connected to the same current source. In testing, the functionality of each LED is tested. If the test results show two functioning LEDs, one LED can be specifically deactivated to compensate for the color change or brightness reduction of the other LED due to the different current flow. On the other hand, if a defect is detected, the redundant LED continues to be used.

[0275] Figure 29 shows an example configuration of a proposed device that provides such redundancy and failover simultaneously. This figure shows two pixel cells, each having a first branch and a second branch, with either an LED D1a or D1b. LEDs D1a and D1b are connected to a common reference potential terminal, GND. Their other terminals are connected to electronic fuses Fa and Fb, respectively. For example, these are fuses that blow when the current flowing through them becomes sufficiently large. Furthermore, the second branch, i.e., the branch with fuse Fb and LED D1b, represents an embossed structure element EPT. In this configuration, it is configured as an MSOFET transistor, with its drain terminal connected between the fuse and the LED. Its source contact is a common reference potential, and the gate can be supplied with a select signal Vburn via the embossed signal line EP die. In principle, depending on the circuit, the embossed signal line EP can be used to address, drive, control, or select rows or, alternatively, columns.

[0276] Furthermore, the pixel cell includes a 2T1C circuit with a current driver transistor T1, which is connected on one side to the supply potential and on the other side to the first and second branches and their fuses Fa and Fb. A charge storage means C is electrically connected to the gate and source terminal of the first transistor T1. In addition, the "t1C cell" also includes a transistor T2 connected between the data terminal Vdata and the gate of transistor T1. A select signal can be supplied to its gate.

[0277] For each color of a pixel, two LEDs, D1a and D1b, may be provided, electrically connected in series to electrical fuses Fa and Fb, respectively. In this way, redundancy is provided for all subpixels of each pixel.

[0278] If each LED is electrically connected to a common embossed signal line EP along a row and column, then, for example, each pixel cell in a column may be electrically connected to and addressed to a supply potential terminal VDD by a common supply lead to a switching transistor located on a common carrier outside the active display. This allows each fuse in the column to be activated or blown.

[0279] The following section will explain the operating modes of this circuit in detail.

[0280] In the first case, one of the two LEDs is defective, specifically indicating "OPEN," meaning no current flows through the defective LED. In this case, the test produces the corresponding result, and the other LED is automatically used in each case. On the other hand, there is also the case of "SHORT," meaning a short circuit has occurred. When a short circuit occurs, the resistance through the shorted diode becomes very small, causing the current flowing through each fuse to become significantly larger. As a result, the fuse blows when a SHORT occurs.

[0281] The third case concerns a state where both LEDs function as expected. In this case, the current from the current source is split between the two branches, which can lead to color errors. Here, the occupied wavelength differs depending on the selected current. Therefore, in this case, a signal Vburn (high potential, e.g., VDD) is applied so that the embossed structure element EPT becomes conductive. Transistor T1 is simultaneously and completely switched by the corresponding signals on the data line and select line, and a high potential is applied to the fuse. As a result, a large current flows, destroying fuse Fb and safely disconnecting diode D1b.

[0282] In PMOS technology configurations, the potential and signal polarity are reversed accordingly.

[0283] The fuse may be formed as a metal strip having different widths. For example, it could have a length of 33 μm, a width of 20 μm at one longitudinal end, 9 μm at the other longitudinal end, and 2 μm in a central region with a length of 12 μm. The longitudinal ends may be made square or rectangular and have passages. The longitudinal ends of the square may be formed toward the transistor T1, and the longitudinal ends of the rectangular may be formed toward the light-emitting diode. The material may be, for example, IGZO.

[0284] In particular, in diode circuits where the gate and source are continuously electrically connected, thin-film transistors can be used instead of the metal strips mentioned above. Each LED can have its own thin-film transistor. This can function as both a controllable current source and an electrical fuse. A signal can be used to turn off the LED, for example, by bringing the thin-film transistor to zero potential, which will burn out the thin-film transistor due to the increased current flow. In principle, any commonly known electrical fuse can be used. The fuse will not be destroyed by starting or triggering, but in any case, it is necessary to ensure that the associated LED is not energized.

[0285] In this way, end-of-line testing can be performed without additional steps such as laser cutting. Furthermore, it can be combined with an embossed diode as an embossed structure element.

[0286] Figure 29 shows the adjacent cells of the first pixel cell on the right. Each row can be connected to a select signal line Vsel, an emboss signal line EP, and a data signal line Vdata. The select signal line uses Vsel and Vdata to generate a signal for selecting the relevant row to activate the associated fuse. The emboss signal line EP supplies the fuse blowing voltage V_burn to generate the fuse blowing current (Durchschmelzstrom) I_burn.

[0287] Figure 30 shows a second configuration example of the device design in which the arrangement of the current source and the LED is reversed. Figure 29 shows a configuration with a common cathode, while Figure 30 shows an arrangement with an LED and a common anode.

[0288] The anode terminals of LEDs D1a and D1b are connected to the supply potential terminal VDD. The first current line contact of the first transistor T1 is connected to the reference potential terminal GND. The drain terminal of the first transistor T1 is connected to the common terminals of the electrical fuses Fa and Fb. The select-hold circuit has a charge storage means C connected to the control contact of the first transistor T1 and to the source terminal of the first transistor T1.

[0289] The operation of this arrangement is similar, but the transistor EPT is connected between the fuse Fb and LED D1b and the supply potential. By applying the voltage V_burn to the gate of the embossed transistor EPT via the embossed signal line EP, the electric fuse Fb, which is a blown fuse, can be blown.

[0290] Figure 31 shows a third configuration example of a device with redundant branches of LEDs selectable by a select fuse. In contrast to the configuration in Figure 31, the series connection of the fuse and LEDs is reversed in each branch. Thus, the fuse is directly connected to the supply potential terminal, and the LEDs of each branch are connected to a common base point and current driver transistor T1 on the cathode side. Furthermore, the drain terminal of the embossed transistor EPT is connected between the fuse Fb and LED D1b. Its source terminal is also connected to the current driver transistor T1, which is the common base point of the LEDs. The structure of the 2T1C cell is the same as in the previous figure. To blow the fuse, the embossed transistor EPT and the signal Vburn are bridged to diode D1b, so that a high fuse blowing current flows through the fuse Fb.

[0291] Since the light-emitting diodes here are not commonly connected to the VDD or GND potential terminals, it is not possible to have a common electrode for the LEDs, i.e., to assign one electrode to multiple pixels. This arrangement is suitable, for example, when a common electrode is not required for process technology reasons.

[0292] Figure 32 shows a slightly modified configuration of Figure 29. Here, the transistor is configured as a PMOS, specifically transistor T1, and the charge storage means is connected between the gate and the fixed power supply. The advantage of this configuration is that the voltage across the charge storage means C is independent, in contrast to the configuration of Figure 29, where the voltage across the charge storage means C may vary slightly due to changes in the forward voltage and temperature fluctuations. A similar advantage of being unaffected by temperature fluctuations is also shown in the configuration of Figure 30.

[0293] Figure 33 shows a further alternative configuration of the configuration in Figure 32. The embossed structural element here is an embossed diode EPD, to which one terminal is connected to the second terminal of LED D1b to which the embossed diode EPD is assigned, and the other terminal is connected to an embossed signal line EP that enables addressing. According to Figure 33, the first terminal of the embossed diode EPD is connected between the fuse Fb and LED D1b, and the second terminal of the embossed diode EPD is connected to the embossed signal line EP. The blowing voltage V_burn that blows the electrical fuse is also applied to the latter.

[0294] During operation, the first transistor T1 is switched to select the triggering electric fuse Fb. For this purpose, the data line Data and the select line Sel program the corresponding voltages to the charge storage means C. Unlike normal operation, the VDD terminal is set to 0 volts or a negative voltage. In this case, a voltage V_burn, which is more positive than the VDD voltage, is applied to the emboss signal line EP. In this way, a large current IF or I_burn flows through the electric fuse Fb and the conductively connected first transistor T1 to the emboss diode EPD, triggering the fuse Fb of the selected pixel cell. The fuse Fb blows, and the associated light-emitting diode D1b turns off. Furthermore, to prevent the large current from flowing through the light-emitting diode D1b or D1a and damaging it, the potential of the first potential terminal GND is also greater than 0 volts, ideally equal to the melting voltage V_burn.

[0295] In this configuration example, the current required to trigger the electrical fuse Fb (IF,I_burn) flows in the opposite direction to the current that flows during "normal operation". This method eliminates the need for additional process steps, such as laser cutting, as part of the EOL test.

[0296] Figure 34 shows a configuration with some modifications from Figure 33, except that the orientation of the embossed diode is reversed. Here, the embossed diode is connected on the anode side between the fuse Fb of the second branch and the LED D1b. The arrangement shown in Figure 34 is constructed by a PMOS thin-film transistor as the current driver transistor T1 and a common cathode arrangement for the LED. All the embossed signal lines EP of the display row are connected here. The selection of the triggering electric fuse Fb is performed by switching the first transistor T1. To this end, the charge storage means C is set to a voltage such as oV so that T1 conducts. A positive voltage such as 10 volts is applied to the VDD terminal. The voltage V_burn applied to the embossed signal line EP is a negative value here than the voltage of the supply potential terminal VDD, for example, 0 volts. In this way, a large current I_burn flows through the embossed diode EPD, the electrically blown fuse Fb, and the conductively connected first transistor T1, triggering and subsequently blowing the fuse Fb of the selected pixel cell.

[0297] On the other hand, the potential of the first potential terminal GND should ideally be about the same as the potential of the second potential terminal VDD, so that even though the light-emitting diodes D1a and D1b are connected in reverse, and consequently the first transistor T1 is conducting, there is no risk of a large current flowing through the light-emitting diodes D1b or D1a and damaging them. In this configuration example, the current (IF)I_burn required to trigger the fuse Fd flows in the same direction as it flows during the "normal operation" of the arrangement.

[0298] Figure 35 shows an example of a method for electronically configuring multiple LEDs. In the first step S1, the functionality of each LED in the first and second branches is tested. Several possibilities are possible, but the most common is the following: In this case, both LEDs function as expected. If this is the case, in the second step S2, an emboss signal is applied to the emboss electronic structure element. Then, a current is supplied by a current driver or current source, and this current flows through the conductive current emboss element. In this case, the current is selected so as not to damage the LED but to break the fuse in the corresponding branch. This causes the corresponding branch to become inactive. On the other hand, if a defect is found, only one of the two branches will function. The other is either "OPEN," meaning no current is flowing through the defective branch, or "SHORT," meaning a short circuit has occurred. In the latter case, the increased current and low resistance of this branch may cause the fuse of the faulty branch to blow, thus changing between the SHORT and OPEN states and no longer affecting the function of the entire arrangement structure.

[0299] By the method described above, the embossed signal line can be configured as a global line connected to all pixels. Addressing is performed by supply leads via transistor circuits on a panel outside the active display, and by select leads of the charge storage means of the 2T1C cell and corresponding programming.

[0300] In this way, the wiring effort is reduced. Similarly, the number of required layers or films can be reduced, which can lead to cost savings. However, the switching transistors must be configured so that they can carry the current through the column. Furthermore, power loss in the panel or common carrier increases during this process.

[0301] Figure 36A provides a general overview of the digital and analog concepts of the three main parts of the LED display unit arrangement structure having this function. Sections I and II relate to the analog region of a display or video wall in which multiple pixels are arranged in rows and columns. Each pixel 141 may consist of subpixels of different colors, or different colors can be obtained using display units with pixels of the same size. In this example configuration, the LED display unit is implemented as a monolithic display unit including an integrated LED pixel on or within a first substrate carrier, but other configurations, particularly those disclosed herein, are also possible.

[0302] In some cases, the first substrate carrier also includes the circuitry of analog section II. Alternatively, the LED substrate is thinner and has multiple contacts on its underside. In this case, the underside contacts are bonded to the carrier containing analog section II, or otherwise mounted. Alternatively, analog section II can be grown on a thin substrate with LED pixels mounted on the opposite side. This approach can reduce misalignment between the analog section and the LED pixels. On the other hand, there is a need for material systems suitable for the integration of analog circuits.

[0303] The analog section II of this arrangement structure includes a control circuit for the current flowing through each pixel. For this purpose, each pixel 141 has its anode contact connected to a common source potential 1411. The cathode of each LED pixel is connected to an adjustable driver, which in this case is implemented as a current source 142, and this current source is also connected to terminal 1412 integrated in section II. Thus, a common anode contact is realized in this configuration. The cover electrodes disclosed in this application can provide such a function. However, another case exists in which a common cathode exists. In this case, the LED is placed between the cathode potential terminal 1412 and the current source. The advantages of such an arrangement structure are that the supply voltage can be kept relatively low and the LED does not need to handle a large input voltage.

[0304] Section II also includes a reference current source 1410, such as a temperature-stabilized current mirror, which provides the same reference current to each current source 142. Although this example shows only one current source, multiple reference current sources can be used to provide separate reference currents to different pixels. For example, each pixel row may be assigned to a reference current source. If such reference current sources are switchable, the current sources for each row can be periodically switched on / off, which leads to a reduction in power consumption. In this configuration, Section II is manufactured from polysilicon and therefore includes a different material system than the LED realization in Section I.

[0305] In addition to the reference current supplied to each current source 142, the current sources also include switching inputs for operating each pixel separately after selective operation at each current source. As described, the overall power consumption is further reduced by switching the current sources using PWM technology to adjust the brightness of individual pixels. The PWM signal is generated in the digital section III of this arrangement.

[0306] Digital section III includes a clock input CLK and a data input DAT. The data input DAT is coupled in series to a 12-bit shift register 148. The shift register receives the input data stream and stores the corresponding word in a 12-bit memory 147. The 12-bit memory may have circuits such as flip-flops for storing the 12-bit word in memory. Each of these memories is coupled to the other input of comparator 144. In this way, the brightness values ​​of an entire row can be temporarily stored in the flip-flops of memory 147 with a single data stream.

[0307] The input CLK clock signal defines the clock for counter 149 and supplies a 12-bit counter word D0..11. The counter words D0..11 are applied to the respective comparators 144 connected to the current source 142 of each LED pixel. In alternative configurations, other structural elements, such as different gate combinations, may be used as needed to check whether the counter words D0..D11 are smaller than the word in the connected memory.

[0308] In the operation of this arrangement, the comparator 144 compares the counter words D0..D11 with the memory words, i.e., the contents of the 12-bit memory. Depending on the result, for example, the comparison using the comparator indicates whether the counter words D0..S11 are greater than or less than the memory words, and the current source is turned on or off. In other words, the comparison using the comparator provides a pulse width based on the clock signal of the counter 149 for driving each pixel. For example, the first pixel in the chain diagram is intended to have a dark value, i.e., be off, and the second pixel is intended to have a bright value, i.e., be fully on. The data stream then consists of a string of two related words, 0s and 1s, in the form of "0000000000001111111111111". Each word is stored in one of the two memories 147 and then passed in reverse form to the comparator 144. This comparison is performed by the comparator. The driver remains on as long as the counter word D is smaller than the memory word M (therefore, in the example using the inverted comparator, "111111111111" is compared to "000000000000").

[0309] LED display configurations or video walls contain various components with differing requirements and constraints, making it difficult to implement them using a single semiconductor material.

[0310] Figure 36B shows another configuration of three parts of the LED display arrangement having this function. The first part is substantially the same as the corresponding part I of Figure 36A, but part II has a slightly different configuration. Part II includes a demultiplexer DEMUX that switches between different pixels using a higher clock synchronization signal Sync. The frequency of this signal Sync is higher than the refresh rate and depends on the number of signals O1 - O3 generated by the demultiplexer DEMUX. In one configuration, the demultiplexer controls all the pixels in a row or a column. In an alternative configuration, a demultiplexer may be used for each sub - pixel of a pixel. It is also possible to combine these. Thus, the number of necessary contact areas between part II and part III can be reduced.

[0311] On the other hand, part III includes a multiplexer between the output of each comparator Comp.D>M and the demultiplexer of the second part II. The synchronization signal Sync is the same as in the case of the demultiplexer of part II and is generated commonly. Another difference when compared with the configuration of Figure 36A is that the counter word (D0..D11) that determines the PWM modulation of the individual comparators is supplied directly to the individual comparators instead of commonly. In contrast to the configuration of Figure 36A, the implementation of the multiplexer and the demultiplexer has the advantage that the number of interconnections, that is, the connections between the purely digital part III and part II can be reduced. On the other hand, between part III and II, an additional high - frequency synchronization signal needs to be routed through any of these interfaces.

[0312] Figure 36C shows a functional circuit diagram of a known comparator configuration that can be used partially in principle in the configurations of Figures 36A and 36B. This circuit represents a 2 - bit comparator, but can be extended up to several bits. In practice, it is also possible to implement it by omitting the inverted input. Further, since the comparison with the counter word is made, the implementation of the circuit part A>B or A<B is sufficient.

[0313] Figure 36D is a time diagram of different counterwords 1D-3D and memory registers used, for example, to generate output signals. Counterwords D0-11 are time-shifted, with each timeword starting at the point when the previous timeword has passed. Output signals O1-O3 are generated using a comparator or OR function and are supplied to a multiplexer.

[0314] Because LED display configurations involve various components with differing requirements and constraints, it is difficult to implement them using a single semiconductor material.

[0315] Figure 37A shows an exemplary cross-sectional view of a display or video wall to illustrate various aspects of the contact and wiring profiles of individual parts. Similar to Figures 37A or 339B, the display includes an LED section I, an analog section II, and a digital section III. The LED section is based on GaN, InGaP, or other semiconductor material suitable for blue, red, or green light emission. LED section I includes a common cathode or anode (+) contact layer 1411, which extends over the surface and connects each active region of the LED pixels 141. Not shown are additional extraction structures or photoshaping structures on the surface of layer 1411. These may include photonic structures or converters, etc.

[0316] Since the pixels are arranged on a substrate and are optically and electrically isolated from one another, their light emission does not interfere with that of adjacent LED pixels, and each pixel can be controlled independently. For example, LED pixel 141 can be implemented using the current-limiting doping described above. In this case, the doping restricts the flow of current to a smaller region. The doping changes the band gap, effectively confining charge carriers. Examples of such structural measures, including confinement, to improve quantum efficiency and / or radiation patterns are disclosed elsewhere in this specification. The pixels may include LED nanorods arranged in a slot-type antenna structure, as also stated above. Ingots or other LED structures disclosed in this specification are also conceivable.

[0317] The lower side has a partially insulating material to avoid leakage current. The surface is shaped such that region II is aligned so that it is mainly located below each pixel element. Each LED pixel has a contact surface facing region II, which forms a connection with region II of the LED display.

[0318] The analog section II of the display in Figure 37A can be mounted from or based on the same semiconductor material system. For example, active and passive elements used in the current source can be mounted on GaN, InGaP, or InAlP systems. In such cases, elements can be formed using several conventional deposition techniques. This has the advantage that the contacts of the LED pixels at the interface of section I can be easily aligned with the conductor tracks in section II. Distortion due to differences in temperature coefficients can also be minimized. Alternatively, section II can be formed from a different semiconductor material. For example, polycrystalline silicon or amorphous silicon structures are suitable and are understood to form small components. The two sections may be formed separately, aligned, and interconnected. As a further option, polysilicon material can be deposited on the lower surface layer by various growth processes, and then the necessary circuit components can be formed. One or more sacrificial layers can also be mounted to reduce voltage. Furthermore, a polysilicon layer may be formed first, and then LED pixels may be formed using the desired material system. In this example, different material systems are used for region II and region I, but they can be manufactured together by adjusting parameters such as expansion coefficients.

[0319] For this purpose, region II is fabricated from polycrystalline silicon. Polycrystalline or amorphous silicon structures are well known, especially for forming small-scale components. For this purpose, polysilicon material is deposited on a suitable carrier, where the required components are formed. To suppress thermal expansion, several intermediate or sacrificial layers are provided; these layers do not take over any further function but are regulated thermally or by different crystalline structures. Such layers are also present between region II and region I, where modifications to the material system intended for LED pixel fabrication are made. Subsequently, the LED pixels are formed.

[0320] Alternatively, all parts can be formed separately, aligned, and then bonded together.

[0321] Depending on the complexity, part II includes one or more transistors that are part of a current source or switch, as shown in Figure 37A with element 151 and coupling layer 152. The coupling layer 152, positioned on several layers of part II, connects contacts on the surface of part II to various components within part II. For example, the contacts 165s of transistor 152 are connected to the upper contact and the corresponding LED via this coupling layer. Similarly, a gate contact 169 that controls transistor switching or resistive behavior is coupled to a contact interface 153 on the bottom surface of the part adjacent to digital part III.

[0322] Digital section III is silicon-based and contains several digital circuits 170. Digital section III is typically formed separately and electrically connected to analog section II in a bonding step. Forming the digital and analog sections separately allows for the use of optimized manufacturing techniques and enables testing of the analog and LED sections before bonding to the digital section. Similar to the analog section, digital section III has several intermediate connections for digital and analog signals. Current can also be supplied to digital section III.

[0323] Various assemblies and implementations, in one aspect, may involve integrating transistors within the analog portion to form a current source and control circuit. Figures 38 and 39 show various examples of implementing field-effect transistors within semiconductor materials.

[0324] Figure 38 shows an inverted stacked transistor made of amorphous silicon. This transistor has an insulating gate layer 155 made of SiN on top of a gate contact 156. Since the gate contact 156 is formed by a small protrusion, the gate layer 155 follows this protrusion and has a central region 157 and two inclined side walls 158. A layer of amorphous silicon 154 is formed on top of this gate layer, which also has a central region and two inclined surfaces. The surface of the amorphous layer 154 may be doped with a high concentration of n-type to form a highly conductive amorphous silicon 151 highly n-type doped layer. Alternatively, the highly n-type doped layer 151 is applied on top of layer 154.

[0325] Finally, a metal layer is applied to the n-type doped layer 151, extending to the side edges of the silicon layer 154 and the SiN layer 155. The gap between the metal layer and layer 151 divides the structure, thereby forming the source and drain contacts. In particular, metal layer 152 forms the drain contact of the field-effect transistor, and metal layer 153 forms the source contact. In this case, a conductive channel is formed in the polysilicon layer in the central region between the source and drain. The highly concentrated n-type doped polysilicon layer 151 provides good electrical connectivity with the channel in layer 154. This structure makes it possible to contact the gate from the side other than the source and drain using only a small amount of space.

[0326] Figure 39 shows two examples of space-saving polysilicon transistors. These transistors are formed on a glass carrier having an SiO2 layer grown as a base substrate. Each transistor has two highly doped n-type polysilicon regions 165s and 165d separated by an undoped polysilicon layer 170, which is located between regions 165s and 165d. A less doped drain region 166 is provided between the polysilicon 170 and the drain region 165d, adjacent to the drain region.

[0327] Alternatively, a gold-doped region 167 is formed between the polysilicon 170 and the drain region 165d. In this case, the source 165s, drain 165d, and undoped region 170 are completely covered by an SiO2 layer extending over the respective sidewalls of regions 165s and 165d. Holes are provided in 165s and 165d for accessing the source and drain regions. These holes are filled with a metal, such as Al, to create electrical contacts. These contacts extend beyond the sidewalls of the SiO2 layer, thus increasing the area for contact. In the central part of the polysilicon layer 170, a gate is formed by depositing an aluminum layer 169 on top of an insulating SiO2 layer. The gate 169 is electrically insulated from the respective metal contacts of the source and drain.

[0328] In conventional circuits that control LED displays, pixels are arranged in addressable rows and columns. Each pixel consists of either an LED of a specific color or a triplet of three different LEDs. In the latter case, it may refer to a pixel that includes three subpixels, each subpixel equipped with an LED of a specific color.

[0329] Referring again to the example in Figure 36A or 339B, Figure 37B shows various configurations for connecting an LED structure to a digital circuit section. The two parts here are based on different material systems or technologies. In each case, the upper first part contains LED elements or pixels or subpixels arranged in rows and columns. Different material systems or technologies are used depending on the desired color, and here, exemplarily, the materials InGaN and InGaAlP are cited. In the first example, the wafer or LED structure is connected to a crystalline silicon-based wafer using a W2W (wafer-to-ware) process, which includes the digital circuit section and, if necessary, the analog section. In the example in Figure 36B, part I is realized on the upper wafer, and the lower wafer contains parts II and III. In the second example in Figure 37B, a thin film layer of polycrystalline silicon is deposited at a low temperature on the underside of the first wafer having part I. This part provides a pure interconnect for connecting to the digital section III, or additionally houses components such as driver circuits for driving and controlling the LEDs. In these two examples, wafers are bonded together to create the desired display or matrix. In a third example, an alternative configuration provides individual chips with digital circuits, which are in an operational coupling relationship with part II. These chips include, for example, row and column drivers for driving and controlling parts of the display.

[0330] In addition, Figure 41 shows a configuration that will be described in detail below. In this way, each part of the display can be driven and controlled separately. Furthermore, by separating the manufacturing in this way, even if a defect occurs in the digital circuit elements of part III, the defective circuit can be isolated individually without having to replace the entire wafer.

[0331] Within the analog section, new concepts are needed to realize the concept of digital drive control. In conventional circuits for controlling LED displays, pixels are arranged in addressable rows and columns. The same principle can be applied here. Each pixel has an LED of a specific color, or a triplet of three different LEDs. In the latter case, it can also be called a pixel if it contains three subpixels, each with one subpixel equipped with an LED of a specific color.

[0332] Figure 40 shows a schematic diagram of the elements necessary to address a conventional LED display. Each pixel contains three LEDs of different colors, but for simplicity, only one color type is shown. Pixels are arranged in addressable columns and rows. The display has a pixel matrix 1800 with 1920 pixels per row and 1020 columns per row. The pixel matrix was assembled monolithically. This display has multiple row drivers 1802 and multiple column drivers 1803 to individually address each pixel of the pixel matrix. Any type of driver can be embedded in the matrix or provided as an external component coupled to the matrix via an interface. Combinations are also possible.

[0333] Each row driver 1812 has an individual driver device, which is coupled to the corresponding lead wires 1805a, 1805b and drives current through these lead wires. Similarly, each column driver has a driver element 1813, which is connected to data lines 1804a, 1804b. Pixel drivers 1801 are located at the intersections of rows and columns. Pixel drivers 1801 are connected to both rows and columns and drive the associated pixels.

[0334] This display includes control and address signals from external components, two of which, DATA and SYNC, are described here. The latter signal, SYNC, is used to synchronize the row driver and column driver with each other, avoiding artifacts and enabling clean programming. By addressing the corresponding row, the pixels associated with that row are selected. The DATA signal is then applied to the corresponding column to program each pixel driver 1801 of the selected row.

[0335] In the case of displays with a high pixel count, the programming signal frequency may become too high with conventional display programming clocks. For example, in the display shown in Figure 40, the programming frequency per bit / line can be in the range of several MHz, depending on the color depth of each subpixel. For example, with a 10-bit brightness depth corresponding to 1024 different illumination values, the programming frequency for 1080 display lines and a frame rate of 60Hz would be approximately 66MHz.

[0336] The table below shows the programming signal frequency and the programming time per bit / line (in μs). As color depth or illumination depth increases, the PWM time units for programming increase, and therefore the programming frequency also increases.

[0337] [Table 1]

[0338] Especially with a high number of color bits or illumination bits (i.e., 12 or 14 bits), the programming time becomes extremely short, placing a heavy load on the corresponding row and column drivers. In extreme cases, such as when a single pixel changes from white to black or vice versa, the column driver must reprogram (reload) the pixel in a matter of nanoseconds. For comparison, state-of-the-art DDR4 RAM operates at an internal frequency of approximately 800MHz to 1.5GHz, which is within the programming frequency range for 14-bit illumination depth.

[0339] To lower the programming frequency, programming can be performed using the rising and falling edges of the clock, similar to how it's done with memory. It's also possible to segment the display to divide the display matrix. Depending on the manufacturing technology, segmentation allows individual segments to be tested separately and replaced if defects are found.

[0340] Figure 41 shows an example of a 1920 x 1080 pixel display segmented into a 2 x 2 matrix to create sub-displays. Each sub-display 1800a-1800d contains a 960 x 540 pixel matrix. Similar to the display in Figure 40, each sub-display has its own column and row drivers 1802a-1802d and 1803a-1803d. DATA and SYNC signals are supplied to each segment. As the number of rows decreases, the programming frequency also decreases accordingly. Further segmenting the columns as in Figure 41 reduces the requirements for the column drivers and lessens the load per programming cycle. The following table shows an example of programming time and programming frequency when there are 108 display rows in one segment (there are a total of 10 such segments, and the refresh rate is also 60Hz).

[0341] [Table 2]

[0342] As shown in the table, segmentation reduces the number of rows, resulting in programming time and programming frequency requirements being approximately one-tenth of the number of segments. Each segment is implemented in a similar manner. Each pixel matrix 1800, 1800a to 1800d contains rows and columns where the pixel drivers and light-emitting devices are located.

[0343] Figure 42 shows an example of a conventional pixel driver, such as a 2T1C structure, in which the current flowing through the LEDs is controlled by a programmed charge during the display blanking time. The driver is located at the intersection of row line 1805 and data line 1804. Furthermore, the power supply voltage V DD and current I DAC A supply line 2002 that provides current is coupled to the light-emitting device 2004 via a driver transistor 2003. In this way, the driver transistor 2003 acts as a controllable current source. The current flowing through the driver transistor 2003 is controlled by the 1T1C structure 2002. In particular, the field-effect transistor M2 functions as a switch, with its gate connected to a row select line for programming.

[0344] When activated by the "HIGH" signal on the row select line, transistor M1 closes, and data line 1804 charges capacitor C1 to the desired level. During this programming, the supply line is off, so the light-emitting device may be effectively off. This prevents various artifacts during programming. After reprogramming, transistor M2 opens again, and the charge stored in the capacitor drives current transistor M1, allowing current to flow to the light-emitting device. This current corresponds to the stored charge and therefore to the desired illumination level.

[0345] Figure 43 shows a circuit diagram of a conventional column driver or data driver. The driver has a digital section and an analog section that drive the corresponding data lines. Alternatively, a dedicated driver for the data lines can be driven with this output. In addition to the current supply connections for GND, VDD, and VSS, further control signals CLK and DIR are supplied. Digital values ​​of different colors R, G, and B are stored in a temporary memory buffer. The digital values ​​are transferred and processed by a level shifter and supplied to the digital-to-analog converter. The DAC can correct some values ​​using a separately generated correction signal Vg-cor. After being converted to an analog signal, it is stored in an output buffer and then applied to the output buffer. The analog RGB signals are then applied to the data lines. Although only three data output lines are shown here, a column data driver supplies signals to all data lines of the display matrix.

[0346] Figure 44 shows an example of a conventional row driver. This driver has a shift register that receives CLK and DIR signals and is coupled to multiple logic AND gates via a level shifter. The gates also receive an ENABLE signal, in which case the corresponding output of the output buffer becomes HIGH. During operation, the shift register shifts a bit for each CLK signal and selectively applies a HIGH signal to one of the corresponding gates. The ENABLE signal is required to globally activate row selection during reprogramming.

[0347] In the following, various devices and arrangements, as well as methods for manufacturing, processing, and operating them, are described again as illustrative subjects. The following subjects present various aspects and configurations of the proposed principles and concepts, which can be combined in various ways. Such combinations are not limited to those shown below.

[0348] 1. A device for electronically driving and controlling LED pixel cells, particularly those created using NMOS technology, - Data signal lines, threshold lines and select signal lines, - An LED electrically connected in series with a dual-gate transistor between the first potential terminal and the second potential terminal, - The dual-gate transistor described above has its current line contacts positioned between the terminals and potential terminals of the LED, and the first control gate of the dual-gate transistor is connected to the threshold line, and the LED and - A select-hold circuit comprising a second control gate of the dual-gate transistor and a charge storage unit connected to the current line contact of the dual-gate transistor and also to a control transistor having a control terminal connected to the select signal line. A device that has this feature.

[0349] 2. The device according to Subject 1, wherein the dual-gate transistor includes a back-gate transistor, and the back-gate forms the first control gate.

[0350] 3. The device according to Subject 1 or 2, wherein the first control gate of the dual-gate transistor is configured to adjust the threshold voltage.

[0351] 4. The device according to any one of the preceding subjects, wherein the dual-gate transistor has thin-film transistors having two opposing control gates.

[0352] 5. A device according to any one of the preceding subjects, configured such that a switching signal (PWM signal) is applied to the threshold line during operation.

[0353] 6. The device according to any one of the preceding subjects, wherein the first terminal of the LED is connected to the first potential terminal, the dual gate transistor is positioned between the second terminal of the LED and the second potential terminal with its current line contact, and the charge storage unit is connected to the second control gate of the dual gate transistor and also to the second terminal of the photoelectronic structure element.

[0354] 7. The first terminal of the LED is connected to the second current line contact of the dual gate transistor, and the second terminal of the LED is connected to the second potential terminal. The dual-gate transistor described above is arranged with a current line contact between the first terminal of the LED and the first potential terminal. The device according to any one of the aforementioned subjects, wherein the charge storage unit is connected to the second control gate and the first potential terminal of the dual-gate transistor.

[0355] 8. - The first terminal of the above LED is connected to the first potential terminal, - The dual-gate transistor is arranged with a current line contact between the second terminal of the LED and the second potential terminal. - The device according to any one of the preceding subjects, wherein the charge storage unit is connected to the second control gate and the second potential terminal of the dual-gate transistor.

[0356] 9. The device according to any one of the preceding subjects, wherein the select-hold circuit includes a further control transistor, which is connected in parallel with the LED, and the control terminal of the control transistor is connected to a select signal line.

[0357] 10. The device according to Subject 9, wherein the dual-gate transistor is formed solely as a transistor having a gate that provides the second control gate.

[0358] 11. The charge storage unit is connected to the second control gate and the first potential terminal of the dual-gate transistor, and further, A temperature compensation circuit that provides negative feedback based on the detection of the forward voltage by the LED mentioned above. The device according to any one of the aforementioned subjects, wherein the above temperature compensation circuit is configured to send a signal at a threshold line on the output side.

[0359] 12. The device according to Subject 11, wherein the temperature compensation circuit is juxtaposed with the dual-gate transistor and includes a control path having two paths connected in series.

[0360] 13. The device according to Subject 11, wherein the threshold line is connected to the first control gate of the dual-gate transistor from a node between two controlled paths provided by a third control transistor and a fourth control transistor.

[0361] 14. The device according to Subject 13, wherein the control terminal of the fourth control transistor is connected to the second potential terminal.

[0362] 15. The device according to any one of Subjects 11 to 14, wherein the temperature compensation circuit includes a second charge storage unit connected to the control terminal of a control transistor providing one of the two paths and to the first potential terminal.

[0363] 16. The device according to Subject 15, wherein the second data signal line is coupled to the second charge storage unit and the third control transistor for programming a negative feedback coefficient.

[0364] 17. The device according to Subject 16, wherein the above coupling is constructed via a fifth control transistor driven and controlled by a second select signal line.

[0365] 18. The device according to any one of Subjects 11 to 14, wherein the temperature compensation circuit is connected to a second potential terminal via a third control transistor.

[0366] 19. A device according to any one of subjects 11 to 14, wherein a fifth control transistor is connected in parallel with the LED, and a switching signal (PWM signal) is applied to the control terminal of the control transistor during operation.

[0367] 20. A device described in any one of the preceding subjects, wherein the above transistor is configured as a field-effect transistor using NMOS technology.

[0368] 21. A method for operating any one of the devices described in the above subject, wherein the LED is color-controlled by applying an analog data-driven control signal to the LED via the select-hold circuit using a select signal, and the brightness of the LED is controlled by acquiring a pulse-width modulated signal.

[0369] 22. A driver circuit for driving multiple optoelectronic elements, Multiple first memory cells, each having a set input, a reset input, and an output. Includes, Each first memory cell is triggered to a first state by the set signal of the set input at the output, and maintains the first state until it is reset to a second state by the reset input. A driver circuit in which the above output of each first memory cell is configured to control one of each of the optoelectronic elements.

[0370] 23. The driver circuit according to Subject 22, wherein each of the first memory cells supplies a pulse-width modulation (PWM) signal at its output, and the PWM signal controls a switch configured to turn on / off the current flowing through each optoelectronic element.

[0371] 24. A driver circuit according to any one of the preceding subjects, wherein each of the first memory cells comprises two cross-coupled NOR gates or two cross-coupled NAND gates.

[0372] 25. A driver circuit according to any one of the preceding subjects, wherein each of the first memory cells includes an NMOS transistor and a PMOS transistor connected in series, and an inverter having an input connected between the NMOS transistor and the PMOS transistor and an output connected to the gates of the NMOS transistor and the PMOS transistor.

[0373] 26. A driver circuit as described in any one of the preceding subjects, further comprising a plurality of counters, each configured to activate a set signal when a data value is loaded into each counter, and to activate a reset signal when each counter reaches the loaded data value.

[0374] 27. A driver circuit according to any one of the preceding subjects, further comprising a common counter configured to generate a common dimming signal for the plurality of photoelectronic elements described above.

[0375] 28. A driver circuit according to any one of the preceding subjects, further comprising a plurality of second memory cells, each second memory cell coupled to one of the respective first memory cells, and configured to override the output signal of each of the respective first memory cells as necessary, so that each of the respective optoelectronic elements remains off.

[0376] 29. Optoelectronic devices, Multiple photoelectronic elements, A driver circuit for driving multiple optoelectronic elements described in any one of the aforementioned subjects and Optoelectronic devices, including optoelectronic devices.

[0377] 30. The following steps are performed in the specified order within the frame: - Step to turn off all photoelectronic elements; - A step of controlling the photoelectronic element that goes dark during the frame using the second memory cell described above; - A step of controlling the current flowing through the photoelectronic element using the first memory cell described above. A method for operating the optoelectronic device described in Subject 29, including the method described in Subject 29.

[0378] 31. The method according to Subject 30, wherein common dimming of the photoelectronic element is performed before controlling the current flowing through the photoelectronic element with the first memory cell.

[0379] 32. A control circuit for adjusting the brightness of at least one LED, - A control terminal in which the first terminal is connected to the first potential and - A charge storage means connected between the control terminal and the first potential, which forms a capacitive voltage divider with a capacitance defined between the control terminal and the first potential, - A control element configured to apply a control signal to a control terminal during a first period, wherein the current flowing through at least one LED is adjustable during the first period based on this control signal. Includes a current driver element equipped with, During the second period following the first period described above, the current flowing through the LED is determined by the reduced control signal formed by the control signal during the first period and the capacitance divider. The control element is arranged to supply a first control signal or a second control signal during the first period to cause the LED to operate at at least two different brightness levels.

[0380] 33. The control circuit according to Subject 32, wherein the current driver element includes a field-effect transistor, the gate of which forms a control terminal, and the defined capacitance is a gate-source capacitance predetermined by design.

[0381] 34. A control circuit according to any one of the preceding subjects, wherein the reduced control signal applied to the control terminal during the second period is obtained based on the control signal during the first period, the capacity of the charge storage means, and the ratio of the sum of the capacity of the charge storage means and the defined capacity.

[0382] 35. A control circuit according to any one of the above-mentioned topics, characterized in that the control elements are arranged to drive the first and second periods at a repetition frequency of 60 Hz or higher.

[0383] 36. A control circuit according to any one of the preceding subjects, wherein the control element includes a control transistor, and the first and second periods can be adjusted by a signal at its control terminal.

[0384] 37. A control circuit according to any one of the preceding subjects, wherein the ratio of the second period to the first period is in the range of 300:1 to 100:1, particularly in the range of 100:1.

[0385] 38. A control circuit according to any one of the preceding subjects, configured to operate the LED at a first dim brightness level when the voltage of the first control signal is within a first voltage interval, and to operate the LED at at least a second bright brightness level when the voltage of the second control signal is within a second voltage interval that is at least partially higher than the first voltage interval.

[0386] 39. The control circuit according to Subject 38, characterized in that the first voltage interval is in the range of 1.3V to 4.5V.

[0387] 40. The control circuit according to Subject 38 or 39, characterized in that the second voltage interval is in the range of 4.0V to 10.0V.

[0388] 41. A method for adjusting the brightness of at least one LED connected to a current driver element, which has a control terminal whose first terminal is connected to a first potential, and which has a charge storage means connected between the control terminal and the first terminal, forming a capacitive voltage divider with a capacitance defined between the control terminal and the first potential, the following steps: - A step of adjusting the current flowing through at least one LED during the first period by applying a control signal to the control terminal during the first period, - The step of adjusting the current flowing through the LED by turning off the control signal during the second period following the first period, thereby reducing the current flowing through the LED by the reduced control signal formed by the control signal during the first period and the capacitive voltage divider. Methods that include...

[0389] 42. The method according to Subject 41, wherein the reduced control signal applied to the control terminal during the second period is obtained from the control signal during the first period based on the capacity of the charge storage means and the ratio of the sum of the capacity of the charge storage means and the defined capacity.

[0390] 43. A method describing any one of the aforementioned subjects, wherein the ratio of the second period to the first period is in the range of 300:1 to 100:1, particularly in the range of 100:1.

[0391] 44. The method described in any one of the preceding subjects, wherein the LED is operated at a first dim brightness level when the voltage of the first control signal is within a first voltage interval, and the LED is operated at at least a second bright brightness level when the voltage of the second control signal is within a second voltage interval that is at least partially higher than the first voltage interval.

[0392] 45. The method described in any one of the preceding subjects, wherein the control signal is derived from a digital control word having n bits, the n bits corresponding to a second control signal, and the least significant m bits corresponding to the first control signal.

[0393] 46. ​​Use of a control circuit described in any of the preceding subjects for driving and controlling an LED, LED arrangement structure, or LED module described in any of the preceding subjects.

[0394] 47. A supply circuit, - An error correction detector having a reference signal input, an error signal input, and a correction signal output, - A controllable current source having a current output and a control signal terminal, wherein the control signal terminal is connected to a correction signal output to form a control loop for the controllable current source, and the current source is configured to supply current to the current output in response to a signal from the control signal terminal, - A backup source having an output configured to supply a backup signal, - A switching device configured to supply either a signal derived from the current of the current output or a backup signal to an error signal input, with the current output of the current source further isolated in response to a switching signal. A supply circuit, including the supply circuit.

[0395] 48. The supply circuit described in Subject 47, wherein the above backup signal substantially corresponds to the signal derived from the current signal.

[0396] 49. A supply circuit according to any one of the preceding subjects, wherein the controllable current source includes a current mirror having a switchable output branch connected to the current output.

[0397] 50. The supply circuit according to Subject 49, wherein the output branch includes an output transistor, and the control terminal of the output transistor is connected to a fixed potential to open the transistor via the switching device in response to a switching signal.

[0398] 51. A supply circuit according to any one of the preceding subjects, wherein the controllable current source has an input branch capable of supplying a reference current, and the input branch has a node connected to the reference signal input of an error correction detector.

[0399] 52. A supply circuit according to any one of the preceding subjects, wherein the controllable current source includes a current mirror, and the control signal terminal is connected to the control terminal of the output transistor of the current mirror.

[0400] 53. A supply circuit according to any one of the preceding subjects, wherein the error correction detector includes a differential amplifier, the two branches of which are connected to each other at the supply potential via a current mirror.

[0401] 54. The supply circuit according to Subject 53, wherein the two branches of the differential amplifier each include an input transistor having different geometric parameters.

[0402] 55. A supply circuit according to any one of the preceding Subjects, wherein the backup source includes a voltage generating element coupled to its output such that the backup signal substantially corresponds to a signal derived from the current signal.

[0403] 56. A supply circuit according to any one of the preceding subjects, wherein the backup source includes a series circuit consisting of a current supply element and a voltage supply element, and the output is located between the two elements.

[0404] 57. A supply circuit according to any one of the preceding subjects, wherein the backup source includes a transistor having a control terminal connected to the control terminal of the current mirror transistor of the current source.

[0405] 58. A supply circuit according to any one of the preceding subjects, wherein the switching device has one or more transmission gates.

[0406] 59. A supply circuit according to any one of the preceding subjects, comprising a reference current mirror configured to supply a current defined on the input side to the error correction detector and the current source on the output side.

[0407] 60. A method for supplying power to an LED, - A step to detect the supply current flowing to the above LED, - A step of comparing the above supply current with a reference signal and deriving a corrected signal from the comparison result, - A step of changing the supply current in response to the above correction signal to adjust the supply current to a target value, - A step of turning off the supply current flowing to the above LED and simultaneously supplying a backup signal for the comparison step. Methods that include...

[0408] 61. The method according to Subject 60, wherein the backup signal substantially corresponds to a signal derived from the supply current or supply signal flowing to the LED.

[0409] 62. Use of a power supply circuit according to any one of the preceding subjects for supplying power to an LED or LED arrangement structure, in particular an LED or LED arrangement structure according to any one of the preceding subjects, which is operated by a signal that pulses width modulated to a current supply unit.

[0410] 63. A control circuit for a display matrix including a plurality of light-emitting devices arranged in rows and columns, - Row select input for row select signal and column data input for data signal, - A ramp signal input for a ramp signal and a trigger input for a trigger signal, having a level between a first value and a second value. - A column data buffer configured to buffer data signals in response to the row select signal mentioned above, - A pulse generator coupled to the above column data buffer and the above ramp signal input, configured to supply a buffered output signal to control the on / off ratio of at least one of the plurality of light-emitting devices in response to the above trigger signal, the above data signal and the above ramp signal, and A control circuit, including one.

[0411] 64. The above pulse generator, - A comparator device that compares the buffered data signal with the ramp signal. - Output buffer coupled to the output of the above comparator device and the above trigger input and A control circuit as described in Subject 63, which includes the control circuit described in Subject 63.

[0412] 65. The control circuit according to Subject 64, wherein the output buffer includes a flip-flop, in particular an RS flip-flop having inputs coupled to the output of the comparator device and the trigger input, respectively.

[0413] 66. The control circuit according to any one of Subjects 63 to 65, wherein the column data buffer includes a capacitor for storing the data signal and a switch positioned between the capacitor and the column data input.

[0414] 67. A control circuit according to any one of Subjects 63 to 66, wherein the comparator device includes a power control input coupled to the trigger input for adjusting its power consumption based on the trigger signal.

[0415] 68. A control circuit according to any one of Subjects 63 to 67, wherein the comparator device is coupled to the output buffer to control its power consumption based on the output state of the output buffer.

[0416] 69. The control circuit according to any one of Subjects 63 to 68, wherein the comparator has its inverting input coupled to the data column buffer and its non-inverting input coupled to the ramp signal input.

[0417] 70. Furthermore, - Lamp generator that supplies the above lamp signal to the above lamp signal input A control circuit according to any one of Subjects 63 to 68, comprising the lamp generator configured to generate a signal that fluctuates between a start value and an end value in response to the trigger signal.

[0418] 71. A method for controlling the illumination level of a light-emitting device in a matrix display unit having multiple light-emitting devices arranged in addressable rows and columns, - A step of supplying data signals to the selected column and at least one light-emitting device, - Steps include supplying a trigger signal and - A step of converting the level of the above data signal into a pulse with reference to the trigger signal, - A step of controlling the on / off ratio of the above light-emitting device with pulses. Methods that include...

[0419] 72. The step of converting the level of the above data signal is: - A step of generating a ramp signal between a first value and a second value, - A step of comparing the above data signal with the above ramp signal to generate a comparison signal, - A step of generating a pulse based on the changes in the trigger signal and the comparison signal. The method described in Subject 71, including the method described in Subject 71.

[0420] 73. The method according to Subject 71, wherein the step of generating the pulses includes the steps of setting the level of the output signal to a first value in response to a trigger signal and resetting the level of the output signal to a second value in response to a change in the comparison signal.

[0421] 74. The method according to Subject 72 or 73 for generating the ramp signal in response to the trigger signal.

[0422] 75. The method according to any one of Subjects 71 to 74, wherein the step of supplying the data signal includes pre-buffering the data signal, in particular pre-buffering the data signal to a memory device.

[0423] 76. A device for electronically driving and controlling multiple LEDs, - The device has a first branch and at least one second branch to which an LED is internally connected, and an electronic fuse arranged in series with the LED, wherein one side of the first branch and at least one second branch is connected to a potential terminal. - A driver circuit having a data signal input, a select signal input, and a drive output is connected to the other side of the first branch and at least one second branch described above. - A device having an embossed structural element that is assigned to at least one second branch above and configured to generate a current flow that triggers the electronic fuses arranged in series above.

[0424] 77. The device according to any one of the preceding subjects, characterized in that the embossed structure element has an embossed transistor, the current line contacts thereof are electrically connected in parallel to the LED to which the embossed transistor is assigned, and the control contacts thereof are connected to an embossed signal line.

[0425] 78. The device according to any one of the preceding subjects, characterized in that the embossed structural element has an embossed diode, one terminal of which is connected to the second terminal of the LED to which the embossed diode is assigned, and the other terminal of which is connected to the embossed signal line.

[0426] 79. The first terminal of the above LED is connected to the reference potential terminal. A first transistor having a current line contact is placed between the common terminal and the supply potential terminal of the fuse of the above LED. The device according to any one of the preceding subjects, characterized in that the charge storage means is electrically connected to the control contact of the first transistor and the first current line contact of the first transistor.

[0427] 80. The second terminal of the above LED is connected to the supply potential terminal. The first current line contact of the first transistor is connected to the reference potential terminal, and the second current line contact of the first transistor is connected to the common terminal and the supply potential terminal of the electric fuse. The device according to any one of the preceding subjects, characterized in that the charge storage means is connected to the control contact of the first transistor and the first current line contact of the first transistor.

[0428] 81. The second terminal of the above LED is connected to the fuse assigned to the above LED, The first current line contact of the first transistor is connected to the reference potential terminal, and the second current line contact of the first transistor is connected to the first terminal of the LED. The device according to any one of the preceding subjects, characterized in that the charge storage means is connected to the control contact of the first transistor and the first current line contact of the first transistor.

[0429] 82. The first terminal of the above LED is connected to the reference potential terminal. A first transistor having a current line contact is placed between the common terminal and the supply potential terminal of the fuse of the above LED. The device according to any one of the preceding subjects, characterized in that the charge storage means is electrically connected to the control contact of the first transistor and the second current line contact of the first transistor.

[0430] 83. The first terminal of the above LED is connected to the reference potential terminal. A first transistor having a current line contact is placed between the common terminal and the supply potential terminal of the fuse of the above LED. The device according to any one of the above-mentioned subject, characterized in that the charge storage means is electrically connected to the control contact of the first transistor and the second current line contact of the first transistor, the first terminal of the embossed diode is connected to the second terminal of the LED, and the second terminal of the embossed diode is connected to the embossed signal line.

[0431] 84. The first terminal of the above LED is connected to the reference potential terminal. A first transistor having a current line contact is placed between the common terminal and the supply potential terminal of the fuse of the above LED. The device according to any one of the above-mentioned subjects, characterized in that the charge storage means is electrically connected to the control contact of the first transistor and the second current line contact of the first transistor, the second terminal of the embossed diode is connected to the second terminal of the LED, and the first terminal of the embossed diode is connected to the embossed signal line.

[0432] 85. The device according to any one of the preceding subjects, wherein the driver circuit comprises a first transistor, a second transistor, and a charge storage means, the select signal line contacts the control contact of the second transistor, the data signal input contacts the current line contact of the second transistor, and the first or second current line contact of the first transistor provides a drive output connected for supplying current to the LEDs of the first branch and the second branch.

[0433] 86. A display or display module comprising any of the devices described in any one of the preceding subjects, The pixel cells of the above display are electrically connected to a common embossed signal line along the row and / or column. A display or display module in which each pixel cell in a row is electrically connected at a supply potential terminal to a switching transistor located on a common carrier outside the display via a common supply lead.

[0434] 87. A method for electronically configuring multiple LEDs as described in any one of the preceding subjects, comprising the following steps: - A step to test the function of the LEDs in the first branch and the second branch described above, - If the LEDs on the first branch and the second branch described above are not defective, - The step of applying an embossing signal to the above-mentioned electronic embossing structural element, - The step of applying a current flow to the second branch that triggers a fuse connected in series with the LED of the second branch. Methods that include...

[0435] 88. A display arrangement structure comprising a display having multiple pixels arranged in rows and columns, - A first substrate structure wherein LEDs forming a pixel structure arranged in rows and columns are arranged in or on the first substrate structure, the LEDs are individually controllable, and a plurality of contacts are arranged on the surface of the first substrate structure facing the direction of light irradiation, - A second substrate structure having a plurality of contacts on its surface corresponding to the contacts of the first substrate structure, and having a plurality of digital circuits for addressing the optoelectronic structural elements, The first substrate structure and the second substrate structure are connected to each other, and multiple contacts are electrically joined to the corresponding contacts. A display arrangement structure in which the first substrate structure is formed of a first material system, and the second substrate structure is formed of a second material system different from the first material system.

[0436] 89. The arrangement structure according to Subject 88, wherein the first material system comprises at least one of the following compounds: GaN, GaP, GaInP, InAlP, GaAlP or GaAlInP, GaAs, and AlGaAs, and the second material system comprises at least one of the following materials: single crystal, polycrystalline, amorphous silicon, indium gallium zinc oxide, GaN, or GaAs.

[0437] 90. The arrangement described in any one of the preceding subjects, wherein the first carrier structure includes a plurality of switchable current sources, each current source connected to a pixel to supply current to the pixel, and its switching input is coupled to a contact for supplying a switching signal from a digital circuit.

[0438] 91. The display arrangement structure according to Subject 90, wherein the above-mentioned switchable current source is located in a material system different from the material system used for the LED or the first material system.

[0439] 92. The arrangement of any one of the above-mentioned subjects, wherein the multiple digital circuits of the second substrate structure described above are configured to generate a PWM-like signal from the clock signal and data word of each pixel.

[0440] 93. The arrangement structure according to Subject 92, wherein the above-mentioned multiple digital circuits include a number of shift registers connected in series, each shift register having a length corresponding to the above-mentioned data word of the pixel, and each shift register is connected to a buffer for temporary storage.

[0441] 94. The arrangement according to any one of the preceding subjects, wherein the plurality of digital circuits include a multiplexer electrically coupled to the demultiplexer of the first substrate structure for driving and controlling the plurality of optoelectronic structural elements.

Claims

[Claim 1] It is a configuration structure, In particular, a device for electronically driving and controlling LED pixel cells created using NMOS technology, - Data signal lines, threshold lines and select signal lines, - An LED, which is electrically connected in series with a dual-gate transistor and connected together with the dual-gate transistor between a first potential terminal and a second potential terminal, - Here, the dual-gate transistor is positioned between the terminal and potential terminal of the LED by its current line contact, and the first control gate of the dual-gate transistor is connected to the threshold line. - A select-hold circuit having a second control gate of the dual-gate transistor, a charge storage unit coupled to the current line contact of the dual-gate transistor, and a control transistor having a control terminal connected to the select signal line. A device having and / or A driver circuit for driving multiple optoelectronic elements, Multiple first memory cells, each having a set input, a reset input, and an output. Includes, Each first memory cell is triggered to a first state at the output by the set signal of the set input, and maintains the first state until it is reset to a second state by the reset input. The output of each first memory cell is configured to control one of the photoelectronic elements. Driver circuit and / or A supply circuit, - An error correction detector having a reference signal input, an error signal input, and a correction signal output, - A controllable current source having a current output and a control signal terminal, wherein the control signal terminal is connected to the modification signal output to form a control loop for the controllable current source, and the current source is configured to supply current to the current output in response to a signal from the control signal terminal, - A backup source having an output, configured to supply a backup signal, - A switching device configured to supply either a signal derived from the current of the current output or the backup signal to the error signal input, in a state where the current output of the current source is additionally isolated in accordance with the switching signal. A supply circuit having and / or A control circuit for a display matrix including multiple light-emitting devices arranged in rows and columns, - Row select input for row select signal and column data input for data signal, - A ramp signal input for a ramp signal having a trigger input for a level between a first value and a second value and a trigger signal, - A column data buffer configured to buffer the data signal in response to the row select signal, - A pulse generator coupled to the column data buffer and the ramp signal input, configured to supply a buffered output signal to control the on / off ratio of at least one of the plurality of light-emitting devices in response to the trigger signal, the data signal and the ramp signal, and control circuits and / or A display arrangement structure comprising a display having multiple pixels arranged in rows and columns, - A first substrate structure wherein LEDs forming a pixel structure arranged in rows and columns are arranged in or on the first substrate structure, the LEDs are individually drive-controllable, and a plurality of contacts are arranged on the surface of the first substrate structure facing the direction of light irradiation, - A second substrate structure having a plurality of contacts on its surface corresponding to the contacts of the first substrate structure, and a plurality of digital circuits for addressing photoelectronic structural elements. It has, The first substrate structure and the second substrate structure are connected to each other, and the plurality of contacts are electrically joined to the corresponding contacts. The first substrate structure is formed from a first material system, and the second substrate structure is formed from a second material system different from the first material system. Display arrangement structure and / or A control circuit for adjusting the brightness of at least one LED, - A control terminal whose first terminal is connected to the first potential and - A charge storage unit connected between the control terminal and the first potential, which forms a capacitive voltage divider with a capacitance defined between the control terminal and the first potential, - A control element configured to apply a control signal to the control terminal during a first period, wherein the current flowing through the at least one LED can be adjusted during the first period based on the control signal. Includes a current driver element equipped with, During the second period following the first period, the current flowing through the LED is determined by a reduced control signal formed by the control signal during the first period and the control signal of the capacitance divider. The control element is configured to supply a first control signal or a second control signal during the first period to operate the LED at at least two different brightness levels. Control circuit A configuration structure that includes the following features.

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